msm_vidc_debug.h 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2020-2021,, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef __MSM_VIDC_DEBUG__
  7. #define __MSM_VIDC_DEBUG__
  8. #include <linux/types.h>
  9. #include <linux/errno.h>
  10. #include <linux/debugfs.h>
  11. #include <linux/delay.h>
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. struct msm_vidc_core;
  15. struct msm_vidc_inst;
  16. #ifndef VIDC_DBG_LABEL
  17. #define VIDC_DBG_LABEL "msm_vidc"
  18. #endif
  19. /* Allow only 6 prints/sec */
  20. #define VIDC_DBG_SESSION_RATELIMIT_INTERVAL (1 * HZ)
  21. #define VIDC_DBG_SESSION_RATELIMIT_BURST 6
  22. #define VIDC_DBG_TAG_INST VIDC_DBG_LABEL ": %4s: %s: "
  23. #define VIDC_DBG_TAG_CORE VIDC_DBG_LABEL ": %4s: %08x: %s: "
  24. #define FW_DBG_TAG VIDC_DBG_LABEL ": %6s: "
  25. #define DEFAULT_SID ((u32)-1)
  26. #ifndef MSM_VIDC_EMPTY_BRACE
  27. #define MSM_VIDC_EMPTY_BRACE {},
  28. #endif
  29. extern unsigned int msm_vidc_debug;
  30. extern bool msm_vidc_lossless_encode;
  31. extern bool msm_vidc_syscache_disable;
  32. extern int msm_vidc_clock_voting;
  33. extern int msm_vidc_ddr_bw;
  34. extern int msm_vidc_llc_bw;
  35. extern bool msm_vidc_fw_dump;
  36. extern unsigned int msm_vidc_enable_bugon;
  37. extern bool msm_vidc_synx_fence_enable;
  38. /* do not modify the log message as it is used in test scripts */
  39. #define FMT_STRING_SET_CTRL \
  40. "%s: state %s, name %s, id 0x%x value %d\n"
  41. #define FMT_STRING_STATE_CHANGE \
  42. "%s: state changed to %s from %s\n"
  43. #define FMT_STRING_MSG_SFR \
  44. "SFR Message from FW: %s\n"
  45. #define FMT_STRING_FAULT_HANDLER \
  46. "%s: faulting address: %lx\n"
  47. #define FMT_STRING_SET_CAP \
  48. "set cap: name: %24s, cap value: %#10x, hfi: %#10llx\n"
  49. /* To enable messages OR these values and
  50. * echo the result to debugfs file.
  51. *
  52. * To enable all messages set msm_vidc_debug = 0x101F
  53. */
  54. enum vidc_msg_prio {
  55. VIDC_ERR = 0x00000001,
  56. VIDC_HIGH = 0x00000002,
  57. VIDC_LOW = 0x00000004,
  58. VIDC_PERF = 0x00000008,
  59. VIDC_PKT = 0x00000010,
  60. VIDC_BUS = 0x00000020,
  61. VIDC_STAT = 0x00000040,
  62. VIDC_ENCODER = 0x00000100,
  63. VIDC_DECODER = 0x00000200,
  64. VIDC_PRINTK = 0x00001000,
  65. VIDC_FTRACE = 0x00002000,
  66. FW_LOW = 0x00010000,
  67. FW_MED = 0x00020000,
  68. FW_HIGH = 0x00040000,
  69. FW_ERROR = 0x00080000,
  70. FW_FATAL = 0x00100000,
  71. FW_PERF = 0x00200000,
  72. FW_PRINTK = 0x10000000,
  73. FW_FTRACE = 0x20000000,
  74. };
  75. #define DRV_LOG (VIDC_ERR | VIDC_PRINTK)
  76. #define DRV_LOGSHIFT (0)
  77. #define DRV_LOGMASK (0x0FFF)
  78. #define FW_LOG (FW_ERROR | FW_FATAL | FW_PRINTK)
  79. #define FW_LOGSHIFT (16)
  80. #define FW_LOGMASK (0x0FFF0000)
  81. #define dprintk_inst(__level, __level_str, inst, __fmt, ...) \
  82. do { \
  83. if (inst && (msm_vidc_debug & (__level))) { \
  84. pr_info(VIDC_DBG_TAG_INST __fmt, \
  85. __level_str, \
  86. inst->debug_str, \
  87. ##__VA_ARGS__); \
  88. } \
  89. } while (0)
  90. #define i_vpr_e(inst, __fmt, ...) dprintk_inst(VIDC_ERR, "err ", inst, __fmt, ##__VA_ARGS__)
  91. #define i_vpr_i(inst, __fmt, ...) dprintk_inst(VIDC_HIGH, "high", inst, __fmt, ##__VA_ARGS__)
  92. #define i_vpr_h(inst, __fmt, ...) dprintk_inst(VIDC_HIGH, "high", inst, __fmt, ##__VA_ARGS__)
  93. #define i_vpr_l(inst, __fmt, ...) dprintk_inst(VIDC_LOW, "low ", inst, __fmt, ##__VA_ARGS__)
  94. #define i_vpr_p(inst, __fmt, ...) dprintk_inst(VIDC_PERF, "perf", inst, __fmt, ##__VA_ARGS__)
  95. #define i_vpr_t(inst, __fmt, ...) dprintk_inst(VIDC_PKT, "pkt ", inst, __fmt, ##__VA_ARGS__)
  96. #define i_vpr_b(inst, __fmt, ...) dprintk_inst(VIDC_BUS, "bus ", inst, __fmt, ##__VA_ARGS__)
  97. #define i_vpr_s(inst, __fmt, ...) dprintk_inst(VIDC_STAT, "stat", inst, __fmt, ##__VA_ARGS__)
  98. #define i_vpr_hp(inst, __fmt, ...) \
  99. dprintk_inst(VIDC_HIGH | VIDC_PERF, "high", inst, __fmt, ##__VA_ARGS__)
  100. #define i_vpr_hs(inst, __fmt, ...) \
  101. dprintk_inst(VIDC_HIGH | VIDC_STAT, "stat", inst, __fmt, ##__VA_ARGS__)
  102. #define dprintk_core(__level, __level_str, __fmt, ...) \
  103. do { \
  104. if (msm_vidc_debug & (__level)) { \
  105. pr_info(VIDC_DBG_TAG_CORE __fmt, \
  106. __level_str, \
  107. DEFAULT_SID, \
  108. "codec", \
  109. ##__VA_ARGS__); \
  110. } \
  111. } while (0)
  112. #define d_vpr_e(__fmt, ...) dprintk_core(VIDC_ERR, "err ", __fmt, ##__VA_ARGS__)
  113. #define d_vpr_h(__fmt, ...) dprintk_core(VIDC_HIGH, "high", __fmt, ##__VA_ARGS__)
  114. #define d_vpr_l(__fmt, ...) dprintk_core(VIDC_LOW, "low ", __fmt, ##__VA_ARGS__)
  115. #define d_vpr_p(__fmt, ...) dprintk_core(VIDC_PERF, "perf", __fmt, ##__VA_ARGS__)
  116. #define d_vpr_t(__fmt, ...) dprintk_core(VIDC_PKT, "pkt ", __fmt, ##__VA_ARGS__)
  117. #define d_vpr_b(__fmt, ...) dprintk_core(VIDC_BUS, "bus ", __fmt, ##__VA_ARGS__)
  118. #define d_vpr_s(__fmt, ...) dprintk_core(VIDC_STAT, "stat", __fmt, ##__VA_ARGS__)
  119. #define d_vpr_hs(__fmt, ...) \
  120. dprintk_core(VIDC_HIGH | VIDC_STAT, "high", __fmt, ##__VA_ARGS__)
  121. #define dprintk_ratelimit(__level, __level_str, __fmt, ...) \
  122. do { \
  123. if (msm_vidc_check_ratelimit()) { \
  124. dprintk_core(__level, __level_str, __fmt, ##__VA_ARGS__); \
  125. } \
  126. } while (0)
  127. #define dprintk_firmware(__level, __fmt, ...) \
  128. do { \
  129. if (__level & FW_PRINTK) { \
  130. pr_info(FW_DBG_TAG __fmt, \
  131. "fw", \
  132. ##__VA_ARGS__); \
  133. } \
  134. } while (0)
  135. #define MSM_VIDC_FATAL(value) \
  136. do { \
  137. if (value) { \
  138. d_vpr_e("bug on\n"); \
  139. BUG_ON(value); \
  140. } \
  141. } while (0)
  142. enum msm_vidc_debugfs_event {
  143. MSM_VIDC_DEBUGFS_EVENT_ETB,
  144. MSM_VIDC_DEBUGFS_EVENT_EBD,
  145. MSM_VIDC_DEBUGFS_EVENT_FTB,
  146. MSM_VIDC_DEBUGFS_EVENT_FBD,
  147. };
  148. enum msm_vidc_bug_on_error {
  149. MSM_VIDC_BUG_ON_FATAL = BIT(0),
  150. MSM_VIDC_BUG_ON_NOC = BIT(1),
  151. MSM_VIDC_BUG_ON_WD_TIMEOUT = BIT(2),
  152. };
  153. struct dentry *msm_vidc_debugfs_init_drv(void);
  154. struct dentry *msm_vidc_debugfs_init_core(struct msm_vidc_core *core);
  155. struct dentry *msm_vidc_debugfs_init_inst(struct msm_vidc_inst *inst,
  156. struct dentry *parent);
  157. void msm_vidc_debugfs_deinit_inst(struct msm_vidc_inst *inst);
  158. void msm_vidc_debugfs_update(struct msm_vidc_inst *inst,
  159. enum msm_vidc_debugfs_event e);
  160. int msm_vidc_check_ratelimit(void);
  161. void msm_vidc_show_stats(struct msm_vidc_inst *inst);
  162. static inline bool is_stats_enabled(void)
  163. {
  164. return !!(msm_vidc_debug & VIDC_STAT);
  165. }
  166. #endif