hal_5018.c 72 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "hal_li_hw_headers.h"
  20. #include "hal_internal.h"
  21. #include "hal_api.h"
  22. #include "target_type.h"
  23. #include "wcss_version.h"
  24. #include "qdf_module.h"
  25. #include "hal_flow.h"
  26. #include "rx_flow_search_entry.h"
  27. #include "hal_rx_flow_info.h"
  28. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
  29. RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
  30. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
  31. RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK
  32. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
  33. RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB
  34. #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \
  35. RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET
  36. #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \
  37. RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK
  38. #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \
  39. RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB
  40. #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
  41. PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET
  42. #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
  43. PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
  44. #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
  45. PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
  46. #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
  47. PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
  48. #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
  49. PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
  50. #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
  51. PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
  52. #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
  53. PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
  54. #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
  55. PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
  56. #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
  57. PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
  58. #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
  59. PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
  60. #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
  61. PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
  62. #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
  63. RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
  64. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  65. RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  66. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  67. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  68. #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  69. RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  70. #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  71. REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  72. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
  73. STATUS_HEADER_REO_STATUS_NUMBER
  74. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
  75. STATUS_HEADER_TIMESTAMP
  76. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  77. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  78. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  79. RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  80. #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  81. TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
  82. #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  83. TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
  84. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
  85. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
  86. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
  87. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
  88. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
  89. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
  90. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
  91. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
  92. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
  93. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
  94. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
  95. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
  96. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
  97. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
  98. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
  99. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
  100. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
  101. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
  102. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
  103. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
  104. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
  105. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
  106. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
  107. WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
  108. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
  109. WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
  110. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
  111. WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
  112. #define CE_WINDOW_ADDRESS_5018 \
  113. ((WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
  114. #define UMAC_WINDOW_ADDRESS_5018 \
  115. ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
  116. #define WINDOW_CONFIGURATION_VALUE_5018 \
  117. ((CE_WINDOW_ADDRESS_5018 << 6) |\
  118. (UMAC_WINDOW_ADDRESS_5018 << 12) | \
  119. WINDOW_ENABLE_BIT)
  120. #define HOST_CE_MASK_VALUE 0xFF000000
  121. #include "hal_5018_tx.h"
  122. #include "hal_5018_rx.h"
  123. #include <hal_generic_api.h>
  124. #include "hal_li_rx.h"
  125. #include "hal_li_api.h"
  126. #include "hal_li_generic_api.h"
  127. /**
  128. * hal_rx_msdu_start_nss_get_5018(): API to get the NSS
  129. * Interval from rx_msdu_start
  130. *
  131. * @buf: pointer to the start of RX PKT TLV header
  132. * Return: uint32_t(nss)
  133. */
  134. static uint32_t hal_rx_msdu_start_nss_get_5018(uint8_t *buf)
  135. {
  136. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  137. struct rx_msdu_start *msdu_start =
  138. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  139. uint8_t mimo_ss_bitmap;
  140. mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
  141. return qdf_get_hweight8(mimo_ss_bitmap);
  142. }
  143. /**
  144. * hal_rx_mon_hw_desc_get_mpdu_status_5018(): Retrieve MPDU status
  145. *
  146. * @ hw_desc_addr: Start address of Rx HW TLVs
  147. * @ rs: Status for monitor mode
  148. *
  149. * Return: void
  150. */
  151. static void hal_rx_mon_hw_desc_get_mpdu_status_5018(void *hw_desc_addr,
  152. struct mon_rx_status *rs)
  153. {
  154. struct rx_msdu_start *rx_msdu_start;
  155. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  156. uint32_t reg_value;
  157. const uint32_t sgi_hw_to_cdp[] = {
  158. CDP_SGI_0_8_US,
  159. CDP_SGI_0_4_US,
  160. CDP_SGI_1_6_US,
  161. CDP_SGI_3_2_US,
  162. };
  163. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  164. HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
  165. rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
  166. RX_MSDU_START_5, USER_RSSI);
  167. rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
  168. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
  169. rs->sgi = sgi_hw_to_cdp[reg_value];
  170. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
  171. rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
  172. /* TODO: rs->beamformed should be set for SU beamforming also */
  173. }
  174. #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
  175. /**
  176. * hal_get_link_desc_size_5018(): API to get the link desc size
  177. *
  178. * Return: uint32_t
  179. */
  180. static uint32_t hal_get_link_desc_size_5018(void)
  181. {
  182. return LINK_DESC_SIZE;
  183. }
  184. /**
  185. * hal_rx_get_tlv_5018(): API to get the tlv
  186. *
  187. * @rx_tlv: TLV data extracted from the rx packet
  188. * Return: uint8_t
  189. */
  190. static uint8_t hal_rx_get_tlv_5018(void *rx_tlv)
  191. {
  192. return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
  193. }
  194. /**
  195. * hal_rx_mpdu_start_tlv_tag_valid_5018 () - API to check if RX_MPDU_START
  196. * tlv tag is valid
  197. *
  198. *@rx_tlv_hdr: start address of rx_pkt_tlvs
  199. *
  200. * Return: true if RX_MPDU_START is valied, else false.
  201. */
  202. uint8_t hal_rx_mpdu_start_tlv_tag_valid_5018(void *rx_tlv_hdr)
  203. {
  204. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
  205. uint32_t tlv_tag;
  206. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv);
  207. return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
  208. }
  209. /**
  210. * hal_rx_wbm_err_msdu_continuation_get_5018 () - API to check if WBM
  211. * msdu continuation bit is set
  212. *
  213. *@wbm_desc: wbm release ring descriptor
  214. *
  215. * Return: true if msdu continuation bit is set.
  216. */
  217. uint8_t hal_rx_wbm_err_msdu_continuation_get_5018(void *wbm_desc)
  218. {
  219. uint32_t comp_desc =
  220. *(uint32_t *)(((uint8_t *)wbm_desc) +
  221. WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET);
  222. return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >>
  223. WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB;
  224. }
  225. static
  226. void hal_compute_reo_remap_ix2_ix3_5018(uint32_t *ring, uint32_t num_rings,
  227. uint32_t *remap1, uint32_t *remap2)
  228. {
  229. switch (num_rings) {
  230. case 1:
  231. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  232. HAL_REO_REMAP_IX2(ring[0], 17) |
  233. HAL_REO_REMAP_IX2(ring[0], 18) |
  234. HAL_REO_REMAP_IX2(ring[0], 19) |
  235. HAL_REO_REMAP_IX2(ring[0], 20) |
  236. HAL_REO_REMAP_IX2(ring[0], 21) |
  237. HAL_REO_REMAP_IX2(ring[0], 22) |
  238. HAL_REO_REMAP_IX2(ring[0], 23);
  239. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  240. HAL_REO_REMAP_IX3(ring[0], 25) |
  241. HAL_REO_REMAP_IX3(ring[0], 26) |
  242. HAL_REO_REMAP_IX3(ring[0], 27) |
  243. HAL_REO_REMAP_IX3(ring[0], 28) |
  244. HAL_REO_REMAP_IX3(ring[0], 29) |
  245. HAL_REO_REMAP_IX3(ring[0], 30) |
  246. HAL_REO_REMAP_IX3(ring[0], 31);
  247. break;
  248. case 2:
  249. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  250. HAL_REO_REMAP_IX2(ring[0], 17) |
  251. HAL_REO_REMAP_IX2(ring[1], 18) |
  252. HAL_REO_REMAP_IX2(ring[1], 19) |
  253. HAL_REO_REMAP_IX2(ring[0], 20) |
  254. HAL_REO_REMAP_IX2(ring[0], 21) |
  255. HAL_REO_REMAP_IX2(ring[1], 22) |
  256. HAL_REO_REMAP_IX2(ring[1], 23);
  257. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  258. HAL_REO_REMAP_IX3(ring[0], 25) |
  259. HAL_REO_REMAP_IX3(ring[1], 26) |
  260. HAL_REO_REMAP_IX3(ring[1], 27) |
  261. HAL_REO_REMAP_IX3(ring[0], 28) |
  262. HAL_REO_REMAP_IX3(ring[0], 29) |
  263. HAL_REO_REMAP_IX3(ring[1], 30) |
  264. HAL_REO_REMAP_IX3(ring[1], 31);
  265. break;
  266. case 3:
  267. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  268. HAL_REO_REMAP_IX2(ring[1], 17) |
  269. HAL_REO_REMAP_IX2(ring[2], 18) |
  270. HAL_REO_REMAP_IX2(ring[0], 19) |
  271. HAL_REO_REMAP_IX2(ring[1], 20) |
  272. HAL_REO_REMAP_IX2(ring[2], 21) |
  273. HAL_REO_REMAP_IX2(ring[0], 22) |
  274. HAL_REO_REMAP_IX2(ring[1], 23);
  275. *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
  276. HAL_REO_REMAP_IX3(ring[0], 25) |
  277. HAL_REO_REMAP_IX3(ring[1], 26) |
  278. HAL_REO_REMAP_IX3(ring[2], 27) |
  279. HAL_REO_REMAP_IX3(ring[0], 28) |
  280. HAL_REO_REMAP_IX3(ring[1], 29) |
  281. HAL_REO_REMAP_IX3(ring[2], 30) |
  282. HAL_REO_REMAP_IX3(ring[0], 31);
  283. break;
  284. case 4:
  285. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  286. HAL_REO_REMAP_IX2(ring[1], 17) |
  287. HAL_REO_REMAP_IX2(ring[2], 18) |
  288. HAL_REO_REMAP_IX2(ring[3], 19) |
  289. HAL_REO_REMAP_IX2(ring[0], 20) |
  290. HAL_REO_REMAP_IX2(ring[1], 21) |
  291. HAL_REO_REMAP_IX2(ring[2], 22) |
  292. HAL_REO_REMAP_IX2(ring[3], 23);
  293. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  294. HAL_REO_REMAP_IX3(ring[1], 25) |
  295. HAL_REO_REMAP_IX3(ring[2], 26) |
  296. HAL_REO_REMAP_IX3(ring[3], 27) |
  297. HAL_REO_REMAP_IX3(ring[0], 28) |
  298. HAL_REO_REMAP_IX3(ring[1], 29) |
  299. HAL_REO_REMAP_IX3(ring[2], 30) |
  300. HAL_REO_REMAP_IX3(ring[3], 31);
  301. break;
  302. }
  303. }
  304. /**
  305. * hal_rx_proc_phyrx_other_receive_info_tlv_5018(): API to get tlv info
  306. *
  307. * Return: uint32_t
  308. */
  309. static inline
  310. void hal_rx_proc_phyrx_other_receive_info_tlv_5018(void *rx_tlv_hdr,
  311. void *ppdu_info_hdl)
  312. {
  313. }
  314. #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
  315. static inline
  316. void hal_rx_get_bb_info_5018(void *rx_tlv,
  317. void *ppdu_info_hdl)
  318. {
  319. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  320. ppdu_info->cfr_info.bb_captured_channel =
  321. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL);
  322. ppdu_info->cfr_info.bb_captured_timeout =
  323. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT);
  324. ppdu_info->cfr_info.bb_captured_reason =
  325. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON);
  326. }
  327. static inline
  328. void hal_rx_get_rtt_info_5018(void *rx_tlv,
  329. void *ppdu_info_hdl)
  330. {
  331. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  332. ppdu_info->cfr_info.rx_location_info_valid =
  333. HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS,
  334. RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID);
  335. ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
  336. HAL_RX_GET(rx_tlv,
  337. PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
  338. RTT_CHE_BUFFER_POINTER_LOW32);
  339. ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
  340. HAL_RX_GET(rx_tlv,
  341. PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
  342. RTT_CHE_BUFFER_POINTER_HIGH8);
  343. ppdu_info->cfr_info.chan_capture_status =
  344. HAL_RX_GET(rx_tlv,
  345. PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
  346. RESERVED_8);
  347. }
  348. #endif
  349. /**
  350. * hal_rx_dump_msdu_start_tlv_5018() : dump RX msdu_start TLV in structured
  351. * human readable format.
  352. * @ msdu_start: pointer the msdu_start TLV in pkt.
  353. * @ dbg_level: log level.
  354. *
  355. * Return: void
  356. */
  357. static void hal_rx_dump_msdu_start_tlv_5018(void *msdustart,
  358. uint8_t dbg_level)
  359. {
  360. struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart;
  361. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  362. "rx_msdu_start tlv - "
  363. "rxpcu_mpdu_filter_in_category: %d "
  364. "sw_frame_group_id: %d "
  365. "phy_ppdu_id: %d "
  366. "msdu_length: %d "
  367. "ipsec_esp: %d "
  368. "l3_offset: %d "
  369. "ipsec_ah: %d "
  370. "l4_offset: %d "
  371. "msdu_number: %d "
  372. "decap_format: %d "
  373. "ipv4_proto: %d "
  374. "ipv6_proto: %d "
  375. "tcp_proto: %d "
  376. "udp_proto: %d "
  377. "ip_frag: %d "
  378. "tcp_only_ack: %d "
  379. "da_is_bcast_mcast: %d "
  380. "ip4_protocol_ip6_next_header: %d "
  381. "toeplitz_hash_2_or_4: %d "
  382. "flow_id_toeplitz: %d "
  383. "user_rssi: %d "
  384. "pkt_type: %d "
  385. "stbc: %d "
  386. "sgi: %d "
  387. "rate_mcs: %d "
  388. "receive_bandwidth: %d "
  389. "reception_type: %d "
  390. "ppdu_start_timestamp: %d "
  391. "sw_phy_meta_data: %d ",
  392. msdu_start->rxpcu_mpdu_filter_in_category,
  393. msdu_start->sw_frame_group_id,
  394. msdu_start->phy_ppdu_id,
  395. msdu_start->msdu_length,
  396. msdu_start->ipsec_esp,
  397. msdu_start->l3_offset,
  398. msdu_start->ipsec_ah,
  399. msdu_start->l4_offset,
  400. msdu_start->msdu_number,
  401. msdu_start->decap_format,
  402. msdu_start->ipv4_proto,
  403. msdu_start->ipv6_proto,
  404. msdu_start->tcp_proto,
  405. msdu_start->udp_proto,
  406. msdu_start->ip_frag,
  407. msdu_start->tcp_only_ack,
  408. msdu_start->da_is_bcast_mcast,
  409. msdu_start->ip4_protocol_ip6_next_header,
  410. msdu_start->toeplitz_hash_2_or_4,
  411. msdu_start->flow_id_toeplitz,
  412. msdu_start->user_rssi,
  413. msdu_start->pkt_type,
  414. msdu_start->stbc,
  415. msdu_start->sgi,
  416. msdu_start->rate_mcs,
  417. msdu_start->receive_bandwidth,
  418. msdu_start->reception_type,
  419. msdu_start->ppdu_start_timestamp,
  420. msdu_start->sw_phy_meta_data);
  421. }
  422. /**
  423. * hal_rx_dump_msdu_end_tlv_5018: dump RX msdu_end TLV in structured
  424. * human readable format.
  425. * @ msdu_end: pointer the msdu_end TLV in pkt.
  426. * @ dbg_level: log level.
  427. *
  428. * Return: void
  429. */
  430. static void hal_rx_dump_msdu_end_tlv_5018(void *msduend,
  431. uint8_t dbg_level)
  432. {
  433. struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend;
  434. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  435. "rx_msdu_end tlv - "
  436. "rxpcu_mpdu_filter_in_category: %d "
  437. "sw_frame_group_id: %d "
  438. "phy_ppdu_id: %d "
  439. "ip_hdr_chksum: %d "
  440. "reported_mpdu_length: %d "
  441. "key_id_octet: %d "
  442. "cce_super_rule: %d "
  443. "cce_classify_not_done_truncat: %d "
  444. "cce_classify_not_done_cce_dis: %d "
  445. "rule_indication_31_0: %d "
  446. "rule_indication_63_32: %d "
  447. "da_offset: %d "
  448. "sa_offset: %d "
  449. "da_offset_valid: %d "
  450. "sa_offset_valid: %d "
  451. "ipv6_options_crc: %d "
  452. "tcp_seq_number: %d "
  453. "tcp_ack_number: %d "
  454. "tcp_flag: %d "
  455. "lro_eligible: %d "
  456. "window_size: %d "
  457. "tcp_udp_chksum: %d "
  458. "sa_idx_timeout: %d "
  459. "da_idx_timeout: %d "
  460. "msdu_limit_error: %d "
  461. "flow_idx_timeout: %d "
  462. "flow_idx_invalid: %d "
  463. "wifi_parser_error: %d "
  464. "amsdu_parser_error: %d "
  465. "sa_is_valid: %d "
  466. "da_is_valid: %d "
  467. "da_is_mcbc: %d "
  468. "l3_header_padding: %d "
  469. "first_msdu: %d "
  470. "last_msdu: %d "
  471. "sa_idx: %d "
  472. "msdu_drop: %d "
  473. "reo_destination_indication: %d "
  474. "flow_idx: %d "
  475. "fse_metadata: %d "
  476. "cce_metadata: %d "
  477. "sa_sw_peer_id: %d ",
  478. msdu_end->rxpcu_mpdu_filter_in_category,
  479. msdu_end->sw_frame_group_id,
  480. msdu_end->phy_ppdu_id,
  481. msdu_end->ip_hdr_chksum,
  482. msdu_end->reported_mpdu_length,
  483. msdu_end->key_id_octet,
  484. msdu_end->cce_super_rule,
  485. msdu_end->cce_classify_not_done_truncate,
  486. msdu_end->cce_classify_not_done_cce_dis,
  487. msdu_end->rule_indication_31_0,
  488. msdu_end->rule_indication_63_32,
  489. msdu_end->da_offset,
  490. msdu_end->sa_offset,
  491. msdu_end->da_offset_valid,
  492. msdu_end->sa_offset_valid,
  493. msdu_end->ipv6_options_crc,
  494. msdu_end->tcp_seq_number,
  495. msdu_end->tcp_ack_number,
  496. msdu_end->tcp_flag,
  497. msdu_end->lro_eligible,
  498. msdu_end->window_size,
  499. msdu_end->tcp_udp_chksum,
  500. msdu_end->sa_idx_timeout,
  501. msdu_end->da_idx_timeout,
  502. msdu_end->msdu_limit_error,
  503. msdu_end->flow_idx_timeout,
  504. msdu_end->flow_idx_invalid,
  505. msdu_end->wifi_parser_error,
  506. msdu_end->amsdu_parser_error,
  507. msdu_end->sa_is_valid,
  508. msdu_end->da_is_valid,
  509. msdu_end->da_is_mcbc,
  510. msdu_end->l3_header_padding,
  511. msdu_end->first_msdu,
  512. msdu_end->last_msdu,
  513. msdu_end->sa_idx,
  514. msdu_end->msdu_drop,
  515. msdu_end->reo_destination_indication,
  516. msdu_end->flow_idx,
  517. msdu_end->fse_metadata,
  518. msdu_end->cce_metadata,
  519. msdu_end->sa_sw_peer_id);
  520. }
  521. /**
  522. * hal_rx_mpdu_start_tid_get_5018(): API to get tid
  523. * from rx_msdu_start
  524. *
  525. * @buf: pointer to the start of RX PKT TLV header
  526. * Return: uint32_t(tid value)
  527. */
  528. static uint32_t hal_rx_mpdu_start_tid_get_5018(uint8_t *buf)
  529. {
  530. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  531. struct rx_mpdu_start *mpdu_start =
  532. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  533. uint32_t tid;
  534. tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
  535. return tid;
  536. }
  537. /**
  538. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  539. * Interval from rx_msdu_start
  540. *
  541. * @buf: pointer to the start of RX PKT TLV header
  542. * Return: uint32_t(reception_type)
  543. */
  544. static uint32_t hal_rx_msdu_start_reception_type_get_5018(uint8_t *buf)
  545. {
  546. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  547. struct rx_msdu_start *msdu_start =
  548. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  549. uint32_t reception_type;
  550. reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
  551. return reception_type;
  552. }
  553. /**
  554. * hal_rx_msdu_end_da_idx_get_5018: API to get da_idx
  555. * from rx_msdu_end TLV
  556. *
  557. * @ buf: pointer to the start of RX PKT TLV headers
  558. * Return: da index
  559. */
  560. static uint16_t hal_rx_msdu_end_da_idx_get_5018(uint8_t *buf)
  561. {
  562. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  563. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  564. uint16_t da_idx;
  565. da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  566. return da_idx;
  567. }
  568. /**
  569. * hal_rx_get_rx_fragment_number_5018(): Function to retrieve rx fragment number
  570. *
  571. * @nbuf: Network buffer
  572. * Returns: rx fragment number
  573. */
  574. static
  575. uint8_t hal_rx_get_rx_fragment_number_5018(uint8_t *buf)
  576. {
  577. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  578. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  579. /* Return first 4 bits as fragment number */
  580. return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
  581. DOT11_SEQ_FRAG_MASK);
  582. }
  583. /**
  584. * hal_rx_msdu_end_da_is_mcbc_get_5018(): API to check if pkt is MCBC
  585. * from rx_msdu_end TLV
  586. *
  587. * @ buf: pointer to the start of RX PKT TLV headers
  588. * Return: da_is_mcbc
  589. */
  590. static uint8_t
  591. hal_rx_msdu_end_da_is_mcbc_get_5018(uint8_t *buf)
  592. {
  593. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  594. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  595. return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
  596. }
  597. /**
  598. * hal_rx_msdu_end_sa_is_valid_get_5018(): API to get_5018 the
  599. * sa_is_valid bit from rx_msdu_end TLV
  600. *
  601. * @ buf: pointer to the start of RX PKT TLV headers
  602. * Return: sa_is_valid bit
  603. */
  604. static uint8_t
  605. hal_rx_msdu_end_sa_is_valid_get_5018(uint8_t *buf)
  606. {
  607. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  608. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  609. uint8_t sa_is_valid;
  610. sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
  611. return sa_is_valid;
  612. }
  613. /**
  614. * hal_rx_msdu_end_sa_idx_get_5018(): API to get_5018 the
  615. * sa_idx from rx_msdu_end TLV
  616. *
  617. * @ buf: pointer to the start of RX PKT TLV headers
  618. * Return: sa_idx (SA AST index)
  619. */
  620. static uint16_t hal_rx_msdu_end_sa_idx_get_5018(uint8_t *buf)
  621. {
  622. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  623. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  624. uint16_t sa_idx;
  625. sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  626. return sa_idx;
  627. }
  628. /**
  629. * hal_rx_desc_is_first_msdu_5018() - Check if first msdu
  630. *
  631. * @hal_soc_hdl: hal_soc handle
  632. * @hw_desc_addr: hardware descriptor address
  633. *
  634. * Return: 0 - success/ non-zero failure
  635. */
  636. static uint32_t hal_rx_desc_is_first_msdu_5018(void *hw_desc_addr)
  637. {
  638. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  639. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  640. return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU);
  641. }
  642. /**
  643. * hal_rx_msdu_end_l3_hdr_padding_get_5018(): API to get_5018 the
  644. * l3_header padding from rx_msdu_end TLV
  645. *
  646. * @ buf: pointer to the start of RX PKT TLV headers
  647. * Return: number of l3 header padding bytes
  648. */
  649. static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_5018(uint8_t *buf)
  650. {
  651. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  652. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  653. uint32_t l3_header_padding;
  654. l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  655. return l3_header_padding;
  656. }
  657. /**
  658. * @ hal_rx_encryption_info_valid_5018: Returns encryption type.
  659. *
  660. * @ buf: rx_tlv_hdr of the received packet
  661. * @ Return: encryption type
  662. */
  663. inline uint32_t hal_rx_encryption_info_valid_5018(uint8_t *buf)
  664. {
  665. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  666. struct rx_mpdu_start *mpdu_start =
  667. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  668. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  669. uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
  670. return encryption_info;
  671. }
  672. /*
  673. * @ hal_rx_print_pn_5018: Prints the PN of rx packet.
  674. *
  675. * @ buf: rx_tlv_hdr of the received packet
  676. * @ Return: void
  677. */
  678. static void hal_rx_print_pn_5018(uint8_t *buf)
  679. {
  680. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  681. struct rx_mpdu_start *mpdu_start =
  682. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  683. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  684. uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
  685. uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
  686. uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
  687. uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
  688. hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ",
  689. pn_127_96, pn_95_64, pn_63_32, pn_31_0);
  690. }
  691. /**
  692. * hal_rx_msdu_end_first_msdu_get_5018: API to get first msdu status
  693. * from rx_msdu_end TLV
  694. *
  695. * @ buf: pointer to the start of RX PKT TLV headers
  696. * Return: first_msdu
  697. */
  698. static uint8_t hal_rx_msdu_end_first_msdu_get_5018(uint8_t *buf)
  699. {
  700. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  701. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  702. uint8_t first_msdu;
  703. first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
  704. return first_msdu;
  705. }
  706. /**
  707. * hal_rx_msdu_end_da_is_valid_get_5018: API to check if da is valid
  708. * from rx_msdu_end TLV
  709. *
  710. * @ buf: pointer to the start of RX PKT TLV headers
  711. * Return: da_is_valid
  712. */
  713. static uint8_t hal_rx_msdu_end_da_is_valid_get_5018(uint8_t *buf)
  714. {
  715. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  716. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  717. uint8_t da_is_valid;
  718. da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
  719. return da_is_valid;
  720. }
  721. /**
  722. * hal_rx_msdu_end_last_msdu_get_5018: API to get last msdu status
  723. * from rx_msdu_end TLV
  724. *
  725. * @ buf: pointer to the start of RX PKT TLV headers
  726. * Return: last_msdu
  727. */
  728. static uint8_t hal_rx_msdu_end_last_msdu_get_5018(uint8_t *buf)
  729. {
  730. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  731. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  732. uint8_t last_msdu;
  733. last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
  734. return last_msdu;
  735. }
  736. /*
  737. * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid
  738. *
  739. * @nbuf: Network buffer
  740. * Returns: value of mpdu 4th address valid field
  741. */
  742. inline bool hal_rx_get_mpdu_mac_ad4_valid_5018(uint8_t *buf)
  743. {
  744. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  745. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  746. bool ad4_valid = 0;
  747. ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info);
  748. return ad4_valid;
  749. }
  750. /**
  751. * hal_rx_mpdu_start_sw_peer_id_get_5018: Retrieve sw peer_id
  752. * @buf: network buffer
  753. *
  754. * Return: sw peer_id
  755. */
  756. static uint32_t hal_rx_mpdu_start_sw_peer_id_get_5018(uint8_t *buf)
  757. {
  758. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  759. struct rx_mpdu_start *mpdu_start =
  760. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  761. return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
  762. &mpdu_start->rx_mpdu_info_details);
  763. }
  764. /*
  765. * hal_rx_mpdu_get_to_ds_5018(): API to get the tods info
  766. * from rx_mpdu_start
  767. *
  768. * @buf: pointer to the start of RX PKT TLV header
  769. * Return: uint32_t(to_ds)
  770. */
  771. static uint32_t hal_rx_mpdu_get_to_ds_5018(uint8_t *buf)
  772. {
  773. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  774. struct rx_mpdu_start *mpdu_start =
  775. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  776. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  777. return HAL_RX_MPDU_GET_TODS(mpdu_info);
  778. }
  779. /*
  780. * hal_rx_mpdu_get_fr_ds_5018(): API to get the from ds info
  781. * from rx_mpdu_start
  782. *
  783. * @buf: pointer to the start of RX PKT TLV header
  784. * Return: uint32_t(fr_ds)
  785. */
  786. static uint32_t hal_rx_mpdu_get_fr_ds_5018(uint8_t *buf)
  787. {
  788. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  789. struct rx_mpdu_start *mpdu_start =
  790. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  791. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  792. return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
  793. }
  794. /*
  795. * hal_rx_get_mpdu_frame_control_valid_5018(): Retrieves mpdu
  796. * frame control valid
  797. *
  798. * @nbuf: Network buffer
  799. * Returns: value of frame control valid field
  800. */
  801. static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf)
  802. {
  803. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  804. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  805. return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
  806. }
  807. /*
  808. * hal_rx_mpdu_get_addr1_5018(): API to check get address1 of the mpdu
  809. *
  810. * @buf: pointer to the start of RX PKT TLV headera
  811. * @mac_addr: pointer to mac address
  812. * Return: success/failure
  813. */
  814. static QDF_STATUS hal_rx_mpdu_get_addr1_5018(uint8_t *buf,
  815. uint8_t *mac_addr)
  816. {
  817. struct __attribute__((__packed__)) hal_addr1 {
  818. uint32_t ad1_31_0;
  819. uint16_t ad1_47_32;
  820. };
  821. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  822. struct rx_mpdu_start *mpdu_start =
  823. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  824. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  825. struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
  826. uint32_t mac_addr_ad1_valid;
  827. mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
  828. if (mac_addr_ad1_valid) {
  829. addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
  830. addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
  831. return QDF_STATUS_SUCCESS;
  832. }
  833. return QDF_STATUS_E_FAILURE;
  834. }
  835. /*
  836. * hal_rx_mpdu_get_addr2_5018(): API to check get address2 of the mpdu
  837. * in the packet
  838. *
  839. * @buf: pointer to the start of RX PKT TLV header
  840. * @mac_addr: pointer to mac address
  841. * Return: success/failure
  842. */
  843. static QDF_STATUS hal_rx_mpdu_get_addr2_5018(uint8_t *buf, uint8_t *mac_addr)
  844. {
  845. struct __attribute__((__packed__)) hal_addr2 {
  846. uint16_t ad2_15_0;
  847. uint32_t ad2_47_16;
  848. };
  849. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  850. struct rx_mpdu_start *mpdu_start =
  851. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  852. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  853. struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
  854. uint32_t mac_addr_ad2_valid;
  855. mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
  856. if (mac_addr_ad2_valid) {
  857. addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
  858. addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
  859. return QDF_STATUS_SUCCESS;
  860. }
  861. return QDF_STATUS_E_FAILURE;
  862. }
  863. /*
  864. * hal_rx_mpdu_get_addr3_5018(): API to get address3 of the mpdu
  865. * in the packet
  866. *
  867. * @buf: pointer to the start of RX PKT TLV header
  868. * @mac_addr: pointer to mac address
  869. * Return: success/failure
  870. */
  871. static QDF_STATUS hal_rx_mpdu_get_addr3_5018(uint8_t *buf, uint8_t *mac_addr)
  872. {
  873. struct __attribute__((__packed__)) hal_addr3 {
  874. uint32_t ad3_31_0;
  875. uint16_t ad3_47_32;
  876. };
  877. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  878. struct rx_mpdu_start *mpdu_start =
  879. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  880. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  881. struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
  882. uint32_t mac_addr_ad3_valid;
  883. mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
  884. if (mac_addr_ad3_valid) {
  885. addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
  886. addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
  887. return QDF_STATUS_SUCCESS;
  888. }
  889. return QDF_STATUS_E_FAILURE;
  890. }
  891. /*
  892. * hal_rx_mpdu_get_addr4_5018(): API to get address4 of the mpdu
  893. * in the packet
  894. *
  895. * @buf: pointer to the start of RX PKT TLV header
  896. * @mac_addr: pointer to mac address
  897. * Return: success/failure
  898. */
  899. static QDF_STATUS hal_rx_mpdu_get_addr4_5018(uint8_t *buf, uint8_t *mac_addr)
  900. {
  901. struct __attribute__((__packed__)) hal_addr4 {
  902. uint32_t ad4_31_0;
  903. uint16_t ad4_47_32;
  904. };
  905. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  906. struct rx_mpdu_start *mpdu_start =
  907. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  908. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  909. struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
  910. uint32_t mac_addr_ad4_valid;
  911. mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
  912. if (mac_addr_ad4_valid) {
  913. addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
  914. addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
  915. return QDF_STATUS_SUCCESS;
  916. }
  917. return QDF_STATUS_E_FAILURE;
  918. }
  919. /*
  920. * hal_rx_get_mpdu_sequence_control_valid_5018(): Get mpdu
  921. * sequence control valid
  922. *
  923. * @nbuf: Network buffer
  924. * Returns: value of sequence control valid field
  925. */
  926. static uint8_t hal_rx_get_mpdu_sequence_control_valid_5018(uint8_t *buf)
  927. {
  928. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  929. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  930. return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
  931. }
  932. /**
  933. * hal_rx_is_unicast_5018: check packet is unicast frame or not.
  934. *
  935. * @ buf: pointer to rx pkt TLV.
  936. *
  937. * Return: true on unicast.
  938. */
  939. static bool hal_rx_is_unicast_5018(uint8_t *buf)
  940. {
  941. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  942. struct rx_mpdu_start *mpdu_start =
  943. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  944. uint32_t grp_id;
  945. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  946. grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  947. RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)),
  948. RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK,
  949. RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB));
  950. return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
  951. }
  952. /**
  953. * hal_rx_tid_get_5018: get tid based on qos control valid.
  954. * @hal_soc_hdl: hal soc handle
  955. * @buf: pointer to rx pkt TLV.
  956. *
  957. * Return: tid
  958. */
  959. static uint32_t hal_rx_tid_get_5018(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  960. {
  961. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  962. struct rx_mpdu_start *mpdu_start =
  963. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  964. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  965. uint8_t qos_control_valid =
  966. (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  967. RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)),
  968. RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK,
  969. RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB));
  970. if (qos_control_valid)
  971. return hal_rx_mpdu_start_tid_get_5018(buf);
  972. return HAL_RX_NON_QOS_TID;
  973. }
  974. /**
  975. * hal_rx_hw_desc_get_ppduid_get_5018(): retrieve ppdu id
  976. * @rx_tlv_hdr: rx tlv header
  977. * @rxdma_dst_ring_desc: rxdma HW descriptor
  978. *
  979. * Return: ppdu id
  980. */
  981. static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *rx_tlv_hdr,
  982. void *rxdma_dst_ring_desc)
  983. {
  984. struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc;
  985. return HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent);
  986. }
  987. /**
  988. * hal_reo_status_get_header_5018 - Process reo desc info
  989. * @ring_desc: REO status ring descriptor
  990. * @b - tlv type info
  991. * @h1 - Pointer to hal_reo_status_header where info to be stored
  992. *
  993. * Return - none.
  994. *
  995. */
  996. static void hal_reo_status_get_header_5018(hal_ring_desc_t ring_desc, int b,
  997. void *h1)
  998. {
  999. uint32_t *d = (uint32_t *)ring_desc;
  1000. uint32_t val1 = 0;
  1001. struct hal_reo_status_header *h =
  1002. (struct hal_reo_status_header *)h1;
  1003. /* Offsets of descriptor fields defined in HW headers start
  1004. * from the field after TLV header
  1005. */
  1006. d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
  1007. switch (b) {
  1008. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  1009. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
  1010. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1011. break;
  1012. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  1013. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
  1014. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1015. break;
  1016. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  1017. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
  1018. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1019. break;
  1020. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  1021. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
  1022. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1023. break;
  1024. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  1025. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
  1026. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1027. break;
  1028. case HAL_REO_DESC_THRES_STATUS_TLV:
  1029. val1 =
  1030. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
  1031. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1032. break;
  1033. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  1034. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
  1035. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1036. break;
  1037. default:
  1038. qdf_nofl_err("ERROR: Unknown tlv\n");
  1039. break;
  1040. }
  1041. h->cmd_num =
  1042. HAL_GET_FIELD(
  1043. UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
  1044. val1);
  1045. h->exec_time =
  1046. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  1047. CMD_EXECUTION_TIME, val1);
  1048. h->status =
  1049. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  1050. REO_CMD_EXECUTION_STATUS, val1);
  1051. switch (b) {
  1052. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  1053. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
  1054. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1055. break;
  1056. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  1057. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
  1058. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1059. break;
  1060. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  1061. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
  1062. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1063. break;
  1064. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  1065. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
  1066. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1067. break;
  1068. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  1069. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
  1070. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1071. break;
  1072. case HAL_REO_DESC_THRES_STATUS_TLV:
  1073. val1 =
  1074. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
  1075. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1076. break;
  1077. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  1078. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
  1079. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1080. break;
  1081. default:
  1082. qdf_nofl_err("ERROR: Unknown tlv\n");
  1083. break;
  1084. }
  1085. h->tstamp =
  1086. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
  1087. }
  1088. /**
  1089. * hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018():
  1090. * Retrieve qos control valid bit from the tlv.
  1091. * @buf: pointer to rx pkt TLV.
  1092. *
  1093. * Return: qos control value.
  1094. */
  1095. static inline uint32_t
  1096. hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(uint8_t *buf)
  1097. {
  1098. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1099. struct rx_mpdu_start *mpdu_start =
  1100. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1101. return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
  1102. &mpdu_start->rx_mpdu_info_details);
  1103. }
  1104. /**
  1105. * hal_rx_msdu_end_sa_sw_peer_id_get_5018(): API to get the
  1106. * sa_sw_peer_id from rx_msdu_end TLV
  1107. * @buf: pointer to the start of RX PKT TLV headers
  1108. *
  1109. * Return: sa_sw_peer_id index
  1110. */
  1111. static inline uint32_t
  1112. hal_rx_msdu_end_sa_sw_peer_id_get_5018(uint8_t *buf)
  1113. {
  1114. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1115. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1116. return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  1117. }
  1118. /**
  1119. * hal_tx_desc_set_mesh_en_5018 - Set mesh_enable flag in Tx descriptor
  1120. * @desc: Handle to Tx Descriptor
  1121. * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
  1122. * enabling the interpretation of the 'Mesh Control Present' bit
  1123. * (bit 8) of QoS Control (otherwise this bit is ignored),
  1124. * For native WiFi frames, this indicates that a 'Mesh Control' field
  1125. * is present between the header and the LLC.
  1126. *
  1127. * Return: void
  1128. */
  1129. static inline
  1130. void hal_tx_desc_set_mesh_en_5018(void *desc, uint8_t en)
  1131. {
  1132. HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |=
  1133. HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
  1134. }
  1135. static
  1136. void *hal_rx_msdu0_buffer_addr_lsb_5018(void *link_desc_va)
  1137. {
  1138. return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
  1139. }
  1140. static
  1141. void *hal_rx_msdu_desc_info_ptr_get_5018(void *msdu0)
  1142. {
  1143. return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
  1144. }
  1145. static
  1146. void *hal_ent_mpdu_desc_info_5018(void *ent_ring_desc)
  1147. {
  1148. return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
  1149. }
  1150. static
  1151. void *hal_dst_mpdu_desc_info_5018(void *dst_ring_desc)
  1152. {
  1153. return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
  1154. }
  1155. static
  1156. uint8_t hal_rx_get_fc_valid_5018(uint8_t *buf)
  1157. {
  1158. return HAL_RX_GET_FC_VALID(buf);
  1159. }
  1160. static uint8_t hal_rx_get_to_ds_flag_5018(uint8_t *buf)
  1161. {
  1162. return HAL_RX_GET_TO_DS_FLAG(buf);
  1163. }
  1164. static uint8_t hal_rx_get_mac_addr2_valid_5018(uint8_t *buf)
  1165. {
  1166. return HAL_RX_GET_MAC_ADDR2_VALID(buf);
  1167. }
  1168. static uint8_t hal_rx_get_filter_category_5018(uint8_t *buf)
  1169. {
  1170. return HAL_RX_GET_FILTER_CATEGORY(buf);
  1171. }
  1172. static uint32_t
  1173. hal_rx_get_ppdu_id_5018(uint8_t *buf)
  1174. {
  1175. struct rx_mpdu_info *rx_mpdu_info;
  1176. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf;
  1177. rx_mpdu_info =
  1178. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  1179. return HAL_RX_GET_PPDU_ID(rx_mpdu_info);
  1180. }
  1181. /**
  1182. * hal_reo_config_5018(): Set reo config parameters
  1183. * @soc: hal soc handle
  1184. * @reg_val: value to be set
  1185. * @reo_params: reo parameters
  1186. *
  1187. * Return: void
  1188. */
  1189. static void
  1190. hal_reo_config_5018(struct hal_soc *soc,
  1191. uint32_t reg_val,
  1192. struct hal_reo_params *reo_params)
  1193. {
  1194. HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
  1195. }
  1196. /**
  1197. * hal_rx_msdu_desc_info_get_ptr_5018() - Get msdu desc info ptr
  1198. * @msdu_details_ptr - Pointer to msdu_details_ptr
  1199. *
  1200. * Return - Pointer to rx_msdu_desc_info structure.
  1201. *
  1202. */
  1203. static void *hal_rx_msdu_desc_info_get_ptr_5018(void *msdu_details_ptr)
  1204. {
  1205. return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
  1206. }
  1207. /**
  1208. * hal_rx_link_desc_msdu0_ptr_5018 - Get pointer to rx_msdu details
  1209. * @link_desc - Pointer to link desc
  1210. *
  1211. * Return - Pointer to rx_msdu_details structure
  1212. *
  1213. */
  1214. static void *hal_rx_link_desc_msdu0_ptr_5018(void *link_desc)
  1215. {
  1216. return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
  1217. }
  1218. /**
  1219. * hal_rx_msdu_flow_idx_get_5018: API to get flow index
  1220. * from rx_msdu_end TLV
  1221. * @buf: pointer to the start of RX PKT TLV headers
  1222. *
  1223. * Return: flow index value from MSDU END TLV
  1224. */
  1225. static inline uint32_t hal_rx_msdu_flow_idx_get_5018(uint8_t *buf)
  1226. {
  1227. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1228. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1229. return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  1230. }
  1231. /**
  1232. * hal_rx_msdu_flow_idx_invalid_5018: API to get flow index invalid
  1233. * from rx_msdu_end TLV
  1234. * @buf: pointer to the start of RX PKT TLV headers
  1235. *
  1236. * Return: flow index invalid value from MSDU END TLV
  1237. */
  1238. static bool hal_rx_msdu_flow_idx_invalid_5018(uint8_t *buf)
  1239. {
  1240. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1241. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1242. return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  1243. }
  1244. /**
  1245. * hal_rx_msdu_flow_idx_timeout_5018: API to get flow index timeout
  1246. * from rx_msdu_end TLV
  1247. * @buf: pointer to the start of RX PKT TLV headers
  1248. *
  1249. * Return: flow index timeout value from MSDU END TLV
  1250. */
  1251. static bool hal_rx_msdu_flow_idx_timeout_5018(uint8_t *buf)
  1252. {
  1253. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1254. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1255. return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  1256. }
  1257. /**
  1258. * hal_rx_msdu_fse_metadata_get_5018: API to get FSE metadata
  1259. * from rx_msdu_end TLV
  1260. * @buf: pointer to the start of RX PKT TLV headers
  1261. *
  1262. * Return: fse metadata value from MSDU END TLV
  1263. */
  1264. static uint32_t hal_rx_msdu_fse_metadata_get_5018(uint8_t *buf)
  1265. {
  1266. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1267. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1268. return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
  1269. }
  1270. /**
  1271. * hal_rx_msdu_cce_metadata_get_5018: API to get CCE metadata
  1272. * from rx_msdu_end TLV
  1273. * @buf: pointer to the start of RX PKT TLV headers
  1274. *
  1275. * Return: cce_metadata
  1276. */
  1277. static uint16_t
  1278. hal_rx_msdu_cce_metadata_get_5018(uint8_t *buf)
  1279. {
  1280. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1281. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1282. return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
  1283. }
  1284. /**
  1285. * hal_rx_msdu_get_flow_params_5018: API to get flow index, flow index invalid
  1286. * and flow index timeout from rx_msdu_end TLV
  1287. * @buf: pointer to the start of RX PKT TLV headers
  1288. * @flow_invalid: pointer to return value of flow_idx_valid
  1289. * @flow_timeout: pointer to return value of flow_idx_timeout
  1290. * @flow_index: pointer to return value of flow_idx
  1291. *
  1292. * Return: none
  1293. */
  1294. static inline void
  1295. hal_rx_msdu_get_flow_params_5018(uint8_t *buf,
  1296. bool *flow_invalid,
  1297. bool *flow_timeout,
  1298. uint32_t *flow_index)
  1299. {
  1300. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1301. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1302. *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  1303. *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  1304. *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  1305. }
  1306. /**
  1307. * hal_rx_tlv_get_tcp_chksum_5018() - API to get tcp checksum
  1308. * @buf: rx_tlv_hdr
  1309. *
  1310. * Return: tcp checksum
  1311. */
  1312. static uint16_t
  1313. hal_rx_tlv_get_tcp_chksum_5018(uint8_t *buf)
  1314. {
  1315. return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
  1316. }
  1317. /**
  1318. * hal_rx_get_rx_sequence_5018(): Function to retrieve rx sequence number
  1319. *
  1320. * @nbuf: Network buffer
  1321. * Returns: rx sequence number
  1322. */
  1323. static
  1324. uint16_t hal_rx_get_rx_sequence_5018(uint8_t *buf)
  1325. {
  1326. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  1327. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  1328. return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
  1329. }
  1330. /**
  1331. * hal_get_window_address_5018(): Function to get hp/tp address
  1332. * @hal_soc: Pointer to hal_soc
  1333. * @addr: address offset of register
  1334. *
  1335. * Return: modified address offset of register
  1336. */
  1337. static inline qdf_iomem_t hal_get_window_address_5018(struct hal_soc *hal_soc,
  1338. qdf_iomem_t addr)
  1339. {
  1340. uint32_t offset = addr - hal_soc->dev_base_addr;
  1341. qdf_iomem_t new_offset;
  1342. /*
  1343. * Check if offset lies within CE register range(0x08400000)
  1344. * or UMAC/DP register range (0x00A00000).
  1345. * If offset lies within CE register range, map it
  1346. * into CE region.
  1347. */
  1348. if (offset & HOST_CE_MASK_VALUE) {
  1349. offset = offset - WFSS_CE_REG_BASE;
  1350. new_offset = (hal_soc->dev_base_addr_ce + offset);
  1351. return new_offset;
  1352. } else {
  1353. /*
  1354. * If offset lies within DP register range,
  1355. * return the address as such
  1356. */
  1357. return addr;
  1358. }
  1359. }
  1360. static inline void hal_write_window_register(struct hal_soc *hal_soc)
  1361. {
  1362. /* Write value into window configuration register */
  1363. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  1364. WINDOW_CONFIGURATION_VALUE_5018);
  1365. }
  1366. /**
  1367. * hal_rx_msdu_packet_metadata_get_5018(): API to get the
  1368. * msdu information from rx_msdu_end TLV
  1369. *
  1370. * @ buf: pointer to the start of RX PKT TLV headers
  1371. * @ hal_rx_msdu_metadata: pointer to the msdu info structure
  1372. */
  1373. static void
  1374. hal_rx_msdu_packet_metadata_get_5018(uint8_t *buf,
  1375. void *msdu_pkt_metadata)
  1376. {
  1377. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1378. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1379. struct hal_rx_msdu_metadata *msdu_metadata =
  1380. (struct hal_rx_msdu_metadata *)msdu_pkt_metadata;
  1381. msdu_metadata->l3_hdr_pad =
  1382. HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  1383. msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  1384. msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  1385. msdu_metadata->sa_sw_peer_id =
  1386. HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  1387. }
  1388. /**
  1389. * hal_rx_flow_setup_fse_5018() - Setup a flow search entry in HW FST
  1390. * @fst: Pointer to the Rx Flow Search Table
  1391. * @table_offset: offset into the table where the flow is to be setup
  1392. * @flow: Flow Parameters
  1393. *
  1394. * Return: Success/Failure
  1395. */
  1396. static void *
  1397. hal_rx_flow_setup_fse_5018(uint8_t *rx_fst, uint32_t table_offset,
  1398. uint8_t *rx_flow)
  1399. {
  1400. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  1401. struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
  1402. uint8_t *fse;
  1403. bool fse_valid;
  1404. if (table_offset >= fst->max_entries) {
  1405. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1406. "HAL FSE table offset %u exceeds max entries %u",
  1407. table_offset, fst->max_entries);
  1408. return NULL;
  1409. }
  1410. fse = (uint8_t *)fst->base_vaddr +
  1411. (table_offset * HAL_RX_FST_ENTRY_SIZE);
  1412. fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  1413. if (fse_valid) {
  1414. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1415. "HAL FSE %pK already valid", fse);
  1416. return NULL;
  1417. }
  1418. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) =
  1419. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
  1420. qdf_htonl(flow->tuple_info.src_ip_127_96));
  1421. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) =
  1422. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
  1423. qdf_htonl(flow->tuple_info.src_ip_95_64));
  1424. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) =
  1425. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
  1426. qdf_htonl(flow->tuple_info.src_ip_63_32));
  1427. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) =
  1428. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
  1429. qdf_htonl(flow->tuple_info.src_ip_31_0));
  1430. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) =
  1431. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
  1432. qdf_htonl(flow->tuple_info.dest_ip_127_96));
  1433. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) =
  1434. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
  1435. qdf_htonl(flow->tuple_info.dest_ip_95_64));
  1436. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) =
  1437. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
  1438. qdf_htonl(flow->tuple_info.dest_ip_63_32));
  1439. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) =
  1440. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
  1441. qdf_htonl(flow->tuple_info.dest_ip_31_0));
  1442. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT);
  1443. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |=
  1444. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
  1445. (flow->tuple_info.dest_port));
  1446. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT);
  1447. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |=
  1448. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
  1449. (flow->tuple_info.src_port));
  1450. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL);
  1451. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |=
  1452. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
  1453. flow->tuple_info.l4_protocol);
  1454. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER);
  1455. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |=
  1456. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
  1457. flow->reo_destination_handler);
  1458. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  1459. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |=
  1460. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
  1461. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA);
  1462. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) =
  1463. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
  1464. flow->fse_metadata);
  1465. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION);
  1466. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |=
  1467. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9,
  1468. REO_DESTINATION_INDICATION,
  1469. flow->reo_destination_indication);
  1470. /* Reset all the other fields in FSE */
  1471. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9);
  1472. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP);
  1473. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT);
  1474. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT);
  1475. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP);
  1476. return fse;
  1477. }
  1478. static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc)
  1479. {
  1480. /* init and setup */
  1481. hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
  1482. hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
  1483. hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
  1484. hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
  1485. hal_soc->ops->hal_get_window_address = hal_get_window_address_5018;
  1486. /* tx */
  1487. hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
  1488. hal_tx_desc_set_dscp_tid_table_id_5018;
  1489. hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5018;
  1490. hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5018;
  1491. hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_5018;
  1492. hal_soc->ops->hal_tx_desc_set_buf_addr =
  1493. hal_tx_desc_set_buf_addr_generic_li;
  1494. hal_soc->ops->hal_tx_desc_set_search_type =
  1495. hal_tx_desc_set_search_type_generic_li;
  1496. hal_soc->ops->hal_tx_desc_set_search_index =
  1497. hal_tx_desc_set_search_index_generic_li;
  1498. hal_soc->ops->hal_tx_desc_set_cache_set_num =
  1499. hal_tx_desc_set_cache_set_num_generic_li;
  1500. hal_soc->ops->hal_tx_comp_get_status =
  1501. hal_tx_comp_get_status_generic_li;
  1502. hal_soc->ops->hal_tx_comp_get_release_reason =
  1503. hal_tx_comp_get_release_reason_generic_li;
  1504. hal_soc->ops->hal_get_wbm_internal_error =
  1505. hal_get_wbm_internal_error_generic_li;
  1506. hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_5018;
  1507. hal_soc->ops->hal_tx_init_cmd_credit_ring =
  1508. hal_tx_init_cmd_credit_ring_5018;
  1509. /* rx */
  1510. hal_soc->ops->hal_rx_msdu_start_nss_get =
  1511. hal_rx_msdu_start_nss_get_5018;
  1512. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
  1513. hal_rx_mon_hw_desc_get_mpdu_status_5018;
  1514. hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5018;
  1515. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
  1516. hal_rx_proc_phyrx_other_receive_info_tlv_5018;
  1517. hal_soc->ops->hal_rx_dump_msdu_start_tlv =
  1518. hal_rx_dump_msdu_start_tlv_5018;
  1519. hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5018;
  1520. hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5018;
  1521. hal_soc->ops->hal_rx_mpdu_start_tid_get =
  1522. hal_rx_mpdu_start_tid_get_5018;
  1523. hal_soc->ops->hal_rx_msdu_start_reception_type_get =
  1524. hal_rx_msdu_start_reception_type_get_5018;
  1525. hal_soc->ops->hal_rx_msdu_end_da_idx_get =
  1526. hal_rx_msdu_end_da_idx_get_5018;
  1527. hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
  1528. hal_rx_msdu_desc_info_get_ptr_5018;
  1529. hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
  1530. hal_rx_link_desc_msdu0_ptr_5018;
  1531. hal_soc->ops->hal_reo_status_get_header =
  1532. hal_reo_status_get_header_5018;
  1533. hal_soc->ops->hal_rx_status_get_tlv_info =
  1534. hal_rx_status_get_tlv_info_generic_li;
  1535. hal_soc->ops->hal_rx_wbm_err_info_get =
  1536. hal_rx_wbm_err_info_get_generic_li;
  1537. hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
  1538. hal_rx_dump_mpdu_start_tlv_generic_li;
  1539. hal_soc->ops->hal_tx_set_pcp_tid_map =
  1540. hal_tx_set_pcp_tid_map_generic_li;
  1541. hal_soc->ops->hal_tx_update_pcp_tid_map =
  1542. hal_tx_update_pcp_tid_generic_li;
  1543. hal_soc->ops->hal_tx_set_tidmap_prty =
  1544. hal_tx_update_tidmap_prty_generic_li;
  1545. hal_soc->ops->hal_rx_get_rx_fragment_number =
  1546. hal_rx_get_rx_fragment_number_5018;
  1547. hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
  1548. hal_rx_msdu_end_da_is_mcbc_get_5018;
  1549. hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
  1550. hal_rx_msdu_end_sa_is_valid_get_5018;
  1551. hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
  1552. hal_rx_msdu_end_sa_idx_get_5018;
  1553. hal_soc->ops->hal_rx_desc_is_first_msdu =
  1554. hal_rx_desc_is_first_msdu_5018;
  1555. hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
  1556. hal_rx_msdu_end_l3_hdr_padding_get_5018;
  1557. hal_soc->ops->hal_rx_encryption_info_valid =
  1558. hal_rx_encryption_info_valid_5018;
  1559. hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_5018;
  1560. hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
  1561. hal_rx_msdu_end_first_msdu_get_5018;
  1562. hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
  1563. hal_rx_msdu_end_da_is_valid_get_5018;
  1564. hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
  1565. hal_rx_msdu_end_last_msdu_get_5018;
  1566. hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
  1567. hal_rx_get_mpdu_mac_ad4_valid_5018;
  1568. hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
  1569. hal_rx_mpdu_start_sw_peer_id_get_5018;
  1570. hal_soc->ops->hal_rx_mpdu_peer_meta_data_get =
  1571. hal_rx_mpdu_peer_meta_data_get_li;
  1572. hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_5018;
  1573. hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_5018;
  1574. hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
  1575. hal_rx_get_mpdu_frame_control_valid_5018;
  1576. hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_5018;
  1577. hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_5018;
  1578. hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_5018;
  1579. hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_5018;
  1580. hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
  1581. hal_rx_get_mpdu_sequence_control_valid_5018;
  1582. hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_5018;
  1583. hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_5018;
  1584. hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
  1585. hal_rx_hw_desc_get_ppduid_get_5018;
  1586. hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
  1587. hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018;
  1588. hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
  1589. hal_rx_msdu_end_sa_sw_peer_id_get_5018;
  1590. hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
  1591. hal_rx_msdu0_buffer_addr_lsb_5018;
  1592. hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
  1593. hal_rx_msdu_desc_info_ptr_get_5018;
  1594. hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5018;
  1595. hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5018;
  1596. hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_5018;
  1597. hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_5018;
  1598. hal_soc->ops->hal_rx_get_mac_addr2_valid =
  1599. hal_rx_get_mac_addr2_valid_5018;
  1600. hal_soc->ops->hal_rx_get_filter_category =
  1601. hal_rx_get_filter_category_5018;
  1602. hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_5018;
  1603. hal_soc->ops->hal_reo_config = hal_reo_config_5018;
  1604. hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_5018;
  1605. hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
  1606. hal_rx_msdu_flow_idx_invalid_5018;
  1607. hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
  1608. hal_rx_msdu_flow_idx_timeout_5018;
  1609. hal_soc->ops->hal_rx_msdu_fse_metadata_get =
  1610. hal_rx_msdu_fse_metadata_get_5018;
  1611. hal_soc->ops->hal_rx_msdu_cce_match_get =
  1612. hal_rx_msdu_cce_match_get_li;
  1613. hal_soc->ops->hal_rx_msdu_cce_metadata_get =
  1614. hal_rx_msdu_cce_metadata_get_5018;
  1615. hal_soc->ops->hal_rx_msdu_get_flow_params =
  1616. hal_rx_msdu_get_flow_params_5018;
  1617. hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
  1618. hal_rx_tlv_get_tcp_chksum_5018;
  1619. hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_5018;
  1620. #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
  1621. hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5018;
  1622. hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5018;
  1623. #endif
  1624. /* rx - msdu fast path info fields */
  1625. hal_soc->ops->hal_rx_msdu_packet_metadata_get =
  1626. hal_rx_msdu_packet_metadata_get_5018;
  1627. hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
  1628. hal_rx_mpdu_start_tlv_tag_valid_5018;
  1629. hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
  1630. hal_rx_wbm_err_msdu_continuation_get_5018;
  1631. /* rx - TLV struct offsets */
  1632. hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
  1633. hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
  1634. hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
  1635. hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
  1636. hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
  1637. #ifndef NO_RX_PKT_HDR_TLV
  1638. hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
  1639. #endif
  1640. hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5018;
  1641. hal_soc->ops->hal_rx_flow_get_tuple_info =
  1642. hal_rx_flow_get_tuple_info_li;
  1643. hal_soc->ops->hal_rx_flow_delete_entry =
  1644. hal_rx_flow_delete_entry_li;
  1645. hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li;
  1646. hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_5018;
  1647. hal_soc->ops->hal_setup_link_idle_list =
  1648. hal_setup_link_idle_list_generic_li;
  1649. hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
  1650. };
  1651. struct hal_hw_srng_config hw_srng_table_5018[] = {
  1652. /* TODO: max_rings can populated by querying HW capabilities */
  1653. { /* REO_DST */
  1654. .start_ring_id = HAL_SRNG_REO2SW1,
  1655. .max_rings = 4,
  1656. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1657. .lmac_ring = FALSE,
  1658. .ring_dir = HAL_SRNG_DST_RING,
  1659. .reg_start = {
  1660. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
  1661. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1662. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
  1663. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1664. },
  1665. .reg_size = {
  1666. HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
  1667. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
  1668. HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
  1669. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
  1670. },
  1671. .max_size =
  1672. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1673. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
  1674. },
  1675. { /* REO_EXCEPTION */
  1676. /* Designating REO2TCL ring as exception ring. This ring is
  1677. * similar to other REO2SW rings though it is named as REO2TCL.
  1678. * Any of theREO2SW rings can be used as exception ring.
  1679. */
  1680. .start_ring_id = HAL_SRNG_REO2TCL,
  1681. .max_rings = 1,
  1682. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1683. .lmac_ring = FALSE,
  1684. .ring_dir = HAL_SRNG_DST_RING,
  1685. .reg_start = {
  1686. HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
  1687. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1688. HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
  1689. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1690. },
  1691. /* Single ring - provide ring size if multiple rings of this
  1692. * type are supported
  1693. */
  1694. .reg_size = {},
  1695. .max_size =
  1696. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
  1697. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
  1698. },
  1699. { /* REO_REINJECT */
  1700. .start_ring_id = HAL_SRNG_SW2REO,
  1701. .max_rings = 1,
  1702. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1703. .lmac_ring = FALSE,
  1704. .ring_dir = HAL_SRNG_SRC_RING,
  1705. .reg_start = {
  1706. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
  1707. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1708. HWIO_REO_R2_SW2REO_RING_HP_ADDR(
  1709. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1710. },
  1711. /* Single ring - provide ring size if multiple rings of this
  1712. * type are supported
  1713. */
  1714. .reg_size = {},
  1715. .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
  1716. HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
  1717. },
  1718. { /* REO_CMD */
  1719. .start_ring_id = HAL_SRNG_REO_CMD,
  1720. .max_rings = 1,
  1721. .entry_size = (sizeof(struct tlv_32_hdr) +
  1722. sizeof(struct reo_get_queue_stats)) >> 2,
  1723. .lmac_ring = FALSE,
  1724. .ring_dir = HAL_SRNG_SRC_RING,
  1725. .reg_start = {
  1726. HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
  1727. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1728. HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
  1729. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1730. },
  1731. /* Single ring - provide ring size if multiple rings of this
  1732. * type are supported
  1733. */
  1734. .reg_size = {},
  1735. .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1736. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1737. },
  1738. { /* REO_STATUS */
  1739. .start_ring_id = HAL_SRNG_REO_STATUS,
  1740. .max_rings = 1,
  1741. .entry_size = (sizeof(struct tlv_32_hdr) +
  1742. sizeof(struct reo_get_queue_stats_status)) >> 2,
  1743. .lmac_ring = FALSE,
  1744. .ring_dir = HAL_SRNG_DST_RING,
  1745. .reg_start = {
  1746. HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
  1747. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1748. HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
  1749. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1750. },
  1751. /* Single ring - provide ring size if multiple rings of this
  1752. * type are supported
  1753. */
  1754. .reg_size = {},
  1755. .max_size =
  1756. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1757. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1758. },
  1759. { /* TCL_DATA */
  1760. .start_ring_id = HAL_SRNG_SW2TCL1,
  1761. .max_rings = 3,
  1762. .entry_size = (sizeof(struct tlv_32_hdr) +
  1763. sizeof(struct tcl_data_cmd)) >> 2,
  1764. .lmac_ring = FALSE,
  1765. .ring_dir = HAL_SRNG_SRC_RING,
  1766. .reg_start = {
  1767. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
  1768. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1769. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
  1770. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1771. },
  1772. .reg_size = {
  1773. HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
  1774. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
  1775. HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
  1776. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
  1777. },
  1778. .max_size =
  1779. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1780. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
  1781. },
  1782. { /* TCL_CMD */
  1783. .start_ring_id = HAL_SRNG_SW2TCL_CMD,
  1784. .max_rings = 1,
  1785. .entry_size = (sizeof(struct tlv_32_hdr) +
  1786. sizeof(struct tcl_data_cmd)) >> 2,
  1787. .lmac_ring = FALSE,
  1788. .ring_dir = HAL_SRNG_SRC_RING,
  1789. .reg_start = {
  1790. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
  1791. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1792. HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
  1793. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1794. },
  1795. /* Single ring - provide ring size if multiple rings of this
  1796. * type are supported
  1797. */
  1798. .reg_size = {},
  1799. .max_size =
  1800. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
  1801. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
  1802. },
  1803. { /* TCL_STATUS */
  1804. .start_ring_id = HAL_SRNG_TCL_STATUS,
  1805. .max_rings = 1,
  1806. .entry_size = (sizeof(struct tlv_32_hdr) +
  1807. sizeof(struct tcl_status_ring)) >> 2,
  1808. .lmac_ring = FALSE,
  1809. .ring_dir = HAL_SRNG_DST_RING,
  1810. .reg_start = {
  1811. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
  1812. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1813. HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
  1814. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1815. },
  1816. /* Single ring - provide ring size if multiple rings of this
  1817. * type are supported
  1818. */
  1819. .reg_size = {},
  1820. .max_size =
  1821. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1822. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
  1823. },
  1824. { /* CE_SRC */
  1825. .start_ring_id = HAL_SRNG_CE_0_SRC,
  1826. .max_rings = 12,
  1827. .entry_size = sizeof(struct ce_src_desc) >> 2,
  1828. .lmac_ring = FALSE,
  1829. .ring_dir = HAL_SRNG_SRC_RING,
  1830. .reg_start = {
  1831. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1832. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1833. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1834. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1835. },
  1836. .reg_size = {
  1837. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1838. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1839. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1840. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1841. },
  1842. .max_size =
  1843. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1844. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1845. },
  1846. { /* CE_DST */
  1847. .start_ring_id = HAL_SRNG_CE_0_DST,
  1848. .max_rings = 12,
  1849. .entry_size = 8 >> 2,
  1850. /*TODO: entry_size above should actually be
  1851. * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
  1852. * of struct ce_dst_desc in HW header files
  1853. */
  1854. .lmac_ring = FALSE,
  1855. .ring_dir = HAL_SRNG_SRC_RING,
  1856. .reg_start = {
  1857. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1858. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1859. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1860. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1861. },
  1862. .reg_size = {
  1863. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1864. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1865. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1866. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1867. },
  1868. .max_size =
  1869. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1870. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1871. },
  1872. { /* CE_DST_STATUS */
  1873. .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
  1874. .max_rings = 12,
  1875. .entry_size = sizeof(struct ce_stat_desc) >> 2,
  1876. .lmac_ring = FALSE,
  1877. .ring_dir = HAL_SRNG_DST_RING,
  1878. .reg_start = {
  1879. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
  1880. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1881. HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
  1882. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1883. },
  1884. /* TODO: check destination status ring registers */
  1885. .reg_size = {
  1886. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1887. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1888. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1889. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1890. },
  1891. .max_size =
  1892. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1893. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1894. },
  1895. { /* WBM_IDLE_LINK */
  1896. .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
  1897. .max_rings = 1,
  1898. .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
  1899. .lmac_ring = FALSE,
  1900. .ring_dir = HAL_SRNG_SRC_RING,
  1901. .reg_start = {
  1902. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1903. HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1904. },
  1905. /* Single ring - provide ring size if multiple rings of this
  1906. * type are supported
  1907. */
  1908. .reg_size = {},
  1909. .max_size =
  1910. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
  1911. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
  1912. },
  1913. { /* SW2WBM_RELEASE */
  1914. .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
  1915. .max_rings = 1,
  1916. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1917. .lmac_ring = FALSE,
  1918. .ring_dir = HAL_SRNG_SRC_RING,
  1919. .reg_start = {
  1920. HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1921. HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1922. },
  1923. /* Single ring - provide ring size if multiple rings of this
  1924. * type are supported
  1925. */
  1926. .reg_size = {},
  1927. .max_size =
  1928. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1929. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1930. },
  1931. { /* WBM2SW_RELEASE */
  1932. .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
  1933. .max_rings = 5,
  1934. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1935. .lmac_ring = FALSE,
  1936. .ring_dir = HAL_SRNG_DST_RING,
  1937. .reg_start = {
  1938. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1939. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1940. },
  1941. .reg_size = {
  1942. HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  1943. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1944. HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  1945. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1946. },
  1947. .max_size =
  1948. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1949. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1950. },
  1951. { /* RXDMA_BUF */
  1952. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
  1953. #ifdef IPA_OFFLOAD
  1954. .max_rings = 3,
  1955. #else
  1956. .max_rings = 2,
  1957. #endif
  1958. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1959. .lmac_ring = TRUE,
  1960. .ring_dir = HAL_SRNG_SRC_RING,
  1961. /* reg_start is not set because LMAC rings are not accessed
  1962. * from host
  1963. */
  1964. .reg_start = {},
  1965. .reg_size = {},
  1966. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1967. },
  1968. { /* RXDMA_DST */
  1969. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
  1970. .max_rings = 1,
  1971. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1972. .lmac_ring = TRUE,
  1973. .ring_dir = HAL_SRNG_DST_RING,
  1974. /* reg_start is not set because LMAC rings are not accessed
  1975. * from host
  1976. */
  1977. .reg_start = {},
  1978. .reg_size = {},
  1979. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1980. },
  1981. { /* RXDMA_MONITOR_BUF */
  1982. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  1983. .max_rings = 1,
  1984. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1985. .lmac_ring = TRUE,
  1986. .ring_dir = HAL_SRNG_SRC_RING,
  1987. /* reg_start is not set because LMAC rings are not accessed
  1988. * from host
  1989. */
  1990. .reg_start = {},
  1991. .reg_size = {},
  1992. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1993. },
  1994. { /* RXDMA_MONITOR_STATUS */
  1995. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  1996. .max_rings = 1,
  1997. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1998. .lmac_ring = TRUE,
  1999. .ring_dir = HAL_SRNG_SRC_RING,
  2000. /* reg_start is not set because LMAC rings are not accessed
  2001. * from host
  2002. */
  2003. .reg_start = {},
  2004. .reg_size = {},
  2005. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2006. },
  2007. { /* RXDMA_MONITOR_DST */
  2008. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
  2009. .max_rings = 1,
  2010. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  2011. .lmac_ring = TRUE,
  2012. .ring_dir = HAL_SRNG_DST_RING,
  2013. /* reg_start is not set because LMAC rings are not accessed
  2014. * from host
  2015. */
  2016. .reg_start = {},
  2017. .reg_size = {},
  2018. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2019. },
  2020. { /* RXDMA_MONITOR_DESC */
  2021. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  2022. .max_rings = 1,
  2023. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2024. .lmac_ring = TRUE,
  2025. .ring_dir = HAL_SRNG_SRC_RING,
  2026. /* reg_start is not set because LMAC rings are not accessed
  2027. * from host
  2028. */
  2029. .reg_start = {},
  2030. .reg_size = {},
  2031. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2032. },
  2033. { /* DIR_BUF_RX_DMA_SRC */
  2034. .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  2035. /* one ring for spectral and one ring for cfr */
  2036. .max_rings = 2,
  2037. .entry_size = 2,
  2038. .lmac_ring = TRUE,
  2039. .ring_dir = HAL_SRNG_SRC_RING,
  2040. /* reg_start is not set because LMAC rings are not accessed
  2041. * from host
  2042. */
  2043. .reg_start = {},
  2044. .reg_size = {},
  2045. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2046. },
  2047. #ifdef WLAN_FEATURE_CIF_CFR
  2048. { /* WIFI_POS_SRC */
  2049. .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  2050. .max_rings = 1,
  2051. .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
  2052. .lmac_ring = TRUE,
  2053. .ring_dir = HAL_SRNG_SRC_RING,
  2054. /* reg_start is not set because LMAC rings are not accessed
  2055. * from host
  2056. */
  2057. .reg_start = {},
  2058. .reg_size = {},
  2059. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2060. },
  2061. #endif
  2062. { /* REO2PPE */ 0},
  2063. { /* PPE2TCL */ 0},
  2064. { /* PPE_RELEASE */ 0},
  2065. { /* TX_MONITOR_BUF */ 0},
  2066. { /* TX_MONITOR_DST */ 0},
  2067. { /* SW2RXDMA_NEW */ 0},
  2068. };
  2069. /**
  2070. * hal_qca5018_attach()- Attach 5018 target specific hal_soc ops,
  2071. * offset and srng table
  2072. * Return: void
  2073. */
  2074. void hal_qca5018_attach(struct hal_soc *hal_soc)
  2075. {
  2076. hal_soc->hw_srng_table = hw_srng_table_5018;
  2077. hal_srng_hw_reg_offset_init_generic(hal_soc);
  2078. hal_hw_txrx_default_ops_attach_li(hal_soc);
  2079. hal_hw_txrx_ops_attach_qca5018(hal_soc);
  2080. }