hal_li_rx.h 36 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_LI_RX_H_
  20. #define _HAL_LI_RX_H_
  21. #include <hal_rx.h>
  22. /*
  23. * macro to set the cookie into the rxdma ring entry
  24. */
  25. #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \
  26. ((*(((unsigned int *)buff_addr_info) + \
  27. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
  28. ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \
  29. ((*(((unsigned int *)buff_addr_info) + \
  30. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  31. ((cookie) << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
  32. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)
  33. /*
  34. * macro to set the manager into the rxdma ring entry
  35. */
  36. #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \
  37. ((*(((unsigned int *)buff_addr_info) + \
  38. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \
  39. ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \
  40. ((*(((unsigned int *)buff_addr_info) + \
  41. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \
  42. ((manager) << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \
  43. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK)
  44. #define HAL_RX_ERROR_STATUS_GET(reo_desc) \
  45. (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \
  46. REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\
  47. REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \
  48. REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB))
  49. #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \
  50. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  51. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \
  52. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \
  53. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB))
  54. #define HAL_RX_BUF_RBM_GET(buff_addr_info) \
  55. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  56. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\
  57. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \
  58. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB))
  59. /* TODO: Convert the following structure fields accesseses to offsets */
  60. #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \
  61. (HAL_RX_BUF_COOKIE_GET(& \
  62. (((struct reo_destination_ring *) \
  63. reo_desc)->buf_or_link_desc_addr_info)))
  64. #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \
  65. ((mpdu_info_ptr \
  66. [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \
  67. RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \
  68. RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB)
  69. #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \
  70. ((mpdu_info_ptr \
  71. [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \
  72. RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \
  73. RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB)
  74. #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \
  75. ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \
  76. RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \
  77. RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB)
  78. #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \
  79. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \
  80. RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK)
  81. #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \
  82. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \
  83. RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK)
  84. #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \
  85. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \
  86. RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK)
  87. #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \
  88. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \
  89. RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK)
  90. #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \
  91. (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \
  92. HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \
  93. HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \
  94. HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr))
  95. #define HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info_ptr) \
  96. ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET >> 2] & \
  97. RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK) >> \
  98. RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB)
  99. /*
  100. * NOTE: None of the following _GET macros need a right
  101. * shift by the corresponding _LSB. This is because, they are
  102. * finally taken and "OR'ed" into a single word again.
  103. */
  104. #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \
  105. ((*(((uint32_t *)msdu_info_ptr) + \
  106. (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \
  107. ((val) << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \
  108. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK)
  109. #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \
  110. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  111. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \
  112. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK)
  113. #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \
  114. (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  115. RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \
  116. RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \
  117. RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB))
  118. #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  119. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  120. RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \
  121. RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK)
  122. #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  123. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  124. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \
  125. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK)
  126. #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  127. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  128. RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \
  129. RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK)
  130. #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \
  131. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  132. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \
  133. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK)
  134. #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  135. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  136. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \
  137. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK)
  138. #define HAL_RX_REO_MSDU_REO_DST_IND_GET(reo_desc) \
  139. (HAL_RX_MSDU_REO_DST_IND_GET(& \
  140. (((struct reo_destination_ring *) \
  141. reo_desc)->rx_msdu_desc_info_details)))
  142. #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \
  143. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  144. RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \
  145. RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \
  146. RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB))
  147. #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \
  148. HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \
  149. _field, _val)
  150. #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \
  151. HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \
  152. _field, _val)
  153. /*
  154. * Structures & Macros to obtain fields from the TLV's in the Rx packet
  155. * pre-header.
  156. */
  157. /*
  158. * Every Rx packet starts at an offset from the top of the buffer.
  159. * If the host hasn't subscribed to any specific TLV, there is
  160. * still space reserved for the following TLV's from the start of
  161. * the buffer:
  162. * -- RX ATTENTION
  163. * -- RX MPDU START
  164. * -- RX MSDU START
  165. * -- RX MSDU END
  166. * -- RX MPDU END
  167. * -- RX PACKET HEADER (802.11)
  168. * If the host subscribes to any of the TLV's above, that TLV
  169. * if populated by the HW
  170. */
  171. #define NUM_DWORDS_TAG 1
  172. /* By default the packet header TLV is 128 bytes */
  173. #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128
  174. #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \
  175. (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2)
  176. #define RX_PKT_OFFSET_WORDS \
  177. ( \
  178. NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \
  179. NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \
  180. NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \
  181. NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \
  182. NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \
  183. NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \
  184. )
  185. #define RX_PKT_OFFSET_BYTES \
  186. (RX_PKT_OFFSET_WORDS << 2)
  187. #define RX_PKT_HDR_TLV_LEN 120
  188. /*
  189. * Each RX descriptor TLV is preceded by 1 DWORD "tag"
  190. */
  191. struct rx_attention_tlv {
  192. uint32_t tag;
  193. struct rx_attention rx_attn;
  194. };
  195. struct rx_mpdu_start_tlv {
  196. uint32_t tag;
  197. struct rx_mpdu_start rx_mpdu_start;
  198. };
  199. struct rx_msdu_start_tlv {
  200. uint32_t tag;
  201. struct rx_msdu_start rx_msdu_start;
  202. };
  203. struct rx_msdu_end_tlv {
  204. uint32_t tag;
  205. struct rx_msdu_end rx_msdu_end;
  206. };
  207. struct rx_mpdu_end_tlv {
  208. uint32_t tag;
  209. struct rx_mpdu_end rx_mpdu_end;
  210. };
  211. struct rx_pkt_hdr_tlv {
  212. uint32_t tag; /* 4 B */
  213. uint32_t phy_ppdu_id; /* 4 B */
  214. char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */
  215. };
  216. /* rx_pkt_tlvs structure should be used to process Data buffers, monitor status
  217. * buffers, monitor destination buffers and monitor descriptor buffers.
  218. */
  219. #ifdef RXDMA_OPTIMIZATION
  220. /*
  221. * The RX_PADDING_BYTES is required so that the TLV's don't
  222. * spread across the 128 byte boundary
  223. * RXDMA optimization requires:
  224. * 1) MSDU_END & ATTENTION TLV's follow in that order
  225. * 2) TLV's don't span across 128 byte lines
  226. * 3) Rx Buffer is nicely aligned on the 128 byte boundary
  227. */
  228. #define RX_PADDING0_BYTES 4
  229. #define RX_PADDING1_BYTES 16
  230. struct rx_pkt_tlvs {
  231. struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
  232. struct rx_attention_tlv attn_tlv; /* 16 bytes */
  233. struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
  234. uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
  235. struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
  236. struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
  237. uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
  238. #ifndef NO_RX_PKT_HDR_TLV
  239. struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
  240. #endif
  241. };
  242. #else /* RXDMA_OPTIMIZATION */
  243. struct rx_pkt_tlvs {
  244. struct rx_attention_tlv attn_tlv;
  245. struct rx_mpdu_start_tlv mpdu_start_tlv;
  246. struct rx_msdu_start_tlv msdu_start_tlv;
  247. struct rx_msdu_end_tlv msdu_end_tlv;
  248. struct rx_mpdu_end_tlv mpdu_end_tlv;
  249. struct rx_pkt_hdr_tlv pkt_hdr_tlv;
  250. };
  251. #endif /* RXDMA_OPTIMIZATION */
  252. /* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */
  253. #ifdef RXDMA_OPTIMIZATION
  254. struct rx_mon_pkt_tlvs {
  255. struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
  256. struct rx_attention_tlv attn_tlv; /* 16 bytes */
  257. struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
  258. uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
  259. struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
  260. struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
  261. uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
  262. struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
  263. };
  264. #else /* RXDMA_OPTIMIZATION */
  265. struct rx_mon_pkt_tlvs {
  266. struct rx_attention_tlv attn_tlv;
  267. struct rx_mpdu_start_tlv mpdu_start_tlv;
  268. struct rx_msdu_start_tlv msdu_start_tlv;
  269. struct rx_msdu_end_tlv msdu_end_tlv;
  270. struct rx_mpdu_end_tlv mpdu_end_tlv;
  271. struct rx_pkt_hdr_tlv pkt_hdr_tlv;
  272. };
  273. #endif
  274. #define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs)
  275. #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs)
  276. #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV
  277. #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field)
  278. #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \
  279. RX_PKT_TLV_OFFSET(mpdu_start_tlv)
  280. #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv)
  281. #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \
  282. RX_PKT_TLV_OFFSET(msdu_start_tlv)
  283. #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv)
  284. #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv)
  285. #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv)
  286. /**
  287. * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf
  288. *
  289. * @nbuf: Pointer to data buffer field
  290. * Returns: pointer to rx_pkt_tlvs
  291. */
  292. static inline
  293. struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start)
  294. {
  295. return (struct rx_pkt_tlvs *)rx_buf_start;
  296. }
  297. /**
  298. * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs
  299. *
  300. * @pkt_tlvs: Pointer to pkt_tlvs
  301. * Returns: pointer to rx_mpdu_info structure
  302. */
  303. static inline
  304. struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs)
  305. {
  306. return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  307. }
  308. /**
  309. * hal_rx_mon_dest_get_buffer_info_from_tlv(): Retrieve mon dest frame info
  310. * from the reserved bytes of rx_tlv_hdr.
  311. * @buf: start of rx_tlv_hdr
  312. * @buf_info: hal_rx_mon_dest_buf_info structure
  313. *
  314. * Return: void
  315. */
  316. static inline void hal_rx_mon_dest_get_buffer_info_from_tlv(
  317. uint8_t *buf,
  318. struct hal_rx_mon_dest_buf_info *buf_info)
  319. {
  320. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  321. qdf_mem_copy(buf_info, pkt_tlvs->rx_padding0,
  322. sizeof(struct hal_rx_mon_dest_buf_info));
  323. }
  324. /*
  325. * Get msdu_done bit from the RX_ATTENTION TLV
  326. */
  327. #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \
  328. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  329. RX_ATTENTION_2_MSDU_DONE_OFFSET)), \
  330. RX_ATTENTION_2_MSDU_DONE_MASK, \
  331. RX_ATTENTION_2_MSDU_DONE_LSB))
  332. #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \
  333. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  334. RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \
  335. RX_ATTENTION_1_FIRST_MPDU_MASK, \
  336. RX_ATTENTION_1_FIRST_MPDU_LSB))
  337. #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \
  338. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  339. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \
  340. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \
  341. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB))
  342. /*
  343. * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit
  344. * from rx attention
  345. * @buf: pointer to rx_pkt_tlvs
  346. *
  347. * Return: tcp_udp_cksum_fail
  348. */
  349. static inline bool
  350. hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf)
  351. {
  352. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  353. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  354. uint8_t tcp_udp_cksum_fail;
  355. tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn);
  356. return !!tcp_udp_cksum_fail;
  357. }
  358. #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \
  359. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  360. RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \
  361. RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \
  362. RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB))
  363. /*
  364. * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit
  365. * from rx attention
  366. * @buf: pointer to rx_pkt_tlvs
  367. *
  368. * Return: ip_cksum_fail
  369. */
  370. static inline bool
  371. hal_rx_attn_ip_cksum_fail_get(uint8_t *buf)
  372. {
  373. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  374. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  375. uint8_t ip_cksum_fail;
  376. ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn);
  377. return !!ip_cksum_fail;
  378. }
  379. #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \
  380. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  381. RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \
  382. RX_ATTENTION_0_PHY_PPDU_ID_MASK, \
  383. RX_ATTENTION_0_PHY_PPDU_ID_LSB))
  384. #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \
  385. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  386. RX_ATTENTION_1_CCE_MATCH_OFFSET)), \
  387. RX_ATTENTION_1_CCE_MATCH_MASK, \
  388. RX_ATTENTION_1_CCE_MATCH_LSB))
  389. /*
  390. * hal_rx_msdu_cce_match_get_li(): get CCE match bit
  391. * from rx attention
  392. * @buf: pointer to rx_pkt_tlvs
  393. * Return: CCE match value
  394. */
  395. static inline bool
  396. hal_rx_msdu_cce_match_get_li(uint8_t *buf)
  397. {
  398. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  399. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  400. uint8_t cce_match_val;
  401. cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn);
  402. return !!cce_match_val;
  403. }
  404. /*
  405. * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START
  406. */
  407. #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \
  408. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  409. RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \
  410. RX_MPDU_INFO_8_PEER_META_DATA_MASK, \
  411. RX_MPDU_INFO_8_PEER_META_DATA_LSB))
  412. static inline uint32_t
  413. hal_rx_mpdu_peer_meta_data_get_li(uint8_t *buf)
  414. {
  415. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  416. struct rx_mpdu_start *mpdu_start =
  417. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  418. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  419. uint32_t peer_meta_data;
  420. peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info);
  421. return peer_meta_data;
  422. }
  423. #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \
  424. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  425. RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \
  426. RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \
  427. RX_MPDU_INFO_12_AMPDU_FLAG_LSB))
  428. #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \
  429. ((*(((uint32_t *)_rx_mpdu_info) + \
  430. (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \
  431. ((peer_mdata) << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \
  432. RX_MPDU_INFO_8_PEER_META_DATA_MASK)
  433. /*
  434. * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv
  435. *
  436. * @ buf: rx_tlv_hdr of the received packet
  437. * @ peer_mdata: peer meta data to be set.
  438. * @ Return: void
  439. */
  440. static inline void
  441. hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata)
  442. {
  443. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  444. struct rx_mpdu_start *mpdu_start =
  445. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  446. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  447. HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata);
  448. }
  449. /**
  450. * LRO information needed from the TLVs
  451. */
  452. #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \
  453. (_HAL_MS( \
  454. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  455. msdu_end_tlv.rx_msdu_end), \
  456. RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \
  457. RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \
  458. RX_MSDU_END_9_LRO_ELIGIBLE_LSB))
  459. #define HAL_RX_TLV_GET_TCP_ACK(buf) \
  460. (_HAL_MS( \
  461. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  462. msdu_end_tlv.rx_msdu_end), \
  463. RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \
  464. RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \
  465. RX_MSDU_END_8_TCP_ACK_NUMBER_LSB))
  466. #define HAL_RX_TLV_GET_TCP_SEQ(buf) \
  467. (_HAL_MS( \
  468. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  469. msdu_end_tlv.rx_msdu_end), \
  470. RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \
  471. RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \
  472. RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB))
  473. #define HAL_RX_TLV_GET_TCP_WIN(buf) \
  474. (_HAL_MS( \
  475. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  476. msdu_end_tlv.rx_msdu_end), \
  477. RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \
  478. RX_MSDU_END_9_WINDOW_SIZE_MASK, \
  479. RX_MSDU_END_9_WINDOW_SIZE_LSB))
  480. #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \
  481. (_HAL_MS( \
  482. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  483. msdu_start_tlv.rx_msdu_start), \
  484. RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \
  485. RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \
  486. RX_MSDU_START_2_TCP_ONLY_ACK_LSB))
  487. #define HAL_RX_TLV_GET_TCP_PROTO(buf) \
  488. (_HAL_MS( \
  489. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  490. msdu_start_tlv.rx_msdu_start), \
  491. RX_MSDU_START_2_TCP_PROTO_OFFSET)), \
  492. RX_MSDU_START_2_TCP_PROTO_MASK, \
  493. RX_MSDU_START_2_TCP_PROTO_LSB))
  494. #define HAL_RX_TLV_GET_UDP_PROTO(buf) \
  495. (_HAL_MS( \
  496. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  497. msdu_start_tlv.rx_msdu_start), \
  498. RX_MSDU_START_2_UDP_PROTO_OFFSET)), \
  499. RX_MSDU_START_2_UDP_PROTO_MASK, \
  500. RX_MSDU_START_2_UDP_PROTO_LSB))
  501. #define HAL_RX_TLV_GET_IPV6(buf) \
  502. (_HAL_MS( \
  503. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  504. msdu_start_tlv.rx_msdu_start), \
  505. RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \
  506. RX_MSDU_START_2_IPV6_PROTO_MASK, \
  507. RX_MSDU_START_2_IPV6_PROTO_LSB))
  508. #define HAL_RX_TLV_GET_IP_OFFSET(buf) \
  509. (_HAL_MS( \
  510. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  511. msdu_start_tlv.rx_msdu_start), \
  512. RX_MSDU_START_1_L3_OFFSET_OFFSET)), \
  513. RX_MSDU_START_1_L3_OFFSET_MASK, \
  514. RX_MSDU_START_1_L3_OFFSET_LSB))
  515. #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \
  516. (_HAL_MS( \
  517. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  518. msdu_start_tlv.rx_msdu_start), \
  519. RX_MSDU_START_1_L4_OFFSET_OFFSET)), \
  520. RX_MSDU_START_1_L4_OFFSET_MASK, \
  521. RX_MSDU_START_1_L4_OFFSET_LSB))
  522. #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \
  523. (_HAL_MS( \
  524. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  525. msdu_start_tlv.rx_msdu_start), \
  526. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \
  527. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \
  528. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB))
  529. #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \
  530. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  531. RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \
  532. RX_MSDU_START_1_MSDU_LENGTH_MASK, \
  533. RX_MSDU_START_1_MSDU_LENGTH_LSB))
  534. #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \
  535. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  536. RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \
  537. RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \
  538. RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB))
  539. #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \
  540. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  541. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \
  542. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \
  543. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB))
  544. /**
  545. * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash
  546. * from rx_msdu_start TLV
  547. *
  548. * @ buf: pointer to the start of RX PKT TLV headers
  549. * Return: toeplitz hash
  550. */
  551. static inline uint32_t
  552. hal_rx_msdu_start_toeplitz_get(uint8_t *buf)
  553. {
  554. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  555. struct rx_msdu_start *msdu_start =
  556. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  557. return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start);
  558. }
  559. #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \
  560. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  561. RX_MSDU_START_5_SGI_OFFSET)), \
  562. RX_MSDU_START_5_SGI_MASK, \
  563. RX_MSDU_START_5_SGI_LSB))
  564. #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \
  565. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  566. RX_MSDU_START_5_RATE_MCS_OFFSET)), \
  567. RX_MSDU_START_5_RATE_MCS_MASK, \
  568. RX_MSDU_START_5_RATE_MCS_LSB))
  569. #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \
  570. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  571. RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \
  572. RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \
  573. RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB))
  574. /*
  575. * Get key index from RX_MSDU_END
  576. */
  577. #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \
  578. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  579. RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \
  580. RX_MSDU_END_2_KEY_ID_OCTET_MASK, \
  581. RX_MSDU_END_2_KEY_ID_OCTET_LSB))
  582. #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \
  583. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  584. RX_MSDU_START_5_USER_RSSI_OFFSET)), \
  585. RX_MSDU_START_5_USER_RSSI_MASK, \
  586. RX_MSDU_START_5_USER_RSSI_LSB))
  587. /*
  588. * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt
  589. * from rx_msdu_start
  590. *
  591. * @buf: pointer to the start of RX PKT TLV header
  592. * Return: uint32_t(rssi)
  593. */
  594. static inline uint32_t
  595. hal_rx_msdu_start_get_rssi(uint8_t *buf)
  596. {
  597. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  598. struct rx_msdu_start *msdu_start =
  599. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  600. uint32_t rssi;
  601. rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start);
  602. return rssi;
  603. }
  604. #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \
  605. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  606. RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \
  607. RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \
  608. RX_MSDU_START_7_SW_PHY_META_DATA_LSB))
  609. #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \
  610. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  611. RX_MSDU_START_5_PKT_TYPE_OFFSET)), \
  612. RX_MSDU_START_5_PKT_TYPE_MASK, \
  613. RX_MSDU_START_5_PKT_TYPE_LSB))
  614. #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
  615. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  616. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
  617. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
  618. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
  619. #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
  620. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  621. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
  622. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
  623. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
  624. /*******************************************************************************
  625. * RX ERROR APIS
  626. ******************************************************************************/
  627. #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \
  628. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  629. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \
  630. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \
  631. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB))
  632. #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \
  633. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  634. RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \
  635. RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \
  636. RX_MPDU_END_1_TKIP_MIC_ERR_LSB))
  637. /*******************************************************************************
  638. * RX REO ERROR APIS
  639. ******************************************************************************/
  640. #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \
  641. (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \
  642. REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \
  643. REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB)
  644. #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \
  645. (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \
  646. REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \
  647. REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB)
  648. #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \
  649. (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \
  650. REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \
  651. REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB)
  652. /*
  653. * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to
  654. * REO entrance ring
  655. *
  656. * @ soc: HAL version of the SOC pointer
  657. * @ pa: Physical address of the MSDU Link Descriptor
  658. * @ cookie: SW cookie to get to the virtual address
  659. * @ error_enabled_reo_q: Argument to determine whether this needs to go
  660. * to the error enabled REO queue
  661. *
  662. * Return: void
  663. */
  664. static inline
  665. void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc,
  666. uint64_t pa,
  667. uint32_t cookie,
  668. bool error_enabled_reo_q)
  669. {
  670. /* TODO */
  671. }
  672. #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \
  673. (((*(((uint32_t *)wbm_desc) + \
  674. (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \
  675. WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \
  676. WBM_RELEASE_RING_4_FIRST_MSDU_LSB)
  677. #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \
  678. (((*(((uint32_t *)wbm_desc) + \
  679. (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \
  680. WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \
  681. WBM_RELEASE_RING_4_LAST_MSDU_LSB)
  682. #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \
  683. HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \
  684. wbm_desc)->released_buff_or_desc_addr_info)
  685. #define HAL_RX_WBM_BUF_ADDR_39_32_GET(wbm_desc) \
  686. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  687. (((struct wbm_release_ring *) \
  688. wbm_desc)->released_buff_or_desc_addr_info)))
  689. #define HAL_RX_WBM_BUF_ADDR_31_0_GET(wbm_desc) \
  690. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  691. (((struct wbm_release_ring *) \
  692. wbm_desc)->released_buff_or_desc_addr_info)))
  693. static inline
  694. uint32_t
  695. HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) {
  696. struct rx_msdu_start *rx_msdu_start;
  697. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  698. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  699. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  700. }
  701. /**
  702. * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured
  703. * humman readable format.
  704. * @ rx_attn: pointer the rx_attention TLV in pkt.
  705. * @ dbg_level: log level.
  706. *
  707. * Return: void
  708. */
  709. static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn,
  710. uint8_t dbg_level)
  711. {
  712. hal_verbose_debug("rx_attention tlv (1/2) - "
  713. "rxpcu_mpdu_filter_in_category: %x "
  714. "sw_frame_group_id: %x "
  715. "reserved_0: %x "
  716. "phy_ppdu_id: %x "
  717. "first_mpdu : %x "
  718. "reserved_1a: %x "
  719. "mcast_bcast: %x "
  720. "ast_index_not_found: %x "
  721. "ast_index_timeout: %x "
  722. "power_mgmt: %x "
  723. "non_qos: %x "
  724. "null_data: %x "
  725. "mgmt_type: %x "
  726. "ctrl_type: %x "
  727. "more_data: %x "
  728. "eosp: %x "
  729. "a_msdu_error: %x "
  730. "fragment_flag: %x "
  731. "order: %x "
  732. "cce_match: %x "
  733. "overflow_err: %x "
  734. "msdu_length_err: %x "
  735. "tcp_udp_chksum_fail: %x "
  736. "ip_chksum_fail: %x "
  737. "sa_idx_invalid: %x "
  738. "da_idx_invalid: %x "
  739. "reserved_1b: %x "
  740. "rx_in_tx_decrypt_byp: %x ",
  741. rx_attn->rxpcu_mpdu_filter_in_category,
  742. rx_attn->sw_frame_group_id,
  743. rx_attn->reserved_0,
  744. rx_attn->phy_ppdu_id,
  745. rx_attn->first_mpdu,
  746. rx_attn->reserved_1a,
  747. rx_attn->mcast_bcast,
  748. rx_attn->ast_index_not_found,
  749. rx_attn->ast_index_timeout,
  750. rx_attn->power_mgmt,
  751. rx_attn->non_qos,
  752. rx_attn->null_data,
  753. rx_attn->mgmt_type,
  754. rx_attn->ctrl_type,
  755. rx_attn->more_data,
  756. rx_attn->eosp,
  757. rx_attn->a_msdu_error,
  758. rx_attn->fragment_flag,
  759. rx_attn->order,
  760. rx_attn->cce_match,
  761. rx_attn->overflow_err,
  762. rx_attn->msdu_length_err,
  763. rx_attn->tcp_udp_chksum_fail,
  764. rx_attn->ip_chksum_fail,
  765. rx_attn->sa_idx_invalid,
  766. rx_attn->da_idx_invalid,
  767. rx_attn->reserved_1b,
  768. rx_attn->rx_in_tx_decrypt_byp);
  769. hal_verbose_debug("rx_attention tlv (2/2) - "
  770. "encrypt_required: %x "
  771. "directed: %x "
  772. "buffer_fragment: %x "
  773. "mpdu_length_err: %x "
  774. "tkip_mic_err: %x "
  775. "decrypt_err: %x "
  776. "unencrypted_frame_err: %x "
  777. "fcs_err: %x "
  778. "flow_idx_timeout: %x "
  779. "flow_idx_invalid: %x "
  780. "wifi_parser_error: %x "
  781. "amsdu_parser_error: %x "
  782. "sa_idx_timeout: %x "
  783. "da_idx_timeout: %x "
  784. "msdu_limit_error: %x "
  785. "da_is_valid: %x "
  786. "da_is_mcbc: %x "
  787. "sa_is_valid: %x "
  788. "decrypt_status_code: %x "
  789. "rx_bitmap_not_updated: %x "
  790. "reserved_2: %x "
  791. "msdu_done: %x ",
  792. rx_attn->encrypt_required,
  793. rx_attn->directed,
  794. rx_attn->buffer_fragment,
  795. rx_attn->mpdu_length_err,
  796. rx_attn->tkip_mic_err,
  797. rx_attn->decrypt_err,
  798. rx_attn->unencrypted_frame_err,
  799. rx_attn->fcs_err,
  800. rx_attn->flow_idx_timeout,
  801. rx_attn->flow_idx_invalid,
  802. rx_attn->wifi_parser_error,
  803. rx_attn->amsdu_parser_error,
  804. rx_attn->sa_idx_timeout,
  805. rx_attn->da_idx_timeout,
  806. rx_attn->msdu_limit_error,
  807. rx_attn->da_is_valid,
  808. rx_attn->da_is_mcbc,
  809. rx_attn->sa_is_valid,
  810. rx_attn->decrypt_status_code,
  811. rx_attn->rx_bitmap_not_updated,
  812. rx_attn->reserved_2,
  813. rx_attn->msdu_done);
  814. }
  815. /**
  816. * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured
  817. * human readable format.
  818. * @ mpdu_end: pointer the mpdu_end TLV in pkt.
  819. * @ dbg_level: log level.
  820. *
  821. * Return: void
  822. */
  823. static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end,
  824. uint8_t dbg_level)
  825. {
  826. hal_verbose_debug("rx_mpdu_end tlv - "
  827. "rxpcu_mpdu_filter_in_category: %x "
  828. "sw_frame_group_id: %x "
  829. "phy_ppdu_id: %x "
  830. "unsup_ktype_short_frame: %x "
  831. "rx_in_tx_decrypt_byp: %x "
  832. "overflow_err: %x "
  833. "mpdu_length_err: %x "
  834. "tkip_mic_err: %x "
  835. "decrypt_err: %x "
  836. "unencrypted_frame_err: %x "
  837. "pn_fields_contain_valid_info: %x "
  838. "fcs_err: %x "
  839. "msdu_length_err: %x "
  840. "rxdma0_destination_ring: %x "
  841. "rxdma1_destination_ring: %x "
  842. "decrypt_status_code: %x "
  843. "rx_bitmap_not_updated: %x ",
  844. mpdu_end->rxpcu_mpdu_filter_in_category,
  845. mpdu_end->sw_frame_group_id,
  846. mpdu_end->phy_ppdu_id,
  847. mpdu_end->unsup_ktype_short_frame,
  848. mpdu_end->rx_in_tx_decrypt_byp,
  849. mpdu_end->overflow_err,
  850. mpdu_end->mpdu_length_err,
  851. mpdu_end->tkip_mic_err,
  852. mpdu_end->decrypt_err,
  853. mpdu_end->unencrypted_frame_err,
  854. mpdu_end->pn_fields_contain_valid_info,
  855. mpdu_end->fcs_err,
  856. mpdu_end->msdu_length_err,
  857. mpdu_end->rxdma0_destination_ring,
  858. mpdu_end->rxdma1_destination_ring,
  859. mpdu_end->decrypt_status_code,
  860. mpdu_end->rx_bitmap_not_updated);
  861. }
  862. #ifdef NO_RX_PKT_HDR_TLV
  863. static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs,
  864. uint8_t dbg_level)
  865. {
  866. }
  867. #else
  868. /**
  869. * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format
  870. * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt.
  871. * @ dbg_level: log level.
  872. *
  873. * Return: void
  874. */
  875. static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs,
  876. uint8_t dbg_level)
  877. {
  878. struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
  879. hal_verbose_debug("\n---------------\nrx_pkt_hdr_tlv"
  880. "\n---------------\nphy_ppdu_id %d ",
  881. pkt_hdr_tlv->phy_ppdu_id);
  882. hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128);
  883. }
  884. #endif
  885. #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \
  886. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  887. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \
  888. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \
  889. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB))
  890. /**
  891. * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit
  892. *
  893. * @nbuf: Network buffer
  894. * Returns: rx more fragment bit
  895. */
  896. static inline
  897. uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf)
  898. {
  899. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  900. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  901. uint16_t frame_ctrl = 0;
  902. frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >>
  903. DOT11_FC1_MORE_FRAG_OFFSET;
  904. /* more fragment bit if at offset bit 4 */
  905. return frame_ctrl;
  906. }
  907. static inline
  908. void hal_rx_mpdu_desc_info_get_li(void *desc_addr,
  909. void *mpdu_desc_info_hdl)
  910. {
  911. struct reo_destination_ring *reo_dst_ring;
  912. struct hal_rx_mpdu_desc_info *mpdu_desc_info =
  913. (struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl;
  914. uint32_t *mpdu_info;
  915. reo_dst_ring = (struct reo_destination_ring *)desc_addr;
  916. mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details;
  917. mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info);
  918. mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info);
  919. mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info);
  920. mpdu_desc_info->peer_meta_data =
  921. HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info);
  922. mpdu_desc_info->bar_frame = HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info);
  923. }
  924. /**
  925. * hal_rx_attn_msdu_done_get_li() - Get msdi done flag from RX TLV
  926. * @buf: RX tlv address
  927. *
  928. * Return: msdu done flag
  929. */
  930. static inline uint32_t hal_rx_attn_msdu_done_get_li(uint8_t *buf)
  931. {
  932. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  933. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  934. uint32_t msdu_done;
  935. msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn);
  936. return msdu_done;
  937. }
  938. #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \
  939. (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  940. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  941. HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \
  942. HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  943. HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \
  944. HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  945. HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \
  946. HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr))
  947. /**
  948. * hal_rx_msdu_flags_get_li() - Get msdu flags from ring desc
  949. * @msdu_desc_info_hdl: msdu desc info handle
  950. *
  951. * Return: msdu flags
  952. */
  953. static inline
  954. uint32_t hal_rx_msdu_flags_get_li(rx_msdu_desc_info_t msdu_desc_info_hdl)
  955. {
  956. struct rx_msdu_desc_info *msdu_desc_info =
  957. (struct rx_msdu_desc_info *)msdu_desc_info_hdl;
  958. return HAL_RX_MSDU_FLAGS_GET(msdu_desc_info);
  959. }
  960. /*
  961. *hal_rx_msdu_desc_info_get_li: Gets the flags related to MSDU descriptor.
  962. *@desc_addr: REO ring descriptor addr
  963. *@msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor
  964. *
  965. * Specifically flags needed are: first_msdu_in_mpdu,
  966. * last_msdu_in_mpdu, msdu_continuation, sa_is_valid,
  967. * sa_idx_timeout, da_is_valid, da_idx_timeout, da_is_MCBC
  968. *
  969. *Return: void
  970. */
  971. static inline void
  972. hal_rx_msdu_desc_info_get_li(void *desc_addr,
  973. struct hal_rx_msdu_desc_info *msdu_desc_info)
  974. {
  975. struct reo_destination_ring *reo_dst_ring;
  976. uint32_t *msdu_info;
  977. reo_dst_ring = (struct reo_destination_ring *)desc_addr;
  978. msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details;
  979. msdu_desc_info->msdu_flags =
  980. hal_rx_msdu_flags_get_li((struct rx_msdu_desc_info *)msdu_info);
  981. msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info);
  982. }
  983. #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \
  984. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
  985. RX_MSDU_START_5_NSS_OFFSET)), \
  986. RX_MSDU_START_5_NSS_MASK, \
  987. RX_MSDU_START_5_NSS_LSB))
  988. #define HAL_RX_ATTN_MSDU_LEN_ERR_GET(_rx_attn) \
  989. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  990. RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET)), \
  991. RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK, \
  992. RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB))
  993. /**
  994. * hal_rx_attn_msdu_len_err_get_li(): Get msdu_len_err value from
  995. * rx attention tlvs
  996. * @buf: pointer to rx pkt tlvs hdr
  997. *
  998. * Return: msdu_len_err value
  999. */
  1000. static inline uint32_t
  1001. hal_rx_attn_msdu_len_err_get_li(uint8_t *buf)
  1002. {
  1003. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1004. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  1005. return HAL_RX_ATTN_MSDU_LEN_ERR_GET(rx_attn);
  1006. }
  1007. #endif /* _HAL_LI_RX_H_ */