hal_li_reo.c 41 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "qdf_module.h"
  20. #include "hal_li_hw_headers.h"
  21. #include "hal_reo.h"
  22. #include "hal_li_reo.h"
  23. #include "hal_li_api.h"
  24. uint32_t hal_get_reo_reg_base_offset_li(void)
  25. {
  26. return SEQ_WCSS_UMAC_REO_REG_OFFSET;
  27. }
  28. /**
  29. * hal_reo_qdesc_setup - Setup HW REO queue descriptor
  30. *
  31. * @hal_soc: Opaque HAL SOC handle
  32. * @ba_window_size: BlockAck window size
  33. * @start_seq: Starting sequence number
  34. * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
  35. * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
  36. * @tid: TID
  37. *
  38. */
  39. void hal_reo_qdesc_setup_li(hal_soc_handle_t hal_soc_hdl, int tid,
  40. uint32_t ba_window_size,
  41. uint32_t start_seq, void *hw_qdesc_vaddr,
  42. qdf_dma_addr_t hw_qdesc_paddr,
  43. int pn_type, uint8_t vdev_stats_id)
  44. {
  45. uint32_t *reo_queue_desc = (uint32_t *)hw_qdesc_vaddr;
  46. uint32_t *reo_queue_ext_desc;
  47. uint32_t reg_val;
  48. uint32_t pn_enable;
  49. uint32_t pn_size = 0;
  50. qdf_mem_zero(hw_qdesc_vaddr, sizeof(struct rx_reo_queue));
  51. hal_uniform_desc_hdr_setup(reo_queue_desc, HAL_DESC_REO_OWNED,
  52. HAL_REO_QUEUE_DESC);
  53. /* Fixed pattern in reserved bits for debugging */
  54. HAL_DESC_SET_FIELD(reo_queue_desc, UNIFORM_DESCRIPTOR_HEADER_0,
  55. RESERVED_0A, 0xDDBEEF);
  56. /* This a just a SW meta data and will be copied to REO destination
  57. * descriptors indicated by hardware.
  58. * TODO: Setting TID in this field. See if we should set something else.
  59. */
  60. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_1,
  61. RECEIVE_QUEUE_NUMBER, tid);
  62. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
  63. VLD, 1);
  64. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
  65. ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
  66. HAL_RX_LINK_DESC_CNTR);
  67. /*
  68. * Fields DISABLE_DUPLICATE_DETECTION and SOFT_REORDER_ENABLE will be 0
  69. */
  70. reg_val = TID_TO_WME_AC(tid);
  71. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, AC, reg_val);
  72. if (ba_window_size < 1)
  73. ba_window_size = 1;
  74. /* WAR to get 2k exception in Non BA case.
  75. * Setting window size to 2 to get 2k jump exception
  76. * when we receive aggregates in Non BA case
  77. */
  78. ba_window_size = hal_update_non_ba_win_size(tid, ba_window_size);
  79. /* Set RTY bit for non-BA case. Duplicate detection is currently not
  80. * done by HW in non-BA case if RTY bit is not set.
  81. * TODO: This is a temporary War and should be removed once HW fix is
  82. * made to check and discard duplicates even if RTY bit is not set.
  83. */
  84. if (ba_window_size == 1)
  85. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, RTY, 1);
  86. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, BA_WINDOW_SIZE,
  87. ba_window_size - 1);
  88. switch (pn_type) {
  89. case HAL_PN_WPA:
  90. pn_enable = 1;
  91. pn_size = PN_SIZE_48;
  92. break;
  93. case HAL_PN_WAPI_EVEN:
  94. case HAL_PN_WAPI_UNEVEN:
  95. pn_enable = 1;
  96. pn_size = PN_SIZE_128;
  97. break;
  98. default:
  99. pn_enable = 0;
  100. break;
  101. }
  102. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_CHECK_NEEDED,
  103. pn_enable);
  104. if (pn_type == HAL_PN_WAPI_EVEN)
  105. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
  106. PN_SHALL_BE_EVEN, 1);
  107. else if (pn_type == HAL_PN_WAPI_UNEVEN)
  108. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
  109. PN_SHALL_BE_UNEVEN, 1);
  110. /*
  111. * TODO: Need to check if PN handling in SW needs to be enabled
  112. * So far this is not a requirement
  113. */
  114. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_SIZE,
  115. pn_size);
  116. /* TODO: Check if RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG need to be set
  117. * based on BA window size and/or AMPDU capabilities
  118. */
  119. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
  120. IGNORE_AMPDU_FLAG, 1);
  121. if (start_seq <= 0xfff)
  122. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SSN,
  123. start_seq);
  124. /* TODO: SVLD should be set to 1 if a valid SSN is received in ADDBA,
  125. * but REO is not delivering packets if we set it to 1. Need to enable
  126. * this once the issue is resolved
  127. */
  128. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SVLD, 0);
  129. /* TODO: Check if we should set start PN for WAPI */
  130. /* TODO: HW queue descriptors are currently allocated for max BA
  131. * window size for all QOS TIDs so that same descriptor can be used
  132. * later when ADDBA request is recevied. This should be changed to
  133. * allocate HW queue descriptors based on BA window size being
  134. * negotiated (0 for non BA cases), and reallocate when BA window
  135. * size changes and also send WMI message to FW to change the REO
  136. * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
  137. */
  138. if (tid == HAL_NON_QOS_TID)
  139. return;
  140. reo_queue_ext_desc = (uint32_t *)
  141. (((struct rx_reo_queue *)reo_queue_desc) + 1);
  142. qdf_mem_zero(reo_queue_ext_desc, 3 *
  143. sizeof(struct rx_reo_queue_ext));
  144. /* Initialize first reo queue extension descriptor */
  145. hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
  146. HAL_DESC_REO_OWNED,
  147. HAL_REO_QUEUE_EXT_DESC);
  148. /* Fixed pattern in reserved bits for debugging */
  149. HAL_DESC_SET_FIELD(reo_queue_ext_desc,
  150. UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A,
  151. 0xADBEEF);
  152. /* Initialize second reo queue extension descriptor */
  153. reo_queue_ext_desc = (uint32_t *)
  154. (((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
  155. hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
  156. HAL_DESC_REO_OWNED,
  157. HAL_REO_QUEUE_EXT_DESC);
  158. /* Fixed pattern in reserved bits for debugging */
  159. HAL_DESC_SET_FIELD(reo_queue_ext_desc,
  160. UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A,
  161. 0xBDBEEF);
  162. /* Initialize third reo queue extension descriptor */
  163. reo_queue_ext_desc = (uint32_t *)
  164. (((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
  165. hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
  166. HAL_DESC_REO_OWNED,
  167. HAL_REO_QUEUE_EXT_DESC);
  168. /* Fixed pattern in reserved bits for debugging */
  169. HAL_DESC_SET_FIELD(reo_queue_ext_desc,
  170. UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A,
  171. 0xCDBEEF);
  172. }
  173. qdf_export_symbol(hal_reo_qdesc_setup_li);
  174. /**
  175. * hal_get_ba_aging_timeout_li - Get BA Aging timeout
  176. *
  177. * @hal_soc: Opaque HAL SOC handle
  178. * @ac: Access category
  179. * @value: window size to get
  180. */
  181. void hal_get_ba_aging_timeout_li(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
  182. uint32_t *value)
  183. {
  184. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  185. switch (ac) {
  186. case WME_AC_BE:
  187. *value = HAL_REG_READ(soc,
  188. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  189. SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
  190. break;
  191. case WME_AC_BK:
  192. *value = HAL_REG_READ(soc,
  193. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  194. SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
  195. break;
  196. case WME_AC_VI:
  197. *value = HAL_REG_READ(soc,
  198. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  199. SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
  200. break;
  201. case WME_AC_VO:
  202. *value = HAL_REG_READ(soc,
  203. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  204. SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
  205. break;
  206. default:
  207. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  208. "Invalid AC: %d\n", ac);
  209. }
  210. }
  211. qdf_export_symbol(hal_get_ba_aging_timeout_li);
  212. /**
  213. * hal_set_ba_aging_timeout_li - Set BA Aging timeout
  214. *
  215. * @hal_soc: Opaque HAL SOC handle
  216. * @ac: Access category
  217. * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice
  218. * @value: Input value to set
  219. */
  220. void hal_set_ba_aging_timeout_li(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
  221. uint32_t value)
  222. {
  223. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  224. switch (ac) {
  225. case WME_AC_BE:
  226. HAL_REG_WRITE(soc,
  227. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  228. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  229. value * 1000);
  230. break;
  231. case WME_AC_BK:
  232. HAL_REG_WRITE(soc,
  233. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  234. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  235. value * 1000);
  236. break;
  237. case WME_AC_VI:
  238. HAL_REG_WRITE(soc,
  239. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  240. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  241. value * 1000);
  242. break;
  243. case WME_AC_VO:
  244. HAL_REG_WRITE(soc,
  245. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  246. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  247. value * 1000);
  248. break;
  249. default:
  250. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  251. "Invalid AC: %d\n", ac);
  252. }
  253. }
  254. qdf_export_symbol(hal_set_ba_aging_timeout_li);
  255. static inline void
  256. hal_reo_cmd_set_descr_addr_li(uint32_t *reo_desc, enum hal_reo_cmd_type type,
  257. uint32_t paddr_lo, uint8_t paddr_hi)
  258. {
  259. switch (type) {
  260. case CMD_GET_QUEUE_STATS:
  261. HAL_DESC_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS_1,
  262. RX_REO_QUEUE_DESC_ADDR_31_0, paddr_lo);
  263. HAL_DESC_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS_2,
  264. RX_REO_QUEUE_DESC_ADDR_39_32, paddr_hi);
  265. break;
  266. case CMD_FLUSH_QUEUE:
  267. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_1,
  268. FLUSH_DESC_ADDR_31_0, paddr_lo);
  269. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_2,
  270. FLUSH_DESC_ADDR_39_32, paddr_hi);
  271. break;
  272. case CMD_FLUSH_CACHE:
  273. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_1,
  274. FLUSH_ADDR_31_0, paddr_lo);
  275. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
  276. FLUSH_ADDR_39_32, paddr_hi);
  277. break;
  278. case CMD_UPDATE_RX_REO_QUEUE:
  279. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_1,
  280. RX_REO_QUEUE_DESC_ADDR_31_0, paddr_lo);
  281. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  282. RX_REO_QUEUE_DESC_ADDR_39_32, paddr_hi);
  283. break;
  284. default:
  285. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  286. "%s: Invalid REO command type", __func__);
  287. break;
  288. }
  289. }
  290. static inline int
  291. hal_reo_cmd_queue_stats_li(hal_ring_handle_t hal_ring_hdl,
  292. hal_soc_handle_t hal_soc_hdl,
  293. struct hal_reo_cmd_params *cmd)
  294. {
  295. uint32_t *reo_desc, val;
  296. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  297. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  298. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  299. if (!reo_desc) {
  300. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  301. "%s: Out of cmd ring entries", __func__);
  302. hal_srng_access_end(hal_soc, hal_ring_hdl);
  303. return -EBUSY;
  304. }
  305. HAL_SET_TLV_HDR(reo_desc, WIFIREO_GET_QUEUE_STATS_E,
  306. sizeof(struct reo_get_queue_stats));
  307. /*
  308. * Offsets of descriptor fields defined in HW headers start from
  309. * the field after TLV header
  310. */
  311. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  312. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  313. sizeof(struct reo_get_queue_stats) -
  314. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  315. HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
  316. REO_STATUS_REQUIRED, cmd->std.need_status);
  317. hal_reo_cmd_set_descr_addr_li(reo_desc, CMD_GET_QUEUE_STATS,
  318. cmd->std.addr_lo,
  319. cmd->std.addr_hi);
  320. HAL_DESC_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS_2, CLEAR_STATS,
  321. cmd->u.stats_params.clear);
  322. if (hif_pm_runtime_get(hal_soc->hif_handle,
  323. RTPM_ID_HAL_REO_CMD, false) == 0) {
  324. hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
  325. hif_pm_runtime_put(hal_soc->hif_handle,
  326. RTPM_ID_HAL_REO_CMD);
  327. } else {
  328. hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
  329. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  330. hal_srng_inc_flush_cnt(hal_ring_hdl);
  331. }
  332. val = reo_desc[CMD_HEADER_DW_OFFSET];
  333. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
  334. val);
  335. }
  336. static inline int
  337. hal_reo_cmd_flush_queue_li(hal_ring_handle_t hal_ring_hdl,
  338. hal_soc_handle_t hal_soc_hdl,
  339. struct hal_reo_cmd_params *cmd)
  340. {
  341. uint32_t *reo_desc, val;
  342. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  343. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  344. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  345. if (!reo_desc) {
  346. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  347. "%s: Out of cmd ring entries", __func__);
  348. hal_srng_access_end(hal_soc, hal_ring_hdl);
  349. return -EBUSY;
  350. }
  351. HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_QUEUE_E,
  352. sizeof(struct reo_flush_queue));
  353. /*
  354. * Offsets of descriptor fields defined in HW headers start from
  355. * the field after TLV header
  356. */
  357. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  358. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  359. sizeof(struct reo_flush_queue) -
  360. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  361. HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
  362. REO_STATUS_REQUIRED, cmd->std.need_status);
  363. hal_reo_cmd_set_descr_addr_li(reo_desc, CMD_FLUSH_QUEUE,
  364. cmd->std.addr_lo, cmd->std.addr_hi);
  365. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_2,
  366. BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH,
  367. cmd->u.fl_queue_params.block_use_after_flush);
  368. if (cmd->u.fl_queue_params.block_use_after_flush) {
  369. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_2,
  370. BLOCK_RESOURCE_INDEX,
  371. cmd->u.fl_queue_params.index);
  372. }
  373. hal_srng_access_end(hal_soc, hal_ring_hdl);
  374. val = reo_desc[CMD_HEADER_DW_OFFSET];
  375. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
  376. val);
  377. }
  378. static inline int
  379. hal_reo_cmd_flush_cache_li(hal_ring_handle_t hal_ring_hdl,
  380. hal_soc_handle_t hal_soc_hdl,
  381. struct hal_reo_cmd_params *cmd)
  382. {
  383. uint32_t *reo_desc, val;
  384. struct hal_reo_cmd_flush_cache_params *cp;
  385. uint8_t index = 0;
  386. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  387. cp = &cmd->u.fl_cache_params;
  388. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  389. /* We need a cache block resource for this operation, and REO HW has
  390. * only 4 such blocking resources. These resources are managed using
  391. * reo_res_bitmap, and we return failure if none is available.
  392. */
  393. if (cp->block_use_after_flush) {
  394. index = hal_find_zero_bit(hal_soc->reo_res_bitmap);
  395. if (index > 3) {
  396. qdf_print("No blocking resource available!");
  397. hal_srng_access_end(hal_soc, hal_ring_hdl);
  398. return -EBUSY;
  399. }
  400. hal_soc->index = index;
  401. }
  402. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  403. if (!reo_desc) {
  404. hal_srng_access_end(hal_soc, hal_ring_hdl);
  405. hal_srng_dump(hal_ring_handle_to_hal_srng(hal_ring_hdl));
  406. return -EBUSY;
  407. }
  408. HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_CACHE_E,
  409. sizeof(struct reo_flush_cache));
  410. /*
  411. * Offsets of descriptor fields defined in HW headers start from
  412. * the field after TLV header
  413. */
  414. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  415. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  416. sizeof(struct reo_flush_cache) -
  417. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  418. HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
  419. REO_STATUS_REQUIRED, cmd->std.need_status);
  420. hal_reo_cmd_set_descr_addr_li(reo_desc, CMD_FLUSH_CACHE,
  421. cmd->std.addr_lo, cmd->std.addr_hi);
  422. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
  423. FORWARD_ALL_MPDUS_IN_QUEUE, cp->fwd_mpdus_in_queue);
  424. /* set it to 0 for now */
  425. cp->rel_block_index = 0;
  426. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
  427. RELEASE_CACHE_BLOCK_INDEX, cp->rel_block_index);
  428. if (cp->block_use_after_flush) {
  429. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
  430. CACHE_BLOCK_RESOURCE_INDEX, index);
  431. }
  432. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
  433. FLUSH_WITHOUT_INVALIDATE, cp->flush_no_inval);
  434. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
  435. BLOCK_CACHE_USAGE_AFTER_FLUSH,
  436. cp->block_use_after_flush);
  437. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2, FLUSH_ENTIRE_CACHE,
  438. cp->flush_entire_cache);
  439. if (hif_pm_runtime_get(hal_soc->hif_handle,
  440. RTPM_ID_HAL_REO_CMD, false) == 0) {
  441. hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
  442. hif_pm_runtime_put(hal_soc->hif_handle,
  443. RTPM_ID_HAL_REO_CMD);
  444. } else {
  445. hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
  446. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  447. hal_srng_inc_flush_cnt(hal_ring_hdl);
  448. }
  449. val = reo_desc[CMD_HEADER_DW_OFFSET];
  450. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
  451. val);
  452. }
  453. static inline int
  454. hal_reo_cmd_unblock_cache_li(hal_ring_handle_t hal_ring_hdl,
  455. hal_soc_handle_t hal_soc_hdl,
  456. struct hal_reo_cmd_params *cmd)
  457. {
  458. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  459. uint32_t *reo_desc, val;
  460. uint8_t index = 0;
  461. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  462. if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) {
  463. index = hal_find_one_bit(hal_soc->reo_res_bitmap);
  464. if (index > 3) {
  465. hal_srng_access_end(hal_soc, hal_ring_hdl);
  466. qdf_print("No blocking resource to unblock!");
  467. return -EBUSY;
  468. }
  469. }
  470. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  471. if (!reo_desc) {
  472. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  473. "%s: Out of cmd ring entries", __func__);
  474. hal_srng_access_end(hal_soc, hal_ring_hdl);
  475. return -EBUSY;
  476. }
  477. HAL_SET_TLV_HDR(reo_desc, WIFIREO_UNBLOCK_CACHE_E,
  478. sizeof(struct reo_unblock_cache));
  479. /*
  480. * Offsets of descriptor fields defined in HW headers start from
  481. * the field after TLV header
  482. */
  483. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  484. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  485. sizeof(struct reo_unblock_cache) -
  486. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  487. HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
  488. REO_STATUS_REQUIRED, cmd->std.need_status);
  489. HAL_DESC_SET_FIELD(reo_desc, REO_UNBLOCK_CACHE_1,
  490. UNBLOCK_TYPE, cmd->u.unblk_cache_params.type);
  491. if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) {
  492. HAL_DESC_SET_FIELD(reo_desc, REO_UNBLOCK_CACHE_1,
  493. CACHE_BLOCK_RESOURCE_INDEX,
  494. cmd->u.unblk_cache_params.index);
  495. }
  496. hal_srng_access_end(hal_soc, hal_ring_hdl);
  497. val = reo_desc[CMD_HEADER_DW_OFFSET];
  498. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
  499. val);
  500. }
  501. static inline int
  502. hal_reo_cmd_flush_timeout_list_li(hal_ring_handle_t hal_ring_hdl,
  503. hal_soc_handle_t hal_soc_hdl,
  504. struct hal_reo_cmd_params *cmd)
  505. {
  506. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  507. uint32_t *reo_desc, val;
  508. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  509. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  510. if (!reo_desc) {
  511. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  512. "%s: Out of cmd ring entries", __func__);
  513. hal_srng_access_end(hal_soc, hal_ring_hdl);
  514. return -EBUSY;
  515. }
  516. HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_TIMEOUT_LIST_E,
  517. sizeof(struct reo_flush_timeout_list));
  518. /*
  519. * Offsets of descriptor fields defined in HW headers start from
  520. * the field after TLV header
  521. */
  522. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  523. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  524. sizeof(struct reo_flush_timeout_list) -
  525. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  526. HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
  527. REO_STATUS_REQUIRED, cmd->std.need_status);
  528. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST_1, AC_TIMOUT_LIST,
  529. cmd->u.fl_tim_list_params.ac_list);
  530. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST_2,
  531. MINIMUM_RELEASE_DESC_COUNT,
  532. cmd->u.fl_tim_list_params.min_rel_desc);
  533. HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST_2,
  534. MINIMUM_FORWARD_BUF_COUNT,
  535. cmd->u.fl_tim_list_params.min_fwd_buf);
  536. hal_srng_access_end(hal_soc, hal_ring_hdl);
  537. val = reo_desc[CMD_HEADER_DW_OFFSET];
  538. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
  539. val);
  540. }
  541. static inline int
  542. hal_reo_cmd_update_rx_queue_li(hal_ring_handle_t hal_ring_hdl,
  543. hal_soc_handle_t hal_soc_hdl,
  544. struct hal_reo_cmd_params *cmd)
  545. {
  546. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  547. uint32_t *reo_desc, val;
  548. struct hal_reo_cmd_update_queue_params *p;
  549. p = &cmd->u.upd_queue_params;
  550. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  551. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  552. if (!reo_desc) {
  553. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  554. "%s: Out of cmd ring entries", __func__);
  555. hal_srng_access_end(hal_soc, hal_ring_hdl);
  556. return -EBUSY;
  557. }
  558. HAL_SET_TLV_HDR(reo_desc, WIFIREO_UPDATE_RX_REO_QUEUE_E,
  559. sizeof(struct reo_update_rx_reo_queue));
  560. /*
  561. * Offsets of descriptor fields defined in HW headers start from
  562. * the field after TLV header
  563. */
  564. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  565. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  566. sizeof(struct reo_update_rx_reo_queue) -
  567. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  568. HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
  569. REO_STATUS_REQUIRED, cmd->std.need_status);
  570. hal_reo_cmd_set_descr_addr_li(reo_desc, CMD_UPDATE_RX_REO_QUEUE,
  571. cmd->std.addr_lo, cmd->std.addr_hi);
  572. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  573. UPDATE_RECEIVE_QUEUE_NUMBER, p->update_rx_queue_num);
  574. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, UPDATE_VLD,
  575. p->update_vld);
  576. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  577. UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
  578. p->update_assoc_link_desc);
  579. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  580. UPDATE_DISABLE_DUPLICATE_DETECTION,
  581. p->update_disable_dup_detect);
  582. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  583. UPDATE_DISABLE_DUPLICATE_DETECTION,
  584. p->update_disable_dup_detect);
  585. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  586. UPDATE_SOFT_REORDER_ENABLE,
  587. p->update_soft_reorder_enab);
  588. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  589. UPDATE_AC, p->update_ac);
  590. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  591. UPDATE_BAR, p->update_bar);
  592. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  593. UPDATE_BAR, p->update_bar);
  594. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  595. UPDATE_RTY, p->update_rty);
  596. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  597. UPDATE_CHK_2K_MODE, p->update_chk_2k_mode);
  598. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  599. UPDATE_OOR_MODE, p->update_oor_mode);
  600. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  601. UPDATE_BA_WINDOW_SIZE, p->update_ba_window_size);
  602. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  603. UPDATE_PN_CHECK_NEEDED, p->update_pn_check_needed);
  604. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  605. UPDATE_PN_SHALL_BE_EVEN, p->update_pn_even);
  606. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  607. UPDATE_PN_SHALL_BE_UNEVEN, p->update_pn_uneven);
  608. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  609. UPDATE_PN_HANDLING_ENABLE, p->update_pn_hand_enab);
  610. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  611. UPDATE_PN_SIZE, p->update_pn_size);
  612. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  613. UPDATE_IGNORE_AMPDU_FLAG, p->update_ignore_ampdu);
  614. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  615. UPDATE_SVLD, p->update_svld);
  616. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  617. UPDATE_SSN, p->update_ssn);
  618. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  619. UPDATE_SEQ_2K_ERROR_DETECTED_FLAG,
  620. p->update_seq_2k_err_detect);
  621. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  622. UPDATE_PN_VALID, p->update_pn_valid);
  623. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
  624. UPDATE_PN, p->update_pn);
  625. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  626. RECEIVE_QUEUE_NUMBER, p->rx_queue_num);
  627. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  628. VLD, p->vld);
  629. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  630. ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
  631. p->assoc_link_desc);
  632. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  633. DISABLE_DUPLICATE_DETECTION, p->disable_dup_detect);
  634. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  635. SOFT_REORDER_ENABLE, p->soft_reorder_enab);
  636. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, AC, p->ac);
  637. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  638. BAR, p->bar);
  639. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  640. CHK_2K_MODE, p->chk_2k_mode);
  641. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  642. RTY, p->rty);
  643. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  644. OOR_MODE, p->oor_mode);
  645. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  646. PN_CHECK_NEEDED, p->pn_check_needed);
  647. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  648. PN_SHALL_BE_EVEN, p->pn_even);
  649. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  650. PN_SHALL_BE_UNEVEN, p->pn_uneven);
  651. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  652. PN_HANDLING_ENABLE, p->pn_hand_enab);
  653. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
  654. IGNORE_AMPDU_FLAG, p->ignore_ampdu);
  655. if (p->ba_window_size < 1)
  656. p->ba_window_size = 1;
  657. /*
  658. * WAR to get 2k exception in Non BA case.
  659. * Setting window size to 2 to get 2k jump exception
  660. * when we receive aggregates in Non BA case
  661. */
  662. if (p->ba_window_size == 1)
  663. p->ba_window_size++;
  664. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
  665. BA_WINDOW_SIZE, p->ba_window_size - 1);
  666. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
  667. PN_SIZE, p->pn_size);
  668. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
  669. SVLD, p->svld);
  670. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
  671. SSN, p->ssn);
  672. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
  673. SEQ_2K_ERROR_DETECTED_FLAG, p->seq_2k_err_detect);
  674. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
  675. PN_ERROR_DETECTED_FLAG, p->pn_err_detect);
  676. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_5,
  677. PN_31_0, p->pn_31_0);
  678. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_6,
  679. PN_63_32, p->pn_63_32);
  680. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_7,
  681. PN_95_64, p->pn_95_64);
  682. HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_8,
  683. PN_127_96, p->pn_127_96);
  684. if (hif_pm_runtime_get(hal_soc->hif_handle,
  685. RTPM_ID_HAL_REO_CMD, false) == 0) {
  686. hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
  687. hif_pm_runtime_put(hal_soc->hif_handle,
  688. RTPM_ID_HAL_REO_CMD);
  689. } else {
  690. hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
  691. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  692. hal_srng_inc_flush_cnt(hal_ring_hdl);
  693. }
  694. val = reo_desc[CMD_HEADER_DW_OFFSET];
  695. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
  696. val);
  697. }
  698. int hal_reo_send_cmd_li(hal_soc_handle_t hal_soc_hdl,
  699. hal_ring_handle_t hal_ring_hdl,
  700. enum hal_reo_cmd_type cmd,
  701. void *params)
  702. {
  703. struct hal_reo_cmd_params *cmd_params =
  704. (struct hal_reo_cmd_params *)params;
  705. int num = 0;
  706. switch (cmd) {
  707. case CMD_GET_QUEUE_STATS:
  708. num = hal_reo_cmd_queue_stats_li(hal_ring_hdl,
  709. hal_soc_hdl, cmd_params);
  710. break;
  711. case CMD_FLUSH_QUEUE:
  712. num = hal_reo_cmd_flush_queue_li(hal_ring_hdl,
  713. hal_soc_hdl, cmd_params);
  714. break;
  715. case CMD_FLUSH_CACHE:
  716. num = hal_reo_cmd_flush_cache_li(hal_ring_hdl,
  717. hal_soc_hdl, cmd_params);
  718. break;
  719. case CMD_UNBLOCK_CACHE:
  720. num = hal_reo_cmd_unblock_cache_li(hal_ring_hdl,
  721. hal_soc_hdl, cmd_params);
  722. break;
  723. case CMD_FLUSH_TIMEOUT_LIST:
  724. num = hal_reo_cmd_flush_timeout_list_li(hal_ring_hdl,
  725. hal_soc_hdl,
  726. cmd_params);
  727. break;
  728. case CMD_UPDATE_RX_REO_QUEUE:
  729. num = hal_reo_cmd_update_rx_queue_li(hal_ring_hdl,
  730. hal_soc_hdl, cmd_params);
  731. break;
  732. default:
  733. hal_err("Invalid REO command type: %d", cmd);
  734. return -EINVAL;
  735. };
  736. return num;
  737. }
  738. void
  739. hal_reo_queue_stats_status_li(hal_ring_desc_t ring_desc,
  740. void *st_handle,
  741. hal_soc_handle_t hal_soc_hdl)
  742. {
  743. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  744. struct hal_reo_queue_status *st =
  745. (struct hal_reo_queue_status *)st_handle;
  746. uint32_t *reo_desc = (uint32_t *)ring_desc;
  747. uint32_t val;
  748. /*
  749. * Offsets of descriptor fields defined in HW headers start
  750. * from the field after TLV header
  751. */
  752. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  753. /* header */
  754. hal_reo_status_get_header(ring_desc, HAL_REO_QUEUE_STATS_STATUS_TLV,
  755. &(st->header), hal_soc);
  756. /* SSN */
  757. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_2, SSN)];
  758. st->ssn = HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_2, SSN, val);
  759. /* current index */
  760. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_2,
  761. CURRENT_INDEX)];
  762. st->curr_idx =
  763. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_2,
  764. CURRENT_INDEX, val);
  765. /* PN bits */
  766. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_3,
  767. PN_31_0)];
  768. st->pn_31_0 =
  769. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_3,
  770. PN_31_0, val);
  771. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_4,
  772. PN_63_32)];
  773. st->pn_63_32 =
  774. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_4,
  775. PN_63_32, val);
  776. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_5,
  777. PN_95_64)];
  778. st->pn_95_64 =
  779. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_5,
  780. PN_95_64, val);
  781. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_6,
  782. PN_127_96)];
  783. st->pn_127_96 =
  784. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_6,
  785. PN_127_96, val);
  786. /* timestamps */
  787. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_7,
  788. LAST_RX_ENQUEUE_TIMESTAMP)];
  789. st->last_rx_enq_tstamp =
  790. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_7,
  791. LAST_RX_ENQUEUE_TIMESTAMP, val);
  792. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_8,
  793. LAST_RX_DEQUEUE_TIMESTAMP)];
  794. st->last_rx_deq_tstamp =
  795. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_8,
  796. LAST_RX_DEQUEUE_TIMESTAMP, val);
  797. /* rx bitmap */
  798. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_9,
  799. RX_BITMAP_31_0)];
  800. st->rx_bitmap_31_0 =
  801. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_9,
  802. RX_BITMAP_31_0, val);
  803. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_10,
  804. RX_BITMAP_63_32)];
  805. st->rx_bitmap_63_32 =
  806. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_10,
  807. RX_BITMAP_63_32, val);
  808. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_11,
  809. RX_BITMAP_95_64)];
  810. st->rx_bitmap_95_64 =
  811. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_11,
  812. RX_BITMAP_95_64, val);
  813. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_12,
  814. RX_BITMAP_127_96)];
  815. st->rx_bitmap_127_96 =
  816. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_12,
  817. RX_BITMAP_127_96, val);
  818. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_13,
  819. RX_BITMAP_159_128)];
  820. st->rx_bitmap_159_128 =
  821. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_13,
  822. RX_BITMAP_159_128, val);
  823. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_14,
  824. RX_BITMAP_191_160)];
  825. st->rx_bitmap_191_160 =
  826. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_14,
  827. RX_BITMAP_191_160, val);
  828. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_15,
  829. RX_BITMAP_223_192)];
  830. st->rx_bitmap_223_192 =
  831. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_15,
  832. RX_BITMAP_223_192, val);
  833. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_16,
  834. RX_BITMAP_255_224)];
  835. st->rx_bitmap_255_224 =
  836. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_16,
  837. RX_BITMAP_255_224, val);
  838. /* various counts */
  839. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_17,
  840. CURRENT_MPDU_COUNT)];
  841. st->curr_mpdu_cnt =
  842. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_17,
  843. CURRENT_MPDU_COUNT, val);
  844. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_17,
  845. CURRENT_MSDU_COUNT)];
  846. st->curr_msdu_cnt =
  847. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_17,
  848. CURRENT_MSDU_COUNT, val);
  849. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_18,
  850. TIMEOUT_COUNT)];
  851. st->fwd_timeout_cnt =
  852. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_18,
  853. TIMEOUT_COUNT, val);
  854. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_18,
  855. FORWARD_DUE_TO_BAR_COUNT)];
  856. st->fwd_bar_cnt =
  857. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_18,
  858. FORWARD_DUE_TO_BAR_COUNT, val);
  859. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_18,
  860. DUPLICATE_COUNT)];
  861. st->dup_cnt =
  862. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_18,
  863. DUPLICATE_COUNT, val);
  864. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_19,
  865. FRAMES_IN_ORDER_COUNT)];
  866. st->frms_in_order_cnt =
  867. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_19,
  868. FRAMES_IN_ORDER_COUNT, val);
  869. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_19,
  870. BAR_RECEIVED_COUNT)];
  871. st->bar_rcvd_cnt =
  872. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_19,
  873. BAR_RECEIVED_COUNT, val);
  874. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_20,
  875. MPDU_FRAMES_PROCESSED_COUNT)];
  876. st->mpdu_frms_cnt =
  877. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_20,
  878. MPDU_FRAMES_PROCESSED_COUNT, val);
  879. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_21,
  880. MSDU_FRAMES_PROCESSED_COUNT)];
  881. st->msdu_frms_cnt =
  882. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_21,
  883. MSDU_FRAMES_PROCESSED_COUNT, val);
  884. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_22,
  885. TOTAL_PROCESSED_BYTE_COUNT)];
  886. st->total_cnt =
  887. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_22,
  888. TOTAL_PROCESSED_BYTE_COUNT, val);
  889. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_23,
  890. LATE_RECEIVE_MPDU_COUNT)];
  891. st->late_recv_mpdu_cnt =
  892. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_23,
  893. LATE_RECEIVE_MPDU_COUNT, val);
  894. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_23,
  895. WINDOW_JUMP_2K)];
  896. st->win_jump_2k =
  897. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_23,
  898. WINDOW_JUMP_2K, val);
  899. val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_23,
  900. HOLE_COUNT)];
  901. st->hole_cnt =
  902. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_23,
  903. HOLE_COUNT, val);
  904. }
  905. void
  906. hal_reo_flush_queue_status_li(hal_ring_desc_t ring_desc,
  907. void *st_handle,
  908. hal_soc_handle_t hal_soc_hdl)
  909. {
  910. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  911. struct hal_reo_flush_queue_status *st =
  912. (struct hal_reo_flush_queue_status *)st_handle;
  913. uint32_t *reo_desc = (uint32_t *)ring_desc;
  914. uint32_t val;
  915. /*
  916. * Offsets of descriptor fields defined in HW headers start
  917. * from the field after TLV header
  918. */
  919. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  920. /* header */
  921. hal_reo_status_get_header(ring_desc, HAL_REO_FLUSH_QUEUE_STATUS_TLV,
  922. &(st->header), hal_soc);
  923. /* error bit */
  924. val = reo_desc[HAL_OFFSET(REO_FLUSH_QUEUE_STATUS_2,
  925. ERROR_DETECTED)];
  926. st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS_2, ERROR_DETECTED,
  927. val);
  928. }
  929. void
  930. hal_reo_flush_cache_status_li(hal_ring_desc_t ring_desc,
  931. void *st_handle,
  932. hal_soc_handle_t hal_soc_hdl)
  933. {
  934. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  935. struct hal_reo_flush_cache_status *st =
  936. (struct hal_reo_flush_cache_status *)st_handle;
  937. uint32_t *reo_desc = (uint32_t *)ring_desc;
  938. uint32_t val;
  939. /*
  940. * Offsets of descriptor fields defined in HW headers start
  941. * from the field after TLV header
  942. */
  943. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  944. /* header */
  945. hal_reo_status_get_header(ring_desc, HAL_REO_FLUSH_CACHE_STATUS_TLV,
  946. &(st->header), hal_soc);
  947. /* error bit */
  948. val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
  949. ERROR_DETECTED)];
  950. st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS_2, ERROR_DETECTED,
  951. val);
  952. /* block error */
  953. val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
  954. BLOCK_ERROR_DETAILS)];
  955. st->block_error = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2,
  956. BLOCK_ERROR_DETAILS,
  957. val);
  958. if (!st->block_error)
  959. qdf_set_bit(hal_soc->index,
  960. (unsigned long *)&hal_soc->reo_res_bitmap);
  961. /* cache flush status */
  962. val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
  963. CACHE_CONTROLLER_FLUSH_STATUS_HIT)];
  964. st->cache_flush_status = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2,
  965. CACHE_CONTROLLER_FLUSH_STATUS_HIT,
  966. val);
  967. /* cache flush descriptor type */
  968. val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
  969. CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE)];
  970. st->cache_flush_status_desc_type =
  971. HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2,
  972. CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE,
  973. val);
  974. /* cache flush count */
  975. val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
  976. CACHE_CONTROLLER_FLUSH_COUNT)];
  977. st->cache_flush_cnt =
  978. HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2,
  979. CACHE_CONTROLLER_FLUSH_COUNT,
  980. val);
  981. }
  982. void
  983. hal_reo_unblock_cache_status_li(hal_ring_desc_t ring_desc,
  984. hal_soc_handle_t hal_soc_hdl,
  985. void *st_handle)
  986. {
  987. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  988. struct hal_reo_unblk_cache_status *st =
  989. (struct hal_reo_unblk_cache_status *)st_handle;
  990. uint32_t *reo_desc = (uint32_t *)ring_desc;
  991. uint32_t val;
  992. /*
  993. * Offsets of descriptor fields defined in HW headers start
  994. * from the field after TLV header
  995. */
  996. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  997. /* header */
  998. hal_reo_status_get_header(ring_desc, HAL_REO_UNBLK_CACHE_STATUS_TLV,
  999. &st->header, hal_soc);
  1000. /* error bit */
  1001. val = reo_desc[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_2,
  1002. ERROR_DETECTED)];
  1003. st->error = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS_2,
  1004. ERROR_DETECTED,
  1005. val);
  1006. /* unblock type */
  1007. val = reo_desc[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_2,
  1008. UNBLOCK_TYPE)];
  1009. st->unblock_type = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS_2,
  1010. UNBLOCK_TYPE,
  1011. val);
  1012. if (!st->error && (st->unblock_type == UNBLOCK_RES_INDEX))
  1013. qdf_clear_bit(hal_soc->index,
  1014. (unsigned long *)&hal_soc->reo_res_bitmap);
  1015. }
  1016. void hal_reo_flush_timeout_list_status_li(hal_ring_desc_t ring_desc,
  1017. void *st_handle,
  1018. hal_soc_handle_t hal_soc_hdl)
  1019. {
  1020. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1021. struct hal_reo_flush_timeout_list_status *st =
  1022. (struct hal_reo_flush_timeout_list_status *)st_handle;
  1023. uint32_t *reo_desc = (uint32_t *)ring_desc;
  1024. uint32_t val;
  1025. /*
  1026. * Offsets of descriptor fields defined in HW headers start
  1027. * from the field after TLV header
  1028. */
  1029. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  1030. /* header */
  1031. hal_reo_status_get_header(ring_desc, HAL_REO_TIMOUT_LIST_STATUS_TLV,
  1032. &(st->header), hal_soc);
  1033. /* error bit */
  1034. val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_2,
  1035. ERROR_DETECTED)];
  1036. st->error = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_2,
  1037. ERROR_DETECTED,
  1038. val);
  1039. /* list empty */
  1040. val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_2,
  1041. TIMOUT_LIST_EMPTY)];
  1042. st->list_empty = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_2,
  1043. TIMOUT_LIST_EMPTY,
  1044. val);
  1045. /* release descriptor count */
  1046. val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_3,
  1047. RELEASE_DESC_COUNT)];
  1048. st->rel_desc_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_3,
  1049. RELEASE_DESC_COUNT,
  1050. val);
  1051. /* forward buf count */
  1052. val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_3,
  1053. FORWARD_BUF_COUNT)];
  1054. st->fwd_buf_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_3,
  1055. FORWARD_BUF_COUNT,
  1056. val);
  1057. }
  1058. void hal_reo_desc_thres_reached_status_li(hal_ring_desc_t ring_desc,
  1059. void *st_handle,
  1060. hal_soc_handle_t hal_soc_hdl)
  1061. {
  1062. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1063. struct hal_reo_desc_thres_reached_status *st =
  1064. (struct hal_reo_desc_thres_reached_status *)st_handle;
  1065. uint32_t *reo_desc = (uint32_t *)ring_desc;
  1066. uint32_t val;
  1067. /*
  1068. * Offsets of descriptor fields defined in HW headers start
  1069. * from the field after TLV header
  1070. */
  1071. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  1072. /* header */
  1073. hal_reo_status_get_header(ring_desc,
  1074. HAL_REO_DESC_THRES_STATUS_TLV,
  1075. &(st->header), hal_soc);
  1076. /* threshold index */
  1077. val = reo_desc[HAL_OFFSET_DW(
  1078. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2,
  1079. THRESHOLD_INDEX)];
  1080. st->thres_index = HAL_GET_FIELD(
  1081. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2,
  1082. THRESHOLD_INDEX,
  1083. val);
  1084. /* link desc counters */
  1085. val = reo_desc[HAL_OFFSET_DW(
  1086. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3,
  1087. LINK_DESCRIPTOR_COUNTER0)];
  1088. st->link_desc_counter0 = HAL_GET_FIELD(
  1089. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3,
  1090. LINK_DESCRIPTOR_COUNTER0,
  1091. val);
  1092. val = reo_desc[HAL_OFFSET_DW(
  1093. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4,
  1094. LINK_DESCRIPTOR_COUNTER1)];
  1095. st->link_desc_counter1 = HAL_GET_FIELD(
  1096. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4,
  1097. LINK_DESCRIPTOR_COUNTER1,
  1098. val);
  1099. val = reo_desc[HAL_OFFSET_DW(
  1100. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5,
  1101. LINK_DESCRIPTOR_COUNTER2)];
  1102. st->link_desc_counter2 = HAL_GET_FIELD(
  1103. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5,
  1104. LINK_DESCRIPTOR_COUNTER2,
  1105. val);
  1106. val = reo_desc[HAL_OFFSET_DW(
  1107. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6,
  1108. LINK_DESCRIPTOR_COUNTER_SUM)];
  1109. st->link_desc_counter_sum = HAL_GET_FIELD(
  1110. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6,
  1111. LINK_DESCRIPTOR_COUNTER_SUM,
  1112. val);
  1113. }
  1114. void
  1115. hal_reo_rx_update_queue_status_li(hal_ring_desc_t ring_desc,
  1116. void *st_handle,
  1117. hal_soc_handle_t hal_soc_hdl)
  1118. {
  1119. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1120. struct hal_reo_update_rx_queue_status *st =
  1121. (struct hal_reo_update_rx_queue_status *)st_handle;
  1122. uint32_t *reo_desc = (uint32_t *)ring_desc;
  1123. /*
  1124. * Offsets of descriptor fields defined in HW headers start
  1125. * from the field after TLV header
  1126. */
  1127. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  1128. /* header */
  1129. hal_reo_status_get_header(ring_desc,
  1130. HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV,
  1131. &(st->header), hal_soc);
  1132. }
  1133. uint8_t hal_get_tlv_hdr_size_li(void)
  1134. {
  1135. return sizeof(struct tlv_32_hdr);
  1136. }
  1137. uint64_t hal_rx_get_qdesc_addr_li(uint8_t *dst_ring_desc, uint8_t *buf)
  1138. {
  1139. return *(uint64_t *)dst_ring_desc +
  1140. REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
  1141. }