hal_li_generic_api.c 37 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "hal_li_api.h"
  20. #include "hal_li_hw_headers.h"
  21. #include "hal_li_reo.h"
  22. #include "hal_rx.h"
  23. #include "hal_li_rx.h"
  24. #include "hal_tx.h"
  25. #include <hal_api_mon.h>
  26. static uint32_t hal_get_reo_qdesc_size_li(uint32_t ba_window_size, int tid)
  27. {
  28. /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
  29. * NON_QOS_TID until HW issues are resolved.
  30. */
  31. if (tid != HAL_NON_QOS_TID)
  32. ba_window_size = HAL_RX_MAX_BA_WINDOW;
  33. /* Return descriptor size corresponding to window size of 2 since
  34. * we set ba_window_size to 2 while setting up REO descriptors as
  35. * a WAR to get 2k jump exception aggregates are received without
  36. * a BA session.
  37. */
  38. if (ba_window_size <= 1) {
  39. if (tid != HAL_NON_QOS_TID)
  40. return sizeof(struct rx_reo_queue) +
  41. sizeof(struct rx_reo_queue_ext);
  42. else
  43. return sizeof(struct rx_reo_queue);
  44. }
  45. if (ba_window_size <= 105)
  46. return sizeof(struct rx_reo_queue) +
  47. sizeof(struct rx_reo_queue_ext);
  48. if (ba_window_size <= 210)
  49. return sizeof(struct rx_reo_queue) +
  50. (2 * sizeof(struct rx_reo_queue_ext));
  51. return sizeof(struct rx_reo_queue) +
  52. (3 * sizeof(struct rx_reo_queue_ext));
  53. }
  54. void hal_set_link_desc_addr_li(void *desc, uint32_t cookie,
  55. qdf_dma_addr_t link_desc_paddr,
  56. uint8_t bm_id)
  57. {
  58. uint32_t *buf_addr = (uint32_t *)desc;
  59. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0,
  60. link_desc_paddr & 0xffffffff);
  61. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
  62. (uint64_t)link_desc_paddr >> 32);
  63. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER,
  64. bm_id);
  65. HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
  66. cookie);
  67. }
  68. void hal_tx_init_data_ring_li(hal_soc_handle_t hal_soc_hdl,
  69. hal_ring_handle_t hal_ring_hdl)
  70. {
  71. uint8_t *desc_addr;
  72. struct hal_srng_params srng_params;
  73. uint32_t desc_size;
  74. uint32_t num_desc;
  75. hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params);
  76. desc_addr = (uint8_t *)srng_params.ring_base_vaddr;
  77. desc_size = sizeof(struct tcl_data_cmd);
  78. num_desc = srng_params.num_entries;
  79. while (num_desc) {
  80. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG,
  81. desc_size);
  82. desc_addr += (desc_size + sizeof(struct tlv_32_hdr));
  83. num_desc--;
  84. }
  85. }
  86. /*
  87. * hal_rx_msdu_is_wlan_mcast_generic_li(): Check if the buffer is for multicast
  88. * address
  89. * @nbuf: Network buffer
  90. *
  91. * Returns: flag to indicate whether the nbuf has MC/BC address
  92. */
  93. static uint32_t hal_rx_msdu_is_wlan_mcast_generic_li(qdf_nbuf_t nbuf)
  94. {
  95. uint8_t *buf = qdf_nbuf_data(nbuf);
  96. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  97. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  98. return rx_attn->mcast_bcast;
  99. }
  100. /**
  101. * hal_rx_tlv_decap_format_get_li() - Get packet decap format from the TLV
  102. * @hw_desc_addr: rx tlv desc
  103. *
  104. * Return: pkt decap format
  105. */
  106. static uint32_t hal_rx_tlv_decap_format_get_li(void *hw_desc_addr)
  107. {
  108. struct rx_msdu_start *rx_msdu_start;
  109. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  110. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  111. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  112. }
  113. /**
  114. * hal_rx_dump_pkt_tlvs_li(): API to print all member elements of
  115. * RX TLVs
  116. * @ buf: pointer the pkt buffer.
  117. * @ dbg_level: log level.
  118. *
  119. * Return: void
  120. */
  121. static void hal_rx_dump_pkt_tlvs_li(hal_soc_handle_t hal_soc_hdl,
  122. uint8_t *buf, uint8_t dbg_level)
  123. {
  124. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  125. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  126. struct rx_mpdu_start *mpdu_start =
  127. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  128. struct rx_msdu_start *msdu_start =
  129. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  130. struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  131. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  132. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  133. hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level);
  134. hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc);
  135. hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level);
  136. hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level);
  137. hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level);
  138. hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level);
  139. }
  140. /**
  141. * hal_rx_tlv_get_offload_info_li() - Get the offload info from TLV
  142. * @rx_tlv: RX tlv start address in buffer
  143. * @offload_info: Buffer to store the offload info
  144. *
  145. * Return: 0 on success, -EINVAL on failure.
  146. */
  147. static int
  148. hal_rx_tlv_get_offload_info_li(uint8_t *rx_tlv,
  149. struct hal_offload_info *offload_info)
  150. {
  151. offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_tlv);
  152. offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_tlv);
  153. offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_tlv);
  154. offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_tlv);
  155. if (offload_info->tcp_proto) {
  156. offload_info->tcp_pure_ack =
  157. HAL_RX_TLV_GET_TCP_PURE_ACK(rx_tlv);
  158. offload_info->tcp_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_tlv);
  159. offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_tlv);
  160. offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_tlv);
  161. offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_tlv);
  162. }
  163. return 0;
  164. }
  165. /*
  166. * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value
  167. * from rx attention
  168. * @buf: pointer to rx_pkt_tlvs
  169. *
  170. * Return: phy_ppdu_id
  171. */
  172. static uint16_t hal_rx_attn_phy_ppdu_id_get_li(uint8_t *buf)
  173. {
  174. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  175. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  176. uint16_t phy_ppdu_id;
  177. phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn);
  178. return phy_ppdu_id;
  179. }
  180. /**
  181. * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length
  182. * from rx_msdu_start TLV
  183. *
  184. * @ buf: pointer to the start of RX PKT TLV headers
  185. * Return: msdu length
  186. */
  187. static uint32_t hal_rx_msdu_start_msdu_len_get_li(uint8_t *buf)
  188. {
  189. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  190. struct rx_msdu_start *msdu_start =
  191. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  192. uint32_t msdu_len;
  193. msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
  194. return msdu_len;
  195. }
  196. /**
  197. * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field
  198. *
  199. * @nbuf: Network buffer
  200. * Returns: rx more fragment bit
  201. *
  202. */
  203. static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf)
  204. {
  205. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  206. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  207. uint16_t frame_ctrl = 0;
  208. frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
  209. return frame_ctrl;
  210. }
  211. /**
  212. * hal_rx_get_proto_params_li() - Get l4 proto values from TLV
  213. * @buf: rx tlv address
  214. * @proto_params: Buffer to store proto parameters
  215. *
  216. * Return: 0 on success.
  217. */
  218. static int hal_rx_get_proto_params_li(uint8_t *buf, void *proto_params)
  219. {
  220. struct hal_proto_params *param =
  221. (struct hal_proto_params *)proto_params;
  222. param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(buf);
  223. param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(buf);
  224. param->ipv6_proto = HAL_RX_TLV_GET_IPV6(buf);
  225. return 0;
  226. }
  227. /**
  228. * hal_rx_get_l3_l4_offsets_li() - Get l3/l4 header offset from TLV
  229. * @buf: rx tlv start address
  230. * @l3_hdr_offset: buffer to store l3 offset
  231. * @l4_hdr_offset: buffer to store l4 offset
  232. *
  233. * Return: 0 on success.
  234. */
  235. static int hal_rx_get_l3_l4_offsets_li(uint8_t *buf, uint32_t *l3_hdr_offset,
  236. uint32_t *l4_hdr_offset)
  237. {
  238. *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(buf);
  239. *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(buf);
  240. return 0;
  241. }
  242. /**
  243. * hal_rx_tlv_get_pn_num_li() - Get packet number from RX TLV
  244. * @buf: rx tlv address
  245. * @pn_num: buffer to store packet number
  246. *
  247. * Return: None
  248. */
  249. static inline void hal_rx_tlv_get_pn_num_li(uint8_t *buf, uint64_t *pn_num)
  250. {
  251. struct rx_pkt_tlvs *rx_pkt_tlv =
  252. (struct rx_pkt_tlvs *)buf;
  253. struct rx_mpdu_info *rx_mpdu_info_details =
  254. &rx_pkt_tlv->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  255. pn_num[0] = rx_mpdu_info_details->pn_31_0;
  256. pn_num[0] |=
  257. ((uint64_t)rx_mpdu_info_details->pn_63_32 << 32);
  258. pn_num[1] = rx_mpdu_info_details->pn_95_64;
  259. pn_num[1] |=
  260. ((uint64_t)rx_mpdu_info_details->pn_127_96 << 32);
  261. }
  262. #ifdef NO_RX_PKT_HDR_TLV
  263. /**
  264. * hal_rx_pkt_hdr_get_li() - Get rx packet header start address.
  265. * @buf: packet start address
  266. *
  267. * Return: packet data start address.
  268. */
  269. static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf)
  270. {
  271. return buf + RX_PKT_TLVS_LEN;
  272. }
  273. #else
  274. static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf)
  275. {
  276. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  277. return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr;
  278. }
  279. #endif
  280. /**
  281. * hal_rx_priv_info_set_in_tlv_li(): Save the private info to
  282. * the reserved bytes of rx_tlv_hdr
  283. * @buf: start of rx_tlv_hdr
  284. * @priv_data: hal_wbm_err_desc_info structure
  285. * @len: length of the private data
  286. * Return: void
  287. */
  288. static inline void
  289. hal_rx_priv_info_set_in_tlv_li(uint8_t *buf, uint8_t *priv_data,
  290. uint32_t len)
  291. {
  292. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  293. uint32_t copy_len = (len > RX_PADDING0_BYTES) ?
  294. RX_PADDING0_BYTES : len;
  295. qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len);
  296. }
  297. /**
  298. * hal_rx_priv_info_get_from_tlv_li(): retrieve the private data from
  299. * the reserved bytes of rx_tlv_hdr.
  300. * @buf: start of rx_tlv_hdr
  301. * @priv_data: hal_wbm_err_desc_info structure
  302. * @len: length of the private data
  303. * Return: void
  304. */
  305. static inline void
  306. hal_rx_priv_info_get_from_tlv_li(uint8_t *buf, uint8_t *priv_data,
  307. uint32_t len)
  308. {
  309. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  310. uint32_t copy_len = (len > RX_PADDING0_BYTES) ?
  311. RX_PADDING0_BYTES : len;
  312. qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len);
  313. }
  314. /**
  315. * hal_rx_get_tlv_size_generic_li() - Get rx packet tlv size
  316. * @rx_pkt_tlv_size: TLV size for regular RX packets
  317. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  318. *
  319. * Return: size of rx pkt tlv before the actual data
  320. */
  321. static void hal_rx_get_tlv_size_generic_li(uint16_t *rx_pkt_tlv_size,
  322. uint16_t *rx_mon_pkt_tlv_size)
  323. {
  324. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  325. *rx_mon_pkt_tlv_size = SIZE_OF_MONITOR_TLV;
  326. }
  327. /**
  328. * hal_rx_wbm_err_src_get_li() - Get WBM error source from descriptor
  329. * @ring_desc: ring descriptor
  330. *
  331. * Return: wbm error source
  332. */
  333. uint32_t hal_rx_wbm_err_src_get_li(hal_ring_desc_t ring_desc)
  334. {
  335. return HAL_WBM2SW_RELEASE_SRC_GET(ring_desc);
  336. }
  337. /**
  338. * hal_rx_ret_buf_manager_get_li() - Get return buffer manager from ring desc
  339. * @ring_desc: ring descriptor
  340. *
  341. * Return: rbm
  342. */
  343. uint8_t hal_rx_ret_buf_manager_get_li(hal_ring_desc_t ring_desc)
  344. {
  345. /*
  346. * The following macro takes buf_addr_info as argument,
  347. * but since buf_addr_info is the first field in ring_desc
  348. * Hence the following call is OK
  349. */
  350. return HAL_RX_BUF_RBM_GET(ring_desc);
  351. }
  352. /**
  353. * hal_rx_reo_buf_paddr_get_li: Gets the physical address and
  354. * cookie from the REO destination ring element
  355. *
  356. * @ rx_desc: Opaque cookie pointer used by HAL to get to
  357. * the current descriptor
  358. * @ buf_info: structure to return the buffer information
  359. * Return: void
  360. */
  361. static void hal_rx_reo_buf_paddr_get_li(hal_ring_desc_t rx_desc,
  362. struct hal_buf_info *buf_info)
  363. {
  364. struct reo_destination_ring *reo_ring =
  365. (struct reo_destination_ring *)rx_desc;
  366. buf_info->paddr =
  367. (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) |
  368. ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32));
  369. buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring);
  370. }
  371. /**
  372. * hal_rx_msdu_link_desc_set_li: Retrieves MSDU Link Descriptor to WBM
  373. *
  374. * @ hal_soc_hdl : HAL version of the SOC pointer
  375. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  376. * @ buf_addr_info : void pointer to the buffer_addr_info
  377. * @ bm_action : put in IDLE list or release to MSDU_LIST
  378. *
  379. * Return: void
  380. */
  381. /* look at implementation at dp_hw_link_desc_pool_setup()*/
  382. static void hal_rx_msdu_link_desc_set_li(hal_soc_handle_t hal_soc_hdl,
  383. void *src_srng_desc,
  384. hal_buff_addrinfo_t buf_addr_info,
  385. uint8_t bm_action)
  386. {
  387. /*
  388. * The offsets for fields used in this function are same in
  389. * wbm_release_ring for Lithium and wbm_release_ring_tx
  390. * for Beryllium. hence we can use wbm_release_ring directly.
  391. */
  392. struct wbm_release_ring *wbm_rel_srng =
  393. (struct wbm_release_ring *)src_srng_desc;
  394. uint32_t addr_31_0;
  395. uint8_t addr_39_32;
  396. /* Structure copy !!! */
  397. wbm_rel_srng->released_buff_or_desc_addr_info =
  398. *(struct buffer_addr_info *)buf_addr_info;
  399. addr_31_0 =
  400. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0;
  401. addr_39_32 =
  402. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32;
  403. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING,
  404. RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW);
  405. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, BM_ACTION,
  406. bm_action);
  407. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING,
  408. BUFFER_OR_DESC_TYPE,
  409. HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC);
  410. /* WBM error is indicated when any of the link descriptors given to
  411. * WBM has a NULL address, and one those paths is the link descriptors
  412. * released from host after processing RXDMA errors,
  413. * or from Rx defrag path, and we want to add an assert here to ensure
  414. * host is not releasing descriptors with NULL address.
  415. */
  416. if (qdf_unlikely(!addr_31_0 && !addr_39_32)) {
  417. hal_dump_wbm_rel_desc(src_srng_desc);
  418. qdf_assert_always(0);
  419. }
  420. }
  421. static
  422. void hal_rx_buf_cookie_rbm_get_li(uint32_t *buf_addr_info_hdl,
  423. hal_buf_info_t buf_info_hdl)
  424. {
  425. struct hal_buf_info *buf_info =
  426. (struct hal_buf_info *)buf_info_hdl;
  427. struct buffer_addr_info *buf_addr_info =
  428. (struct buffer_addr_info *)buf_addr_info_hdl;
  429. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  430. /*
  431. * buffer addr info is the first member of ring desc, so the typecast
  432. * can be done.
  433. */
  434. buf_info->rbm = hal_rx_ret_buf_manager_get_li
  435. ((hal_ring_desc_t)buf_addr_info);
  436. }
  437. /**
  438. * hal_rx_msdu_link_desc_get(): API to get the MSDU information
  439. * from the MSDU link descriptor
  440. *
  441. * @ hal_soc_hdl : HAL version of the SOC pointer
  442. * @msdu_link_desc: Opaque pointer used by HAL to get to the
  443. * MSDU link descriptor (struct rx_msdu_link)
  444. *
  445. * @msdu_list: Return the list of MSDUs contained in this link descriptor
  446. *
  447. * @num_msdus: Number of MSDUs in the MPDU
  448. *
  449. * Return: void
  450. */
  451. static inline void hal_rx_msdu_list_get_li(hal_soc_handle_t hal_soc_hdl,
  452. void *msdu_link_desc,
  453. void *hal_msdu_list,
  454. uint16_t *num_msdus)
  455. {
  456. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  457. struct rx_msdu_details *msdu_details;
  458. struct rx_msdu_desc_info *msdu_desc_info;
  459. struct hal_rx_msdu_list *msdu_list = hal_msdu_list;
  460. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  461. int i;
  462. struct hal_buf_info buf_info;
  463. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  464. hal_debug("msdu_link=%pK msdu_details=%pK", msdu_link, msdu_details);
  465. for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
  466. /* num_msdus received in mpdu descriptor may be incorrect
  467. * sometimes due to HW issue. Check msdu buffer address also
  468. */
  469. if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET(
  470. &msdu_details[i].buffer_addr_info_details) == 0))
  471. break;
  472. if (HAL_RX_BUFFER_ADDR_31_0_GET(
  473. &msdu_details[i].buffer_addr_info_details) == 0) {
  474. /* set the last msdu bit in the prev msdu_desc_info */
  475. msdu_desc_info =
  476. hal_rx_msdu_desc_info_get_ptr
  477. (&msdu_details[i - 1], hal_soc);
  478. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  479. break;
  480. }
  481. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i],
  482. hal_soc);
  483. /* set first MSDU bit or the last MSDU bit */
  484. if (!i)
  485. HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  486. else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
  487. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  488. msdu_list->msdu_info[i].msdu_flags =
  489. hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info);
  490. msdu_list->msdu_info[i].msdu_len =
  491. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  492. /* addr field in buf_info will not be valid */
  493. hal_rx_buf_cookie_rbm_get_li(
  494. (uint32_t *)
  495. &msdu_details[i].buffer_addr_info_details,
  496. &buf_info);
  497. msdu_list->sw_cookie[i] = buf_info.sw_cookie;
  498. msdu_list->rbm[i] = buf_info.rbm;
  499. msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET(
  500. &msdu_details[i].buffer_addr_info_details) |
  501. (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET(
  502. &msdu_details[i].buffer_addr_info_details) << 32;
  503. hal_debug("i=%d sw_cookie=%d", i, msdu_list->sw_cookie[i]);
  504. }
  505. *num_msdus = i;
  506. }
  507. /*
  508. * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the
  509. * rxdma ring entry.
  510. * @rxdma_entry: descriptor entry
  511. * @paddr: physical address of nbuf data pointer.
  512. * @cookie: SW cookie used as a index to SW rx desc.
  513. * @manager: who owns the nbuf (host, NSS, etc...).
  514. *
  515. */
  516. static void hal_rxdma_buff_addr_info_set_li(void *rxdma_entry,
  517. qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager)
  518. {
  519. uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff);
  520. uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32;
  521. HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo);
  522. HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi);
  523. HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie);
  524. HAL_RXDMA_MANAGER_SET(rxdma_entry, manager);
  525. }
  526. /**
  527. * hal_rx_get_reo_error_code_li() - Get REO error code from ring desc
  528. * @rx_desc: rx descriptor
  529. *
  530. * Return: REO error code
  531. */
  532. static uint32_t hal_rx_get_reo_error_code_li(hal_ring_desc_t rx_desc)
  533. {
  534. struct reo_destination_ring *reo_desc =
  535. (struct reo_destination_ring *)rx_desc;
  536. return HAL_RX_REO_ERROR_GET(reo_desc);
  537. }
  538. /**
  539. * hal_gen_reo_remap_val_generic_li() - Generate the reo map value
  540. * @ix0_map: mapping values for reo
  541. *
  542. * Return: IX0 reo remap register value to be written
  543. */
  544. static uint32_t
  545. hal_gen_reo_remap_val_generic_li(enum hal_reo_remap_reg remap_reg,
  546. uint8_t *ix0_map)
  547. {
  548. uint32_t ix_val = 0;
  549. switch (remap_reg) {
  550. case HAL_REO_REMAP_REG_IX0:
  551. ix_val = HAL_REO_REMAP_IX0(ix0_map[0], 0) |
  552. HAL_REO_REMAP_IX0(ix0_map[1], 1) |
  553. HAL_REO_REMAP_IX0(ix0_map[2], 2) |
  554. HAL_REO_REMAP_IX0(ix0_map[3], 3) |
  555. HAL_REO_REMAP_IX0(ix0_map[4], 4) |
  556. HAL_REO_REMAP_IX0(ix0_map[5], 5) |
  557. HAL_REO_REMAP_IX0(ix0_map[6], 6) |
  558. HAL_REO_REMAP_IX0(ix0_map[7], 7);
  559. break;
  560. case HAL_REO_REMAP_REG_IX2:
  561. ix_val = HAL_REO_REMAP_IX2(ix0_map[0], 16) |
  562. HAL_REO_REMAP_IX2(ix0_map[1], 17) |
  563. HAL_REO_REMAP_IX2(ix0_map[2], 18) |
  564. HAL_REO_REMAP_IX2(ix0_map[3], 19) |
  565. HAL_REO_REMAP_IX2(ix0_map[4], 20) |
  566. HAL_REO_REMAP_IX2(ix0_map[5], 21) |
  567. HAL_REO_REMAP_IX2(ix0_map[6], 22) |
  568. HAL_REO_REMAP_IX2(ix0_map[7], 23);
  569. break;
  570. default:
  571. break;
  572. }
  573. return ix_val;
  574. }
  575. /**
  576. * hal_rx_tlv_csum_err_get_li() - Get IP and tcp-udp checksum fail flag
  577. * @rx_tlv_hdr: start address of rx_tlv_hdr
  578. * @ip_csum_err: buffer to return ip_csum_fail flag
  579. * @tcp_udp_csum_fail: placeholder to return tcp-udp checksum fail flag
  580. *
  581. * Return: None
  582. */
  583. static inline void
  584. hal_rx_tlv_csum_err_get_li(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err,
  585. uint32_t *tcp_udp_csum_err)
  586. {
  587. *ip_csum_err = hal_rx_attn_ip_cksum_fail_get(rx_tlv_hdr);
  588. *tcp_udp_csum_err = hal_rx_attn_tcp_udp_cksum_fail_get(rx_tlv_hdr);
  589. }
  590. static
  591. void hal_rx_tlv_get_pkt_capture_flags_li(uint8_t *rx_tlv_pkt_hdr,
  592. struct hal_rx_pkt_capture_flags *flags)
  593. {
  594. struct rx_pkt_tlvs *rx_tlv_hdr = (struct rx_pkt_tlvs *)rx_tlv_pkt_hdr;
  595. struct rx_attention *rx_attn = &rx_tlv_hdr->attn_tlv.rx_attn;
  596. struct rx_mpdu_start *mpdu_start =
  597. &rx_tlv_hdr->mpdu_start_tlv.rx_mpdu_start;
  598. struct rx_mpdu_end *mpdu_end = &rx_tlv_hdr->mpdu_end_tlv.rx_mpdu_end;
  599. struct rx_msdu_start *msdu_start =
  600. &rx_tlv_hdr->msdu_start_tlv.rx_msdu_start;
  601. flags->encrypt_type = mpdu_start->rx_mpdu_info_details.encrypt_type;
  602. flags->fcs_err = mpdu_end->fcs_err;
  603. flags->fragment_flag = rx_attn->fragment_flag;
  604. flags->chan_freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
  605. flags->rssi_comb = HAL_RX_MSDU_START_RSSI_GET(msdu_start);
  606. flags->tsft = msdu_start->ppdu_start_timestamp;
  607. }
  608. static uint8_t hal_rx_err_status_get_li(hal_ring_desc_t rx_desc)
  609. {
  610. return HAL_RX_ERROR_STATUS_GET(rx_desc);
  611. }
  612. static uint8_t hal_rx_reo_buf_type_get_li(hal_ring_desc_t rx_desc)
  613. {
  614. return HAL_RX_REO_BUF_TYPE_GET(rx_desc);
  615. }
  616. static inline bool
  617. hal_rx_mpdu_info_ampdu_flag_get_li(uint8_t *buf)
  618. {
  619. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  620. struct rx_mpdu_start *mpdu_start =
  621. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  622. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  623. bool ampdu_flag;
  624. ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info);
  625. return ampdu_flag;
  626. }
  627. static
  628. uint32_t hal_rx_tlv_mpdu_len_err_get_li(void *hw_desc_addr)
  629. {
  630. struct rx_attention *rx_attn;
  631. struct rx_mon_pkt_tlvs *rx_desc =
  632. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  633. rx_attn = &rx_desc->attn_tlv.rx_attn;
  634. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
  635. }
  636. static
  637. uint32_t hal_rx_tlv_mpdu_fcs_err_get_li(void *hw_desc_addr)
  638. {
  639. struct rx_attention *rx_attn;
  640. struct rx_mon_pkt_tlvs *rx_desc =
  641. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  642. rx_attn = &rx_desc->attn_tlv.rx_attn;
  643. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
  644. }
  645. #ifdef NO_RX_PKT_HDR_TLV
  646. static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr)
  647. {
  648. uint8_t *rx_pkt_hdr;
  649. struct rx_mon_pkt_tlvs *rx_desc =
  650. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  651. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  652. return rx_pkt_hdr;
  653. }
  654. #else
  655. static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr)
  656. {
  657. uint8_t *rx_pkt_hdr;
  658. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  659. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  660. return rx_pkt_hdr;
  661. }
  662. #endif
  663. static uint32_t hal_rx_hw_desc_mpdu_user_id_li(void *hw_desc_addr)
  664. {
  665. struct rx_mon_pkt_tlvs *rx_desc =
  666. (struct rx_mon_pkt_tlvs *)hw_desc_addr;
  667. uint32_t user_id;
  668. user_id = HAL_RX_GET_USER_TLV32_USERID(
  669. &rx_desc->mpdu_start_tlv);
  670. return user_id;
  671. }
  672. /**
  673. * hal_rx_msdu_start_msdu_len_set_li(): API to set the MSDU length
  674. * from rx_msdu_start TLV
  675. *
  676. * @buf: pointer to the start of RX PKT TLV headers
  677. * @len: msdu length
  678. *
  679. * Return: none
  680. */
  681. static inline void
  682. hal_rx_msdu_start_msdu_len_set_li(uint8_t *buf, uint32_t len)
  683. {
  684. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  685. struct rx_msdu_start *msdu_start =
  686. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  687. void *wrd1;
  688. wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET;
  689. *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK);
  690. *(uint32_t *)wrd1 |= len;
  691. }
  692. /*
  693. * hal_rx_tlv_bw_get_li(): API to get the Bandwidth
  694. * Interval from rx_msdu_start
  695. *
  696. * @buf: pointer to the start of RX PKT TLV header
  697. * Return: uint32_t(bw)
  698. */
  699. static inline uint32_t hal_rx_tlv_bw_get_li(uint8_t *buf)
  700. {
  701. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  702. struct rx_msdu_start *msdu_start =
  703. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  704. uint32_t bw;
  705. bw = HAL_RX_MSDU_START_BW_GET(msdu_start);
  706. return bw;
  707. }
  708. /*
  709. * hal_rx_tlv_get_freq_li(): API to get the frequency of operating channel
  710. * from rx_msdu_start
  711. *
  712. * @buf: pointer to the start of RX PKT TLV header
  713. * Return: uint32_t(frequency)
  714. */
  715. static inline uint32_t
  716. hal_rx_tlv_get_freq_li(uint8_t *buf)
  717. {
  718. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  719. struct rx_msdu_start *msdu_start =
  720. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  721. uint32_t freq;
  722. freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
  723. return freq;
  724. }
  725. /**
  726. * hal_rx_tlv_sgi_get_li(): API to get the Short Gaurd
  727. * Interval from rx_msdu_start TLV
  728. *
  729. * @buf: pointer to the start of RX PKT TLV headers
  730. * Return: uint32_t(sgi)
  731. */
  732. static inline uint32_t
  733. hal_rx_tlv_sgi_get_li(uint8_t *buf)
  734. {
  735. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  736. struct rx_msdu_start *msdu_start =
  737. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  738. uint32_t sgi;
  739. sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start);
  740. return sgi;
  741. }
  742. /**
  743. * hal_rx_tlv_rate_mcs_get_li(): API to get the MCS rate
  744. * from rx_msdu_start TLV
  745. *
  746. * @buf: pointer to the start of RX PKT TLV headers
  747. * Return: uint32_t(rate_mcs)
  748. */
  749. static inline uint32_t
  750. hal_rx_tlv_rate_mcs_get_li(uint8_t *buf)
  751. {
  752. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  753. struct rx_msdu_start *msdu_start =
  754. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  755. uint32_t rate_mcs;
  756. rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start);
  757. return rate_mcs;
  758. }
  759. /*
  760. * hal_rx_tlv_get_pkt_type_li(): API to get the pkt type
  761. * from rx_msdu_start
  762. *
  763. * @buf: pointer to the start of RX PKT TLV header
  764. * Return: uint32_t(pkt type)
  765. */
  766. static inline uint32_t hal_rx_tlv_get_pkt_type_li(uint8_t *buf)
  767. {
  768. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  769. struct rx_msdu_start *msdu_start =
  770. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  771. uint32_t pkt_type;
  772. pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start);
  773. return pkt_type;
  774. }
  775. /**
  776. * hal_rx_tlv_mic_err_get_li(): API to get the MIC ERR
  777. * from rx_mpdu_end TLV
  778. *
  779. * @buf: pointer to the start of RX PKT TLV headers
  780. * Return: uint32_t(mic_err)
  781. */
  782. static inline uint32_t
  783. hal_rx_tlv_mic_err_get_li(uint8_t *buf)
  784. {
  785. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  786. struct rx_mpdu_end *mpdu_end =
  787. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  788. uint32_t mic_err;
  789. mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end);
  790. return mic_err;
  791. }
  792. /**
  793. * hal_rx_tlv_decrypt_err_get_li(): API to get the Decrypt ERR
  794. * from rx_mpdu_end TLV
  795. *
  796. * @buf: pointer to the start of RX PKT TLV headers
  797. * Return: uint32_t(decrypt_err)
  798. */
  799. static inline uint32_t
  800. hal_rx_tlv_decrypt_err_get_li(uint8_t *buf)
  801. {
  802. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  803. struct rx_mpdu_end *mpdu_end =
  804. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  805. uint32_t decrypt_err;
  806. decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end);
  807. return decrypt_err;
  808. }
  809. /*
  810. * hal_rx_tlv_first_mpdu_get_li(): get fist_mpdu bit from rx attention
  811. * @buf: pointer to rx_pkt_tlvs
  812. *
  813. * reutm: uint32_t(first_msdu)
  814. */
  815. static inline uint32_t
  816. hal_rx_tlv_first_mpdu_get_li(uint8_t *buf)
  817. {
  818. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  819. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  820. uint32_t first_mpdu;
  821. first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn);
  822. return first_mpdu;
  823. }
  824. /*
  825. * hal_rx_msdu_get_keyid_li(): API to get the key id if the decrypted packet
  826. * from rx_msdu_end
  827. *
  828. * @buf: pointer to the start of RX PKT TLV header
  829. * Return: uint32_t(key id)
  830. */
  831. static inline uint8_t
  832. hal_rx_msdu_get_keyid_li(uint8_t *buf)
  833. {
  834. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  835. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  836. uint32_t keyid_octet;
  837. keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end);
  838. return keyid_octet & 0x3;
  839. }
  840. /*
  841. * hal_rx_tlv_get_is_decrypted_li(): API to get the decrypt status of the
  842. * packet from rx_attention
  843. *
  844. * @buf: pointer to the start of RX PKT TLV header
  845. * Return: uint32_t(decryt status)
  846. */
  847. static inline uint32_t
  848. hal_rx_tlv_get_is_decrypted_li(uint8_t *buf)
  849. {
  850. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  851. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  852. uint32_t is_decrypt = 0;
  853. uint32_t decrypt_status;
  854. decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn);
  855. if (!decrypt_status)
  856. is_decrypt = 1;
  857. return is_decrypt;
  858. }
  859. /**
  860. * hal_rx_msdu_reo_dst_ind_get_li: Gets the REO
  861. * destination ring ID from the msdu desc info
  862. *
  863. * @ hal_soc_hdl : HAL version of the SOC pointer
  864. * @msdu_link_desc : Opaque cookie pointer used by HAL to get to
  865. * the current descriptor
  866. *
  867. * Return: dst_ind (REO destination ring ID)
  868. */
  869. static inline uint32_t
  870. hal_rx_msdu_reo_dst_ind_get_li(hal_soc_handle_t hal_soc_hdl,
  871. void *msdu_link_desc)
  872. {
  873. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  874. struct rx_msdu_details *msdu_details;
  875. struct rx_msdu_desc_info *msdu_desc_info;
  876. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  877. uint32_t dst_ind;
  878. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  879. /* The first msdu in the link should exsist */
  880. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0],
  881. hal_soc);
  882. dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info);
  883. return dst_ind;
  884. }
  885. static inline void
  886. hal_mpdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl,
  887. void *mpdu_desc, uint32_t seq_no)
  888. {
  889. struct rx_mpdu_desc_info *mpdu_desc_info =
  890. (struct rx_mpdu_desc_info *)mpdu_desc;
  891. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  892. MSDU_COUNT, 0x1);
  893. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  894. MPDU_SEQUENCE_NUMBER, seq_no);
  895. /* unset frag bit */
  896. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  897. FRAGMENT_FLAG, 0x0);
  898. /* set sa/da valid bits */
  899. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  900. SA_IS_VALID, 0x1);
  901. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  902. DA_IS_VALID, 0x1);
  903. HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
  904. RAW_MPDU, 0x0);
  905. }
  906. static inline void
  907. hal_msdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl,
  908. void *msdu_desc, uint32_t dst_ind,
  909. uint32_t nbuf_len)
  910. {
  911. struct rx_msdu_desc_info *msdu_desc_info =
  912. (struct rx_msdu_desc_info *)msdu_desc;
  913. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  914. FIRST_MSDU_IN_MPDU_FLAG, 1);
  915. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  916. LAST_MSDU_IN_MPDU_FLAG, 1);
  917. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  918. MSDU_CONTINUATION, 0x0);
  919. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  920. REO_DESTINATION_INDICATION,
  921. dst_ind);
  922. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  923. MSDU_LENGTH, nbuf_len);
  924. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  925. SA_IS_VALID, 1);
  926. HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
  927. DA_IS_VALID, 1);
  928. }
  929. static inline
  930. uint8_t *hal_get_reo_ent_desc_qdesc_addr_li(uint8_t *desc)
  931. {
  932. return desc + REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
  933. }
  934. static inline
  935. void hal_set_reo_ent_desc_reo_dest_ind_li(uint8_t *desc, uint32_t dst_ind)
  936. {
  937. HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING_5,
  938. REO_DESTINATION_INDICATION, dst_ind);
  939. }
  940. static inline void
  941. hal_rx_wbm_rel_buf_paddr_get_li(hal_ring_desc_t rx_desc,
  942. struct hal_buf_info *buf_info)
  943. {
  944. struct wbm_release_ring *wbm_rel_ring =
  945. (struct wbm_release_ring *)rx_desc;
  946. buf_info->paddr =
  947. (HAL_RX_WBM_BUF_ADDR_31_0_GET(wbm_rel_ring) |
  948. ((uint64_t)(HAL_RX_WBM_BUF_ADDR_39_32_GET(wbm_rel_ring)) << 32));
  949. buf_info->sw_cookie = HAL_RX_WBM_BUF_COOKIE_GET(wbm_rel_ring);
  950. }
  951. static QDF_STATUS hal_reo_status_update_li(hal_soc_handle_t hal_soc_hdl,
  952. hal_ring_desc_t reo_desc,
  953. void *st_handle,
  954. uint32_t tlv, int *num_ref)
  955. {
  956. union hal_reo_status *reo_status_ref;
  957. reo_status_ref = (union hal_reo_status *)st_handle;
  958. switch (tlv) {
  959. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  960. hal_reo_queue_stats_status_li(reo_desc,
  961. &reo_status_ref->queue_status,
  962. hal_soc_hdl);
  963. *num_ref = reo_status_ref->queue_status.header.cmd_num;
  964. break;
  965. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  966. hal_reo_flush_queue_status_li(reo_desc,
  967. &reo_status_ref->fl_queue_status,
  968. hal_soc_hdl);
  969. *num_ref = reo_status_ref->fl_queue_status.header.cmd_num;
  970. break;
  971. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  972. hal_reo_flush_cache_status_li(reo_desc,
  973. &reo_status_ref->fl_cache_status,
  974. hal_soc_hdl);
  975. *num_ref = reo_status_ref->fl_cache_status.header.cmd_num;
  976. break;
  977. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  978. hal_reo_unblock_cache_status_li(
  979. reo_desc, hal_soc_hdl,
  980. &reo_status_ref->unblk_cache_status);
  981. *num_ref = reo_status_ref->unblk_cache_status.header.cmd_num;
  982. break;
  983. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  984. hal_reo_flush_timeout_list_status_li(
  985. reo_desc,
  986. &reo_status_ref->fl_timeout_status,
  987. hal_soc_hdl);
  988. *num_ref = reo_status_ref->fl_timeout_status.header.cmd_num;
  989. break;
  990. case HAL_REO_DESC_THRES_STATUS_TLV:
  991. hal_reo_desc_thres_reached_status_li(
  992. reo_desc,
  993. &reo_status_ref->thres_status,
  994. hal_soc_hdl);
  995. *num_ref = reo_status_ref->thres_status.header.cmd_num;
  996. break;
  997. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  998. hal_reo_rx_update_queue_status_li(
  999. reo_desc,
  1000. &reo_status_ref->rx_queue_status,
  1001. hal_soc_hdl);
  1002. *num_ref = reo_status_ref->rx_queue_status.header.cmd_num;
  1003. break;
  1004. default:
  1005. QDF_TRACE(QDF_MODULE_ID_DP_REO, QDF_TRACE_LEVEL_WARN,
  1006. "hal_soc %pK: no handler for TLV:%d",
  1007. hal_soc_hdl, tlv);
  1008. return QDF_STATUS_E_FAILURE;
  1009. } /* switch */
  1010. return QDF_STATUS_SUCCESS;
  1011. }
  1012. /**
  1013. * hal_get_idle_link_bm_id_li() - Get idle link BM id from chid_id
  1014. * @chip_id: mlo chip_id
  1015. *
  1016. * Returns: RBM ID
  1017. */
  1018. static uint8_t hal_get_idle_link_bm_id_li(uint8_t chip_id)
  1019. {
  1020. return WBM_IDLE_DESC_LIST;
  1021. }
  1022. /**
  1023. * hal_hw_txrx_default_ops_attach_li() - Attach the default hal ops for
  1024. * lithium chipsets.
  1025. * @hal_soc_hdl: HAL soc handle
  1026. *
  1027. * Return: None
  1028. */
  1029. void hal_hw_txrx_default_ops_attach_li(struct hal_soc *hal_soc)
  1030. {
  1031. hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_li;
  1032. hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_li;
  1033. hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_li;
  1034. hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_li;
  1035. hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_li;
  1036. hal_soc->ops->hal_get_reo_reg_base_offset =
  1037. hal_get_reo_reg_base_offset_li;
  1038. hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_li;
  1039. hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
  1040. hal_rx_msdu_is_wlan_mcast_generic_li;
  1041. hal_soc->ops->hal_rx_tlv_decap_format_get =
  1042. hal_rx_tlv_decap_format_get_li;
  1043. hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_li;
  1044. hal_soc->ops->hal_rx_tlv_get_offload_info =
  1045. hal_rx_tlv_get_offload_info_li;
  1046. hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
  1047. hal_rx_attn_phy_ppdu_id_get_li;
  1048. hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_li;
  1049. hal_soc->ops->hal_rx_tlv_msdu_len_get =
  1050. hal_rx_msdu_start_msdu_len_get_li;
  1051. hal_soc->ops->hal_rx_get_frame_ctrl_field =
  1052. hal_rx_get_frame_ctrl_field_li;
  1053. hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_li;
  1054. hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_li;
  1055. hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_li;
  1056. hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_li;
  1057. hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_li;
  1058. hal_soc->ops->hal_rx_ret_buf_manager_get =
  1059. hal_rx_ret_buf_manager_get_li;
  1060. hal_soc->ops->hal_rxdma_buff_addr_info_set =
  1061. hal_rxdma_buff_addr_info_set_li;
  1062. hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_li;
  1063. hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_li;
  1064. hal_soc->ops->hal_gen_reo_remap_val =
  1065. hal_gen_reo_remap_val_generic_li;
  1066. hal_soc->ops->hal_rx_tlv_csum_err_get =
  1067. hal_rx_tlv_csum_err_get_li;
  1068. hal_soc->ops->hal_rx_mpdu_desc_info_get =
  1069. hal_rx_mpdu_desc_info_get_li;
  1070. hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_li;
  1071. hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_li;
  1072. hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_li;
  1073. hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_li;
  1074. hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get =
  1075. hal_rx_wbm_rel_buf_paddr_get_li;
  1076. hal_soc->ops->hal_rx_priv_info_set_in_tlv =
  1077. hal_rx_priv_info_set_in_tlv_li;
  1078. hal_soc->ops->hal_rx_priv_info_get_from_tlv =
  1079. hal_rx_priv_info_get_from_tlv_li;
  1080. hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
  1081. hal_rx_mpdu_info_ampdu_flag_get_li;
  1082. hal_soc->ops->hal_rx_tlv_mpdu_len_err_get =
  1083. hal_rx_tlv_mpdu_len_err_get_li;
  1084. hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get =
  1085. hal_rx_tlv_mpdu_fcs_err_get_li;
  1086. hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_li;
  1087. hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags =
  1088. hal_rx_tlv_get_pkt_capture_flags_li;
  1089. hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_li;
  1090. hal_soc->ops->hal_rx_hw_desc_mpdu_user_id =
  1091. hal_rx_hw_desc_mpdu_user_id_li;
  1092. hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_li;
  1093. hal_soc->ops->hal_rx_tlv_msdu_len_set =
  1094. hal_rx_msdu_start_msdu_len_set_li;
  1095. hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_li;
  1096. hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_li;
  1097. hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_li;
  1098. hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_li;
  1099. hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_li;
  1100. hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li;
  1101. hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li;
  1102. hal_soc->ops->hal_rx_tlv_decrypt_err_get =
  1103. hal_rx_tlv_decrypt_err_get_li;
  1104. hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_li;
  1105. hal_soc->ops->hal_rx_tlv_get_is_decrypted =
  1106. hal_rx_tlv_get_is_decrypted_li;
  1107. hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_li;
  1108. hal_soc->ops->hal_rx_msdu_reo_dst_ind_get =
  1109. hal_rx_msdu_reo_dst_ind_get_li;
  1110. hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_li;
  1111. hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_li;
  1112. hal_soc->ops->hal_reo_status_update = hal_reo_status_update_li;
  1113. hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_li;
  1114. hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr =
  1115. hal_get_reo_ent_desc_qdesc_addr_li;
  1116. hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_li;
  1117. hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind =
  1118. hal_set_reo_ent_desc_reo_dest_ind_li;
  1119. hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_li;
  1120. }