hal_kiwi_rx.h 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195
  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_KIWI_RX_H_
  20. #define _HAL_KIWI_RX_H_
  21. #include "qdf_util.h"
  22. #include "qdf_types.h"
  23. #include "qdf_lock.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include "tcl_data_cmd.h"
  27. //#include "mac_tcl_reg_seq_hwioreg.h"
  28. #include "phyrx_rssi_legacy.h"
  29. #include "rx_msdu_start.h"
  30. #include "tlv_tag_def.h"
  31. #include "hal_hw_headers.h"
  32. #include "hal_internal.h"
  33. #include "cdp_txrx_mon_struct.h"
  34. #include "qdf_trace.h"
  35. #include "hal_rx.h"
  36. #include "hal_tx.h"
  37. #include "dp_types.h"
  38. #include "hal_api_mon.h"
  39. #include "phyrx_other_receive_info_ru_details.h"
  40. #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
  41. (uint8_t *)(link_desc_va) + \
  42. RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  43. #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
  44. (uint8_t *)(msdu0) + \
  45. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  46. #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
  47. (uint8_t *)(ent_ring_desc) + \
  48. RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  49. #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
  50. (uint8_t *)(dst_ring_desc) + \
  51. REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  52. #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
  53. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID)
  54. #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
  55. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID)
  56. #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \
  57. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_PEER_ID)
  58. #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
  59. do { \
  60. reg_val &= \
  61. ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\
  62. HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
  63. reg_val |= \
  64. HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
  65. AGING_LIST_ENABLE, 1) |\
  66. HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
  67. AGING_FLUSH_ENABLE, 1);\
  68. HAL_REG_WRITE((soc), \
  69. HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
  70. REO_REG_REG_BASE), \
  71. (reg_val)); \
  72. reg_val = \
  73. HAL_REG_READ((soc), \
  74. HWIO_REO_R0_MISC_CTL_ADDR( \
  75. REO_REG_REG_BASE)); \
  76. reg_val &= \
  77. ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
  78. reg_val |= \
  79. HAL_SM(HWIO_REO_R0_MISC_CTL, \
  80. FRAGMENT_DEST_RING, \
  81. (reo_params)->frag_dst_ring); \
  82. reg_val &= \
  83. (~HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK |\
  84. (REO_REMAP_TCL << HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT)); \
  85. HAL_REG_WRITE((soc), \
  86. HWIO_REO_R0_MISC_CTL_ADDR( \
  87. REO_REG_REG_BASE), \
  88. (reg_val)); \
  89. } while (0)
  90. #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
  91. ((struct rx_msdu_desc_info *) \
  92. _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
  93. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
  94. #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
  95. ((struct rx_msdu_details *) \
  96. _OFFSET_TO_BYTE_PTR((link_desc),\
  97. RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
  98. #if defined(QCA_WIFI_KIWI) && defined(WLAN_CFR_ENABLE) && \
  99. defined(WLAN_ENH_CFR_ENABLE)
  100. static inline
  101. void hal_rx_get_bb_info_kiwi(void *rx_tlv,
  102. void *ppdu_info_hdl)
  103. {
  104. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  105. ppdu_info->cfr_info.bb_captured_channel =
  106. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
  107. ppdu_info->cfr_info.bb_captured_timeout =
  108. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
  109. ppdu_info->cfr_info.bb_captured_reason =
  110. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
  111. }
  112. static inline
  113. void hal_rx_get_rtt_info_kiwi(void *rx_tlv,
  114. void *ppdu_info_hdl)
  115. {
  116. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  117. ppdu_info->cfr_info.rx_location_info_valid =
  118. HAL_RX_GET(rx_tlv, PHYRX_LOCATION,
  119. RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID);
  120. ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
  121. HAL_RX_GET(rx_tlv,
  122. RX_LOCATION_INFO,
  123. RTT_CHE_BUFFER_POINTER_LOW32);
  124. ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
  125. HAL_RX_GET(rx_tlv,
  126. RX_LOCATION_INFO,
  127. RTT_CHE_BUFFER_POINTER_HIGH8);
  128. // TODO Beryllium - Changed reserved8 to reserved3 to avoid
  129. // compilation failure for kiwi
  130. ppdu_info->cfr_info.chan_capture_status =
  131. HAL_RX_GET(rx_tlv,
  132. RX_LOCATION_INFO,
  133. RESERVED_3);
  134. ppdu_info->cfr_info.rx_start_ts =
  135. HAL_RX_GET(rx_tlv,
  136. RX_LOCATION_INFO,
  137. RX_START_TS);
  138. ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
  139. HAL_RX_GET(rx_tlv,
  140. RX_LOCATION_INFO,
  141. RTT_CFO_MEASUREMENT);
  142. ppdu_info->cfr_info.agc_gain_info0 =
  143. HAL_RX_GET(rx_tlv,
  144. PHYRX_PKT_END_RX_PKT_END_DETAILS,
  145. PHY_TIMESTAMP_1_LOWER_32);
  146. ppdu_info->cfr_info.agc_gain_info1 =
  147. HAL_RX_GET(rx_tlv,
  148. PHYRX_PKT_END_RX_PKT_END_DETAILS,
  149. PHY_TIMESTAMP_1_UPPER_32);
  150. ppdu_info->cfr_info.agc_gain_info2 =
  151. HAL_RX_GET(rx_tlv,
  152. PHYRX_PKT_END_RX_PKT_END_DETAILS,
  153. PHY_TIMESTAMP_2_LOWER_32);
  154. ppdu_info->cfr_info.agc_gain_info3 =
  155. HAL_RX_GET(rx_tlv,
  156. PHYRX_PKT_END_RX_PKT_END_DETAILS,
  157. PHY_TIMESTAMP_2_UPPER_32);
  158. ppdu_info->cfr_info.mcs_rate =
  159. HAL_RX_GET(rx_tlv,
  160. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  161. RTT_MCS_RATE);
  162. ppdu_info->cfr_info.gi_type =
  163. HAL_RX_GET(rx_tlv,
  164. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  165. RTT_GI_TYPE);
  166. }
  167. #endif
  168. #endif