hal_tx.h 28 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #if !defined(HAL_TX_H)
  20. #define HAL_TX_H
  21. /*---------------------------------------------------------------------------
  22. Include files
  23. ---------------------------------------------------------------------------*/
  24. #include "hal_api.h"
  25. #include "wcss_version.h"
  26. #include "hal_hw_headers.h"
  27. #include "hal_tx_hw_defines.h"
  28. #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0
  29. #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1
  30. #define HAL_TX_DESC_TLV_TAG_OFFSET 1
  31. #define HAL_TX_DESC_TLV_LEN_OFFSET 10
  32. /*---------------------------------------------------------------------------
  33. Preprocessor definitions and constants
  34. ---------------------------------------------------------------------------*/
  35. #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET
  36. #define HAL_TX_LSB(block, field) block ## _ ## field ## _LSB
  37. #define HAL_TX_MASK(block, field) block ## _ ## field ## _MASK
  38. #define HAL_TX_DESC_OFFSET(desc, block, field) \
  39. (((uint8_t *)desc) + HAL_OFFSET(block, field))
  40. #define HAL_SET_FLD(desc, block , field) \
  41. (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field)))
  42. #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \
  43. (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset)))
  44. #define HAL_SET_FLD_64(desc, block, field) \
  45. (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field)))
  46. #define HAL_SET_FLD_OFFSET_64(desc, block, field, offset) \
  47. (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field) + (offset)))
  48. #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \
  49. do { \
  50. uint32_t temp = 0; \
  51. temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \
  52. temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \
  53. (*(uint32_t *)desc) = temp; \
  54. } while (0)
  55. #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E
  56. #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E
  57. #define HAL_TX_SM(block, field, value) \
  58. ((value << (block ## _ ## field ## _LSB)) & \
  59. (block ## _ ## field ## _MASK))
  60. #define HAL_TX_MS(block, field, value) \
  61. (((value) & (block ## _ ## field ## _MASK)) >> \
  62. (block ## _ ## field ## _LSB))
  63. #define HAL_TX_DESC_GET(desc, block, field) \
  64. HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field))
  65. #define HAL_TX_DESC_OFFSET_GET(desc, block, field, offset) \
  66. HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET(desc, block, field, offset))
  67. #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \
  68. HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub))
  69. #define HAL_TX_DESC_GET_64(desc, block, field) \
  70. HAL_TX_MS(block, field, HAL_SET_FLD_64(desc, block, field))
  71. #define HAL_TX_DESC_OFFSET_GET_64(desc, block, field, offset) \
  72. HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET_64(desc, block, field,\
  73. offset))
  74. #define HAL_TX_DESC_SUBBLOCK_GET_64(desc, block, sub, field) \
  75. HAL_TX_MS(sub, field, HAL_SET_FLD_64(desc, block, sub))
  76. #define HAL_TX_BUF_TYPE_BUFFER 0
  77. #define HAL_TX_BUF_TYPE_EXT_DESC 1
  78. #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
  79. #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD)
  80. #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4)
  81. #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION)
  82. #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4)
  83. #define NUM_OF_DWORDS_WBM_RELEASE_RING 8
  84. #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING)
  85. #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4)
  86. #define HAL_TX_BITS_PER_TID 3
  87. #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1)
  88. #define HAL_TX_NUM_DSCP_PER_REGISTER 10
  89. #define HAL_MAX_HW_DSCP_TID_MAPS 2
  90. #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32
  91. #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48
  92. #define HTT_META_HEADER_LEN_BYTES 64
  93. #define HAL_TX_EXT_DESC_WITH_META_DATA \
  94. (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES)
  95. #define HAL_TX_NUM_PCP_PER_REGISTER 8
  96. /* Length of WBM release ring without the status words */
  97. #define HAL_TX_COMPLETION_DESC_BASE_LEN 12
  98. #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0
  99. #define HAL_TX_COMP_RELEASE_SOURCE_REO 2
  100. #define HAL_TX_COMP_RELEASE_SOURCE_FW 3
  101. /* Define a place-holder release reason for FW */
  102. #define HAL_TX_COMP_RELEASE_REASON_FW 99
  103. /*
  104. * Offset of HTT Tx Descriptor in WBM Completion
  105. * HTT Tx Desc structure is passed from firmware to host overlayed
  106. * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions
  107. * (Exception frames and TQM bypass frames)
  108. */
  109. #define HAL_TX_COMP_HTT_STATUS_OFFSET 8
  110. #define HAL_TX_COMP_HTT_STATUS_LEN 16
  111. #define HAL_TX_BUF_TYPE_BUFFER 0
  112. #define HAL_TX_BUF_TYPE_EXT_DESC 1
  113. #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET
  114. #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK
  115. #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK
  116. #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK
  117. #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB
  118. #define HAL_TX_EXT_BUF_WD_SIZE 2
  119. #define HAL_TX_DESC_ADDRX_EN 0x1
  120. #define HAL_TX_DESC_ADDRY_EN 0x2
  121. #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3
  122. #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0
  123. #define HAL_TX_ADDR_INDEX_SEARCH 0x1
  124. #define HAL_TX_FLOW_INDEX_SEARCH 0x2
  125. #define HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc)(((*(((uint32_t *)wbm_desc) + \
  126. (HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \
  127. HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK) >> \
  128. HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB)
  129. #define HAL_WBM_SW0_BM_ID(sw0_bm_id) (sw0_bm_id)
  130. #define HAL_WBM_SW1_BM_ID(sw0_bm_id) ((sw0_bm_id) + 1)
  131. #define HAL_WBM_SW2_BM_ID(sw0_bm_id) ((sw0_bm_id) + 2)
  132. #define HAL_WBM_SW3_BM_ID(sw0_bm_id) ((sw0_bm_id) + 3)
  133. #define HAL_WBM_SW4_BM_ID(sw0_bm_id) ((sw0_bm_id) + 4)
  134. #define HAL_WBM_SW5_BM_ID(sw0_bm_id) ((sw0_bm_id) + 5)
  135. #define HAL_WBM_SW6_BM_ID(sw0_bm_id) ((sw0_bm_id) + 6)
  136. /*---------------------------------------------------------------------------
  137. Structures
  138. ---------------------------------------------------------------------------*/
  139. /**
  140. * struct hal_tx_completion_status - HAL Tx completion descriptor contents
  141. * @status: frame acked/failed
  142. * @release_src: release source = TQM/FW
  143. * @ack_frame_rssi: RSSI of the received ACK or BA frame
  144. * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU
  145. * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU
  146. * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU
  147. * @bw: Indicates the BW of the upcoming transmission -
  148. * <enum 0 transmit_bw_20_MHz>
  149. * <enum 1 transmit_bw_40_MHz>
  150. * <enum 2 transmit_bw_80_MHz>
  151. * <enum 3 transmit_bw_160_MHz>
  152. * @pkt_type: Transmit Packet Type
  153. * @stbc: When set, STBC transmission rate was used
  154. * @ldpc: When set, use LDPC transmission rates
  155. * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI
  156. * <enum 1 0_4_us_sgi > Legacy short GI
  157. * <enum 2 1_6_us_sgi > HE related GI
  158. * <enum 3 3_2_us_sgi > HE
  159. * @mcs: Transmit MCS Rate
  160. * @ofdma: Set when the transmission was an OFDMA transmission
  161. * @tones_in_ru: The number of tones in the RU used.
  162. * @tsf: Lower 32 bits of the TSF
  163. * @ppdu_id: TSF, snapshot of this value when transmission of the
  164. * PPDU containing the frame finished.
  165. * @transmit_cnt: Number of times this frame has been transmitted
  166. * @tid: TID of the flow or MPDU queue
  167. * @peer_id: Peer ID of the flow or MPDU queue
  168. * @buffer_timestamp: Frame system entrance timestamp in units of 1024
  169. * microseconds
  170. */
  171. struct hal_tx_completion_status {
  172. uint8_t status;
  173. uint8_t release_src;
  174. uint8_t ack_frame_rssi;
  175. uint8_t first_msdu:1,
  176. last_msdu:1,
  177. msdu_part_of_amsdu:1;
  178. uint32_t bw:2,
  179. pkt_type:4,
  180. stbc:1,
  181. ldpc:1,
  182. sgi:2,
  183. mcs:4,
  184. ofdma:1,
  185. tones_in_ru:12,
  186. valid:1;
  187. uint32_t tsf;
  188. uint32_t ppdu_id;
  189. uint8_t transmit_cnt;
  190. uint8_t tid;
  191. uint16_t peer_id;
  192. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF)
  193. uint32_t buffer_timestamp:19;
  194. #endif
  195. };
  196. /**
  197. * struct hal_tx_desc_comp_s - hal tx completion descriptor contents
  198. * @desc: Transmit status information from descriptor
  199. */
  200. struct hal_tx_desc_comp_s {
  201. uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS];
  202. };
  203. /*
  204. * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW)
  205. * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit
  206. * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit
  207. * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC
  208. * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128
  209. * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC
  210. * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI
  211. * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128
  212. * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER
  213. * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256
  214. * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128
  215. * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256
  216. * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4
  217. */
  218. enum hal_tx_encrypt_type {
  219. HAL_TX_ENCRYPT_TYPE_WEP_40 = 0,
  220. HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 ,
  221. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2,
  222. HAL_TX_ENCRYPT_TYPE_WEP_128 = 3,
  223. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4,
  224. HAL_TX_ENCRYPT_TYPE_WAPI = 5,
  225. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6,
  226. HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7,
  227. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8,
  228. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9,
  229. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10,
  230. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11,
  231. };
  232. /*
  233. * enum hal_tx_encap_type - Encapsulation type that HW will perform
  234. * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type
  235. * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type
  236. * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet
  237. * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame
  238. */
  239. enum hal_tx_encap_type {
  240. HAL_TX_ENCAP_TYPE_RAW = 0,
  241. HAL_TX_ENCAP_TYPE_NWIFI = 1,
  242. HAL_TX_ENCAP_TYPE_ETHERNET = 2,
  243. HAL_TX_ENCAP_TYPE_802_3 = 3,
  244. };
  245. /**
  246. * enum hal_tx_tqm_release_reason - TQM Release reason codes
  247. *
  248. * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received
  249. * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated
  250. * by SW
  251. * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus
  252. * initiated by SW
  253. * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus
  254. * initiated by SW
  255. * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or
  256. * “Remove_aged_msdus” initiated by SW
  257. * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that
  258. * remove reason is fw_reason1
  259. * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that
  260. * remove reason is fw_reason2
  261. * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that
  262. * remove reason is fw_reason3
  263. * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that
  264. * remove reason is remove disable queue
  265. * @HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING: Remove command from fw to remove
  266. * all mpdu until 1st non-match
  267. * @HAL_TX_TQM_RR_DROP_THRESHOLD: Dropped due to drop threshold criteria
  268. * @HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE: Dropped due to link desc not available
  269. * @HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU: Dropped due drop bit set or null flow
  270. * @HAL_TX_TQM_RR_MULTICAST_DROP: Dropped due mcast drop set for VDEV
  271. *
  272. */
  273. enum hal_tx_tqm_release_reason {
  274. HAL_TX_TQM_RR_FRAME_ACKED,
  275. HAL_TX_TQM_RR_REM_CMD_REM,
  276. HAL_TX_TQM_RR_REM_CMD_TX,
  277. HAL_TX_TQM_RR_REM_CMD_NOTX,
  278. HAL_TX_TQM_RR_REM_CMD_AGED,
  279. HAL_TX_TQM_RR_FW_REASON1,
  280. HAL_TX_TQM_RR_FW_REASON2,
  281. HAL_TX_TQM_RR_FW_REASON3,
  282. HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE,
  283. HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING,
  284. HAL_TX_TQM_RR_DROP_THRESHOLD,
  285. HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE,
  286. HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU,
  287. HAL_TX_TQM_RR_MULTICAST_DROP,
  288. };
  289. /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports
  290. * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table
  291. * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table
  292. */
  293. enum hal_tx_dscp_tid_table_id {
  294. HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT,
  295. HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE,
  296. };
  297. /*---------------------------------------------------------------------------
  298. Function declarations and documentation
  299. ---------------------------------------------------------------------------*/
  300. /*---------------------------------------------------------------------------
  301. Tx MSDU Extension Descriptor accessor APIs
  302. ---------------------------------------------------------------------------*/
  303. /**
  304. * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag
  305. * @desc: Handle to Tx MSDU Extension Descriptor
  306. * @tso_en: bool value set to true if TSO is enabled
  307. *
  308. * Return: none
  309. */
  310. static inline void hal_tx_ext_desc_set_tso_enable(void *desc,
  311. uint8_t tso_en)
  312. {
  313. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE) |=
  314. HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TSO_ENABLE, tso_en);
  315. }
  316. /**
  317. * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags
  318. * @desc: Handle to Tx MSDU Extension Descriptor
  319. * @falgs: 32-bit word with all TSO flags consolidated
  320. *
  321. * Return: none
  322. */
  323. static inline void hal_tx_ext_desc_set_tso_flags(void *desc,
  324. uint32_t tso_flags)
  325. {
  326. HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE, 0) =
  327. tso_flags;
  328. }
  329. /**
  330. * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload
  331. * @desc: Handle to Tx MSDU Extension Descriptor
  332. * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}
  333. * @mask: TCP flag mask. Tcp_flag is inserted into the header
  334. * based on the mask, if tso is enabled
  335. *
  336. * Return: none
  337. */
  338. static inline void hal_tx_ext_desc_set_tcp_flags(void *desc,
  339. uint16_t tcp_flags,
  340. uint16_t mask)
  341. {
  342. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_FLAG) |=
  343. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG, tcp_flags)) |
  344. (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG_MASK, mask)));
  345. }
  346. /**
  347. * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths
  348. * @desc: Handle to Tx MSDU Extension Descriptor
  349. * @l2_len: L2 length for the msdu, if tso is enabled
  350. * @ip_len: IP length for the msdu, if tso is enabled
  351. *
  352. * Return: none
  353. */
  354. static inline void hal_tx_ext_desc_set_msdu_length(void *desc,
  355. uint16_t l2_len,
  356. uint16_t ip_len)
  357. {
  358. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, L2_LENGTH) |=
  359. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, L2_LENGTH, l2_len)) |
  360. (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_LENGTH, ip_len)));
  361. }
  362. /**
  363. * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number
  364. * @desc: Handle to Tx MSDU Extension Descriptor
  365. * @seq_num: Tcp_seq_number for the msdu, if tso is enabled
  366. *
  367. * Return: none
  368. */
  369. static inline void hal_tx_ext_desc_set_tcp_seq(void *desc,
  370. uint32_t seq_num)
  371. {
  372. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER) |=
  373. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER, seq_num)));
  374. }
  375. /**
  376. * hal_tx_ext_desc_set_ip_id() - Set IP Identification field
  377. * @desc: Handle to Tx MSDU Extension Descriptor
  378. * @id: IP Id field for the msdu, if tso is enabled
  379. *
  380. * Return: none
  381. */
  382. static inline void hal_tx_ext_desc_set_ip_id(void *desc,
  383. uint16_t id)
  384. {
  385. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION) |=
  386. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION, id)));
  387. }
  388. /**
  389. * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment
  390. * @desc: Handle to Tx MSDU Extension Descriptor
  391. * @frag_num: Fragment number (value can be 0 to 5)
  392. * @paddr_lo: Lower 32-bit of Buffer Physical address
  393. * @paddr_hi: Upper 32-bit of Buffer Physical address
  394. * @length: Buffer Length
  395. *
  396. * Return: none
  397. */
  398. static inline void hal_tx_ext_desc_set_buffer(void *desc,
  399. uint8_t frag_num,
  400. uint32_t paddr_lo,
  401. uint16_t paddr_hi,
  402. uint16_t length)
  403. {
  404. HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0,
  405. (frag_num << 3)) |=
  406. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo)));
  407. HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32,
  408. (frag_num << 3)) |=
  409. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32,
  410. (paddr_hi))));
  411. HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN,
  412. (frag_num << 3)) |=
  413. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length)));
  414. }
  415. /**
  416. * hal_tx_ext_desc_get_frag_info() - Get the frag_num'th frag iova and len
  417. * @desc: Handle to Tx MSDU Extension Descriptor
  418. * @frag_num: fragment number (value can be 0 to 5)
  419. * @iova: fragment dma address
  420. * @len: fragement Length
  421. *
  422. * Return: None
  423. */
  424. static inline void hal_tx_ext_desc_get_frag_info(void *desc, uint8_t frag_num,
  425. qdf_dma_addr_t *iova,
  426. uint32_t *len)
  427. {
  428. uint64_t iova_hi;
  429. *iova = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION,
  430. BUF0_PTR_31_0, (frag_num << 3));
  431. iova_hi = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION,
  432. BUF0_PTR_39_32, (frag_num << 3));
  433. *iova |= (iova_hi << 32);
  434. *len = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN,
  435. (frag_num << 3));
  436. }
  437. /**
  438. * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length
  439. * @desc: Handle to Tx MSDU Extension Descriptor
  440. * @paddr_lo: Lower 32-bit of Buffer Physical address
  441. * @paddr_hi: Upper 32-bit of Buffer Physical address
  442. * @length: Buffer 0 Length
  443. *
  444. * Return: none
  445. */
  446. static inline void hal_tx_ext_desc_set_buffer0_param(void *desc,
  447. uint32_t paddr_lo,
  448. uint16_t paddr_hi,
  449. uint16_t length)
  450. {
  451. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0) |=
  452. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo)));
  453. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32) |=
  454. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION,
  455. BUF0_PTR_39_32, paddr_hi)));
  456. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN) |=
  457. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length)));
  458. }
  459. /**
  460. * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length
  461. * @desc: Handle to Tx MSDU Extension Descriptor
  462. * @paddr_lo: Lower 32-bit of Buffer Physical address
  463. * @paddr_hi: Upper 32-bit of Buffer Physical address
  464. * @length: Buffer 1 Length
  465. *
  466. * Return: none
  467. */
  468. static inline void hal_tx_ext_desc_set_buffer1_param(void *desc,
  469. uint32_t paddr_lo,
  470. uint16_t paddr_hi,
  471. uint16_t length)
  472. {
  473. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0) |=
  474. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0, paddr_lo)));
  475. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_39_32) |=
  476. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION,
  477. BUF1_PTR_39_32, paddr_hi)));
  478. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_LEN) |=
  479. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_LEN, length)));
  480. }
  481. /**
  482. * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length
  483. * @desc: Handle to Tx MSDU Extension Descriptor
  484. * @paddr_lo: Lower 32-bit of Buffer Physical address
  485. * @paddr_hi: Upper 32-bit of Buffer Physical address
  486. * @length: Buffer 2 Length
  487. *
  488. * Return: none
  489. */
  490. static inline void hal_tx_ext_desc_set_buffer2_param(void *desc,
  491. uint32_t paddr_lo,
  492. uint16_t paddr_hi,
  493. uint16_t length)
  494. {
  495. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0) |=
  496. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0,
  497. paddr_lo)));
  498. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32) |=
  499. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32,
  500. paddr_hi)));
  501. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_LEN) |=
  502. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_LEN, length)));
  503. }
  504. /**
  505. * hal_tx_ext_desc_sync - Commit the descriptor to Hardware
  506. * @desc_cached: Cached descriptor that software maintains
  507. * @hw_desc: Hardware descriptor to be updated
  508. *
  509. * Return: none
  510. */
  511. static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached,
  512. uint8_t *hw_desc)
  513. {
  514. qdf_mem_copy(&hw_desc[0], &desc_cached[0],
  515. HAL_TX_EXT_DESC_WITH_META_DATA);
  516. }
  517. /**
  518. * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag
  519. * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor
  520. *
  521. * Return: tso_enable value in the descriptor
  522. */
  523. static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc)
  524. {
  525. uint32_t *desc = (uint32_t *) hal_tx_ext_desc;
  526. return (*desc & HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK) >>
  527. HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB;
  528. }
  529. /*---------------------------------------------------------------------------
  530. WBM Descriptor accessor APIs for Tx completions
  531. ---------------------------------------------------------------------------*/
  532. /**
  533. * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type
  534. * @hal_desc: completion ring descriptor pointer
  535. *
  536. * This function will return the type of pointer - buffer or descriptor
  537. *
  538. * Return: buffer type
  539. */
  540. static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc)
  541. {
  542. uint32_t comp_desc =
  543. *(uint32_t *) (((uint8_t *) hal_desc) +
  544. HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET);
  545. return (comp_desc & HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK) >>
  546. HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB;
  547. }
  548. #ifdef QCA_WIFI_KIWI
  549. /**
  550. * hal_tx_comp_get_buffer_source() - Get buffer release source value
  551. * @hal_desc: completion ring descriptor pointer
  552. *
  553. * This function will get buffer release source from Tx completion descriptor
  554. *
  555. * Return: buffer release source
  556. */
  557. static inline uint32_t
  558. hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl,
  559. void *hal_desc)
  560. {
  561. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  562. return hal_soc->ops->hal_tx_comp_get_buffer_source(hal_desc);
  563. }
  564. #else
  565. static inline uint32_t
  566. hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl,
  567. void *hal_desc)
  568. {
  569. return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc);
  570. }
  571. #endif
  572. /**
  573. * hal_tx_comp_get_release_reason() - TQM Release reason
  574. * @hal_desc: completion ring descriptor pointer
  575. *
  576. * This function will return the type of pointer - buffer or descriptor
  577. *
  578. * Return: buffer type
  579. */
  580. static inline
  581. uint8_t hal_tx_comp_get_release_reason(void *hal_desc,
  582. hal_soc_handle_t hal_soc_hdl)
  583. {
  584. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  585. return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc);
  586. }
  587. /**
  588. * hal_tx_comp_get_peer_id() - Get peer_id value()
  589. * @hal_desc: completion ring descriptor pointer
  590. *
  591. * This function will get peer_id value from Tx completion descriptor
  592. *
  593. * Return: buffer release source
  594. */
  595. static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc)
  596. {
  597. uint32_t comp_desc =
  598. *(uint32_t *)(((uint8_t *)hal_desc) +
  599. HAL_TX_COMP_SW_PEER_ID_OFFSET);
  600. return (comp_desc & HAL_TX_COMP_SW_PEER_ID_MASK) >>
  601. HAL_TX_COMP_SW_PEER_ID_LSB;
  602. }
  603. /**
  604. * hal_tx_comp_get_tx_status() - Get tx transmission status()
  605. * @hal_desc: completion ring descriptor pointer
  606. *
  607. * This function will get transmit status value from Tx completion descriptor
  608. *
  609. * Return: buffer release source
  610. */
  611. static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc)
  612. {
  613. uint32_t comp_desc =
  614. *(uint32_t *)(((uint8_t *)hal_desc) +
  615. HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET);
  616. return (comp_desc & HAL_TX_COMP_TQM_RELEASE_REASON_MASK) >>
  617. HAL_TX_COMP_TQM_RELEASE_REASON_LSB;
  618. }
  619. /**
  620. * hal_tx_comp_desc_sync() - collect hardware descriptor contents
  621. * @hal_desc: hardware descriptor pointer
  622. * @comp: software descriptor pointer
  623. * @read_status: 0 - Do not read status words from descriptors
  624. * 1 - Enable reading of status words from descriptor
  625. *
  626. * This function will collect hardware release ring element contents and
  627. * translate to software descriptor content
  628. *
  629. * Return: none
  630. */
  631. static inline void hal_tx_comp_desc_sync(void *hw_desc,
  632. struct hal_tx_desc_comp_s *comp,
  633. bool read_status)
  634. {
  635. if (!read_status)
  636. qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN);
  637. else
  638. qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES);
  639. }
  640. /**
  641. * hal_dump_comp_desc() - dump tx completion descriptor
  642. * @hal_desc: hardware descriptor pointer
  643. *
  644. * This function will print tx completion descriptor
  645. *
  646. * Return: none
  647. */
  648. static inline void hal_dump_comp_desc(void *hw_desc)
  649. {
  650. struct hal_tx_desc_comp_s *comp =
  651. (struct hal_tx_desc_comp_s *)hw_desc;
  652. uint32_t i;
  653. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  654. "Current tx completion descriptor is");
  655. for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) {
  656. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  657. "DWORD[i] = 0x%x", comp->desc[i]);
  658. }
  659. }
  660. /**
  661. * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor
  662. * @hal_desc: Hardware (WBM) descriptor pointer
  663. * @htt_desc: Software HTT descriptor pointer
  664. *
  665. * This function will read the HTT structure overlaid on WBM descriptor
  666. * into a cached software descriptor
  667. *
  668. */
  669. static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc)
  670. {
  671. uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET;
  672. qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN);
  673. }
  674. /**
  675. * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG
  676. * @hal_soc_hdl: Handle to HAL SoC structure
  677. * @hal_srng: Handle to HAL SRNG structure
  678. *
  679. * Return: none
  680. */
  681. static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl,
  682. hal_ring_handle_t hal_ring_hdl)
  683. {
  684. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  685. hal_soc->ops->hal_tx_init_data_ring(hal_soc_hdl, hal_ring_hdl);
  686. }
  687. /**
  688. * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table
  689. *
  690. * @soc: HAL SoC context
  691. * @map: DSCP-TID mapping table
  692. * @id: mapping table ID - 0,1
  693. *
  694. * Return: void
  695. */
  696. static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl,
  697. uint8_t *map, uint8_t id)
  698. {
  699. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  700. hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id);
  701. }
  702. /**
  703. * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user
  704. *
  705. * @soc: HAL SoC context
  706. * @map: DSCP-TID mapping table
  707. * @id : MAP ID
  708. * @dscp: DSCP_TID map index
  709. *
  710. * Return: void
  711. */
  712. static inline
  713. void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid,
  714. uint8_t id, uint8_t dscp)
  715. {
  716. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  717. hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp);
  718. }
  719. /**
  720. * hal_tx_comp_get_status() - TQM Release reason
  721. * @hal_desc: completion ring Tx status
  722. *
  723. * This function will parse the WBM completion descriptor and populate in
  724. * HAL structure
  725. *
  726. * Return: none
  727. */
  728. static inline void hal_tx_comp_get_status(void *desc, void *ts,
  729. hal_soc_handle_t hal_soc_hdl)
  730. {
  731. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  732. hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc);
  733. }
  734. /**
  735. * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table
  736. *
  737. * @soc: HAL SoC context
  738. * @map: PCP-TID mapping table
  739. *
  740. * Return: void
  741. */
  742. static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl,
  743. uint8_t *map)
  744. {
  745. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  746. hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map);
  747. }
  748. /**
  749. * hal_tx_update_pcp_tid_map() - Update PCP to TID map table
  750. *
  751. * @soc: HAL SoC context
  752. * @pcp: pcp value
  753. * @tid: tid no
  754. *
  755. * Return: void
  756. */
  757. static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl,
  758. uint8_t pcp, uint8_t tid)
  759. {
  760. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  761. hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, pcp, tid);
  762. }
  763. /**
  764. * hal_tx_set_tidmap_prty() - Configure TIDmap priority
  765. *
  766. * @soc: HAL SoC context
  767. * @val: priority value
  768. *
  769. * Return: void
  770. */
  771. static inline
  772. void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val)
  773. {
  774. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  775. hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val);
  776. }
  777. /**
  778. * hal_get_wbm_internal_error() - wbm internal error
  779. * @hal_desc: completion ring descriptor pointer
  780. *
  781. * This function will return the type of pointer - buffer or descriptor
  782. *
  783. * Return: buffer type
  784. */
  785. static inline
  786. uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc)
  787. {
  788. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  789. return hal_soc->ops->hal_get_wbm_internal_error(hal_desc);
  790. }
  791. #endif /* HAL_TX_H */