hal_be_reo.c 41 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "qdf_module.h"
  20. #include "hal_hw_headers.h"
  21. #include "hal_be_hw_headers.h"
  22. #include "hal_reo.h"
  23. #include "hal_be_reo.h"
  24. #include "hal_be_api.h"
  25. uint32_t hal_get_reo_reg_base_offset_be(void)
  26. {
  27. return REO_REG_REG_BASE;
  28. }
  29. /**
  30. * hal_reo_qdesc_setup - Setup HW REO queue descriptor
  31. *
  32. * @hal_soc: Opaque HAL SOC handle
  33. * @ba_window_size: BlockAck window size
  34. * @start_seq: Starting sequence number
  35. * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
  36. * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
  37. * @tid: TID
  38. *
  39. */
  40. void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl, int tid,
  41. uint32_t ba_window_size,
  42. uint32_t start_seq, void *hw_qdesc_vaddr,
  43. qdf_dma_addr_t hw_qdesc_paddr,
  44. int pn_type, uint8_t vdev_stats_id)
  45. {
  46. uint32_t *reo_queue_desc = (uint32_t *)hw_qdesc_vaddr;
  47. uint32_t *reo_queue_ext_desc;
  48. uint32_t reg_val;
  49. uint32_t pn_enable;
  50. uint32_t pn_size = 0;
  51. qdf_mem_zero(hw_qdesc_vaddr, sizeof(struct rx_reo_queue));
  52. hal_uniform_desc_hdr_setup(reo_queue_desc, HAL_DESC_REO_OWNED,
  53. HAL_REO_QUEUE_DESC);
  54. /* Fixed pattern in reserved bits for debugging */
  55. HAL_DESC_SET_FIELD(reo_queue_desc, UNIFORM_DESCRIPTOR_HEADER,
  56. RESERVED_0A, 0xDDBEEF);
  57. /* This a just a SW meta data and will be copied to REO destination
  58. * descriptors indicated by hardware.
  59. * TODO: Setting TID in this field. See if we should set something else.
  60. */
  61. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  62. RECEIVE_QUEUE_NUMBER, tid);
  63. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  64. VLD, 1);
  65. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  66. ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
  67. HAL_RX_LINK_DESC_CNTR);
  68. /*
  69. * Fields DISABLE_DUPLICATE_DETECTION and SOFT_REORDER_ENABLE will be 0
  70. */
  71. reg_val = TID_TO_WME_AC(tid);
  72. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, AC, reg_val);
  73. if (ba_window_size < 1)
  74. ba_window_size = 1;
  75. /* WAR to get 2k exception in Non BA case.
  76. * Setting window size to 2 to get 2k jump exception
  77. * when we receive aggregates in Non BA case
  78. */
  79. ba_window_size = hal_update_non_ba_win_size(tid, ba_window_size);
  80. /* Set RTY bit for non-BA case. Duplicate detection is currently not
  81. * done by HW in non-BA case if RTY bit is not set.
  82. * TODO: This is a temporary War and should be removed once HW fix is
  83. * made to check and discard duplicates even if RTY bit is not set.
  84. */
  85. if (ba_window_size == 1)
  86. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, RTY, 1);
  87. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, BA_WINDOW_SIZE,
  88. ba_window_size - 1);
  89. switch (pn_type) {
  90. case HAL_PN_WPA:
  91. pn_enable = 1;
  92. pn_size = PN_SIZE_48;
  93. break;
  94. case HAL_PN_WAPI_EVEN:
  95. case HAL_PN_WAPI_UNEVEN:
  96. pn_enable = 1;
  97. pn_size = PN_SIZE_128;
  98. break;
  99. default:
  100. pn_enable = 0;
  101. break;
  102. }
  103. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, PN_CHECK_NEEDED,
  104. pn_enable);
  105. if (pn_type == HAL_PN_WAPI_EVEN)
  106. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  107. PN_SHALL_BE_EVEN, 1);
  108. else if (pn_type == HAL_PN_WAPI_UNEVEN)
  109. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  110. PN_SHALL_BE_UNEVEN, 1);
  111. /*
  112. * TODO: Need to check if PN handling in SW needs to be enabled
  113. * So far this is not a requirement
  114. */
  115. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, PN_SIZE,
  116. pn_size);
  117. /* TODO: Check if RX_REO_QUEUE_IGNORE_AMPDU_FLAG need to be set
  118. * based on BA window size and/or AMPDU capabilities
  119. */
  120. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
  121. IGNORE_AMPDU_FLAG, 1);
  122. if (start_seq <= 0xfff)
  123. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, SSN,
  124. start_seq);
  125. /* TODO: SVLD should be set to 1 if a valid SSN is received in ADDBA,
  126. * but REO is not delivering packets if we set it to 1. Need to enable
  127. * this once the issue is resolved
  128. */
  129. HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, SVLD, 0);
  130. hal_update_stats_counter_index(reo_queue_desc, vdev_stats_id);
  131. /* TODO: Check if we should set start PN for WAPI */
  132. /* TODO: HW queue descriptors are currently allocated for max BA
  133. * window size for all QOS TIDs so that same descriptor can be used
  134. * later when ADDBA request is recevied. This should be changed to
  135. * allocate HW queue descriptors based on BA window size being
  136. * negotiated (0 for non BA cases), and reallocate when BA window
  137. * size changes and also send WMI message to FW to change the REO
  138. * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
  139. */
  140. if (tid == HAL_NON_QOS_TID)
  141. return;
  142. reo_queue_ext_desc = (uint32_t *)
  143. (((struct rx_reo_queue *)reo_queue_desc) + 1);
  144. qdf_mem_zero(reo_queue_ext_desc, 3 *
  145. sizeof(struct rx_reo_queue_ext));
  146. /* Initialize first reo queue extension descriptor */
  147. hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
  148. HAL_DESC_REO_OWNED,
  149. HAL_REO_QUEUE_EXT_DESC);
  150. /* Fixed pattern in reserved bits for debugging */
  151. HAL_DESC_SET_FIELD(reo_queue_ext_desc,
  152. UNIFORM_DESCRIPTOR_HEADER, RESERVED_0A,
  153. 0xADBEEF);
  154. /* Initialize second reo queue extension descriptor */
  155. reo_queue_ext_desc = (uint32_t *)
  156. (((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
  157. hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
  158. HAL_DESC_REO_OWNED,
  159. HAL_REO_QUEUE_EXT_DESC);
  160. /* Fixed pattern in reserved bits for debugging */
  161. HAL_DESC_SET_FIELD(reo_queue_ext_desc,
  162. UNIFORM_DESCRIPTOR_HEADER, RESERVED_0A,
  163. 0xBDBEEF);
  164. /* Initialize third reo queue extension descriptor */
  165. reo_queue_ext_desc = (uint32_t *)
  166. (((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
  167. hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
  168. HAL_DESC_REO_OWNED,
  169. HAL_REO_QUEUE_EXT_DESC);
  170. /* Fixed pattern in reserved bits for debugging */
  171. HAL_DESC_SET_FIELD(reo_queue_ext_desc,
  172. UNIFORM_DESCRIPTOR_HEADER, RESERVED_0A,
  173. 0xCDBEEF);
  174. }
  175. qdf_export_symbol(hal_reo_qdesc_setup_be);
  176. /**
  177. * hal_get_ba_aging_timeout_be - Get BA Aging timeout
  178. *
  179. * @hal_soc: Opaque HAL SOC handle
  180. * @ac: Access category
  181. * @value: window size to get
  182. */
  183. void hal_get_ba_aging_timeout_be(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
  184. uint32_t *value)
  185. {
  186. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  187. switch (ac) {
  188. case WME_AC_BE:
  189. *value = HAL_REG_READ(soc,
  190. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  191. REO_REG_REG_BASE)) / 1000;
  192. break;
  193. case WME_AC_BK:
  194. *value = HAL_REG_READ(soc,
  195. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  196. REO_REG_REG_BASE)) / 1000;
  197. break;
  198. case WME_AC_VI:
  199. *value = HAL_REG_READ(soc,
  200. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  201. REO_REG_REG_BASE)) / 1000;
  202. break;
  203. case WME_AC_VO:
  204. *value = HAL_REG_READ(soc,
  205. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  206. REO_REG_REG_BASE)) / 1000;
  207. break;
  208. default:
  209. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  210. "Invalid AC: %d\n", ac);
  211. }
  212. }
  213. qdf_export_symbol(hal_get_ba_aging_timeout_be);
  214. /**
  215. * hal_set_ba_aging_timeout_be - Set BA Aging timeout
  216. *
  217. * @hal_soc: Opaque HAL SOC handle
  218. * @ac: Access category
  219. * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice
  220. * @value: Input value to set
  221. */
  222. void hal_set_ba_aging_timeout_be(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
  223. uint32_t value)
  224. {
  225. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  226. switch (ac) {
  227. case WME_AC_BE:
  228. HAL_REG_WRITE(soc,
  229. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  230. REO_REG_REG_BASE),
  231. value * 1000);
  232. break;
  233. case WME_AC_BK:
  234. HAL_REG_WRITE(soc,
  235. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  236. REO_REG_REG_BASE),
  237. value * 1000);
  238. break;
  239. case WME_AC_VI:
  240. HAL_REG_WRITE(soc,
  241. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  242. REO_REG_REG_BASE),
  243. value * 1000);
  244. break;
  245. case WME_AC_VO:
  246. HAL_REG_WRITE(soc,
  247. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  248. REO_REG_REG_BASE),
  249. value * 1000);
  250. break;
  251. default:
  252. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  253. "Invalid AC: %d\n", ac);
  254. }
  255. }
  256. qdf_export_symbol(hal_set_ba_aging_timeout_be);
  257. static inline void
  258. hal_reo_cmd_set_descr_addr_be(uint32_t *reo_desc,
  259. enum hal_reo_cmd_type type,
  260. uint32_t paddr_lo,
  261. uint8_t paddr_hi)
  262. {
  263. switch (type) {
  264. case CMD_GET_QUEUE_STATS:
  265. HAL_DESC_64_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS,
  266. RX_REO_QUEUE_DESC_ADDR_31_0, paddr_lo);
  267. HAL_DESC_64_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS,
  268. RX_REO_QUEUE_DESC_ADDR_39_32, paddr_hi);
  269. break;
  270. case CMD_FLUSH_QUEUE:
  271. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_QUEUE,
  272. FLUSH_DESC_ADDR_31_0, paddr_lo);
  273. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_QUEUE,
  274. FLUSH_DESC_ADDR_39_32, paddr_hi);
  275. break;
  276. case CMD_FLUSH_CACHE:
  277. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  278. FLUSH_ADDR_31_0, paddr_lo);
  279. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  280. FLUSH_ADDR_39_32, paddr_hi);
  281. break;
  282. case CMD_UPDATE_RX_REO_QUEUE:
  283. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  284. RX_REO_QUEUE_DESC_ADDR_31_0, paddr_lo);
  285. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  286. RX_REO_QUEUE_DESC_ADDR_39_32, paddr_hi);
  287. break;
  288. default:
  289. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  290. "%s: Invalid REO command type", __func__);
  291. break;
  292. }
  293. }
  294. static inline int
  295. hal_reo_cmd_queue_stats_be(hal_ring_handle_t hal_ring_hdl,
  296. hal_soc_handle_t hal_soc_hdl,
  297. struct hal_reo_cmd_params *cmd)
  298. {
  299. uint32_t *reo_desc, val;
  300. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  301. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  302. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  303. if (!reo_desc) {
  304. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  305. "%s: Out of cmd ring entries", __func__);
  306. hal_srng_access_end(hal_soc, hal_ring_hdl);
  307. return -EBUSY;
  308. }
  309. HAL_SET_TLV_HDR(reo_desc, WIFIREO_GET_QUEUE_STATS_E,
  310. sizeof(struct reo_get_queue_stats));
  311. /*
  312. * Offsets of descriptor fields defined in HW headers start from
  313. * the field after TLV header
  314. */
  315. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  316. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  317. sizeof(struct reo_get_queue_stats) -
  318. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  319. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  320. REO_STATUS_REQUIRED, cmd->std.need_status);
  321. hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_GET_QUEUE_STATS,
  322. cmd->std.addr_lo,
  323. cmd->std.addr_hi);
  324. HAL_DESC_64_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS, CLEAR_STATS,
  325. cmd->u.stats_params.clear);
  326. if (hif_pm_runtime_get(hal_soc->hif_handle,
  327. RTPM_ID_HAL_REO_CMD, true) == 0) {
  328. hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
  329. hif_pm_runtime_put(hal_soc->hif_handle,
  330. RTPM_ID_HAL_REO_CMD);
  331. } else {
  332. hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
  333. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  334. hal_srng_inc_flush_cnt(hal_ring_hdl);
  335. }
  336. val = reo_desc[CMD_HEADER_DW_OFFSET];
  337. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  338. val);
  339. }
  340. static inline int
  341. hal_reo_cmd_flush_queue_be(hal_ring_handle_t hal_ring_hdl,
  342. hal_soc_handle_t hal_soc_hdl,
  343. struct hal_reo_cmd_params *cmd)
  344. {
  345. uint32_t *reo_desc, val;
  346. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  347. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  348. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  349. if (!reo_desc) {
  350. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  351. "%s: Out of cmd ring entries", __func__);
  352. hal_srng_access_end(hal_soc, hal_ring_hdl);
  353. return -EBUSY;
  354. }
  355. HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_QUEUE_E,
  356. sizeof(struct reo_flush_queue));
  357. /*
  358. * Offsets of descriptor fields defined in HW headers start from
  359. * the field after TLV header
  360. */
  361. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  362. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  363. sizeof(struct reo_flush_queue) -
  364. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  365. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  366. REO_STATUS_REQUIRED, cmd->std.need_status);
  367. hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_FLUSH_QUEUE,
  368. cmd->std.addr_lo, cmd->std.addr_hi);
  369. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_QUEUE,
  370. BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH,
  371. cmd->u.fl_queue_params.block_use_after_flush);
  372. if (cmd->u.fl_queue_params.block_use_after_flush) {
  373. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_QUEUE,
  374. BLOCK_RESOURCE_INDEX,
  375. cmd->u.fl_queue_params.index);
  376. }
  377. hal_srng_access_end(hal_soc, hal_ring_hdl);
  378. val = reo_desc[CMD_HEADER_DW_OFFSET];
  379. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  380. val);
  381. }
  382. static inline int
  383. hal_reo_cmd_flush_cache_be(hal_ring_handle_t hal_ring_hdl,
  384. hal_soc_handle_t hal_soc_hdl,
  385. struct hal_reo_cmd_params *cmd)
  386. {
  387. uint32_t *reo_desc, val;
  388. struct hal_reo_cmd_flush_cache_params *cp;
  389. uint8_t index = 0;
  390. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  391. cp = &cmd->u.fl_cache_params;
  392. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  393. /* We need a cache block resource for this operation, and REO HW has
  394. * only 4 such blocking resources. These resources are managed using
  395. * reo_res_bitmap, and we return failure if none is available.
  396. */
  397. if (cp->block_use_after_flush) {
  398. index = hal_find_zero_bit(hal_soc->reo_res_bitmap);
  399. if (index > 3) {
  400. qdf_print("No blocking resource available!");
  401. hal_srng_access_end(hal_soc, hal_ring_hdl);
  402. return -EBUSY;
  403. }
  404. hal_soc->index = index;
  405. }
  406. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  407. if (!reo_desc) {
  408. hal_srng_access_end(hal_soc, hal_ring_hdl);
  409. hal_srng_dump(hal_ring_handle_to_hal_srng(hal_ring_hdl));
  410. return -EBUSY;
  411. }
  412. HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_CACHE_E,
  413. sizeof(struct reo_flush_cache));
  414. /*
  415. * Offsets of descriptor fields defined in HW headers start from
  416. * the field after TLV header
  417. */
  418. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  419. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  420. sizeof(struct reo_flush_cache) -
  421. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  422. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  423. REO_STATUS_REQUIRED, cmd->std.need_status);
  424. hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_FLUSH_CACHE,
  425. cmd->std.addr_lo, cmd->std.addr_hi);
  426. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  427. FORWARD_ALL_MPDUS_IN_QUEUE,
  428. cp->fwd_mpdus_in_queue);
  429. /* set it to 0 for now */
  430. cp->rel_block_index = 0;
  431. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  432. RELEASE_CACHE_BLOCK_INDEX, cp->rel_block_index);
  433. if (cp->block_use_after_flush) {
  434. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  435. CACHE_BLOCK_RESOURCE_INDEX, index);
  436. }
  437. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  438. FLUSH_WITHOUT_INVALIDATE, cp->flush_no_inval);
  439. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE,
  440. BLOCK_CACHE_USAGE_AFTER_FLUSH,
  441. cp->block_use_after_flush);
  442. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_CACHE, FLUSH_ENTIRE_CACHE,
  443. cp->flush_entire_cache);
  444. if (hif_pm_runtime_get(hal_soc->hif_handle,
  445. RTPM_ID_HAL_REO_CMD, true) == 0) {
  446. hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
  447. hif_pm_runtime_put(hal_soc->hif_handle,
  448. RTPM_ID_HAL_REO_CMD);
  449. } else {
  450. hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
  451. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  452. hal_srng_inc_flush_cnt(hal_ring_hdl);
  453. }
  454. val = reo_desc[CMD_HEADER_DW_OFFSET];
  455. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  456. val);
  457. }
  458. static inline int
  459. hal_reo_cmd_unblock_cache_be(hal_ring_handle_t hal_ring_hdl,
  460. hal_soc_handle_t hal_soc_hdl,
  461. struct hal_reo_cmd_params *cmd)
  462. {
  463. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  464. uint32_t *reo_desc, val;
  465. uint8_t index = 0;
  466. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  467. if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) {
  468. index = hal_find_one_bit(hal_soc->reo_res_bitmap);
  469. if (index > 3) {
  470. hal_srng_access_end(hal_soc, hal_ring_hdl);
  471. qdf_print("No blocking resource to unblock!");
  472. return -EBUSY;
  473. }
  474. }
  475. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  476. if (!reo_desc) {
  477. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  478. "%s: Out of cmd ring entries", __func__);
  479. hal_srng_access_end(hal_soc, hal_ring_hdl);
  480. return -EBUSY;
  481. }
  482. HAL_SET_TLV_HDR(reo_desc, WIFIREO_UNBLOCK_CACHE_E,
  483. sizeof(struct reo_unblock_cache));
  484. /*
  485. * Offsets of descriptor fields defined in HW headers start from
  486. * the field after TLV header
  487. */
  488. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  489. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  490. sizeof(struct reo_unblock_cache) -
  491. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  492. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  493. REO_STATUS_REQUIRED, cmd->std.need_status);
  494. HAL_DESC_64_SET_FIELD(reo_desc, REO_UNBLOCK_CACHE,
  495. UNBLOCK_TYPE, cmd->u.unblk_cache_params.type);
  496. if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) {
  497. HAL_DESC_64_SET_FIELD(reo_desc, REO_UNBLOCK_CACHE,
  498. CACHE_BLOCK_RESOURCE_INDEX,
  499. cmd->u.unblk_cache_params.index);
  500. }
  501. hal_srng_access_end(hal_soc, hal_ring_hdl);
  502. val = reo_desc[CMD_HEADER_DW_OFFSET];
  503. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  504. val);
  505. }
  506. static inline int
  507. hal_reo_cmd_flush_timeout_list_be(hal_ring_handle_t hal_ring_hdl,
  508. hal_soc_handle_t hal_soc_hdl,
  509. struct hal_reo_cmd_params *cmd)
  510. {
  511. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  512. uint32_t *reo_desc, val;
  513. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  514. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  515. if (!reo_desc) {
  516. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  517. "%s: Out of cmd ring entries", __func__);
  518. hal_srng_access_end(hal_soc, hal_ring_hdl);
  519. return -EBUSY;
  520. }
  521. HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_TIMEOUT_LIST_E,
  522. sizeof(struct reo_flush_timeout_list));
  523. /*
  524. * Offsets of descriptor fields defined in HW headers start from
  525. * the field after TLV header
  526. */
  527. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  528. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  529. sizeof(struct reo_flush_timeout_list) -
  530. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  531. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  532. REO_STATUS_REQUIRED, cmd->std.need_status);
  533. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST, AC_TIMOUT_LIST,
  534. cmd->u.fl_tim_list_params.ac_list);
  535. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST,
  536. MINIMUM_RELEASE_DESC_COUNT,
  537. cmd->u.fl_tim_list_params.min_rel_desc);
  538. HAL_DESC_64_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST,
  539. MINIMUM_FORWARD_BUF_COUNT,
  540. cmd->u.fl_tim_list_params.min_fwd_buf);
  541. hal_srng_access_end(hal_soc, hal_ring_hdl);
  542. val = reo_desc[CMD_HEADER_DW_OFFSET];
  543. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  544. val);
  545. }
  546. static inline int
  547. hal_reo_cmd_update_rx_queue_be(hal_ring_handle_t hal_ring_hdl,
  548. hal_soc_handle_t hal_soc_hdl,
  549. struct hal_reo_cmd_params *cmd)
  550. {
  551. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  552. uint32_t *reo_desc, val;
  553. struct hal_reo_cmd_update_queue_params *p;
  554. p = &cmd->u.upd_queue_params;
  555. hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
  556. reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
  557. if (!reo_desc) {
  558. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  559. "%s: Out of cmd ring entries", __func__);
  560. hal_srng_access_end(hal_soc, hal_ring_hdl);
  561. return -EBUSY;
  562. }
  563. HAL_SET_TLV_HDR(reo_desc, WIFIREO_UPDATE_RX_REO_QUEUE_E,
  564. sizeof(struct reo_update_rx_reo_queue));
  565. /*
  566. * Offsets of descriptor fields defined in HW headers start from
  567. * the field after TLV header
  568. */
  569. reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
  570. qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
  571. sizeof(struct reo_update_rx_reo_queue) -
  572. (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
  573. HAL_DESC_64_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER,
  574. REO_STATUS_REQUIRED, cmd->std.need_status);
  575. hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_UPDATE_RX_REO_QUEUE,
  576. cmd->std.addr_lo, cmd->std.addr_hi);
  577. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  578. UPDATE_RECEIVE_QUEUE_NUMBER,
  579. p->update_rx_queue_num);
  580. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE, UPDATE_VLD,
  581. p->update_vld);
  582. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  583. UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
  584. p->update_assoc_link_desc);
  585. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  586. UPDATE_DISABLE_DUPLICATE_DETECTION,
  587. p->update_disable_dup_detect);
  588. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  589. UPDATE_DISABLE_DUPLICATE_DETECTION,
  590. p->update_disable_dup_detect);
  591. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  592. UPDATE_SOFT_REORDER_ENABLE,
  593. p->update_soft_reorder_enab);
  594. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  595. UPDATE_AC, p->update_ac);
  596. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  597. UPDATE_BAR, p->update_bar);
  598. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  599. UPDATE_BAR, p->update_bar);
  600. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  601. UPDATE_RTY, p->update_rty);
  602. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  603. UPDATE_CHK_2K_MODE, p->update_chk_2k_mode);
  604. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  605. UPDATE_OOR_MODE, p->update_oor_mode);
  606. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  607. UPDATE_BA_WINDOW_SIZE, p->update_ba_window_size);
  608. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  609. UPDATE_PN_CHECK_NEEDED,
  610. p->update_pn_check_needed);
  611. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  612. UPDATE_PN_SHALL_BE_EVEN, p->update_pn_even);
  613. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  614. UPDATE_PN_SHALL_BE_UNEVEN, p->update_pn_uneven);
  615. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  616. UPDATE_PN_HANDLING_ENABLE,
  617. p->update_pn_hand_enab);
  618. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  619. UPDATE_PN_SIZE, p->update_pn_size);
  620. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  621. UPDATE_IGNORE_AMPDU_FLAG, p->update_ignore_ampdu);
  622. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  623. UPDATE_SVLD, p->update_svld);
  624. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  625. UPDATE_SSN, p->update_ssn);
  626. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  627. UPDATE_SEQ_2K_ERROR_DETECTED_FLAG,
  628. p->update_seq_2k_err_detect);
  629. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  630. UPDATE_PN_VALID, p->update_pn_valid);
  631. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  632. UPDATE_PN, p->update_pn);
  633. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  634. RECEIVE_QUEUE_NUMBER, p->rx_queue_num);
  635. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  636. VLD, p->vld);
  637. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  638. ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
  639. p->assoc_link_desc);
  640. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  641. DISABLE_DUPLICATE_DETECTION,
  642. p->disable_dup_detect);
  643. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  644. SOFT_REORDER_ENABLE, p->soft_reorder_enab);
  645. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE, AC, p->ac);
  646. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  647. BAR, p->bar);
  648. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  649. CHK_2K_MODE, p->chk_2k_mode);
  650. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  651. RTY, p->rty);
  652. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  653. OOR_MODE, p->oor_mode);
  654. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  655. PN_CHECK_NEEDED, p->pn_check_needed);
  656. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  657. PN_SHALL_BE_EVEN, p->pn_even);
  658. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  659. PN_SHALL_BE_UNEVEN, p->pn_uneven);
  660. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  661. PN_HANDLING_ENABLE, p->pn_hand_enab);
  662. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  663. IGNORE_AMPDU_FLAG, p->ignore_ampdu);
  664. if (p->ba_window_size < 1)
  665. p->ba_window_size = 1;
  666. /*
  667. * WAR to get 2k exception in Non BA case.
  668. * Setting window size to 2 to get 2k jump exception
  669. * when we receive aggregates in Non BA case
  670. */
  671. if (p->ba_window_size == 1)
  672. p->ba_window_size++;
  673. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  674. BA_WINDOW_SIZE, p->ba_window_size - 1);
  675. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  676. PN_SIZE, p->pn_size);
  677. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  678. SVLD, p->svld);
  679. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  680. SSN, p->ssn);
  681. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  682. SEQ_2K_ERROR_DETECTED_FLAG, p->seq_2k_err_detect);
  683. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  684. PN_ERROR_DETECTED_FLAG, p->pn_err_detect);
  685. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  686. PN_31_0, p->pn_31_0);
  687. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  688. PN_63_32, p->pn_63_32);
  689. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  690. PN_95_64, p->pn_95_64);
  691. HAL_DESC_64_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE,
  692. PN_127_96, p->pn_127_96);
  693. if (hif_pm_runtime_get(hal_soc->hif_handle,
  694. RTPM_ID_HAL_REO_CMD, false) == 0) {
  695. hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
  696. hif_pm_runtime_put(hal_soc->hif_handle,
  697. RTPM_ID_HAL_REO_CMD);
  698. } else {
  699. hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
  700. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  701. hal_srng_inc_flush_cnt(hal_ring_hdl);
  702. }
  703. val = reo_desc[CMD_HEADER_DW_OFFSET];
  704. return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
  705. val);
  706. }
  707. int hal_reo_send_cmd_be(hal_soc_handle_t hal_soc_hdl,
  708. hal_ring_handle_t hal_ring_hdl,
  709. enum hal_reo_cmd_type cmd,
  710. void *params)
  711. {
  712. struct hal_reo_cmd_params *cmd_params =
  713. (struct hal_reo_cmd_params *)params;
  714. int num = 0;
  715. switch (cmd) {
  716. case CMD_GET_QUEUE_STATS:
  717. num = hal_reo_cmd_queue_stats_be(hal_ring_hdl,
  718. hal_soc_hdl, cmd_params);
  719. break;
  720. case CMD_FLUSH_QUEUE:
  721. num = hal_reo_cmd_flush_queue_be(hal_ring_hdl,
  722. hal_soc_hdl, cmd_params);
  723. break;
  724. case CMD_FLUSH_CACHE:
  725. num = hal_reo_cmd_flush_cache_be(hal_ring_hdl,
  726. hal_soc_hdl, cmd_params);
  727. break;
  728. case CMD_UNBLOCK_CACHE:
  729. num = hal_reo_cmd_unblock_cache_be(hal_ring_hdl,
  730. hal_soc_hdl, cmd_params);
  731. break;
  732. case CMD_FLUSH_TIMEOUT_LIST:
  733. num = hal_reo_cmd_flush_timeout_list_be(hal_ring_hdl,
  734. hal_soc_hdl,
  735. cmd_params);
  736. break;
  737. case CMD_UPDATE_RX_REO_QUEUE:
  738. num = hal_reo_cmd_update_rx_queue_be(hal_ring_hdl,
  739. hal_soc_hdl, cmd_params);
  740. break;
  741. default:
  742. hal_err("Invalid REO command type: %d", cmd);
  743. return -EINVAL;
  744. };
  745. return num;
  746. }
  747. void
  748. hal_reo_queue_stats_status_be(hal_ring_desc_t ring_desc,
  749. void *st_handle,
  750. hal_soc_handle_t hal_soc_hdl)
  751. {
  752. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  753. struct hal_reo_queue_status *st =
  754. (struct hal_reo_queue_status *)st_handle;
  755. uint64_t *reo_desc = (uint64_t *)ring_desc;
  756. uint64_t val;
  757. /*
  758. * Offsets of descriptor fields defined in HW headers start
  759. * from the field after TLV header
  760. */
  761. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  762. /* header */
  763. hal_reo_status_get_header(ring_desc, HAL_REO_QUEUE_STATS_STATUS_TLV,
  764. &(st->header), hal_soc);
  765. /* SSN */
  766. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, SSN)];
  767. st->ssn = HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS, SSN, val);
  768. /* current index */
  769. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  770. CURRENT_INDEX)];
  771. st->curr_idx =
  772. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  773. CURRENT_INDEX, val);
  774. /* PN bits */
  775. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  776. PN_31_0)];
  777. st->pn_31_0 =
  778. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  779. PN_31_0, val);
  780. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  781. PN_63_32)];
  782. st->pn_63_32 =
  783. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  784. PN_63_32, val);
  785. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  786. PN_95_64)];
  787. st->pn_95_64 =
  788. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  789. PN_95_64, val);
  790. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  791. PN_127_96)];
  792. st->pn_127_96 =
  793. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  794. PN_127_96, val);
  795. /* timestamps */
  796. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  797. LAST_RX_ENQUEUE_TIMESTAMP)];
  798. st->last_rx_enq_tstamp =
  799. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  800. LAST_RX_ENQUEUE_TIMESTAMP, val);
  801. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  802. LAST_RX_DEQUEUE_TIMESTAMP)];
  803. st->last_rx_deq_tstamp =
  804. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  805. LAST_RX_DEQUEUE_TIMESTAMP, val);
  806. /* rx bitmap */
  807. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  808. RX_BITMAP_31_0)];
  809. st->rx_bitmap_31_0 =
  810. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  811. RX_BITMAP_31_0, val);
  812. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  813. RX_BITMAP_63_32)];
  814. st->rx_bitmap_63_32 =
  815. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  816. RX_BITMAP_63_32, val);
  817. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  818. RX_BITMAP_95_64)];
  819. st->rx_bitmap_95_64 =
  820. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  821. RX_BITMAP_95_64, val);
  822. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  823. RX_BITMAP_127_96)];
  824. st->rx_bitmap_127_96 =
  825. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  826. RX_BITMAP_127_96, val);
  827. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  828. RX_BITMAP_159_128)];
  829. st->rx_bitmap_159_128 =
  830. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  831. RX_BITMAP_159_128, val);
  832. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  833. RX_BITMAP_191_160)];
  834. st->rx_bitmap_191_160 =
  835. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  836. RX_BITMAP_191_160, val);
  837. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  838. RX_BITMAP_223_192)];
  839. st->rx_bitmap_223_192 =
  840. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  841. RX_BITMAP_223_192, val);
  842. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  843. RX_BITMAP_255_224)];
  844. st->rx_bitmap_255_224 =
  845. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  846. RX_BITMAP_255_224, val);
  847. /* various counts */
  848. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  849. CURRENT_MPDU_COUNT)];
  850. st->curr_mpdu_cnt =
  851. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  852. CURRENT_MPDU_COUNT, val);
  853. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  854. CURRENT_MSDU_COUNT)];
  855. st->curr_msdu_cnt =
  856. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  857. CURRENT_MSDU_COUNT, val);
  858. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  859. TIMEOUT_COUNT)];
  860. st->fwd_timeout_cnt =
  861. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  862. TIMEOUT_COUNT, val);
  863. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  864. FORWARD_DUE_TO_BAR_COUNT)];
  865. st->fwd_bar_cnt =
  866. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  867. FORWARD_DUE_TO_BAR_COUNT, val);
  868. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  869. DUPLICATE_COUNT)];
  870. st->dup_cnt =
  871. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  872. DUPLICATE_COUNT, val);
  873. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  874. FRAMES_IN_ORDER_COUNT)];
  875. st->frms_in_order_cnt =
  876. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  877. FRAMES_IN_ORDER_COUNT, val);
  878. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  879. BAR_RECEIVED_COUNT)];
  880. st->bar_rcvd_cnt =
  881. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  882. BAR_RECEIVED_COUNT, val);
  883. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  884. MPDU_FRAMES_PROCESSED_COUNT)];
  885. st->mpdu_frms_cnt =
  886. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  887. MPDU_FRAMES_PROCESSED_COUNT, val);
  888. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  889. MSDU_FRAMES_PROCESSED_COUNT)];
  890. st->msdu_frms_cnt =
  891. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  892. MSDU_FRAMES_PROCESSED_COUNT, val);
  893. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  894. TOTAL_PROCESSED_BYTE_COUNT)];
  895. st->total_cnt =
  896. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  897. TOTAL_PROCESSED_BYTE_COUNT, val);
  898. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  899. LATE_RECEIVE_MPDU_COUNT)];
  900. st->late_recv_mpdu_cnt =
  901. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  902. LATE_RECEIVE_MPDU_COUNT, val);
  903. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  904. WINDOW_JUMP_2K)];
  905. st->win_jump_2k =
  906. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  907. WINDOW_JUMP_2K, val);
  908. val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  909. HOLE_COUNT)];
  910. st->hole_cnt =
  911. HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
  912. HOLE_COUNT, val);
  913. }
  914. void
  915. hal_reo_flush_queue_status_be(hal_ring_desc_t ring_desc,
  916. void *st_handle,
  917. hal_soc_handle_t hal_soc_hdl)
  918. {
  919. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  920. struct hal_reo_flush_queue_status *st =
  921. (struct hal_reo_flush_queue_status *)st_handle;
  922. uint64_t *reo_desc = (uint64_t *)ring_desc;
  923. uint64_t val;
  924. /*
  925. * Offsets of descriptor fields defined in HW headers start
  926. * from the field after TLV header
  927. */
  928. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  929. /* header */
  930. hal_reo_status_get_header(ring_desc, HAL_REO_FLUSH_QUEUE_STATUS_TLV,
  931. &(st->header), hal_soc);
  932. /* error bit */
  933. val = reo_desc[HAL_OFFSET(REO_FLUSH_QUEUE_STATUS,
  934. ERROR_DETECTED)];
  935. st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS, ERROR_DETECTED,
  936. val);
  937. }
  938. void
  939. hal_reo_flush_cache_status_be(hal_ring_desc_t ring_desc,
  940. void *st_handle,
  941. hal_soc_handle_t hal_soc_hdl)
  942. {
  943. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  944. struct hal_reo_flush_cache_status *st =
  945. (struct hal_reo_flush_cache_status *)st_handle;
  946. uint64_t *reo_desc = (uint64_t *)ring_desc;
  947. uint64_t val;
  948. /*
  949. * Offsets of descriptor fields defined in HW headers start
  950. * from the field after TLV header
  951. */
  952. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  953. /* header */
  954. hal_reo_status_get_header(ring_desc, HAL_REO_FLUSH_CACHE_STATUS_TLV,
  955. &(st->header), hal_soc);
  956. /* error bit */
  957. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  958. ERROR_DETECTED)];
  959. st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS, ERROR_DETECTED,
  960. val);
  961. /* block error */
  962. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  963. BLOCK_ERROR_DETAILS)];
  964. st->block_error = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
  965. BLOCK_ERROR_DETAILS,
  966. val);
  967. if (!st->block_error)
  968. qdf_set_bit(hal_soc->index,
  969. (unsigned long *)&hal_soc->reo_res_bitmap);
  970. /* cache flush status */
  971. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  972. CACHE_CONTROLLER_FLUSH_STATUS_HIT)];
  973. st->cache_flush_status = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
  974. CACHE_CONTROLLER_FLUSH_STATUS_HIT,
  975. val);
  976. /* cache flush descriptor type */
  977. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  978. CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE)];
  979. st->cache_flush_status_desc_type =
  980. HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
  981. CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE,
  982. val);
  983. /* cache flush count */
  984. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  985. CACHE_CONTROLLER_FLUSH_COUNT)];
  986. st->cache_flush_cnt =
  987. HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
  988. CACHE_CONTROLLER_FLUSH_COUNT,
  989. val);
  990. }
  991. void
  992. hal_reo_unblock_cache_status_be(hal_ring_desc_t ring_desc,
  993. hal_soc_handle_t hal_soc_hdl,
  994. void *st_handle)
  995. {
  996. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  997. struct hal_reo_unblk_cache_status *st =
  998. (struct hal_reo_unblk_cache_status *)st_handle;
  999. uint64_t *reo_desc = (uint64_t *)ring_desc;
  1000. uint64_t val;
  1001. /*
  1002. * Offsets of descriptor fields defined in HW headers start
  1003. * from the field after TLV header
  1004. */
  1005. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  1006. /* header */
  1007. hal_reo_status_get_header(ring_desc, HAL_REO_UNBLK_CACHE_STATUS_TLV,
  1008. &st->header, hal_soc);
  1009. /* error bit */
  1010. val = reo_desc[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
  1011. ERROR_DETECTED)];
  1012. st->error = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS,
  1013. ERROR_DETECTED,
  1014. val);
  1015. /* unblock type */
  1016. val = reo_desc[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
  1017. UNBLOCK_TYPE)];
  1018. st->unblock_type = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS,
  1019. UNBLOCK_TYPE,
  1020. val);
  1021. if (!st->error && (st->unblock_type == UNBLOCK_RES_INDEX))
  1022. qdf_clear_bit(hal_soc->index,
  1023. (unsigned long *)&hal_soc->reo_res_bitmap);
  1024. }
  1025. void hal_reo_flush_timeout_list_status_be(hal_ring_desc_t ring_desc,
  1026. void *st_handle,
  1027. hal_soc_handle_t hal_soc_hdl)
  1028. {
  1029. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1030. struct hal_reo_flush_timeout_list_status *st =
  1031. (struct hal_reo_flush_timeout_list_status *)st_handle;
  1032. uint64_t *reo_desc = (uint64_t *)ring_desc;
  1033. uint64_t val;
  1034. /*
  1035. * Offsets of descriptor fields defined in HW headers start
  1036. * from the field after TLV header
  1037. */
  1038. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  1039. /* header */
  1040. hal_reo_status_get_header(ring_desc, HAL_REO_TIMOUT_LIST_STATUS_TLV,
  1041. &(st->header), hal_soc);
  1042. /* error bit */
  1043. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1044. ERROR_DETECTED)];
  1045. st->error = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1046. ERROR_DETECTED,
  1047. val);
  1048. /* list empty */
  1049. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1050. TIMOUT_LIST_EMPTY)];
  1051. st->list_empty = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1052. TIMOUT_LIST_EMPTY,
  1053. val);
  1054. /* release descriptor count */
  1055. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1056. RELEASE_DESC_COUNT)];
  1057. st->rel_desc_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1058. RELEASE_DESC_COUNT,
  1059. val);
  1060. /* forward buf count */
  1061. val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1062. FORWARD_BUF_COUNT)];
  1063. st->fwd_buf_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
  1064. FORWARD_BUF_COUNT,
  1065. val);
  1066. }
  1067. void hal_reo_desc_thres_reached_status_be(hal_ring_desc_t ring_desc,
  1068. void *st_handle,
  1069. hal_soc_handle_t hal_soc_hdl)
  1070. {
  1071. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1072. struct hal_reo_desc_thres_reached_status *st =
  1073. (struct hal_reo_desc_thres_reached_status *)st_handle;
  1074. uint64_t *reo_desc = (uint64_t *)ring_desc;
  1075. uint64_t val;
  1076. /*
  1077. * Offsets of descriptor fields defined in HW headers start
  1078. * from the field after TLV header
  1079. */
  1080. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  1081. /* header */
  1082. hal_reo_status_get_header(ring_desc,
  1083. HAL_REO_DESC_THRES_STATUS_TLV,
  1084. &(st->header), hal_soc);
  1085. /* threshold index */
  1086. val = reo_desc[HAL_OFFSET_QW(
  1087. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1088. THRESHOLD_INDEX)];
  1089. st->thres_index = HAL_GET_FIELD(
  1090. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1091. THRESHOLD_INDEX,
  1092. val);
  1093. /* link desc counters */
  1094. val = reo_desc[HAL_OFFSET_QW(
  1095. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1096. LINK_DESCRIPTOR_COUNTER0)];
  1097. st->link_desc_counter0 = HAL_GET_FIELD(
  1098. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1099. LINK_DESCRIPTOR_COUNTER0,
  1100. val);
  1101. val = reo_desc[HAL_OFFSET_QW(
  1102. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1103. LINK_DESCRIPTOR_COUNTER1)];
  1104. st->link_desc_counter1 = HAL_GET_FIELD(
  1105. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1106. LINK_DESCRIPTOR_COUNTER1,
  1107. val);
  1108. val = reo_desc[HAL_OFFSET_QW(
  1109. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1110. LINK_DESCRIPTOR_COUNTER2)];
  1111. st->link_desc_counter2 = HAL_GET_FIELD(
  1112. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1113. LINK_DESCRIPTOR_COUNTER2,
  1114. val);
  1115. val = reo_desc[HAL_OFFSET_QW(
  1116. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1117. LINK_DESCRIPTOR_COUNTER_SUM)];
  1118. st->link_desc_counter_sum = HAL_GET_FIELD(
  1119. REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  1120. LINK_DESCRIPTOR_COUNTER_SUM,
  1121. val);
  1122. }
  1123. void
  1124. hal_reo_rx_update_queue_status_be(hal_ring_desc_t ring_desc,
  1125. void *st_handle,
  1126. hal_soc_handle_t hal_soc_hdl)
  1127. {
  1128. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1129. struct hal_reo_update_rx_queue_status *st =
  1130. (struct hal_reo_update_rx_queue_status *)st_handle;
  1131. uint64_t *reo_desc = (uint64_t *)ring_desc;
  1132. /*
  1133. * Offsets of descriptor fields defined in HW headers start
  1134. * from the field after TLV header
  1135. */
  1136. reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  1137. /* header */
  1138. hal_reo_status_get_header(ring_desc,
  1139. HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV,
  1140. &(st->header), hal_soc);
  1141. }
  1142. uint8_t hal_get_tlv_hdr_size_be(void)
  1143. {
  1144. return sizeof(struct tlv_32_hdr);
  1145. }