hal_be_api.h 4.8 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_API_H_
  20. #define _HAL_BE_API_H_
  21. #include "hal_hw_headers.h"
  22. #include "hal_rx.h"
  23. struct hal_hw_cc_config {
  24. uint32_t lut_base_addr_31_0;
  25. uint32_t cc_global_en:1,
  26. page_4k_align:1,
  27. cookie_offset_msb:5,
  28. cookie_page_msb:5,
  29. lut_base_addr_39_32:8,
  30. wbm2sw6_cc_en:1,
  31. wbm2sw5_cc_en:1,
  32. wbm2sw4_cc_en:1,
  33. wbm2sw3_cc_en:1,
  34. wbm2sw2_cc_en:1,
  35. wbm2sw1_cc_en:1,
  36. wbm2sw0_cc_en:1,
  37. wbm2fw_cc_en:1,
  38. error_path_cookie_conv_en:1,
  39. release_path_cookie_conv_en:1,
  40. reserved:2;
  41. };
  42. #define HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr) \
  43. ((struct rx_msdu_ext_desc_info *) \
  44. _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
  45. RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
  46. /**
  47. * hal_reo_setup_generic_be - Initialize HW REO block
  48. *
  49. * @hal_soc: Opaque HAL SOC handle
  50. * @reo_params: parameters needed by HAL for REO config
  51. */
  52. void hal_reo_setup_generic_be(struct hal_soc *soc,
  53. void *reoparams);
  54. /**
  55. * hal_rx_msdu_ext_desc_info_get_ptr_be() - Get the msdu extension
  56. * descriptor pointer.
  57. * @msdu_details_ptr: msdu details
  58. *
  59. * Return: msdu exntension descriptor pointer.
  60. */
  61. void *hal_rx_msdu_ext_desc_info_get_ptr_be(void *msdu_details_ptr);
  62. /**
  63. * hal_set_link_desc_addr_be - Setup link descriptor in a buffer_addr_info
  64. * HW structure
  65. *
  66. * @desc: Descriptor entry (from WBM_IDLE_LINK ring)
  67. * @cookie: SW cookie for the buffer/descriptor
  68. * @link_desc_paddr: Physical address of link descriptor entry
  69. * @bm_id: idle link BM id
  70. *
  71. */
  72. void hal_set_link_desc_addr_be(void *desc, uint32_t cookie,
  73. qdf_dma_addr_t link_desc_paddr,
  74. uint8_t bm_id);
  75. /**
  76. * hal_hw_txrx_default_ops_attach_be(): Add default ops for BE chips
  77. * @ hal_soc_hdl: hal_soc handle
  78. *
  79. * Return: None
  80. */
  81. void hal_hw_txrx_default_ops_attach_be(struct hal_soc *soc);
  82. uint32_t hal_tx_comp_get_buffer_source_generic_be(void *hal_desc);
  83. uint8_t hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc);
  84. void hal_rx_wbm_err_info_get_generic_be(void *wbm_desc, void *wbm_er_info1);
  85. /**
  86. * hal_reo_qdesc_setup - Setup HW REO queue descriptor
  87. *
  88. * @hal_soc: Opaque HAL SOC handle
  89. * @ba_window_size: BlockAck window size
  90. * @start_seq: Starting sequence number
  91. * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
  92. * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
  93. * @pn_type: PN type (one of the types defined in 'enum hal_pn_type')
  94. * @vdev_stats_id: vdev_stats_id to be programmed in REO Queue Descriptor
  95. */
  96. void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl,
  97. int tid, uint32_t ba_window_size,
  98. uint32_t start_seq, void *hw_qdesc_vaddr,
  99. qdf_dma_addr_t hw_qdesc_paddr,
  100. int pn_type, uint8_t vdev_stats_id);
  101. /**
  102. * hal_cookie_conversion_reg_cfg_be() - set cookie conversion relevant register
  103. * for REO/WBM
  104. * @soc: HAL soc handle
  105. * @cc_cfg: structure pointer for HW cookie conversion configuration
  106. *
  107. * Return: None
  108. */
  109. void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl,
  110. struct hal_hw_cc_config *cc_cfg);
  111. /**
  112. * hal_reo_ix_remap_value_get() - Calculate reo remap register value from
  113. * ring_id_mask which is used for hash based
  114. * reo distribution
  115. *
  116. * @hal_soc: Handle to HAL SoC structure
  117. * @ring_id_mask: mask value indicating the rx rings 0th bit set indicate
  118. * REO2SW1 is included in hash distribution
  119. *
  120. * Return: REO remap value
  121. */
  122. uint32_t
  123. hal_reo_ix_remap_value_get_be(hal_soc_handle_t hal_soc_hdl,
  124. uint8_t rx_ring_mask);
  125. /**
  126. * hal_reo_ring_remap_value_get_be() - return REO remap value
  127. *
  128. * @ring_id: REO2SW ring id
  129. *
  130. * Return: REO remap value
  131. */
  132. uint8_t
  133. hal_reo_ring_remap_value_get_be(uint8_t rx_ring_id);
  134. /**
  135. * hal_setup_reo_swap() - Set the swap flag for big endian machines
  136. * @soc: HAL soc handle
  137. *
  138. * Return: None
  139. */
  140. void hal_setup_reo_swap(struct hal_soc *soc);
  141. /**
  142. * hal_get_idle_link_bm_id_be() - Get idle link BM id from chid_id
  143. * @chip_id: mlo chip_id
  144. *
  145. * Returns: RBM ID
  146. */
  147. uint8_t hal_get_idle_link_bm_id_be(uint8_t chip_id);
  148. #endif /* _HAL_BE_API_H_ */