dp_be.c 47 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  26. #include "dp_mon_2.0.h"
  27. #endif
  28. #include <hal_be_api.h>
  29. /* Generic AST entry aging timer value */
  30. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  31. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  32. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  33. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  34. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  35. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  36. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  37. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  38. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  39. };
  40. #else
  41. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  42. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  43. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  44. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  45. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  46. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  47. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  48. };
  49. #endif
  50. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  51. {
  52. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  53. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  54. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  55. /* this is used only when dmac mode is enabled */
  56. soc->num_rx_refill_buf_rings = 1;
  57. }
  58. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  59. {
  60. switch (context_type) {
  61. case DP_CONTEXT_TYPE_SOC:
  62. return sizeof(struct dp_soc_be);
  63. case DP_CONTEXT_TYPE_PDEV:
  64. return sizeof(struct dp_pdev_be);
  65. case DP_CONTEXT_TYPE_VDEV:
  66. return sizeof(struct dp_vdev_be);
  67. case DP_CONTEXT_TYPE_PEER:
  68. return sizeof(struct dp_peer_be);
  69. default:
  70. return 0;
  71. }
  72. }
  73. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  74. qdf_size_t dp_mon_get_context_size_be(enum dp_context_type context_type)
  75. {
  76. switch (context_type) {
  77. case DP_CONTEXT_TYPE_MON_SOC:
  78. return sizeof(struct dp_mon_soc_be);
  79. case DP_CONTEXT_TYPE_MON_PDEV:
  80. return sizeof(struct dp_mon_pdev_be);
  81. default:
  82. return 0;
  83. }
  84. }
  85. #else
  86. qdf_size_t dp_mon_get_context_size_be(enum dp_context_type context_type)
  87. {
  88. switch (context_type) {
  89. case DP_CONTEXT_TYPE_MON_SOC:
  90. return sizeof(struct dp_mon_soc);
  91. case DP_CONTEXT_TYPE_MON_PDEV:
  92. return sizeof(struct dp_mon_pdev);
  93. default:
  94. return 0;
  95. }
  96. }
  97. #endif
  98. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  99. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  100. /**
  101. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  102. per wbm2sw ring
  103. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  104. *
  105. * Return: None
  106. */
  107. static inline
  108. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  109. {
  110. cc_cfg->wbm2sw6_cc_en = 1;
  111. cc_cfg->wbm2sw5_cc_en = 1;
  112. cc_cfg->wbm2sw4_cc_en = 1;
  113. cc_cfg->wbm2sw3_cc_en = 1;
  114. cc_cfg->wbm2sw2_cc_en = 1;
  115. /* disable wbm2sw1 hw cc as it's for FW */
  116. cc_cfg->wbm2sw1_cc_en = 0;
  117. cc_cfg->wbm2sw0_cc_en = 1;
  118. cc_cfg->wbm2fw_cc_en = 0;
  119. }
  120. #else
  121. static inline
  122. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  123. {
  124. cc_cfg->wbm2sw6_cc_en = 1;
  125. cc_cfg->wbm2sw5_cc_en = 1;
  126. cc_cfg->wbm2sw4_cc_en = 1;
  127. cc_cfg->wbm2sw3_cc_en = 1;
  128. cc_cfg->wbm2sw2_cc_en = 1;
  129. cc_cfg->wbm2sw1_cc_en = 1;
  130. cc_cfg->wbm2sw0_cc_en = 1;
  131. cc_cfg->wbm2fw_cc_en = 0;
  132. }
  133. #endif
  134. /**
  135. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  136. conversion register
  137. * @soc: SOC handle
  138. * @is_4k_align: page address 4k alignd
  139. *
  140. * Return: None
  141. */
  142. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  143. bool is_4k_align)
  144. {
  145. struct hal_hw_cc_config cc_cfg = { 0 };
  146. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  147. if (soc->cdp_soc.ol_ops->get_con_mode &&
  148. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  149. return;
  150. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  151. dp_info("INI skip HW CC register setting");
  152. return;
  153. }
  154. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  155. cc_cfg.cc_global_en = true;
  156. cc_cfg.page_4k_align = is_4k_align;
  157. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  158. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  159. /* 36th bit should be 1 then HW know this is CMEM address */
  160. cc_cfg.lut_base_addr_39_32 = 0x10;
  161. cc_cfg.error_path_cookie_conv_en = true;
  162. cc_cfg.release_path_cookie_conv_en = true;
  163. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  164. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  165. }
  166. /**
  167. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  168. * @hal_soc_hdl: HAL SOC handle
  169. * @offset: CMEM address
  170. * @value: value to write
  171. *
  172. * Return: None.
  173. */
  174. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  175. uint32_t offset,
  176. uint32_t value)
  177. {
  178. hal_cmem_write(hal_soc_hdl, offset, value);
  179. }
  180. /**
  181. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  182. HW cookie conversion
  183. * @soc: SOC handle
  184. * @cc_ctx: cookie conversion context pointer
  185. *
  186. * Return: 0 in case of success, else error value
  187. */
  188. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  189. {
  190. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  191. dp_info("cmem base 0x%llx, size 0x%llx",
  192. soc->cmem_base, soc->cmem_size);
  193. /* get CMEM for cookie conversion */
  194. if (soc->cmem_size < DP_CC_PPT_MEM_SIZE) {
  195. dp_err("cmem_size %llu bytes < 4K", soc->cmem_size);
  196. return QDF_STATUS_E_RESOURCES;
  197. }
  198. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  199. DP_CC_MEM_OFFSET_IN_CMEM);
  200. return QDF_STATUS_SUCCESS;
  201. }
  202. #else
  203. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  204. bool is_4k_align) {}
  205. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  206. uint32_t offset,
  207. uint32_t value)
  208. { }
  209. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  210. {
  211. return QDF_STATUS_SUCCESS;
  212. }
  213. #endif
  214. QDF_STATUS
  215. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  216. struct dp_hw_cookie_conversion_t *cc_ctx,
  217. uint32_t num_descs,
  218. enum dp_desc_type desc_type,
  219. uint8_t desc_pool_id)
  220. {
  221. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  222. uint32_t num_spt_pages, i = 0;
  223. struct dp_spt_page_desc *spt_desc;
  224. struct qdf_mem_dma_page_t *dma_page;
  225. uint8_t chip_id;
  226. /* estimate how many SPT DDR pages needed */
  227. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  228. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  229. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  230. dp_info("num_spt_pages needed %d", num_spt_pages);
  231. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  232. &cc_ctx->page_pool, qdf_page_size,
  233. num_spt_pages, 0, false);
  234. if (!cc_ctx->page_pool.dma_pages) {
  235. dp_err("spt ddr pages allocation failed");
  236. return QDF_STATUS_E_RESOURCES;
  237. }
  238. cc_ctx->page_desc_base = qdf_mem_malloc(
  239. num_spt_pages * sizeof(struct dp_spt_page_desc));
  240. if (!cc_ctx->page_desc_base) {
  241. dp_err("spt page descs allocation failed");
  242. goto fail_0;
  243. }
  244. chip_id = dp_mlo_get_chip_id(soc);
  245. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  246. desc_type);
  247. /* initial page desc */
  248. spt_desc = cc_ctx->page_desc_base;
  249. dma_page = cc_ctx->page_pool.dma_pages;
  250. while (i < num_spt_pages) {
  251. /* check if page address 4K aligned */
  252. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  253. dp_err("non-4k aligned pages addr %pK",
  254. (void *)dma_page[i].page_p_addr);
  255. goto fail_1;
  256. }
  257. spt_desc[i].page_v_addr =
  258. dma_page[i].page_v_addr_start;
  259. spt_desc[i].page_p_addr =
  260. dma_page[i].page_p_addr;
  261. i++;
  262. }
  263. cc_ctx->total_page_num = num_spt_pages;
  264. qdf_spinlock_create(&cc_ctx->cc_lock);
  265. return QDF_STATUS_SUCCESS;
  266. fail_1:
  267. qdf_mem_free(cc_ctx->page_desc_base);
  268. fail_0:
  269. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  270. &cc_ctx->page_pool, 0, false);
  271. return QDF_STATUS_E_FAILURE;
  272. }
  273. QDF_STATUS
  274. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  275. struct dp_hw_cookie_conversion_t *cc_ctx)
  276. {
  277. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  278. qdf_mem_free(cc_ctx->page_desc_base);
  279. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  280. &cc_ctx->page_pool, 0, false);
  281. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  282. return QDF_STATUS_SUCCESS;
  283. }
  284. QDF_STATUS
  285. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  286. struct dp_hw_cookie_conversion_t *cc_ctx)
  287. {
  288. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  289. uint32_t i = 0;
  290. struct dp_spt_page_desc *spt_desc;
  291. uint32_t ppt_index;
  292. uint32_t ppt_id_start;
  293. if (!cc_ctx->total_page_num) {
  294. dp_err("total page num is 0");
  295. return QDF_STATUS_E_INVAL;
  296. }
  297. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  298. spt_desc = cc_ctx->page_desc_base;
  299. while (i < cc_ctx->total_page_num) {
  300. /* write page PA to CMEM */
  301. dp_hw_cc_cmem_write(soc->hal_soc,
  302. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  303. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  304. (spt_desc[i].page_p_addr >>
  305. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  306. ppt_index = ppt_id_start + i;
  307. spt_desc[i].ppt_index = ppt_index;
  308. be_soc->page_desc_base[ppt_index].page_v_addr =
  309. spt_desc[i].page_v_addr;
  310. i++;
  311. }
  312. return QDF_STATUS_SUCCESS;
  313. }
  314. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  315. QDF_STATUS
  316. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  317. struct dp_hw_cookie_conversion_t *cc_ctx)
  318. {
  319. uint32_t ppt_index;
  320. struct dp_spt_page_desc *spt_desc;
  321. int i = 0;
  322. spt_desc = cc_ctx->page_desc_base;
  323. while (i < cc_ctx->total_page_num) {
  324. ppt_index = spt_desc[i].ppt_index;
  325. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  326. i++;
  327. }
  328. return QDF_STATUS_SUCCESS;
  329. }
  330. #else
  331. QDF_STATUS
  332. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  333. struct dp_hw_cookie_conversion_t *cc_ctx)
  334. {
  335. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  336. uint32_t ppt_index;
  337. struct dp_spt_page_desc *spt_desc;
  338. int i = 0;
  339. spt_desc = cc_ctx->page_desc_base;
  340. while (i < cc_ctx->total_page_num) {
  341. /* reset PA in CMEM to NULL */
  342. dp_hw_cc_cmem_write(soc->hal_soc,
  343. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  344. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  345. 0);
  346. ppt_index = spt_desc[i].ppt_index;
  347. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  348. i++;
  349. }
  350. return QDF_STATUS_SUCCESS;
  351. }
  352. #endif
  353. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  354. {
  355. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  356. int i = 0;
  357. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  358. dp_hw_cookie_conversion_detach(be_soc,
  359. &be_soc->tx_cc_ctx[i]);
  360. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  361. dp_hw_cookie_conversion_detach(be_soc,
  362. &be_soc->rx_cc_ctx[i]);
  363. qdf_mem_free(be_soc->page_desc_base);
  364. be_soc->page_desc_base = NULL;
  365. return QDF_STATUS_SUCCESS;
  366. }
  367. #ifdef WLAN_MLO_MULTI_CHIP
  368. #ifdef WLAN_MCAST_MLO
  369. static inline void
  370. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  371. {
  372. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  373. be_vdev->mcast_primary = false;
  374. be_vdev->seq_num = 0;
  375. dp_tx_mcast_mlo_reinject_routing_set(soc,
  376. (void *)&be_vdev->mcast_primary);
  377. if (vdev->opmode == wlan_op_mode_ap) {
  378. if (vdev->mlo_vdev)
  379. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  380. vdev->vdev_id,
  381. HAL_TX_MCAST_CTRL_DROP);
  382. else
  383. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  384. vdev->vdev_id,
  385. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  386. }
  387. }
  388. static inline void
  389. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  390. {
  391. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  392. be_vdev->seq_num = 0;
  393. be_vdev->mcast_primary = false;
  394. vdev->mlo_vdev = false;
  395. }
  396. #else
  397. static inline void
  398. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  399. {
  400. }
  401. static inline void
  402. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  403. {
  404. }
  405. #endif
  406. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  407. {
  408. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  409. qdf_mem_set(be_vdev->partner_vdev_list,
  410. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  411. CDP_INVALID_VDEV_ID);
  412. }
  413. #else
  414. static inline void
  415. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  416. {
  417. }
  418. static inline void
  419. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  420. {
  421. }
  422. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  423. {
  424. }
  425. #endif
  426. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  427. struct cdp_soc_attach_params *params)
  428. {
  429. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  430. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  431. uint32_t max_tx_rx_desc_num, num_spt_pages;
  432. uint32_t num_entries;
  433. int i = 0;
  434. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  435. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
  436. /* estimate how many SPT DDR pages needed */
  437. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  438. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  439. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  440. be_soc->page_desc_base = qdf_mem_malloc(
  441. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  442. if (!be_soc->page_desc_base) {
  443. dp_err("spt page descs allocation failed");
  444. return QDF_STATUS_E_NOMEM;
  445. }
  446. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  447. qdf_status = dp_hw_cc_cmem_addr_init(soc);
  448. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  449. goto fail;
  450. dp_soc_mlo_fill_params(soc, params);
  451. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  452. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  453. qdf_status =
  454. dp_hw_cookie_conversion_attach(be_soc,
  455. &be_soc->tx_cc_ctx[i],
  456. num_entries,
  457. DP_TX_DESC_TYPE, i);
  458. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  459. goto fail;
  460. }
  461. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  462. num_entries =
  463. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  464. qdf_status =
  465. dp_hw_cookie_conversion_attach(be_soc,
  466. &be_soc->rx_cc_ctx[i],
  467. num_entries,
  468. DP_RX_DESC_BUF_TYPE, i);
  469. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  470. goto fail;
  471. }
  472. return qdf_status;
  473. fail:
  474. dp_soc_detach_be(soc);
  475. return qdf_status;
  476. }
  477. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  478. {
  479. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  480. int i = 0;
  481. dp_tx_deinit_bank_profiles(be_soc);
  482. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  483. dp_hw_cookie_conversion_deinit(be_soc,
  484. &be_soc->tx_cc_ctx[i]);
  485. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  486. dp_hw_cookie_conversion_deinit(be_soc,
  487. &be_soc->rx_cc_ctx[i]);
  488. return QDF_STATUS_SUCCESS;
  489. }
  490. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  491. {
  492. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  493. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  494. int i = 0;
  495. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  496. qdf_status =
  497. dp_hw_cookie_conversion_init(be_soc,
  498. &be_soc->tx_cc_ctx[i]);
  499. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  500. goto fail;
  501. }
  502. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  503. qdf_status =
  504. dp_hw_cookie_conversion_init(be_soc,
  505. &be_soc->rx_cc_ctx[i]);
  506. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  507. goto fail;
  508. }
  509. /* route vdev_id mismatch notification via FW completion */
  510. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  511. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  512. qdf_status = dp_tx_init_bank_profiles(be_soc);
  513. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  514. goto fail;
  515. /* write WBM/REO cookie conversion CFG register */
  516. dp_cc_reg_cfg_init(soc, true);
  517. return qdf_status;
  518. fail:
  519. dp_soc_deinit_be(soc);
  520. return qdf_status;
  521. }
  522. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  523. struct cdp_pdev_attach_params *params)
  524. {
  525. dp_pdev_mlo_fill_params(pdev, params);
  526. return QDF_STATUS_SUCCESS;
  527. }
  528. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  529. {
  530. return QDF_STATUS_SUCCESS;
  531. }
  532. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  533. {
  534. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  535. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  536. struct dp_pdev *pdev = vdev->pdev;
  537. if (vdev->opmode == wlan_op_mode_monitor)
  538. return QDF_STATUS_SUCCESS;
  539. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  540. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  541. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  542. QDF_BUG(0);
  543. return QDF_STATUS_E_FAULT;
  544. }
  545. if (vdev->opmode == wlan_op_mode_sta) {
  546. if (soc->cdp_soc.ol_ops->set_mec_timer)
  547. soc->cdp_soc.ol_ops->set_mec_timer(
  548. soc->ctrl_psoc,
  549. vdev->vdev_id,
  550. DP_AST_AGING_TIMER_DEFAULT_MS);
  551. if (pdev->isolation)
  552. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  553. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  554. else
  555. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  556. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  557. }
  558. dp_mlo_mcast_init(soc, vdev);
  559. dp_mlo_init_ptnr_list(vdev);
  560. return QDF_STATUS_SUCCESS;
  561. }
  562. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  563. {
  564. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  565. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  566. if (vdev->opmode == wlan_op_mode_monitor)
  567. return QDF_STATUS_SUCCESS;
  568. if (vdev->opmode == wlan_op_mode_ap)
  569. dp_mlo_mcast_deinit(soc, vdev);
  570. dp_tx_put_bank_profile(be_soc, be_vdev);
  571. dp_clr_mlo_ptnr_list(soc, vdev);
  572. return QDF_STATUS_SUCCESS;
  573. }
  574. qdf_size_t dp_get_soc_context_size_be(void)
  575. {
  576. return sizeof(struct dp_soc_be);
  577. }
  578. #ifdef NO_RX_PKT_HDR_TLV
  579. /**
  580. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  581. * @soc: Common DP soc handle
  582. *
  583. * Return: QDF_STATUS
  584. */
  585. static QDF_STATUS
  586. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  587. {
  588. int i;
  589. int mac_id;
  590. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  591. struct dp_srng *rx_mac_srng;
  592. QDF_STATUS status = QDF_STATUS_SUCCESS;
  593. /*
  594. * In Beryllium chipset msdu_start, mpdu_end
  595. * and rx_attn are part of msdu_end/mpdu_start
  596. */
  597. htt_tlv_filter.msdu_start = 0;
  598. htt_tlv_filter.mpdu_end = 0;
  599. htt_tlv_filter.attention = 0;
  600. htt_tlv_filter.mpdu_start = 1;
  601. htt_tlv_filter.msdu_end = 1;
  602. htt_tlv_filter.packet = 1;
  603. htt_tlv_filter.packet_header = 1;
  604. htt_tlv_filter.ppdu_start = 0;
  605. htt_tlv_filter.ppdu_end = 0;
  606. htt_tlv_filter.ppdu_end_user_stats = 0;
  607. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  608. htt_tlv_filter.ppdu_end_status_done = 0;
  609. htt_tlv_filter.enable_fp = 1;
  610. htt_tlv_filter.enable_md = 0;
  611. htt_tlv_filter.enable_md = 0;
  612. htt_tlv_filter.enable_mo = 0;
  613. htt_tlv_filter.fp_mgmt_filter = 0;
  614. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  615. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  616. FILTER_DATA_MCAST |
  617. FILTER_DATA_DATA);
  618. htt_tlv_filter.mo_mgmt_filter = 0;
  619. htt_tlv_filter.mo_ctrl_filter = 0;
  620. htt_tlv_filter.mo_data_filter = 0;
  621. htt_tlv_filter.md_data_filter = 0;
  622. htt_tlv_filter.offset_valid = true;
  623. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  624. htt_tlv_filter.rx_mpdu_end_offset = 0;
  625. htt_tlv_filter.rx_msdu_start_offset = 0;
  626. htt_tlv_filter.rx_attn_offset = 0;
  627. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  628. /*Not subscribing rx_pkt_header*/
  629. htt_tlv_filter.rx_header_offset = 0;
  630. htt_tlv_filter.rx_mpdu_start_offset =
  631. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  632. htt_tlv_filter.rx_msdu_end_offset =
  633. hal_rx_msdu_end_offset_get(soc->hal_soc);
  634. for (i = 0; i < MAX_PDEV_CNT; i++) {
  635. struct dp_pdev *pdev = soc->pdev_list[i];
  636. if (!pdev)
  637. continue;
  638. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  639. int mac_for_pdev =
  640. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  641. /*
  642. * Obtain lmac id from pdev to access the LMAC ring
  643. * in soc context
  644. */
  645. int lmac_id =
  646. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  647. pdev->pdev_id);
  648. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  649. if (!rx_mac_srng->hal_srng)
  650. continue;
  651. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  652. rx_mac_srng->hal_srng,
  653. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  654. &htt_tlv_filter);
  655. }
  656. }
  657. return status;
  658. }
  659. #else
  660. /**
  661. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  662. * @soc: Common DP soc handle
  663. *
  664. * Return: QDF_STATUS
  665. */
  666. static QDF_STATUS
  667. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  668. {
  669. int i;
  670. int mac_id;
  671. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  672. struct dp_srng *rx_mac_srng;
  673. QDF_STATUS status = QDF_STATUS_SUCCESS;
  674. /*
  675. * In Beryllium chipset msdu_start, mpdu_end
  676. * and rx_attn are part of msdu_end/mpdu_start
  677. */
  678. htt_tlv_filter.msdu_start = 0;
  679. htt_tlv_filter.mpdu_end = 0;
  680. htt_tlv_filter.attention = 0;
  681. htt_tlv_filter.mpdu_start = 1;
  682. htt_tlv_filter.msdu_end = 1;
  683. htt_tlv_filter.packet = 1;
  684. htt_tlv_filter.packet_header = 1;
  685. htt_tlv_filter.ppdu_start = 0;
  686. htt_tlv_filter.ppdu_end = 0;
  687. htt_tlv_filter.ppdu_end_user_stats = 0;
  688. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  689. htt_tlv_filter.ppdu_end_status_done = 0;
  690. htt_tlv_filter.enable_fp = 1;
  691. htt_tlv_filter.enable_md = 0;
  692. htt_tlv_filter.enable_md = 0;
  693. htt_tlv_filter.enable_mo = 0;
  694. htt_tlv_filter.fp_mgmt_filter = 0;
  695. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  696. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  697. FILTER_DATA_MCAST |
  698. FILTER_DATA_DATA);
  699. htt_tlv_filter.mo_mgmt_filter = 0;
  700. htt_tlv_filter.mo_ctrl_filter = 0;
  701. htt_tlv_filter.mo_data_filter = 0;
  702. htt_tlv_filter.md_data_filter = 0;
  703. htt_tlv_filter.offset_valid = true;
  704. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  705. htt_tlv_filter.rx_mpdu_end_offset = 0;
  706. htt_tlv_filter.rx_msdu_start_offset = 0;
  707. htt_tlv_filter.rx_attn_offset = 0;
  708. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  709. htt_tlv_filter.rx_header_offset =
  710. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  711. htt_tlv_filter.rx_mpdu_start_offset =
  712. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  713. htt_tlv_filter.rx_msdu_end_offset =
  714. hal_rx_msdu_end_offset_get(soc->hal_soc);
  715. dp_info("TLV subscription\n"
  716. "msdu_start %d, mpdu_end %d, attention %d"
  717. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  718. "TLV offsets\n"
  719. "msdu_start %d, mpdu_end %d, attention %d"
  720. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  721. htt_tlv_filter.msdu_start,
  722. htt_tlv_filter.mpdu_end,
  723. htt_tlv_filter.attention,
  724. htt_tlv_filter.mpdu_start,
  725. htt_tlv_filter.msdu_end,
  726. htt_tlv_filter.packet_header,
  727. htt_tlv_filter.packet,
  728. htt_tlv_filter.rx_msdu_start_offset,
  729. htt_tlv_filter.rx_mpdu_end_offset,
  730. htt_tlv_filter.rx_attn_offset,
  731. htt_tlv_filter.rx_mpdu_start_offset,
  732. htt_tlv_filter.rx_msdu_end_offset,
  733. htt_tlv_filter.rx_header_offset,
  734. htt_tlv_filter.rx_packet_offset);
  735. for (i = 0; i < MAX_PDEV_CNT; i++) {
  736. struct dp_pdev *pdev = soc->pdev_list[i];
  737. if (!pdev)
  738. continue;
  739. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  740. int mac_for_pdev =
  741. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  742. /*
  743. * Obtain lmac id from pdev to access the LMAC ring
  744. * in soc context
  745. */
  746. int lmac_id =
  747. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  748. pdev->pdev_id);
  749. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  750. if (!rx_mac_srng->hal_srng)
  751. continue;
  752. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  753. rx_mac_srng->hal_srng,
  754. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  755. &htt_tlv_filter);
  756. }
  757. }
  758. return status;
  759. }
  760. #endif
  761. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  762. /**
  763. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  764. * near-full IRQs.
  765. * @soc: Datapath SoC handle
  766. * @int_ctx: Interrupt context
  767. * @dp_budget: Budget of the work that can be done in the bottom half
  768. *
  769. * Return: work done in the handler
  770. */
  771. static uint32_t
  772. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  773. uint32_t dp_budget)
  774. {
  775. int ring = 0;
  776. int budget = dp_budget;
  777. uint32_t work_done = 0;
  778. uint32_t remaining_quota = dp_budget;
  779. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  780. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  781. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  782. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  783. int rx_near_full_mask = rx_near_full_grp_1_mask |
  784. rx_near_full_grp_2_mask;
  785. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  786. rx_near_full_mask,
  787. tx_ring_near_full_mask);
  788. if (rx_near_full_mask) {
  789. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  790. if (!(rx_near_full_mask & (1 << ring)))
  791. continue;
  792. work_done = dp_rx_nf_process(int_ctx,
  793. soc->reo_dest_ring[ring].hal_srng,
  794. ring, remaining_quota);
  795. if (work_done) {
  796. intr_stats->num_rx_ring_near_full_masks[ring]++;
  797. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  798. rx_near_full_mask, ring,
  799. work_done,
  800. budget);
  801. budget -= work_done;
  802. if (budget <= 0)
  803. goto budget_done;
  804. remaining_quota = budget;
  805. }
  806. }
  807. }
  808. if (tx_ring_near_full_mask) {
  809. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  810. if (!(tx_ring_near_full_mask & (1 << ring)))
  811. continue;
  812. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  813. soc->tx_comp_ring[ring].hal_srng,
  814. ring, remaining_quota);
  815. if (work_done) {
  816. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  817. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  818. tx_ring_near_full_mask, ring,
  819. work_done, budget);
  820. budget -= work_done;
  821. if (budget <= 0)
  822. break;
  823. remaining_quota = budget;
  824. }
  825. }
  826. }
  827. intr_stats->num_near_full_masks++;
  828. budget_done:
  829. return dp_budget - budget;
  830. }
  831. /**
  832. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  833. * state and set the reap_limit appropriately
  834. * as per the near full state
  835. * @soc: Datapath soc handle
  836. * @dp_srng: Datapath handle for SRNG
  837. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  838. * the srng near-full state
  839. *
  840. * Return: 1, if the srng is in near-full state
  841. * 0, if the srng is not in near-full state
  842. */
  843. static int
  844. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  845. struct dp_srng *dp_srng,
  846. int *max_reap_limit)
  847. {
  848. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  849. }
  850. /**
  851. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  852. * near full IRQ handling operations.
  853. * @arch_ops: arch ops handle
  854. *
  855. * Return: none
  856. */
  857. static inline void
  858. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  859. {
  860. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  861. arch_ops->dp_srng_test_and_update_nf_params =
  862. dp_srng_test_and_update_nf_params_be;
  863. }
  864. #else
  865. static inline void
  866. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  867. {
  868. }
  869. #endif
  870. #ifdef WLAN_SUPPORT_PPEDS
  871. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  872. {
  873. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  874. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  875. soc_cfg_ctx = soc->wlan_cfg_ctx;
  876. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  877. return;
  878. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  879. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  880. be_soc->ppe_release_ring.alloc_size,
  881. soc->ctrl_psoc,
  882. WLAN_MD_DP_SRNG_PPE_RELEASE,
  883. "ppe_release_ring");
  884. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  885. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  886. be_soc->ppe2tcl_ring.alloc_size,
  887. soc->ctrl_psoc,
  888. WLAN_MD_DP_SRNG_PPE2TCL,
  889. "ppe2tcl_ring");
  890. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  891. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  892. be_soc->reo2ppe_ring.alloc_size,
  893. soc->ctrl_psoc,
  894. WLAN_MD_DP_SRNG_REO2PPE,
  895. "reo2ppe_ring");
  896. }
  897. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  898. {
  899. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  900. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  901. soc_cfg_ctx = soc->wlan_cfg_ctx;
  902. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  903. return;
  904. dp_srng_free(soc, &be_soc->ppe_release_ring);
  905. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  906. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  907. }
  908. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  909. {
  910. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  911. uint32_t entries;
  912. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  913. soc_cfg_ctx = soc->wlan_cfg_ctx;
  914. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  915. return QDF_STATUS_SUCCESS;
  916. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  917. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  918. entries, 0)) {
  919. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  920. goto fail;
  921. }
  922. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  923. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  924. entries, 0)) {
  925. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  926. goto fail;
  927. }
  928. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  929. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  930. entries, 0)) {
  931. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  932. goto fail;
  933. }
  934. return QDF_STATUS_SUCCESS;
  935. fail:
  936. dp_soc_ppe_srng_free(soc);
  937. return QDF_STATUS_E_NOMEM;
  938. }
  939. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  940. {
  941. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  942. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  943. soc_cfg_ctx = soc->wlan_cfg_ctx;
  944. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  945. return QDF_STATUS_SUCCESS;
  946. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  947. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  948. goto fail;
  949. }
  950. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  951. be_soc->reo2ppe_ring.alloc_size,
  952. soc->ctrl_psoc,
  953. WLAN_MD_DP_SRNG_REO2PPE,
  954. "reo2ppe_ring");
  955. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  956. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  957. goto fail;
  958. }
  959. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  960. be_soc->ppe2tcl_ring.alloc_size,
  961. soc->ctrl_psoc,
  962. WLAN_MD_DP_SRNG_PPE2TCL,
  963. "ppe2tcl_ring");
  964. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  965. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  966. goto fail;
  967. }
  968. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  969. be_soc->ppe_release_ring.alloc_size,
  970. soc->ctrl_psoc,
  971. WLAN_MD_DP_SRNG_PPE_RELEASE,
  972. "ppe_release_ring");
  973. return QDF_STATUS_SUCCESS;
  974. fail:
  975. dp_soc_ppe_srng_deinit(soc);
  976. return QDF_STATUS_E_NOMEM;
  977. }
  978. #else
  979. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  980. {
  981. }
  982. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  983. {
  984. }
  985. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  986. {
  987. return QDF_STATUS_SUCCESS;
  988. }
  989. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  990. {
  991. return QDF_STATUS_SUCCESS;
  992. }
  993. #endif
  994. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  995. {
  996. uint32_t i;
  997. dp_soc_ppe_srng_deinit(soc);
  998. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  999. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1000. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1001. RXDMA_BUF, 0);
  1002. }
  1003. }
  1004. }
  1005. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1006. {
  1007. uint32_t i;
  1008. dp_soc_ppe_srng_free(soc);
  1009. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1010. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1011. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1012. }
  1013. }
  1014. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1015. {
  1016. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1017. uint32_t ring_size;
  1018. uint32_t i;
  1019. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1020. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1021. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1022. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1023. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1024. RXDMA_BUF, ring_size, 0)) {
  1025. dp_err("%pK: dp_srng_alloc failed refill ring",
  1026. soc);
  1027. goto fail;
  1028. }
  1029. }
  1030. }
  1031. if (dp_soc_ppe_srng_alloc(soc)) {
  1032. dp_err("%pK: ppe rings alloc failed",
  1033. soc);
  1034. goto fail;
  1035. }
  1036. return QDF_STATUS_SUCCESS;
  1037. fail:
  1038. dp_soc_srng_free_be(soc);
  1039. return QDF_STATUS_E_NOMEM;
  1040. }
  1041. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1042. {
  1043. int i = 0;
  1044. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1045. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1046. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1047. RXDMA_BUF, 0, 0)) {
  1048. dp_err("%pK: dp_srng_init failed refill ring",
  1049. soc);
  1050. goto fail;
  1051. }
  1052. }
  1053. }
  1054. if (dp_soc_ppe_srng_init(soc)) {
  1055. dp_err("%pK: ppe rings init failed",
  1056. soc);
  1057. goto fail;
  1058. }
  1059. return QDF_STATUS_SUCCESS;
  1060. fail:
  1061. dp_soc_srng_deinit_be(soc);
  1062. return QDF_STATUS_E_NOMEM;
  1063. }
  1064. #ifdef WLAN_FEATURE_11BE_MLO
  1065. static inline unsigned
  1066. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1067. union dp_align_mac_addr *mac_addr)
  1068. {
  1069. uint32_t index;
  1070. index =
  1071. mac_addr->align2.bytes_ab ^
  1072. mac_addr->align2.bytes_cd ^
  1073. mac_addr->align2.bytes_ef;
  1074. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1075. index &= mld_hash_obj->mld_peer_hash.mask;
  1076. return index;
  1077. }
  1078. QDF_STATUS
  1079. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1080. int hash_elems)
  1081. {
  1082. int i, log2;
  1083. if (!mld_hash_obj)
  1084. return QDF_STATUS_E_FAILURE;
  1085. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1086. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1087. log2 = dp_log2_ceil(hash_elems);
  1088. hash_elems = 1 << log2;
  1089. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1090. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1091. /* allocate an array of TAILQ peer object lists */
  1092. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1093. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1094. if (!mld_hash_obj->mld_peer_hash.bins)
  1095. return QDF_STATUS_E_NOMEM;
  1096. for (i = 0; i < hash_elems; i++)
  1097. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1098. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1099. return QDF_STATUS_SUCCESS;
  1100. }
  1101. void
  1102. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1103. {
  1104. if (!mld_hash_obj)
  1105. return;
  1106. if (mld_hash_obj->mld_peer_hash.bins) {
  1107. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1108. mld_hash_obj->mld_peer_hash.bins = NULL;
  1109. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1110. }
  1111. }
  1112. #ifdef WLAN_MLO_MULTI_CHIP
  1113. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1114. {
  1115. /* In case of MULTI chip MLO peer hash table when MLO global object
  1116. * is created, avoid from SOC attach path
  1117. */
  1118. return QDF_STATUS_SUCCESS;
  1119. }
  1120. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1121. {
  1122. }
  1123. #else
  1124. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1125. {
  1126. dp_mld_peer_hash_obj_t mld_hash_obj;
  1127. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1128. if (!mld_hash_obj)
  1129. return QDF_STATUS_E_FAILURE;
  1130. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1131. }
  1132. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1133. {
  1134. dp_mld_peer_hash_obj_t mld_hash_obj;
  1135. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1136. if (!mld_hash_obj)
  1137. return;
  1138. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1139. }
  1140. #endif
  1141. static struct dp_peer *
  1142. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1143. uint8_t *peer_mac_addr,
  1144. int mac_addr_is_aligned,
  1145. enum dp_mod_id mod_id,
  1146. uint8_t vdev_id)
  1147. {
  1148. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1149. uint32_t index;
  1150. struct dp_peer *peer;
  1151. struct dp_vdev *vdev;
  1152. dp_mld_peer_hash_obj_t mld_hash_obj;
  1153. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1154. if (!mld_hash_obj)
  1155. return NULL;
  1156. if (!mld_hash_obj->mld_peer_hash.bins)
  1157. return NULL;
  1158. if (mac_addr_is_aligned) {
  1159. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1160. } else {
  1161. qdf_mem_copy(
  1162. &local_mac_addr_aligned.raw[0],
  1163. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1164. mac_addr = &local_mac_addr_aligned;
  1165. }
  1166. if (vdev_id != DP_VDEV_ALL) {
  1167. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1168. if (!vdev) {
  1169. dp_err("vdev is null\n");
  1170. return NULL;
  1171. }
  1172. } else {
  1173. vdev = NULL;
  1174. }
  1175. /* search mld peer table if no link peer for given mac address */
  1176. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1177. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1178. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1179. hash_list_elem) {
  1180. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1181. if ((vdev_id == DP_VDEV_ALL) || (
  1182. dp_peer_find_mac_addr_cmp(
  1183. &peer->vdev->mld_mac_addr,
  1184. &vdev->mld_mac_addr) == 0)) {
  1185. /* take peer reference before returning */
  1186. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1187. QDF_STATUS_SUCCESS)
  1188. peer = NULL;
  1189. if (vdev)
  1190. dp_vdev_unref_delete(soc, vdev, mod_id);
  1191. qdf_spin_unlock_bh(
  1192. &mld_hash_obj->mld_peer_hash_lock);
  1193. return peer;
  1194. }
  1195. }
  1196. }
  1197. if (vdev)
  1198. dp_vdev_unref_delete(soc, vdev, mod_id);
  1199. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1200. return NULL; /* failure */
  1201. }
  1202. static void
  1203. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1204. {
  1205. uint32_t index;
  1206. struct dp_peer *tmppeer = NULL;
  1207. int found = 0;
  1208. dp_mld_peer_hash_obj_t mld_hash_obj;
  1209. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1210. if (!mld_hash_obj)
  1211. return;
  1212. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1213. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1214. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1215. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1216. hash_list_elem) {
  1217. if (tmppeer == peer) {
  1218. found = 1;
  1219. break;
  1220. }
  1221. }
  1222. QDF_ASSERT(found);
  1223. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1224. hash_list_elem);
  1225. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1226. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1227. }
  1228. static void
  1229. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1230. {
  1231. uint32_t index;
  1232. dp_mld_peer_hash_obj_t mld_hash_obj;
  1233. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1234. if (!mld_hash_obj)
  1235. return;
  1236. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1237. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1238. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1239. DP_MOD_ID_CONFIG))) {
  1240. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1241. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1242. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1243. return;
  1244. }
  1245. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1246. hash_list_elem);
  1247. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1248. }
  1249. #endif
  1250. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1251. defined(WLAN_MCAST_MLO)
  1252. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1253. struct dp_vdev_be *be_vdev,
  1254. cdp_config_param_type val)
  1255. {
  1256. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1257. be_vdev->vdev.pdev->soc);
  1258. hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc;
  1259. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  1260. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1261. if (be_vdev->mcast_primary) {
  1262. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1263. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1264. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128,
  1265. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1266. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1267. dp_tx_mcast_mlo_reinject_routing_set,
  1268. (void *)&be_vdev->mcast_primary);
  1269. } else {
  1270. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1271. HAL_TX_MCAST_CTRL_DROP);
  1272. }
  1273. }
  1274. #else
  1275. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1276. struct dp_vdev_be *be_vdev,
  1277. cdp_config_param_type val)
  1278. {
  1279. }
  1280. #endif
  1281. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1282. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1283. uint8_t tx_ring_id,
  1284. uint8_t bm_id)
  1285. {
  1286. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1287. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1288. bm_id);
  1289. }
  1290. #else
  1291. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1292. uint8_t tx_ring_id,
  1293. uint8_t bm_id)
  1294. {
  1295. }
  1296. #endif
  1297. #ifdef WLAN_MLO_MULTI_CHIP
  1298. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1299. struct cdp_peer_setup_info *setup_info,
  1300. enum cdp_host_reo_dest_ring *reo_dest,
  1301. bool *hash_based,
  1302. uint8_t *lmac_peer_id_msb)
  1303. {
  1304. struct dp_soc *soc = vdev->pdev->soc;
  1305. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1306. uint8_t default_rx_ring_id;
  1307. uint8_t chip_id;
  1308. if (!be_soc->mlo_enabled)
  1309. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  1310. hash_based);
  1311. chip_id = be_soc->mlo_chip_id;
  1312. default_rx_ring_id =
  1313. wlan_cfg_mlo_default_rx_ring_get_by_chip_id(soc->wlan_cfg_ctx,
  1314. chip_id);
  1315. *reo_dest = hal_reo_ring_remap_value_get_be(default_rx_ring_id);
  1316. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1317. *lmac_peer_id_msb =
  1318. wlan_cfg_mlo_lmac_peer_id_msb_get_by_chip_id(soc->wlan_cfg_ctx,
  1319. chip_id);
  1320. }
  1321. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1322. uint32_t *remap0,
  1323. uint32_t *remap1,
  1324. uint32_t *remap2)
  1325. {
  1326. uint8_t rx_ring_mask;
  1327. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1328. if (!be_soc->mlo_enabled)
  1329. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1330. rx_ring_mask =
  1331. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 0);
  1332. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1333. rx_ring_mask =
  1334. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 1);
  1335. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1336. rx_ring_mask =
  1337. wlan_cfg_mlo_rx_ring_map_get_by_chip_id(soc->wlan_cfg_ctx, 2);
  1338. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, rx_ring_mask);
  1339. return true;
  1340. }
  1341. #else
  1342. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1343. struct cdp_peer_setup_info *setup_info,
  1344. enum cdp_host_reo_dest_ring *reo_dest,
  1345. bool *hash_based,
  1346. uint8_t *lmac_peer_id_msb)
  1347. {
  1348. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  1349. }
  1350. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1351. uint32_t *remap0,
  1352. uint32_t *remap1,
  1353. uint32_t *remap2)
  1354. {
  1355. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1356. }
  1357. #endif
  1358. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1359. struct dp_vdev *vdev,
  1360. enum cdp_vdev_param_type param,
  1361. cdp_config_param_type val)
  1362. {
  1363. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1364. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1365. switch (param) {
  1366. case CDP_TX_ENCAP_TYPE:
  1367. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1368. case CDP_UPDATE_TDLS_FLAGS:
  1369. dp_tx_update_bank_profile(be_soc, be_vdev);
  1370. break;
  1371. case CDP_ENABLE_CIPHER:
  1372. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1373. dp_tx_update_bank_profile(be_soc, be_vdev);
  1374. break;
  1375. case CDP_SET_MCAST_VDEV:
  1376. dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val);
  1377. break;
  1378. default:
  1379. dp_warn("invalid param %d", param);
  1380. break;
  1381. }
  1382. return QDF_STATUS_SUCCESS;
  1383. }
  1384. #ifdef WLAN_FEATURE_11BE_MLO
  1385. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1386. static inline void
  1387. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1388. {
  1389. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1390. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1391. /*
  1392. * Double the peers since we use ML indication bit
  1393. * alongwith peer_id to find peers.
  1394. */
  1395. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1396. }
  1397. #else
  1398. static inline void
  1399. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1400. {
  1401. soc->max_peer_id =
  1402. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1403. }
  1404. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1405. #else
  1406. static inline void
  1407. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1408. {
  1409. soc->max_peer_id = soc->max_peers;
  1410. }
  1411. #endif /* WLAN_FEATURE_11BE_MLO */
  1412. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1413. {
  1414. }
  1415. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1416. {
  1417. dp_soc_max_peer_id_set(soc);
  1418. return QDF_STATUS_SUCCESS;
  1419. }
  1420. #ifdef WLAN_FEATURE_11BE_MLO
  1421. #ifdef WLAN_MCAST_MLO
  1422. static inline void
  1423. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1424. {
  1425. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1426. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1427. }
  1428. #else /* WLAN_MCAST_MLO */
  1429. static inline void
  1430. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1431. {
  1432. }
  1433. #endif /* WLAN_MCAST_MLO */
  1434. static inline void
  1435. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1436. {
  1437. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  1438. arch_ops->mlo_peer_find_hash_detach =
  1439. dp_mlo_peer_find_hash_detach_wrapper;
  1440. arch_ops->mlo_peer_find_hash_attach =
  1441. dp_mlo_peer_find_hash_attach_wrapper;
  1442. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1443. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1444. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1445. }
  1446. #else /* WLAN_FEATURE_11BE_MLO */
  1447. static inline void
  1448. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1449. {
  1450. }
  1451. #endif /* WLAN_FEATURE_11BE_MLO */
  1452. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  1453. {
  1454. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1455. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  1456. arch_ops->dp_rx_process = dp_rx_process_be;
  1457. arch_ops->tx_comp_get_params_from_hal_desc =
  1458. dp_tx_comp_get_params_from_hal_desc_be;
  1459. arch_ops->dp_tx_process_htt_completion =
  1460. dp_tx_process_htt_completion_be;
  1461. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  1462. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  1463. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  1464. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  1465. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  1466. dp_wbm_get_rx_desc_from_hal_desc_be;
  1467. #endif
  1468. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  1469. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  1470. arch_ops->dp_rx_desc_cookie_2_va =
  1471. dp_rx_desc_cookie_2_va_be;
  1472. arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
  1473. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  1474. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  1475. arch_ops->txrx_soc_init = dp_soc_init_be;
  1476. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  1477. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  1478. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  1479. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  1480. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  1481. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  1482. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  1483. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  1484. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  1485. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  1486. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  1487. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  1488. arch_ops->dp_rx_peer_metadata_peer_id_get =
  1489. dp_rx_peer_metadata_peer_id_get_be;
  1490. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  1491. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  1492. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  1493. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  1494. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  1495. dp_initialize_arch_ops_be_mlo(arch_ops);
  1496. arch_ops->dp_peer_rx_reorder_queue_setup =
  1497. dp_peer_rx_reorder_queue_setup_be;
  1498. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  1499. dp_init_near_full_arch_ops_be(arch_ops);
  1500. }