msm_cvp_platform.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/debugfs.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/init.h>
  9. #include <linux/ioctl.h>
  10. #include <linux/list.h>
  11. #include <linux/module.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/slab.h>
  15. #include <linux/types.h>
  16. #include <linux/version.h>
  17. #include <linux/io.h>
  18. #include <soc/qcom/of_common.h>
  19. #include "msm_cvp_internal.h"
  20. #include "msm_cvp_debug.h"
  21. #include "cvp_hfi_api.h"
  22. #include "cvp_hfi.h"
  23. #define UBWC_CONFIG(mco, mlo, hbo, bslo, bso, rs, mc, ml, hbb, bsl, bsp) \
  24. { \
  25. .override_bit_info.max_channel_override = mco, \
  26. .override_bit_info.mal_length_override = mlo, \
  27. .override_bit_info.hb_override = hbo, \
  28. .override_bit_info.bank_swzl_level_override = bslo, \
  29. .override_bit_info.bank_spreading_override = bso, \
  30. .override_bit_info.reserved = rs, \
  31. .max_channels = mc, \
  32. .mal_length = ml, \
  33. .highest_bank_bit = hbb, \
  34. .bank_swzl_level = bsl, \
  35. .bank_spreading = bsp, \
  36. }
  37. static struct msm_cvp_common_data default_common_data[] = {
  38. {
  39. .key = "qcom,auto-pil",
  40. .value = 1,
  41. },
  42. };
  43. static struct msm_cvp_common_data sm8450_common_data[] = {
  44. {
  45. .key = "qcom,pm-qos-latency-us",
  46. .value = 50,
  47. },
  48. {
  49. .key = "qcom,sw-power-collapse",
  50. .value = 1,
  51. },
  52. {
  53. .key = "qcom,domain-attr-non-fatal-faults",
  54. .value = 1,
  55. },
  56. {
  57. .key = "qcom,max-secure-instances",
  58. .value = 2, /*
  59. * As per design driver allows 3rd
  60. * instance as well since the secure
  61. * flags were updated later for the
  62. * current instance. Hence total
  63. * secure sessions would be
  64. * max-secure-instances + 1.
  65. */
  66. },
  67. {
  68. .key = "qcom,max-ssr-allowed",
  69. .value = 1, /*
  70. * Maxinum number of SSR before BUG_ON
  71. */
  72. },
  73. {
  74. .key = "qcom,power-collapse-delay",
  75. .value = 3000,
  76. },
  77. {
  78. .key = "qcom,hw-resp-timeout",
  79. .value = 2000,
  80. },
  81. {
  82. .key = "qcom,dsp-resp-timeout",
  83. .value = 1000,
  84. },
  85. {
  86. .key = "qcom,debug-timeout",
  87. .value = 0,
  88. },
  89. {
  90. .key = "qcom,dsp-enabled",
  91. .value = 1,
  92. }
  93. };
  94. static struct msm_cvp_common_data sm8550_common_data[] = {
  95. {
  96. .key = "qcom,pm-qos-latency-us",
  97. .value = 50,
  98. },
  99. {
  100. .key = "qcom,sw-power-collapse",
  101. .value = 1,
  102. },
  103. {
  104. .key = "qcom,domain-attr-non-fatal-faults",
  105. .value = 0,
  106. },
  107. {
  108. .key = "qcom,max-secure-instances",
  109. .value = 2, /*
  110. * As per design driver allows 3rd
  111. * instance as well since the secure
  112. * flags were updated later for the
  113. * current instance. Hence total
  114. * secure sessions would be
  115. * max-secure-instances + 1.
  116. */
  117. },
  118. {
  119. .key = "qcom,max-ssr-allowed",
  120. .value = 1, /*
  121. * Maxinum number of SSR before BUG_ON
  122. */
  123. },
  124. {
  125. .key = "qcom,power-collapse-delay",
  126. .value = 3000,
  127. },
  128. {
  129. .key = "qcom,hw-resp-timeout",
  130. .value = 2000,
  131. },
  132. {
  133. .key = "qcom,dsp-resp-timeout",
  134. .value = 1000,
  135. },
  136. {
  137. .key = "qcom,debug-timeout",
  138. .value = 0,
  139. },
  140. {
  141. .key = "qcom,dsp-enabled",
  142. .value = 1,
  143. }
  144. };
  145. static struct msm_cvp_common_data sm8550_tvm_common_data[] = {
  146. {
  147. .key = "qcom,pm-qos-latency-us",
  148. .value = 50,
  149. },
  150. {
  151. .key = "qcom,sw-power-collapse",
  152. .value = 0,
  153. },
  154. {
  155. .key = "qcom,domain-attr-non-fatal-faults",
  156. .value = 0,
  157. },
  158. {
  159. .key = "qcom,max-secure-instances",
  160. .value = 2, /*
  161. * As per design driver allows 3rd
  162. * instance as well since the secure
  163. * flags were updated later for the
  164. * current instance. Hence total
  165. * secure sessions would be
  166. * max-secure-instances + 1.
  167. */
  168. },
  169. {
  170. .key = "qcom,max-ssr-allowed",
  171. .value = 1, /*
  172. * Maxinum number of SSR before BUG_ON
  173. */
  174. },
  175. {
  176. .key = "qcom,power-collapse-delay",
  177. .value = 3000,
  178. },
  179. {
  180. .key = "qcom,hw-resp-timeout",
  181. .value = 2000,
  182. },
  183. {
  184. .key = "qcom,dsp-resp-timeout",
  185. .value = 1000,
  186. },
  187. {
  188. .key = "qcom,debug-timeout",
  189. .value = 0,
  190. },
  191. {
  192. .key = "qcom,dsp-enabled",
  193. .value = 0,
  194. }
  195. };
  196. static struct msm_cvp_common_data sm8650_common_data[] = {
  197. {
  198. .key = "qcom,pm-qos-latency-us",
  199. .value = 50,
  200. },
  201. {
  202. .key = "qcom,sw-power-collapse",
  203. .value = 1,
  204. },
  205. {
  206. .key = "qcom,domain-attr-non-fatal-faults",
  207. .value = 0,
  208. },
  209. {
  210. .key = "qcom,max-secure-instances",
  211. .value = 2, /*
  212. * As per design driver allows 3rd
  213. * instance as well since the secure
  214. * flags were updated later for the
  215. * current instance. Hence total
  216. * secure sessions would be
  217. * max-secure-instances + 1.
  218. */
  219. },
  220. {
  221. .key = "qcom,max-ssr-allowed",
  222. .value = 1, /*
  223. * Maxinum number of SSR before BUG_ON
  224. */
  225. },
  226. {
  227. .key = "qcom,power-collapse-delay",
  228. .value = 3000,
  229. },
  230. {
  231. .key = "qcom,hw-resp-timeout",
  232. .value = 2000,
  233. },
  234. {
  235. .key = "qcom,dsp-resp-timeout",
  236. .value = 1000,
  237. },
  238. {
  239. .key = "qcom,debug-timeout",
  240. .value = 0,
  241. },
  242. {
  243. .key = "qcom,dsp-enabled",
  244. .value = 1,
  245. },
  246. {
  247. .key = "qcom,qos_noc_rge_niu_offset",
  248. .value = 0x0,
  249. },
  250. {
  251. .key = "qcom,qos_noc_gce_vadl_tof_niu_offset",
  252. .value = 0x0,
  253. },
  254. {
  255. .key = "qcom,qos_noc_cdm_niu_offset",
  256. .value = 0x0,
  257. },
  258. {
  259. .key = "qcom,noc_core_err_offset",
  260. .value = 0xA000,
  261. },
  262. {
  263. .key = "qcom,noc_main_sidebandmanager_offset",
  264. .value = 0x6E00,
  265. }
  266. };
  267. static struct msm_cvp_common_data sm7650_common_data[] = {
  268. {
  269. .key = "qcom,pm-qos-latency-us",
  270. .value = 50,
  271. },
  272. {
  273. .key = "qcom,sw-power-collapse",
  274. .value = 1,
  275. },
  276. {
  277. .key = "qcom,domain-attr-non-fatal-faults",
  278. .value = 0,
  279. },
  280. {
  281. .key = "qcom,max-secure-instances",
  282. .value = 2,
  283. },
  284. {
  285. .key = "qcom,max-ssr-allowed",
  286. .value = 1,
  287. },
  288. {
  289. .key = "qcom,power-collapse-delay",
  290. .value = 3000,
  291. },
  292. {
  293. .key = "qcom,hw-resp-timeout",
  294. .value = 2000,
  295. },
  296. {
  297. .key = "qcom,dsp-resp-timeout",
  298. .value = 1000,
  299. },
  300. {
  301. .key = "qcom,debug-timeout",
  302. .value = 0,
  303. },
  304. {
  305. .key = "qcom,dsp-enabled",
  306. .value = 1,
  307. },
  308. {
  309. .key = "qcom,qos_noc_rge_niu_offset",
  310. .value = 0x200,
  311. },
  312. {
  313. .key = "qcom,qos_noc_gce_vadl_tof_niu_offset",
  314. .value = 0xE00,
  315. },
  316. {
  317. .key = "qcom,qos_noc_cdm_niu_offset",
  318. .value = 0x1A00,
  319. },
  320. {
  321. .key = "qcom,noc_core_err_offset",
  322. .value = 0x0,
  323. },
  324. {
  325. .key = "qcom,noc_main_sidebandmanager_offset",
  326. .value = 0x0,
  327. }
  328. };
  329. /* Default UBWC config for LPDDR5 */
  330. static struct msm_cvp_ubwc_config_data kona_ubwc_data[] = {
  331. UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 16, 0, 0),
  332. };
  333. static struct msm_cvp_qos_setting waipio_noc_qos = {
  334. .axi_qos = 0x99,
  335. .prioritylut_low = 0x22222222,
  336. .prioritylut_high = 0x33333333,
  337. .urgency_low = 0x1022,
  338. .dangerlut_low = 0x0,
  339. .safelut_low = 0xffff,
  340. };
  341. static struct msm_cvp_qos_setting lanai_noc_qos = {
  342. .axi_qos = 0x99,
  343. .prioritylut_low = 0x33333333,
  344. .prioritylut_high = 0x33333333,
  345. .urgency_low = 0x1033,
  346. .urgency_low_ro = 0x1003,
  347. .dangerlut_low = 0x0,
  348. .safelut_low = 0xffff,
  349. };
  350. static struct msm_cvp_qos_setting palawan_noc_qos = {
  351. .axi_qos = 0x99,
  352. .prioritylut_low = 0x33333333,
  353. .prioritylut_high = 0x33333333,
  354. .urgency_low = 0x1003,
  355. .urgency_low_ro = 0x1003,
  356. .dangerlut_low = 0x0,
  357. .safelut_low = 0xffff,
  358. };
  359. static struct msm_cvp_platform_data default_data = {
  360. .common_data = default_common_data,
  361. .common_data_length = ARRAY_SIZE(default_common_data),
  362. .sku_version = 0,
  363. .vpu_ver = VPU_VERSION_5,
  364. .ubwc_config = 0x0,
  365. .noc_qos = 0x0,
  366. .vm_id = 1,
  367. };
  368. static struct msm_cvp_platform_data sm8450_data = {
  369. .common_data = sm8450_common_data,
  370. .common_data_length = ARRAY_SIZE(sm8450_common_data),
  371. .sku_version = 0,
  372. .vpu_ver = VPU_VERSION_5,
  373. .ubwc_config = kona_ubwc_data,
  374. .noc_qos = &waipio_noc_qos,
  375. .vm_id = 1,
  376. };
  377. static struct msm_cvp_platform_data sm8550_data = {
  378. .common_data = sm8550_common_data,
  379. .common_data_length = ARRAY_SIZE(sm8550_common_data),
  380. .sku_version = 0,
  381. .vpu_ver = VPU_VERSION_5,
  382. .ubwc_config = kona_ubwc_data, /*Reuse Kona setting*/
  383. .noc_qos = &waipio_noc_qos, /*Reuse Waipio setting*/
  384. .vm_id = 1,
  385. };
  386. static struct msm_cvp_platform_data sm8550_tvm_data = {
  387. .common_data = sm8550_tvm_common_data,
  388. .common_data_length = ARRAY_SIZE(sm8550_tvm_common_data),
  389. .sku_version = 0,
  390. .vpu_ver = VPU_VERSION_5,
  391. .ubwc_config = kona_ubwc_data, /*Reuse Kona setting*/
  392. .noc_qos = &waipio_noc_qos, /*Reuse Waipio setting*/
  393. .vm_id = 2,
  394. };
  395. static struct msm_cvp_platform_data sm8650_data = {
  396. .common_data = sm8650_common_data,
  397. .common_data_length = ARRAY_SIZE(sm8650_common_data),
  398. .sku_version = 0,
  399. .vpu_ver = VPU_VERSION_5,
  400. .ubwc_config = kona_ubwc_data, /*Reuse Kona setting*/
  401. .noc_qos = &lanai_noc_qos,
  402. .vm_id = 1,
  403. };
  404. static struct msm_cvp_platform_data sm7650_data = {
  405. .common_data = sm7650_common_data,
  406. .common_data_length = ARRAY_SIZE(sm7650_common_data),
  407. .sku_version = 0,
  408. .vpu_ver = VPU_VERSION_5,
  409. .ubwc_config = kona_ubwc_data, /*Reuse Kona setting*/
  410. .noc_qos = &palawan_noc_qos,
  411. .vm_id = 1,
  412. };
  413. static const struct of_device_id msm_cvp_dt_match[] = {
  414. {
  415. .compatible = "qcom,waipio-cvp",
  416. .data = &sm8450_data,
  417. },
  418. {
  419. .compatible = "qcom,kalama-cvp",
  420. .data = &sm8550_data,
  421. },
  422. {
  423. .compatible = "qcom,kalama-cvp-tvm",
  424. .data = &sm8550_tvm_data,
  425. },
  426. {
  427. .compatible = "qcom,pineapple-cvp",
  428. .data = &sm8650_data,
  429. },
  430. {
  431. .compatible = "qcom,cliffs-cvp",
  432. .data = &sm7650_data,
  433. },
  434. {},
  435. };
  436. /*
  437. * WARN: name field CAN NOT hold more than 23 chars
  438. * excluding the ending '\0'
  439. *
  440. * NOTE: the def entry index for the command packet is
  441. * "the packet type - HFI_CMD_SESSION_CVP_START"
  442. */
  443. const struct msm_cvp_hfi_defs cvp_hfi_defs[MAX_PKT_IDX] = {
  444. [HFI_CMD_SESSION_CVP_DFS_CONFIG - HFI_CMD_SESSION_CVP_START] =
  445. {
  446. .size = HFI_DFS_CONFIG_CMD_SIZE,
  447. .type = HFI_CMD_SESSION_CVP_DFS_CONFIG,
  448. .is_config_pkt = true,
  449. .resp = HAL_NO_RESP,
  450. .name = "DFS",
  451. },
  452. [HFI_CMD_SESSION_CVP_DFS_FRAME - HFI_CMD_SESSION_CVP_START] =
  453. {
  454. .size = HFI_DFS_FRAME_CMD_SIZE,
  455. .type = HFI_CMD_SESSION_CVP_DFS_FRAME,
  456. .is_config_pkt = false,
  457. .resp = HAL_NO_RESP,
  458. .name = "DFS_FRAME",
  459. .force_kernel_fence = false,
  460. },
  461. [HFI_CMD_SESSION_CVP_SGM_OF_CONFIG - HFI_CMD_SESSION_CVP_START] =
  462. {
  463. .size = 0xFFFFFFFF,
  464. .type = HFI_CMD_SESSION_CVP_SGM_OF_CONFIG,
  465. .is_config_pkt = true,
  466. .resp = HAL_NO_RESP,
  467. .name = "SGM_OF",
  468. },
  469. [HFI_CMD_SESSION_CVP_SGM_OF_FRAME - HFI_CMD_SESSION_CVP_START] =
  470. {
  471. .size = 0xFFFFFFFF,
  472. .type = HFI_CMD_SESSION_CVP_SGM_OF_FRAME,
  473. .is_config_pkt = false,
  474. .resp = HAL_NO_RESP,
  475. .name = "SGM_OF_FRAME",
  476. .force_kernel_fence = false,
  477. },
  478. [HFI_CMD_SESSION_CVP_WARP_NCC_CONFIG - HFI_CMD_SESSION_CVP_START] =
  479. {
  480. .size = 0xFFFFFFFF,
  481. .type = HFI_CMD_SESSION_CVP_WARP_NCC_CONFIG,
  482. .is_config_pkt = true,
  483. .resp = HAL_NO_RESP,
  484. .name = "WARP_NCC",
  485. },
  486. [HFI_CMD_SESSION_CVP_WARP_NCC_FRAME - HFI_CMD_SESSION_CVP_START] =
  487. {
  488. .size = 0xFFFFFFFF,
  489. .type = HFI_CMD_SESSION_CVP_WARP_NCC_FRAME,
  490. .is_config_pkt = false,
  491. .resp = HAL_NO_RESP,
  492. .name = "WARP_NCC_FRAME",
  493. .force_kernel_fence = false,
  494. },
  495. [HFI_CMD_SESSION_CVP_WARP_CONFIG - HFI_CMD_SESSION_CVP_START] =
  496. {
  497. .size = 0xFFFFFFFF,
  498. .type = HFI_CMD_SESSION_CVP_WARP_CONFIG,
  499. .is_config_pkt = true,
  500. .resp = HAL_NO_RESP,
  501. .name = "WARP",
  502. },
  503. [HFI_CMD_SESSION_CVP_WARP_DS_PARAMS - HFI_CMD_SESSION_CVP_START] =
  504. {
  505. .size = 0xFFFFFFFF,
  506. .type = HFI_CMD_SESSION_CVP_WARP_DS_PARAMS,
  507. .is_config_pkt = true,
  508. .resp = HAL_NO_RESP,
  509. .name = "WARP_DS_PARAMS",
  510. },
  511. [HFI_CMD_SESSION_CVP_WARP_FRAME - HFI_CMD_SESSION_CVP_START] =
  512. {
  513. .size = 0xFFFFFFFF,
  514. .type = HFI_CMD_SESSION_CVP_WARP_FRAME,
  515. .is_config_pkt = false,
  516. .resp = HAL_NO_RESP,
  517. .name = "WARP_FRAME",
  518. .force_kernel_fence = true,
  519. },
  520. [HFI_CMD_SESSION_CVP_DMM_CONFIG - HFI_CMD_SESSION_CVP_START] =
  521. {
  522. .size = HFI_DMM_CONFIG_CMD_SIZE,
  523. .type = HFI_CMD_SESSION_CVP_DMM_CONFIG,
  524. .is_config_pkt = true,
  525. .resp = HAL_NO_RESP,
  526. .name = "DMM",
  527. },
  528. [HFI_CMD_SESSION_CVP_DMM_PARAMS - HFI_CMD_SESSION_CVP_START] =
  529. {
  530. .size = 0xFFFFFFFF,
  531. .type = HFI_CMD_SESSION_CVP_DMM_PARAMS,
  532. .is_config_pkt = true,
  533. .resp = HAL_NO_RESP,
  534. .name = "DMM_PARAMS",
  535. },
  536. [HFI_CMD_SESSION_CVP_DMM_FRAME - HFI_CMD_SESSION_CVP_START] =
  537. {
  538. .size = HFI_DMM_FRAME_CMD_SIZE,
  539. .type = HFI_CMD_SESSION_CVP_DMM_FRAME,
  540. .is_config_pkt = false,
  541. .resp = HAL_NO_RESP,
  542. .name = "DMM_FRAME",
  543. .force_kernel_fence = true,
  544. },
  545. [HFI_CMD_SESSION_CVP_SET_PERSIST_BUFFERS - HFI_CMD_SESSION_CVP_START] =
  546. {
  547. .size = HFI_PERSIST_CMD_SIZE,
  548. .type =HFI_CMD_SESSION_CVP_SET_PERSIST_BUFFERS,
  549. .is_config_pkt = true,
  550. .resp = HAL_NO_RESP,
  551. .name = "SET_PERSIST",
  552. },
  553. [HFI_CMD_SESSION_CVP_RELEASE_PERSIST_BUFFERS - HFI_CMD_SESSION_CVP_START] =
  554. {
  555. .size = 0xffffffff,
  556. .type =HFI_CMD_SESSION_CVP_RELEASE_PERSIST_BUFFERS,
  557. .is_config_pkt = false,
  558. .resp = HAL_NO_RESP,
  559. .name = "REL_PERSIST",
  560. },
  561. [HFI_CMD_SESSION_CVP_DS_CONFIG - HFI_CMD_SESSION_CVP_START] =
  562. {
  563. .size = HFI_DS_CONFIG_CMD_SIZE,
  564. .type = HFI_CMD_SESSION_CVP_DS_CONFIG,
  565. .is_config_pkt = true,
  566. .resp = HAL_NO_RESP,
  567. .name = "DS_CONFIG",
  568. },
  569. [HFI_CMD_SESSION_CVP_DS - HFI_CMD_SESSION_CVP_START] =
  570. {
  571. .size = HFI_DS_CMD_SIZE,
  572. .type =HFI_CMD_SESSION_CVP_DS,
  573. .is_config_pkt = false,
  574. .resp = HAL_NO_RESP,
  575. .name = "DS",
  576. },
  577. [HFI_CMD_SESSION_CVP_CV_TME_CONFIG - HFI_CMD_SESSION_CVP_START] =
  578. {
  579. .size = HFI_OF_CONFIG_CMD_SIZE,
  580. .type =HFI_CMD_SESSION_CVP_CV_TME_CONFIG,
  581. .is_config_pkt = true,
  582. .resp = HAL_NO_RESP,
  583. .name = "TME",
  584. },
  585. [HFI_CMD_SESSION_CVP_CV_TME_FRAME - HFI_CMD_SESSION_CVP_START] =
  586. {
  587. .size = HFI_OF_FRAME_CMD_SIZE,
  588. .type =HFI_CMD_SESSION_CVP_CV_TME_FRAME,
  589. .is_config_pkt = false,
  590. .resp = HAL_NO_RESP,
  591. .name = "TME_FRAME",
  592. .force_kernel_fence = false,
  593. },
  594. [HFI_CMD_SESSION_CVP_CV_ODT_CONFIG - HFI_CMD_SESSION_CVP_START] =
  595. {
  596. .size = HFI_ODT_CONFIG_CMD_SIZE,
  597. .type = HFI_CMD_SESSION_CVP_CV_ODT_CONFIG,
  598. .is_config_pkt = true,
  599. .resp = HAL_NO_RESP,
  600. .name = "ODT",
  601. },
  602. [HFI_CMD_SESSION_CVP_CV_ODT_FRAME - HFI_CMD_SESSION_CVP_START] =
  603. {
  604. .size = HFI_ODT_FRAME_CMD_SIZE,
  605. .type =HFI_CMD_SESSION_CVP_CV_ODT_FRAME,
  606. .is_config_pkt = false,
  607. .resp = HAL_NO_RESP,
  608. .name = "ODT_FRAME",
  609. },
  610. [HFI_CMD_SESSION_CVP_CV_OD_CONFIG - HFI_CMD_SESSION_CVP_START] =
  611. {
  612. .size = HFI_OD_CONFIG_CMD_SIZE,
  613. .type = HFI_CMD_SESSION_CVP_CV_OD_CONFIG,
  614. .is_config_pkt = true,
  615. .resp = HAL_NO_RESP,
  616. .name = "OD",
  617. },
  618. [HFI_CMD_SESSION_CVP_CV_OD_FRAME - HFI_CMD_SESSION_CVP_START] =
  619. {
  620. .size = HFI_OD_FRAME_CMD_SIZE,
  621. .type = HFI_CMD_SESSION_CVP_CV_OD_FRAME,
  622. .is_config_pkt = false,
  623. .resp = HAL_NO_RESP,
  624. .name = "OD_FRAME",
  625. },
  626. [HFI_CMD_SESSION_CVP_NCC_CONFIG - HFI_CMD_SESSION_CVP_START] =
  627. {
  628. .size = HFI_NCC_CONFIG_CMD_SIZE,
  629. .type =HFI_CMD_SESSION_CVP_NCC_CONFIG,
  630. .is_config_pkt = true,
  631. .resp = HAL_NO_RESP,
  632. .name = "NCC",
  633. },
  634. [HFI_CMD_SESSION_CVP_NCC_FRAME - HFI_CMD_SESSION_CVP_START] =
  635. {
  636. .size = HFI_NCC_FRAME_CMD_SIZE,
  637. .type = HFI_CMD_SESSION_CVP_NCC_FRAME,
  638. .is_config_pkt = false,
  639. .resp = HAL_NO_RESP,
  640. .name = "NCC_FRAME",
  641. .force_kernel_fence = false,
  642. },
  643. [HFI_CMD_SESSION_CVP_ICA_CONFIG - HFI_CMD_SESSION_CVP_START] =
  644. {
  645. .size = HFI_ICA_CONFIG_CMD_SIZE,
  646. .type = HFI_CMD_SESSION_CVP_ICA_CONFIG,
  647. .is_config_pkt = true,
  648. .resp = HAL_NO_RESP,
  649. .name = "ICA",
  650. },
  651. [HFI_CMD_SESSION_CVP_ICA_FRAME - HFI_CMD_SESSION_CVP_START] =
  652. {
  653. .size = HFI_ICA_FRAME_CMD_SIZE,
  654. .type =HFI_CMD_SESSION_CVP_ICA_FRAME,
  655. .is_config_pkt = false,
  656. .resp = HAL_NO_RESP,
  657. .name = "ICA_FRAME",
  658. .force_kernel_fence = false,
  659. },
  660. [HFI_CMD_SESSION_CVP_HCD_CONFIG - HFI_CMD_SESSION_CVP_START] =
  661. {
  662. .size = HFI_HCD_CONFIG_CMD_SIZE,
  663. .type = HFI_CMD_SESSION_CVP_HCD_CONFIG,
  664. .is_config_pkt = true,
  665. .resp = HAL_NO_RESP,
  666. .name = "HCD",
  667. },
  668. [HFI_CMD_SESSION_CVP_HCD_FRAME - HFI_CMD_SESSION_CVP_START] =
  669. {
  670. .size = HFI_HCD_FRAME_CMD_SIZE,
  671. .type = HFI_CMD_SESSION_CVP_HCD_FRAME,
  672. .is_config_pkt = false,
  673. .resp = HAL_NO_RESP,
  674. .name = "HCD_FRAME",
  675. .force_kernel_fence = false,
  676. },
  677. [HFI_CMD_SESSION_CVP_DC_CONFIG - HFI_CMD_SESSION_CVP_START] =
  678. {
  679. .size = HFI_DCM_CONFIG_CMD_SIZE,
  680. .type = HFI_CMD_SESSION_CVP_DC_CONFIG,
  681. .is_config_pkt = true,
  682. .resp = HAL_NO_RESP,
  683. .name = "DC",
  684. },
  685. [HFI_CMD_SESSION_CVP_DC_FRAME - HFI_CMD_SESSION_CVP_START] =
  686. {
  687. .size = HFI_DCM_FRAME_CMD_SIZE,
  688. .type = HFI_CMD_SESSION_CVP_DC_FRAME,
  689. .is_config_pkt = false,
  690. .resp = HAL_NO_RESP,
  691. .name = "DC_FRAME",
  692. .force_kernel_fence = false,
  693. },
  694. [HFI_CMD_SESSION_CVP_DCM_CONFIG - HFI_CMD_SESSION_CVP_START] =
  695. {
  696. .size = HFI_DCM_CONFIG_CMD_SIZE,
  697. .type = HFI_CMD_SESSION_CVP_DCM_CONFIG,
  698. .is_config_pkt = true,
  699. .resp = HAL_NO_RESP,
  700. .name = "DCM",
  701. },
  702. [HFI_CMD_SESSION_CVP_DCM_FRAME - HFI_CMD_SESSION_CVP_START] =
  703. {
  704. .size = HFI_DCM_FRAME_CMD_SIZE,
  705. .type = HFI_CMD_SESSION_CVP_DCM_FRAME,
  706. .is_config_pkt = false,
  707. .resp = HAL_NO_RESP,
  708. .name = "DCM_FRAME",
  709. .force_kernel_fence = false,
  710. },
  711. [HFI_CMD_SESSION_CVP_PYS_HCD_CONFIG - HFI_CMD_SESSION_CVP_START] =
  712. {
  713. .size = HFI_PYS_HCD_CONFIG_CMD_SIZE,
  714. .type = HFI_CMD_SESSION_CVP_PYS_HCD_CONFIG,
  715. .is_config_pkt = true,
  716. .resp = HAL_NO_RESP,
  717. .name = "PYS_HCD",
  718. },
  719. [HFI_CMD_SESSION_CVP_PYS_HCD_FRAME - HFI_CMD_SESSION_CVP_START] =
  720. {
  721. .size = HFI_PYS_HCD_FRAME_CMD_SIZE,
  722. .type = HFI_CMD_SESSION_CVP_PYS_HCD_FRAME,
  723. .is_config_pkt = false,
  724. .resp = HAL_NO_RESP,
  725. .name = "PYS_HCD_FRAME",
  726. .force_kernel_fence = true,
  727. },
  728. [HFI_CMD_SESSION_CVP_SET_MODEL_BUFFERS - HFI_CMD_SESSION_CVP_START] =
  729. {
  730. .size = 0xFFFFFFFF,
  731. .type = HFI_CMD_SESSION_CVP_SET_MODEL_BUFFERS,
  732. .is_config_pkt = true,
  733. .resp = HAL_NO_RESP,
  734. .name = "SET_MODEL",
  735. },
  736. [HFI_CMD_SESSION_CVP_SET_SNAPSHOT_BUFFERS - HFI_CMD_SESSION_CVP_START] =
  737. {
  738. .size = 0xFFFFFFFF,
  739. .type = HFI_CMD_SESSION_CVP_SET_SNAPSHOT_BUFFERS,
  740. .is_config_pkt = false,
  741. .resp = HAL_NO_RESP,
  742. .name = "SET_SNAPSHOT",
  743. },
  744. [HFI_CMD_SESSION_CVP_RELEASE_SNAPSHOT_BUFFERS - HFI_CMD_SESSION_CVP_START] =
  745. {
  746. .size = 0xFFFFFFFF,
  747. .type = HFI_CMD_SESSION_CVP_RELEASE_SNAPSHOT_BUFFERS,
  748. .is_config_pkt = false,
  749. .resp = HAL_NO_RESP,
  750. .name = "REL_SNAPSHOT",
  751. },
  752. [HFI_CMD_SESSION_CVP_SET_SNAPSHOT_MODE - HFI_CMD_SESSION_CVP_START] =
  753. {
  754. .size = 0xFFFFFFFF,
  755. .type = HFI_CMD_SESSION_CVP_SET_SNAPSHOT_MODE,
  756. .is_config_pkt = true,
  757. .resp = HAL_NO_RESP,
  758. .name = "SNAPSHOT_MODE",
  759. },
  760. [HFI_CMD_SESSION_CVP_SNAPSHOT_WRITE_DONE - HFI_CMD_SESSION_CVP_START] =
  761. {
  762. .size = 0xFFFFFFFF,
  763. .type = HFI_CMD_SESSION_CVP_SNAPSHOT_WRITE_DONE,
  764. .is_config_pkt = true,
  765. .resp = HAL_NO_RESP,
  766. .name = "SNAPSHOT_DONE",
  767. },
  768. [HFI_CMD_SESSION_CVP_FD_CONFIG - HFI_CMD_SESSION_CVP_START] =
  769. {
  770. .size = 0xFFFFFFFF,
  771. .type = HFI_CMD_SESSION_CVP_FD_CONFIG,
  772. .is_config_pkt = true,
  773. .resp = HAL_NO_RESP,
  774. .name = "FD",
  775. },
  776. [HFI_CMD_SESSION_CVP_FD_FRAME - HFI_CMD_SESSION_CVP_START] =
  777. {
  778. .size = 0xFFFFFFFF,
  779. .type = HFI_CMD_SESSION_CVP_FD_FRAME,
  780. .is_config_pkt = false,
  781. .resp = HAL_NO_RESP,
  782. .name = "FD_FRAME",
  783. },
  784. [HFI_CMD_SESSION_CVP_XRA_FRAME - HFI_CMD_SESSION_CVP_START] =
  785. {
  786. .size = 0xFFFFFFFF,
  787. .type = HFI_CMD_SESSION_CVP_XRA_FRAME,
  788. .is_config_pkt = false,
  789. .resp = HAL_NO_RESP,
  790. .name = "XRA_FRAME",
  791. },
  792. [HFI_CMD_SESSION_CVP_XRA_CONFIG - HFI_CMD_SESSION_CVP_START] =
  793. {
  794. .size = 0xFFFFFFFF,
  795. .type = HFI_CMD_SESSION_CVP_XRA_CONFIG,
  796. .is_config_pkt = true,
  797. .resp = HAL_NO_RESP,
  798. .name = "XRA_CONFIG",
  799. },
  800. [HFI_CMD_SESSION_CVP_XRA_BLOB_FRAME - HFI_CMD_SESSION_CVP_START] =
  801. {
  802. .size = 0xFFFFFFFF,
  803. .type = HFI_CMD_SESSION_CVP_XRA_BLOB_FRAME,
  804. .is_config_pkt = false,
  805. .resp = HAL_NO_RESP,
  806. .name = "XRA_BLOB_FRAME",
  807. },
  808. [HFI_CMD_SESSION_CVP_XRA_BLOB_CONFIG - HFI_CMD_SESSION_CVP_START] =
  809. {
  810. .size = 0xFFFFFFFF,
  811. .type = HFI_CMD_SESSION_CVP_XRA_BLOB_CONFIG,
  812. .is_config_pkt = true,
  813. .resp = HAL_NO_RESP,
  814. .name = "XRA_BLOB_CONFIG",
  815. },
  816. [HFI_CMD_SESSION_CVP_XRA_PATCH_FRAME - HFI_CMD_SESSION_CVP_START] =
  817. {
  818. .size = 0xFFFFFFFF,
  819. .type = HFI_CMD_SESSION_CVP_XRA_PATCH_FRAME,
  820. .is_config_pkt = false,
  821. .resp = HAL_NO_RESP,
  822. .name = "XRA_PATCH_FRAME",
  823. .force_kernel_fence = false,
  824. },
  825. [HFI_CMD_SESSION_CVP_XRA_PATCH_CONFIG - HFI_CMD_SESSION_CVP_START] =
  826. {
  827. .size = 0xFFFFFFFF,
  828. .type = HFI_CMD_SESSION_CVP_XRA_PATCH_CONFIG,
  829. .is_config_pkt = true,
  830. .resp = HAL_NO_RESP,
  831. .name = "XRA_PATCH_CONFIG",
  832. },
  833. [HFI_CMD_SESSION_CVP_XRA_MATCH_FRAME - HFI_CMD_SESSION_CVP_START] =
  834. {
  835. .size = 0xFFFFFFFF,
  836. .type = HFI_CMD_SESSION_CVP_XRA_MATCH_FRAME,
  837. .is_config_pkt = false,
  838. .resp = HAL_NO_RESP,
  839. .name = "XRA_MATCH_FRAME",
  840. .force_kernel_fence = false,
  841. },
  842. [HFI_CMD_SESSION_CVP_XRA_MATCH_CONFIG - HFI_CMD_SESSION_CVP_START] =
  843. {
  844. .size = 0xFFFFFFFF,
  845. .type = HFI_CMD_SESSION_CVP_XRA_MATCH_CONFIG,
  846. .is_config_pkt = true,
  847. .resp = HAL_NO_RESP,
  848. .name = "XRA_MATCH_CONFIG",
  849. },
  850. [HFI_CMD_SESSION_CVP_RGE_FRAME - HFI_CMD_SESSION_CVP_START] =
  851. {
  852. .size = 0xFFFFFFFF,
  853. .type = HFI_CMD_SESSION_CVP_RGE_FRAME,
  854. .is_config_pkt = false,
  855. .resp = HAL_NO_RESP,
  856. .name = "RGE_FRAME",
  857. .force_kernel_fence = true,
  858. },
  859. [HFI_CMD_SESSION_CVP_RGE_CONFIG - HFI_CMD_SESSION_CVP_START] =
  860. {
  861. .size = 0xFFFFFFFF,
  862. .type = HFI_CMD_SESSION_CVP_RGE_CONFIG,
  863. .is_config_pkt = true,
  864. .resp = HAL_NO_RESP,
  865. .name = "RGE_CONFIG",
  866. },
  867. [HFI_CMD_SESSION_EVA_ITOF_FRAME - HFI_CMD_SESSION_CVP_START] =
  868. {
  869. .size = 0xFFFFFFFF,
  870. .type = HFI_CMD_SESSION_EVA_ITOF_FRAME,
  871. .is_config_pkt = false,
  872. .resp = HAL_NO_RESP,
  873. .name = "ITOF_FRAME",
  874. .force_kernel_fence = true,
  875. },
  876. [HFI_CMD_SESSION_EVA_ITOF_CONFIG - HFI_CMD_SESSION_CVP_START] =
  877. {
  878. .size = 0xFFFFFFFF,
  879. .type = HFI_CMD_SESSION_EVA_ITOF_CONFIG,
  880. .is_config_pkt = true,
  881. .resp = HAL_NO_RESP,
  882. .name = "ITOF_CONFIG",
  883. },
  884. [HFI_CMD_SESSION_EVA_DLFD_FRAME - HFI_CMD_SESSION_CVP_START] =
  885. {
  886. .size = 0xFFFFFFFF,
  887. .type = HFI_CMD_SESSION_EVA_DLFD_FRAME,
  888. .is_config_pkt = false,
  889. .resp = HAL_NO_RESP,
  890. .name = "DLFD_FRAME",
  891. },
  892. [HFI_CMD_SESSION_EVA_DLFD_CONFIG - HFI_CMD_SESSION_CVP_START] =
  893. {
  894. .size = 0xFFFFFFFF,
  895. .type = HFI_CMD_SESSION_EVA_DLFD_CONFIG,
  896. .is_config_pkt = true,
  897. .resp = HAL_NO_RESP,
  898. .name = "DLFD_CONFIG",
  899. },
  900. [HFI_CMD_SESSION_EVA_DLFL_FRAME - HFI_CMD_SESSION_CVP_START] =
  901. {
  902. .size = 0xFFFFFFFF,
  903. .type = HFI_CMD_SESSION_EVA_DLFL_FRAME,
  904. .is_config_pkt = false,
  905. .resp = HAL_NO_RESP,
  906. .name = "DLFL_FRAME",
  907. .force_kernel_fence = false,
  908. },
  909. [HFI_CMD_SESSION_EVA_DLFL_CONFIG - HFI_CMD_SESSION_CVP_START] =
  910. {
  911. .size = 0xFFFFFFFF,
  912. .type = HFI_CMD_SESSION_EVA_DLFL_CONFIG,
  913. .is_config_pkt = true,
  914. .resp = HAL_NO_RESP,
  915. .name = "DLFL_CONFIG",
  916. },
  917. [HFI_CMD_SESSION_CVP_SYNX - HFI_CMD_SESSION_CVP_START] =
  918. {
  919. .size = 0xFFFFFFFF,
  920. .type = HFI_CMD_SESSION_CVP_SYNX,
  921. .is_config_pkt = true,
  922. .resp = HAL_NO_RESP,
  923. .name = "SYNX_TEST",
  924. },
  925. [HFI_CMD_SESSION_EVA_DME_ONLY_CONFIG - HFI_CMD_SESSION_CVP_START] =
  926. {
  927. .size = 0xFFFFFFFF,
  928. .type = HFI_CMD_SESSION_EVA_DME_ONLY_CONFIG,
  929. .is_config_pkt = true,
  930. .resp = HAL_NO_RESP,
  931. .name = "DME_CONFIG",
  932. },
  933. [HFI_CMD_SESSION_EVA_DME_ONLY_FRAME - HFI_CMD_SESSION_CVP_START] =
  934. {
  935. .size = 0xFFFFFFFF,
  936. .type = HFI_CMD_SESSION_EVA_DME_ONLY_FRAME,
  937. .is_config_pkt = false,
  938. .resp = HAL_NO_RESP,
  939. .name = "DME_FRAME",
  940. .force_kernel_fence = true,
  941. },
  942. };
  943. int get_pkt_index(struct cvp_hal_session_cmd_pkt *hdr)
  944. {
  945. if (!hdr || (hdr->packet_type < HFI_CMD_SESSION_CVP_START)
  946. || hdr->packet_type >= (HFI_CMD_SESSION_CVP_START + MAX_PKT_IDX))
  947. return -EINVAL;
  948. if (cvp_hfi_defs[hdr->packet_type - HFI_CMD_SESSION_CVP_START].size)
  949. return (hdr->packet_type - HFI_CMD_SESSION_CVP_START);
  950. return -EINVAL;
  951. }
  952. int get_pkt_fenceoverride(struct cvp_hal_session_cmd_pkt* hdr)
  953. {
  954. return cvp_hfi_defs[hdr->packet_type - HFI_CMD_SESSION_CVP_START].force_kernel_fence;
  955. }
  956. int get_pkt_index_from_type(u32 pkt_type)
  957. {
  958. if ((pkt_type < HFI_CMD_SESSION_CVP_START) ||
  959. pkt_type >= (HFI_CMD_SESSION_CVP_START + MAX_PKT_IDX))
  960. return -EINVAL;
  961. if (cvp_hfi_defs[pkt_type - HFI_CMD_SESSION_CVP_START].size)
  962. return (pkt_type - HFI_CMD_SESSION_CVP_START);
  963. return -EINVAL;
  964. }
  965. MODULE_DEVICE_TABLE(of, msm_cvp_dt_match);
  966. int cvp_of_fdt_get_ddrtype(void)
  967. {
  968. #ifdef FIXED_DDR_TYPE
  969. /* of_fdt_get_ddrtype() is usually unavailable during pre-sil */
  970. return DDR_TYPE_LPDDR5;
  971. #else
  972. return of_fdt_get_ddrtype();
  973. #endif
  974. }
  975. void *cvp_get_drv_data(struct device *dev)
  976. {
  977. struct msm_cvp_platform_data *driver_data;
  978. const struct of_device_id *match;
  979. uint32_t ddr_type = DDR_TYPE_LPDDR5;
  980. driver_data = &default_data;
  981. if (!IS_ENABLED(CONFIG_OF) || !dev->of_node)
  982. goto exit;
  983. match = of_match_node(msm_cvp_dt_match, dev->of_node);
  984. if (!match)
  985. return NULL;
  986. driver_data = (struct msm_cvp_platform_data *)match->data;
  987. if (!strcmp(match->compatible, "qcom,waipio-cvp")) {
  988. ddr_type = cvp_of_fdt_get_ddrtype();
  989. if (ddr_type == -ENOENT) {
  990. dprintk(CVP_ERR,
  991. "Failed to get ddr type, use LPDDR5\n");
  992. }
  993. if (driver_data->ubwc_config &&
  994. (ddr_type == DDR_TYPE_LPDDR4 ||
  995. ddr_type == DDR_TYPE_LPDDR4X))
  996. driver_data->ubwc_config->highest_bank_bit = 15;
  997. dprintk(CVP_CORE, "DDR Type 0x%x hbb 0x%x\n",
  998. ddr_type, driver_data->ubwc_config ?
  999. driver_data->ubwc_config->highest_bank_bit : -1);
  1000. }
  1001. exit:
  1002. return driver_data;
  1003. }