872c22a405
Added QCA5424 target header files based on E2R38 under QCA5424 to make fw-api project compatible to host. Update the CE base address for QCA5424. patch_3: updated the E3R42 hw header files Change-Id: I2c0d42d37faa2082199c8b1f97bac31f1d5ddea5 CRs-Fixed: 3822334
725 lines
34 KiB
C
725 lines
34 KiB
C
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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* SPDX-License-Identifier: ISC
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*/
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#ifndef _PDG_RESPONSE_H_
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#define _PDG_RESPONSE_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "pdg_response_rate_setting.h"
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#define NUM_OF_DWORDS_PDG_RESPONSE 12
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#define NUM_OF_QWORDS_PDG_RESPONSE 6
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struct pdg_response {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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struct pdg_response_rate_setting hw_response_rate_info;
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uint32_t hw_response_tx_duration : 16,
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rx_duration_field : 16;
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uint32_t punctured_response_transmission : 1,
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cca_subband_channel_bonding_mask : 16,
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scrambler_seed_override : 2,
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response_density_valid : 1,
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response_density : 5,
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more_data : 1,
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duration_indication : 1,
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relayed_frame : 1,
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address_indicator : 1,
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bandwidth : 3;
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uint32_t ack_id : 16,
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block_ack_bitmap : 16;
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uint32_t response_frame_type : 4,
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ack_id_ext : 10,
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ftm_en : 1,
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group_id : 6,
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sta_partial_aid : 11;
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uint32_t ndp_ba_start_seq_ctrl : 12,
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active_channel : 3,
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txop_duration_all_ones : 1,
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frame_length : 16;
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#else
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struct pdg_response_rate_setting hw_response_rate_info;
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uint32_t rx_duration_field : 16,
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hw_response_tx_duration : 16;
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uint32_t bandwidth : 3,
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address_indicator : 1,
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relayed_frame : 1,
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duration_indication : 1,
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more_data : 1,
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response_density : 5,
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response_density_valid : 1,
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scrambler_seed_override : 2,
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cca_subband_channel_bonding_mask : 16,
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punctured_response_transmission : 1;
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uint32_t block_ack_bitmap : 16,
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ack_id : 16;
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uint32_t sta_partial_aid : 11,
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group_id : 6,
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ftm_en : 1,
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ack_id_ext : 10,
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response_frame_type : 4;
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uint32_t frame_length : 16,
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txop_duration_all_ones : 1,
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active_channel : 3,
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ndp_ba_start_seq_ctrl : 12;
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#endif
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};
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x000000000000000f
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 32
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff00000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 45
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c0000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 46
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 47
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c00000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
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#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
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#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018
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#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32
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#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47
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#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000
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#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018
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#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48
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#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63
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#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000
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#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0
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#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0
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#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001
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#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1
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#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16
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#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe
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#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17
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#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18
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#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000
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#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19
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#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19
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#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000
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#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20
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#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24
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#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000
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#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_MORE_DATA_LSB 25
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#define PDG_RESPONSE_MORE_DATA_MSB 25
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#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000
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#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_DURATION_INDICATION_LSB 26
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#define PDG_RESPONSE_DURATION_INDICATION_MSB 26
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#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000
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#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_RELAYED_FRAME_LSB 27
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#define PDG_RESPONSE_RELAYED_FRAME_MSB 27
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#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x0000000008000000
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#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28
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#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28
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#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x0000000010000000
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#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_BANDWIDTH_LSB 29
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#define PDG_RESPONSE_BANDWIDTH_MSB 31
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#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000
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#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_ACK_ID_LSB 32
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#define PDG_RESPONSE_ACK_ID_MSB 47
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#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000
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#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020
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#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48
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#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63
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#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000
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#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028
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#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0
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#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3
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#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f
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#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028
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#define PDG_RESPONSE_ACK_ID_EXT_LSB 4
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#define PDG_RESPONSE_ACK_ID_EXT_MSB 13
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#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0
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#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028
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#define PDG_RESPONSE_FTM_EN_LSB 14
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#define PDG_RESPONSE_FTM_EN_MSB 14
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#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000
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#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028
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#define PDG_RESPONSE_GROUP_ID_LSB 15
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#define PDG_RESPONSE_GROUP_ID_MSB 20
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#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000
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#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028
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#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21
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#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31
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#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000
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#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028
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#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32
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#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43
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#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000
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#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028
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#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44
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#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46
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#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000
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#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028
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#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47
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#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47
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#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000
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#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028
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#define PDG_RESPONSE_FRAME_LENGTH_LSB 48
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#define PDG_RESPONSE_FRAME_LENGTH_MSB 63
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#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000
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#endif
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