e1205760ac8b7789b84c1fde5000683f44cb74bb

Update csiphy2.1.0 reset sequence to not relese the reset during the reset sequence. Add support to read cphy lane status register after programming the csiphy. Program datarate specific settings before programming the lane registers. Add a delay of 100us before and 1ms after releasing the csiphy reset respectively for cphy. CRs-fixed: 2947752 Change-Id: I4befa03bab85779749efd33908ab5a02c96c0cb4 Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
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