e05daba83d
Disable double buffer vsync configuration while enabling clk and cmd state switch sequence. Leaving this configuration in enable state may cause different issues for different state switch. Clock state switch may see a vsync delay for solver disable. Command state switch may not update the vsync source. Change-Id: I910fc7e33a20a04b602435020173d85a4ee926d1 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>