dp_tx.c 178 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef WLAN_PEER_JITTER
  66. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  67. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  68. #endif
  69. #ifdef QCA_DP_TX_FW_METADATA_V2
  70. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  71. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  80. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  81. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  82. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  84. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  85. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  86. #else
  87. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  88. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  97. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  98. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  99. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  100. HTT_TCL_METADATA_TYPE_PEER_BASED
  101. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  102. HTT_TCL_METADATA_TYPE_VDEV_BASED
  103. #endif
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  232. /**
  233. * dp_is_tput_high() - Check if throughput is high
  234. *
  235. * @soc - core txrx main context
  236. *
  237. * The current function is based of the RTPM tput policy variable where RTPM is
  238. * avoided based on throughput.
  239. */
  240. static inline int dp_is_tput_high(struct dp_soc *soc)
  241. {
  242. return dp_get_rtpm_tput_policy_requirement(soc);
  243. }
  244. #if defined(FEATURE_TSO)
  245. /**
  246. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  247. *
  248. * @soc - core txrx main context
  249. * @seg_desc - tso segment descriptor
  250. * @num_seg_desc - tso number segment descriptor
  251. */
  252. static void dp_tx_tso_unmap_segment(
  253. struct dp_soc *soc,
  254. struct qdf_tso_seg_elem_t *seg_desc,
  255. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  256. {
  257. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  258. if (qdf_unlikely(!seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else if (qdf_unlikely(!num_seg_desc)) {
  263. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  264. __func__, __LINE__);
  265. qdf_assert(0);
  266. } else {
  267. bool is_last_seg;
  268. /* no tso segment left to do dma unmap */
  269. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  270. return;
  271. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  272. true : false;
  273. qdf_nbuf_unmap_tso_segment(soc->osdev,
  274. seg_desc, is_last_seg);
  275. num_seg_desc->num_seg.tso_cmn_num_seg--;
  276. }
  277. }
  278. /**
  279. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  280. * back to the freelist
  281. *
  282. * @soc - soc device handle
  283. * @tx_desc - Tx software descriptor
  284. */
  285. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  286. struct dp_tx_desc_s *tx_desc)
  287. {
  288. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  289. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  290. dp_tx_err("SO desc is NULL!");
  291. qdf_assert(0);
  292. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  293. dp_tx_err("TSO num desc is NULL!");
  294. qdf_assert(0);
  295. } else {
  296. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  297. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  298. msdu_ext_desc->tso_num_desc;
  299. /* Add the tso num segment into the free list */
  300. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  301. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  302. tx_desc->msdu_ext_desc->
  303. tso_num_desc);
  304. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  305. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  306. }
  307. /* Add the tso segment into the free list*/
  308. dp_tx_tso_desc_free(soc,
  309. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  310. tso_desc);
  311. tx_desc->msdu_ext_desc->tso_desc = NULL;
  312. }
  313. }
  314. #else
  315. static void dp_tx_tso_unmap_segment(
  316. struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *seg_desc,
  318. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  319. {
  320. }
  321. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  322. struct dp_tx_desc_s *tx_desc)
  323. {
  324. }
  325. #endif
  326. /**
  327. * dp_tx_desc_release() - Release Tx Descriptor
  328. * @tx_desc : Tx Descriptor
  329. * @desc_pool_id: Descriptor Pool ID
  330. *
  331. * Deallocate all resources attached to Tx descriptor and free the Tx
  332. * descriptor.
  333. *
  334. * Return:
  335. */
  336. void
  337. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  338. {
  339. struct dp_pdev *pdev = tx_desc->pdev;
  340. struct dp_soc *soc;
  341. uint8_t comp_status = 0;
  342. qdf_assert(pdev);
  343. soc = pdev->soc;
  344. dp_tx_outstanding_dec(pdev);
  345. if (tx_desc->msdu_ext_desc) {
  346. if (tx_desc->frm_type == dp_tx_frm_tso)
  347. dp_tx_tso_desc_release(soc, tx_desc);
  348. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  349. dp_tx_me_free_buf(tx_desc->pdev,
  350. tx_desc->msdu_ext_desc->me_buffer);
  351. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  352. }
  353. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  354. qdf_atomic_dec(&soc->num_tx_exception);
  355. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  356. tx_desc->buffer_src)
  357. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  358. soc->hal_soc);
  359. else
  360. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  361. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  362. tx_desc->id, comp_status,
  363. qdf_atomic_read(&pdev->num_tx_outstanding));
  364. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  365. return;
  366. }
  367. /**
  368. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  369. * @vdev: DP vdev Handle
  370. * @nbuf: skb
  371. * @msdu_info: msdu_info required to create HTT metadata
  372. *
  373. * Prepares and fills HTT metadata in the frame pre-header for special frames
  374. * that should be transmitted using varying transmit parameters.
  375. * There are 2 VDEV modes that currently needs this special metadata -
  376. * 1) Mesh Mode
  377. * 2) DSRC Mode
  378. *
  379. * Return: HTT metadata size
  380. *
  381. */
  382. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  383. struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. uint32_t *meta_data = msdu_info->meta_data;
  386. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  387. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  388. uint8_t htt_desc_size;
  389. /* Size rounded of multiple of 8 bytes */
  390. uint8_t htt_desc_size_aligned;
  391. uint8_t *hdr = NULL;
  392. /*
  393. * Metadata - HTT MSDU Extension header
  394. */
  395. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  396. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  397. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  398. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  399. meta_data[0]) ||
  400. msdu_info->exception_fw) {
  401. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  402. htt_desc_size_aligned)) {
  403. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  404. htt_desc_size_aligned);
  405. if (!nbuf) {
  406. /*
  407. * qdf_nbuf_realloc_headroom won't do skb_clone
  408. * as skb_realloc_headroom does. so, no free is
  409. * needed here.
  410. */
  411. DP_STATS_INC(vdev,
  412. tx_i.dropped.headroom_insufficient,
  413. 1);
  414. qdf_print(" %s[%d] skb_realloc_headroom failed",
  415. __func__, __LINE__);
  416. return 0;
  417. }
  418. }
  419. /* Fill and add HTT metaheader */
  420. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  421. if (!hdr) {
  422. dp_tx_err("Error in filling HTT metadata");
  423. return 0;
  424. }
  425. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  426. } else if (vdev->opmode == wlan_op_mode_ocb) {
  427. /* Todo - Add support for DSRC */
  428. }
  429. return htt_desc_size_aligned;
  430. }
  431. /**
  432. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  433. * @tso_seg: TSO segment to process
  434. * @ext_desc: Pointer to MSDU extension descriptor
  435. *
  436. * Return: void
  437. */
  438. #if defined(FEATURE_TSO)
  439. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  440. void *ext_desc)
  441. {
  442. uint8_t num_frag;
  443. uint32_t tso_flags;
  444. /*
  445. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  446. * tcp_flag_mask
  447. *
  448. * Checksum enable flags are set in TCL descriptor and not in Extension
  449. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  450. */
  451. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  452. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  453. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  454. tso_seg->tso_flags.ip_len);
  455. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  456. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  457. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  458. uint32_t lo = 0;
  459. uint32_t hi = 0;
  460. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  461. (tso_seg->tso_frags[num_frag].length));
  462. qdf_dmaaddr_to_32s(
  463. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  464. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  465. tso_seg->tso_frags[num_frag].length);
  466. }
  467. return;
  468. }
  469. #else
  470. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  471. void *ext_desc)
  472. {
  473. return;
  474. }
  475. #endif
  476. #if defined(FEATURE_TSO)
  477. /**
  478. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  479. * allocated and free them
  480. *
  481. * @soc: soc handle
  482. * @free_seg: list of tso segments
  483. * @msdu_info: msdu descriptor
  484. *
  485. * Return - void
  486. */
  487. static void dp_tx_free_tso_seg_list(
  488. struct dp_soc *soc,
  489. struct qdf_tso_seg_elem_t *free_seg,
  490. struct dp_tx_msdu_info_s *msdu_info)
  491. {
  492. struct qdf_tso_seg_elem_t *next_seg;
  493. while (free_seg) {
  494. next_seg = free_seg->next;
  495. dp_tx_tso_desc_free(soc,
  496. msdu_info->tx_queue.desc_pool_id,
  497. free_seg);
  498. free_seg = next_seg;
  499. }
  500. }
  501. /**
  502. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  503. * allocated and free them
  504. *
  505. * @soc: soc handle
  506. * @free_num_seg: list of tso number segments
  507. * @msdu_info: msdu descriptor
  508. * Return - void
  509. */
  510. static void dp_tx_free_tso_num_seg_list(
  511. struct dp_soc *soc,
  512. struct qdf_tso_num_seg_elem_t *free_num_seg,
  513. struct dp_tx_msdu_info_s *msdu_info)
  514. {
  515. struct qdf_tso_num_seg_elem_t *next_num_seg;
  516. while (free_num_seg) {
  517. next_num_seg = free_num_seg->next;
  518. dp_tso_num_seg_free(soc,
  519. msdu_info->tx_queue.desc_pool_id,
  520. free_num_seg);
  521. free_num_seg = next_num_seg;
  522. }
  523. }
  524. /**
  525. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  526. * do dma unmap for each segment
  527. *
  528. * @soc: soc handle
  529. * @free_seg: list of tso segments
  530. * @num_seg_desc: tso number segment descriptor
  531. *
  532. * Return - void
  533. */
  534. static void dp_tx_unmap_tso_seg_list(
  535. struct dp_soc *soc,
  536. struct qdf_tso_seg_elem_t *free_seg,
  537. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  538. {
  539. struct qdf_tso_seg_elem_t *next_seg;
  540. if (qdf_unlikely(!num_seg_desc)) {
  541. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  542. return;
  543. }
  544. while (free_seg) {
  545. next_seg = free_seg->next;
  546. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  547. free_seg = next_seg;
  548. }
  549. }
  550. #ifdef FEATURE_TSO_STATS
  551. /**
  552. * dp_tso_get_stats_idx: Retrieve the tso packet id
  553. * @pdev - pdev handle
  554. *
  555. * Return: id
  556. */
  557. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  558. {
  559. uint32_t stats_idx;
  560. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  561. % CDP_MAX_TSO_PACKETS);
  562. return stats_idx;
  563. }
  564. #else
  565. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  566. {
  567. return 0;
  568. }
  569. #endif /* FEATURE_TSO_STATS */
  570. /**
  571. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  572. * free the tso segments descriptor and
  573. * tso num segments descriptor
  574. *
  575. * @soc: soc handle
  576. * @msdu_info: msdu descriptor
  577. * @tso_seg_unmap: flag to show if dma unmap is necessary
  578. *
  579. * Return - void
  580. */
  581. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  582. struct dp_tx_msdu_info_s *msdu_info,
  583. bool tso_seg_unmap)
  584. {
  585. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  586. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  587. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  588. tso_info->tso_num_seg_list;
  589. /* do dma unmap for each segment */
  590. if (tso_seg_unmap)
  591. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  592. /* free all tso number segment descriptor though looks only have 1 */
  593. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  594. /* free all tso segment descriptor */
  595. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  596. }
  597. /**
  598. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  599. * @vdev: virtual device handle
  600. * @msdu: network buffer
  601. * @msdu_info: meta data associated with the msdu
  602. *
  603. * Return: QDF_STATUS_SUCCESS success
  604. */
  605. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  606. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  607. {
  608. struct qdf_tso_seg_elem_t *tso_seg;
  609. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  610. struct dp_soc *soc = vdev->pdev->soc;
  611. struct dp_pdev *pdev = vdev->pdev;
  612. struct qdf_tso_info_t *tso_info;
  613. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  614. tso_info = &msdu_info->u.tso_info;
  615. tso_info->curr_seg = NULL;
  616. tso_info->tso_seg_list = NULL;
  617. tso_info->num_segs = num_seg;
  618. msdu_info->frm_type = dp_tx_frm_tso;
  619. tso_info->tso_num_seg_list = NULL;
  620. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  621. while (num_seg) {
  622. tso_seg = dp_tx_tso_desc_alloc(
  623. soc, msdu_info->tx_queue.desc_pool_id);
  624. if (tso_seg) {
  625. tso_seg->next = tso_info->tso_seg_list;
  626. tso_info->tso_seg_list = tso_seg;
  627. num_seg--;
  628. } else {
  629. dp_err_rl("Failed to alloc tso seg desc");
  630. DP_STATS_INC_PKT(vdev->pdev,
  631. tso_stats.tso_no_mem_dropped, 1,
  632. qdf_nbuf_len(msdu));
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  634. return QDF_STATUS_E_NOMEM;
  635. }
  636. }
  637. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  638. tso_num_seg = dp_tso_num_seg_alloc(soc,
  639. msdu_info->tx_queue.desc_pool_id);
  640. if (tso_num_seg) {
  641. tso_num_seg->next = tso_info->tso_num_seg_list;
  642. tso_info->tso_num_seg_list = tso_num_seg;
  643. } else {
  644. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  645. __func__);
  646. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  647. return QDF_STATUS_E_NOMEM;
  648. }
  649. msdu_info->num_seg =
  650. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  651. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  652. msdu_info->num_seg);
  653. if (!(msdu_info->num_seg)) {
  654. /*
  655. * Free allocated TSO seg desc and number seg desc,
  656. * do unmap for segments if dma map has done.
  657. */
  658. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  659. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  660. return QDF_STATUS_E_INVAL;
  661. }
  662. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  663. msdu, 0, DP_TX_DESC_MAP);
  664. tso_info->curr_seg = tso_info->tso_seg_list;
  665. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  666. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  667. msdu, msdu_info->num_seg);
  668. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  669. tso_info->msdu_stats_idx);
  670. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  671. return QDF_STATUS_SUCCESS;
  672. }
  673. #else
  674. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  675. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  676. {
  677. return QDF_STATUS_E_NOMEM;
  678. }
  679. #endif
  680. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  681. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  682. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  683. /**
  684. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  685. * @vdev: DP Vdev handle
  686. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  687. * @desc_pool_id: Descriptor Pool ID
  688. *
  689. * Return:
  690. */
  691. static
  692. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  693. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  694. {
  695. uint8_t i;
  696. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  697. struct dp_tx_seg_info_s *seg_info;
  698. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  699. struct dp_soc *soc = vdev->pdev->soc;
  700. /* Allocate an extension descriptor */
  701. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  702. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  703. if (!msdu_ext_desc) {
  704. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  705. return NULL;
  706. }
  707. if (msdu_info->exception_fw &&
  708. qdf_unlikely(vdev->mesh_vdev)) {
  709. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  710. &msdu_info->meta_data[0],
  711. sizeof(struct htt_tx_msdu_desc_ext2_t));
  712. qdf_atomic_inc(&soc->num_tx_exception);
  713. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  714. }
  715. switch (msdu_info->frm_type) {
  716. case dp_tx_frm_sg:
  717. case dp_tx_frm_me:
  718. case dp_tx_frm_raw:
  719. seg_info = msdu_info->u.sg_info.curr_seg;
  720. /* Update the buffer pointers in MSDU Extension Descriptor */
  721. for (i = 0; i < seg_info->frag_cnt; i++) {
  722. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  723. seg_info->frags[i].paddr_lo,
  724. seg_info->frags[i].paddr_hi,
  725. seg_info->frags[i].len);
  726. }
  727. break;
  728. case dp_tx_frm_tso:
  729. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  730. &cached_ext_desc[0]);
  731. break;
  732. default:
  733. break;
  734. }
  735. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  736. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  737. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  738. msdu_ext_desc->vaddr);
  739. return msdu_ext_desc;
  740. }
  741. /**
  742. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  743. *
  744. * @skb: skb to be traced
  745. * @msdu_id: msdu_id of the packet
  746. * @vdev_id: vdev_id of the packet
  747. *
  748. * Return: None
  749. */
  750. #ifdef DP_DISABLE_TX_PKT_TRACE
  751. static void dp_tx_trace_pkt(struct dp_soc *soc,
  752. qdf_nbuf_t skb, uint16_t msdu_id,
  753. uint8_t vdev_id)
  754. {
  755. }
  756. #else
  757. static void dp_tx_trace_pkt(struct dp_soc *soc,
  758. qdf_nbuf_t skb, uint16_t msdu_id,
  759. uint8_t vdev_id)
  760. {
  761. if (dp_is_tput_high(soc))
  762. return;
  763. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  764. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  765. DPTRACE(qdf_dp_trace_ptr(skb,
  766. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  767. QDF_TRACE_DEFAULT_PDEV_ID,
  768. qdf_nbuf_data_addr(skb),
  769. sizeof(qdf_nbuf_data(skb)),
  770. msdu_id, vdev_id, 0));
  771. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  772. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  773. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  774. msdu_id, QDF_TX));
  775. }
  776. #endif
  777. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  778. /**
  779. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  780. * exception by the upper layer (OS_IF)
  781. * @soc: DP soc handle
  782. * @nbuf: packet to be transmitted
  783. *
  784. * Returns: 1 if the packet is marked as exception,
  785. * 0, if the packet is not marked as exception.
  786. */
  787. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  788. qdf_nbuf_t nbuf)
  789. {
  790. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  791. }
  792. #else
  793. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  794. qdf_nbuf_t nbuf)
  795. {
  796. return 0;
  797. }
  798. #endif
  799. #ifdef DP_TRAFFIC_END_INDICATION
  800. /**
  801. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  802. * as indication to fw to inform that
  803. * data stream has ended
  804. * @vdev: DP vdev handle
  805. * @nbuf: original buffer from network stack
  806. *
  807. * Return: NULL on failure,
  808. * nbuf on success
  809. */
  810. static inline qdf_nbuf_t
  811. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  812. qdf_nbuf_t nbuf)
  813. {
  814. /* Packet length should be enough to copy upto L3 header */
  815. uint8_t end_nbuf_len = 64;
  816. uint8_t htt_desc_size_aligned;
  817. uint8_t htt_desc_size;
  818. qdf_nbuf_t end_nbuf;
  819. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  820. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  821. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  822. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  823. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  824. if (!end_nbuf) {
  825. end_nbuf = qdf_nbuf_alloc(NULL,
  826. (htt_desc_size_aligned +
  827. end_nbuf_len),
  828. htt_desc_size_aligned,
  829. 8, false);
  830. if (!end_nbuf) {
  831. dp_err("Packet allocation failed");
  832. goto out;
  833. }
  834. } else {
  835. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  836. }
  837. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  838. end_nbuf_len);
  839. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  840. return end_nbuf;
  841. }
  842. out:
  843. return NULL;
  844. }
  845. /**
  846. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  847. * via exception path.
  848. * @vdev: DP vdev handle
  849. * @end_nbuf: skb to send as indication
  850. * @msdu_info: msdu_info of original nbuf
  851. * @peer_id: peer id
  852. *
  853. * Return: None
  854. */
  855. static inline void
  856. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  857. qdf_nbuf_t end_nbuf,
  858. struct dp_tx_msdu_info_s *msdu_info,
  859. uint16_t peer_id)
  860. {
  861. struct dp_tx_msdu_info_s e_msdu_info = {0};
  862. qdf_nbuf_t nbuf;
  863. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  864. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  865. e_msdu_info.tx_queue = msdu_info->tx_queue;
  866. e_msdu_info.tid = msdu_info->tid;
  867. e_msdu_info.exception_fw = 1;
  868. desc_ext->host_tx_desc_pool = 1;
  869. desc_ext->traffic_end_indication = 1;
  870. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  871. peer_id, NULL);
  872. if (nbuf) {
  873. dp_err("Traffic end indication packet tx failed");
  874. qdf_nbuf_free(nbuf);
  875. }
  876. }
  877. /**
  878. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  879. * mark it traffic end indication
  880. * packet.
  881. * @tx_desc: Tx descriptor pointer
  882. * @msdu_info: msdu_info structure pointer
  883. *
  884. * Return: None
  885. */
  886. static inline void
  887. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  888. struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  891. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  892. if (qdf_unlikely(desc_ext->traffic_end_indication))
  893. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  894. }
  895. /**
  896. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  897. * freeing which are associated
  898. * with traffic end indication
  899. * flagged descriptor.
  900. * @soc: dp soc handle
  901. * @desc: Tx descriptor pointer
  902. * @nbuf: buffer pointer
  903. *
  904. * Return: True if packet gets enqueued else false
  905. */
  906. static bool
  907. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  908. struct dp_tx_desc_s *desc,
  909. qdf_nbuf_t nbuf)
  910. {
  911. struct dp_vdev *vdev = NULL;
  912. if (qdf_unlikely((desc->flags &
  913. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  914. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  915. DP_MOD_ID_TX_COMP);
  916. if (vdev) {
  917. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  918. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  919. return true;
  920. }
  921. }
  922. return false;
  923. }
  924. /**
  925. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  926. * enable/disable status
  927. * @vdev: dp vdev handle
  928. *
  929. * Return: True if feature is enable else false
  930. */
  931. static inline bool
  932. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  933. {
  934. return qdf_unlikely(vdev->traffic_end_ind_en);
  935. }
  936. static inline qdf_nbuf_t
  937. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  938. struct dp_tx_msdu_info_s *msdu_info,
  939. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  940. {
  941. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  942. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  943. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  944. if (qdf_unlikely(end_nbuf))
  945. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  946. msdu_info, peer_id);
  947. return nbuf;
  948. }
  949. #else
  950. static inline qdf_nbuf_t
  951. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  952. qdf_nbuf_t nbuf)
  953. {
  954. return NULL;
  955. }
  956. static inline void
  957. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  958. qdf_nbuf_t end_nbuf,
  959. struct dp_tx_msdu_info_s *msdu_info,
  960. uint16_t peer_id)
  961. {}
  962. static inline void
  963. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  964. struct dp_tx_msdu_info_s *msdu_info)
  965. {}
  966. static inline bool
  967. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  968. struct dp_tx_desc_s *desc,
  969. qdf_nbuf_t nbuf)
  970. {
  971. return false;
  972. }
  973. static inline bool
  974. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  975. {
  976. return false;
  977. }
  978. static inline qdf_nbuf_t
  979. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  980. struct dp_tx_msdu_info_s *msdu_info,
  981. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  982. {
  983. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  984. }
  985. #endif
  986. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  987. static bool
  988. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  989. struct cdp_tx_exception_metadata *tx_exc_metadata)
  990. {
  991. if (soc->features.wds_ext_ast_override_enable &&
  992. tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  993. return true;
  994. return false;
  995. }
  996. #else
  997. static bool
  998. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  999. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1000. {
  1001. return false;
  1002. }
  1003. #endif
  1004. /**
  1005. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  1006. * @vdev: DP vdev handle
  1007. * @nbuf: skb
  1008. * @desc_pool_id: Descriptor pool ID
  1009. * @meta_data: Metadata to the fw
  1010. * @tx_exc_metadata: Handle that holds exception path metadata
  1011. * Allocate and prepare Tx descriptor with msdu information.
  1012. *
  1013. * Return: Pointer to Tx Descriptor on success,
  1014. * NULL on failure
  1015. */
  1016. static
  1017. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1018. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1019. struct dp_tx_msdu_info_s *msdu_info,
  1020. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1021. {
  1022. uint8_t align_pad;
  1023. uint8_t is_exception = 0;
  1024. uint8_t htt_hdr_size;
  1025. struct dp_tx_desc_s *tx_desc;
  1026. struct dp_pdev *pdev = vdev->pdev;
  1027. struct dp_soc *soc = pdev->soc;
  1028. if (dp_tx_limit_check(vdev, nbuf))
  1029. return NULL;
  1030. /* Allocate software Tx descriptor */
  1031. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1032. if (qdf_unlikely(!tx_desc)) {
  1033. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1034. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1035. return NULL;
  1036. }
  1037. dp_tx_outstanding_inc(pdev);
  1038. /* Initialize the SW tx descriptor */
  1039. tx_desc->nbuf = nbuf;
  1040. tx_desc->frm_type = dp_tx_frm_std;
  1041. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1042. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1043. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1044. tx_desc->vdev_id = vdev->vdev_id;
  1045. tx_desc->pdev = pdev;
  1046. tx_desc->msdu_ext_desc = NULL;
  1047. tx_desc->pkt_offset = 0;
  1048. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1049. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1050. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1051. if (qdf_unlikely(vdev->multipass_en)) {
  1052. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1053. goto failure;
  1054. }
  1055. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1056. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1057. is_exception = 1;
  1058. /* for BE chipsets if wds extension was enbled will not mark FW
  1059. * in desc will mark ast index based search for ast index.
  1060. */
  1061. if (dp_tx_is_wds_ast_override_en(soc, tx_exc_metadata))
  1062. return tx_desc;
  1063. /*
  1064. * For special modes (vdev_type == ocb or mesh), data frames should be
  1065. * transmitted using varying transmit parameters (tx spec) which include
  1066. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1067. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1068. * These frames are sent as exception packets to firmware.
  1069. *
  1070. * HW requirement is that metadata should always point to a
  1071. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1072. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1073. * to get 8-byte aligned start address along with align_pad added
  1074. *
  1075. * |-----------------------------|
  1076. * | |
  1077. * |-----------------------------| <-----Buffer Pointer Address given
  1078. * | | ^ in HW descriptor (aligned)
  1079. * | HTT Metadata | |
  1080. * | | |
  1081. * | | | Packet Offset given in descriptor
  1082. * | | |
  1083. * |-----------------------------| |
  1084. * | Alignment Pad | v
  1085. * |-----------------------------| <----- Actual buffer start address
  1086. * | SKB Data | (Unaligned)
  1087. * | |
  1088. * | |
  1089. * | |
  1090. * | |
  1091. * | |
  1092. * |-----------------------------|
  1093. */
  1094. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1095. (vdev->opmode == wlan_op_mode_ocb) ||
  1096. (tx_exc_metadata &&
  1097. tx_exc_metadata->is_tx_sniffer)) {
  1098. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1099. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1100. DP_STATS_INC(vdev,
  1101. tx_i.dropped.headroom_insufficient, 1);
  1102. goto failure;
  1103. }
  1104. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1105. dp_tx_err("qdf_nbuf_push_head failed");
  1106. goto failure;
  1107. }
  1108. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1109. msdu_info);
  1110. if (htt_hdr_size == 0)
  1111. goto failure;
  1112. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1113. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1114. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1115. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1116. msdu_info);
  1117. is_exception = 1;
  1118. tx_desc->length -= tx_desc->pkt_offset;
  1119. }
  1120. #if !TQM_BYPASS_WAR
  1121. if (is_exception || tx_exc_metadata)
  1122. #endif
  1123. {
  1124. /* Temporary WAR due to TQM VP issues */
  1125. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1126. qdf_atomic_inc(&soc->num_tx_exception);
  1127. }
  1128. return tx_desc;
  1129. failure:
  1130. dp_tx_desc_release(tx_desc, desc_pool_id);
  1131. return NULL;
  1132. }
  1133. /**
  1134. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1135. * @vdev: DP vdev handle
  1136. * @nbuf: skb
  1137. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1138. * @desc_pool_id : Descriptor Pool ID
  1139. *
  1140. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1141. * information. For frames with fragments, allocate and prepare
  1142. * an MSDU extension descriptor
  1143. *
  1144. * Return: Pointer to Tx Descriptor on success,
  1145. * NULL on failure
  1146. */
  1147. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1148. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1149. uint8_t desc_pool_id)
  1150. {
  1151. struct dp_tx_desc_s *tx_desc;
  1152. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1153. struct dp_pdev *pdev = vdev->pdev;
  1154. struct dp_soc *soc = pdev->soc;
  1155. if (dp_tx_limit_check(vdev, nbuf))
  1156. return NULL;
  1157. /* Allocate software Tx descriptor */
  1158. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1159. if (!tx_desc) {
  1160. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1161. return NULL;
  1162. }
  1163. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1164. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1165. dp_tx_outstanding_inc(pdev);
  1166. /* Initialize the SW tx descriptor */
  1167. tx_desc->nbuf = nbuf;
  1168. tx_desc->frm_type = msdu_info->frm_type;
  1169. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1170. tx_desc->vdev_id = vdev->vdev_id;
  1171. tx_desc->pdev = pdev;
  1172. tx_desc->pkt_offset = 0;
  1173. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1174. /* Handle scattered frames - TSO/SG/ME */
  1175. /* Allocate and prepare an extension descriptor for scattered frames */
  1176. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1177. if (!msdu_ext_desc) {
  1178. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1179. goto failure;
  1180. }
  1181. #if TQM_BYPASS_WAR
  1182. /* Temporary WAR due to TQM VP issues */
  1183. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1184. qdf_atomic_inc(&soc->num_tx_exception);
  1185. #endif
  1186. if (qdf_unlikely(msdu_info->exception_fw))
  1187. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1188. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1189. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1190. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1191. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1192. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1193. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1194. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1195. else
  1196. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1197. return tx_desc;
  1198. failure:
  1199. dp_tx_desc_release(tx_desc, desc_pool_id);
  1200. return NULL;
  1201. }
  1202. /**
  1203. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1204. * @vdev: DP vdev handle
  1205. * @nbuf: buffer pointer
  1206. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1207. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1208. * descriptor
  1209. *
  1210. * Return:
  1211. */
  1212. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1213. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1214. {
  1215. qdf_nbuf_t curr_nbuf = NULL;
  1216. uint16_t total_len = 0;
  1217. qdf_dma_addr_t paddr;
  1218. int32_t i;
  1219. int32_t mapped_buf_num = 0;
  1220. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1221. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1222. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1223. /* Continue only if frames are of DATA type */
  1224. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1225. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1226. dp_tx_debug("Pkt. recd is of not data type");
  1227. goto error;
  1228. }
  1229. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1230. if (vdev->raw_mode_war &&
  1231. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1232. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1233. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1234. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1235. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1236. /*
  1237. * Number of nbuf's must not exceed the size of the frags
  1238. * array in seg_info.
  1239. */
  1240. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1241. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1242. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1243. goto error;
  1244. }
  1245. if (QDF_STATUS_SUCCESS !=
  1246. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1247. curr_nbuf,
  1248. QDF_DMA_TO_DEVICE,
  1249. curr_nbuf->len)) {
  1250. dp_tx_err("%s dma map error ", __func__);
  1251. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1252. goto error;
  1253. }
  1254. /* Update the count of mapped nbuf's */
  1255. mapped_buf_num++;
  1256. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1257. seg_info->frags[i].paddr_lo = paddr;
  1258. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1259. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1260. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1261. total_len += qdf_nbuf_len(curr_nbuf);
  1262. }
  1263. seg_info->frag_cnt = i;
  1264. seg_info->total_len = total_len;
  1265. seg_info->next = NULL;
  1266. sg_info->curr_seg = seg_info;
  1267. msdu_info->frm_type = dp_tx_frm_raw;
  1268. msdu_info->num_seg = 1;
  1269. return nbuf;
  1270. error:
  1271. i = 0;
  1272. while (nbuf) {
  1273. curr_nbuf = nbuf;
  1274. if (i < mapped_buf_num) {
  1275. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1276. QDF_DMA_TO_DEVICE,
  1277. curr_nbuf->len);
  1278. i++;
  1279. }
  1280. nbuf = qdf_nbuf_next(nbuf);
  1281. qdf_nbuf_free(curr_nbuf);
  1282. }
  1283. return NULL;
  1284. }
  1285. /**
  1286. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1287. * @soc: DP soc handle
  1288. * @nbuf: Buffer pointer
  1289. *
  1290. * unmap the chain of nbufs that belong to this RAW frame.
  1291. *
  1292. * Return: None
  1293. */
  1294. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1295. qdf_nbuf_t nbuf)
  1296. {
  1297. qdf_nbuf_t cur_nbuf = nbuf;
  1298. do {
  1299. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1300. QDF_DMA_TO_DEVICE,
  1301. cur_nbuf->len);
  1302. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1303. } while (cur_nbuf);
  1304. }
  1305. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1306. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1307. qdf_nbuf_t nbuf)
  1308. {
  1309. qdf_nbuf_t nbuf_local;
  1310. struct dp_vdev *vdev_local = vdev_hdl;
  1311. do {
  1312. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1313. break;
  1314. nbuf_local = nbuf;
  1315. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1316. htt_cmn_pkt_type_raw))
  1317. break;
  1318. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1319. break;
  1320. else if (qdf_nbuf_is_tso((nbuf_local)))
  1321. break;
  1322. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1323. (nbuf_local),
  1324. NULL, 1, 0);
  1325. } while (0);
  1326. }
  1327. #endif
  1328. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1329. /**
  1330. * dp_tx_update_stats() - Update soc level tx stats
  1331. * @soc: DP soc handle
  1332. * @tx_desc: TX descriptor reference
  1333. * @ring_id: TCL ring id
  1334. *
  1335. * Returns: none
  1336. */
  1337. void dp_tx_update_stats(struct dp_soc *soc,
  1338. struct dp_tx_desc_s *tx_desc,
  1339. uint8_t ring_id)
  1340. {
  1341. uint32_t stats_len = 0;
  1342. if (tx_desc->frm_type == dp_tx_frm_tso)
  1343. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1344. else
  1345. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1346. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1347. }
  1348. int
  1349. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1350. struct dp_tx_desc_s *tx_desc,
  1351. uint8_t tid,
  1352. struct dp_tx_msdu_info_s *msdu_info,
  1353. uint8_t ring_id)
  1354. {
  1355. struct dp_swlm *swlm = &soc->swlm;
  1356. union swlm_data swlm_query_data;
  1357. struct dp_swlm_tcl_data tcl_data;
  1358. QDF_STATUS status;
  1359. int ret;
  1360. if (!swlm->is_enabled)
  1361. return msdu_info->skip_hp_update;
  1362. tcl_data.nbuf = tx_desc->nbuf;
  1363. tcl_data.tid = tid;
  1364. tcl_data.ring_id = ring_id;
  1365. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1366. tcl_data.pkt_len =
  1367. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1368. } else {
  1369. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1370. }
  1371. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1372. swlm_query_data.tcl_data = &tcl_data;
  1373. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1374. if (QDF_IS_STATUS_ERROR(status)) {
  1375. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1376. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1377. return 0;
  1378. }
  1379. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1380. if (ret) {
  1381. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1382. } else {
  1383. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1384. }
  1385. return ret;
  1386. }
  1387. void
  1388. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1389. int coalesce)
  1390. {
  1391. if (coalesce)
  1392. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1393. else
  1394. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1395. }
  1396. static inline void
  1397. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1398. {
  1399. if (((i + 1) < msdu_info->num_seg))
  1400. msdu_info->skip_hp_update = 1;
  1401. else
  1402. msdu_info->skip_hp_update = 0;
  1403. }
  1404. static inline void
  1405. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1406. {
  1407. hal_ring_handle_t hal_ring_hdl =
  1408. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1409. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1410. dp_err("Fillmore: SRNG access start failed");
  1411. return;
  1412. }
  1413. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1414. }
  1415. static inline void
  1416. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1417. QDF_STATUS status,
  1418. struct dp_tx_msdu_info_s *msdu_info)
  1419. {
  1420. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1421. dp_flush_tcp_hp(soc,
  1422. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1423. }
  1424. }
  1425. #else
  1426. static inline void
  1427. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1428. {
  1429. }
  1430. static inline void
  1431. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1432. QDF_STATUS status,
  1433. struct dp_tx_msdu_info_s *msdu_info)
  1434. {
  1435. }
  1436. #endif
  1437. #ifdef FEATURE_RUNTIME_PM
  1438. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1439. {
  1440. int ret;
  1441. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1442. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1443. return ret;
  1444. }
  1445. /**
  1446. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1447. * @soc: Datapath soc handle
  1448. * @hal_ring_hdl: HAL ring handle
  1449. * @coalesce: Coalesce the current write or not
  1450. *
  1451. * Wrapper for HAL ring access end for data transmission for
  1452. * FEATURE_RUNTIME_PM
  1453. *
  1454. * Returns: none
  1455. */
  1456. void
  1457. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1458. hal_ring_handle_t hal_ring_hdl,
  1459. int coalesce)
  1460. {
  1461. int ret;
  1462. /*
  1463. * Avoid runtime get and put APIs under high throughput scenarios.
  1464. */
  1465. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1466. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1467. return;
  1468. }
  1469. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1470. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1471. if (hif_system_pm_state_check(soc->hif_handle)) {
  1472. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1473. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1474. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1475. } else {
  1476. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1477. }
  1478. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1479. } else {
  1480. dp_runtime_get(soc);
  1481. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1482. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1483. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1484. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1485. dp_runtime_put(soc);
  1486. }
  1487. }
  1488. #else
  1489. #ifdef DP_POWER_SAVE
  1490. void
  1491. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1492. hal_ring_handle_t hal_ring_hdl,
  1493. int coalesce)
  1494. {
  1495. if (hif_system_pm_state_check(soc->hif_handle)) {
  1496. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1497. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1498. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1499. } else {
  1500. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1501. }
  1502. }
  1503. #endif
  1504. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1505. {
  1506. return 0;
  1507. }
  1508. #endif
  1509. /**
  1510. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1511. * @vdev: DP vdev handle
  1512. * @nbuf: skb
  1513. *
  1514. * Extract the DSCP or PCP information from frame and map into TID value.
  1515. *
  1516. * Return: void
  1517. */
  1518. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1519. struct dp_tx_msdu_info_s *msdu_info)
  1520. {
  1521. uint8_t tos = 0, dscp_tid_override = 0;
  1522. uint8_t *hdr_ptr, *L3datap;
  1523. uint8_t is_mcast = 0;
  1524. qdf_ether_header_t *eh = NULL;
  1525. qdf_ethervlan_header_t *evh = NULL;
  1526. uint16_t ether_type;
  1527. qdf_llc_t *llcHdr;
  1528. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1529. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1530. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1531. eh = (qdf_ether_header_t *)nbuf->data;
  1532. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1533. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1534. } else {
  1535. qdf_dot3_qosframe_t *qos_wh =
  1536. (qdf_dot3_qosframe_t *) nbuf->data;
  1537. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1538. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1539. return;
  1540. }
  1541. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1542. ether_type = eh->ether_type;
  1543. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1544. /*
  1545. * Check if packet is dot3 or eth2 type.
  1546. */
  1547. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1548. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1549. sizeof(*llcHdr));
  1550. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1551. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1552. sizeof(*llcHdr);
  1553. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1554. + sizeof(*llcHdr) +
  1555. sizeof(qdf_net_vlanhdr_t));
  1556. } else {
  1557. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1558. sizeof(*llcHdr);
  1559. }
  1560. } else {
  1561. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1562. evh = (qdf_ethervlan_header_t *) eh;
  1563. ether_type = evh->ether_type;
  1564. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1565. }
  1566. }
  1567. /*
  1568. * Find priority from IP TOS DSCP field
  1569. */
  1570. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1571. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1572. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1573. /* Only for unicast frames */
  1574. if (!is_mcast) {
  1575. /* send it on VO queue */
  1576. msdu_info->tid = DP_VO_TID;
  1577. }
  1578. } else {
  1579. /*
  1580. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1581. * from TOS byte.
  1582. */
  1583. tos = ip->ip_tos;
  1584. dscp_tid_override = 1;
  1585. }
  1586. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1587. /* TODO
  1588. * use flowlabel
  1589. *igmpmld cases to be handled in phase 2
  1590. */
  1591. unsigned long ver_pri_flowlabel;
  1592. unsigned long pri;
  1593. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1594. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1595. DP_IPV6_PRIORITY_SHIFT;
  1596. tos = pri;
  1597. dscp_tid_override = 1;
  1598. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1599. msdu_info->tid = DP_VO_TID;
  1600. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1601. /* Only for unicast frames */
  1602. if (!is_mcast) {
  1603. /* send ucast arp on VO queue */
  1604. msdu_info->tid = DP_VO_TID;
  1605. }
  1606. }
  1607. /*
  1608. * Assign all MCAST packets to BE
  1609. */
  1610. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1611. if (is_mcast) {
  1612. tos = 0;
  1613. dscp_tid_override = 1;
  1614. }
  1615. }
  1616. if (dscp_tid_override == 1) {
  1617. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1618. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1619. }
  1620. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1621. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1622. return;
  1623. }
  1624. /**
  1625. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1626. * @vdev: DP vdev handle
  1627. * @nbuf: skb
  1628. *
  1629. * Software based TID classification is required when more than 2 DSCP-TID
  1630. * mapping tables are needed.
  1631. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1632. *
  1633. * Return: void
  1634. */
  1635. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1636. struct dp_tx_msdu_info_s *msdu_info)
  1637. {
  1638. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1639. /*
  1640. * skip_sw_tid_classification flag will set in below cases-
  1641. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1642. * 2. hlos_tid_override enabled for vdev
  1643. * 3. mesh mode enabled for vdev
  1644. */
  1645. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1646. /* Update tid in msdu_info from skb priority */
  1647. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1648. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1649. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1650. if (tid == DP_TX_INVALID_QOS_TAG)
  1651. return;
  1652. msdu_info->tid = tid;
  1653. return;
  1654. }
  1655. return;
  1656. }
  1657. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1658. }
  1659. #ifdef FEATURE_WLAN_TDLS
  1660. /**
  1661. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1662. * @soc: datapath SOC
  1663. * @vdev: datapath vdev
  1664. * @tx_desc: TX descriptor
  1665. *
  1666. * Return: None
  1667. */
  1668. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1669. struct dp_vdev *vdev,
  1670. struct dp_tx_desc_s *tx_desc)
  1671. {
  1672. if (vdev) {
  1673. if (vdev->is_tdls_frame) {
  1674. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1675. vdev->is_tdls_frame = false;
  1676. }
  1677. }
  1678. }
  1679. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1680. {
  1681. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1682. switch (soc->arch_id) {
  1683. case CDP_ARCH_TYPE_LI:
  1684. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1685. break;
  1686. case CDP_ARCH_TYPE_BE:
  1687. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1688. break;
  1689. default:
  1690. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1691. QDF_BUG(0);
  1692. }
  1693. return tx_status;
  1694. }
  1695. /**
  1696. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1697. * @soc: dp_soc handle
  1698. * @tx_desc: TX descriptor
  1699. * @vdev: datapath vdev handle
  1700. *
  1701. * Return: None
  1702. */
  1703. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1704. struct dp_tx_desc_s *tx_desc)
  1705. {
  1706. uint8_t tx_status = 0;
  1707. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1708. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1709. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1710. DP_MOD_ID_TDLS);
  1711. if (qdf_unlikely(!vdev)) {
  1712. dp_err_rl("vdev is null!");
  1713. goto error;
  1714. }
  1715. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1716. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1717. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1718. if (vdev->tx_non_std_data_callback.func) {
  1719. qdf_nbuf_set_next(nbuf, NULL);
  1720. vdev->tx_non_std_data_callback.func(
  1721. vdev->tx_non_std_data_callback.ctxt,
  1722. nbuf, tx_status);
  1723. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1724. return;
  1725. } else {
  1726. dp_err_rl("callback func is null");
  1727. }
  1728. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1729. error:
  1730. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1731. qdf_nbuf_free(nbuf);
  1732. }
  1733. /**
  1734. * dp_tx_msdu_single_map() - do nbuf map
  1735. * @vdev: DP vdev handle
  1736. * @tx_desc: DP TX descriptor pointer
  1737. * @nbuf: skb pointer
  1738. *
  1739. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1740. * operation done in other component.
  1741. *
  1742. * Return: QDF_STATUS
  1743. */
  1744. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1745. struct dp_tx_desc_s *tx_desc,
  1746. qdf_nbuf_t nbuf)
  1747. {
  1748. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1749. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1750. nbuf,
  1751. QDF_DMA_TO_DEVICE,
  1752. nbuf->len);
  1753. else
  1754. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1755. QDF_DMA_TO_DEVICE);
  1756. }
  1757. #else
  1758. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1759. struct dp_vdev *vdev,
  1760. struct dp_tx_desc_s *tx_desc)
  1761. {
  1762. }
  1763. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1764. struct dp_tx_desc_s *tx_desc)
  1765. {
  1766. }
  1767. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1768. struct dp_tx_desc_s *tx_desc,
  1769. qdf_nbuf_t nbuf)
  1770. {
  1771. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1772. nbuf,
  1773. QDF_DMA_TO_DEVICE,
  1774. nbuf->len);
  1775. }
  1776. #endif
  1777. static inline
  1778. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1779. struct dp_tx_desc_s *tx_desc,
  1780. qdf_nbuf_t nbuf)
  1781. {
  1782. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1783. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1784. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1785. return 0;
  1786. return qdf_nbuf_mapped_paddr_get(nbuf);
  1787. }
  1788. static inline
  1789. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1790. {
  1791. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1792. desc->nbuf,
  1793. desc->dma_addr,
  1794. QDF_DMA_TO_DEVICE,
  1795. desc->length);
  1796. }
  1797. #ifdef QCA_DP_TX_RMNET_OPTIMIZATION
  1798. static inline bool
  1799. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1800. {
  1801. struct net_device *ingress_dev;
  1802. skb_frag_t *frag;
  1803. uint16_t buf_len = 0;
  1804. uint16_t linear_data_len = 0;
  1805. uint8_t *payload_addr = NULL;
  1806. ingress_dev = dev_get_by_index(dev_net(nbuf->dev), nbuf->skb_iif);
  1807. if ((ingress_dev->priv_flags & IFF_PHONY_HEADROOM)) {
  1808. dev_put(ingress_dev);
  1809. frag = &(skb_shinfo(nbuf)->frags[0]);
  1810. buf_len = skb_frag_size(frag);
  1811. payload_addr = (uint8_t *)skb_frag_address(frag);
  1812. linear_data_len = skb_headlen(nbuf);
  1813. buf_len += linear_data_len;
  1814. payload_addr = payload_addr - linear_data_len;
  1815. memcpy(payload_addr, nbuf->data, linear_data_len);
  1816. msdu_info->frm_type = dp_tx_frm_rmnet;
  1817. msdu_info->buf_len = buf_len;
  1818. msdu_info->payload_addr = payload_addr;
  1819. return true;
  1820. }
  1821. dev_put(ingress_dev);
  1822. return false;
  1823. }
  1824. static inline
  1825. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1826. struct dp_tx_desc_s *tx_desc)
  1827. {
  1828. qdf_dma_addr_t paddr;
  1829. paddr = (qdf_dma_addr_t)qdf_mem_virt_to_phys(msdu_info->payload_addr);
  1830. tx_desc->length = msdu_info->buf_len;
  1831. qdf_nbuf_dma_clean_range((void *)msdu_info->payload_addr,
  1832. (void *)(msdu_info->payload_addr +
  1833. msdu_info->buf_len));
  1834. tx_desc->flags |= DP_TX_DESC_FLAG_RMNET;
  1835. return paddr;
  1836. }
  1837. #else
  1838. static inline bool
  1839. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1840. {
  1841. return false;
  1842. }
  1843. static inline
  1844. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1845. struct dp_tx_desc_s *tx_desc)
  1846. {
  1847. return 0;
  1848. }
  1849. #endif
  1850. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1851. static inline
  1852. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1853. struct dp_tx_desc_s *tx_desc,
  1854. qdf_nbuf_t nbuf)
  1855. {
  1856. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1857. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1858. (void *)(nbuf->data + nbuf->len));
  1859. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1860. } else {
  1861. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1862. }
  1863. }
  1864. static inline
  1865. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1866. struct dp_tx_desc_s *desc)
  1867. {
  1868. if (qdf_unlikely(!(desc->flags &
  1869. (DP_TX_DESC_FLAG_SIMPLE | DP_TX_DESC_FLAG_RMNET))))
  1870. return dp_tx_nbuf_unmap_regular(soc, desc);
  1871. }
  1872. #else
  1873. static inline
  1874. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1875. struct dp_tx_desc_s *tx_desc,
  1876. qdf_nbuf_t nbuf)
  1877. {
  1878. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1879. }
  1880. static inline
  1881. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1882. struct dp_tx_desc_s *desc)
  1883. {
  1884. return dp_tx_nbuf_unmap_regular(soc, desc);
  1885. }
  1886. #endif
  1887. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1888. static inline
  1889. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1890. {
  1891. dp_tx_nbuf_unmap(soc, desc);
  1892. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1893. }
  1894. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1895. {
  1896. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1897. dp_tx_nbuf_unmap(soc, desc);
  1898. }
  1899. #else
  1900. static inline
  1901. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1902. {
  1903. }
  1904. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1905. {
  1906. dp_tx_nbuf_unmap(soc, desc);
  1907. }
  1908. #endif
  1909. #ifdef MESH_MODE_SUPPORT
  1910. /**
  1911. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1912. * @soc: datapath SOC
  1913. * @vdev: datapath vdev
  1914. * @tx_desc: TX descriptor
  1915. *
  1916. * Return: None
  1917. */
  1918. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1919. struct dp_vdev *vdev,
  1920. struct dp_tx_desc_s *tx_desc)
  1921. {
  1922. if (qdf_unlikely(vdev->mesh_vdev))
  1923. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1924. }
  1925. /**
  1926. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1927. * @soc: dp_soc handle
  1928. * @tx_desc: TX descriptor
  1929. * @delayed_free: delay the nbuf free
  1930. *
  1931. * Return: nbuf to be freed late
  1932. */
  1933. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1934. struct dp_tx_desc_s *tx_desc,
  1935. bool delayed_free)
  1936. {
  1937. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1938. struct dp_vdev *vdev = NULL;
  1939. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1940. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1941. if (vdev)
  1942. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1943. if (delayed_free)
  1944. return nbuf;
  1945. qdf_nbuf_free(nbuf);
  1946. } else {
  1947. if (vdev && vdev->osif_tx_free_ext) {
  1948. vdev->osif_tx_free_ext((nbuf));
  1949. } else {
  1950. if (delayed_free)
  1951. return nbuf;
  1952. qdf_nbuf_free(nbuf);
  1953. }
  1954. }
  1955. if (vdev)
  1956. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1957. return NULL;
  1958. }
  1959. #else
  1960. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1961. struct dp_vdev *vdev,
  1962. struct dp_tx_desc_s *tx_desc)
  1963. {
  1964. }
  1965. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1966. struct dp_tx_desc_s *tx_desc,
  1967. bool delayed_free)
  1968. {
  1969. return NULL;
  1970. }
  1971. #endif
  1972. /**
  1973. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1974. * @vdev: DP vdev handle
  1975. * @nbuf: skb
  1976. *
  1977. * Return: 1 if frame needs to be dropped else 0
  1978. */
  1979. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1980. {
  1981. struct dp_pdev *pdev = NULL;
  1982. struct dp_ast_entry *src_ast_entry = NULL;
  1983. struct dp_ast_entry *dst_ast_entry = NULL;
  1984. struct dp_soc *soc = NULL;
  1985. qdf_assert(vdev);
  1986. pdev = vdev->pdev;
  1987. qdf_assert(pdev);
  1988. soc = pdev->soc;
  1989. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1990. (soc, dstmac, vdev->pdev->pdev_id);
  1991. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1992. (soc, srcmac, vdev->pdev->pdev_id);
  1993. if (dst_ast_entry && src_ast_entry) {
  1994. if (dst_ast_entry->peer_id ==
  1995. src_ast_entry->peer_id)
  1996. return 1;
  1997. }
  1998. return 0;
  1999. }
  2000. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  2001. defined(WLAN_MCAST_MLO)
  2002. /* MLO peer id for reinject*/
  2003. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  2004. /* MLO vdev id inc offset */
  2005. #define DP_MLO_VDEV_ID_OFFSET 0x80
  2006. static inline void
  2007. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2008. {
  2009. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  2010. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2011. qdf_atomic_inc(&soc->num_tx_exception);
  2012. }
  2013. }
  2014. static inline void
  2015. dp_tx_update_mcast_param(uint16_t peer_id,
  2016. uint16_t *htt_tcl_metadata,
  2017. struct dp_vdev *vdev,
  2018. struct dp_tx_msdu_info_s *msdu_info)
  2019. {
  2020. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  2021. *htt_tcl_metadata = 0;
  2022. DP_TX_TCL_METADATA_TYPE_SET(
  2023. *htt_tcl_metadata,
  2024. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  2025. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  2026. msdu_info->gsn);
  2027. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  2028. if (qdf_unlikely(vdev->nawds_enabled))
  2029. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2030. *htt_tcl_metadata, 1);
  2031. } else {
  2032. msdu_info->vdev_id = vdev->vdev_id;
  2033. }
  2034. }
  2035. #else
  2036. static inline void
  2037. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2038. {
  2039. }
  2040. static inline void
  2041. dp_tx_update_mcast_param(uint16_t peer_id,
  2042. uint16_t *htt_tcl_metadata,
  2043. struct dp_vdev *vdev,
  2044. struct dp_tx_msdu_info_s *msdu_info)
  2045. {
  2046. }
  2047. #endif
  2048. #ifdef DP_TX_SW_DROP_STATS_INC
  2049. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2050. qdf_nbuf_t nbuf,
  2051. enum cdp_tx_sw_drop drop_code)
  2052. {
  2053. /* EAPOL Drop stats */
  2054. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  2055. switch (drop_code) {
  2056. case TX_DESC_ERR:
  2057. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  2058. break;
  2059. case TX_HAL_RING_ACCESS_ERR:
  2060. DP_STATS_INC(pdev,
  2061. eap_drop_stats.tx_hal_ring_access_err, 1);
  2062. break;
  2063. case TX_DMA_MAP_ERR:
  2064. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  2065. break;
  2066. case TX_HW_ENQUEUE:
  2067. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  2068. break;
  2069. case TX_SW_ENQUEUE:
  2070. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  2071. break;
  2072. default:
  2073. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  2074. break;
  2075. }
  2076. }
  2077. }
  2078. #else
  2079. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2080. qdf_nbuf_t nbuf,
  2081. enum cdp_tx_sw_drop drop_code)
  2082. {
  2083. }
  2084. #endif
  2085. /**
  2086. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  2087. * @vdev: DP vdev handle
  2088. * @nbuf: skb
  2089. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  2090. * @meta_data: Metadata to the fw
  2091. * @tx_q: Tx queue to be used for this Tx frame
  2092. * @peer_id: peer_id of the peer in case of NAWDS frames
  2093. * @tx_exc_metadata: Handle that holds exception path metadata
  2094. *
  2095. * Return: NULL on success,
  2096. * nbuf when it fails to send
  2097. */
  2098. qdf_nbuf_t
  2099. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2100. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2101. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2102. {
  2103. struct dp_pdev *pdev = vdev->pdev;
  2104. struct dp_soc *soc = pdev->soc;
  2105. struct dp_tx_desc_s *tx_desc;
  2106. QDF_STATUS status;
  2107. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2108. uint16_t htt_tcl_metadata = 0;
  2109. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2110. uint8_t tid = msdu_info->tid;
  2111. struct cdp_tid_tx_stats *tid_stats = NULL;
  2112. qdf_dma_addr_t paddr;
  2113. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2114. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2115. msdu_info, tx_exc_metadata);
  2116. if (!tx_desc) {
  2117. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2118. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2119. drop_code = TX_DESC_ERR;
  2120. goto fail_return;
  2121. }
  2122. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2123. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2124. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2125. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2126. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2127. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2128. DP_TCL_METADATA_TYPE_PEER_BASED);
  2129. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2130. peer_id);
  2131. dp_tx_bypass_reinjection(soc, tx_desc);
  2132. } else
  2133. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2134. if (msdu_info->exception_fw)
  2135. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2136. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2137. !pdev->enhanced_stats_en);
  2138. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2139. if (qdf_unlikely(msdu_info->frm_type == dp_tx_frm_rmnet))
  2140. paddr = dp_tx_rmnet_nbuf_map(msdu_info, tx_desc);
  2141. else
  2142. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2143. if (!paddr) {
  2144. /* Handle failure */
  2145. dp_err("qdf_nbuf_map failed");
  2146. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2147. drop_code = TX_DMA_MAP_ERR;
  2148. goto release_desc;
  2149. }
  2150. tx_desc->dma_addr = paddr;
  2151. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2152. tx_desc->id, DP_TX_DESC_MAP);
  2153. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2154. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2155. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2156. htt_tcl_metadata,
  2157. tx_exc_metadata, msdu_info);
  2158. if (status != QDF_STATUS_SUCCESS) {
  2159. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2160. tx_desc, tx_q->ring_id);
  2161. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2162. tx_desc->id, DP_TX_DESC_UNMAP);
  2163. dp_tx_nbuf_unmap(soc, tx_desc);
  2164. drop_code = TX_HW_ENQUEUE;
  2165. goto release_desc;
  2166. }
  2167. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2168. return NULL;
  2169. release_desc:
  2170. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2171. fail_return:
  2172. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2173. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2174. tid_stats = &pdev->stats.tid_stats.
  2175. tid_tx_stats[tx_q->ring_id][tid];
  2176. tid_stats->swdrop_cnt[drop_code]++;
  2177. return nbuf;
  2178. }
  2179. /**
  2180. * dp_tdls_tx_comp_free_buff() - Free non std buffer when TDLS flag is set
  2181. * @soc: Soc handle
  2182. * @desc: software Tx descriptor to be processed
  2183. *
  2184. * Return: 0 if Success
  2185. */
  2186. #ifdef FEATURE_WLAN_TDLS
  2187. static inline int
  2188. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2189. {
  2190. /* If it is TDLS mgmt, don't unmap or free the frame */
  2191. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2192. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2193. return 0;
  2194. }
  2195. return 1;
  2196. }
  2197. #else
  2198. static inline int
  2199. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2200. {
  2201. return 1;
  2202. }
  2203. #endif
  2204. /**
  2205. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2206. * @soc: Soc handle
  2207. * @desc: software Tx descriptor to be processed
  2208. * @delayed_free: defer freeing of nbuf
  2209. *
  2210. * Return: nbuf to be freed later
  2211. */
  2212. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2213. bool delayed_free)
  2214. {
  2215. qdf_nbuf_t nbuf = desc->nbuf;
  2216. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2217. /* nbuf already freed in vdev detach path */
  2218. if (!nbuf)
  2219. return NULL;
  2220. if (!dp_tdls_tx_comp_free_buff(soc, desc))
  2221. return NULL;
  2222. /* 0 : MSDU buffer, 1 : MLE */
  2223. if (desc->msdu_ext_desc) {
  2224. /* TSO free */
  2225. if (hal_tx_ext_desc_get_tso_enable(
  2226. desc->msdu_ext_desc->vaddr)) {
  2227. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2228. desc->id, DP_TX_COMP_MSDU_EXT);
  2229. dp_tx_tso_seg_history_add(soc,
  2230. desc->msdu_ext_desc->tso_desc,
  2231. desc->nbuf, desc->id, type);
  2232. /* unmap eash TSO seg before free the nbuf */
  2233. dp_tx_tso_unmap_segment(soc,
  2234. desc->msdu_ext_desc->tso_desc,
  2235. desc->msdu_ext_desc->
  2236. tso_num_desc);
  2237. goto nbuf_free;
  2238. }
  2239. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2240. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2241. qdf_dma_addr_t iova;
  2242. uint32_t frag_len;
  2243. uint32_t i;
  2244. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2245. QDF_DMA_TO_DEVICE,
  2246. qdf_nbuf_headlen(nbuf));
  2247. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2248. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2249. &iova,
  2250. &frag_len);
  2251. if (!iova || !frag_len)
  2252. break;
  2253. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2254. QDF_DMA_TO_DEVICE);
  2255. }
  2256. goto nbuf_free;
  2257. }
  2258. }
  2259. /* If it's ME frame, dont unmap the cloned nbuf's */
  2260. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2261. goto nbuf_free;
  2262. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2263. dp_tx_unmap(soc, desc);
  2264. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2265. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2266. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2267. return NULL;
  2268. nbuf_free:
  2269. if (delayed_free)
  2270. return nbuf;
  2271. qdf_nbuf_free(nbuf);
  2272. return NULL;
  2273. }
  2274. /**
  2275. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2276. * @soc: DP soc handle
  2277. * @nbuf: skb
  2278. * @msdu_info: MSDU info
  2279. *
  2280. * Return: None
  2281. */
  2282. static inline void
  2283. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2284. struct dp_tx_msdu_info_s *msdu_info)
  2285. {
  2286. uint32_t cur_idx;
  2287. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2288. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2289. qdf_nbuf_headlen(nbuf));
  2290. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2291. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2292. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2293. seg->frags[cur_idx].paddr_hi) << 32),
  2294. seg->frags[cur_idx].len,
  2295. QDF_DMA_TO_DEVICE);
  2296. }
  2297. /**
  2298. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2299. * @vdev: DP vdev handle
  2300. * @nbuf: skb
  2301. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2302. *
  2303. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2304. *
  2305. * Return: NULL on success,
  2306. * nbuf when it fails to send
  2307. */
  2308. #if QDF_LOCK_STATS
  2309. noinline
  2310. #else
  2311. #endif
  2312. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2313. struct dp_tx_msdu_info_s *msdu_info)
  2314. {
  2315. uint32_t i;
  2316. struct dp_pdev *pdev = vdev->pdev;
  2317. struct dp_soc *soc = pdev->soc;
  2318. struct dp_tx_desc_s *tx_desc;
  2319. bool is_cce_classified = false;
  2320. QDF_STATUS status;
  2321. uint16_t htt_tcl_metadata = 0;
  2322. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2323. struct cdp_tid_tx_stats *tid_stats = NULL;
  2324. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2325. if (msdu_info->frm_type == dp_tx_frm_me)
  2326. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2327. i = 0;
  2328. /* Print statement to track i and num_seg */
  2329. /*
  2330. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2331. * descriptors using information in msdu_info
  2332. */
  2333. while (i < msdu_info->num_seg) {
  2334. /*
  2335. * Setup Tx descriptor for an MSDU, and MSDU extension
  2336. * descriptor
  2337. */
  2338. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2339. tx_q->desc_pool_id);
  2340. if (!tx_desc) {
  2341. if (msdu_info->frm_type == dp_tx_frm_me) {
  2342. prep_desc_fail++;
  2343. dp_tx_me_free_buf(pdev,
  2344. (void *)(msdu_info->u.sg_info
  2345. .curr_seg->frags[0].vaddr));
  2346. if (prep_desc_fail == msdu_info->num_seg) {
  2347. /*
  2348. * Unmap is needed only if descriptor
  2349. * preparation failed for all segments.
  2350. */
  2351. qdf_nbuf_unmap(soc->osdev,
  2352. msdu_info->u.sg_info.
  2353. curr_seg->nbuf,
  2354. QDF_DMA_TO_DEVICE);
  2355. }
  2356. /*
  2357. * Free the nbuf for the current segment
  2358. * and make it point to the next in the list.
  2359. * For me, there are as many segments as there
  2360. * are no of clients.
  2361. */
  2362. qdf_nbuf_free(msdu_info->u.sg_info
  2363. .curr_seg->nbuf);
  2364. if (msdu_info->u.sg_info.curr_seg->next) {
  2365. msdu_info->u.sg_info.curr_seg =
  2366. msdu_info->u.sg_info
  2367. .curr_seg->next;
  2368. nbuf = msdu_info->u.sg_info
  2369. .curr_seg->nbuf;
  2370. }
  2371. i++;
  2372. continue;
  2373. }
  2374. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2375. dp_tx_tso_seg_history_add(
  2376. soc,
  2377. msdu_info->u.tso_info.curr_seg,
  2378. nbuf, 0, DP_TX_DESC_UNMAP);
  2379. dp_tx_tso_unmap_segment(soc,
  2380. msdu_info->u.tso_info.
  2381. curr_seg,
  2382. msdu_info->u.tso_info.
  2383. tso_num_seg_list);
  2384. if (msdu_info->u.tso_info.curr_seg->next) {
  2385. msdu_info->u.tso_info.curr_seg =
  2386. msdu_info->u.tso_info.curr_seg->next;
  2387. i++;
  2388. continue;
  2389. }
  2390. }
  2391. if (msdu_info->frm_type == dp_tx_frm_sg)
  2392. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2393. goto done;
  2394. }
  2395. if (msdu_info->frm_type == dp_tx_frm_me) {
  2396. tx_desc->msdu_ext_desc->me_buffer =
  2397. (struct dp_tx_me_buf_t *)msdu_info->
  2398. u.sg_info.curr_seg->frags[0].vaddr;
  2399. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2400. }
  2401. if (is_cce_classified)
  2402. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2403. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2404. if (msdu_info->exception_fw) {
  2405. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2406. }
  2407. dp_tx_is_hp_update_required(i, msdu_info);
  2408. /*
  2409. * For frames with multiple segments (TSO, ME), jump to next
  2410. * segment.
  2411. */
  2412. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2413. if (msdu_info->u.tso_info.curr_seg->next) {
  2414. msdu_info->u.tso_info.curr_seg =
  2415. msdu_info->u.tso_info.curr_seg->next;
  2416. /*
  2417. * If this is a jumbo nbuf, then increment the
  2418. * number of nbuf users for each additional
  2419. * segment of the msdu. This will ensure that
  2420. * the skb is freed only after receiving tx
  2421. * completion for all segments of an nbuf
  2422. */
  2423. qdf_nbuf_inc_users(nbuf);
  2424. /* Check with MCL if this is needed */
  2425. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2426. */
  2427. }
  2428. }
  2429. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2430. &htt_tcl_metadata,
  2431. vdev,
  2432. msdu_info);
  2433. /*
  2434. * Enqueue the Tx MSDU descriptor to HW for transmit
  2435. */
  2436. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2437. htt_tcl_metadata,
  2438. NULL, msdu_info);
  2439. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2440. if (status != QDF_STATUS_SUCCESS) {
  2441. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2442. tx_desc, tx_q->ring_id);
  2443. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2444. tid_stats = &pdev->stats.tid_stats.
  2445. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2446. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2447. if (msdu_info->frm_type == dp_tx_frm_me) {
  2448. hw_enq_fail++;
  2449. if (hw_enq_fail == msdu_info->num_seg) {
  2450. /*
  2451. * Unmap is needed only if enqueue
  2452. * failed for all segments.
  2453. */
  2454. qdf_nbuf_unmap(soc->osdev,
  2455. msdu_info->u.sg_info.
  2456. curr_seg->nbuf,
  2457. QDF_DMA_TO_DEVICE);
  2458. }
  2459. /*
  2460. * Free the nbuf for the current segment
  2461. * and make it point to the next in the list.
  2462. * For me, there are as many segments as there
  2463. * are no of clients.
  2464. */
  2465. qdf_nbuf_free(msdu_info->u.sg_info
  2466. .curr_seg->nbuf);
  2467. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2468. if (msdu_info->u.sg_info.curr_seg->next) {
  2469. msdu_info->u.sg_info.curr_seg =
  2470. msdu_info->u.sg_info
  2471. .curr_seg->next;
  2472. nbuf = msdu_info->u.sg_info
  2473. .curr_seg->nbuf;
  2474. } else
  2475. break;
  2476. i++;
  2477. continue;
  2478. }
  2479. /*
  2480. * For TSO frames, the nbuf users increment done for
  2481. * the current segment has to be reverted, since the
  2482. * hw enqueue for this segment failed
  2483. */
  2484. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2485. msdu_info->u.tso_info.curr_seg) {
  2486. /*
  2487. * unmap and free current,
  2488. * retransmit remaining segments
  2489. */
  2490. dp_tx_comp_free_buf(soc, tx_desc, false);
  2491. i++;
  2492. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2493. continue;
  2494. }
  2495. if (msdu_info->frm_type == dp_tx_frm_sg)
  2496. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2497. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2498. goto done;
  2499. }
  2500. /*
  2501. * TODO
  2502. * if tso_info structure can be modified to have curr_seg
  2503. * as first element, following 2 blocks of code (for TSO and SG)
  2504. * can be combined into 1
  2505. */
  2506. /*
  2507. * For Multicast-Unicast converted packets,
  2508. * each converted frame (for a client) is represented as
  2509. * 1 segment
  2510. */
  2511. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2512. (msdu_info->frm_type == dp_tx_frm_me)) {
  2513. if (msdu_info->u.sg_info.curr_seg->next) {
  2514. msdu_info->u.sg_info.curr_seg =
  2515. msdu_info->u.sg_info.curr_seg->next;
  2516. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2517. } else
  2518. break;
  2519. }
  2520. i++;
  2521. }
  2522. nbuf = NULL;
  2523. done:
  2524. return nbuf;
  2525. }
  2526. /**
  2527. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2528. * for SG frames
  2529. * @vdev: DP vdev handle
  2530. * @nbuf: skb
  2531. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2532. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2533. *
  2534. * Return: NULL on success,
  2535. * nbuf when it fails to send
  2536. */
  2537. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2538. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2539. {
  2540. uint32_t cur_frag, nr_frags, i;
  2541. qdf_dma_addr_t paddr;
  2542. struct dp_tx_sg_info_s *sg_info;
  2543. sg_info = &msdu_info->u.sg_info;
  2544. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2545. if (QDF_STATUS_SUCCESS !=
  2546. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2547. QDF_DMA_TO_DEVICE,
  2548. qdf_nbuf_headlen(nbuf))) {
  2549. dp_tx_err("dma map error");
  2550. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2551. qdf_nbuf_free(nbuf);
  2552. return NULL;
  2553. }
  2554. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2555. seg_info->frags[0].paddr_lo = paddr;
  2556. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2557. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2558. seg_info->frags[0].vaddr = (void *) nbuf;
  2559. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2560. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2561. nbuf, 0,
  2562. QDF_DMA_TO_DEVICE,
  2563. cur_frag)) {
  2564. dp_tx_err("frag dma map error");
  2565. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2566. goto map_err;
  2567. }
  2568. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2569. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2570. seg_info->frags[cur_frag + 1].paddr_hi =
  2571. ((uint64_t) paddr) >> 32;
  2572. seg_info->frags[cur_frag + 1].len =
  2573. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2574. }
  2575. seg_info->frag_cnt = (cur_frag + 1);
  2576. seg_info->total_len = qdf_nbuf_len(nbuf);
  2577. seg_info->next = NULL;
  2578. sg_info->curr_seg = seg_info;
  2579. msdu_info->frm_type = dp_tx_frm_sg;
  2580. msdu_info->num_seg = 1;
  2581. return nbuf;
  2582. map_err:
  2583. /* restore paddr into nbuf before calling unmap */
  2584. qdf_nbuf_mapped_paddr_set(nbuf,
  2585. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2586. ((uint64_t)
  2587. seg_info->frags[0].paddr_hi) << 32));
  2588. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2589. QDF_DMA_TO_DEVICE,
  2590. seg_info->frags[0].len);
  2591. for (i = 1; i <= cur_frag; i++) {
  2592. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2593. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2594. seg_info->frags[i].paddr_hi) << 32),
  2595. seg_info->frags[i].len,
  2596. QDF_DMA_TO_DEVICE);
  2597. }
  2598. qdf_nbuf_free(nbuf);
  2599. return NULL;
  2600. }
  2601. /**
  2602. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2603. * @vdev: DP vdev handle
  2604. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2605. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2606. *
  2607. * Return: NULL on failure,
  2608. * nbuf when extracted successfully
  2609. */
  2610. static
  2611. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2612. struct dp_tx_msdu_info_s *msdu_info,
  2613. uint16_t ppdu_cookie)
  2614. {
  2615. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2616. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2617. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2618. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2619. (msdu_info->meta_data[5], 1);
  2620. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2621. (msdu_info->meta_data[5], 1);
  2622. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2623. (msdu_info->meta_data[6], ppdu_cookie);
  2624. msdu_info->exception_fw = 1;
  2625. msdu_info->is_tx_sniffer = 1;
  2626. }
  2627. #ifdef MESH_MODE_SUPPORT
  2628. /**
  2629. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2630. and prepare msdu_info for mesh frames.
  2631. * @vdev: DP vdev handle
  2632. * @nbuf: skb
  2633. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2634. *
  2635. * Return: NULL on failure,
  2636. * nbuf when extracted successfully
  2637. */
  2638. static
  2639. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2640. struct dp_tx_msdu_info_s *msdu_info)
  2641. {
  2642. struct meta_hdr_s *mhdr;
  2643. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2644. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2645. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2646. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2647. msdu_info->exception_fw = 0;
  2648. goto remove_meta_hdr;
  2649. }
  2650. msdu_info->exception_fw = 1;
  2651. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2652. meta_data->host_tx_desc_pool = 1;
  2653. meta_data->update_peer_cache = 1;
  2654. meta_data->learning_frame = 1;
  2655. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2656. meta_data->power = mhdr->power;
  2657. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2658. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2659. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2660. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2661. meta_data->dyn_bw = 1;
  2662. meta_data->valid_pwr = 1;
  2663. meta_data->valid_mcs_mask = 1;
  2664. meta_data->valid_nss_mask = 1;
  2665. meta_data->valid_preamble_type = 1;
  2666. meta_data->valid_retries = 1;
  2667. meta_data->valid_bw_info = 1;
  2668. }
  2669. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2670. meta_data->encrypt_type = 0;
  2671. meta_data->valid_encrypt_type = 1;
  2672. meta_data->learning_frame = 0;
  2673. }
  2674. meta_data->valid_key_flags = 1;
  2675. meta_data->key_flags = (mhdr->keyix & 0x3);
  2676. remove_meta_hdr:
  2677. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2678. dp_tx_err("qdf_nbuf_pull_head failed");
  2679. qdf_nbuf_free(nbuf);
  2680. return NULL;
  2681. }
  2682. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2683. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2684. " tid %d to_fw %d",
  2685. msdu_info->meta_data[0],
  2686. msdu_info->meta_data[1],
  2687. msdu_info->meta_data[2],
  2688. msdu_info->meta_data[3],
  2689. msdu_info->meta_data[4],
  2690. msdu_info->meta_data[5],
  2691. msdu_info->tid, msdu_info->exception_fw);
  2692. return nbuf;
  2693. }
  2694. #else
  2695. static
  2696. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2697. struct dp_tx_msdu_info_s *msdu_info)
  2698. {
  2699. return nbuf;
  2700. }
  2701. #endif
  2702. /**
  2703. * dp_check_exc_metadata() - Checks if parameters are valid
  2704. * @tx_exc - holds all exception path parameters
  2705. *
  2706. * Returns true when all the parameters are valid else false
  2707. *
  2708. */
  2709. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2710. {
  2711. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2712. HTT_INVALID_TID);
  2713. bool invalid_encap_type =
  2714. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2715. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2716. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2717. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2718. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2719. tx_exc->ppdu_cookie == 0);
  2720. if (tx_exc->is_intrabss_fwd)
  2721. return true;
  2722. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2723. invalid_cookie) {
  2724. return false;
  2725. }
  2726. return true;
  2727. }
  2728. #ifdef ATH_SUPPORT_IQUE
  2729. /**
  2730. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2731. * @vdev: vdev handle
  2732. * @nbuf: skb
  2733. *
  2734. * Return: true on success,
  2735. * false on failure
  2736. */
  2737. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2738. {
  2739. qdf_ether_header_t *eh;
  2740. /* Mcast to Ucast Conversion*/
  2741. if (qdf_likely(!vdev->mcast_enhancement_en))
  2742. return true;
  2743. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2744. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2745. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2746. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2747. qdf_nbuf_set_next(nbuf, NULL);
  2748. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2749. qdf_nbuf_len(nbuf));
  2750. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2751. QDF_STATUS_SUCCESS) {
  2752. return false;
  2753. }
  2754. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2755. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2756. QDF_STATUS_SUCCESS) {
  2757. return false;
  2758. }
  2759. }
  2760. }
  2761. return true;
  2762. }
  2763. #else
  2764. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2765. {
  2766. return true;
  2767. }
  2768. #endif
  2769. #ifdef QCA_SUPPORT_WDS_EXTENDED
  2770. /**
  2771. * dp_tx_mcast_drop() - Drop mcast frame if drop_tx_mcast is set in WDS_EXT
  2772. * @vdev: vdev handle
  2773. * @nbuf: skb
  2774. *
  2775. * Return: true if frame is dropped, false otherwise
  2776. */
  2777. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2778. {
  2779. /* Drop tx mcast and WDS Extended feature check */
  2780. if (qdf_unlikely((vdev->drop_tx_mcast) && (vdev->wds_ext_enabled))) {
  2781. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2782. qdf_nbuf_data(nbuf);
  2783. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  2784. DP_STATS_INC(vdev, tx_i.dropped.tx_mcast_drop, 1);
  2785. return true;
  2786. }
  2787. }
  2788. return false;
  2789. }
  2790. #else
  2791. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2792. {
  2793. return false;
  2794. }
  2795. #endif
  2796. /**
  2797. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2798. * @nbuf: qdf_nbuf_t
  2799. * @vdev: struct dp_vdev *
  2800. *
  2801. * Allow packet for processing only if it is for peer client which is
  2802. * connected with same vap. Drop packet if client is connected to
  2803. * different vap.
  2804. *
  2805. * Return: QDF_STATUS
  2806. */
  2807. static inline QDF_STATUS
  2808. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2809. {
  2810. struct dp_ast_entry *dst_ast_entry = NULL;
  2811. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2812. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2813. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2814. return QDF_STATUS_SUCCESS;
  2815. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2816. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2817. eh->ether_dhost,
  2818. vdev->vdev_id);
  2819. /* If there is no ast entry, return failure */
  2820. if (qdf_unlikely(!dst_ast_entry)) {
  2821. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2822. return QDF_STATUS_E_FAILURE;
  2823. }
  2824. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2825. return QDF_STATUS_SUCCESS;
  2826. }
  2827. /**
  2828. * dp_tx_nawds_handler() - NAWDS handler
  2829. *
  2830. * @soc: DP soc handle
  2831. * @vdev_id: id of DP vdev handle
  2832. * @msdu_info: msdu_info required to create HTT metadata
  2833. * @nbuf: skb
  2834. *
  2835. * This API transfers the multicast frames with the peer id
  2836. * on NAWDS enabled peer.
  2837. * Return: none
  2838. */
  2839. static inline
  2840. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2841. struct dp_tx_msdu_info_s *msdu_info,
  2842. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2843. {
  2844. struct dp_peer *peer = NULL;
  2845. qdf_nbuf_t nbuf_clone = NULL;
  2846. uint16_t peer_id = DP_INVALID_PEER;
  2847. struct dp_txrx_peer *txrx_peer;
  2848. /* This check avoids pkt forwarding which is entered
  2849. * in the ast table but still doesn't have valid peerid.
  2850. */
  2851. if (sa_peer_id == HTT_INVALID_PEER)
  2852. return;
  2853. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2854. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2855. txrx_peer = dp_get_txrx_peer(peer);
  2856. if (!txrx_peer)
  2857. continue;
  2858. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2859. peer_id = peer->peer_id;
  2860. if (!dp_peer_is_primary_link_peer(peer))
  2861. continue;
  2862. /* Multicast packets needs to be
  2863. * dropped in case of intra bss forwarding
  2864. */
  2865. if (sa_peer_id == txrx_peer->peer_id) {
  2866. dp_tx_debug("multicast packet");
  2867. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2868. tx.nawds_mcast_drop,
  2869. 1);
  2870. continue;
  2871. }
  2872. nbuf_clone = qdf_nbuf_clone(nbuf);
  2873. if (!nbuf_clone) {
  2874. QDF_TRACE(QDF_MODULE_ID_DP,
  2875. QDF_TRACE_LEVEL_ERROR,
  2876. FL("nbuf clone failed"));
  2877. break;
  2878. }
  2879. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2880. msdu_info, peer_id,
  2881. NULL);
  2882. if (nbuf_clone) {
  2883. dp_tx_debug("pkt send failed");
  2884. qdf_nbuf_free(nbuf_clone);
  2885. } else {
  2886. if (peer_id != DP_INVALID_PEER)
  2887. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2888. tx.nawds_mcast,
  2889. 1, qdf_nbuf_len(nbuf));
  2890. }
  2891. }
  2892. }
  2893. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2894. }
  2895. /**
  2896. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2897. * @soc: DP soc handle
  2898. * @vdev_id: id of DP vdev handle
  2899. * @nbuf: skb
  2900. * @tx_exc_metadata: Handle that holds exception path meta data
  2901. *
  2902. * Entry point for Core Tx layer (DP_TX) invoked from
  2903. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2904. *
  2905. * Return: NULL on success,
  2906. * nbuf when it fails to send
  2907. */
  2908. qdf_nbuf_t
  2909. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2910. qdf_nbuf_t nbuf,
  2911. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2912. {
  2913. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2914. qdf_ether_header_t *eh = NULL;
  2915. struct dp_tx_msdu_info_s msdu_info;
  2916. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2917. DP_MOD_ID_TX_EXCEPTION);
  2918. if (qdf_unlikely(!vdev))
  2919. goto fail;
  2920. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2921. if (!tx_exc_metadata)
  2922. goto fail;
  2923. msdu_info.tid = tx_exc_metadata->tid;
  2924. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2925. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2926. QDF_MAC_ADDR_REF(nbuf->data));
  2927. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2928. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2929. dp_tx_err("Invalid parameters in exception path");
  2930. goto fail;
  2931. }
  2932. /* for peer based metadata check if peer is valid */
  2933. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2934. struct dp_peer *peer = NULL;
  2935. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2936. tx_exc_metadata->peer_id,
  2937. DP_MOD_ID_TX_EXCEPTION);
  2938. if (qdf_unlikely(!peer)) {
  2939. DP_STATS_INC(vdev,
  2940. tx_i.dropped.invalid_peer_id_in_exc_path,
  2941. 1);
  2942. goto fail;
  2943. }
  2944. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2945. }
  2946. /* Basic sanity checks for unsupported packets */
  2947. /* MESH mode */
  2948. if (qdf_unlikely(vdev->mesh_vdev)) {
  2949. dp_tx_err("Mesh mode is not supported in exception path");
  2950. goto fail;
  2951. }
  2952. /*
  2953. * Classify the frame and call corresponding
  2954. * "prepare" function which extracts the segment (TSO)
  2955. * and fragmentation information (for TSO , SG, ME, or Raw)
  2956. * into MSDU_INFO structure which is later used to fill
  2957. * SW and HW descriptors.
  2958. */
  2959. if (qdf_nbuf_is_tso(nbuf)) {
  2960. dp_verbose_debug("TSO frame %pK", vdev);
  2961. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2962. qdf_nbuf_len(nbuf));
  2963. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2964. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2965. qdf_nbuf_len(nbuf));
  2966. goto fail;
  2967. }
  2968. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  2969. goto send_multiple;
  2970. }
  2971. /* SG */
  2972. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2973. struct dp_tx_seg_info_s seg_info = {0};
  2974. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2975. if (!nbuf)
  2976. goto fail;
  2977. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2978. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2979. qdf_nbuf_len(nbuf));
  2980. goto send_multiple;
  2981. }
  2982. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2983. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2984. qdf_nbuf_len(nbuf));
  2985. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2986. tx_exc_metadata->ppdu_cookie);
  2987. }
  2988. /*
  2989. * Get HW Queue to use for this frame.
  2990. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2991. * dedicated for data and 1 for command.
  2992. * "queue_id" maps to one hardware ring.
  2993. * With each ring, we also associate a unique Tx descriptor pool
  2994. * to minimize lock contention for these resources.
  2995. */
  2996. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2997. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2998. if (qdf_unlikely(vdev->nawds_enabled)) {
  2999. /*
  3000. * This is a multicast packet
  3001. */
  3002. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3003. tx_exc_metadata->peer_id);
  3004. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3005. 1, qdf_nbuf_len(nbuf));
  3006. }
  3007. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  3008. DP_INVALID_PEER, NULL);
  3009. } else {
  3010. /*
  3011. * Check exception descriptors
  3012. */
  3013. if (dp_tx_exception_limit_check(vdev))
  3014. goto fail;
  3015. /* Single linear frame */
  3016. /*
  3017. * If nbuf is a simple linear frame, use send_single function to
  3018. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3019. * SRNG. There is no need to setup a MSDU extension descriptor.
  3020. */
  3021. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  3022. tx_exc_metadata->peer_id,
  3023. tx_exc_metadata);
  3024. }
  3025. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3026. return nbuf;
  3027. send_multiple:
  3028. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3029. fail:
  3030. if (vdev)
  3031. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3032. dp_verbose_debug("pkt send failed");
  3033. return nbuf;
  3034. }
  3035. /**
  3036. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  3037. * in exception path in special case to avoid regular exception path chk.
  3038. * @soc: DP soc handle
  3039. * @vdev_id: id of DP vdev handle
  3040. * @nbuf: skb
  3041. * @tx_exc_metadata: Handle that holds exception path meta data
  3042. *
  3043. * Entry point for Core Tx layer (DP_TX) invoked from
  3044. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  3045. *
  3046. * Return: NULL on success,
  3047. * nbuf when it fails to send
  3048. */
  3049. qdf_nbuf_t
  3050. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3051. uint8_t vdev_id, qdf_nbuf_t nbuf,
  3052. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3053. {
  3054. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3055. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3056. DP_MOD_ID_TX_EXCEPTION);
  3057. if (qdf_unlikely(!vdev))
  3058. goto fail;
  3059. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3060. == QDF_STATUS_E_FAILURE)) {
  3061. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3062. goto fail;
  3063. }
  3064. /* Unref count as it will again be taken inside dp_tx_exception */
  3065. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3066. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  3067. fail:
  3068. if (vdev)
  3069. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3070. dp_verbose_debug("pkt send failed");
  3071. return nbuf;
  3072. }
  3073. /**
  3074. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  3075. * @soc: DP soc handle
  3076. * @vdev_id: DP vdev handle
  3077. * @nbuf: skb
  3078. *
  3079. * Entry point for Core Tx layer (DP_TX) invoked from
  3080. * hard_start_xmit in OSIF/HDD
  3081. *
  3082. * Return: NULL on success,
  3083. * nbuf when it fails to send
  3084. */
  3085. #ifdef MESH_MODE_SUPPORT
  3086. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3087. qdf_nbuf_t nbuf)
  3088. {
  3089. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3090. struct meta_hdr_s *mhdr;
  3091. qdf_nbuf_t nbuf_mesh = NULL;
  3092. qdf_nbuf_t nbuf_clone = NULL;
  3093. struct dp_vdev *vdev;
  3094. uint8_t no_enc_frame = 0;
  3095. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3096. if (!nbuf_mesh) {
  3097. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3098. "qdf_nbuf_unshare failed");
  3099. return nbuf;
  3100. }
  3101. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3102. if (!vdev) {
  3103. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3104. "vdev is NULL for vdev_id %d", vdev_id);
  3105. return nbuf;
  3106. }
  3107. nbuf = nbuf_mesh;
  3108. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3109. if ((vdev->sec_type != cdp_sec_type_none) &&
  3110. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3111. no_enc_frame = 1;
  3112. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3113. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3114. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3115. !no_enc_frame) {
  3116. nbuf_clone = qdf_nbuf_clone(nbuf);
  3117. if (!nbuf_clone) {
  3118. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3119. "qdf_nbuf_clone failed");
  3120. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3121. return nbuf;
  3122. }
  3123. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3124. }
  3125. if (nbuf_clone) {
  3126. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3127. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3128. } else {
  3129. qdf_nbuf_free(nbuf_clone);
  3130. }
  3131. }
  3132. if (no_enc_frame)
  3133. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3134. else
  3135. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3136. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3137. if ((!nbuf) && no_enc_frame) {
  3138. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3139. }
  3140. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3141. return nbuf;
  3142. }
  3143. #else
  3144. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  3145. qdf_nbuf_t nbuf)
  3146. {
  3147. return dp_tx_send(soc, vdev_id, nbuf);
  3148. }
  3149. #endif
  3150. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3151. static inline
  3152. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3153. {
  3154. if (nbuf) {
  3155. qdf_prefetch(&nbuf->len);
  3156. qdf_prefetch(&nbuf->data);
  3157. }
  3158. }
  3159. #else
  3160. static inline
  3161. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3162. {
  3163. }
  3164. #endif
  3165. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3166. /*
  3167. * dp_tx_drop() - Drop the frame on a given VAP
  3168. * @soc: DP soc handle
  3169. * @vdev_id: id of DP vdev handle
  3170. * @nbuf: skb
  3171. *
  3172. * Drop all the incoming packets
  3173. *
  3174. * Return: nbuf
  3175. *
  3176. */
  3177. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3178. qdf_nbuf_t nbuf)
  3179. {
  3180. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3181. struct dp_vdev *vdev = NULL;
  3182. vdev = soc->vdev_id_map[vdev_id];
  3183. if (qdf_unlikely(!vdev))
  3184. return nbuf;
  3185. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3186. return nbuf;
  3187. }
  3188. /*
  3189. * dp_tx_exc_drop() - Drop the frame on a given VAP
  3190. * @soc: DP soc handle
  3191. * @vdev_id: id of DP vdev handle
  3192. * @nbuf: skb
  3193. * @tx_exc_metadata: Handle that holds exception path meta data
  3194. *
  3195. * Drop all the incoming packets
  3196. *
  3197. * Return: nbuf
  3198. *
  3199. */
  3200. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3201. qdf_nbuf_t nbuf,
  3202. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3203. {
  3204. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3205. }
  3206. #endif
  3207. /*
  3208. * dp_tx_send() - Transmit a frame on a given VAP
  3209. * @soc: DP soc handle
  3210. * @vdev_id: id of DP vdev handle
  3211. * @nbuf: skb
  3212. *
  3213. * Entry point for Core Tx layer (DP_TX) invoked from
  3214. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3215. * cases
  3216. *
  3217. * Return: NULL on success,
  3218. * nbuf when it fails to send
  3219. */
  3220. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3221. qdf_nbuf_t nbuf)
  3222. {
  3223. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3224. uint16_t peer_id = HTT_INVALID_PEER;
  3225. /*
  3226. * doing a memzero is causing additional function call overhead
  3227. * so doing static stack clearing
  3228. */
  3229. struct dp_tx_msdu_info_s msdu_info = {0};
  3230. struct dp_vdev *vdev = NULL;
  3231. qdf_nbuf_t end_nbuf = NULL;
  3232. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3233. return nbuf;
  3234. /*
  3235. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3236. * this in per packet path.
  3237. *
  3238. * As in this path vdev memory is already protected with netdev
  3239. * tx lock
  3240. */
  3241. vdev = soc->vdev_id_map[vdev_id];
  3242. if (qdf_unlikely(!vdev))
  3243. return nbuf;
  3244. /*
  3245. * Set Default Host TID value to invalid TID
  3246. * (TID override disabled)
  3247. */
  3248. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3249. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  3250. if (qdf_unlikely(vdev->mesh_vdev)) {
  3251. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3252. &msdu_info);
  3253. if (!nbuf_mesh) {
  3254. dp_verbose_debug("Extracting mesh metadata failed");
  3255. return nbuf;
  3256. }
  3257. nbuf = nbuf_mesh;
  3258. }
  3259. /*
  3260. * Get HW Queue to use for this frame.
  3261. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3262. * dedicated for data and 1 for command.
  3263. * "queue_id" maps to one hardware ring.
  3264. * With each ring, we also associate a unique Tx descriptor pool
  3265. * to minimize lock contention for these resources.
  3266. */
  3267. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3268. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3269. 1);
  3270. /*
  3271. * TCL H/W supports 2 DSCP-TID mapping tables.
  3272. * Table 1 - Default DSCP-TID mapping table
  3273. * Table 2 - 1 DSCP-TID override table
  3274. *
  3275. * If we need a different DSCP-TID mapping for this vap,
  3276. * call tid_classify to extract DSCP/ToS from frame and
  3277. * map to a TID and store in msdu_info. This is later used
  3278. * to fill in TCL Input descriptor (per-packet TID override).
  3279. */
  3280. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3281. /*
  3282. * Classify the frame and call corresponding
  3283. * "prepare" function which extracts the segment (TSO)
  3284. * and fragmentation information (for TSO , SG, ME, or Raw)
  3285. * into MSDU_INFO structure which is later used to fill
  3286. * SW and HW descriptors.
  3287. */
  3288. if (qdf_nbuf_is_tso(nbuf)) {
  3289. dp_verbose_debug("TSO frame %pK", vdev);
  3290. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3291. qdf_nbuf_len(nbuf));
  3292. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3293. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3294. qdf_nbuf_len(nbuf));
  3295. return nbuf;
  3296. }
  3297. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  3298. goto send_multiple;
  3299. }
  3300. /* SG */
  3301. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3302. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3303. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3304. return nbuf;
  3305. } else {
  3306. struct dp_tx_seg_info_s seg_info = {0};
  3307. if (qdf_unlikely(is_nbuf_frm_rmnet(nbuf, &msdu_info)))
  3308. goto send_single;
  3309. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3310. &msdu_info);
  3311. if (!nbuf)
  3312. return NULL;
  3313. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3314. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3315. qdf_nbuf_len(nbuf));
  3316. goto send_multiple;
  3317. }
  3318. }
  3319. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3320. return NULL;
  3321. if (qdf_unlikely(dp_tx_mcast_drop(vdev, nbuf)))
  3322. return nbuf;
  3323. /* RAW */
  3324. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3325. struct dp_tx_seg_info_s seg_info = {0};
  3326. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3327. if (!nbuf)
  3328. return NULL;
  3329. dp_verbose_debug("Raw frame %pK", vdev);
  3330. goto send_multiple;
  3331. }
  3332. if (qdf_unlikely(vdev->nawds_enabled)) {
  3333. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3334. qdf_nbuf_data(nbuf);
  3335. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3336. uint16_t sa_peer_id = DP_INVALID_PEER;
  3337. if (!soc->ast_offload_support) {
  3338. struct dp_ast_entry *ast_entry = NULL;
  3339. qdf_spin_lock_bh(&soc->ast_lock);
  3340. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3341. (soc,
  3342. (uint8_t *)(eh->ether_shost),
  3343. vdev->pdev->pdev_id);
  3344. if (ast_entry)
  3345. sa_peer_id = ast_entry->peer_id;
  3346. qdf_spin_unlock_bh(&soc->ast_lock);
  3347. }
  3348. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3349. sa_peer_id);
  3350. }
  3351. peer_id = DP_INVALID_PEER;
  3352. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3353. 1, qdf_nbuf_len(nbuf));
  3354. }
  3355. send_single:
  3356. /* Single linear frame */
  3357. /*
  3358. * If nbuf is a simple linear frame, use send_single function to
  3359. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3360. * SRNG. There is no need to setup a MSDU extension descriptor.
  3361. */
  3362. dp_tx_prefetch_nbuf_data(nbuf);
  3363. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3364. peer_id, end_nbuf);
  3365. return nbuf;
  3366. send_multiple:
  3367. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3368. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3369. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3370. return nbuf;
  3371. }
  3372. /**
  3373. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3374. * case to vaoid check in perpkt path.
  3375. * @soc: DP soc handle
  3376. * @vdev_id: id of DP vdev handle
  3377. * @nbuf: skb
  3378. *
  3379. * Entry point for Core Tx layer (DP_TX) invoked from
  3380. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3381. * with special condition to avoid per pkt check in dp_tx_send
  3382. *
  3383. * Return: NULL on success,
  3384. * nbuf when it fails to send
  3385. */
  3386. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3387. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3388. {
  3389. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3390. struct dp_vdev *vdev = NULL;
  3391. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3392. return nbuf;
  3393. /*
  3394. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3395. * this in per packet path.
  3396. *
  3397. * As in this path vdev memory is already protected with netdev
  3398. * tx lock
  3399. */
  3400. vdev = soc->vdev_id_map[vdev_id];
  3401. if (qdf_unlikely(!vdev))
  3402. return nbuf;
  3403. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3404. == QDF_STATUS_E_FAILURE)) {
  3405. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3406. return nbuf;
  3407. }
  3408. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3409. }
  3410. #ifdef UMAC_SUPPORT_PROXY_ARP
  3411. /**
  3412. * dp_tx_proxy_arp() - Tx proxy arp handler
  3413. * @vdev: datapath vdev handle
  3414. * @buf: sk buffer
  3415. *
  3416. * Return: status
  3417. */
  3418. static inline
  3419. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3420. {
  3421. if (vdev->osif_proxy_arp)
  3422. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3423. /*
  3424. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3425. * osif_proxy_arp has a valid function pointer assigned
  3426. * to it
  3427. */
  3428. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3429. return QDF_STATUS_NOT_INITIALIZED;
  3430. }
  3431. #else
  3432. /**
  3433. * dp_tx_proxy_arp() - Tx proxy arp handler
  3434. * @vdev: datapath vdev handle
  3435. * @buf: sk buffer
  3436. *
  3437. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3438. * is not defined.
  3439. *
  3440. * Return: status
  3441. */
  3442. static inline
  3443. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3444. {
  3445. return QDF_STATUS_SUCCESS;
  3446. }
  3447. #endif
  3448. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3449. #ifdef WLAN_MCAST_MLO
  3450. static bool
  3451. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3452. struct dp_tx_desc_s *tx_desc,
  3453. qdf_nbuf_t nbuf,
  3454. uint8_t reinject_reason)
  3455. {
  3456. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3457. if (soc->arch_ops.dp_tx_mcast_handler)
  3458. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3459. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3460. return true;
  3461. }
  3462. return false;
  3463. }
  3464. #else /* WLAN_MCAST_MLO */
  3465. static inline bool
  3466. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3467. struct dp_tx_desc_s *tx_desc,
  3468. qdf_nbuf_t nbuf,
  3469. uint8_t reinject_reason)
  3470. {
  3471. return false;
  3472. }
  3473. #endif /* WLAN_MCAST_MLO */
  3474. #else
  3475. static inline bool
  3476. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3477. struct dp_tx_desc_s *tx_desc,
  3478. qdf_nbuf_t nbuf,
  3479. uint8_t reinject_reason)
  3480. {
  3481. return false;
  3482. }
  3483. #endif
  3484. /**
  3485. * dp_tx_reinject_handler() - Tx Reinject Handler
  3486. * @soc: datapath soc handle
  3487. * @vdev: datapath vdev handle
  3488. * @tx_desc: software descriptor head pointer
  3489. * @status : Tx completion status from HTT descriptor
  3490. * @reinject_reason : reinject reason from HTT descriptor
  3491. *
  3492. * This function reinjects frames back to Target.
  3493. * Todo - Host queue needs to be added
  3494. *
  3495. * Return: none
  3496. */
  3497. void dp_tx_reinject_handler(struct dp_soc *soc,
  3498. struct dp_vdev *vdev,
  3499. struct dp_tx_desc_s *tx_desc,
  3500. uint8_t *status,
  3501. uint8_t reinject_reason)
  3502. {
  3503. struct dp_peer *peer = NULL;
  3504. uint32_t peer_id = HTT_INVALID_PEER;
  3505. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3506. qdf_nbuf_t nbuf_copy = NULL;
  3507. struct dp_tx_msdu_info_s msdu_info;
  3508. #ifdef WDS_VENDOR_EXTENSION
  3509. int is_mcast = 0, is_ucast = 0;
  3510. int num_peers_3addr = 0;
  3511. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3512. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3513. #endif
  3514. struct dp_txrx_peer *txrx_peer;
  3515. qdf_assert(vdev);
  3516. dp_tx_debug("Tx reinject path");
  3517. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3518. qdf_nbuf_len(tx_desc->nbuf));
  3519. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3520. return;
  3521. #ifdef WDS_VENDOR_EXTENSION
  3522. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3523. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3524. } else {
  3525. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3526. }
  3527. is_ucast = !is_mcast;
  3528. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3529. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3530. txrx_peer = dp_get_txrx_peer(peer);
  3531. if (!txrx_peer || txrx_peer->bss_peer)
  3532. continue;
  3533. /* Detect wds peers that use 3-addr framing for mcast.
  3534. * if there are any, the bss_peer is used to send the
  3535. * the mcast frame using 3-addr format. all wds enabled
  3536. * peers that use 4-addr framing for mcast frames will
  3537. * be duplicated and sent as 4-addr frames below.
  3538. */
  3539. if (!txrx_peer->wds_enabled ||
  3540. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3541. num_peers_3addr = 1;
  3542. break;
  3543. }
  3544. }
  3545. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3546. #endif
  3547. if (qdf_unlikely(vdev->mesh_vdev)) {
  3548. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3549. } else {
  3550. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3551. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3552. txrx_peer = dp_get_txrx_peer(peer);
  3553. if (!txrx_peer)
  3554. continue;
  3555. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3556. #ifdef WDS_VENDOR_EXTENSION
  3557. /*
  3558. * . if 3-addr STA, then send on BSS Peer
  3559. * . if Peer WDS enabled and accept 4-addr mcast,
  3560. * send mcast on that peer only
  3561. * . if Peer WDS enabled and accept 4-addr ucast,
  3562. * send ucast on that peer only
  3563. */
  3564. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3565. (txrx_peer->wds_enabled &&
  3566. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3567. (is_ucast &&
  3568. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3569. #else
  3570. (txrx_peer->bss_peer &&
  3571. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3572. #endif
  3573. peer_id = DP_INVALID_PEER;
  3574. nbuf_copy = qdf_nbuf_copy(nbuf);
  3575. if (!nbuf_copy) {
  3576. dp_tx_debug("nbuf copy failed");
  3577. break;
  3578. }
  3579. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3580. dp_tx_get_queue(vdev, nbuf,
  3581. &msdu_info.tx_queue);
  3582. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3583. nbuf_copy,
  3584. &msdu_info,
  3585. peer_id,
  3586. NULL);
  3587. if (nbuf_copy) {
  3588. dp_tx_debug("pkt send failed");
  3589. qdf_nbuf_free(nbuf_copy);
  3590. }
  3591. }
  3592. }
  3593. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3594. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3595. QDF_DMA_TO_DEVICE, nbuf->len);
  3596. qdf_nbuf_free(nbuf);
  3597. }
  3598. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3599. }
  3600. /**
  3601. * dp_tx_inspect_handler() - Tx Inspect Handler
  3602. * @soc: datapath soc handle
  3603. * @vdev: datapath vdev handle
  3604. * @tx_desc: software descriptor head pointer
  3605. * @status : Tx completion status from HTT descriptor
  3606. *
  3607. * Handles Tx frames sent back to Host for inspection
  3608. * (ProxyARP)
  3609. *
  3610. * Return: none
  3611. */
  3612. void dp_tx_inspect_handler(struct dp_soc *soc,
  3613. struct dp_vdev *vdev,
  3614. struct dp_tx_desc_s *tx_desc,
  3615. uint8_t *status)
  3616. {
  3617. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3618. "%s Tx inspect path",
  3619. __func__);
  3620. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3621. qdf_nbuf_len(tx_desc->nbuf));
  3622. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3623. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3624. }
  3625. #ifdef MESH_MODE_SUPPORT
  3626. /**
  3627. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3628. * in mesh meta header
  3629. * @tx_desc: software descriptor head pointer
  3630. * @ts: pointer to tx completion stats
  3631. * Return: none
  3632. */
  3633. static
  3634. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3635. struct hal_tx_completion_status *ts)
  3636. {
  3637. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3638. if (!tx_desc->msdu_ext_desc) {
  3639. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3640. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3641. "netbuf %pK offset %d",
  3642. netbuf, tx_desc->pkt_offset);
  3643. return;
  3644. }
  3645. }
  3646. }
  3647. #else
  3648. static
  3649. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3650. struct hal_tx_completion_status *ts)
  3651. {
  3652. }
  3653. #endif
  3654. #ifdef CONFIG_SAWF
  3655. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3656. struct dp_vdev *vdev,
  3657. struct dp_txrx_peer *txrx_peer,
  3658. struct dp_tx_desc_s *tx_desc,
  3659. struct hal_tx_completion_status *ts,
  3660. uint8_t tid)
  3661. {
  3662. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3663. ts, tid);
  3664. }
  3665. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3666. uint32_t nw_delay,
  3667. uint32_t sw_delay,
  3668. uint32_t hw_delay)
  3669. {
  3670. dp_peer_tid_delay_avg(tx_delay,
  3671. nw_delay,
  3672. sw_delay,
  3673. hw_delay);
  3674. }
  3675. #else
  3676. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3677. struct dp_vdev *vdev,
  3678. struct dp_txrx_peer *txrx_peer,
  3679. struct dp_tx_desc_s *tx_desc,
  3680. struct hal_tx_completion_status *ts,
  3681. uint8_t tid)
  3682. {
  3683. }
  3684. static inline void
  3685. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3686. uint32_t nw_delay, uint32_t sw_delay,
  3687. uint32_t hw_delay)
  3688. {
  3689. }
  3690. #endif
  3691. #ifdef QCA_PEER_EXT_STATS
  3692. #ifdef WLAN_CONFIG_TX_DELAY
  3693. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3694. struct dp_tx_desc_s *tx_desc,
  3695. struct hal_tx_completion_status *ts,
  3696. struct dp_vdev *vdev)
  3697. {
  3698. struct dp_soc *soc = vdev->pdev->soc;
  3699. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3700. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3701. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3702. if (!ts->valid)
  3703. return;
  3704. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3705. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3706. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3707. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3708. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3709. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3710. &fwhw_transmit_delay))
  3711. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3712. fwhw_transmit_delay);
  3713. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3714. fwhw_transmit_delay);
  3715. }
  3716. #else
  3717. /*
  3718. * dp_tx_compute_tid_delay() - Compute per TID delay
  3719. * @stats: Per TID delay stats
  3720. * @tx_desc: Software Tx descriptor
  3721. * @ts: Tx completion status
  3722. * @vdev: vdev
  3723. *
  3724. * Compute the software enqueue and hw enqueue delays and
  3725. * update the respective histograms
  3726. *
  3727. * Return: void
  3728. */
  3729. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3730. struct dp_tx_desc_s *tx_desc,
  3731. struct hal_tx_completion_status *ts,
  3732. struct dp_vdev *vdev)
  3733. {
  3734. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3735. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3736. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3737. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3738. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3739. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3740. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3741. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3742. timestamp_hw_enqueue);
  3743. /*
  3744. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3745. */
  3746. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3747. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3748. }
  3749. #endif
  3750. /*
  3751. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3752. * @txrx_peer: DP peer context
  3753. * @tx_desc: Tx software descriptor
  3754. * @tid: Transmission ID
  3755. * @ring_id: Rx CPU context ID/CPU_ID
  3756. *
  3757. * Update the peer extended stats. These are enhanced other
  3758. * delay stats per msdu level.
  3759. *
  3760. * Return: void
  3761. */
  3762. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3763. struct dp_tx_desc_s *tx_desc,
  3764. struct hal_tx_completion_status *ts,
  3765. uint8_t ring_id)
  3766. {
  3767. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3768. struct dp_soc *soc = NULL;
  3769. struct dp_peer_delay_stats *delay_stats = NULL;
  3770. uint8_t tid;
  3771. soc = pdev->soc;
  3772. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3773. return;
  3774. tid = ts->tid;
  3775. delay_stats = txrx_peer->delay_stats;
  3776. qdf_assert(delay_stats);
  3777. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3778. /*
  3779. * For non-TID packets use the TID 9
  3780. */
  3781. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3782. tid = CDP_MAX_DATA_TIDS - 1;
  3783. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3784. tx_desc, ts, txrx_peer->vdev);
  3785. }
  3786. #else
  3787. static inline
  3788. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3789. struct dp_tx_desc_s *tx_desc,
  3790. struct hal_tx_completion_status *ts,
  3791. uint8_t ring_id)
  3792. {
  3793. }
  3794. #endif
  3795. #ifdef WLAN_PEER_JITTER
  3796. /*
  3797. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3798. * @curr_delay: Current delay
  3799. * @prev_Delay: Previous delay
  3800. * @avg_jitter: Average Jitter
  3801. * Return: Newly Computed Average Jitter
  3802. */
  3803. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3804. uint32_t prev_delay,
  3805. uint32_t avg_jitter)
  3806. {
  3807. uint32_t curr_jitter;
  3808. int32_t jitter_diff;
  3809. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3810. if (!avg_jitter)
  3811. return curr_jitter;
  3812. jitter_diff = curr_jitter - avg_jitter;
  3813. if (jitter_diff < 0)
  3814. avg_jitter = avg_jitter -
  3815. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3816. else
  3817. avg_jitter = avg_jitter +
  3818. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3819. return avg_jitter;
  3820. }
  3821. /*
  3822. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3823. * @curr_delay: Current delay
  3824. * @avg_Delay: Average delay
  3825. * Return: Newly Computed Average Delay
  3826. */
  3827. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3828. uint32_t avg_delay)
  3829. {
  3830. int32_t delay_diff;
  3831. if (!avg_delay)
  3832. return curr_delay;
  3833. delay_diff = curr_delay - avg_delay;
  3834. if (delay_diff < 0)
  3835. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3836. DP_AVG_DELAY_WEIGHT_DENOM);
  3837. else
  3838. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3839. DP_AVG_DELAY_WEIGHT_DENOM);
  3840. return avg_delay;
  3841. }
  3842. #ifdef WLAN_CONFIG_TX_DELAY
  3843. /*
  3844. * dp_tx_compute_cur_delay() - get the current delay
  3845. * @soc: soc handle
  3846. * @vdev: vdev structure for data path state
  3847. * @ts: Tx completion status
  3848. * @curr_delay: current delay
  3849. * @tx_desc: tx descriptor
  3850. * Return: void
  3851. */
  3852. static
  3853. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3854. struct dp_vdev *vdev,
  3855. struct hal_tx_completion_status *ts,
  3856. uint32_t *curr_delay,
  3857. struct dp_tx_desc_s *tx_desc)
  3858. {
  3859. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3860. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3861. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3862. curr_delay);
  3863. return status;
  3864. }
  3865. #else
  3866. static
  3867. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3868. struct dp_vdev *vdev,
  3869. struct hal_tx_completion_status *ts,
  3870. uint32_t *curr_delay,
  3871. struct dp_tx_desc_s *tx_desc)
  3872. {
  3873. int64_t current_timestamp, timestamp_hw_enqueue;
  3874. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3875. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3876. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3877. return QDF_STATUS_SUCCESS;
  3878. }
  3879. #endif
  3880. /* dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3881. * @jiiter - per tid per ring jitter stats
  3882. * @ts: Tx completion status
  3883. * @vdev - vdev structure for data path state
  3884. * @tx_desc - tx descriptor
  3885. * Return: void
  3886. */
  3887. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3888. struct hal_tx_completion_status *ts,
  3889. struct dp_vdev *vdev,
  3890. struct dp_tx_desc_s *tx_desc)
  3891. {
  3892. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3893. struct dp_soc *soc = vdev->pdev->soc;
  3894. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3895. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3896. jitter->tx_drop += 1;
  3897. return;
  3898. }
  3899. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3900. tx_desc);
  3901. if (QDF_IS_STATUS_SUCCESS(status)) {
  3902. avg_delay = jitter->tx_avg_delay;
  3903. avg_jitter = jitter->tx_avg_jitter;
  3904. prev_delay = jitter->tx_prev_delay;
  3905. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3906. prev_delay,
  3907. avg_jitter);
  3908. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3909. jitter->tx_avg_delay = avg_delay;
  3910. jitter->tx_avg_jitter = avg_jitter;
  3911. jitter->tx_prev_delay = curr_delay;
  3912. jitter->tx_total_success += 1;
  3913. } else if (status == QDF_STATUS_E_FAILURE) {
  3914. jitter->tx_avg_err += 1;
  3915. }
  3916. }
  3917. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3918. * @txrx_peer: DP peer context
  3919. * @tx_desc: Tx software descriptor
  3920. * @ts: Tx completion status
  3921. * @ring_id: Rx CPU context ID/CPU_ID
  3922. * Return: void
  3923. */
  3924. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3925. struct dp_tx_desc_s *tx_desc,
  3926. struct hal_tx_completion_status *ts,
  3927. uint8_t ring_id)
  3928. {
  3929. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3930. struct dp_soc *soc = pdev->soc;
  3931. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3932. uint8_t tid;
  3933. struct cdp_peer_tid_stats *rx_tid = NULL;
  3934. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3935. return;
  3936. tid = ts->tid;
  3937. jitter_stats = txrx_peer->jitter_stats;
  3938. qdf_assert_always(jitter_stats);
  3939. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3940. /*
  3941. * For non-TID packets use the TID 9
  3942. */
  3943. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3944. tid = CDP_MAX_DATA_TIDS - 1;
  3945. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3946. dp_tx_compute_tid_jitter(rx_tid,
  3947. ts, txrx_peer->vdev, tx_desc);
  3948. }
  3949. #else
  3950. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3951. struct dp_tx_desc_s *tx_desc,
  3952. struct hal_tx_completion_status *ts,
  3953. uint8_t ring_id)
  3954. {
  3955. }
  3956. #endif
  3957. #ifdef HW_TX_DELAY_STATS_ENABLE
  3958. /**
  3959. * dp_update_tx_delay_stats() - update the delay stats
  3960. * @vdev: vdev handle
  3961. * @delay: delay in ms or us based on the flag delay_in_us
  3962. * @tid: tid value
  3963. * @mode: type of tx delay mode
  3964. * @ring id: ring number
  3965. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3966. *
  3967. * Return: none
  3968. */
  3969. static inline
  3970. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3971. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3972. {
  3973. struct cdp_tid_tx_stats *tstats =
  3974. &vdev->stats.tid_tx_stats[ring_id][tid];
  3975. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3976. delay_in_us);
  3977. }
  3978. #else
  3979. static inline
  3980. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3981. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3982. {
  3983. struct cdp_tid_tx_stats *tstats =
  3984. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3985. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3986. delay_in_us);
  3987. }
  3988. #endif
  3989. /**
  3990. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3991. * to pass in correct fields
  3992. *
  3993. * @vdev: pdev handle
  3994. * @tx_desc: tx descriptor
  3995. * @tid: tid value
  3996. * @ring_id: TCL or WBM ring number for transmit path
  3997. * Return: none
  3998. */
  3999. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  4000. uint8_t tid, uint8_t ring_id)
  4001. {
  4002. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  4003. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  4004. uint32_t fwhw_transmit_delay_us;
  4005. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  4006. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  4007. return;
  4008. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  4009. fwhw_transmit_delay_us =
  4010. qdf_ktime_to_us(qdf_ktime_real_get()) -
  4011. qdf_ktime_to_us(tx_desc->timestamp);
  4012. /*
  4013. * Delay between packet enqueued to HW and Tx completion in us
  4014. */
  4015. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  4016. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  4017. ring_id, true);
  4018. /*
  4019. * For MCL, only enqueue to completion delay is required
  4020. * so return if the vdev flag is enabled.
  4021. */
  4022. return;
  4023. }
  4024. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  4025. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  4026. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  4027. timestamp_hw_enqueue);
  4028. /*
  4029. * Delay between packet enqueued to HW and Tx completion in ms
  4030. */
  4031. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  4032. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  4033. false);
  4034. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  4035. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  4036. interframe_delay = (uint32_t)(timestamp_ingress -
  4037. vdev->prev_tx_enq_tstamp);
  4038. /*
  4039. * Delay in software enqueue
  4040. */
  4041. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  4042. CDP_DELAY_STATS_SW_ENQ, ring_id,
  4043. false);
  4044. /*
  4045. * Update interframe delay stats calculated at hardstart receive point.
  4046. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  4047. * interframe delay will not be calculate correctly for 1st frame.
  4048. * On the other side, this will help in avoiding extra per packet check
  4049. * of !vdev->prev_tx_enq_tstamp.
  4050. */
  4051. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  4052. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  4053. false);
  4054. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  4055. }
  4056. #ifdef DISABLE_DP_STATS
  4057. static
  4058. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  4059. struct dp_txrx_peer *txrx_peer)
  4060. {
  4061. }
  4062. #else
  4063. static inline void
  4064. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  4065. {
  4066. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  4067. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  4068. if (subtype != QDF_PROTO_INVALID)
  4069. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  4070. 1);
  4071. }
  4072. #endif
  4073. #ifndef QCA_ENHANCED_STATS_SUPPORT
  4074. #ifdef DP_PEER_EXTENDED_API
  4075. static inline uint8_t
  4076. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4077. {
  4078. return txrx_peer->mpdu_retry_threshold;
  4079. }
  4080. #else
  4081. static inline uint8_t
  4082. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4083. {
  4084. return 0;
  4085. }
  4086. #endif
  4087. /**
  4088. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  4089. *
  4090. * @ts: Tx compltion status
  4091. * @txrx_peer: datapath txrx_peer handle
  4092. *
  4093. * Return: void
  4094. */
  4095. static inline void
  4096. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4097. struct dp_txrx_peer *txrx_peer)
  4098. {
  4099. uint8_t mcs, pkt_type, dst_mcs_idx;
  4100. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  4101. mcs = ts->mcs;
  4102. pkt_type = ts->pkt_type;
  4103. /* do HW to SW pkt type conversion */
  4104. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  4105. hal_2_dp_pkt_type_map[pkt_type]);
  4106. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  4107. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  4108. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4109. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  4110. 1);
  4111. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  4112. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  4113. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  4114. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4115. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  4116. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  4117. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  4118. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  4119. if (ts->first_msdu) {
  4120. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  4121. ts->transmit_cnt > 1);
  4122. if (!retry_threshold)
  4123. return;
  4124. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  4125. qdf_do_div(ts->transmit_cnt,
  4126. retry_threshold),
  4127. ts->transmit_cnt > retry_threshold);
  4128. }
  4129. }
  4130. #else
  4131. static inline void
  4132. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4133. struct dp_txrx_peer *txrx_peer)
  4134. {
  4135. }
  4136. #endif
  4137. /**
  4138. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  4139. * per wbm ring
  4140. *
  4141. * @tx_desc: software descriptor head pointer
  4142. * @ts: Tx completion status
  4143. * @peer: peer handle
  4144. * @ring_id: ring number
  4145. *
  4146. * Return: None
  4147. */
  4148. static inline void
  4149. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  4150. struct hal_tx_completion_status *ts,
  4151. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  4152. {
  4153. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  4154. uint8_t tid = ts->tid;
  4155. uint32_t length;
  4156. struct cdp_tid_tx_stats *tid_stats;
  4157. if (!pdev)
  4158. return;
  4159. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  4160. tid = CDP_MAX_DATA_TIDS - 1;
  4161. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4162. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4163. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4164. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  4165. return;
  4166. }
  4167. length = qdf_nbuf_len(tx_desc->nbuf);
  4168. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4169. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4170. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4171. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4172. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4173. tid_stats->tqm_status_cnt[ts->status]++;
  4174. }
  4175. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4176. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4177. ts->transmit_cnt > 1);
  4178. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4179. 1, ts->transmit_cnt > 2);
  4180. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  4181. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4182. ts->msdu_part_of_amsdu);
  4183. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4184. !ts->msdu_part_of_amsdu);
  4185. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  4186. qdf_system_ticks();
  4187. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  4188. return;
  4189. }
  4190. /*
  4191. * tx_failed is ideally supposed to be updated from HTT ppdu
  4192. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4193. * hw limitation there are no completions for failed cases.
  4194. * Hence updating tx_failed from data path. Please note that
  4195. * if tx_failed is fixed to be from ppdu, then this has to be
  4196. * removed
  4197. */
  4198. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4199. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4200. ts->transmit_cnt > DP_RETRY_COUNT);
  4201. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  4202. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4203. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  4204. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4205. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4206. length);
  4207. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4208. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  4209. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4210. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  4211. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4212. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  4213. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4214. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  4215. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4216. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  4217. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4218. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4219. tx.dropped.fw_rem_queue_disable, 1);
  4220. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4221. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4222. tx.dropped.fw_rem_no_match, 1);
  4223. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4224. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4225. tx.dropped.drop_threshold, 1);
  4226. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4227. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4228. tx.dropped.drop_link_desc_na, 1);
  4229. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4230. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4231. tx.dropped.invalid_drop, 1);
  4232. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4233. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4234. tx.dropped.mcast_vdev_drop, 1);
  4235. } else {
  4236. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  4237. }
  4238. }
  4239. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4240. /**
  4241. * dp_tx_flow_pool_lock() - take flow pool lock
  4242. * @soc: core txrx main context
  4243. * @tx_desc: tx desc
  4244. *
  4245. * Return: None
  4246. */
  4247. static inline
  4248. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4249. struct dp_tx_desc_s *tx_desc)
  4250. {
  4251. struct dp_tx_desc_pool_s *pool;
  4252. uint8_t desc_pool_id;
  4253. desc_pool_id = tx_desc->pool_id;
  4254. pool = &soc->tx_desc[desc_pool_id];
  4255. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4256. }
  4257. /**
  4258. * dp_tx_flow_pool_unlock() - release flow pool lock
  4259. * @soc: core txrx main context
  4260. * @tx_desc: tx desc
  4261. *
  4262. * Return: None
  4263. */
  4264. static inline
  4265. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4266. struct dp_tx_desc_s *tx_desc)
  4267. {
  4268. struct dp_tx_desc_pool_s *pool;
  4269. uint8_t desc_pool_id;
  4270. desc_pool_id = tx_desc->pool_id;
  4271. pool = &soc->tx_desc[desc_pool_id];
  4272. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4273. }
  4274. #else
  4275. static inline
  4276. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4277. {
  4278. }
  4279. static inline
  4280. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4281. {
  4282. }
  4283. #endif
  4284. /**
  4285. * dp_tx_notify_completion() - Notify tx completion for this desc
  4286. * @soc: core txrx main context
  4287. * @vdev: datapath vdev handle
  4288. * @tx_desc: tx desc
  4289. * @netbuf: buffer
  4290. * @status: tx status
  4291. *
  4292. * Return: none
  4293. */
  4294. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4295. struct dp_vdev *vdev,
  4296. struct dp_tx_desc_s *tx_desc,
  4297. qdf_nbuf_t netbuf,
  4298. uint8_t status)
  4299. {
  4300. void *osif_dev;
  4301. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4302. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4303. qdf_assert(tx_desc);
  4304. if (!vdev ||
  4305. !vdev->osif_vdev) {
  4306. return;
  4307. }
  4308. osif_dev = vdev->osif_vdev;
  4309. tx_compl_cbk = vdev->tx_comp;
  4310. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4311. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4312. if (tx_compl_cbk)
  4313. tx_compl_cbk(netbuf, osif_dev, flag);
  4314. }
  4315. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  4316. * @pdev: pdev handle
  4317. * @tid: tid value
  4318. * @txdesc_ts: timestamp from txdesc
  4319. * @ppdu_id: ppdu id
  4320. *
  4321. * Return: none
  4322. */
  4323. #ifdef FEATURE_PERPKT_INFO
  4324. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4325. struct dp_txrx_peer *txrx_peer,
  4326. uint8_t tid,
  4327. uint64_t txdesc_ts,
  4328. uint32_t ppdu_id)
  4329. {
  4330. uint64_t delta_ms;
  4331. struct cdp_tx_sojourn_stats *sojourn_stats;
  4332. struct dp_peer *primary_link_peer = NULL;
  4333. struct dp_soc *link_peer_soc = NULL;
  4334. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4335. return;
  4336. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4337. tid >= CDP_DATA_TID_MAX))
  4338. return;
  4339. if (qdf_unlikely(!pdev->sojourn_buf))
  4340. return;
  4341. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4342. txrx_peer->peer_id,
  4343. DP_MOD_ID_TX_COMP);
  4344. if (qdf_unlikely(!primary_link_peer))
  4345. return;
  4346. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4347. qdf_nbuf_data(pdev->sojourn_buf);
  4348. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4349. sojourn_stats->cookie = (void *)
  4350. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4351. primary_link_peer);
  4352. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4353. txdesc_ts;
  4354. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4355. delta_ms);
  4356. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4357. sojourn_stats->num_msdus[tid] = 1;
  4358. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4359. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4360. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4361. pdev->sojourn_buf, HTT_INVALID_PEER,
  4362. WDI_NO_VAL, pdev->pdev_id);
  4363. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4364. sojourn_stats->num_msdus[tid] = 0;
  4365. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4366. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4367. }
  4368. #else
  4369. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4370. struct dp_txrx_peer *txrx_peer,
  4371. uint8_t tid,
  4372. uint64_t txdesc_ts,
  4373. uint32_t ppdu_id)
  4374. {
  4375. }
  4376. #endif
  4377. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4378. /**
  4379. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  4380. * @soc: dp_soc handle
  4381. * @desc: Tx Descriptor
  4382. * @ts: HAL Tx completion descriptor contents
  4383. *
  4384. * This function is used to send tx completion to packet capture
  4385. */
  4386. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4387. struct dp_tx_desc_s *desc,
  4388. struct hal_tx_completion_status *ts)
  4389. {
  4390. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4391. desc, ts->peer_id,
  4392. WDI_NO_VAL, desc->pdev->pdev_id);
  4393. }
  4394. #endif
  4395. /**
  4396. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  4397. * @soc: DP Soc handle
  4398. * @tx_desc: software Tx descriptor
  4399. * @ts : Tx completion status from HAL/HTT descriptor
  4400. *
  4401. * Return: none
  4402. */
  4403. void
  4404. dp_tx_comp_process_desc(struct dp_soc *soc,
  4405. struct dp_tx_desc_s *desc,
  4406. struct hal_tx_completion_status *ts,
  4407. struct dp_txrx_peer *txrx_peer)
  4408. {
  4409. uint64_t time_latency = 0;
  4410. uint16_t peer_id = DP_INVALID_PEER_ID;
  4411. /*
  4412. * m_copy/tx_capture modes are not supported for
  4413. * scatter gather packets
  4414. */
  4415. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4416. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4417. qdf_ktime_to_ms(desc->timestamp));
  4418. }
  4419. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4420. if (dp_tx_pkt_tracepoints_enabled())
  4421. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4422. desc->msdu_ext_desc ?
  4423. desc->msdu_ext_desc->tso_desc : NULL,
  4424. qdf_ktime_to_ms(desc->timestamp));
  4425. if (!(desc->msdu_ext_desc)) {
  4426. dp_tx_enh_unmap(soc, desc);
  4427. if (txrx_peer)
  4428. peer_id = txrx_peer->peer_id;
  4429. if (QDF_STATUS_SUCCESS ==
  4430. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4431. return;
  4432. }
  4433. if (QDF_STATUS_SUCCESS ==
  4434. dp_get_completion_indication_for_stack(soc,
  4435. desc->pdev,
  4436. txrx_peer, ts,
  4437. desc->nbuf,
  4438. time_latency)) {
  4439. dp_send_completion_to_stack(soc,
  4440. desc->pdev,
  4441. ts->peer_id,
  4442. ts->ppdu_id,
  4443. desc->nbuf);
  4444. return;
  4445. }
  4446. }
  4447. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4448. dp_tx_comp_free_buf(soc, desc, false);
  4449. }
  4450. #ifdef DISABLE_DP_STATS
  4451. /**
  4452. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4453. * @soc: core txrx main context
  4454. * @tx_desc: tx desc
  4455. * @status: tx status
  4456. *
  4457. * Return: none
  4458. */
  4459. static inline
  4460. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4461. struct dp_vdev *vdev,
  4462. struct dp_tx_desc_s *tx_desc,
  4463. uint8_t status)
  4464. {
  4465. }
  4466. #else
  4467. static inline
  4468. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4469. struct dp_vdev *vdev,
  4470. struct dp_tx_desc_s *tx_desc,
  4471. uint8_t status)
  4472. {
  4473. void *osif_dev;
  4474. ol_txrx_stats_rx_fp stats_cbk;
  4475. uint8_t pkt_type;
  4476. qdf_assert(tx_desc);
  4477. if (!vdev ||
  4478. !vdev->osif_vdev ||
  4479. !vdev->stats_cb)
  4480. return;
  4481. osif_dev = vdev->osif_vdev;
  4482. stats_cbk = vdev->stats_cb;
  4483. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4484. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4485. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4486. &pkt_type);
  4487. }
  4488. #endif
  4489. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4490. /* Mask for bit29 ~ bit31 */
  4491. #define DP_TX_TS_BIT29_31_MASK 0xE0000000
  4492. /* Timestamp value (unit us) if bit29 is set */
  4493. #define DP_TX_TS_BIT29_SET_VALUE BIT(29)
  4494. /**
  4495. * dp_tx_adjust_enqueue_buffer_ts() - adjust the enqueue buffer_timestamp
  4496. * @ack_ts: OTA ack timestamp, unit us.
  4497. * @enqueue_ts: TCL enqueue TX data to TQM timestamp, unit us.
  4498. * @base_delta_ts: base timestamp delta for ack_ts and enqueue_ts
  4499. *
  4500. * this function will restore the bit29 ~ bit31 3 bits value for
  4501. * buffer_timestamp in wbm2sw ring entry, currently buffer_timestamp only
  4502. * can support 0x7FFF * 1024 us (29 bits), but if the timestamp is >
  4503. * 0x7FFF * 1024 us, bit29~ bit31 will be lost.
  4504. *
  4505. * Return: the adjusted buffer_timestamp value
  4506. */
  4507. static inline
  4508. uint32_t dp_tx_adjust_enqueue_buffer_ts(uint32_t ack_ts,
  4509. uint32_t enqueue_ts,
  4510. uint32_t base_delta_ts)
  4511. {
  4512. uint32_t ack_buffer_ts;
  4513. uint32_t ack_buffer_ts_bit29_31;
  4514. uint32_t adjusted_enqueue_ts;
  4515. /* corresponding buffer_timestamp value when receive OTA Ack */
  4516. ack_buffer_ts = ack_ts - base_delta_ts;
  4517. ack_buffer_ts_bit29_31 = ack_buffer_ts & DP_TX_TS_BIT29_31_MASK;
  4518. /* restore the bit29 ~ bit31 value */
  4519. adjusted_enqueue_ts = ack_buffer_ts_bit29_31 | enqueue_ts;
  4520. /*
  4521. * if actual enqueue_ts value occupied 29 bits only, this enqueue_ts
  4522. * value + real UL delay overflow 29 bits, then 30th bit (bit-29)
  4523. * should not be marked, otherwise extra 0x20000000 us is added to
  4524. * enqueue_ts.
  4525. */
  4526. if (qdf_unlikely(adjusted_enqueue_ts > ack_buffer_ts))
  4527. adjusted_enqueue_ts -= DP_TX_TS_BIT29_SET_VALUE;
  4528. return adjusted_enqueue_ts;
  4529. }
  4530. QDF_STATUS
  4531. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4532. uint32_t delta_tsf,
  4533. uint32_t *delay_us)
  4534. {
  4535. uint32_t buffer_ts;
  4536. uint32_t delay;
  4537. if (!delay_us)
  4538. return QDF_STATUS_E_INVAL;
  4539. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4540. if (!ts->valid)
  4541. return QDF_STATUS_E_INVAL;
  4542. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4543. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4544. * valid up to 29 bits.
  4545. */
  4546. buffer_ts = ts->buffer_timestamp << 10;
  4547. buffer_ts = dp_tx_adjust_enqueue_buffer_ts(ts->tsf,
  4548. buffer_ts, delta_tsf);
  4549. delay = ts->tsf - buffer_ts - delta_tsf;
  4550. if (qdf_unlikely(delay & 0x80000000)) {
  4551. dp_err_rl("delay = 0x%x (-ve)\n"
  4552. "release_src = %d\n"
  4553. "ppdu_id = 0x%x\n"
  4554. "peer_id = 0x%x\n"
  4555. "tid = 0x%x\n"
  4556. "release_reason = %d\n"
  4557. "tsf = %u (0x%x)\n"
  4558. "buffer_timestamp = %u (0x%x)\n"
  4559. "delta_tsf = %u (0x%x)\n",
  4560. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4561. ts->tid, ts->status, ts->tsf, ts->tsf,
  4562. ts->buffer_timestamp, ts->buffer_timestamp,
  4563. delta_tsf, delta_tsf);
  4564. delay = 0;
  4565. goto end;
  4566. }
  4567. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4568. if (delay > 0x1000000) {
  4569. dp_info_rl("----------------------\n"
  4570. "Tx completion status:\n"
  4571. "----------------------\n"
  4572. "release_src = %d\n"
  4573. "ppdu_id = 0x%x\n"
  4574. "release_reason = %d\n"
  4575. "tsf = %u (0x%x)\n"
  4576. "buffer_timestamp = %u (0x%x)\n"
  4577. "delta_tsf = %u (0x%x)\n",
  4578. ts->release_src, ts->ppdu_id, ts->status,
  4579. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4580. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4581. return QDF_STATUS_E_FAILURE;
  4582. }
  4583. end:
  4584. *delay_us = delay;
  4585. return QDF_STATUS_SUCCESS;
  4586. }
  4587. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4588. uint32_t delta_tsf)
  4589. {
  4590. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4591. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4592. DP_MOD_ID_CDP);
  4593. if (!vdev) {
  4594. dp_err_rl("vdev %d does not exist", vdev_id);
  4595. return;
  4596. }
  4597. vdev->delta_tsf = delta_tsf;
  4598. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4599. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4600. }
  4601. #endif
  4602. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4603. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4604. uint8_t vdev_id, bool enable)
  4605. {
  4606. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4607. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4608. DP_MOD_ID_CDP);
  4609. if (!vdev) {
  4610. dp_err_rl("vdev %d does not exist", vdev_id);
  4611. return QDF_STATUS_E_FAILURE;
  4612. }
  4613. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4614. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4615. return QDF_STATUS_SUCCESS;
  4616. }
  4617. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4618. uint32_t *val)
  4619. {
  4620. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4621. struct dp_vdev *vdev;
  4622. uint32_t delay_accum;
  4623. uint32_t pkts_accum;
  4624. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4625. if (!vdev) {
  4626. dp_err_rl("vdev %d does not exist", vdev_id);
  4627. return QDF_STATUS_E_FAILURE;
  4628. }
  4629. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4630. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4631. return QDF_STATUS_E_FAILURE;
  4632. }
  4633. /* Average uplink delay based on current accumulated values */
  4634. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4635. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4636. *val = delay_accum / pkts_accum;
  4637. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4638. delay_accum, pkts_accum);
  4639. /* Reset accumulated values to 0 */
  4640. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4641. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4642. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4643. return QDF_STATUS_SUCCESS;
  4644. }
  4645. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4646. struct hal_tx_completion_status *ts)
  4647. {
  4648. uint32_t ul_delay;
  4649. if (qdf_unlikely(!vdev)) {
  4650. dp_info_rl("vdev is null or delete in progress");
  4651. return;
  4652. }
  4653. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4654. return;
  4655. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4656. vdev->delta_tsf,
  4657. &ul_delay)))
  4658. return;
  4659. ul_delay /= 1000; /* in unit of ms */
  4660. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4661. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4662. }
  4663. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4664. static inline
  4665. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4666. struct hal_tx_completion_status *ts)
  4667. {
  4668. }
  4669. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4670. /**
  4671. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4672. * @soc: DP soc handle
  4673. * @tx_desc: software descriptor head pointer
  4674. * @ts: Tx completion status
  4675. * @txrx_peer: txrx peer handle
  4676. * @ring_id: ring number
  4677. *
  4678. * Return: none
  4679. */
  4680. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4681. struct dp_tx_desc_s *tx_desc,
  4682. struct hal_tx_completion_status *ts,
  4683. struct dp_txrx_peer *txrx_peer,
  4684. uint8_t ring_id)
  4685. {
  4686. uint32_t length;
  4687. qdf_ether_header_t *eh;
  4688. struct dp_vdev *vdev = NULL;
  4689. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4690. enum qdf_dp_tx_rx_status dp_status;
  4691. if (!nbuf) {
  4692. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4693. goto out;
  4694. }
  4695. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4696. length = dp_tx_get_pkt_len(tx_desc);
  4697. dp_status = dp_tx_hw_to_qdf(ts->status);
  4698. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4699. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4700. QDF_TRACE_DEFAULT_PDEV_ID,
  4701. qdf_nbuf_data_addr(nbuf),
  4702. sizeof(qdf_nbuf_data(nbuf)),
  4703. tx_desc->id, ts->status, dp_status));
  4704. dp_tx_comp_debug("-------------------- \n"
  4705. "Tx Completion Stats: \n"
  4706. "-------------------- \n"
  4707. "ack_frame_rssi = %d \n"
  4708. "first_msdu = %d \n"
  4709. "last_msdu = %d \n"
  4710. "msdu_part_of_amsdu = %d \n"
  4711. "rate_stats valid = %d \n"
  4712. "bw = %d \n"
  4713. "pkt_type = %d \n"
  4714. "stbc = %d \n"
  4715. "ldpc = %d \n"
  4716. "sgi = %d \n"
  4717. "mcs = %d \n"
  4718. "ofdma = %d \n"
  4719. "tones_in_ru = %d \n"
  4720. "tsf = %d \n"
  4721. "ppdu_id = %d \n"
  4722. "transmit_cnt = %d \n"
  4723. "tid = %d \n"
  4724. "peer_id = %d\n"
  4725. "tx_status = %d\n",
  4726. ts->ack_frame_rssi, ts->first_msdu,
  4727. ts->last_msdu, ts->msdu_part_of_amsdu,
  4728. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4729. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4730. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4731. ts->transmit_cnt, ts->tid, ts->peer_id,
  4732. ts->status);
  4733. /* Update SoC level stats */
  4734. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4735. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4736. if (!txrx_peer) {
  4737. dp_info_rl("peer is null or deletion in progress");
  4738. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4739. goto out;
  4740. }
  4741. vdev = txrx_peer->vdev;
  4742. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4743. dp_tx_update_uplink_delay(soc, vdev, ts);
  4744. /* check tx complete notification */
  4745. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4746. dp_tx_notify_completion(soc, vdev, tx_desc,
  4747. nbuf, ts->status);
  4748. /* Update per-packet stats for mesh mode */
  4749. if (qdf_unlikely(vdev->mesh_vdev) &&
  4750. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4751. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4752. /* Update peer level stats */
  4753. if (qdf_unlikely(txrx_peer->bss_peer &&
  4754. vdev->opmode == wlan_op_mode_ap)) {
  4755. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4756. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4757. length);
  4758. if (txrx_peer->vdev->tx_encap_type ==
  4759. htt_cmn_pkt_type_ethernet &&
  4760. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4761. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4762. tx.bcast, 1,
  4763. length);
  4764. }
  4765. }
  4766. } else {
  4767. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4768. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4769. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4770. 1, length);
  4771. if (qdf_unlikely(txrx_peer->in_twt)) {
  4772. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4773. tx.tx_success_twt,
  4774. 1, length);
  4775. }
  4776. }
  4777. }
  4778. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4779. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4780. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4781. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4782. ts, ts->tid);
  4783. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4784. #ifdef QCA_SUPPORT_RDK_STATS
  4785. if (soc->peerstats_enabled)
  4786. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4787. qdf_ktime_to_ms(tx_desc->timestamp),
  4788. ts->ppdu_id);
  4789. #endif
  4790. out:
  4791. return;
  4792. }
  4793. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4794. defined(QCA_ENHANCED_STATS_SUPPORT)
  4795. /*
  4796. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4797. * @txrx_peer: Datapath txrx_peer handle
  4798. * @length: Length of the packet
  4799. * @tx_status: Tx status from TQM/FW
  4800. * @update: enhanced flag value present in dp_pdev
  4801. *
  4802. * Return: none
  4803. */
  4804. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4805. uint32_t length, uint8_t tx_status,
  4806. bool update)
  4807. {
  4808. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4809. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4810. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4811. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4812. }
  4813. }
  4814. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4815. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4816. uint32_t length, uint8_t tx_status,
  4817. bool update)
  4818. {
  4819. if (!txrx_peer->hw_txrx_stats_en) {
  4820. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4821. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4822. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4823. }
  4824. }
  4825. #else
  4826. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4827. uint32_t length, uint8_t tx_status,
  4828. bool update)
  4829. {
  4830. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4831. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4832. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4833. }
  4834. #endif
  4835. /*
  4836. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4837. * @nbuf: skb buffer
  4838. *
  4839. * Return: none
  4840. */
  4841. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4842. static inline
  4843. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4844. {
  4845. qdf_nbuf_t nbuf = NULL;
  4846. if (next)
  4847. nbuf = next->nbuf;
  4848. if (nbuf)
  4849. qdf_prefetch(nbuf);
  4850. }
  4851. #else
  4852. static inline
  4853. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4854. {
  4855. }
  4856. #endif
  4857. /**
  4858. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4859. * @soc: core txrx main context
  4860. * @desc: software descriptor
  4861. *
  4862. * Return: true when packet is reinjected
  4863. */
  4864. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4865. defined(WLAN_MCAST_MLO)
  4866. static inline bool
  4867. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4868. {
  4869. struct dp_vdev *vdev = NULL;
  4870. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4871. if (!soc->arch_ops.dp_tx_mcast_handler ||
  4872. !soc->arch_ops.dp_tx_is_mcast_primary)
  4873. return false;
  4874. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4875. DP_MOD_ID_REINJECT);
  4876. if (qdf_unlikely(!vdev)) {
  4877. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4878. desc->id);
  4879. return false;
  4880. }
  4881. if (!(soc->arch_ops.dp_tx_is_mcast_primary(soc, vdev))) {
  4882. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4883. return false;
  4884. }
  4885. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4886. qdf_nbuf_len(desc->nbuf));
  4887. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4888. dp_tx_desc_release(desc, desc->pool_id);
  4889. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4890. return true;
  4891. }
  4892. return false;
  4893. }
  4894. #else
  4895. static inline bool
  4896. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4897. {
  4898. return false;
  4899. }
  4900. #endif
  4901. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  4902. static inline void
  4903. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4904. {
  4905. qdf_nbuf_queue_head_init(nbuf_queue_head);
  4906. }
  4907. static inline void
  4908. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4909. struct dp_tx_desc_s *desc)
  4910. {
  4911. qdf_nbuf_t nbuf = NULL;
  4912. nbuf = desc->nbuf;
  4913. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_FAST))
  4914. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4915. else
  4916. qdf_nbuf_free(nbuf);
  4917. }
  4918. static inline void
  4919. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4920. {
  4921. qdf_nbuf_dev_kfree_list(nbuf_queue_head);
  4922. }
  4923. #else
  4924. static inline void
  4925. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4926. {
  4927. }
  4928. static inline void
  4929. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4930. struct dp_tx_desc_s *desc)
  4931. {
  4932. qdf_nbuf_free(desc->nbuf);
  4933. }
  4934. static inline void
  4935. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4936. {
  4937. }
  4938. #endif
  4939. /**
  4940. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4941. * @soc: core txrx main context
  4942. * @comp_head: software descriptor head pointer
  4943. * @ring_id: ring number
  4944. *
  4945. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4946. * and release the software descriptors after processing is complete
  4947. *
  4948. * Return: none
  4949. */
  4950. void
  4951. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4952. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4953. {
  4954. struct dp_tx_desc_s *desc;
  4955. struct dp_tx_desc_s *next;
  4956. struct hal_tx_completion_status ts;
  4957. struct dp_txrx_peer *txrx_peer = NULL;
  4958. uint16_t peer_id = DP_INVALID_PEER;
  4959. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4960. qdf_nbuf_queue_head_t h;
  4961. desc = comp_head;
  4962. dp_tx_nbuf_queue_head_init(&h);
  4963. while (desc) {
  4964. next = desc->next;
  4965. dp_tx_prefetch_next_nbuf_data(next);
  4966. if (peer_id != desc->peer_id) {
  4967. if (txrx_peer)
  4968. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4969. DP_MOD_ID_TX_COMP);
  4970. peer_id = desc->peer_id;
  4971. txrx_peer =
  4972. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4973. &txrx_ref_handle,
  4974. DP_MOD_ID_TX_COMP);
  4975. }
  4976. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4977. desc = next;
  4978. continue;
  4979. }
  4980. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4981. if (qdf_likely(txrx_peer))
  4982. dp_tx_update_peer_basic_stats(txrx_peer,
  4983. desc->length,
  4984. desc->tx_status,
  4985. false);
  4986. dp_tx_nbuf_dev_queue_free(&h, desc);
  4987. dp_ppeds_tx_desc_free(soc, desc);
  4988. desc = next;
  4989. continue;
  4990. }
  4991. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4992. struct dp_pdev *pdev = desc->pdev;
  4993. if (qdf_likely(txrx_peer))
  4994. dp_tx_update_peer_basic_stats(txrx_peer,
  4995. desc->length,
  4996. desc->tx_status,
  4997. false);
  4998. qdf_assert(pdev);
  4999. dp_tx_outstanding_dec(pdev);
  5000. /*
  5001. * Calling a QDF WRAPPER here is creating significant
  5002. * performance impact so avoided the wrapper call here
  5003. */
  5004. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  5005. desc->id, DP_TX_COMP_UNMAP);
  5006. dp_tx_nbuf_unmap(soc, desc);
  5007. dp_tx_nbuf_dev_queue_free(&h, desc);
  5008. dp_tx_desc_free(soc, desc, desc->pool_id);
  5009. desc = next;
  5010. continue;
  5011. }
  5012. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  5013. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  5014. ring_id);
  5015. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  5016. dp_tx_desc_release(desc, desc->pool_id);
  5017. desc = next;
  5018. }
  5019. dp_tx_nbuf_dev_kfree_list(&h);
  5020. if (txrx_peer)
  5021. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  5022. }
  5023. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  5024. static inline
  5025. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  5026. int max_reap_limit)
  5027. {
  5028. bool limit_hit = false;
  5029. limit_hit =
  5030. (num_reaped >= max_reap_limit) ? true : false;
  5031. if (limit_hit)
  5032. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  5033. return limit_hit;
  5034. }
  5035. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  5036. {
  5037. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  5038. }
  5039. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5040. {
  5041. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  5042. return cfg->tx_comp_loop_pkt_limit;
  5043. }
  5044. #else
  5045. static inline
  5046. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  5047. int max_reap_limit)
  5048. {
  5049. return false;
  5050. }
  5051. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  5052. {
  5053. return false;
  5054. }
  5055. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5056. {
  5057. return 0;
  5058. }
  5059. #endif
  5060. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  5061. static inline int
  5062. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5063. int *max_reap_limit)
  5064. {
  5065. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  5066. max_reap_limit);
  5067. }
  5068. #else
  5069. static inline int
  5070. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5071. int *max_reap_limit)
  5072. {
  5073. return 0;
  5074. }
  5075. #endif
  5076. #ifdef DP_TX_TRACKING
  5077. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  5078. {
  5079. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  5080. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  5081. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  5082. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  5083. }
  5084. }
  5085. #endif
  5086. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  5087. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  5088. uint32_t quota)
  5089. {
  5090. void *tx_comp_hal_desc;
  5091. void *last_prefetched_hw_desc = NULL;
  5092. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  5093. hal_soc_handle_t hal_soc;
  5094. uint8_t buffer_src;
  5095. struct dp_tx_desc_s *tx_desc = NULL;
  5096. struct dp_tx_desc_s *head_desc = NULL;
  5097. struct dp_tx_desc_s *tail_desc = NULL;
  5098. uint32_t num_processed = 0;
  5099. uint32_t count;
  5100. uint32_t num_avail_for_reap = 0;
  5101. bool force_break = false;
  5102. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  5103. int max_reap_limit, ring_near_full;
  5104. uint32_t num_entries;
  5105. DP_HIST_INIT();
  5106. num_entries = hal_srng_get_num_entries(soc->hal_soc, hal_ring_hdl);
  5107. more_data:
  5108. hal_soc = soc->hal_soc;
  5109. /* Re-initialize local variables to be re-used */
  5110. head_desc = NULL;
  5111. tail_desc = NULL;
  5112. count = 0;
  5113. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  5114. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  5115. &max_reap_limit);
  5116. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  5117. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  5118. return 0;
  5119. }
  5120. if (!num_avail_for_reap)
  5121. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
  5122. hal_ring_hdl, 0);
  5123. if (num_avail_for_reap >= quota)
  5124. num_avail_for_reap = quota;
  5125. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  5126. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  5127. hal_ring_hdl,
  5128. num_avail_for_reap);
  5129. /* Find head descriptor from completion ring */
  5130. while (qdf_likely(num_avail_for_reap--)) {
  5131. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  5132. if (qdf_unlikely(!tx_comp_hal_desc))
  5133. break;
  5134. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  5135. tx_comp_hal_desc);
  5136. /* If this buffer was not released by TQM or FW, then it is not
  5137. * Tx completion indication, assert */
  5138. if (qdf_unlikely(buffer_src !=
  5139. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  5140. (qdf_unlikely(buffer_src !=
  5141. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  5142. uint8_t wbm_internal_error;
  5143. dp_err_rl(
  5144. "Tx comp release_src != TQM | FW but from %d",
  5145. buffer_src);
  5146. hal_dump_comp_desc(tx_comp_hal_desc);
  5147. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  5148. /* When WBM sees NULL buffer_addr_info in any of
  5149. * ingress rings it sends an error indication,
  5150. * with wbm_internal_error=1, to a specific ring.
  5151. * The WBM2SW ring used to indicate these errors is
  5152. * fixed in HW, and that ring is being used as Tx
  5153. * completion ring. These errors are not related to
  5154. * Tx completions, and should just be ignored
  5155. */
  5156. wbm_internal_error = hal_get_wbm_internal_error(
  5157. hal_soc,
  5158. tx_comp_hal_desc);
  5159. if (wbm_internal_error) {
  5160. dp_err_rl("Tx comp wbm_internal_error!!");
  5161. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  5162. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  5163. buffer_src)
  5164. dp_handle_wbm_internal_error(
  5165. soc,
  5166. tx_comp_hal_desc,
  5167. hal_tx_comp_get_buffer_type(
  5168. tx_comp_hal_desc));
  5169. } else {
  5170. dp_err_rl("Tx comp wbm_internal_error false");
  5171. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  5172. }
  5173. continue;
  5174. }
  5175. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  5176. tx_comp_hal_desc,
  5177. &tx_desc);
  5178. if (qdf_unlikely(!tx_desc)) {
  5179. dp_err("unable to retrieve tx_desc!");
  5180. hal_dump_comp_desc(tx_comp_hal_desc);
  5181. DP_STATS_INC(soc, tx.invalid_tx_comp_desc, 1);
  5182. QDF_BUG(0);
  5183. continue;
  5184. }
  5185. tx_desc->buffer_src = buffer_src;
  5186. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  5187. goto add_to_pool2;
  5188. /*
  5189. * If the release source is FW, process the HTT status
  5190. */
  5191. if (qdf_unlikely(buffer_src ==
  5192. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  5193. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  5194. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  5195. htt_tx_status);
  5196. /* Collect hw completion contents */
  5197. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5198. &tx_desc->comp, 1);
  5199. soc->arch_ops.dp_tx_process_htt_completion(
  5200. soc,
  5201. tx_desc,
  5202. htt_tx_status,
  5203. ring_id);
  5204. } else {
  5205. tx_desc->tx_status =
  5206. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  5207. tx_desc->buffer_src = buffer_src;
  5208. /*
  5209. * If the fast completion mode is enabled extended
  5210. * metadata from descriptor is not copied
  5211. */
  5212. if (qdf_likely(tx_desc->flags &
  5213. DP_TX_DESC_FLAG_SIMPLE))
  5214. goto add_to_pool;
  5215. /*
  5216. * If the descriptor is already freed in vdev_detach,
  5217. * continue to next descriptor
  5218. */
  5219. if (qdf_unlikely
  5220. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5221. !tx_desc->flags)) {
  5222. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5223. tx_desc->id);
  5224. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5225. dp_tx_desc_check_corruption(tx_desc);
  5226. continue;
  5227. }
  5228. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5229. dp_tx_comp_info_rl("pdev in down state %d",
  5230. tx_desc->id);
  5231. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5232. dp_tx_comp_free_buf(soc, tx_desc, false);
  5233. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5234. goto next_desc;
  5235. }
  5236. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5237. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5238. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5239. tx_desc->flags, tx_desc->id);
  5240. qdf_assert_always(0);
  5241. }
  5242. /* Collect hw completion contents */
  5243. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5244. &tx_desc->comp, 1);
  5245. add_to_pool:
  5246. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5247. add_to_pool2:
  5248. /* First ring descriptor on the cycle */
  5249. if (!head_desc) {
  5250. head_desc = tx_desc;
  5251. tail_desc = tx_desc;
  5252. }
  5253. tail_desc->next = tx_desc;
  5254. tx_desc->next = NULL;
  5255. tail_desc = tx_desc;
  5256. }
  5257. next_desc:
  5258. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5259. /*
  5260. * Processed packet count is more than given quota
  5261. * stop to processing
  5262. */
  5263. count++;
  5264. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5265. num_avail_for_reap,
  5266. hal_ring_hdl,
  5267. &last_prefetched_hw_desc,
  5268. &last_prefetched_sw_desc);
  5269. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5270. break;
  5271. }
  5272. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5273. /* Process the reaped descriptors */
  5274. if (head_desc)
  5275. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5276. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5277. /*
  5278. * If we are processing in near-full condition, there are 3 scenario
  5279. * 1) Ring entries has reached critical state
  5280. * 2) Ring entries are still near high threshold
  5281. * 3) Ring entries are below the safe level
  5282. *
  5283. * One more loop will move the state to normal processing and yield
  5284. */
  5285. if (ring_near_full)
  5286. goto more_data;
  5287. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5288. if (num_processed >= quota)
  5289. force_break = true;
  5290. if (!force_break &&
  5291. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5292. hal_ring_hdl)) {
  5293. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5294. if (!hif_exec_should_yield(soc->hif_handle,
  5295. int_ctx->dp_intr_id))
  5296. goto more_data;
  5297. num_avail_for_reap =
  5298. hal_srng_dst_num_valid_locked(soc->hal_soc,
  5299. hal_ring_hdl,
  5300. true);
  5301. if (qdf_unlikely(num_entries &&
  5302. (num_avail_for_reap >=
  5303. num_entries >> 1))) {
  5304. DP_STATS_INC(soc, tx.near_full, 1);
  5305. goto more_data;
  5306. }
  5307. }
  5308. }
  5309. DP_TX_HIST_STATS_PER_PDEV();
  5310. return num_processed;
  5311. }
  5312. #ifdef FEATURE_WLAN_TDLS
  5313. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5314. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5315. {
  5316. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5317. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5318. DP_MOD_ID_TDLS);
  5319. if (!vdev) {
  5320. dp_err("vdev handle for id %d is NULL", vdev_id);
  5321. return NULL;
  5322. }
  5323. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5324. vdev->is_tdls_frame = true;
  5325. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5326. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5327. }
  5328. #endif
  5329. /**
  5330. * dp_tx_vdev_attach() - attach vdev to dp tx
  5331. * @vdev: virtual device instance
  5332. *
  5333. * Return: QDF_STATUS_SUCCESS: success
  5334. * QDF_STATUS_E_RESOURCES: Error return
  5335. */
  5336. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5337. {
  5338. int pdev_id;
  5339. /*
  5340. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5341. */
  5342. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5343. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5344. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5345. vdev->vdev_id);
  5346. pdev_id =
  5347. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5348. vdev->pdev->pdev_id);
  5349. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5350. /*
  5351. * Set HTT Extension Valid bit to 0 by default
  5352. */
  5353. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5354. dp_tx_vdev_update_search_flags(vdev);
  5355. return QDF_STATUS_SUCCESS;
  5356. }
  5357. #ifndef FEATURE_WDS
  5358. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5359. {
  5360. return false;
  5361. }
  5362. #endif
  5363. /**
  5364. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  5365. * @vdev: virtual device instance
  5366. *
  5367. * Return: void
  5368. *
  5369. */
  5370. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5371. {
  5372. struct dp_soc *soc = vdev->pdev->soc;
  5373. /*
  5374. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5375. * for TDLS link
  5376. *
  5377. * Enable AddrY (SA based search) only for non-WDS STA and
  5378. * ProxySTA VAP (in HKv1) modes.
  5379. *
  5380. * In all other VAP modes, only DA based search should be
  5381. * enabled
  5382. */
  5383. if (vdev->opmode == wlan_op_mode_sta &&
  5384. vdev->tdls_link_connected)
  5385. vdev->hal_desc_addr_search_flags =
  5386. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5387. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5388. !dp_tx_da_search_override(vdev))
  5389. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5390. else
  5391. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5392. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5393. vdev->search_type = soc->sta_mode_search_policy;
  5394. else
  5395. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5396. }
  5397. static inline bool
  5398. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5399. struct dp_vdev *vdev,
  5400. struct dp_tx_desc_s *tx_desc)
  5401. {
  5402. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5403. return false;
  5404. /*
  5405. * if vdev is given, then only check whether desc
  5406. * vdev match. if vdev is NULL, then check whether
  5407. * desc pdev match.
  5408. */
  5409. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5410. (tx_desc->pdev == pdev);
  5411. }
  5412. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5413. /**
  5414. * dp_tx_desc_flush() - release resources associated
  5415. * to TX Desc
  5416. *
  5417. * @dp_pdev: Handle to DP pdev structure
  5418. * @vdev: virtual device instance
  5419. * NULL: no specific Vdev is required and check all allcated TX desc
  5420. * on this pdev.
  5421. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  5422. *
  5423. * @force_free:
  5424. * true: flush the TX desc.
  5425. * false: only reset the Vdev in each allocated TX desc
  5426. * that associated to current Vdev.
  5427. *
  5428. * This function will go through the TX desc pool to flush
  5429. * the outstanding TX data or reset Vdev to NULL in associated TX
  5430. * Desc.
  5431. */
  5432. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5433. bool force_free)
  5434. {
  5435. uint8_t i;
  5436. uint32_t j;
  5437. uint32_t num_desc, page_id, offset;
  5438. uint16_t num_desc_per_page;
  5439. struct dp_soc *soc = pdev->soc;
  5440. struct dp_tx_desc_s *tx_desc = NULL;
  5441. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5442. if (!vdev && !force_free) {
  5443. dp_err("Reset TX desc vdev, Vdev param is required!");
  5444. return;
  5445. }
  5446. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5447. tx_desc_pool = &soc->tx_desc[i];
  5448. if (!(tx_desc_pool->pool_size) ||
  5449. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5450. !(tx_desc_pool->desc_pages.cacheable_pages))
  5451. continue;
  5452. /*
  5453. * Add flow pool lock protection in case pool is freed
  5454. * due to all tx_desc is recycled when handle TX completion.
  5455. * this is not necessary when do force flush as:
  5456. * a. double lock will happen if dp_tx_desc_release is
  5457. * also trying to acquire it.
  5458. * b. dp interrupt has been disabled before do force TX desc
  5459. * flush in dp_pdev_deinit().
  5460. */
  5461. if (!force_free)
  5462. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5463. num_desc = tx_desc_pool->pool_size;
  5464. num_desc_per_page =
  5465. tx_desc_pool->desc_pages.num_element_per_page;
  5466. for (j = 0; j < num_desc; j++) {
  5467. page_id = j / num_desc_per_page;
  5468. offset = j % num_desc_per_page;
  5469. if (qdf_unlikely(!(tx_desc_pool->
  5470. desc_pages.cacheable_pages)))
  5471. break;
  5472. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5473. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5474. /*
  5475. * Free TX desc if force free is
  5476. * required, otherwise only reset vdev
  5477. * in this TX desc.
  5478. */
  5479. if (force_free) {
  5480. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5481. dp_tx_comp_free_buf(soc, tx_desc,
  5482. false);
  5483. dp_tx_desc_release(tx_desc, i);
  5484. } else {
  5485. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5486. }
  5487. }
  5488. }
  5489. if (!force_free)
  5490. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5491. }
  5492. }
  5493. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5494. /**
  5495. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5496. *
  5497. * @soc: Handle to DP soc structure
  5498. * @tx_desc: pointer of one TX desc
  5499. * @desc_pool_id: TX Desc pool id
  5500. */
  5501. static inline void
  5502. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5503. uint8_t desc_pool_id)
  5504. {
  5505. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5506. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5507. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5508. }
  5509. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5510. bool force_free)
  5511. {
  5512. uint8_t i, num_pool;
  5513. uint32_t j;
  5514. uint32_t num_desc, page_id, offset;
  5515. uint16_t num_desc_per_page;
  5516. struct dp_soc *soc = pdev->soc;
  5517. struct dp_tx_desc_s *tx_desc = NULL;
  5518. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5519. if (!vdev && !force_free) {
  5520. dp_err("Reset TX desc vdev, Vdev param is required!");
  5521. return;
  5522. }
  5523. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5524. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5525. for (i = 0; i < num_pool; i++) {
  5526. tx_desc_pool = &soc->tx_desc[i];
  5527. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5528. continue;
  5529. num_desc_per_page =
  5530. tx_desc_pool->desc_pages.num_element_per_page;
  5531. for (j = 0; j < num_desc; j++) {
  5532. page_id = j / num_desc_per_page;
  5533. offset = j % num_desc_per_page;
  5534. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5535. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5536. if (force_free) {
  5537. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5538. dp_tx_comp_free_buf(soc, tx_desc,
  5539. false);
  5540. dp_tx_desc_release(tx_desc, i);
  5541. } else {
  5542. dp_tx_desc_reset_vdev(soc, tx_desc,
  5543. i);
  5544. }
  5545. }
  5546. }
  5547. }
  5548. }
  5549. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5550. /**
  5551. * dp_tx_vdev_detach() - detach vdev from dp tx
  5552. * @vdev: virtual device instance
  5553. *
  5554. * Return: QDF_STATUS_SUCCESS: success
  5555. * QDF_STATUS_E_RESOURCES: Error return
  5556. */
  5557. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5558. {
  5559. struct dp_pdev *pdev = vdev->pdev;
  5560. /* Reset TX desc associated to this Vdev as NULL */
  5561. dp_tx_desc_flush(pdev, vdev, false);
  5562. return QDF_STATUS_SUCCESS;
  5563. }
  5564. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5565. /* Pools will be allocated dynamically */
  5566. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5567. int num_desc)
  5568. {
  5569. uint8_t i;
  5570. for (i = 0; i < num_pool; i++) {
  5571. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5572. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5573. }
  5574. return QDF_STATUS_SUCCESS;
  5575. }
  5576. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5577. uint32_t num_desc)
  5578. {
  5579. return QDF_STATUS_SUCCESS;
  5580. }
  5581. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5582. {
  5583. }
  5584. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5585. {
  5586. uint8_t i;
  5587. for (i = 0; i < num_pool; i++)
  5588. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5589. }
  5590. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5591. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5592. uint32_t num_desc)
  5593. {
  5594. uint8_t i, count;
  5595. /* Allocate software Tx descriptor pools */
  5596. for (i = 0; i < num_pool; i++) {
  5597. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5598. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5599. FL("Tx Desc Pool alloc %d failed %pK"),
  5600. i, soc);
  5601. goto fail;
  5602. }
  5603. }
  5604. return QDF_STATUS_SUCCESS;
  5605. fail:
  5606. for (count = 0; count < i; count++)
  5607. dp_tx_desc_pool_free(soc, count);
  5608. return QDF_STATUS_E_NOMEM;
  5609. }
  5610. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5611. uint32_t num_desc)
  5612. {
  5613. uint8_t i;
  5614. for (i = 0; i < num_pool; i++) {
  5615. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5616. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5617. FL("Tx Desc Pool init %d failed %pK"),
  5618. i, soc);
  5619. return QDF_STATUS_E_NOMEM;
  5620. }
  5621. }
  5622. return QDF_STATUS_SUCCESS;
  5623. }
  5624. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5625. {
  5626. uint8_t i;
  5627. for (i = 0; i < num_pool; i++)
  5628. dp_tx_desc_pool_deinit(soc, i);
  5629. }
  5630. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5631. {
  5632. uint8_t i;
  5633. for (i = 0; i < num_pool; i++)
  5634. dp_tx_desc_pool_free(soc, i);
  5635. }
  5636. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5637. /**
  5638. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5639. * @soc: core txrx main context
  5640. * @num_pool: number of pools
  5641. *
  5642. */
  5643. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5644. {
  5645. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5646. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5647. }
  5648. /**
  5649. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5650. * @soc: core txrx main context
  5651. * @num_pool: number of pools
  5652. *
  5653. */
  5654. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5655. {
  5656. dp_tx_tso_desc_pool_free(soc, num_pool);
  5657. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5658. }
  5659. /**
  5660. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5661. * @soc: core txrx main context
  5662. *
  5663. * This function frees all tx related descriptors as below
  5664. * 1. Regular TX descriptors (static pools)
  5665. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5666. * 3. TSO descriptors
  5667. *
  5668. */
  5669. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5670. {
  5671. uint8_t num_pool;
  5672. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5673. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5674. dp_tx_ext_desc_pool_free(soc, num_pool);
  5675. dp_tx_delete_static_pools(soc, num_pool);
  5676. }
  5677. /**
  5678. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5679. * @soc: core txrx main context
  5680. *
  5681. * This function de-initializes all tx related descriptors as below
  5682. * 1. Regular TX descriptors (static pools)
  5683. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5684. * 3. TSO descriptors
  5685. *
  5686. */
  5687. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5688. {
  5689. uint8_t num_pool;
  5690. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5691. dp_tx_flow_control_deinit(soc);
  5692. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5693. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5694. dp_tx_deinit_static_pools(soc, num_pool);
  5695. }
  5696. /**
  5697. * dp_tso_attach() - TSO attach handler
  5698. * @txrx_soc: Opaque Dp handle
  5699. *
  5700. * Reserve TSO descriptor buffers
  5701. *
  5702. * Return: QDF_STATUS_E_FAILURE on failure or
  5703. * QDF_STATUS_SUCCESS on success
  5704. */
  5705. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5706. uint8_t num_pool,
  5707. uint32_t num_desc)
  5708. {
  5709. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5710. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5711. return QDF_STATUS_E_FAILURE;
  5712. }
  5713. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5714. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5715. num_pool, soc);
  5716. return QDF_STATUS_E_FAILURE;
  5717. }
  5718. return QDF_STATUS_SUCCESS;
  5719. }
  5720. /**
  5721. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5722. * @soc: DP soc handle
  5723. * @num_pool: Number of pools
  5724. * @num_desc: Number of descriptors
  5725. *
  5726. * Initialize TSO descriptor pools
  5727. *
  5728. * Return: QDF_STATUS_E_FAILURE on failure or
  5729. * QDF_STATUS_SUCCESS on success
  5730. */
  5731. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5732. uint8_t num_pool,
  5733. uint32_t num_desc)
  5734. {
  5735. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5736. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5737. return QDF_STATUS_E_FAILURE;
  5738. }
  5739. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5740. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5741. num_pool, soc);
  5742. return QDF_STATUS_E_FAILURE;
  5743. }
  5744. return QDF_STATUS_SUCCESS;
  5745. }
  5746. /**
  5747. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5748. * @soc: core txrx main context
  5749. *
  5750. * This function allocates memory for following descriptor pools
  5751. * 1. regular sw tx descriptor pools (static pools)
  5752. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5753. * 3. TSO descriptor pools
  5754. *
  5755. * Return: QDF_STATUS_SUCCESS: success
  5756. * QDF_STATUS_E_RESOURCES: Error return
  5757. */
  5758. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5759. {
  5760. uint8_t num_pool;
  5761. uint32_t num_desc;
  5762. uint32_t num_ext_desc;
  5763. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5764. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5765. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5766. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5767. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5768. __func__, num_pool, num_desc);
  5769. if ((num_pool > MAX_TXDESC_POOLS) ||
  5770. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5771. goto fail1;
  5772. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5773. goto fail1;
  5774. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5775. goto fail2;
  5776. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5777. return QDF_STATUS_SUCCESS;
  5778. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5779. goto fail3;
  5780. return QDF_STATUS_SUCCESS;
  5781. fail3:
  5782. dp_tx_ext_desc_pool_free(soc, num_pool);
  5783. fail2:
  5784. dp_tx_delete_static_pools(soc, num_pool);
  5785. fail1:
  5786. return QDF_STATUS_E_RESOURCES;
  5787. }
  5788. /**
  5789. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5790. * @soc: core txrx main context
  5791. *
  5792. * This function initializes the following TX descriptor pools
  5793. * 1. regular sw tx descriptor pools (static pools)
  5794. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5795. * 3. TSO descriptor pools
  5796. *
  5797. * Return: QDF_STATUS_SUCCESS: success
  5798. * QDF_STATUS_E_RESOURCES: Error return
  5799. */
  5800. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5801. {
  5802. uint8_t num_pool;
  5803. uint32_t num_desc;
  5804. uint32_t num_ext_desc;
  5805. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5806. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5807. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5808. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5809. goto fail1;
  5810. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5811. goto fail2;
  5812. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5813. return QDF_STATUS_SUCCESS;
  5814. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5815. goto fail3;
  5816. dp_tx_flow_control_init(soc);
  5817. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5818. return QDF_STATUS_SUCCESS;
  5819. fail3:
  5820. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5821. fail2:
  5822. dp_tx_deinit_static_pools(soc, num_pool);
  5823. fail1:
  5824. return QDF_STATUS_E_RESOURCES;
  5825. }
  5826. /**
  5827. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5828. * @txrx_soc: dp soc handle
  5829. *
  5830. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5831. * QDF_STATUS_E_FAILURE
  5832. */
  5833. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5834. {
  5835. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5836. uint8_t num_pool;
  5837. uint32_t num_desc;
  5838. uint32_t num_ext_desc;
  5839. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5840. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5841. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5842. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5843. return QDF_STATUS_E_FAILURE;
  5844. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5845. return QDF_STATUS_E_FAILURE;
  5846. return QDF_STATUS_SUCCESS;
  5847. }
  5848. /**
  5849. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5850. * @txrx_soc: dp soc handle
  5851. *
  5852. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5853. */
  5854. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5855. {
  5856. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5857. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5858. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5859. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5860. return QDF_STATUS_SUCCESS;
  5861. }
  5862. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5863. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5864. enum qdf_pkt_timestamp_index index, uint64_t time,
  5865. qdf_nbuf_t nbuf)
  5866. {
  5867. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5868. uint64_t tsf_time;
  5869. if (vdev->get_tsf_time) {
  5870. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5871. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5872. }
  5873. }
  5874. }
  5875. void dp_pkt_get_timestamp(uint64_t *time)
  5876. {
  5877. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5878. *time = qdf_get_log_timestamp();
  5879. }
  5880. #endif