sde_kms.c 89 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/dma-buf.h>
  25. #include <drm/drm_atomic_uapi.h>
  26. #include <drm/drm_probe_helper.h>
  27. #include "msm_drv.h"
  28. #include "msm_mmu.h"
  29. #include "msm_gem.h"
  30. #include "dsi_display.h"
  31. #include "dsi_drm.h"
  32. #include "sde_wb.h"
  33. #include "dp_display.h"
  34. #include "dp_drm.h"
  35. #include "dp_mst_drm.h"
  36. #include "sde_kms.h"
  37. #include "sde_core_irq.h"
  38. #include "sde_formats.h"
  39. #include "sde_hw_vbif.h"
  40. #include "sde_vbif.h"
  41. #include "sde_encoder.h"
  42. #include "sde_plane.h"
  43. #include "sde_crtc.h"
  44. #include "sde_reg_dma.h"
  45. #include "sde_connector.h"
  46. #include <linux/qcom_scm.h>
  47. #include "soc/qcom/secure_buffer.h"
  48. #include <linux/qtee_shmbridge.h>
  49. #define CREATE_TRACE_POINTS
  50. #include "sde_trace.h"
  51. /* defines for secure channel call */
  52. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  53. #define MDP_DEVICE_ID 0x1A
  54. EXPORT_TRACEPOINT_SYMBOL(sde_drm_tracing_mark_write);
  55. static const char * const iommu_ports[] = {
  56. "mdp_0",
  57. };
  58. /**
  59. * Controls size of event log buffer. Specified as a power of 2.
  60. */
  61. #define SDE_EVTLOG_SIZE 1024
  62. /*
  63. * To enable overall DRM driver logging
  64. * # echo 0x2 > /sys/module/drm/parameters/debug
  65. *
  66. * To enable DRM driver h/w logging
  67. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  68. *
  69. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  70. */
  71. #define SDE_DEBUGFS_DIR "msm_sde"
  72. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  73. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  74. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  75. /**
  76. * sdecustom - enable certain driver customizations for sde clients
  77. * Enabling this modifies the standard DRM behavior slightly and assumes
  78. * that the clients have specific knowledge about the modifications that
  79. * are involved, so don't enable this unless you know what you're doing.
  80. *
  81. * Parts of the driver that are affected by this setting may be located by
  82. * searching for invocations of the 'sde_is_custom_client()' function.
  83. *
  84. * This is disabled by default.
  85. */
  86. static bool sdecustom = true;
  87. module_param(sdecustom, bool, 0400);
  88. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  89. static int sde_kms_hw_init(struct msm_kms *kms);
  90. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  91. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  92. static int _sde_kms_register_events(struct msm_kms *kms,
  93. struct drm_mode_object *obj, u32 event, bool en);
  94. bool sde_is_custom_client(void)
  95. {
  96. return sdecustom;
  97. }
  98. #ifdef CONFIG_DEBUG_FS
  99. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  100. {
  101. struct msm_drm_private *priv;
  102. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  103. return NULL;
  104. priv = sde_kms->dev->dev_private;
  105. return priv->debug_root;
  106. }
  107. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  108. {
  109. void *p;
  110. int rc;
  111. void *debugfs_root;
  112. p = sde_hw_util_get_log_mask_ptr();
  113. if (!sde_kms || !p)
  114. return -EINVAL;
  115. debugfs_root = sde_debugfs_get_root(sde_kms);
  116. if (!debugfs_root)
  117. return -EINVAL;
  118. /* allow debugfs_root to be NULL */
  119. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  120. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  121. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  122. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  123. if (rc) {
  124. SDE_ERROR("failed to init perf %d\n", rc);
  125. return rc;
  126. }
  127. if (sde_kms->catalog->qdss_count)
  128. debugfs_create_u32("qdss", 0600, debugfs_root,
  129. (u32 *)&sde_kms->qdss_enabled);
  130. return 0;
  131. }
  132. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  133. {
  134. /* don't need to NULL check debugfs_root */
  135. if (sde_kms) {
  136. sde_debugfs_vbif_destroy(sde_kms);
  137. sde_debugfs_core_irq_destroy(sde_kms);
  138. }
  139. }
  140. #else
  141. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  142. {
  143. return 0;
  144. }
  145. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  146. {
  147. }
  148. #endif
  149. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  150. {
  151. int ret = 0;
  152. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  153. ret = sde_crtc_vblank(crtc, true);
  154. SDE_ATRACE_END("sde_kms_enable_vblank");
  155. return ret;
  156. }
  157. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  158. {
  159. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  160. sde_crtc_vblank(crtc, false);
  161. SDE_ATRACE_END("sde_kms_disable_vblank");
  162. }
  163. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  164. struct drm_crtc *crtc)
  165. {
  166. struct drm_encoder *encoder;
  167. struct drm_device *dev;
  168. int ret;
  169. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  170. SDE_ERROR("invalid params\n");
  171. return;
  172. }
  173. if (!crtc->state->enable) {
  174. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  175. return;
  176. }
  177. if (!crtc->state->active) {
  178. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  179. return;
  180. }
  181. dev = crtc->dev;
  182. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  183. if (encoder->crtc != crtc)
  184. continue;
  185. /*
  186. * Video Mode - Wait for VSYNC
  187. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  188. * complete
  189. */
  190. SDE_EVT32_VERBOSE(DRMID(crtc));
  191. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  192. if (ret && ret != -EWOULDBLOCK) {
  193. SDE_ERROR(
  194. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  195. crtc->base.id, encoder->base.id, ret);
  196. break;
  197. }
  198. }
  199. }
  200. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  201. struct drm_crtc *crtc, bool enable)
  202. {
  203. struct drm_device *dev;
  204. struct msm_drm_private *priv;
  205. struct sde_mdss_cfg *sde_cfg;
  206. struct drm_plane *plane;
  207. int i, ret;
  208. dev = sde_kms->dev;
  209. priv = dev->dev_private;
  210. sde_cfg = sde_kms->catalog;
  211. ret = sde_vbif_halt_xin_mask(sde_kms,
  212. sde_cfg->sui_block_xin_mask, enable);
  213. if (ret) {
  214. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  215. return ret;
  216. }
  217. if (enable) {
  218. for (i = 0; i < priv->num_planes; i++) {
  219. plane = priv->planes[i];
  220. sde_plane_secure_ctrl_xin_client(plane, crtc);
  221. }
  222. }
  223. return 0;
  224. }
  225. /**
  226. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  227. * @sde_kms: Pointer to sde_kms struct
  228. * @vimd: switch the stage 2 translation to this VMID
  229. */
  230. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  231. {
  232. struct drm_device *dev;
  233. uint32_t num_sids;
  234. uint32_t *sec_sid;
  235. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  236. int ret = 0, i;
  237. struct qtee_shm shm;
  238. bool qtee_en = qtee_shmbridge_is_enabled();
  239. phys_addr_t mem_addr;
  240. u64 mem_size;
  241. dev = sde_kms->dev;
  242. num_sids = sde_cfg->sec_sid_mask_count;
  243. if (!num_sids) {
  244. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  245. return -EINVAL;
  246. }
  247. if (qtee_en) {
  248. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  249. &shm);
  250. if (ret)
  251. return -ENOMEM;
  252. sec_sid = (uint32_t *) shm.vaddr;
  253. mem_addr = shm.paddr;
  254. mem_size = shm.size;
  255. } else {
  256. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  257. if (!sec_sid)
  258. return -ENOMEM;
  259. mem_addr = virt_to_phys(sec_sid);
  260. mem_size = sizeof(uint32_t) * num_sids;
  261. }
  262. for (i = 0; i < num_sids; i++) {
  263. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  264. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  265. }
  266. dma_map_single(dev->dev, sec_sid, num_sids *sizeof(uint32_t),
  267. DMA_TO_DEVICE);
  268. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  269. vmid, num_sids, qtee_en);
  270. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  271. mem_size, vmid);
  272. if (ret)
  273. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  274. vmid, ret);
  275. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  276. vmid, qtee_en, num_sids, ret);
  277. if (qtee_en)
  278. qtee_shmbridge_free_shm(&shm);
  279. else
  280. kfree(sec_sid);
  281. return ret;
  282. }
  283. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  284. {
  285. u32 ret;
  286. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  287. return 0;
  288. /* detach_all_contexts */
  289. ret = sde_kms_mmu_detach(sde_kms, false);
  290. if (ret) {
  291. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  292. goto mmu_error;
  293. }
  294. ret = _sde_kms_scm_call(sde_kms, vmid);
  295. if (ret) {
  296. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  297. goto scm_error;
  298. }
  299. return 0;
  300. scm_error:
  301. sde_kms_mmu_attach(sde_kms, false);
  302. mmu_error:
  303. atomic_dec(&sde_kms->detach_all_cb);
  304. return ret;
  305. }
  306. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  307. u32 old_vmid)
  308. {
  309. u32 ret;
  310. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  311. return 0;
  312. ret = _sde_kms_scm_call(sde_kms, vmid);
  313. if (ret) {
  314. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  315. goto scm_error;
  316. }
  317. /* attach_all_contexts */
  318. ret = sde_kms_mmu_attach(sde_kms, false);
  319. if (ret) {
  320. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  321. goto mmu_error;
  322. }
  323. return 0;
  324. mmu_error:
  325. _sde_kms_scm_call(sde_kms, old_vmid);
  326. scm_error:
  327. atomic_inc(&sde_kms->detach_all_cb);
  328. return ret;
  329. }
  330. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  331. {
  332. u32 ret;
  333. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  334. return 0;
  335. /* detach secure_context */
  336. ret = sde_kms_mmu_detach(sde_kms, true);
  337. if (ret) {
  338. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  339. goto mmu_error;
  340. }
  341. ret = _sde_kms_scm_call(sde_kms, vmid);
  342. if (ret) {
  343. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  344. goto scm_error;
  345. }
  346. return 0;
  347. scm_error:
  348. sde_kms_mmu_attach(sde_kms, true);
  349. mmu_error:
  350. atomic_dec(&sde_kms->detach_sec_cb);
  351. return ret;
  352. }
  353. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  354. u32 old_vmid)
  355. {
  356. u32 ret;
  357. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  358. return 0;
  359. ret = _sde_kms_scm_call(sde_kms, vmid);
  360. if (ret) {
  361. goto scm_error;
  362. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  363. }
  364. ret = sde_kms_mmu_attach(sde_kms, true);
  365. if (ret) {
  366. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  367. goto mmu_error;
  368. }
  369. return 0;
  370. mmu_error:
  371. _sde_kms_scm_call(sde_kms, old_vmid);
  372. scm_error:
  373. atomic_inc(&sde_kms->detach_sec_cb);
  374. return ret;
  375. }
  376. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  377. struct drm_crtc *crtc, bool enable)
  378. {
  379. int ret;
  380. if (enable) {
  381. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  382. if (ret < 0) {
  383. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  384. return ret;
  385. }
  386. sde_crtc_misr_setup(crtc, true, 1);
  387. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  388. if (ret) {
  389. sde_crtc_misr_setup(crtc, false, 0);
  390. pm_runtime_put_sync(sde_kms->dev->dev);
  391. return ret;
  392. }
  393. } else {
  394. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  395. sde_crtc_misr_setup(crtc, false, 0);
  396. pm_runtime_put_sync(sde_kms->dev->dev);
  397. }
  398. return 0;
  399. }
  400. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  401. bool post_commit)
  402. {
  403. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  404. int old_smmu_state = smmu_state->state;
  405. int ret = 0;
  406. u32 vmid;
  407. if (!sde_kms || !crtc) {
  408. SDE_ERROR("invalid argument(s)\n");
  409. return -EINVAL;
  410. }
  411. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  412. post_commit, smmu_state->sui_misr_state,
  413. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  414. if ((!smmu_state->transition_type) ||
  415. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  416. /* Bail out */
  417. return 0;
  418. /* enable sui misr if requested, before the transition */
  419. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  420. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  421. if (ret) {
  422. smmu_state->sui_misr_state = NONE;
  423. goto end;
  424. }
  425. }
  426. mutex_lock(&sde_kms->secure_transition_lock);
  427. switch (smmu_state->state) {
  428. case DETACH_ALL_REQ:
  429. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  430. if (!ret)
  431. smmu_state->state = DETACHED;
  432. break;
  433. case ATTACH_ALL_REQ:
  434. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  435. VMID_CP_SEC_DISPLAY);
  436. if (!ret) {
  437. smmu_state->state = ATTACHED;
  438. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  439. }
  440. break;
  441. case DETACH_SEC_REQ:
  442. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  443. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  444. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  445. if (!ret)
  446. smmu_state->state = DETACHED_SEC;
  447. break;
  448. case ATTACH_SEC_REQ:
  449. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  450. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  451. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  452. if (!ret) {
  453. smmu_state->state = ATTACHED;
  454. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  455. }
  456. break;
  457. default:
  458. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  459. DRMID(crtc), smmu_state->state,
  460. smmu_state->transition_type);
  461. ret = -EINVAL;
  462. break;
  463. }
  464. mutex_unlock(&sde_kms->secure_transition_lock);
  465. /* disable sui misr if requested, after the transition */
  466. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  467. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  468. if (ret)
  469. goto end;
  470. }
  471. end:
  472. smmu_state->transition_error = false;
  473. if (ret) {
  474. smmu_state->transition_error = true;
  475. SDE_ERROR(
  476. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  477. DRMID(crtc), old_smmu_state, smmu_state->state,
  478. smmu_state->secure_level, ret);
  479. smmu_state->state = smmu_state->prev_state;
  480. smmu_state->secure_level = smmu_state->prev_secure_level;
  481. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  482. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  483. }
  484. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  485. DRMID(crtc), old_smmu_state, smmu_state->state,
  486. smmu_state->secure_level, ret);
  487. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  488. smmu_state->transition_type,
  489. smmu_state->transition_error,
  490. smmu_state->secure_level, smmu_state->prev_secure_level,
  491. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  492. smmu_state->sui_misr_state = NONE;
  493. smmu_state->transition_type = NONE;
  494. return ret;
  495. }
  496. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  497. struct drm_atomic_state *state)
  498. {
  499. struct drm_crtc *crtc;
  500. struct drm_crtc_state *old_crtc_state;
  501. struct drm_plane_state *old_plane_state, *new_plane_state;
  502. struct drm_plane *plane;
  503. struct drm_plane_state *plane_state;
  504. struct sde_kms *sde_kms = to_sde_kms(kms);
  505. struct drm_device *dev = sde_kms->dev;
  506. int i, ops = 0, ret = 0;
  507. bool old_valid_fb = false;
  508. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  509. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  510. if (!crtc->state || !crtc->state->active)
  511. continue;
  512. /*
  513. * It is safe to assume only one active crtc,
  514. * and compatible translation modes on the
  515. * planes staged on this crtc.
  516. * otherwise validation would have failed.
  517. * For this CRTC,
  518. */
  519. /*
  520. * 1. Check if old state on the CRTC has planes
  521. * staged with valid fbs
  522. */
  523. for_each_old_plane_in_state(state, plane, plane_state, i) {
  524. if (!plane_state->crtc)
  525. continue;
  526. if (plane_state->fb) {
  527. old_valid_fb = true;
  528. break;
  529. }
  530. }
  531. /*
  532. * 2.Get the operations needed to be performed before
  533. * secure transition can be initiated.
  534. */
  535. ops = sde_crtc_get_secure_transition_ops(crtc,
  536. old_crtc_state, old_valid_fb);
  537. if (ops < 0) {
  538. SDE_ERROR("invalid secure operations %x\n", ops);
  539. return ops;
  540. }
  541. if (!ops) {
  542. smmu_state->transition_error = false;
  543. goto no_ops;
  544. }
  545. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  546. crtc->base.id, ops, crtc->state);
  547. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  548. /* 3. Perform operations needed for secure transition */
  549. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  550. SDE_DEBUG("wait_for_transfer_done\n");
  551. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  552. }
  553. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  554. SDE_DEBUG("cleanup planes\n");
  555. drm_atomic_helper_cleanup_planes(dev, state);
  556. for_each_oldnew_plane_in_state(state, plane,
  557. old_plane_state, new_plane_state, i)
  558. sde_plane_destroy_fb(old_plane_state);
  559. }
  560. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  561. SDE_DEBUG("secure ctrl\n");
  562. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  563. }
  564. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  565. SDE_DEBUG("prepare planes %d",
  566. crtc->state->plane_mask);
  567. drm_atomic_crtc_for_each_plane(plane,
  568. crtc) {
  569. const struct drm_plane_helper_funcs *funcs;
  570. plane_state = plane->state;
  571. funcs = plane->helper_private;
  572. SDE_DEBUG("psde:%d FB[%u]\n",
  573. plane->base.id,
  574. plane->fb->base.id);
  575. if (!funcs)
  576. continue;
  577. if (funcs->prepare_fb(plane, plane_state)) {
  578. ret = funcs->prepare_fb(plane,
  579. plane_state);
  580. if (ret)
  581. return ret;
  582. }
  583. }
  584. }
  585. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  586. SDE_DEBUG("secure operations completed\n");
  587. }
  588. no_ops:
  589. return 0;
  590. }
  591. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  592. unsigned int splash_buffer_size,
  593. unsigned int ramdump_base,
  594. unsigned int ramdump_buffer_size)
  595. {
  596. unsigned long pfn_start, pfn_end, pfn_idx;
  597. int ret = 0;
  598. if (!mem_addr || !splash_buffer_size) {
  599. SDE_ERROR("invalid params\n");
  600. return -EINVAL;
  601. }
  602. /* leave ramdump memory only if base address matches */
  603. if (ramdump_base == mem_addr &&
  604. ramdump_buffer_size <= splash_buffer_size) {
  605. mem_addr += ramdump_buffer_size;
  606. splash_buffer_size -= ramdump_buffer_size;
  607. }
  608. pfn_start = mem_addr >> PAGE_SHIFT;
  609. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  610. if (ret) {
  611. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  612. return ret;
  613. }
  614. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  615. free_reserved_page(pfn_to_page(pfn_idx));
  616. return ret;
  617. }
  618. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  619. struct sde_splash_mem *splash)
  620. {
  621. struct msm_mmu *mmu = NULL;
  622. int ret = 0;
  623. if (!sde_kms->aspace[0]) {
  624. SDE_ERROR("aspace not found for sde kms node\n");
  625. return -EINVAL;
  626. }
  627. mmu = sde_kms->aspace[0]->mmu;
  628. if (!mmu) {
  629. SDE_ERROR("mmu not found for aspace\n");
  630. return -EINVAL;
  631. }
  632. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  633. SDE_ERROR("invalid input params for map\n");
  634. return -EINVAL;
  635. }
  636. if (!splash->ref_cnt) {
  637. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  638. splash->splash_buf_base,
  639. splash->splash_buf_size,
  640. IOMMU_READ | IOMMU_NOEXEC);
  641. if (ret)
  642. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  643. }
  644. splash->ref_cnt++;
  645. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  646. splash->splash_buf_base,
  647. splash->splash_buf_size,
  648. splash->ref_cnt);
  649. return ret;
  650. }
  651. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  652. {
  653. int i = 0;
  654. int ret = 0;
  655. if (!sde_kms)
  656. return -EINVAL;
  657. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  658. ret = _sde_kms_splash_mem_get(sde_kms,
  659. sde_kms->splash_data.splash_display[i].splash);
  660. if (ret)
  661. return ret;
  662. }
  663. return ret;
  664. }
  665. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  666. struct sde_splash_mem *splash)
  667. {
  668. struct msm_mmu *mmu = NULL;
  669. int rc = 0;
  670. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  671. SDE_ERROR("invalid params\n");
  672. return -EINVAL;
  673. }
  674. mmu = sde_kms->aspace[0]->mmu;
  675. if (!splash || !splash->ref_cnt ||
  676. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  677. return -EINVAL;
  678. splash->ref_cnt--;
  679. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  680. splash->splash_buf_base, splash->ref_cnt);
  681. if (!splash->ref_cnt) {
  682. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  683. splash->splash_buf_size);
  684. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  685. splash->splash_buf_size, splash->ramdump_base,
  686. splash->ramdump_size);
  687. splash->splash_buf_base = 0;
  688. splash->splash_buf_size = 0;
  689. }
  690. return rc;
  691. }
  692. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  693. {
  694. int i = 0;
  695. int ret = 0;
  696. if (!sde_kms)
  697. return -EINVAL;
  698. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  699. ret = _sde_kms_splash_mem_put(sde_kms,
  700. sde_kms->splash_data.splash_display[i].splash);
  701. if (ret)
  702. return ret;
  703. }
  704. return ret;
  705. }
  706. static void sde_kms_prepare_commit(struct msm_kms *kms,
  707. struct drm_atomic_state *state)
  708. {
  709. struct sde_kms *sde_kms;
  710. struct msm_drm_private *priv;
  711. struct drm_device *dev;
  712. struct drm_encoder *encoder;
  713. struct drm_crtc *crtc;
  714. struct drm_crtc_state *crtc_state;
  715. int i, rc;
  716. if (!kms)
  717. return;
  718. sde_kms = to_sde_kms(kms);
  719. dev = sde_kms->dev;
  720. if (!dev || !dev->dev_private)
  721. return;
  722. priv = dev->dev_private;
  723. SDE_ATRACE_BEGIN("prepare_commit");
  724. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  725. if (rc < 0) {
  726. SDE_ERROR("failed to enable power resources %d\n", rc);
  727. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  728. goto end;
  729. }
  730. if (sde_kms->first_kickoff) {
  731. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  732. sde_kms->first_kickoff = false;
  733. }
  734. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  735. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  736. head) {
  737. if (encoder->crtc != crtc)
  738. continue;
  739. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  740. SDE_ERROR("crtc:%d, initiating hw reset\n",
  741. DRMID(crtc));
  742. sde_encoder_needs_hw_reset(encoder);
  743. sde_crtc_set_needs_hw_reset(crtc);
  744. }
  745. }
  746. }
  747. /*
  748. * NOTE: for secure use cases we want to apply the new HW
  749. * configuration only after completing preparation for secure
  750. * transitions prepare below if any transtions is required.
  751. */
  752. sde_kms_prepare_secure_transition(kms, state);
  753. end:
  754. SDE_ATRACE_END("prepare_commit");
  755. }
  756. static void sde_kms_commit(struct msm_kms *kms,
  757. struct drm_atomic_state *old_state)
  758. {
  759. struct sde_kms *sde_kms;
  760. struct drm_crtc *crtc;
  761. struct drm_crtc_state *old_crtc_state;
  762. int i;
  763. if (!kms || !old_state)
  764. return;
  765. sde_kms = to_sde_kms(kms);
  766. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  767. SDE_ERROR("power resource is not enabled\n");
  768. return;
  769. }
  770. SDE_ATRACE_BEGIN("sde_kms_commit");
  771. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  772. if (crtc->state->active) {
  773. SDE_EVT32(DRMID(crtc));
  774. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  775. }
  776. }
  777. SDE_ATRACE_END("sde_kms_commit");
  778. }
  779. static void _sde_kms_free_splash_region(struct sde_kms *sde_kms,
  780. struct sde_splash_display *splash_display)
  781. {
  782. if (!sde_kms || !splash_display ||
  783. !sde_kms->splash_data.num_splash_displays)
  784. return;
  785. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  786. sde_kms->splash_data.num_splash_displays--;
  787. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  788. sde_kms->splash_data.num_splash_displays);
  789. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  790. }
  791. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  792. struct drm_crtc *crtc)
  793. {
  794. struct msm_drm_private *priv;
  795. struct sde_splash_display *splash_display;
  796. int i;
  797. if (!sde_kms || !crtc)
  798. return;
  799. priv = sde_kms->dev->dev_private;
  800. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  801. return;
  802. SDE_EVT32(DRMID(crtc), crtc->state->active,
  803. sde_kms->splash_data.num_splash_displays);
  804. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  805. splash_display = &sde_kms->splash_data.splash_display[i];
  806. if (splash_display->encoder &&
  807. crtc == splash_display->encoder->crtc)
  808. break;
  809. }
  810. if (i >= MAX_DSI_DISPLAYS)
  811. return;
  812. if (splash_display->cont_splash_enabled) {
  813. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  814. splash_display, false);
  815. _sde_kms_free_splash_region(sde_kms, splash_display);
  816. }
  817. /* remove the votes if all displays are done with splash */
  818. if (!sde_kms->splash_data.num_splash_displays) {
  819. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  820. sde_power_data_bus_set_quota(&priv->phandle, i,
  821. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  822. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  823. pm_runtime_put_sync(sde_kms->dev->dev);
  824. }
  825. }
  826. static void sde_kms_complete_commit(struct msm_kms *kms,
  827. struct drm_atomic_state *old_state)
  828. {
  829. struct sde_kms *sde_kms;
  830. struct msm_drm_private *priv;
  831. struct drm_crtc *crtc;
  832. struct drm_crtc_state *old_crtc_state;
  833. struct drm_connector *connector;
  834. struct drm_connector_state *old_conn_state;
  835. struct msm_display_conn_params params;
  836. int i, rc = 0;
  837. if (!kms || !old_state)
  838. return;
  839. sde_kms = to_sde_kms(kms);
  840. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  841. return;
  842. priv = sde_kms->dev->dev_private;
  843. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  844. SDE_ERROR("power resource is not enabled\n");
  845. return;
  846. }
  847. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  848. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  849. sde_crtc_complete_commit(crtc, old_crtc_state);
  850. /* complete secure transitions if any */
  851. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  852. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  853. }
  854. for_each_old_connector_in_state(old_state, connector,
  855. old_conn_state, i) {
  856. struct sde_connector *c_conn;
  857. c_conn = to_sde_connector(connector);
  858. if (!c_conn->ops.post_kickoff)
  859. continue;
  860. memset(&params, 0, sizeof(params));
  861. sde_connector_complete_qsync_commit(connector, &params);
  862. rc = c_conn->ops.post_kickoff(connector, &params);
  863. if (rc) {
  864. pr_err("Connector Post kickoff failed rc=%d\n",
  865. rc);
  866. }
  867. }
  868. pm_runtime_put_sync(sde_kms->dev->dev);
  869. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  870. _sde_kms_release_splash_resource(sde_kms, crtc);
  871. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  872. SDE_ATRACE_END("sde_kms_complete_commit");
  873. }
  874. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  875. struct drm_crtc *crtc)
  876. {
  877. struct drm_encoder *encoder;
  878. struct drm_device *dev;
  879. int ret;
  880. if (!kms || !crtc || !crtc->state) {
  881. SDE_ERROR("invalid params\n");
  882. return;
  883. }
  884. dev = crtc->dev;
  885. if (!crtc->state->enable) {
  886. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  887. return;
  888. }
  889. if (!crtc->state->active) {
  890. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  891. return;
  892. }
  893. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  894. SDE_ERROR("power resource is not enabled\n");
  895. return;
  896. }
  897. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  898. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  899. if (encoder->crtc != crtc)
  900. continue;
  901. /*
  902. * Wait for post-flush if necessary to delay before
  903. * plane_cleanup. For example, wait for vsync in case of video
  904. * mode panels. This may be a no-op for command mode panels.
  905. */
  906. SDE_EVT32_VERBOSE(DRMID(crtc));
  907. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  908. if (ret && ret != -EWOULDBLOCK) {
  909. SDE_ERROR("wait for commit done returned %d\n", ret);
  910. sde_crtc_request_frame_reset(crtc);
  911. break;
  912. }
  913. sde_crtc_complete_flip(crtc, NULL);
  914. }
  915. sde_crtc_static_cache_read_kickoff(crtc);
  916. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  917. }
  918. static void sde_kms_prepare_fence(struct msm_kms *kms,
  919. struct drm_atomic_state *old_state)
  920. {
  921. struct drm_crtc *crtc;
  922. struct drm_crtc_state *old_crtc_state;
  923. int i, rc;
  924. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  925. SDE_ERROR("invalid argument(s)\n");
  926. return;
  927. }
  928. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  929. retry:
  930. /* attempt to acquire ww mutex for connection */
  931. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  932. old_state->acquire_ctx);
  933. if (rc == -EDEADLK) {
  934. drm_modeset_backoff(old_state->acquire_ctx);
  935. goto retry;
  936. }
  937. /* old_state actually contains updated crtc pointers */
  938. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  939. if (crtc->state->active || crtc->state->active_changed)
  940. sde_crtc_prepare_commit(crtc, old_crtc_state);
  941. }
  942. SDE_ATRACE_END("sde_kms_prepare_fence");
  943. }
  944. /**
  945. * _sde_kms_get_displays - query for underlying display handles and cache them
  946. * @sde_kms: Pointer to sde kms structure
  947. * Returns: Zero on success
  948. */
  949. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  950. {
  951. int rc = -ENOMEM;
  952. if (!sde_kms) {
  953. SDE_ERROR("invalid sde kms\n");
  954. return -EINVAL;
  955. }
  956. /* dsi */
  957. sde_kms->dsi_displays = NULL;
  958. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  959. if (sde_kms->dsi_display_count) {
  960. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  961. sizeof(void *),
  962. GFP_KERNEL);
  963. if (!sde_kms->dsi_displays) {
  964. SDE_ERROR("failed to allocate dsi displays\n");
  965. goto exit_deinit_dsi;
  966. }
  967. sde_kms->dsi_display_count =
  968. dsi_display_get_active_displays(sde_kms->dsi_displays,
  969. sde_kms->dsi_display_count);
  970. }
  971. /* wb */
  972. sde_kms->wb_displays = NULL;
  973. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  974. if (sde_kms->wb_display_count) {
  975. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  976. sizeof(void *),
  977. GFP_KERNEL);
  978. if (!sde_kms->wb_displays) {
  979. SDE_ERROR("failed to allocate wb displays\n");
  980. goto exit_deinit_wb;
  981. }
  982. sde_kms->wb_display_count =
  983. wb_display_get_displays(sde_kms->wb_displays,
  984. sde_kms->wb_display_count);
  985. }
  986. /* dp */
  987. sde_kms->dp_displays = NULL;
  988. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  989. if (sde_kms->dp_display_count) {
  990. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  991. sizeof(void *), GFP_KERNEL);
  992. if (!sde_kms->dp_displays) {
  993. SDE_ERROR("failed to allocate dp displays\n");
  994. goto exit_deinit_dp;
  995. }
  996. sde_kms->dp_display_count =
  997. dp_display_get_displays(sde_kms->dp_displays,
  998. sde_kms->dp_display_count);
  999. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1000. }
  1001. return 0;
  1002. exit_deinit_dp:
  1003. kfree(sde_kms->dp_displays);
  1004. sde_kms->dp_stream_count = 0;
  1005. sde_kms->dp_display_count = 0;
  1006. sde_kms->dp_displays = NULL;
  1007. exit_deinit_wb:
  1008. kfree(sde_kms->wb_displays);
  1009. sde_kms->wb_display_count = 0;
  1010. sde_kms->wb_displays = NULL;
  1011. exit_deinit_dsi:
  1012. kfree(sde_kms->dsi_displays);
  1013. sde_kms->dsi_display_count = 0;
  1014. sde_kms->dsi_displays = NULL;
  1015. return rc;
  1016. }
  1017. /**
  1018. * _sde_kms_release_displays - release cache of underlying display handles
  1019. * @sde_kms: Pointer to sde kms structure
  1020. */
  1021. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1022. {
  1023. if (!sde_kms) {
  1024. SDE_ERROR("invalid sde kms\n");
  1025. return;
  1026. }
  1027. kfree(sde_kms->wb_displays);
  1028. sde_kms->wb_displays = NULL;
  1029. sde_kms->wb_display_count = 0;
  1030. kfree(sde_kms->dsi_displays);
  1031. sde_kms->dsi_displays = NULL;
  1032. sde_kms->dsi_display_count = 0;
  1033. }
  1034. /**
  1035. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1036. * for underlying displays
  1037. * @dev: Pointer to drm device structure
  1038. * @priv: Pointer to private drm device data
  1039. * @sde_kms: Pointer to sde kms structure
  1040. * Returns: Zero on success
  1041. */
  1042. static int _sde_kms_setup_displays(struct drm_device *dev,
  1043. struct msm_drm_private *priv,
  1044. struct sde_kms *sde_kms)
  1045. {
  1046. static const struct sde_connector_ops dsi_ops = {
  1047. .set_info_blob = dsi_conn_set_info_blob,
  1048. .detect = dsi_conn_detect,
  1049. .get_modes = dsi_connector_get_modes,
  1050. .pre_destroy = dsi_connector_put_modes,
  1051. .mode_valid = dsi_conn_mode_valid,
  1052. .get_info = dsi_display_get_info,
  1053. .set_backlight = dsi_display_set_backlight,
  1054. .soft_reset = dsi_display_soft_reset,
  1055. .pre_kickoff = dsi_conn_pre_kickoff,
  1056. .clk_ctrl = dsi_display_clk_ctrl,
  1057. .set_power = dsi_display_set_power,
  1058. .get_mode_info = dsi_conn_get_mode_info,
  1059. .get_dst_format = dsi_display_get_dst_format,
  1060. .post_kickoff = dsi_conn_post_kickoff,
  1061. .check_status = dsi_display_check_status,
  1062. .enable_event = dsi_conn_enable_event,
  1063. .cmd_transfer = dsi_display_cmd_transfer,
  1064. .cont_splash_config = dsi_display_cont_splash_config,
  1065. .get_panel_vfp = dsi_display_get_panel_vfp,
  1066. .get_default_lms = dsi_display_get_default_lms,
  1067. };
  1068. static const struct sde_connector_ops wb_ops = {
  1069. .post_init = sde_wb_connector_post_init,
  1070. .set_info_blob = sde_wb_connector_set_info_blob,
  1071. .detect = sde_wb_connector_detect,
  1072. .get_modes = sde_wb_connector_get_modes,
  1073. .set_property = sde_wb_connector_set_property,
  1074. .get_info = sde_wb_get_info,
  1075. .soft_reset = NULL,
  1076. .get_mode_info = sde_wb_get_mode_info,
  1077. .get_dst_format = NULL,
  1078. .check_status = NULL,
  1079. .cmd_transfer = NULL,
  1080. .cont_splash_config = NULL,
  1081. .get_panel_vfp = NULL,
  1082. };
  1083. static const struct sde_connector_ops dp_ops = {
  1084. .post_init = dp_connector_post_init,
  1085. .detect = dp_connector_detect,
  1086. .get_modes = dp_connector_get_modes,
  1087. .atomic_check = dp_connector_atomic_check,
  1088. .mode_valid = dp_connector_mode_valid,
  1089. .get_info = dp_connector_get_info,
  1090. .get_mode_info = dp_connector_get_mode_info,
  1091. .post_open = dp_connector_post_open,
  1092. .check_status = NULL,
  1093. .set_colorspace = dp_connector_set_colorspace,
  1094. .config_hdr = dp_connector_config_hdr,
  1095. .cmd_transfer = NULL,
  1096. .cont_splash_config = NULL,
  1097. .get_panel_vfp = NULL,
  1098. .update_pps = dp_connector_update_pps,
  1099. };
  1100. struct msm_display_info info;
  1101. struct drm_encoder *encoder;
  1102. void *display, *connector;
  1103. int i, max_encoders;
  1104. int rc = 0;
  1105. if (!dev || !priv || !sde_kms) {
  1106. SDE_ERROR("invalid argument(s)\n");
  1107. return -EINVAL;
  1108. }
  1109. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1110. sde_kms->dp_display_count +
  1111. sde_kms->dp_stream_count;
  1112. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1113. max_encoders = ARRAY_SIZE(priv->encoders);
  1114. SDE_ERROR("capping number of displays to %d", max_encoders);
  1115. }
  1116. /* wb */
  1117. for (i = 0; i < sde_kms->wb_display_count &&
  1118. priv->num_encoders < max_encoders; ++i) {
  1119. display = sde_kms->wb_displays[i];
  1120. encoder = NULL;
  1121. memset(&info, 0x0, sizeof(info));
  1122. rc = sde_wb_get_info(NULL, &info, display);
  1123. if (rc) {
  1124. SDE_ERROR("wb get_info %d failed\n", i);
  1125. continue;
  1126. }
  1127. encoder = sde_encoder_init(dev, &info);
  1128. if (IS_ERR_OR_NULL(encoder)) {
  1129. SDE_ERROR("encoder init failed for wb %d\n", i);
  1130. continue;
  1131. }
  1132. rc = sde_wb_drm_init(display, encoder);
  1133. if (rc) {
  1134. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1135. sde_encoder_destroy(encoder);
  1136. continue;
  1137. }
  1138. connector = sde_connector_init(dev,
  1139. encoder,
  1140. 0,
  1141. display,
  1142. &wb_ops,
  1143. DRM_CONNECTOR_POLL_HPD,
  1144. DRM_MODE_CONNECTOR_VIRTUAL);
  1145. if (connector) {
  1146. priv->encoders[priv->num_encoders++] = encoder;
  1147. priv->connectors[priv->num_connectors++] = connector;
  1148. } else {
  1149. SDE_ERROR("wb %d connector init failed\n", i);
  1150. sde_wb_drm_deinit(display);
  1151. sde_encoder_destroy(encoder);
  1152. }
  1153. }
  1154. /* dsi */
  1155. for (i = 0; i < sde_kms->dsi_display_count &&
  1156. priv->num_encoders < max_encoders; ++i) {
  1157. display = sde_kms->dsi_displays[i];
  1158. encoder = NULL;
  1159. memset(&info, 0x0, sizeof(info));
  1160. rc = dsi_display_get_info(NULL, &info, display);
  1161. if (rc) {
  1162. SDE_ERROR("dsi get_info %d failed\n", i);
  1163. continue;
  1164. }
  1165. encoder = sde_encoder_init(dev, &info);
  1166. if (IS_ERR_OR_NULL(encoder)) {
  1167. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1168. continue;
  1169. }
  1170. rc = dsi_display_drm_bridge_init(display, encoder);
  1171. if (rc) {
  1172. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1173. sde_encoder_destroy(encoder);
  1174. continue;
  1175. }
  1176. connector = sde_connector_init(dev,
  1177. encoder,
  1178. dsi_display_get_drm_panel(display),
  1179. display,
  1180. &dsi_ops,
  1181. DRM_CONNECTOR_POLL_HPD,
  1182. DRM_MODE_CONNECTOR_DSI);
  1183. if (connector) {
  1184. priv->encoders[priv->num_encoders++] = encoder;
  1185. priv->connectors[priv->num_connectors++] = connector;
  1186. } else {
  1187. SDE_ERROR("dsi %d connector init failed\n", i);
  1188. dsi_display_drm_bridge_deinit(display);
  1189. sde_encoder_destroy(encoder);
  1190. continue;
  1191. }
  1192. rc = dsi_display_drm_ext_bridge_init(display,
  1193. encoder, connector);
  1194. if (rc) {
  1195. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1196. dsi_display_drm_bridge_deinit(display);
  1197. sde_connector_destroy(connector);
  1198. sde_encoder_destroy(encoder);
  1199. }
  1200. }
  1201. /* dp */
  1202. for (i = 0; i < sde_kms->dp_display_count &&
  1203. priv->num_encoders < max_encoders; ++i) {
  1204. int idx;
  1205. display = sde_kms->dp_displays[i];
  1206. encoder = NULL;
  1207. memset(&info, 0x0, sizeof(info));
  1208. rc = dp_connector_get_info(NULL, &info, display);
  1209. if (rc) {
  1210. SDE_ERROR("dp get_info %d failed\n", i);
  1211. continue;
  1212. }
  1213. encoder = sde_encoder_init(dev, &info);
  1214. if (IS_ERR_OR_NULL(encoder)) {
  1215. SDE_ERROR("dp encoder init failed %d\n", i);
  1216. continue;
  1217. }
  1218. rc = dp_drm_bridge_init(display, encoder);
  1219. if (rc) {
  1220. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1221. sde_encoder_destroy(encoder);
  1222. continue;
  1223. }
  1224. connector = sde_connector_init(dev,
  1225. encoder,
  1226. NULL,
  1227. display,
  1228. &dp_ops,
  1229. DRM_CONNECTOR_POLL_HPD,
  1230. DRM_MODE_CONNECTOR_DisplayPort);
  1231. if (connector) {
  1232. priv->encoders[priv->num_encoders++] = encoder;
  1233. priv->connectors[priv->num_connectors++] = connector;
  1234. } else {
  1235. SDE_ERROR("dp %d connector init failed\n", i);
  1236. dp_drm_bridge_deinit(display);
  1237. sde_encoder_destroy(encoder);
  1238. }
  1239. /* update display cap to MST_MODE for DP MST encoders */
  1240. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1241. for (idx = 0; idx < sde_kms->dp_stream_count; idx++) {
  1242. info.h_tile_instance[0] = idx;
  1243. encoder = sde_encoder_init(dev, &info);
  1244. if (IS_ERR_OR_NULL(encoder)) {
  1245. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1246. continue;
  1247. }
  1248. rc = dp_mst_drm_bridge_init(display, encoder);
  1249. if (rc) {
  1250. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1251. i, rc);
  1252. sde_encoder_destroy(encoder);
  1253. continue;
  1254. }
  1255. priv->encoders[priv->num_encoders++] = encoder;
  1256. }
  1257. }
  1258. return 0;
  1259. }
  1260. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1261. {
  1262. struct msm_drm_private *priv;
  1263. int i;
  1264. if (!sde_kms) {
  1265. SDE_ERROR("invalid sde_kms\n");
  1266. return;
  1267. } else if (!sde_kms->dev) {
  1268. SDE_ERROR("invalid dev\n");
  1269. return;
  1270. } else if (!sde_kms->dev->dev_private) {
  1271. SDE_ERROR("invalid dev_private\n");
  1272. return;
  1273. }
  1274. priv = sde_kms->dev->dev_private;
  1275. for (i = 0; i < priv->num_crtcs; i++)
  1276. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1277. priv->num_crtcs = 0;
  1278. for (i = 0; i < priv->num_planes; i++)
  1279. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1280. priv->num_planes = 0;
  1281. for (i = 0; i < priv->num_connectors; i++)
  1282. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1283. priv->num_connectors = 0;
  1284. for (i = 0; i < priv->num_encoders; i++)
  1285. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1286. priv->num_encoders = 0;
  1287. _sde_kms_release_displays(sde_kms);
  1288. }
  1289. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1290. {
  1291. struct drm_device *dev;
  1292. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1293. struct drm_crtc *crtc;
  1294. struct msm_drm_private *priv;
  1295. struct sde_mdss_cfg *catalog;
  1296. int primary_planes_idx = 0, i, ret;
  1297. int max_crtc_count;
  1298. u32 sspp_id[MAX_PLANES];
  1299. u32 master_plane_id[MAX_PLANES];
  1300. u32 num_virt_planes = 0;
  1301. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1302. SDE_ERROR("invalid sde_kms\n");
  1303. return -EINVAL;
  1304. }
  1305. dev = sde_kms->dev;
  1306. priv = dev->dev_private;
  1307. catalog = sde_kms->catalog;
  1308. ret = sde_core_irq_domain_add(sde_kms);
  1309. if (ret)
  1310. goto fail_irq;
  1311. /*
  1312. * Query for underlying display drivers, and create connectors,
  1313. * bridges and encoders for them.
  1314. */
  1315. if (!_sde_kms_get_displays(sde_kms))
  1316. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1317. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1318. /* Create the planes */
  1319. for (i = 0; i < catalog->sspp_count; i++) {
  1320. bool primary = true;
  1321. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1322. || primary_planes_idx >= max_crtc_count)
  1323. primary = false;
  1324. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1325. (1UL << max_crtc_count) - 1, 0);
  1326. if (IS_ERR(plane)) {
  1327. SDE_ERROR("sde_plane_init failed\n");
  1328. ret = PTR_ERR(plane);
  1329. goto fail;
  1330. }
  1331. priv->planes[priv->num_planes++] = plane;
  1332. if (primary)
  1333. primary_planes[primary_planes_idx++] = plane;
  1334. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1335. sde_is_custom_client()) {
  1336. int priority =
  1337. catalog->sspp[i].sblk->smart_dma_priority;
  1338. sspp_id[priority - 1] = catalog->sspp[i].id;
  1339. master_plane_id[priority - 1] = plane->base.id;
  1340. num_virt_planes++;
  1341. }
  1342. }
  1343. /* Initialize smart DMA virtual planes */
  1344. for (i = 0; i < num_virt_planes; i++) {
  1345. plane = sde_plane_init(dev, sspp_id[i], false,
  1346. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1347. if (IS_ERR(plane)) {
  1348. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1349. ret = PTR_ERR(plane);
  1350. goto fail;
  1351. }
  1352. priv->planes[priv->num_planes++] = plane;
  1353. }
  1354. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1355. /* Create one CRTC per encoder */
  1356. for (i = 0; i < max_crtc_count; i++) {
  1357. crtc = sde_crtc_init(dev, primary_planes[i]);
  1358. if (IS_ERR(crtc)) {
  1359. ret = PTR_ERR(crtc);
  1360. goto fail;
  1361. }
  1362. priv->crtcs[priv->num_crtcs++] = crtc;
  1363. }
  1364. if (sde_is_custom_client()) {
  1365. /* All CRTCs are compatible with all planes */
  1366. for (i = 0; i < priv->num_planes; i++)
  1367. priv->planes[i]->possible_crtcs =
  1368. (1 << priv->num_crtcs) - 1;
  1369. }
  1370. /* All CRTCs are compatible with all encoders */
  1371. for (i = 0; i < priv->num_encoders; i++)
  1372. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1373. return 0;
  1374. fail:
  1375. _sde_kms_drm_obj_destroy(sde_kms);
  1376. fail_irq:
  1377. sde_core_irq_domain_fini(sde_kms);
  1378. return ret;
  1379. }
  1380. /**
  1381. * sde_kms_timeline_status - provides current timeline status
  1382. * This API should be called without mode config lock.
  1383. * @dev: Pointer to drm device
  1384. */
  1385. void sde_kms_timeline_status(struct drm_device *dev)
  1386. {
  1387. struct drm_crtc *crtc;
  1388. struct drm_connector *conn;
  1389. struct drm_connector_list_iter conn_iter;
  1390. if (!dev) {
  1391. SDE_ERROR("invalid drm device node\n");
  1392. return;
  1393. }
  1394. drm_for_each_crtc(crtc, dev)
  1395. sde_crtc_timeline_status(crtc);
  1396. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1397. /*
  1398. *Probably locked from last close dumping status anyway
  1399. */
  1400. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1401. drm_connector_list_iter_begin(dev, &conn_iter);
  1402. drm_for_each_connector_iter(conn, &conn_iter)
  1403. sde_conn_timeline_status(conn);
  1404. drm_connector_list_iter_end(&conn_iter);
  1405. return;
  1406. }
  1407. mutex_lock(&dev->mode_config.mutex);
  1408. drm_connector_list_iter_begin(dev, &conn_iter);
  1409. drm_for_each_connector_iter(conn, &conn_iter)
  1410. sde_conn_timeline_status(conn);
  1411. drm_connector_list_iter_end(&conn_iter);
  1412. mutex_unlock(&dev->mode_config.mutex);
  1413. }
  1414. static int sde_kms_postinit(struct msm_kms *kms)
  1415. {
  1416. struct sde_kms *sde_kms = to_sde_kms(kms);
  1417. struct drm_device *dev;
  1418. struct drm_crtc *crtc;
  1419. int rc;
  1420. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1421. SDE_ERROR("invalid sde_kms\n");
  1422. return -EINVAL;
  1423. }
  1424. dev = sde_kms->dev;
  1425. rc = _sde_debugfs_init(sde_kms);
  1426. if (rc)
  1427. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1428. drm_for_each_crtc(crtc, dev)
  1429. sde_crtc_post_init(dev, crtc);
  1430. return rc;
  1431. }
  1432. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1433. struct drm_encoder *encoder)
  1434. {
  1435. return rate;
  1436. }
  1437. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1438. struct platform_device *pdev)
  1439. {
  1440. struct drm_device *dev;
  1441. struct msm_drm_private *priv;
  1442. int i;
  1443. if (!sde_kms || !pdev)
  1444. return;
  1445. dev = sde_kms->dev;
  1446. if (!dev)
  1447. return;
  1448. priv = dev->dev_private;
  1449. if (!priv)
  1450. return;
  1451. if (sde_kms->genpd_init) {
  1452. sde_kms->genpd_init = false;
  1453. pm_genpd_remove(&sde_kms->genpd);
  1454. of_genpd_del_provider(pdev->dev.of_node);
  1455. }
  1456. if (sde_kms->hw_intr)
  1457. sde_hw_intr_destroy(sde_kms->hw_intr);
  1458. sde_kms->hw_intr = NULL;
  1459. if (sde_kms->power_event)
  1460. sde_power_handle_unregister_event(
  1461. &priv->phandle, sde_kms->power_event);
  1462. _sde_kms_release_displays(sde_kms);
  1463. _sde_kms_unmap_all_splash_regions(sde_kms);
  1464. /* safe to call these more than once during shutdown */
  1465. _sde_debugfs_destroy(sde_kms);
  1466. _sde_kms_mmu_destroy(sde_kms);
  1467. if (sde_kms->catalog) {
  1468. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1469. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1470. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1471. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1472. }
  1473. }
  1474. if (sde_kms->rm_init)
  1475. sde_rm_destroy(&sde_kms->rm);
  1476. sde_kms->rm_init = false;
  1477. if (sde_kms->catalog)
  1478. sde_hw_catalog_deinit(sde_kms->catalog);
  1479. sde_kms->catalog = NULL;
  1480. if (sde_kms->sid)
  1481. msm_iounmap(pdev, sde_kms->sid);
  1482. sde_kms->sid = NULL;
  1483. if (sde_kms->reg_dma)
  1484. msm_iounmap(pdev, sde_kms->reg_dma);
  1485. sde_kms->reg_dma = NULL;
  1486. if (sde_kms->vbif[VBIF_NRT])
  1487. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1488. sde_kms->vbif[VBIF_NRT] = NULL;
  1489. if (sde_kms->vbif[VBIF_RT])
  1490. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1491. sde_kms->vbif[VBIF_RT] = NULL;
  1492. if (sde_kms->mmio)
  1493. msm_iounmap(pdev, sde_kms->mmio);
  1494. sde_kms->mmio = NULL;
  1495. sde_reg_dma_deinit();
  1496. }
  1497. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1498. {
  1499. int i;
  1500. if (!sde_kms)
  1501. return -EINVAL;
  1502. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1503. struct msm_mmu *mmu;
  1504. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1505. if (!aspace)
  1506. continue;
  1507. mmu = sde_kms->aspace[i]->mmu;
  1508. if (secure_only &&
  1509. !aspace->mmu->funcs->is_domain_secure(mmu))
  1510. continue;
  1511. /* cleanup aspace before detaching */
  1512. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1513. SDE_DEBUG("Detaching domain:%d\n", i);
  1514. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1515. ARRAY_SIZE(iommu_ports));
  1516. aspace->domain_attached = false;
  1517. }
  1518. return 0;
  1519. }
  1520. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1521. {
  1522. int i;
  1523. if (!sde_kms)
  1524. return -EINVAL;
  1525. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1526. struct msm_mmu *mmu;
  1527. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1528. if (!aspace)
  1529. continue;
  1530. mmu = sde_kms->aspace[i]->mmu;
  1531. if (secure_only &&
  1532. !aspace->mmu->funcs->is_domain_secure(mmu))
  1533. continue;
  1534. SDE_DEBUG("Attaching domain:%d\n", i);
  1535. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1536. ARRAY_SIZE(iommu_ports));
  1537. aspace->domain_attached = true;
  1538. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1539. }
  1540. return 0;
  1541. }
  1542. static void sde_kms_destroy(struct msm_kms *kms)
  1543. {
  1544. struct sde_kms *sde_kms;
  1545. struct drm_device *dev;
  1546. if (!kms) {
  1547. SDE_ERROR("invalid kms\n");
  1548. return;
  1549. }
  1550. sde_kms = to_sde_kms(kms);
  1551. dev = sde_kms->dev;
  1552. if (!dev || !dev->dev) {
  1553. SDE_ERROR("invalid device\n");
  1554. return;
  1555. }
  1556. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1557. kfree(sde_kms);
  1558. }
  1559. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1560. struct drm_atomic_state *state)
  1561. {
  1562. struct drm_device *dev = sde_kms->dev;
  1563. struct drm_plane *plane;
  1564. struct drm_plane_state *plane_state;
  1565. struct drm_crtc *crtc;
  1566. struct drm_crtc_state *crtc_state;
  1567. struct drm_connector *conn;
  1568. struct drm_connector_state *conn_state;
  1569. struct drm_connector_list_iter conn_iter;
  1570. int ret = 0;
  1571. drm_for_each_plane(plane, dev) {
  1572. plane_state = drm_atomic_get_plane_state(state, plane);
  1573. if (IS_ERR(plane_state)) {
  1574. ret = PTR_ERR(plane_state);
  1575. SDE_ERROR("error %d getting plane %d state\n",
  1576. ret, DRMID(plane));
  1577. return ret;
  1578. }
  1579. ret = sde_plane_helper_reset_custom_properties(plane,
  1580. plane_state);
  1581. if (ret) {
  1582. SDE_ERROR("error %d resetting plane props %d\n",
  1583. ret, DRMID(plane));
  1584. return ret;
  1585. }
  1586. }
  1587. drm_for_each_crtc(crtc, dev) {
  1588. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1589. if (IS_ERR(crtc_state)) {
  1590. ret = PTR_ERR(crtc_state);
  1591. SDE_ERROR("error %d getting crtc %d state\n",
  1592. ret, DRMID(crtc));
  1593. return ret;
  1594. }
  1595. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1596. if (ret) {
  1597. SDE_ERROR("error %d resetting crtc props %d\n",
  1598. ret, DRMID(crtc));
  1599. return ret;
  1600. }
  1601. }
  1602. drm_connector_list_iter_begin(dev, &conn_iter);
  1603. drm_for_each_connector_iter(conn, &conn_iter) {
  1604. conn_state = drm_atomic_get_connector_state(state, conn);
  1605. if (IS_ERR(conn_state)) {
  1606. ret = PTR_ERR(conn_state);
  1607. SDE_ERROR("error %d getting connector %d state\n",
  1608. ret, DRMID(conn));
  1609. return ret;
  1610. }
  1611. ret = sde_connector_helper_reset_custom_properties(conn,
  1612. conn_state);
  1613. if (ret) {
  1614. SDE_ERROR("error %d resetting connector props %d\n",
  1615. ret, DRMID(conn));
  1616. return ret;
  1617. }
  1618. }
  1619. drm_connector_list_iter_end(&conn_iter);
  1620. return ret;
  1621. }
  1622. static void sde_kms_lastclose(struct msm_kms *kms)
  1623. {
  1624. struct sde_kms *sde_kms;
  1625. struct drm_device *dev;
  1626. struct drm_atomic_state *state;
  1627. struct drm_modeset_acquire_ctx ctx;
  1628. int ret;
  1629. if (!kms) {
  1630. SDE_ERROR("invalid argument\n");
  1631. return;
  1632. }
  1633. sde_kms = to_sde_kms(kms);
  1634. dev = sde_kms->dev;
  1635. drm_modeset_acquire_init(&ctx, 0);
  1636. state = drm_atomic_state_alloc(dev);
  1637. if (!state) {
  1638. ret = -ENOMEM;
  1639. goto out_ctx;
  1640. }
  1641. state->acquire_ctx = &ctx;
  1642. retry:
  1643. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1644. if (ret)
  1645. goto out_state;
  1646. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1647. if (ret)
  1648. goto out_state;
  1649. ret = drm_atomic_commit(state);
  1650. out_state:
  1651. if (ret == -EDEADLK)
  1652. goto backoff;
  1653. drm_atomic_state_put(state);
  1654. out_ctx:
  1655. drm_modeset_drop_locks(&ctx);
  1656. drm_modeset_acquire_fini(&ctx);
  1657. if (ret)
  1658. SDE_ERROR("kms lastclose failed: %d\n", ret);
  1659. return;
  1660. backoff:
  1661. drm_atomic_state_clear(state);
  1662. drm_modeset_backoff(&ctx);
  1663. goto retry;
  1664. }
  1665. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  1666. struct drm_atomic_state *state)
  1667. {
  1668. struct sde_kms *sde_kms;
  1669. struct drm_device *dev;
  1670. struct drm_crtc *crtc;
  1671. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  1672. struct drm_crtc_state *crtc_state;
  1673. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  1674. bool sec_session = false, global_sec_session = false;
  1675. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  1676. int i;
  1677. if (!kms || !state) {
  1678. return -EINVAL;
  1679. SDE_ERROR("invalid arguments\n");
  1680. }
  1681. sde_kms = to_sde_kms(kms);
  1682. dev = sde_kms->dev;
  1683. /* iterate state object for active secure/non-secure crtc */
  1684. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  1685. if (!crtc_state->active)
  1686. continue;
  1687. active_crtc_cnt++;
  1688. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  1689. &fb_sec, &fb_sec_dir);
  1690. if (fb_sec_dir)
  1691. sec_session = true;
  1692. cur_crtc = crtc;
  1693. }
  1694. /* iterate global list for active and secure/non-secure crtc */
  1695. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1696. if (!crtc->state->active)
  1697. continue;
  1698. global_active_crtc_cnt++;
  1699. /* update only when crtc is not the same as current crtc */
  1700. if (crtc != cur_crtc) {
  1701. fb_ns = fb_sec = fb_sec_dir = 0;
  1702. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  1703. &fb_sec, &fb_sec_dir);
  1704. if (fb_sec_dir)
  1705. global_sec_session = true;
  1706. global_crtc = crtc;
  1707. }
  1708. }
  1709. if (!global_sec_session && !sec_session)
  1710. return 0;
  1711. /*
  1712. * - fail crtc commit, if secure-camera/secure-ui session is
  1713. * in-progress in any other display
  1714. * - fail secure-camera/secure-ui crtc commit, if any other display
  1715. * session is in-progress
  1716. */
  1717. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  1718. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  1719. SDE_ERROR(
  1720. "crtc%d secure check failed global_active:%d active:%d\n",
  1721. cur_crtc ? cur_crtc->base.id : -1,
  1722. global_active_crtc_cnt, active_crtc_cnt);
  1723. return -EPERM;
  1724. /*
  1725. * As only one crtc is allowed during secure session, the crtc
  1726. * in this commit should match with the global crtc
  1727. */
  1728. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  1729. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  1730. cur_crtc->base.id, sec_session,
  1731. global_crtc->base.id, global_sec_session);
  1732. return -EPERM;
  1733. }
  1734. return 0;
  1735. }
  1736. static int sde_kms_atomic_check(struct msm_kms *kms,
  1737. struct drm_atomic_state *state)
  1738. {
  1739. struct sde_kms *sde_kms;
  1740. struct drm_device *dev;
  1741. int ret;
  1742. if (!kms || !state)
  1743. return -EINVAL;
  1744. sde_kms = to_sde_kms(kms);
  1745. dev = sde_kms->dev;
  1746. SDE_ATRACE_BEGIN("atomic_check");
  1747. if (sde_kms_is_suspend_blocked(dev)) {
  1748. SDE_DEBUG("suspended, skip atomic_check\n");
  1749. ret = -EBUSY;
  1750. goto end;
  1751. }
  1752. ret = drm_atomic_helper_check(dev, state);
  1753. if (ret)
  1754. goto end;
  1755. /*
  1756. * Check if any secure transition(moving CRTC between secure and
  1757. * non-secure state and vice-versa) is allowed or not. when moving
  1758. * to secure state, planes with fb_mode set to dir_translated only can
  1759. * be staged on the CRTC, and only one CRTC can be active during
  1760. * Secure state
  1761. */
  1762. ret = sde_kms_check_secure_transition(kms, state);
  1763. end:
  1764. SDE_ATRACE_END("atomic_check");
  1765. return ret;
  1766. }
  1767. static struct msm_gem_address_space*
  1768. _sde_kms_get_address_space(struct msm_kms *kms,
  1769. unsigned int domain)
  1770. {
  1771. struct sde_kms *sde_kms;
  1772. if (!kms) {
  1773. SDE_ERROR("invalid kms\n");
  1774. return NULL;
  1775. }
  1776. sde_kms = to_sde_kms(kms);
  1777. if (!sde_kms) {
  1778. SDE_ERROR("invalid sde_kms\n");
  1779. return NULL;
  1780. }
  1781. if (domain >= MSM_SMMU_DOMAIN_MAX)
  1782. return NULL;
  1783. return (sde_kms->aspace[domain] &&
  1784. sde_kms->aspace[domain]->domain_attached) ?
  1785. sde_kms->aspace[domain] : NULL;
  1786. }
  1787. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  1788. unsigned int domain)
  1789. {
  1790. struct msm_gem_address_space *aspace =
  1791. _sde_kms_get_address_space(kms, domain);
  1792. return (aspace && aspace->domain_attached) ?
  1793. msm_gem_get_aspace_device(aspace) : NULL;
  1794. }
  1795. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  1796. {
  1797. struct drm_device *dev = NULL;
  1798. struct sde_kms *sde_kms = NULL;
  1799. struct drm_connector *connector = NULL;
  1800. struct drm_connector_list_iter conn_iter;
  1801. struct sde_connector *sde_conn = NULL;
  1802. if (!kms) {
  1803. SDE_ERROR("invalid kms\n");
  1804. return;
  1805. }
  1806. sde_kms = to_sde_kms(kms);
  1807. dev = sde_kms->dev;
  1808. if (!dev) {
  1809. SDE_ERROR("invalid device\n");
  1810. return;
  1811. }
  1812. if (!dev->mode_config.poll_enabled)
  1813. return;
  1814. mutex_lock(&dev->mode_config.mutex);
  1815. drm_connector_list_iter_begin(dev, &conn_iter);
  1816. drm_for_each_connector_iter(connector, &conn_iter) {
  1817. /* Only handle HPD capable connectors. */
  1818. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  1819. continue;
  1820. sde_conn = to_sde_connector(connector);
  1821. if (sde_conn->ops.post_open)
  1822. sde_conn->ops.post_open(&sde_conn->base,
  1823. sde_conn->display);
  1824. }
  1825. drm_connector_list_iter_end(&conn_iter);
  1826. mutex_unlock(&dev->mode_config.mutex);
  1827. }
  1828. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  1829. struct sde_splash_display *splash_display,
  1830. struct drm_crtc *crtc)
  1831. {
  1832. struct msm_drm_private *priv;
  1833. struct drm_plane *plane;
  1834. struct sde_splash_mem *splash;
  1835. enum sde_sspp plane_id;
  1836. bool is_virtual;
  1837. int i, j;
  1838. if (!sde_kms || !splash_display || !crtc) {
  1839. SDE_ERROR("invalid input args\n");
  1840. return -EINVAL;
  1841. }
  1842. priv = sde_kms->dev->dev_private;
  1843. for (i = 0; i < priv->num_planes; i++) {
  1844. plane = priv->planes[i];
  1845. plane_id = sde_plane_pipe(plane);
  1846. is_virtual = is_sde_plane_virtual(plane);
  1847. splash = splash_display->splash;
  1848. for (j = 0; j < splash_display->pipe_cnt; j++) {
  1849. if ((plane_id != splash_display->pipes[j].sspp) ||
  1850. (splash_display->pipes[j].is_virtual
  1851. != is_virtual))
  1852. continue;
  1853. if (splash && sde_plane_validate_src_addr(plane,
  1854. splash->splash_buf_base,
  1855. splash->splash_buf_size)) {
  1856. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  1857. plane_id, crtc->base.id);
  1858. }
  1859. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  1860. crtc->base.id, plane_id, is_virtual);
  1861. }
  1862. }
  1863. return 0;
  1864. }
  1865. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  1866. {
  1867. void *display;
  1868. struct dsi_display *dsi_display;
  1869. struct msm_display_info info;
  1870. struct drm_encoder *encoder = NULL;
  1871. struct drm_crtc *crtc = NULL;
  1872. int i, rc = 0;
  1873. struct drm_display_mode *drm_mode = NULL;
  1874. struct drm_device *dev;
  1875. struct msm_drm_private *priv;
  1876. struct sde_kms *sde_kms;
  1877. struct drm_connector_list_iter conn_iter;
  1878. struct drm_connector *connector = NULL;
  1879. struct sde_connector *sde_conn = NULL;
  1880. struct sde_splash_display *splash_display;
  1881. if (!kms) {
  1882. SDE_ERROR("invalid kms\n");
  1883. return -EINVAL;
  1884. }
  1885. sde_kms = to_sde_kms(kms);
  1886. dev = sde_kms->dev;
  1887. if (!dev) {
  1888. SDE_ERROR("invalid device\n");
  1889. return -EINVAL;
  1890. }
  1891. if (!sde_kms->splash_data.num_splash_regions ||
  1892. !sde_kms->splash_data.num_splash_displays) {
  1893. DRM_INFO("cont_splash feature not enabled\n");
  1894. return rc;
  1895. }
  1896. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  1897. sde_kms->splash_data.num_splash_displays,
  1898. sde_kms->dsi_display_count);
  1899. /* dsi */
  1900. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  1901. display = sde_kms->dsi_displays[i];
  1902. dsi_display = (struct dsi_display *)display;
  1903. splash_display = &sde_kms->splash_data.splash_display[i];
  1904. if (!splash_display->cont_splash_enabled) {
  1905. SDE_DEBUG("display->name = %s splash not enabled\n",
  1906. dsi_display->name);
  1907. continue;
  1908. }
  1909. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  1910. if (dsi_display->bridge->base.encoder) {
  1911. encoder = dsi_display->bridge->base.encoder;
  1912. SDE_DEBUG("encoder name = %s\n", encoder->name);
  1913. }
  1914. memset(&info, 0x0, sizeof(info));
  1915. rc = dsi_display_get_info(NULL, &info, display);
  1916. if (rc) {
  1917. SDE_ERROR("dsi get_info %d failed\n", i);
  1918. encoder = NULL;
  1919. continue;
  1920. }
  1921. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  1922. ((info.is_connected) ? "true" : "false"),
  1923. info.display_type);
  1924. if (!encoder) {
  1925. SDE_ERROR("encoder not initialized\n");
  1926. return -EINVAL;
  1927. }
  1928. priv = sde_kms->dev->dev_private;
  1929. encoder->crtc = priv->crtcs[i];
  1930. crtc = encoder->crtc;
  1931. splash_display->encoder = encoder;
  1932. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  1933. i, crtc->base.id, encoder->base.id);
  1934. mutex_lock(&dev->mode_config.mutex);
  1935. drm_connector_list_iter_begin(dev, &conn_iter);
  1936. drm_for_each_connector_iter(connector, &conn_iter) {
  1937. /**
  1938. * SDE_KMS doesn't attach more than one encoder to
  1939. * a DSI connector. So it is safe to check only with
  1940. * the first encoder entry. Revisit this logic if we
  1941. * ever have to support continuous splash for
  1942. * external displays in MST configuration.
  1943. */
  1944. if (connector->encoder_ids[0] == encoder->base.id)
  1945. break;
  1946. }
  1947. drm_connector_list_iter_end(&conn_iter);
  1948. if (!connector) {
  1949. SDE_ERROR("connector not initialized\n");
  1950. mutex_unlock(&dev->mode_config.mutex);
  1951. return -EINVAL;
  1952. }
  1953. if (connector->funcs->fill_modes) {
  1954. connector->funcs->fill_modes(connector,
  1955. dev->mode_config.max_width,
  1956. dev->mode_config.max_height);
  1957. } else {
  1958. SDE_ERROR("fill_modes api not defined\n");
  1959. mutex_unlock(&dev->mode_config.mutex);
  1960. return -EINVAL;
  1961. }
  1962. mutex_unlock(&dev->mode_config.mutex);
  1963. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  1964. /* currently consider modes[0] as the preferred mode */
  1965. drm_mode = list_first_entry(&connector->modes,
  1966. struct drm_display_mode, head);
  1967. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  1968. drm_mode->name, drm_mode->type,
  1969. drm_mode->flags);
  1970. /* Update CRTC drm structure */
  1971. crtc->state->active = true;
  1972. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  1973. if (rc) {
  1974. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  1975. return rc;
  1976. }
  1977. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  1978. drm_mode_copy(&crtc->mode, drm_mode);
  1979. /* Update encoder structure */
  1980. sde_encoder_update_caps_for_cont_splash(encoder,
  1981. splash_display, true);
  1982. sde_crtc_update_cont_splash_settings(crtc);
  1983. sde_conn = to_sde_connector(connector);
  1984. if (sde_conn && sde_conn->ops.cont_splash_config)
  1985. sde_conn->ops.cont_splash_config(sde_conn->display);
  1986. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  1987. splash_display, crtc);
  1988. if (rc) {
  1989. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  1990. return rc;
  1991. }
  1992. }
  1993. return rc;
  1994. }
  1995. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  1996. {
  1997. struct sde_kms *sde_kms;
  1998. if (!kms) {
  1999. SDE_ERROR("invalid kms\n");
  2000. return false;
  2001. }
  2002. sde_kms = to_sde_kms(kms);
  2003. return sde_kms->splash_data.num_splash_displays;
  2004. }
  2005. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2006. const struct drm_display_mode *mode,
  2007. const struct msm_resource_caps_info *res, u32 *num_lm)
  2008. {
  2009. struct sde_kms *sde_kms;
  2010. s64 mode_clock_hz = 0;
  2011. s64 max_mdp_clock_hz = 0;
  2012. s64 mdp_fudge_factor = 0;
  2013. s64 temp = 0;
  2014. s64 htotal_fp = 0;
  2015. s64 vtotal_fp = 0;
  2016. s64 vrefresh_fp = 0;
  2017. if (!num_lm) {
  2018. SDE_ERROR("invalid num_lm pointer\n");
  2019. return -EINVAL;
  2020. }
  2021. *num_lm = 1;
  2022. if (!kms || !mode || !res) {
  2023. SDE_ERROR("invalid input args\n");
  2024. return -EINVAL;
  2025. }
  2026. sde_kms = to_sde_kms(kms);
  2027. max_mdp_clock_hz = drm_fixp_from_fraction(
  2028. sde_kms->perf.max_core_clk_rate, 1);
  2029. mdp_fudge_factor = drm_fixp_from_fraction(105, 100); /* 1.05 */
  2030. htotal_fp = drm_fixp_from_fraction(mode->htotal, 1);
  2031. vtotal_fp = drm_fixp_from_fraction(mode->vtotal, 1);
  2032. vrefresh_fp = drm_fixp_from_fraction(mode->vrefresh, 1);
  2033. temp = drm_fixp_mul(htotal_fp, vtotal_fp);
  2034. temp = drm_fixp_mul(temp, vrefresh_fp);
  2035. mode_clock_hz = drm_fixp_mul(temp, mdp_fudge_factor);
  2036. if (mode_clock_hz > max_mdp_clock_hz ||
  2037. mode->hdisplay > res->max_mixer_width) {
  2038. *num_lm = 2;
  2039. if ((mode_clock_hz >> 1) > max_mdp_clock_hz) {
  2040. SDE_DEBUG("[%s] clock %d exceeds max_mdp_clk %d\n",
  2041. mode->name, mode_clock_hz,
  2042. max_mdp_clock_hz);
  2043. return -EINVAL;
  2044. }
  2045. }
  2046. SDE_DEBUG("[%s] h=%d, v=%d, fps=%d, max_mdp_clk_hz=%llu, num_lm=%d\n",
  2047. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2048. sde_kms->perf.max_core_clk_rate, *num_lm);
  2049. return 0;
  2050. }
  2051. static void _sde_kms_null_commit(struct drm_device *dev,
  2052. struct drm_encoder *enc)
  2053. {
  2054. struct drm_modeset_acquire_ctx ctx;
  2055. struct drm_connector *conn = NULL;
  2056. struct drm_connector *tmp_conn = NULL;
  2057. struct drm_connector_list_iter conn_iter;
  2058. struct drm_atomic_state *state = NULL;
  2059. struct drm_crtc_state *crtc_state = NULL;
  2060. struct drm_connector_state *conn_state = NULL;
  2061. int retry_cnt = 0;
  2062. int ret = 0;
  2063. drm_modeset_acquire_init(&ctx, 0);
  2064. retry:
  2065. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2066. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2067. drm_modeset_backoff(&ctx);
  2068. retry_cnt++;
  2069. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2070. goto retry;
  2071. } else if (WARN_ON(ret)) {
  2072. goto end;
  2073. }
  2074. state = drm_atomic_state_alloc(dev);
  2075. if (!state) {
  2076. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2077. goto end;
  2078. }
  2079. state->acquire_ctx = &ctx;
  2080. drm_connector_list_iter_begin(dev, &conn_iter);
  2081. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2082. if (enc == tmp_conn->state->best_encoder) {
  2083. conn = tmp_conn;
  2084. break;
  2085. }
  2086. }
  2087. drm_connector_list_iter_end(&conn_iter);
  2088. if (!conn) {
  2089. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2090. goto end;
  2091. }
  2092. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2093. conn_state = drm_atomic_get_connector_state(state, conn);
  2094. if (IS_ERR(conn_state)) {
  2095. SDE_ERROR("error %d getting connector %d state\n",
  2096. ret, DRMID(conn));
  2097. goto end;
  2098. }
  2099. crtc_state->active = true;
  2100. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2101. if (ret)
  2102. SDE_ERROR("error %d setting the crtc\n", ret);
  2103. ret = drm_atomic_commit(state);
  2104. if (ret)
  2105. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2106. end:
  2107. if (state)
  2108. drm_atomic_state_put(state);
  2109. drm_modeset_drop_locks(&ctx);
  2110. drm_modeset_acquire_fini(&ctx);
  2111. }
  2112. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2113. struct device *dev)
  2114. {
  2115. int i, ret, crtc_id = 0;
  2116. struct drm_device *ddev = dev_get_drvdata(dev);
  2117. struct drm_connector *conn;
  2118. struct drm_connector_list_iter conn_iter;
  2119. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2120. drm_connector_list_iter_begin(ddev, &conn_iter);
  2121. drm_for_each_connector_iter(conn, &conn_iter) {
  2122. uint64_t lp;
  2123. lp = sde_connector_get_lp(conn);
  2124. if (lp != SDE_MODE_DPMS_LP2)
  2125. continue;
  2126. if (sde_encoder_in_clone_mode(conn->encoder))
  2127. continue;
  2128. ret = sde_encoder_wait_for_event(conn->encoder,
  2129. MSM_ENC_TX_COMPLETE);
  2130. if (ret && ret != -EWOULDBLOCK) {
  2131. SDE_ERROR(
  2132. "[conn: %d] wait for commit done returned %d\n",
  2133. conn->base.id, ret);
  2134. } else if (!ret) {
  2135. crtc_id = drm_crtc_index(conn->state->crtc);
  2136. if (priv->event_thread[crtc_id].thread)
  2137. kthread_flush_worker(
  2138. &priv->event_thread[crtc_id].worker);
  2139. sde_encoder_idle_request(conn->encoder);
  2140. }
  2141. }
  2142. drm_connector_list_iter_end(&conn_iter);
  2143. for (i = 0; i < priv->num_crtcs; i++) {
  2144. if (priv->disp_thread[i].thread)
  2145. kthread_flush_worker(
  2146. &priv->disp_thread[i].worker);
  2147. if (priv->event_thread[i].thread)
  2148. kthread_flush_worker(
  2149. &priv->event_thread[i].worker);
  2150. }
  2151. kthread_flush_worker(&priv->pp_event_worker);
  2152. }
  2153. static int sde_kms_pm_suspend(struct device *dev)
  2154. {
  2155. struct drm_device *ddev;
  2156. struct drm_modeset_acquire_ctx ctx;
  2157. struct drm_connector *conn;
  2158. struct drm_encoder *enc;
  2159. struct drm_connector_list_iter conn_iter;
  2160. struct drm_atomic_state *state = NULL;
  2161. struct sde_kms *sde_kms;
  2162. int ret = 0, num_crtcs = 0;
  2163. if (!dev)
  2164. return -EINVAL;
  2165. ddev = dev_get_drvdata(dev);
  2166. if (!ddev || !ddev_to_msm_kms(ddev))
  2167. return -EINVAL;
  2168. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2169. SDE_EVT32(0);
  2170. /* disable hot-plug polling */
  2171. drm_kms_helper_poll_disable(ddev);
  2172. /* if a display stuck in CS trigger a null commit to complete handoff */
  2173. drm_for_each_encoder(enc, ddev) {
  2174. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2175. _sde_kms_null_commit(ddev, enc);
  2176. }
  2177. /* acquire modeset lock(s) */
  2178. drm_modeset_acquire_init(&ctx, 0);
  2179. retry:
  2180. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2181. if (ret)
  2182. goto unlock;
  2183. /* save current state for resume */
  2184. if (sde_kms->suspend_state)
  2185. drm_atomic_state_put(sde_kms->suspend_state);
  2186. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2187. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2188. ret = PTR_ERR(sde_kms->suspend_state);
  2189. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2190. sde_kms->suspend_state = NULL;
  2191. goto unlock;
  2192. }
  2193. /* create atomic state to disable all CRTCs */
  2194. state = drm_atomic_state_alloc(ddev);
  2195. if (!state) {
  2196. ret = -ENOMEM;
  2197. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2198. goto unlock;
  2199. }
  2200. state->acquire_ctx = &ctx;
  2201. drm_connector_list_iter_begin(ddev, &conn_iter);
  2202. drm_for_each_connector_iter(conn, &conn_iter) {
  2203. struct drm_crtc_state *crtc_state;
  2204. uint64_t lp;
  2205. if (!conn->state || !conn->state->crtc ||
  2206. conn->dpms != DRM_MODE_DPMS_ON ||
  2207. sde_encoder_in_clone_mode(conn->encoder))
  2208. continue;
  2209. lp = sde_connector_get_lp(conn);
  2210. if (lp == SDE_MODE_DPMS_LP1) {
  2211. /* transition LP1->LP2 on pm suspend */
  2212. ret = sde_connector_set_property_for_commit(conn, state,
  2213. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2214. if (ret) {
  2215. DRM_ERROR("failed to set lp2 for conn %d\n",
  2216. conn->base.id);
  2217. drm_connector_list_iter_end(&conn_iter);
  2218. goto unlock;
  2219. }
  2220. }
  2221. if (lp != SDE_MODE_DPMS_LP2) {
  2222. /* force CRTC to be inactive */
  2223. crtc_state = drm_atomic_get_crtc_state(state,
  2224. conn->state->crtc);
  2225. if (IS_ERR_OR_NULL(crtc_state)) {
  2226. DRM_ERROR("failed to get crtc %d state\n",
  2227. conn->state->crtc->base.id);
  2228. drm_connector_list_iter_end(&conn_iter);
  2229. goto unlock;
  2230. }
  2231. if (lp != SDE_MODE_DPMS_LP1)
  2232. crtc_state->active = false;
  2233. ++num_crtcs;
  2234. }
  2235. }
  2236. drm_connector_list_iter_end(&conn_iter);
  2237. /* check for nothing to do */
  2238. if (num_crtcs == 0) {
  2239. DRM_DEBUG("all crtcs are already in the off state\n");
  2240. sde_kms->suspend_block = true;
  2241. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2242. goto unlock;
  2243. }
  2244. /* commit the "disable all" state */
  2245. ret = drm_atomic_commit(state);
  2246. if (ret < 0) {
  2247. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2248. goto unlock;
  2249. }
  2250. sde_kms->suspend_block = true;
  2251. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2252. unlock:
  2253. if (state) {
  2254. drm_atomic_state_put(state);
  2255. state = NULL;
  2256. }
  2257. if (ret == -EDEADLK) {
  2258. drm_modeset_backoff(&ctx);
  2259. goto retry;
  2260. }
  2261. drm_modeset_drop_locks(&ctx);
  2262. drm_modeset_acquire_fini(&ctx);
  2263. /*
  2264. * pm runtime driver avoids multiple runtime_suspend API call by
  2265. * checking runtime_status. However, this call helps when there is a
  2266. * race condition between pm_suspend call and doze_suspend/power_off
  2267. * commit. It removes the extra vote from suspend and adds it back
  2268. * later to allow power collapse during pm_suspend call
  2269. */
  2270. pm_runtime_put_sync(dev);
  2271. pm_runtime_get_noresume(dev);
  2272. return ret;
  2273. }
  2274. static int sde_kms_pm_resume(struct device *dev)
  2275. {
  2276. struct drm_device *ddev;
  2277. struct sde_kms *sde_kms;
  2278. struct drm_modeset_acquire_ctx ctx;
  2279. int ret, i;
  2280. if (!dev)
  2281. return -EINVAL;
  2282. ddev = dev_get_drvdata(dev);
  2283. if (!ddev || !ddev_to_msm_kms(ddev))
  2284. return -EINVAL;
  2285. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2286. SDE_EVT32(sde_kms->suspend_state != NULL);
  2287. drm_mode_config_reset(ddev);
  2288. drm_modeset_acquire_init(&ctx, 0);
  2289. retry:
  2290. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2291. if (ret == -EDEADLK) {
  2292. drm_modeset_backoff(&ctx);
  2293. goto retry;
  2294. } else if (WARN_ON(ret)) {
  2295. goto end;
  2296. }
  2297. sde_kms->suspend_block = false;
  2298. if (sde_kms->suspend_state) {
  2299. sde_kms->suspend_state->acquire_ctx = &ctx;
  2300. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2301. ret = drm_atomic_helper_commit_duplicated_state(
  2302. sde_kms->suspend_state, &ctx);
  2303. if (ret != -EDEADLK)
  2304. break;
  2305. drm_modeset_backoff(&ctx);
  2306. }
  2307. if (ret < 0)
  2308. DRM_ERROR("failed to restore state, %d\n", ret);
  2309. drm_atomic_state_put(sde_kms->suspend_state);
  2310. sde_kms->suspend_state = NULL;
  2311. }
  2312. end:
  2313. drm_modeset_drop_locks(&ctx);
  2314. drm_modeset_acquire_fini(&ctx);
  2315. /* enable hot-plug polling */
  2316. drm_kms_helper_poll_enable(ddev);
  2317. return 0;
  2318. }
  2319. static const struct msm_kms_funcs kms_funcs = {
  2320. .hw_init = sde_kms_hw_init,
  2321. .postinit = sde_kms_postinit,
  2322. .irq_preinstall = sde_irq_preinstall,
  2323. .irq_postinstall = sde_irq_postinstall,
  2324. .irq_uninstall = sde_irq_uninstall,
  2325. .irq = sde_irq,
  2326. .lastclose = sde_kms_lastclose,
  2327. .prepare_fence = sde_kms_prepare_fence,
  2328. .prepare_commit = sde_kms_prepare_commit,
  2329. .commit = sde_kms_commit,
  2330. .complete_commit = sde_kms_complete_commit,
  2331. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2332. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2333. .enable_vblank = sde_kms_enable_vblank,
  2334. .disable_vblank = sde_kms_disable_vblank,
  2335. .check_modified_format = sde_format_check_modified_format,
  2336. .atomic_check = sde_kms_atomic_check,
  2337. .get_format = sde_get_msm_format,
  2338. .round_pixclk = sde_kms_round_pixclk,
  2339. .pm_suspend = sde_kms_pm_suspend,
  2340. .pm_resume = sde_kms_pm_resume,
  2341. .destroy = sde_kms_destroy,
  2342. .cont_splash_config = sde_kms_cont_splash_config,
  2343. .register_events = _sde_kms_register_events,
  2344. .get_address_space = _sde_kms_get_address_space,
  2345. .get_address_space_device = _sde_kms_get_address_space_device,
  2346. .postopen = _sde_kms_post_open,
  2347. .check_for_splash = sde_kms_check_for_splash,
  2348. .get_mixer_count = sde_kms_get_mixer_count,
  2349. };
  2350. /* the caller api needs to turn on clock before calling it */
  2351. static inline void _sde_kms_core_hw_rev_init(struct sde_kms *sde_kms)
  2352. {
  2353. sde_kms->core_rev = readl_relaxed(sde_kms->mmio + 0x0);
  2354. }
  2355. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2356. {
  2357. int i;
  2358. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2359. if (!sde_kms->aspace[i])
  2360. continue;
  2361. msm_gem_address_space_put(sde_kms->aspace[i]);
  2362. sde_kms->aspace[i] = NULL;
  2363. }
  2364. return 0;
  2365. }
  2366. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2367. {
  2368. struct msm_mmu *mmu;
  2369. int i, ret;
  2370. int early_map = 0;
  2371. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  2372. return -EINVAL;
  2373. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2374. struct msm_gem_address_space *aspace;
  2375. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2376. if (IS_ERR(mmu)) {
  2377. ret = PTR_ERR(mmu);
  2378. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2379. i, ret);
  2380. continue;
  2381. }
  2382. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2383. mmu, "sde");
  2384. if (IS_ERR(aspace)) {
  2385. ret = PTR_ERR(aspace);
  2386. goto fail;
  2387. }
  2388. sde_kms->aspace[i] = aspace;
  2389. aspace->domain_attached = true;
  2390. /* Mapping splash memory block */
  2391. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2392. sde_kms->splash_data.num_splash_regions) {
  2393. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2394. if (ret) {
  2395. SDE_ERROR("failed to map ret:%d\n", ret);
  2396. goto fail;
  2397. }
  2398. }
  2399. /*
  2400. * disable early-map which would have been enabled during
  2401. * bootup by smmu through the device-tree hint for cont-spash
  2402. */
  2403. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2404. &early_map);
  2405. if (ret) {
  2406. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2407. ret, early_map);
  2408. goto early_map_fail;
  2409. }
  2410. }
  2411. return 0;
  2412. early_map_fail:
  2413. _sde_kms_unmap_all_splash_regions(sde_kms);
  2414. fail:
  2415. mmu->funcs->destroy(mmu);
  2416. _sde_kms_mmu_destroy(sde_kms);
  2417. return ret;
  2418. }
  2419. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2420. {
  2421. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2422. return;
  2423. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2424. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2425. sde_kms->catalog);
  2426. if (sde_kms->sid)
  2427. sde_hw_sid_rotator_set(sde_kms->hw_sid);
  2428. }
  2429. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2430. {
  2431. struct sde_vbif_set_qos_params qos_params;
  2432. struct sde_mdss_cfg *catalog;
  2433. if (!sde_kms->catalog)
  2434. return;
  2435. catalog = sde_kms->catalog;
  2436. memset(&qos_params, 0, sizeof(qos_params));
  2437. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2438. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2439. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2440. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2441. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2442. }
  2443. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  2444. {
  2445. struct sde_hw_uidle *uidle;
  2446. if (!sde_kms) {
  2447. SDE_ERROR("invalid kms\n");
  2448. return -EINVAL;
  2449. }
  2450. uidle = sde_kms->hw_uidle;
  2451. if (uidle && uidle->ops.active_override_enable)
  2452. uidle->ops.active_override_enable(uidle, enable);
  2453. return 0;
  2454. }
  2455. static void sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  2456. {
  2457. struct device *cpu_dev;
  2458. int cpu = 0;
  2459. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2460. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2461. return;
  2462. }
  2463. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2464. cpu_dev = get_cpu_device(cpu);
  2465. if (!cpu_dev) {
  2466. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2467. cpu);
  2468. continue;
  2469. }
  2470. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2471. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  2472. sde_kms->catalog->perf.cpu_dma_latency);
  2473. else
  2474. dev_pm_qos_add_request(cpu_dev,
  2475. &sde_kms->pm_qos_irq_req[cpu],
  2476. DEV_PM_QOS_RESUME_LATENCY,
  2477. sde_kms->catalog->perf.cpu_dma_latency);
  2478. }
  2479. }
  2480. static void sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  2481. {
  2482. struct device *cpu_dev;
  2483. int cpu = 0;
  2484. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2485. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2486. return;
  2487. }
  2488. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2489. cpu_dev = get_cpu_device(cpu);
  2490. if (!cpu_dev) {
  2491. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2492. cpu);
  2493. continue;
  2494. }
  2495. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2496. dev_pm_qos_remove_request(
  2497. &sde_kms->pm_qos_irq_req[cpu]);
  2498. }
  2499. }
  2500. static void sde_kms_irq_affinity_notify(
  2501. struct irq_affinity_notify *affinity_notify,
  2502. const cpumask_t *mask)
  2503. {
  2504. struct msm_drm_private *priv;
  2505. struct sde_kms *sde_kms = container_of(affinity_notify,
  2506. struct sde_kms, affinity_notify);
  2507. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  2508. return;
  2509. priv = sde_kms->dev->dev_private;
  2510. mutex_lock(&priv->phandle.phandle_lock);
  2511. // save irq cpu mask
  2512. sde_kms->irq_cpu_mask = *mask;
  2513. // request vote with updated irq cpu mask
  2514. if (sde_kms->irq_enabled)
  2515. sde_kms_update_pm_qos_irq_request(sde_kms);
  2516. mutex_unlock(&priv->phandle.phandle_lock);
  2517. }
  2518. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  2519. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  2520. {
  2521. struct sde_kms *sde_kms = usr;
  2522. struct msm_kms *msm_kms;
  2523. msm_kms = &sde_kms->base;
  2524. if (!sde_kms)
  2525. return;
  2526. SDE_DEBUG("event_type:%d\n", event_type);
  2527. SDE_EVT32_VERBOSE(event_type);
  2528. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  2529. sde_irq_update(msm_kms, true);
  2530. if (sde_kms->splash_data.num_splash_displays)
  2531. return;
  2532. sde_vbif_init_memtypes(sde_kms);
  2533. sde_kms_init_shared_hw(sde_kms);
  2534. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  2535. sde_kms->first_kickoff = true;
  2536. sde_kms_update_pm_qos_irq_request(sde_kms);
  2537. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  2538. sde_kms_remove_pm_qos_irq_request(sde_kms);
  2539. sde_irq_update(msm_kms, false);
  2540. sde_kms->first_kickoff = false;
  2541. _sde_kms_active_override(sde_kms, true);
  2542. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  2543. sde_vbif_axi_halt_request(sde_kms);
  2544. }
  2545. }
  2546. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  2547. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  2548. {
  2549. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2550. int rc = -EINVAL;
  2551. SDE_DEBUG("\n");
  2552. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2553. if (rc > 0)
  2554. rc = 0;
  2555. SDE_EVT32(rc, genpd->device_count);
  2556. return rc;
  2557. }
  2558. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  2559. {
  2560. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2561. SDE_DEBUG("\n");
  2562. pm_runtime_put_sync(sde_kms->dev->dev);
  2563. SDE_EVT32(genpd->device_count);
  2564. return 0;
  2565. }
  2566. static int _sde_kms_get_splash_data(struct sde_splash_data *data)
  2567. {
  2568. int i = 0;
  2569. int ret = 0;
  2570. struct device_node *parent, *node, *node1;
  2571. struct resource r, r1;
  2572. const char *node_name = "splash_region";
  2573. struct sde_splash_mem *mem;
  2574. bool share_splash_mem = false;
  2575. int num_displays, num_regions;
  2576. struct sde_splash_display *splash_display;
  2577. if (!data)
  2578. return -EINVAL;
  2579. memset(data, 0, sizeof(*data));
  2580. parent = of_find_node_by_path("/reserved-memory");
  2581. if (!parent) {
  2582. SDE_ERROR("failed to find reserved-memory node\n");
  2583. return -EINVAL;
  2584. }
  2585. node = of_find_node_by_name(parent, node_name);
  2586. if (!node) {
  2587. SDE_DEBUG("failed to find node %s\n", node_name);
  2588. return -EINVAL;
  2589. }
  2590. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  2591. if (!node1)
  2592. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  2593. /**
  2594. * Support sharing a single splash memory for all the built in displays
  2595. * and also independent splash region per displays. Incase of
  2596. * independent splash region for each connected display, dtsi node of
  2597. * cont_splash_region should be collection of all memory regions
  2598. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  2599. */
  2600. num_displays = dsi_display_get_num_of_displays();
  2601. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  2602. data->num_splash_displays = num_displays;
  2603. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  2604. if (num_displays > num_regions) {
  2605. share_splash_mem = true;
  2606. pr_info(":%d displays share same splash buf\n", num_displays);
  2607. }
  2608. for (i = 0; i < num_displays; i++) {
  2609. splash_display = &data->splash_display[i];
  2610. if (!i || !share_splash_mem) {
  2611. if (of_address_to_resource(node, i, &r)) {
  2612. SDE_ERROR("invalid data for:%s\n", node_name);
  2613. return -EINVAL;
  2614. }
  2615. mem = &data->splash_mem[i];
  2616. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  2617. SDE_DEBUG("failed to find ramdump memory\n");
  2618. mem->ramdump_base = 0;
  2619. mem->ramdump_size = 0;
  2620. } else {
  2621. mem->ramdump_base = (unsigned long)r1.start;
  2622. mem->ramdump_size = (r1.end - r1.start) + 1;
  2623. }
  2624. mem->splash_buf_base = (unsigned long)r.start;
  2625. mem->splash_buf_size = (r.end - r.start) + 1;
  2626. mem->ref_cnt = 0;
  2627. splash_display->splash = mem;
  2628. data->num_splash_regions++;
  2629. } else {
  2630. data->splash_display[i].splash = &data->splash_mem[0];
  2631. }
  2632. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  2633. splash_display->splash->splash_buf_base,
  2634. splash_display->splash->splash_buf_size);
  2635. }
  2636. return ret;
  2637. }
  2638. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  2639. struct platform_device *platformdev)
  2640. {
  2641. int rc = -EINVAL;
  2642. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  2643. if (IS_ERR(sde_kms->mmio)) {
  2644. rc = PTR_ERR(sde_kms->mmio);
  2645. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  2646. sde_kms->mmio = NULL;
  2647. goto error;
  2648. }
  2649. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  2650. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  2651. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  2652. sde_kms->mmio_len);
  2653. if (rc)
  2654. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  2655. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  2656. "vbif_phys");
  2657. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  2658. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  2659. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  2660. sde_kms->vbif[VBIF_RT] = NULL;
  2661. goto error;
  2662. }
  2663. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  2664. "vbif_phys");
  2665. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  2666. sde_kms->vbif_len[VBIF_RT]);
  2667. if (rc)
  2668. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  2669. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  2670. "vbif_nrt_phys");
  2671. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  2672. sde_kms->vbif[VBIF_NRT] = NULL;
  2673. SDE_DEBUG("VBIF NRT is not defined");
  2674. } else {
  2675. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  2676. "vbif_nrt_phys");
  2677. rc = sde_dbg_reg_register_base("vbif_nrt",
  2678. sde_kms->vbif[VBIF_NRT],
  2679. sde_kms->vbif_len[VBIF_NRT]);
  2680. if (rc)
  2681. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  2682. rc);
  2683. }
  2684. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  2685. "regdma_phys");
  2686. if (IS_ERR(sde_kms->reg_dma)) {
  2687. sde_kms->reg_dma = NULL;
  2688. SDE_DEBUG("REG_DMA is not defined");
  2689. } else {
  2690. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  2691. "regdma_phys");
  2692. rc = sde_dbg_reg_register_base("reg_dma",
  2693. sde_kms->reg_dma,
  2694. sde_kms->reg_dma_len);
  2695. if (rc)
  2696. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  2697. rc);
  2698. }
  2699. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  2700. "sid_phys");
  2701. if (IS_ERR(sde_kms->sid)) {
  2702. SDE_DEBUG("sid register is not defined: %d\n", rc);
  2703. sde_kms->sid = NULL;
  2704. } else {
  2705. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  2706. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  2707. sde_kms->sid_len);
  2708. if (rc)
  2709. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  2710. }
  2711. error:
  2712. return rc;
  2713. }
  2714. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  2715. struct sde_kms *sde_kms)
  2716. {
  2717. int rc = 0;
  2718. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  2719. sde_kms->genpd.name = dev->unique;
  2720. sde_kms->genpd.power_off = sde_kms_pd_disable;
  2721. sde_kms->genpd.power_on = sde_kms_pd_enable;
  2722. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  2723. if (rc < 0) {
  2724. SDE_ERROR("failed to init genpd provider %s: %d\n",
  2725. sde_kms->genpd.name, rc);
  2726. return rc;
  2727. }
  2728. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  2729. &sde_kms->genpd);
  2730. if (rc < 0) {
  2731. SDE_ERROR("failed to add genpd provider %s: %d\n",
  2732. sde_kms->genpd.name, rc);
  2733. pm_genpd_remove(&sde_kms->genpd);
  2734. return rc;
  2735. }
  2736. sde_kms->genpd_init = true;
  2737. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  2738. }
  2739. return rc;
  2740. }
  2741. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  2742. struct drm_device *dev,
  2743. struct msm_drm_private *priv)
  2744. {
  2745. struct sde_rm *rm = NULL;
  2746. int i, rc = -EINVAL;
  2747. _sde_kms_core_hw_rev_init(sde_kms);
  2748. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  2749. sde_kms->catalog = sde_hw_catalog_init(dev, sde_kms->core_rev);
  2750. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  2751. rc = PTR_ERR(sde_kms->catalog);
  2752. if (!sde_kms->catalog)
  2753. rc = -EINVAL;
  2754. SDE_ERROR("catalog init failed: %d\n", rc);
  2755. sde_kms->catalog = NULL;
  2756. goto power_error;
  2757. }
  2758. /* initialize power domain if defined */
  2759. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  2760. if (rc) {
  2761. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  2762. goto genpd_err;
  2763. }
  2764. rc = _sde_kms_mmu_init(sde_kms);
  2765. if (rc) {
  2766. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  2767. goto power_error;
  2768. }
  2769. /* Initialize reg dma block which is a singleton */
  2770. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  2771. sde_kms->dev);
  2772. if (rc) {
  2773. SDE_ERROR("failed: reg dma init failed\n");
  2774. goto power_error;
  2775. }
  2776. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  2777. rm = &sde_kms->rm;
  2778. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  2779. sde_kms->dev);
  2780. if (rc) {
  2781. SDE_ERROR("rm init failed: %d\n", rc);
  2782. goto power_error;
  2783. }
  2784. sde_kms->rm_init = true;
  2785. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  2786. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  2787. rc = PTR_ERR(sde_kms->hw_intr);
  2788. SDE_ERROR("hw_intr init failed: %d\n", rc);
  2789. sde_kms->hw_intr = NULL;
  2790. goto hw_intr_init_err;
  2791. }
  2792. /*
  2793. * Attempt continuous splash handoff only if reserved
  2794. * splash memory is found & release resources on any error
  2795. * in finding display hw config in splash
  2796. */
  2797. if (sde_kms->splash_data.num_splash_regions) {
  2798. struct sde_splash_display *display;
  2799. int ret, display_count =
  2800. sde_kms->splash_data.num_splash_displays;
  2801. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  2802. &sde_kms->splash_data, sde_kms->catalog);
  2803. for (i = 0; i < display_count; i++) {
  2804. display = &sde_kms->splash_data.splash_display[i];
  2805. /*
  2806. * free splash region on resource init failure and
  2807. * cont-splash disabled case
  2808. */
  2809. if (!display->cont_splash_enabled || ret)
  2810. _sde_kms_free_splash_region(sde_kms, display);
  2811. }
  2812. }
  2813. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  2814. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  2815. rc = PTR_ERR(sde_kms->hw_mdp);
  2816. if (!sde_kms->hw_mdp)
  2817. rc = -EINVAL;
  2818. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  2819. sde_kms->hw_mdp = NULL;
  2820. goto power_error;
  2821. }
  2822. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  2823. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  2824. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  2825. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  2826. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  2827. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  2828. if (!sde_kms->hw_vbif[vbif_idx])
  2829. rc = -EINVAL;
  2830. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  2831. sde_kms->hw_vbif[vbif_idx] = NULL;
  2832. goto power_error;
  2833. }
  2834. }
  2835. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  2836. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  2837. sde_kms->mmio_len, sde_kms->catalog);
  2838. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  2839. rc = PTR_ERR(sde_kms->hw_uidle);
  2840. if (!sde_kms->hw_uidle)
  2841. rc = -EINVAL;
  2842. /* uidle is optional, so do not make it a fatal error */
  2843. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  2844. sde_kms->hw_uidle = NULL;
  2845. rc = 0;
  2846. }
  2847. } else {
  2848. sde_kms->hw_uidle = NULL;
  2849. }
  2850. if (sde_kms->sid) {
  2851. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  2852. sde_kms->sid_len, sde_kms->catalog);
  2853. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  2854. rc = PTR_ERR(sde_kms->hw_sid);
  2855. SDE_ERROR("failed to init sid %ld\n", rc);
  2856. sde_kms->hw_sid = NULL;
  2857. goto power_error;
  2858. }
  2859. }
  2860. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  2861. &priv->phandle, "core_clk");
  2862. if (rc) {
  2863. SDE_ERROR("failed to init perf %d\n", rc);
  2864. goto perf_err;
  2865. }
  2866. /*
  2867. * _sde_kms_drm_obj_init should create the DRM related objects
  2868. * i.e. CRTCs, planes, encoders, connectors and so forth
  2869. */
  2870. rc = _sde_kms_drm_obj_init(sde_kms);
  2871. if (rc) {
  2872. SDE_ERROR("modeset init failed: %d\n", rc);
  2873. goto drm_obj_init_err;
  2874. }
  2875. return 0;
  2876. genpd_err:
  2877. drm_obj_init_err:
  2878. sde_core_perf_destroy(&sde_kms->perf);
  2879. hw_intr_init_err:
  2880. perf_err:
  2881. power_error:
  2882. return rc;
  2883. }
  2884. static int sde_kms_hw_init(struct msm_kms *kms)
  2885. {
  2886. struct sde_kms *sde_kms;
  2887. struct drm_device *dev;
  2888. struct msm_drm_private *priv;
  2889. struct platform_device *platformdev;
  2890. int i, irq_num, rc = -EINVAL;
  2891. if (!kms) {
  2892. SDE_ERROR("invalid kms\n");
  2893. goto end;
  2894. }
  2895. sde_kms = to_sde_kms(kms);
  2896. dev = sde_kms->dev;
  2897. if (!dev || !dev->dev) {
  2898. SDE_ERROR("invalid device\n");
  2899. goto end;
  2900. }
  2901. platformdev = to_platform_device(dev->dev);
  2902. priv = dev->dev_private;
  2903. if (!priv) {
  2904. SDE_ERROR("invalid private data\n");
  2905. goto end;
  2906. }
  2907. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  2908. if (rc)
  2909. goto error;
  2910. rc = _sde_kms_get_splash_data(&sde_kms->splash_data);
  2911. if (rc)
  2912. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  2913. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  2914. if (rc)
  2915. goto error;
  2916. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  2917. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  2918. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  2919. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  2920. mutex_init(&sde_kms->secure_transition_lock);
  2921. mutex_init(&sde_kms->vblank_ctl_global_lock);
  2922. atomic_set(&sde_kms->detach_sec_cb, 0);
  2923. atomic_set(&sde_kms->detach_all_cb, 0);
  2924. /*
  2925. * Support format modifiers for compression etc.
  2926. */
  2927. dev->mode_config.allow_fb_modifiers = true;
  2928. /*
  2929. * Handle (re)initializations during power enable
  2930. */
  2931. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  2932. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  2933. SDE_POWER_EVENT_POST_ENABLE |
  2934. SDE_POWER_EVENT_PRE_DISABLE,
  2935. sde_kms_handle_power_event, sde_kms, "kms");
  2936. if (sde_kms->splash_data.num_splash_displays) {
  2937. SDE_DEBUG("Skipping MDP Resources disable\n");
  2938. } else {
  2939. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  2940. sde_power_data_bus_set_quota(&priv->phandle, i,
  2941. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  2942. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  2943. pm_runtime_put_sync(sde_kms->dev->dev);
  2944. }
  2945. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  2946. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  2947. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  2948. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  2949. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  2950. return 0;
  2951. error:
  2952. _sde_kms_hw_destroy(sde_kms, platformdev);
  2953. end:
  2954. return rc;
  2955. }
  2956. struct msm_kms *sde_kms_init(struct drm_device *dev)
  2957. {
  2958. struct msm_drm_private *priv;
  2959. struct sde_kms *sde_kms;
  2960. if (!dev || !dev->dev_private) {
  2961. SDE_ERROR("drm device node invalid\n");
  2962. return ERR_PTR(-EINVAL);
  2963. }
  2964. priv = dev->dev_private;
  2965. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  2966. if (!sde_kms) {
  2967. SDE_ERROR("failed to allocate sde kms\n");
  2968. return ERR_PTR(-ENOMEM);
  2969. }
  2970. msm_kms_init(&sde_kms->base, &kms_funcs);
  2971. sde_kms->dev = dev;
  2972. return &sde_kms->base;
  2973. }
  2974. static int _sde_kms_register_events(struct msm_kms *kms,
  2975. struct drm_mode_object *obj, u32 event, bool en)
  2976. {
  2977. int ret = 0;
  2978. struct drm_crtc *crtc = NULL;
  2979. struct drm_connector *conn = NULL;
  2980. struct sde_kms *sde_kms = NULL;
  2981. if (!kms || !obj) {
  2982. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  2983. return -EINVAL;
  2984. }
  2985. sde_kms = to_sde_kms(kms);
  2986. switch (obj->type) {
  2987. case DRM_MODE_OBJECT_CRTC:
  2988. crtc = obj_to_crtc(obj);
  2989. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  2990. break;
  2991. case DRM_MODE_OBJECT_CONNECTOR:
  2992. conn = obj_to_connector(obj);
  2993. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  2994. en);
  2995. break;
  2996. }
  2997. return ret;
  2998. }
  2999. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3000. {
  3001. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3002. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3003. }