sde_hw_ctl.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/delay.h>
  6. #include "sde_hwio.h"
  7. #include "sde_hw_ctl.h"
  8. #include "sde_dbg.h"
  9. #include "sde_kms.h"
  10. #include "sde_reg_dma.h"
  11. #define CTL_LAYER(lm) \
  12. (((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
  13. #define CTL_LAYER_EXT(lm) \
  14. (0x40 + (((lm) - LM_0) * 0x004))
  15. #define CTL_LAYER_EXT2(lm) \
  16. (0x70 + (((lm) - LM_0) * 0x004))
  17. #define CTL_LAYER_EXT3(lm) \
  18. (0xA0 + (((lm) - LM_0) * 0x004))
  19. #define CTL_TOP 0x014
  20. #define CTL_FLUSH 0x018
  21. #define CTL_START 0x01C
  22. #define CTL_PREPARE 0x0d0
  23. #define CTL_SW_RESET 0x030
  24. #define CTL_SW_RESET_OVERRIDE 0x060
  25. #define CTL_STATUS 0x064
  26. #define CTL_LAYER_EXTN_OFFSET 0x40
  27. #define CTL_ROT_TOP 0x0C0
  28. #define CTL_ROT_FLUSH 0x0C4
  29. #define CTL_ROT_START 0x0CC
  30. #define CTL_MERGE_3D_ACTIVE 0x0E4
  31. #define CTL_DSC_ACTIVE 0x0E8
  32. #define CTL_WB_ACTIVE 0x0EC
  33. #define CTL_CWB_ACTIVE 0x0F0
  34. #define CTL_INTF_ACTIVE 0x0F4
  35. #define CTL_CDM_ACTIVE 0x0F8
  36. #define CTL_FETCH_PIPE_ACTIVE 0x0FC
  37. #define CTL_MERGE_3D_FLUSH 0x100
  38. #define CTL_DSC_FLUSH 0x104
  39. #define CTL_WB_FLUSH 0x108
  40. #define CTL_CWB_FLUSH 0x10C
  41. #define CTL_INTF_FLUSH 0x110
  42. #define CTL_CDM_FLUSH 0x114
  43. #define CTL_PERIPH_FLUSH 0x128
  44. #define CTL_DSPP_0_FLUSH 0x13c
  45. #define CTL_INTF_MASTER 0x134
  46. #define CTL_UIDLE_ACTIVE 0x138
  47. #define CTL_MIXER_BORDER_OUT BIT(24)
  48. #define CTL_FLUSH_MASK_ROT BIT(27)
  49. #define CTL_FLUSH_CTL 17
  50. #define CTL_NUM_EXT 4
  51. #define CTL_SSPP_MAX_RECTS 2
  52. #define SDE_REG_RESET_TIMEOUT_US 2000
  53. #define SDE_REG_WAIT_RESET_TIMEOUT_US 100000
  54. #define UPDATE_MASK(m, idx, en) \
  55. ((m) = (en) ? ((m) | BIT((idx))) : ((m) & ~BIT((idx))))
  56. #define CTL_INVALID_BIT 0xffff
  57. #define VDC_IDX(i) ((i) + 16)
  58. #define UPDATE_ACTIVE(r, idx, en) UPDATE_MASK((r), (idx), (en))
  59. /**
  60. * List of SSPP bits in CTL_FLUSH
  61. */
  62. static const u32 sspp_tbl[SSPP_MAX] = { SDE_NONE, 0, 1, 2, 18, 3, 4, 5,
  63. 19, 11, 12, 24, 25, SDE_NONE, SDE_NONE};
  64. /**
  65. * List of layer mixer bits in CTL_FLUSH
  66. */
  67. static const u32 mixer_tbl[LM_MAX] = {SDE_NONE, 6, 7, 8, 9, 10, 20,
  68. SDE_NONE};
  69. /**
  70. * List of DSPP bits in CTL_FLUSH
  71. */
  72. static const u32 dspp_tbl[DSPP_MAX] = {SDE_NONE, 13, 14, 15, 21};
  73. /**
  74. * List of DSPP PA LUT bits in CTL_FLUSH
  75. */
  76. static const u32 dspp_pav_tbl[DSPP_MAX] = {SDE_NONE, 3, 4, 5, 19};
  77. /**
  78. * List of CDM LUT bits in CTL_FLUSH
  79. */
  80. static const u32 cdm_tbl[CDM_MAX] = {SDE_NONE, 26};
  81. /**
  82. * List of WB bits in CTL_FLUSH
  83. */
  84. static const u32 wb_tbl[WB_MAX] = {SDE_NONE, SDE_NONE, SDE_NONE, 16};
  85. /**
  86. * List of ROT bits in CTL_FLUSH
  87. */
  88. static const u32 rot_tbl[ROT_MAX] = {SDE_NONE, 27};
  89. /**
  90. * List of INTF bits in CTL_FLUSH
  91. */
  92. static const u32 intf_tbl[INTF_MAX] = {SDE_NONE, 31, 30, 29, 28};
  93. /**
  94. * Below definitions are for CTL supporting SDE_CTL_ACTIVE_CFG,
  95. * certain blocks have the individual flush control as well,
  96. * for such blocks flush is done by flushing individual control and
  97. * top level control.
  98. */
  99. /**
  100. * List of SSPP bits in CTL_FETCH_PIPE_ACTIVE
  101. */
  102. static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
  103. CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
  104. 1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT};
  105. /**
  106. * list of WB bits in CTL_WB_FLUSH
  107. */
  108. static const u32 wb_flush_tbl[WB_MAX] = {SDE_NONE, SDE_NONE, SDE_NONE, 2};
  109. /**
  110. * list of INTF bits in CTL_INTF_FLUSH
  111. */
  112. static const u32 intf_flush_tbl[INTF_MAX] = {SDE_NONE, 0, 1, 2, 3, 4, 5};
  113. /**
  114. * list of DSC bits in CTL_DSC_FLUSH
  115. */
  116. static const u32 dsc_flush_tbl[DSC_MAX] = {SDE_NONE, 0, 1, 2, 3, 4, 5};
  117. /**
  118. * list of VDC bits in CTL_DSC_FLUSH
  119. */
  120. static const u32 vdc_flush_tbl[DSC_MAX] = {SDE_NONE, 16, 17};
  121. /**
  122. * list of MERGE_3D bits in CTL_MERGE_3D_FLUSH
  123. */
  124. static const u32 merge_3d_tbl[MERGE_3D_MAX] = {SDE_NONE, 0, 1, 2};
  125. /**
  126. * list of CDM bits in CTL_CDM_FLUSH
  127. */
  128. static const u32 cdm_flush_tbl[CDM_MAX] = {SDE_NONE, 0};
  129. /**
  130. * list of CWB bits in CTL_CWB_FLUSH
  131. */
  132. static const u32 cwb_flush_tbl[CWB_MAX] = {SDE_NONE, SDE_NONE, 1, 2, 3,
  133. 4, 5};
  134. /**
  135. * list of DSPP sub-blk flush bits in CTL_DSPP_x_FLUSH
  136. */
  137. static const u32 dspp_sub_blk_flush_tbl[SDE_DSPP_MAX] = {
  138. [SDE_DSPP_IGC] = 2,
  139. [SDE_DSPP_PCC] = 4,
  140. [SDE_DSPP_GC] = 5,
  141. [SDE_DSPP_HSIC] = 0,
  142. [SDE_DSPP_MEMCOLOR] = 0,
  143. [SDE_DSPP_SIXZONE] = 0,
  144. [SDE_DSPP_GAMUT] = 3,
  145. [SDE_DSPP_DITHER] = 0,
  146. [SDE_DSPP_HIST] = 0,
  147. [SDE_DSPP_VLUT] = 1,
  148. [SDE_DSPP_AD] = 0,
  149. [SDE_DSPP_LTM] = 7,
  150. [SDE_DSPP_SPR] = 8,
  151. [SDE_DSPP_DEMURA] = 9,
  152. [SDE_DSPP_RC] = 10,
  153. [SDE_DSPP_SB] = 31,
  154. };
  155. /**
  156. * struct ctl_sspp_stage_reg_map: Describes bit layout for a sspp stage cfg
  157. * @ext: Index to indicate LAYER_x_EXT id for given sspp
  158. * @start: Start position of blend stage bits for given sspp
  159. * @bits: Number of bits from @start assigned for given sspp
  160. * @sec_bit_mask: Bitmask to add to LAYER_x_EXT1 for missing bit of sspp
  161. */
  162. struct ctl_sspp_stage_reg_map {
  163. u32 ext;
  164. u32 start;
  165. u32 bits;
  166. u32 sec_bit_mask;
  167. };
  168. /* list of ctl_sspp_stage_reg_map for all the sppp */
  169. static const struct ctl_sspp_stage_reg_map
  170. sspp_reg_cfg_tbl[SSPP_MAX][CTL_SSPP_MAX_RECTS] = {
  171. /* SSPP_NONE */{ {0, 0, 0, 0}, {0, 0, 0, 0} },
  172. /* SSPP_VIG0 */{ {0, 0, 3, BIT(0)}, {3, 0, 4, 0} },
  173. /* SSPP_VIG1 */{ {0, 3, 3, BIT(2)}, {3, 4, 4, 0} },
  174. /* SSPP_VIG2 */{ {0, 6, 3, BIT(4)}, {3, 8, 4, 0} },
  175. /* SSPP_VIG3 */{ {0, 26, 3, BIT(6)}, {3, 12, 4, 0} },
  176. /* SSPP_RGB0 */{ {0, 9, 3, BIT(8)}, {0, 0, 0, 0} },
  177. /* SSPP_RGB1 */{ {0, 12, 3, BIT(10)}, {0, 0, 0, 0} },
  178. /* SSPP_RGB2 */{ {0, 15, 3, BIT(12)}, {0, 0, 0, 0} },
  179. /* SSPP_RGB3 */{ {0, 29, 3, BIT(14)}, {0, 0, 0, 0} },
  180. /* SSPP_DMA0 */{ {0, 18, 3, BIT(16)}, {2, 8, 4, 0} },
  181. /* SSPP_DMA1 */{ {0, 21, 3, BIT(18)}, {2, 12, 4, 0} },
  182. /* SSPP_DMA2 */{ {2, 0, 4, 0}, {2, 16, 4, 0} },
  183. /* SSPP_DMA3 */{ {2, 4, 4, 0}, {2, 20, 4, 0} },
  184. /* SSPP_CURSOR0 */{ {1, 20, 4, 0}, {0, 0, 0, 0} },
  185. /* SSPP_CURSOR1 */{ {0, 26, 4, 0}, {0, 0, 0, 0} }
  186. };
  187. /**
  188. * Individual flush bit in CTL_FLUSH
  189. */
  190. #define WB_IDX 16
  191. #define DSC_IDX 22
  192. #define MERGE_3D_IDX 23
  193. #define CDM_IDX 26
  194. #define CWB_IDX 28
  195. #define DSPP_IDX 29
  196. #define PERIPH_IDX 30
  197. #define INTF_IDX 31
  198. /* struct ctl_hw_flush_cfg: Defines the active ctl hw flush config,
  199. * See enum ctl_hw_flush_type for types
  200. * @blk_max: Maximum hw idx
  201. * @flush_reg: Register with corresponding active ctl hw
  202. * @flush_idx: Corresponding index in ctl flush
  203. * @flush_mask_idx: Index of hw flush mask to use
  204. * @flush_tbl: Pointer to flush table
  205. */
  206. struct ctl_hw_flush_cfg {
  207. u32 blk_max;
  208. u32 flush_reg;
  209. u32 flush_idx;
  210. u32 flush_mask_idx;
  211. const u32 *flush_tbl;
  212. };
  213. static const struct ctl_hw_flush_cfg
  214. ctl_hw_flush_cfg_tbl_v1[SDE_HW_FLUSH_MAX] = {
  215. {WB_MAX, CTL_WB_FLUSH, WB_IDX, SDE_HW_FLUSH_WB,
  216. wb_flush_tbl}, /* SDE_HW_FLUSH_WB */
  217. {DSC_MAX, CTL_DSC_FLUSH, DSC_IDX, SDE_HW_FLUSH_DSC,
  218. dsc_flush_tbl}, /* SDE_HW_FLUSH_DSC */
  219. /* VDC is flushed to dsc, flush_reg = 0 so flush is done only once */
  220. {VDC_MAX, 0, DSC_IDX, SDE_HW_FLUSH_DSC,
  221. vdc_flush_tbl}, /* SDE_HW_FLUSH_VDC */
  222. {MERGE_3D_MAX, CTL_MERGE_3D_FLUSH, MERGE_3D_IDX, SDE_HW_FLUSH_MERGE_3D,
  223. merge_3d_tbl}, /* SDE_HW_FLUSH_MERGE_3D */
  224. {CDM_MAX, CTL_CDM_FLUSH, CDM_IDX, SDE_HW_FLUSH_CDM,
  225. cdm_flush_tbl}, /* SDE_HW_FLUSH_CDM */
  226. {CWB_MAX, CTL_CWB_FLUSH, CWB_IDX, SDE_HW_FLUSH_CWB,
  227. cwb_flush_tbl}, /* SDE_HW_FLUSH_CWB */
  228. {INTF_MAX, CTL_PERIPH_FLUSH, PERIPH_IDX, SDE_HW_FLUSH_PERIPH,
  229. intf_flush_tbl }, /* SDE_HW_FLUSH_PERIPH */
  230. {INTF_MAX, CTL_INTF_FLUSH, INTF_IDX, SDE_HW_FLUSH_INTF,
  231. intf_flush_tbl } /* SDE_HW_FLUSH_INTF */
  232. };
  233. static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl,
  234. struct sde_mdss_cfg *m,
  235. void __iomem *addr,
  236. struct sde_hw_blk_reg_map *b)
  237. {
  238. int i;
  239. for (i = 0; i < m->ctl_count; i++) {
  240. if (ctl == m->ctl[i].id) {
  241. b->base_off = addr;
  242. b->blk_off = m->ctl[i].base;
  243. b->length = m->ctl[i].len;
  244. b->hwversion = m->hwversion;
  245. b->log_mask = SDE_DBG_MASK_CTL;
  246. return &m->ctl[i];
  247. }
  248. }
  249. return ERR_PTR(-ENOMEM);
  250. }
  251. static int _mixer_stages(const struct sde_lm_cfg *mixer, int count,
  252. enum sde_lm lm)
  253. {
  254. int i;
  255. int stages = -EINVAL;
  256. for (i = 0; i < count; i++) {
  257. if (lm == mixer[i].id) {
  258. stages = mixer[i].sblk->maxblendstages;
  259. break;
  260. }
  261. }
  262. return stages;
  263. }
  264. static inline bool _is_dspp_flush_pending(struct sde_hw_ctl *ctx)
  265. {
  266. int i;
  267. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++) {
  268. if (ctx->flush.pending_dspp_flush_masks[i])
  269. return true;
  270. }
  271. return false;
  272. }
  273. static inline int sde_hw_ctl_trigger_start(struct sde_hw_ctl *ctx)
  274. {
  275. if (!ctx)
  276. return -EINVAL;
  277. SDE_REG_WRITE(&ctx->hw, CTL_START, 0x1);
  278. return 0;
  279. }
  280. static inline int sde_hw_ctl_get_start_state(struct sde_hw_ctl *ctx)
  281. {
  282. if (!ctx)
  283. return -EINVAL;
  284. return SDE_REG_READ(&ctx->hw, CTL_START);
  285. }
  286. static inline int sde_hw_ctl_trigger_pending(struct sde_hw_ctl *ctx)
  287. {
  288. if (!ctx)
  289. return -EINVAL;
  290. SDE_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
  291. return 0;
  292. }
  293. static inline int sde_hw_ctl_clear_pending_flush(struct sde_hw_ctl *ctx)
  294. {
  295. if (!ctx)
  296. return -EINVAL;
  297. memset(&ctx->flush, 0, sizeof(ctx->flush));
  298. return 0;
  299. }
  300. static inline int sde_hw_ctl_update_pending_flush(struct sde_hw_ctl *ctx,
  301. struct sde_ctl_flush_cfg *cfg)
  302. {
  303. if (!ctx || !cfg)
  304. return -EINVAL;
  305. ctx->flush.pending_flush_mask |= cfg->pending_flush_mask;
  306. return 0;
  307. }
  308. static int sde_hw_ctl_get_pending_flush(struct sde_hw_ctl *ctx,
  309. struct sde_ctl_flush_cfg *cfg)
  310. {
  311. if (!ctx || !cfg)
  312. return -EINVAL;
  313. memcpy(cfg, &ctx->flush, sizeof(*cfg));
  314. return 0;
  315. }
  316. static inline int sde_hw_ctl_trigger_flush(struct sde_hw_ctl *ctx)
  317. {
  318. if (!ctx)
  319. return -EINVAL;
  320. SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
  321. return 0;
  322. }
  323. static inline u32 sde_hw_ctl_get_flush_register(struct sde_hw_ctl *ctx)
  324. {
  325. struct sde_hw_blk_reg_map *c;
  326. u32 rot_op_mode;
  327. if (!ctx)
  328. return 0;
  329. c = &ctx->hw;
  330. rot_op_mode = SDE_REG_READ(c, CTL_ROT_TOP) & 0x3;
  331. /* rotate flush bit is undefined if offline mode, so ignore it */
  332. if (rot_op_mode == SDE_CTL_ROT_OP_MODE_OFFLINE)
  333. return SDE_REG_READ(c, CTL_FLUSH) & ~CTL_FLUSH_MASK_ROT;
  334. return SDE_REG_READ(c, CTL_FLUSH);
  335. }
  336. static inline void sde_hw_ctl_uidle_enable(struct sde_hw_ctl *ctx, bool enable)
  337. {
  338. u32 val;
  339. if (!ctx)
  340. return;
  341. val = SDE_REG_READ(&ctx->hw, CTL_UIDLE_ACTIVE);
  342. val = (val & ~BIT(0)) | (enable ? BIT(0) : 0);
  343. SDE_REG_WRITE(&ctx->hw, CTL_UIDLE_ACTIVE, val);
  344. }
  345. static inline int sde_hw_ctl_update_bitmask_ctl(struct sde_hw_ctl *ctx,
  346. bool enable)
  347. {
  348. if (!ctx)
  349. return -EINVAL;
  350. UPDATE_MASK(ctx->flush.pending_flush_mask, CTL_FLUSH_CTL, enable);
  351. return 0;
  352. }
  353. static inline int sde_hw_ctl_update_bitmask_sspp(struct sde_hw_ctl *ctx,
  354. enum sde_sspp sspp,
  355. bool enable)
  356. {
  357. if (!ctx)
  358. return -EINVAL;
  359. if (!(sspp > SSPP_NONE) || !(sspp < SSPP_MAX)) {
  360. SDE_ERROR("Unsupported pipe %d\n", sspp);
  361. return -EINVAL;
  362. }
  363. UPDATE_MASK(ctx->flush.pending_flush_mask, sspp_tbl[sspp], enable);
  364. return 0;
  365. }
  366. static inline int sde_hw_ctl_update_bitmask_mixer(struct sde_hw_ctl *ctx,
  367. enum sde_lm lm,
  368. bool enable)
  369. {
  370. if (!ctx)
  371. return -EINVAL;
  372. if (!(lm > SDE_NONE) || !(lm < LM_MAX)) {
  373. SDE_ERROR("Unsupported mixer %d\n", lm);
  374. return -EINVAL;
  375. }
  376. UPDATE_MASK(ctx->flush.pending_flush_mask, mixer_tbl[lm], enable);
  377. sde_hw_ctl_update_bitmask_ctl(ctx, true);
  378. return 0;
  379. }
  380. static inline int sde_hw_ctl_update_bitmask_dspp(struct sde_hw_ctl *ctx,
  381. enum sde_dspp dspp,
  382. bool enable)
  383. {
  384. if (!ctx)
  385. return -EINVAL;
  386. if (!(dspp > SDE_NONE) || !(dspp < DSPP_MAX)) {
  387. SDE_ERROR("Unsupported dspp %d\n", dspp);
  388. return -EINVAL;
  389. }
  390. UPDATE_MASK(ctx->flush.pending_flush_mask, dspp_tbl[dspp], enable);
  391. return 0;
  392. }
  393. static inline int sde_hw_ctl_update_bitmask_dspp_pavlut(struct sde_hw_ctl *ctx,
  394. enum sde_dspp dspp, bool enable)
  395. {
  396. if (!ctx)
  397. return -EINVAL;
  398. if (!(dspp > SDE_NONE) || !(dspp < DSPP_MAX)) {
  399. SDE_ERROR("Unsupported dspp %d\n", dspp);
  400. return -EINVAL;
  401. }
  402. UPDATE_MASK(ctx->flush.pending_flush_mask, dspp_pav_tbl[dspp], enable);
  403. return 0;
  404. }
  405. static inline int sde_hw_ctl_update_bitmask_cdm(struct sde_hw_ctl *ctx,
  406. enum sde_cdm cdm,
  407. bool enable)
  408. {
  409. if (!ctx)
  410. return -EINVAL;
  411. if (!(cdm > SDE_NONE) || !(cdm < CDM_MAX) || (cdm == CDM_1)) {
  412. SDE_ERROR("Unsupported cdm %d\n", cdm);
  413. return -EINVAL;
  414. }
  415. UPDATE_MASK(ctx->flush.pending_flush_mask, cdm_tbl[cdm], enable);
  416. return 0;
  417. }
  418. static inline int sde_hw_ctl_update_bitmask_wb(struct sde_hw_ctl *ctx,
  419. enum sde_wb wb, bool enable)
  420. {
  421. if (!ctx)
  422. return -EINVAL;
  423. if (!(wb > SDE_NONE) || !(wb < WB_MAX) ||
  424. (wb == WB_0) || (wb == WB_1)) {
  425. SDE_ERROR("Unsupported wb %d\n", wb);
  426. return -EINVAL;
  427. }
  428. UPDATE_MASK(ctx->flush.pending_flush_mask, wb_tbl[wb], enable);
  429. return 0;
  430. }
  431. static inline int sde_hw_ctl_update_bitmask_intf(struct sde_hw_ctl *ctx,
  432. enum sde_intf intf, bool enable)
  433. {
  434. if (!ctx)
  435. return -EINVAL;
  436. if (!(intf > SDE_NONE) || !(intf < INTF_MAX) || (intf > INTF_4)) {
  437. SDE_ERROR("Unsupported intf %d\n", intf);
  438. return -EINVAL;
  439. }
  440. UPDATE_MASK(ctx->flush.pending_flush_mask, intf_tbl[intf], enable);
  441. return 0;
  442. }
  443. static inline int sde_hw_ctl_update_bitmask(struct sde_hw_ctl *ctx,
  444. enum ctl_hw_flush_type type, u32 blk_idx, bool enable)
  445. {
  446. int ret = 0;
  447. if (!ctx)
  448. return -EINVAL;
  449. switch (type) {
  450. case SDE_HW_FLUSH_CDM:
  451. ret = sde_hw_ctl_update_bitmask_cdm(ctx, blk_idx, enable);
  452. break;
  453. case SDE_HW_FLUSH_WB:
  454. ret = sde_hw_ctl_update_bitmask_wb(ctx, blk_idx, enable);
  455. break;
  456. case SDE_HW_FLUSH_INTF:
  457. ret = sde_hw_ctl_update_bitmask_intf(ctx, blk_idx, enable);
  458. break;
  459. default:
  460. break;
  461. }
  462. return ret;
  463. }
  464. static inline int sde_hw_ctl_update_bitmask_v1(struct sde_hw_ctl *ctx,
  465. enum ctl_hw_flush_type type, u32 blk_idx, bool enable)
  466. {
  467. const struct ctl_hw_flush_cfg *cfg;
  468. if (!ctx || !(type < SDE_HW_FLUSH_MAX))
  469. return -EINVAL;
  470. cfg = &ctl_hw_flush_cfg_tbl_v1[type];
  471. if ((blk_idx <= SDE_NONE) || (blk_idx >= cfg->blk_max)) {
  472. SDE_ERROR("Unsupported hw idx, type:%d, blk_idx:%d, blk_max:%d",
  473. type, blk_idx, cfg->blk_max);
  474. return -EINVAL;
  475. }
  476. UPDATE_MASK(ctx->flush.pending_hw_flush_mask[cfg->flush_mask_idx],
  477. cfg->flush_tbl[blk_idx], enable);
  478. if (ctx->flush.pending_hw_flush_mask[cfg->flush_mask_idx])
  479. UPDATE_MASK(ctx->flush.pending_flush_mask, cfg->flush_idx, 1);
  480. else
  481. UPDATE_MASK(ctx->flush.pending_flush_mask, cfg->flush_idx, 0);
  482. return 0;
  483. }
  484. static inline int sde_hw_ctl_update_pending_flush_v1(
  485. struct sde_hw_ctl *ctx,
  486. struct sde_ctl_flush_cfg *cfg)
  487. {
  488. int i = 0;
  489. if (!ctx || !cfg)
  490. return -EINVAL;
  491. for (i = 0; i < SDE_HW_FLUSH_MAX; i++)
  492. ctx->flush.pending_hw_flush_mask[i] |=
  493. cfg->pending_hw_flush_mask[i];
  494. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++)
  495. ctx->flush.pending_dspp_flush_masks[i] |=
  496. cfg->pending_dspp_flush_masks[i];
  497. ctx->flush.pending_flush_mask |= cfg->pending_flush_mask;
  498. return 0;
  499. }
  500. static inline int sde_hw_ctl_update_bitmask_dspp_subblk(struct sde_hw_ctl *ctx,
  501. enum sde_dspp dspp, u32 sub_blk, bool enable)
  502. {
  503. if (!ctx || dspp < DSPP_0 || dspp >= DSPP_MAX ||
  504. sub_blk < SDE_DSPP_IGC || sub_blk >= SDE_DSPP_MAX) {
  505. SDE_ERROR("invalid args - ctx %s, dspp %d sub_block %d\n",
  506. ctx ? "valid" : "invalid", dspp, sub_blk);
  507. return -EINVAL;
  508. }
  509. UPDATE_MASK(ctx->flush.pending_dspp_flush_masks[dspp - DSPP_0],
  510. dspp_sub_blk_flush_tbl[sub_blk], enable);
  511. if (_is_dspp_flush_pending(ctx))
  512. UPDATE_MASK(ctx->flush.pending_flush_mask, DSPP_IDX, 1);
  513. else
  514. UPDATE_MASK(ctx->flush.pending_flush_mask, DSPP_IDX, 0);
  515. return 0;
  516. }
  517. static inline void _sde_hw_ctl_write_dspp_flushes(struct sde_hw_ctl *ctx) {
  518. int i;
  519. bool has_dspp_flushes = ctx->caps->features &
  520. BIT(SDE_CTL_UNIFIED_DSPP_FLUSH);
  521. if (!has_dspp_flushes)
  522. return;
  523. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++) {
  524. u32 pending = ctx->flush.pending_dspp_flush_masks[i];
  525. if (pending)
  526. SDE_REG_WRITE(&ctx->hw, CTL_DSPP_0_FLUSH + (i * 4),
  527. pending);
  528. }
  529. }
  530. static inline int sde_hw_ctl_trigger_flush_v1(struct sde_hw_ctl *ctx)
  531. {
  532. int i = 0;
  533. const struct ctl_hw_flush_cfg *cfg = &ctl_hw_flush_cfg_tbl_v1[0];
  534. if (!ctx)
  535. return -EINVAL;
  536. if (ctx->flush.pending_flush_mask & BIT(DSPP_IDX))
  537. _sde_hw_ctl_write_dspp_flushes(ctx);
  538. for (i = 0; i < SDE_HW_FLUSH_MAX; i++)
  539. if (cfg[i].flush_reg &&
  540. ctx->flush.pending_flush_mask &
  541. BIT(cfg[i].flush_idx))
  542. SDE_REG_WRITE(&ctx->hw,
  543. cfg[i].flush_reg,
  544. ctx->flush.pending_hw_flush_mask[i]);
  545. SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
  546. return 0;
  547. }
  548. static inline u32 sde_hw_ctl_get_intf_v1(struct sde_hw_ctl *ctx)
  549. {
  550. struct sde_hw_blk_reg_map *c;
  551. u32 intf_active;
  552. if (!ctx) {
  553. pr_err("Invalid input argument\n");
  554. return 0;
  555. }
  556. c = &ctx->hw;
  557. intf_active = SDE_REG_READ(c, CTL_INTF_ACTIVE);
  558. return intf_active;
  559. }
  560. static inline u32 sde_hw_ctl_get_intf(struct sde_hw_ctl *ctx)
  561. {
  562. struct sde_hw_blk_reg_map *c;
  563. u32 ctl_top;
  564. u32 intf_active = 0;
  565. if (!ctx) {
  566. pr_err("Invalid input argument\n");
  567. return 0;
  568. }
  569. c = &ctx->hw;
  570. ctl_top = SDE_REG_READ(c, CTL_TOP);
  571. intf_active = (ctl_top > 0) ?
  572. BIT(ctl_top - 1) : 0;
  573. return intf_active;
  574. }
  575. static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 timeout_us)
  576. {
  577. struct sde_hw_blk_reg_map *c;
  578. ktime_t timeout;
  579. u32 status;
  580. if (!ctx)
  581. return 0;
  582. c = &ctx->hw;
  583. timeout = ktime_add_us(ktime_get(), timeout_us);
  584. /*
  585. * it takes around 30us to have mdp finish resetting its ctl path
  586. * poll every 50us so that reset should be completed at 1st poll
  587. */
  588. do {
  589. status = SDE_REG_READ(c, CTL_SW_RESET);
  590. status &= 0x1;
  591. if (status)
  592. usleep_range(20, 50);
  593. } while (status && ktime_compare_safe(ktime_get(), timeout) < 0);
  594. return status;
  595. }
  596. static u32 sde_hw_ctl_get_reset_status(struct sde_hw_ctl *ctx)
  597. {
  598. if (!ctx)
  599. return 0;
  600. return (u32)SDE_REG_READ(&ctx->hw, CTL_SW_RESET);
  601. }
  602. static u32 sde_hw_ctl_get_scheduler_status(struct sde_hw_ctl *ctx)
  603. {
  604. if (!ctx)
  605. return INVALID_CTL_STATUS;
  606. return (u32)SDE_REG_READ(&ctx->hw, CTL_STATUS);
  607. }
  608. static int sde_hw_ctl_reset_control(struct sde_hw_ctl *ctx)
  609. {
  610. struct sde_hw_blk_reg_map *c;
  611. if (!ctx)
  612. return 0;
  613. c = &ctx->hw;
  614. pr_debug("issuing hw ctl reset for ctl:%d\n", ctx->idx);
  615. SDE_REG_WRITE(c, CTL_SW_RESET, 0x1);
  616. if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_US))
  617. return -EINVAL;
  618. return 0;
  619. }
  620. static void sde_hw_ctl_hard_reset(struct sde_hw_ctl *ctx, bool enable)
  621. {
  622. struct sde_hw_blk_reg_map *c;
  623. if (!ctx)
  624. return;
  625. c = &ctx->hw;
  626. pr_debug("hw ctl hard reset for ctl:%d, %d\n",
  627. ctx->idx - CTL_0, enable);
  628. SDE_REG_WRITE(c, CTL_SW_RESET_OVERRIDE, enable);
  629. }
  630. static int sde_hw_ctl_wait_reset_status(struct sde_hw_ctl *ctx)
  631. {
  632. struct sde_hw_blk_reg_map *c;
  633. u32 status;
  634. if (!ctx)
  635. return 0;
  636. c = &ctx->hw;
  637. status = SDE_REG_READ(c, CTL_SW_RESET);
  638. status &= 0x01;
  639. if (!status)
  640. return 0;
  641. pr_debug("hw ctl reset is set for ctl:%d\n", ctx->idx);
  642. if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_WAIT_RESET_TIMEOUT_US)) {
  643. pr_err("hw recovery is not complete for ctl:%d\n", ctx->idx);
  644. return -EINVAL;
  645. }
  646. return 0;
  647. }
  648. static void sde_hw_ctl_clear_all_blendstages(struct sde_hw_ctl *ctx)
  649. {
  650. struct sde_hw_blk_reg_map *c;
  651. int i;
  652. if (!ctx)
  653. return;
  654. c = &ctx->hw;
  655. for (i = 0; i < ctx->mixer_count; i++) {
  656. int mixer_id = ctx->mixer_hw_caps[i].id;
  657. SDE_REG_WRITE(c, CTL_LAYER(mixer_id), 0);
  658. SDE_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0);
  659. SDE_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0);
  660. SDE_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0);
  661. }
  662. SDE_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);
  663. }
  664. static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
  665. enum sde_lm lm, struct sde_hw_stage_cfg *stage_cfg,
  666. struct sde_hw_stage_cfg *active_cfg)
  667. {
  668. struct sde_hw_blk_reg_map *c;
  669. u32 mixercfg = 0, mixercfg_ext = 0, mix, ext;
  670. u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0;
  671. u32 active_fetch_pipes = 0;
  672. int i, j;
  673. u8 stages;
  674. int pipes_per_stage;
  675. if (!ctx)
  676. return;
  677. c = &ctx->hw;
  678. stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm);
  679. if ((int)stages < 0)
  680. return;
  681. if (test_bit(SDE_MIXER_SOURCESPLIT,
  682. &ctx->mixer_hw_caps->features))
  683. pipes_per_stage = PIPES_PER_STAGE;
  684. else
  685. pipes_per_stage = 1;
  686. if (!stage_cfg)
  687. goto exit;
  688. for (i = 0; i <= stages; i++) {
  689. /* overflow to ext register if 'i + 1 > 7' */
  690. mix = (i + 1) & 0x7;
  691. ext = i >= 7;
  692. for (j = 0 ; j < pipes_per_stage; j++) {
  693. enum sde_sspp pipe = stage_cfg->stage[i][j];
  694. enum sde_sspp_multirect_index rect_index =
  695. stage_cfg->multirect_index[i][j];
  696. switch (pipe) {
  697. case SSPP_VIG0:
  698. if (rect_index == SDE_SSPP_RECT_1) {
  699. mixercfg_ext3 |= ((i + 1) & 0xF) << 0;
  700. } else {
  701. mixercfg |= mix << 0;
  702. mixercfg_ext |= ext << 0;
  703. }
  704. break;
  705. case SSPP_VIG1:
  706. if (rect_index == SDE_SSPP_RECT_1) {
  707. mixercfg_ext3 |= ((i + 1) & 0xF) << 4;
  708. } else {
  709. mixercfg |= mix << 3;
  710. mixercfg_ext |= ext << 2;
  711. }
  712. break;
  713. case SSPP_VIG2:
  714. if (rect_index == SDE_SSPP_RECT_1) {
  715. mixercfg_ext3 |= ((i + 1) & 0xF) << 8;
  716. } else {
  717. mixercfg |= mix << 6;
  718. mixercfg_ext |= ext << 4;
  719. }
  720. break;
  721. case SSPP_VIG3:
  722. if (rect_index == SDE_SSPP_RECT_1) {
  723. mixercfg_ext3 |= ((i + 1) & 0xF) << 12;
  724. } else {
  725. mixercfg |= mix << 26;
  726. mixercfg_ext |= ext << 6;
  727. }
  728. break;
  729. case SSPP_RGB0:
  730. mixercfg |= mix << 9;
  731. mixercfg_ext |= ext << 8;
  732. break;
  733. case SSPP_RGB1:
  734. mixercfg |= mix << 12;
  735. mixercfg_ext |= ext << 10;
  736. break;
  737. case SSPP_RGB2:
  738. mixercfg |= mix << 15;
  739. mixercfg_ext |= ext << 12;
  740. break;
  741. case SSPP_RGB3:
  742. mixercfg |= mix << 29;
  743. mixercfg_ext |= ext << 14;
  744. break;
  745. case SSPP_DMA0:
  746. if (rect_index == SDE_SSPP_RECT_1) {
  747. mixercfg_ext2 |= ((i + 1) & 0xF) << 8;
  748. } else {
  749. mixercfg |= mix << 18;
  750. mixercfg_ext |= ext << 16;
  751. }
  752. break;
  753. case SSPP_DMA1:
  754. if (rect_index == SDE_SSPP_RECT_1) {
  755. mixercfg_ext2 |= ((i + 1) & 0xF) << 12;
  756. } else {
  757. mixercfg |= mix << 21;
  758. mixercfg_ext |= ext << 18;
  759. }
  760. break;
  761. case SSPP_DMA2:
  762. if (rect_index == SDE_SSPP_RECT_1) {
  763. mixercfg_ext2 |= ((i + 1) & 0xF) << 16;
  764. } else {
  765. mix |= (i + 1) & 0xF;
  766. mixercfg_ext2 |= mix << 0;
  767. }
  768. break;
  769. case SSPP_DMA3:
  770. if (rect_index == SDE_SSPP_RECT_1) {
  771. mixercfg_ext2 |= ((i + 1) & 0xF) << 20;
  772. } else {
  773. mix |= (i + 1) & 0xF;
  774. mixercfg_ext2 |= mix << 4;
  775. }
  776. break;
  777. case SSPP_CURSOR0:
  778. mixercfg_ext |= ((i + 1) & 0xF) << 20;
  779. break;
  780. case SSPP_CURSOR1:
  781. mixercfg_ext |= ((i + 1) & 0xF) << 26;
  782. break;
  783. default:
  784. break;
  785. }
  786. if (fetch_tbl[pipe] != CTL_INVALID_BIT)
  787. active_fetch_pipes |= BIT(fetch_tbl[pipe]);
  788. }
  789. }
  790. for (i = 0; i <= stages && active_cfg; i++) {
  791. enum sde_sspp pipe = active_cfg->stage[i][0];
  792. if (pipe == SSPP_NONE)
  793. break;
  794. if (fetch_tbl[pipe] != CTL_INVALID_BIT) {
  795. active_fetch_pipes |= BIT(fetch_tbl[pipe]);
  796. SDE_DEBUG("fetch pipe %d active pipes %x\n",
  797. pipe, active_fetch_pipes);
  798. }
  799. }
  800. exit:
  801. if ((!mixercfg && !mixercfg_ext && !mixercfg_ext2 && !mixercfg_ext3) ||
  802. (stage_cfg && !stage_cfg->stage[0][0]))
  803. mixercfg |= CTL_MIXER_BORDER_OUT;
  804. SDE_REG_WRITE(c, CTL_LAYER(lm), mixercfg);
  805. SDE_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext);
  806. SDE_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2);
  807. SDE_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3);
  808. SDE_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, active_fetch_pipes);
  809. }
  810. static u32 sde_hw_ctl_get_staged_sspp(struct sde_hw_ctl *ctx, enum sde_lm lm,
  811. struct sde_sspp_index_info *info, u32 info_max_cnt)
  812. {
  813. int i, j;
  814. u32 count = 0;
  815. u32 mask = 0;
  816. bool staged;
  817. u32 mixercfg[CTL_NUM_EXT];
  818. struct sde_hw_blk_reg_map *c;
  819. const struct ctl_sspp_stage_reg_map *sspp_cfg;
  820. if (!ctx || (lm >= LM_MAX) || !info)
  821. return count;
  822. c = &ctx->hw;
  823. mixercfg[0] = SDE_REG_READ(c, CTL_LAYER(lm));
  824. mixercfg[1] = SDE_REG_READ(c, CTL_LAYER_EXT(lm));
  825. mixercfg[2] = SDE_REG_READ(c, CTL_LAYER_EXT2(lm));
  826. mixercfg[3] = SDE_REG_READ(c, CTL_LAYER_EXT3(lm));
  827. for (i = SSPP_VIG0; i < SSPP_MAX; i++) {
  828. for (j = 0; j < CTL_SSPP_MAX_RECTS; j++) {
  829. if (count >= info_max_cnt)
  830. goto end;
  831. sspp_cfg = &sspp_reg_cfg_tbl[i][j];
  832. if (!sspp_cfg->bits || sspp_cfg->ext >= CTL_NUM_EXT)
  833. continue;
  834. mask = ((0x1 << sspp_cfg->bits) - 1) << sspp_cfg->start;
  835. staged = mixercfg[sspp_cfg->ext] & mask;
  836. if (!staged)
  837. staged = mixercfg[1] & sspp_cfg->sec_bit_mask;
  838. if (staged) {
  839. info[count].sspp = i;
  840. info[count].is_virtual = j;
  841. count++;
  842. }
  843. }
  844. }
  845. end:
  846. return count;
  847. }
  848. static int sde_hw_ctl_intf_cfg_v1(struct sde_hw_ctl *ctx,
  849. struct sde_hw_intf_cfg_v1 *cfg)
  850. {
  851. struct sde_hw_blk_reg_map *c;
  852. u32 intf_active = 0;
  853. u32 wb_active = 0;
  854. u32 merge_3d_active = 0;
  855. u32 cwb_active = 0;
  856. u32 mode_sel = 0xf0000000;
  857. u32 cdm_active = 0;
  858. u32 intf_master = 0;
  859. u32 i;
  860. if (!ctx)
  861. return -EINVAL;
  862. c = &ctx->hw;
  863. for (i = 0; i < cfg->intf_count; i++) {
  864. if (cfg->intf[i])
  865. intf_active |= BIT(cfg->intf[i] - INTF_0);
  866. }
  867. if (cfg->intf_count > 1)
  868. intf_master = BIT(cfg->intf_master - INTF_0);
  869. for (i = 0; i < cfg->wb_count; i++) {
  870. if (cfg->wb[i])
  871. wb_active |= BIT(cfg->wb[i] - WB_0);
  872. }
  873. for (i = 0; i < cfg->merge_3d_count; i++) {
  874. if (cfg->merge_3d[i])
  875. merge_3d_active |= BIT(cfg->merge_3d[i] - MERGE_3D_0);
  876. }
  877. for (i = 0; i < cfg->cwb_count; i++) {
  878. if (cfg->cwb[i])
  879. cwb_active |= BIT(cfg->cwb[i] - CWB_0);
  880. }
  881. for (i = 0; i < cfg->cdm_count; i++) {
  882. if (cfg->cdm[i])
  883. cdm_active |= BIT(cfg->cdm[i] - CDM_0);
  884. }
  885. if (cfg->intf_mode_sel == SDE_CTL_MODE_SEL_CMD)
  886. mode_sel |= BIT(17);
  887. SDE_REG_WRITE(c, CTL_TOP, mode_sel);
  888. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  889. SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
  890. SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
  891. SDE_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active);
  892. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  893. SDE_REG_WRITE(c, CTL_INTF_MASTER, intf_master);
  894. return 0;
  895. }
  896. static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
  897. struct sde_hw_intf_cfg_v1 *cfg, u32 merge_3d_idx)
  898. {
  899. struct sde_hw_blk_reg_map *c;
  900. u32 intf_active = 0, wb_active = 0, merge_3d_active = 0;
  901. u32 intf_flush = 0, wb_flush = 0;
  902. u32 i;
  903. if (!ctx || !cfg) {
  904. SDE_ERROR("invalid hw_ctl or hw_intf blk\n");
  905. return -EINVAL;
  906. }
  907. c = &ctx->hw;
  908. for (i = 0; i < cfg->intf_count; i++) {
  909. if (cfg->intf[i]) {
  910. intf_active &= ~BIT(cfg->intf[i] - INTF_0);
  911. intf_flush |= BIT(cfg->intf[i] - INTF_0);
  912. }
  913. }
  914. for (i = 0; i < cfg->wb_count; i++) {
  915. if (cfg->wb[i]) {
  916. wb_active &= ~BIT(cfg->wb[i] - WB_0);
  917. wb_flush |= BIT(cfg->wb[i] - WB_0);
  918. }
  919. }
  920. if (merge_3d_idx) {
  921. /* disable and flush merge3d_blk */
  922. merge_3d_active &= ~BIT(merge_3d_idx - MERGE_3D_0);
  923. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_MERGE_3D] =
  924. BIT(merge_3d_idx - MERGE_3D_0);
  925. UPDATE_MASK(ctx->flush.pending_flush_mask, MERGE_3D_IDX, 1);
  926. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  927. }
  928. sde_hw_ctl_clear_all_blendstages(ctx);
  929. if (cfg->intf_count) {
  930. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_INTF] =
  931. intf_flush;
  932. UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 1);
  933. SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
  934. }
  935. if (cfg->wb_count) {
  936. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_WB] = wb_flush;
  937. UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 1);
  938. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  939. }
  940. return 0;
  941. }
  942. static int sde_hw_ctl_update_intf_cfg(struct sde_hw_ctl *ctx,
  943. struct sde_hw_intf_cfg_v1 *cfg, bool enable)
  944. {
  945. int i;
  946. u32 cwb_active = 0;
  947. u32 merge_3d_active = 0;
  948. u32 wb_active = 0;
  949. u32 dsc_active = 0;
  950. u32 vdc_active = 0;
  951. struct sde_hw_blk_reg_map *c;
  952. if (!ctx)
  953. return -EINVAL;
  954. c = &ctx->hw;
  955. if (cfg->cwb_count) {
  956. cwb_active = SDE_REG_READ(c, CTL_CWB_ACTIVE);
  957. for (i = 0; i < cfg->cwb_count; i++) {
  958. if (cfg->cwb[i])
  959. UPDATE_ACTIVE(cwb_active,
  960. (cfg->cwb[i] - CWB_0),
  961. enable);
  962. }
  963. wb_active = enable ? BIT(2) : 0;
  964. SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
  965. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  966. }
  967. if (cfg->merge_3d_count) {
  968. merge_3d_active = SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE);
  969. for (i = 0; i < cfg->merge_3d_count; i++) {
  970. if (cfg->merge_3d[i])
  971. UPDATE_ACTIVE(merge_3d_active,
  972. (cfg->merge_3d[i] - MERGE_3D_0),
  973. enable);
  974. }
  975. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  976. }
  977. if (cfg->dsc_count) {
  978. dsc_active = SDE_REG_READ(c, CTL_DSC_ACTIVE);
  979. for (i = 0; i < cfg->dsc_count; i++) {
  980. if (cfg->dsc[i])
  981. UPDATE_ACTIVE(dsc_active,
  982. (cfg->dsc[i] - DSC_0), enable);
  983. }
  984. SDE_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
  985. }
  986. if (cfg->vdc_count) {
  987. vdc_active = SDE_REG_READ(c, CTL_DSC_ACTIVE);
  988. for (i = 0; i < cfg->vdc_count; i++) {
  989. if (cfg->vdc[i])
  990. UPDATE_ACTIVE(vdc_active,
  991. VDC_IDX(cfg->vdc[i] - VDC_0), enable);
  992. }
  993. SDE_REG_WRITE(c, CTL_DSC_ACTIVE, vdc_active);
  994. }
  995. return 0;
  996. }
  997. static int sde_hw_ctl_intf_cfg(struct sde_hw_ctl *ctx,
  998. struct sde_hw_intf_cfg *cfg)
  999. {
  1000. struct sde_hw_blk_reg_map *c;
  1001. u32 intf_cfg = 0;
  1002. if (!ctx)
  1003. return -EINVAL;
  1004. c = &ctx->hw;
  1005. intf_cfg |= (cfg->intf & 0xF) << 4;
  1006. if (cfg->wb)
  1007. intf_cfg |= (cfg->wb & 0x3) + 2;
  1008. if (cfg->mode_3d) {
  1009. intf_cfg |= BIT(19);
  1010. intf_cfg |= (cfg->mode_3d - 0x1) << 20;
  1011. }
  1012. switch (cfg->intf_mode_sel) {
  1013. case SDE_CTL_MODE_SEL_VID:
  1014. intf_cfg &= ~BIT(17);
  1015. intf_cfg &= ~(0x3 << 15);
  1016. break;
  1017. case SDE_CTL_MODE_SEL_CMD:
  1018. intf_cfg |= BIT(17);
  1019. intf_cfg |= ((cfg->stream_sel & 0x3) << 15);
  1020. break;
  1021. default:
  1022. pr_err("unknown interface type %d\n", cfg->intf_mode_sel);
  1023. return -EINVAL;
  1024. }
  1025. SDE_REG_WRITE(c, CTL_TOP, intf_cfg);
  1026. return 0;
  1027. }
  1028. static void sde_hw_ctl_update_wb_cfg(struct sde_hw_ctl *ctx,
  1029. struct sde_hw_intf_cfg *cfg, bool enable)
  1030. {
  1031. struct sde_hw_blk_reg_map *c = &ctx->hw;
  1032. u32 intf_cfg = 0;
  1033. if (!cfg->wb)
  1034. return;
  1035. intf_cfg = SDE_REG_READ(c, CTL_TOP);
  1036. if (enable)
  1037. intf_cfg |= (cfg->wb & 0x3) + 2;
  1038. else
  1039. intf_cfg &= ~((cfg->wb & 0x3) + 2);
  1040. SDE_REG_WRITE(c, CTL_TOP, intf_cfg);
  1041. }
  1042. static inline u32 sde_hw_ctl_read_ctl_top(struct sde_hw_ctl *ctx)
  1043. {
  1044. struct sde_hw_blk_reg_map *c;
  1045. u32 ctl_top;
  1046. if (!ctx) {
  1047. pr_err("Invalid input argument\n");
  1048. return 0;
  1049. }
  1050. c = &ctx->hw;
  1051. ctl_top = SDE_REG_READ(c, CTL_TOP);
  1052. return ctl_top;
  1053. }
  1054. static inline u32 sde_hw_ctl_read_ctl_layers(struct sde_hw_ctl *ctx, int index)
  1055. {
  1056. struct sde_hw_blk_reg_map *c;
  1057. u32 ctl_top;
  1058. if (!ctx) {
  1059. pr_err("Invalid input argument\n");
  1060. return 0;
  1061. }
  1062. c = &ctx->hw;
  1063. ctl_top = SDE_REG_READ(c, CTL_LAYER(index));
  1064. pr_debug("Ctl_layer value = 0x%x\n", ctl_top);
  1065. return ctl_top;
  1066. }
  1067. static inline bool sde_hw_ctl_read_active_status(struct sde_hw_ctl *ctx,
  1068. enum sde_hw_blk_type blk, int index)
  1069. {
  1070. struct sde_hw_blk_reg_map *c;
  1071. if (!ctx) {
  1072. pr_err("Invalid input argument\n");
  1073. return 0;
  1074. }
  1075. c = &ctx->hw;
  1076. switch (blk) {
  1077. case SDE_HW_BLK_MERGE_3D:
  1078. return (SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE) &
  1079. BIT(index - MERGE_3D_0)) ? true : false;
  1080. case SDE_HW_BLK_DSC:
  1081. return (SDE_REG_READ(c, CTL_DSC_ACTIVE) &
  1082. BIT(index - DSC_0)) ? true : false;
  1083. case SDE_HW_BLK_WB:
  1084. return (SDE_REG_READ(c, CTL_WB_ACTIVE) &
  1085. BIT(index - WB_0)) ? true : false;
  1086. case SDE_HW_BLK_CDM:
  1087. return (SDE_REG_READ(c, CTL_CDM_ACTIVE) &
  1088. BIT(index - CDM_0)) ? true : false;
  1089. case SDE_HW_BLK_INTF:
  1090. return (SDE_REG_READ(c, CTL_INTF_ACTIVE) &
  1091. BIT(index - INTF_0)) ? true : false;
  1092. default:
  1093. pr_err("unsupported blk %d\n", blk);
  1094. return false;
  1095. };
  1096. return false;
  1097. }
  1098. static int sde_hw_reg_dma_flush(struct sde_hw_ctl *ctx, bool blocking)
  1099. {
  1100. struct sde_hw_reg_dma_ops *ops = sde_reg_dma_get_ops();
  1101. if (!ctx)
  1102. return -EINVAL;
  1103. if (ops && ops->last_command)
  1104. return ops->last_command(ctx, DMA_CTL_QUEUE0,
  1105. (blocking ? REG_DMA_WAIT4_COMP : REG_DMA_NOWAIT));
  1106. return 0;
  1107. }
  1108. static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops,
  1109. unsigned long cap)
  1110. {
  1111. if (cap & BIT(SDE_CTL_ACTIVE_CFG)) {
  1112. ops->update_pending_flush =
  1113. sde_hw_ctl_update_pending_flush_v1;
  1114. ops->trigger_flush = sde_hw_ctl_trigger_flush_v1;
  1115. ops->setup_intf_cfg_v1 = sde_hw_ctl_intf_cfg_v1;
  1116. ops->update_intf_cfg = sde_hw_ctl_update_intf_cfg;
  1117. ops->update_bitmask = sde_hw_ctl_update_bitmask_v1;
  1118. ops->get_ctl_intf = sde_hw_ctl_get_intf_v1;
  1119. ops->reset_post_disable = sde_hw_ctl_reset_post_disable;
  1120. ops->get_scheduler_status = sde_hw_ctl_get_scheduler_status;
  1121. ops->read_active_status = sde_hw_ctl_read_active_status;
  1122. } else {
  1123. ops->update_pending_flush = sde_hw_ctl_update_pending_flush;
  1124. ops->trigger_flush = sde_hw_ctl_trigger_flush;
  1125. ops->setup_intf_cfg = sde_hw_ctl_intf_cfg;
  1126. ops->update_bitmask = sde_hw_ctl_update_bitmask;
  1127. ops->get_ctl_intf = sde_hw_ctl_get_intf;
  1128. }
  1129. ops->clear_pending_flush = sde_hw_ctl_clear_pending_flush;
  1130. ops->get_pending_flush = sde_hw_ctl_get_pending_flush;
  1131. ops->get_flush_register = sde_hw_ctl_get_flush_register;
  1132. ops->trigger_start = sde_hw_ctl_trigger_start;
  1133. ops->trigger_pending = sde_hw_ctl_trigger_pending;
  1134. ops->read_ctl_top = sde_hw_ctl_read_ctl_top;
  1135. ops->read_ctl_layers = sde_hw_ctl_read_ctl_layers;
  1136. ops->update_wb_cfg = sde_hw_ctl_update_wb_cfg;
  1137. ops->reset = sde_hw_ctl_reset_control;
  1138. ops->get_reset = sde_hw_ctl_get_reset_status;
  1139. ops->hard_reset = sde_hw_ctl_hard_reset;
  1140. ops->wait_reset_status = sde_hw_ctl_wait_reset_status;
  1141. ops->clear_all_blendstages = sde_hw_ctl_clear_all_blendstages;
  1142. ops->setup_blendstage = sde_hw_ctl_setup_blendstage;
  1143. ops->get_staged_sspp = sde_hw_ctl_get_staged_sspp;
  1144. ops->update_bitmask_ctl = sde_hw_ctl_update_bitmask_ctl;
  1145. ops->update_bitmask_sspp = sde_hw_ctl_update_bitmask_sspp;
  1146. ops->update_bitmask_mixer = sde_hw_ctl_update_bitmask_mixer;
  1147. ops->reg_dma_flush = sde_hw_reg_dma_flush;
  1148. ops->get_start_state = sde_hw_ctl_get_start_state;
  1149. if (cap & BIT(SDE_CTL_UNIFIED_DSPP_FLUSH)) {
  1150. ops->update_bitmask_dspp_subblk =
  1151. sde_hw_ctl_update_bitmask_dspp_subblk;
  1152. } else {
  1153. ops->update_bitmask_dspp = sde_hw_ctl_update_bitmask_dspp;
  1154. ops->update_bitmask_dspp_pavlut =
  1155. sde_hw_ctl_update_bitmask_dspp_pavlut;
  1156. }
  1157. if (cap & BIT(SDE_CTL_UIDLE))
  1158. ops->uidle_enable = sde_hw_ctl_uidle_enable;
  1159. };
  1160. static struct sde_hw_blk_ops sde_hw_ops = {
  1161. .start = NULL,
  1162. .stop = NULL,
  1163. };
  1164. struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx,
  1165. void __iomem *addr,
  1166. struct sde_mdss_cfg *m)
  1167. {
  1168. struct sde_hw_ctl *c;
  1169. struct sde_ctl_cfg *cfg;
  1170. int rc;
  1171. c = kzalloc(sizeof(*c), GFP_KERNEL);
  1172. if (!c)
  1173. return ERR_PTR(-ENOMEM);
  1174. cfg = _ctl_offset(idx, m, addr, &c->hw);
  1175. if (IS_ERR_OR_NULL(cfg)) {
  1176. kfree(c);
  1177. pr_err("failed to create sde_hw_ctl %d\n", idx);
  1178. return ERR_PTR(-EINVAL);
  1179. }
  1180. c->caps = cfg;
  1181. _setup_ctl_ops(&c->ops, c->caps->features);
  1182. c->idx = idx;
  1183. c->mixer_count = m->mixer_count;
  1184. c->mixer_hw_caps = m->mixer;
  1185. rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_CTL, idx, &sde_hw_ops);
  1186. if (rc) {
  1187. SDE_ERROR("failed to init hw blk %d\n", rc);
  1188. goto blk_init_error;
  1189. }
  1190. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
  1191. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  1192. return c;
  1193. blk_init_error:
  1194. kzfree(c);
  1195. return ERR_PTR(rc);
  1196. }
  1197. void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx)
  1198. {
  1199. if (ctx)
  1200. sde_hw_blk_destroy(&ctx->base);
  1201. kfree(ctx);
  1202. }