sde_encoder_phys_wb.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  6. #include <linux/debugfs.h>
  7. #include <uapi/drm/sde_drm.h>
  8. #include "sde_encoder_phys.h"
  9. #include "sde_formats.h"
  10. #include "sde_hw_top.h"
  11. #include "sde_hw_interrupts.h"
  12. #include "sde_core_irq.h"
  13. #include "sde_wb.h"
  14. #include "sde_vbif.h"
  15. #include "sde_crtc.h"
  16. #define to_sde_encoder_phys_wb(x) \
  17. container_of(x, struct sde_encoder_phys_wb, base)
  18. #define WBID(wb_enc) \
  19. ((wb_enc && wb_enc->wb_dev) ? wb_enc->wb_dev->wb_idx - WB_0 : -1)
  20. #define TO_S15D16(_x_) ((_x_) << 7)
  21. static const u32 cwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, INTR_IDX_PP1_OVFL,
  22. INTR_IDX_PP2_OVFL, INTR_IDX_PP3_OVFL, INTR_IDX_PP4_OVFL,
  23. INTR_IDX_PP5_OVFL, SDE_NONE, SDE_NONE};
  24. /**
  25. * sde_rgb2yuv_601l - rgb to yuv color space conversion matrix
  26. *
  27. */
  28. static struct sde_csc_cfg sde_encoder_phys_wb_rgb2yuv_601l = {
  29. {
  30. TO_S15D16(0x0083), TO_S15D16(0x0102), TO_S15D16(0x0032),
  31. TO_S15D16(0x1fb5), TO_S15D16(0x1f6c), TO_S15D16(0x00e1),
  32. TO_S15D16(0x00e1), TO_S15D16(0x1f45), TO_S15D16(0x1fdc)
  33. },
  34. { 0x00, 0x00, 0x00 },
  35. { 0x0040, 0x0200, 0x0200 },
  36. { 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },
  37. { 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },
  38. };
  39. /**
  40. * sde_encoder_phys_wb_is_master - report wb always as master encoder
  41. */
  42. static bool sde_encoder_phys_wb_is_master(struct sde_encoder_phys *phys_enc)
  43. {
  44. return true;
  45. }
  46. /**
  47. * sde_encoder_phys_wb_get_intr_type - get interrupt type based on block mode
  48. * @hw_wb: Pointer to h/w writeback driver
  49. */
  50. static enum sde_intr_type sde_encoder_phys_wb_get_intr_type(
  51. struct sde_hw_wb *hw_wb)
  52. {
  53. return (hw_wb->caps->features & BIT(SDE_WB_BLOCK_MODE)) ?
  54. SDE_IRQ_TYPE_WB_ROT_COMP : SDE_IRQ_TYPE_WB_WFD_COMP;
  55. }
  56. /**
  57. * sde_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
  58. * @phys_enc: Pointer to physical encoder
  59. */
  60. static void sde_encoder_phys_wb_set_ot_limit(
  61. struct sde_encoder_phys *phys_enc)
  62. {
  63. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  64. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  65. struct sde_vbif_set_ot_params ot_params;
  66. memset(&ot_params, 0, sizeof(ot_params));
  67. ot_params.xin_id = hw_wb->caps->xin_id;
  68. ot_params.num = hw_wb->idx - WB_0;
  69. ot_params.width = wb_enc->wb_roi.w;
  70. ot_params.height = wb_enc->wb_roi.h;
  71. ot_params.is_wfd = true;
  72. ot_params.frame_rate = phys_enc->cached_mode.vrefresh;
  73. ot_params.vbif_idx = hw_wb->caps->vbif_idx;
  74. ot_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  75. ot_params.rd = false;
  76. sde_vbif_set_ot_limit(phys_enc->sde_kms, &ot_params);
  77. }
  78. /**
  79. * sde_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
  80. * @phys_enc: Pointer to physical encoder
  81. */
  82. static void sde_encoder_phys_wb_set_qos_remap(
  83. struct sde_encoder_phys *phys_enc)
  84. {
  85. struct sde_encoder_phys_wb *wb_enc;
  86. struct sde_hw_wb *hw_wb;
  87. struct drm_crtc *crtc;
  88. struct sde_vbif_set_qos_params qos_params;
  89. if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
  90. SDE_ERROR("invalid arguments\n");
  91. return;
  92. }
  93. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  94. if (!wb_enc->crtc) {
  95. SDE_ERROR("invalid crtc");
  96. return;
  97. }
  98. crtc = wb_enc->crtc;
  99. if (!wb_enc->hw_wb || !wb_enc->hw_wb->caps) {
  100. SDE_ERROR("invalid writeback hardware\n");
  101. return;
  102. }
  103. hw_wb = wb_enc->hw_wb;
  104. memset(&qos_params, 0, sizeof(qos_params));
  105. qos_params.vbif_idx = hw_wb->caps->vbif_idx;
  106. qos_params.xin_id = hw_wb->caps->xin_id;
  107. qos_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  108. qos_params.num = hw_wb->idx - WB_0;
  109. qos_params.client_type = phys_enc->in_clone_mode ?
  110. VBIF_CWB_CLIENT : VBIF_NRT_CLIENT;
  111. SDE_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d clone:%d\n",
  112. qos_params.num,
  113. qos_params.vbif_idx,
  114. qos_params.xin_id, qos_params.client_type);
  115. sde_vbif_set_qos_remap(phys_enc->sde_kms, &qos_params);
  116. }
  117. static u64 _sde_encoder_phys_wb_get_qos_lut(const struct sde_qos_lut_tbl *tbl,
  118. u32 total_fl)
  119. {
  120. int i;
  121. if (!tbl || !tbl->nentry || !tbl->entries)
  122. return 0;
  123. for (i = 0; i < tbl->nentry; i++)
  124. if (total_fl <= tbl->entries[i].fl)
  125. return tbl->entries[i].lut;
  126. /* if last fl is zero, use as default */
  127. if (!tbl->entries[i-1].fl)
  128. return tbl->entries[i-1].lut;
  129. return 0;
  130. }
  131. /**
  132. * sde_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
  133. * @phys_enc: Pointer to physical encoder
  134. */
  135. static void sde_encoder_phys_wb_set_qos(struct sde_encoder_phys *phys_enc)
  136. {
  137. struct sde_encoder_phys_wb *wb_enc;
  138. struct sde_hw_wb *hw_wb;
  139. struct sde_hw_wb_qos_cfg qos_cfg;
  140. struct sde_mdss_cfg *catalog;
  141. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog) {
  142. SDE_ERROR("invalid parameter(s)\n");
  143. return;
  144. }
  145. catalog = phys_enc->sde_kms->catalog;
  146. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  147. if (!wb_enc->hw_wb) {
  148. SDE_ERROR("invalid writeback hardware\n");
  149. return;
  150. }
  151. hw_wb = wb_enc->hw_wb;
  152. memset(&qos_cfg, 0, sizeof(struct sde_hw_wb_qos_cfg));
  153. qos_cfg.danger_safe_en = true;
  154. qos_cfg.danger_lut =
  155. catalog->perf.danger_lut_tbl[SDE_QOS_LUT_USAGE_NRT];
  156. if (phys_enc->in_clone_mode)
  157. qos_cfg.safe_lut = (u32) _sde_encoder_phys_wb_get_qos_lut(
  158. &catalog->perf.sfe_lut_tbl[SDE_QOS_LUT_USAGE_CWB], 0);
  159. else
  160. qos_cfg.safe_lut = (u32) _sde_encoder_phys_wb_get_qos_lut(
  161. &catalog->perf.sfe_lut_tbl[SDE_QOS_LUT_USAGE_NRT], 0);
  162. if (phys_enc->in_clone_mode)
  163. qos_cfg.creq_lut = _sde_encoder_phys_wb_get_qos_lut(
  164. &catalog->perf.qos_lut_tbl[SDE_QOS_LUT_USAGE_CWB], 0);
  165. else
  166. qos_cfg.creq_lut = _sde_encoder_phys_wb_get_qos_lut(
  167. &catalog->perf.qos_lut_tbl[SDE_QOS_LUT_USAGE_NRT], 0);
  168. if (hw_wb->ops.setup_danger_safe_lut)
  169. hw_wb->ops.setup_danger_safe_lut(hw_wb, &qos_cfg);
  170. if (hw_wb->ops.setup_creq_lut)
  171. hw_wb->ops.setup_creq_lut(hw_wb, &qos_cfg);
  172. if (hw_wb->ops.setup_qos_ctrl)
  173. hw_wb->ops.setup_qos_ctrl(hw_wb, &qos_cfg);
  174. }
  175. /**
  176. * sde_encoder_phys_setup_cdm - setup chroma down block
  177. * @phys_enc: Pointer to physical encoder
  178. * @fb: Pointer to output framebuffer
  179. * @format: Output format
  180. */
  181. void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
  182. struct drm_framebuffer *fb, const struct sde_format *format,
  183. struct sde_rect *wb_roi)
  184. {
  185. struct sde_hw_cdm *hw_cdm;
  186. struct sde_hw_cdm_cfg *cdm_cfg;
  187. struct sde_hw_pingpong *hw_pp;
  188. int ret;
  189. if (!phys_enc || !format)
  190. return;
  191. cdm_cfg = &phys_enc->cdm_cfg;
  192. hw_pp = phys_enc->hw_pp;
  193. hw_cdm = phys_enc->hw_cdm;
  194. if (!hw_cdm)
  195. return;
  196. if (!SDE_FORMAT_IS_YUV(format)) {
  197. SDE_DEBUG("[cdm_disable fmt:%x]\n",
  198. format->base.pixel_format);
  199. if (hw_cdm && hw_cdm->ops.disable)
  200. hw_cdm->ops.disable(hw_cdm);
  201. return;
  202. }
  203. memset(cdm_cfg, 0, sizeof(struct sde_hw_cdm_cfg));
  204. if (!wb_roi)
  205. return;
  206. cdm_cfg->output_width = wb_roi->w;
  207. cdm_cfg->output_height = wb_roi->h;
  208. cdm_cfg->output_fmt = format;
  209. cdm_cfg->output_type = CDM_CDWN_OUTPUT_WB;
  210. cdm_cfg->output_bit_depth = SDE_FORMAT_IS_DX(format) ?
  211. CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
  212. /* enable 10 bit logic */
  213. switch (cdm_cfg->output_fmt->chroma_sample) {
  214. case SDE_CHROMA_RGB:
  215. cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
  216. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  217. break;
  218. case SDE_CHROMA_H2V1:
  219. cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
  220. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  221. break;
  222. case SDE_CHROMA_420:
  223. cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
  224. cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
  225. break;
  226. case SDE_CHROMA_H1V2:
  227. default:
  228. SDE_ERROR("unsupported chroma sampling type\n");
  229. cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
  230. cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
  231. break;
  232. }
  233. SDE_DEBUG("[cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
  234. cdm_cfg->output_width,
  235. cdm_cfg->output_height,
  236. cdm_cfg->output_fmt->base.pixel_format,
  237. cdm_cfg->output_type,
  238. cdm_cfg->output_bit_depth,
  239. cdm_cfg->h_cdwn_type,
  240. cdm_cfg->v_cdwn_type);
  241. if (hw_cdm && hw_cdm->ops.setup_csc_data) {
  242. ret = hw_cdm->ops.setup_csc_data(hw_cdm,
  243. &sde_encoder_phys_wb_rgb2yuv_601l);
  244. if (ret < 0) {
  245. SDE_ERROR("failed to setup CSC %d\n", ret);
  246. return;
  247. }
  248. }
  249. if (hw_cdm && hw_cdm->ops.setup_cdwn) {
  250. ret = hw_cdm->ops.setup_cdwn(hw_cdm, cdm_cfg);
  251. if (ret < 0) {
  252. SDE_ERROR("failed to setup CDM %d\n", ret);
  253. return;
  254. }
  255. }
  256. if (hw_cdm && hw_pp && hw_cdm->ops.enable) {
  257. cdm_cfg->pp_id = hw_pp->idx;
  258. ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
  259. if (ret < 0) {
  260. SDE_ERROR("failed to enable CDM %d\n", ret);
  261. return;
  262. }
  263. }
  264. }
  265. /**
  266. * sde_encoder_phys_wb_setup_fb - setup output framebuffer
  267. * @phys_enc: Pointer to physical encoder
  268. * @fb: Pointer to output framebuffer
  269. * @wb_roi: Pointer to output region of interest
  270. */
  271. static void sde_encoder_phys_wb_setup_fb(struct sde_encoder_phys *phys_enc,
  272. struct drm_framebuffer *fb, struct sde_rect *wb_roi)
  273. {
  274. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  275. struct sde_hw_wb *hw_wb;
  276. struct sde_hw_wb_cfg *wb_cfg;
  277. struct sde_hw_wb_cdp_cfg *cdp_cfg;
  278. const struct msm_format *format;
  279. int ret;
  280. struct msm_gem_address_space *aspace;
  281. u32 fb_mode;
  282. if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog ||
  283. !phys_enc->connector) {
  284. SDE_ERROR("invalid encoder\n");
  285. return;
  286. }
  287. hw_wb = wb_enc->hw_wb;
  288. wb_cfg = &wb_enc->wb_cfg;
  289. cdp_cfg = &wb_enc->cdp_cfg;
  290. memset(wb_cfg, 0, sizeof(struct sde_hw_wb_cfg));
  291. wb_cfg->intf_mode = phys_enc->intf_mode;
  292. fb_mode = sde_connector_get_property(phys_enc->connector->state,
  293. CONNECTOR_PROP_FB_TRANSLATION_MODE);
  294. if (phys_enc->enable_state == SDE_ENC_DISABLING)
  295. wb_cfg->is_secure = false;
  296. else if (fb_mode == SDE_DRM_FB_SEC)
  297. wb_cfg->is_secure = true;
  298. else
  299. wb_cfg->is_secure = false;
  300. aspace = (wb_cfg->is_secure) ?
  301. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] :
  302. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE];
  303. SDE_DEBUG("[fb_secure:%d]\n", wb_cfg->is_secure);
  304. ret = msm_framebuffer_prepare(fb, aspace);
  305. if (ret) {
  306. SDE_ERROR("prep fb failed, %d\n", ret);
  307. return;
  308. }
  309. /* cache framebuffer for cleanup in writeback done */
  310. wb_enc->wb_fb = fb;
  311. wb_enc->wb_aspace = aspace;
  312. format = msm_framebuffer_format(fb);
  313. if (!format) {
  314. SDE_DEBUG("invalid format for fb\n");
  315. return;
  316. }
  317. wb_cfg->dest.format = sde_get_sde_format_ext(
  318. format->pixel_format,
  319. fb->modifier);
  320. if (!wb_cfg->dest.format) {
  321. /* this error should be detected during atomic_check */
  322. SDE_ERROR("failed to get format %x\n", format->pixel_format);
  323. return;
  324. }
  325. wb_cfg->roi = *wb_roi;
  326. if (hw_wb->caps->features & BIT(SDE_WB_XY_ROI_OFFSET)) {
  327. ret = sde_format_populate_layout(aspace, fb, &wb_cfg->dest);
  328. if (ret) {
  329. SDE_DEBUG("failed to populate layout %d\n", ret);
  330. return;
  331. }
  332. wb_cfg->dest.width = fb->width;
  333. wb_cfg->dest.height = fb->height;
  334. wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
  335. } else {
  336. ret = sde_format_populate_layout_with_roi(aspace, fb, wb_roi,
  337. &wb_cfg->dest);
  338. if (ret) {
  339. /* this error should be detected during atomic_check */
  340. SDE_DEBUG("failed to populate layout %d\n", ret);
  341. return;
  342. }
  343. }
  344. if ((wb_cfg->dest.format->fetch_planes == SDE_PLANE_PLANAR) &&
  345. (wb_cfg->dest.format->element[0] == C1_B_Cb))
  346. swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
  347. SDE_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
  348. wb_cfg->dest.plane_addr[0],
  349. wb_cfg->dest.plane_addr[1],
  350. wb_cfg->dest.plane_addr[2],
  351. wb_cfg->dest.plane_addr[3]);
  352. SDE_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
  353. wb_cfg->dest.plane_pitch[0],
  354. wb_cfg->dest.plane_pitch[1],
  355. wb_cfg->dest.plane_pitch[2],
  356. wb_cfg->dest.plane_pitch[3]);
  357. if (hw_wb->ops.setup_roi)
  358. hw_wb->ops.setup_roi(hw_wb, wb_cfg);
  359. if (hw_wb->ops.setup_outformat)
  360. hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
  361. if (hw_wb->ops.setup_cdp) {
  362. memset(cdp_cfg, 0, sizeof(struct sde_hw_wb_cdp_cfg));
  363. cdp_cfg->enable = phys_enc->sde_kms->catalog->perf.cdp_cfg
  364. [SDE_PERF_CDP_USAGE_NRT].wr_enable;
  365. cdp_cfg->ubwc_meta_enable =
  366. SDE_FORMAT_IS_UBWC(wb_cfg->dest.format);
  367. cdp_cfg->tile_amortize_enable =
  368. SDE_FORMAT_IS_UBWC(wb_cfg->dest.format) ||
  369. SDE_FORMAT_IS_TILE(wb_cfg->dest.format);
  370. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  371. hw_wb->ops.setup_cdp(hw_wb, cdp_cfg);
  372. }
  373. if (hw_wb->ops.setup_outaddress) {
  374. SDE_EVT32(hw_wb->idx,
  375. wb_cfg->dest.width,
  376. wb_cfg->dest.height,
  377. wb_cfg->dest.plane_addr[0],
  378. wb_cfg->dest.plane_size[0],
  379. wb_cfg->dest.plane_addr[1],
  380. wb_cfg->dest.plane_size[1],
  381. wb_cfg->dest.plane_addr[2],
  382. wb_cfg->dest.plane_size[2],
  383. wb_cfg->dest.plane_addr[3],
  384. wb_cfg->dest.plane_size[3]);
  385. hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
  386. }
  387. }
  388. static void _sde_encoder_phys_wb_setup_cwb(struct sde_encoder_phys *phys_enc,
  389. bool enable)
  390. {
  391. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  392. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  393. struct sde_hw_ctl *hw_ctl = phys_enc->hw_ctl;
  394. struct sde_crtc *crtc = to_sde_crtc(wb_enc->crtc);
  395. struct sde_hw_pingpong *hw_pp = phys_enc->hw_pp;
  396. bool need_merge = (crtc->num_mixers > 1);
  397. int i = 0;
  398. if (!phys_enc->in_clone_mode) {
  399. SDE_DEBUG("not in CWB mode. early return\n");
  400. return;
  401. }
  402. if (!hw_pp || !hw_ctl || !hw_wb || hw_pp->idx >= PINGPONG_MAX) {
  403. SDE_ERROR("invalid hw resources - return\n");
  404. return;
  405. }
  406. hw_ctl = crtc->mixers[0].hw_ctl;
  407. if (hw_ctl && hw_ctl->ops.setup_intf_cfg_v1 &&
  408. test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features)) {
  409. struct sde_hw_intf_cfg_v1 intf_cfg = { 0, };
  410. for (i = 0; i < crtc->num_mixers; i++)
  411. intf_cfg.cwb[intf_cfg.cwb_count++] =
  412. (enum sde_cwb)(hw_pp->idx + i);
  413. if (enable && hw_pp->merge_3d && (intf_cfg.merge_3d_count <
  414. MAX_MERGE_3D_PER_CTL_V1) && need_merge)
  415. intf_cfg.merge_3d[intf_cfg.merge_3d_count++] =
  416. hw_pp->merge_3d->idx;
  417. if (hw_pp->ops.setup_3d_mode)
  418. hw_pp->ops.setup_3d_mode(hw_pp, (enable && need_merge) ?
  419. BLEND_3D_H_ROW_INT : 0);
  420. if (hw_wb->ops.bind_pingpong_blk)
  421. hw_wb->ops.bind_pingpong_blk(hw_wb, enable, hw_pp->idx);
  422. if (hw_ctl->ops.update_cwb_cfg) {
  423. hw_ctl->ops.update_cwb_cfg(hw_ctl, &intf_cfg);
  424. SDE_DEBUG("in CWB mode on CTL_%d PP-%d merge3d:%d\n",
  425. hw_ctl->idx - CTL_0,
  426. hw_pp->idx - PINGPONG_0,
  427. hw_pp->merge_3d ?
  428. hw_pp->merge_3d->idx - MERGE_3D_0 : -1);
  429. }
  430. } else {
  431. struct sde_hw_intf_cfg *intf_cfg = &phys_enc->intf_cfg;
  432. memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
  433. intf_cfg->intf = SDE_NONE;
  434. intf_cfg->wb = hw_wb->idx;
  435. if (hw_ctl && hw_ctl->ops.update_wb_cfg) {
  436. hw_ctl->ops.update_wb_cfg(hw_ctl, intf_cfg, enable);
  437. SDE_DEBUG("in CWB mode adding WB for CTL_%d\n",
  438. hw_ctl->idx - CTL_0);
  439. }
  440. }
  441. }
  442. /**
  443. * sde_encoder_phys_wb_setup_cdp - setup chroma down prefetch block
  444. * @phys_enc: Pointer to physical encoder
  445. */
  446. static void sde_encoder_phys_wb_setup_cdp(struct sde_encoder_phys *phys_enc,
  447. const struct sde_format *format)
  448. {
  449. struct sde_encoder_phys_wb *wb_enc;
  450. struct sde_hw_wb *hw_wb;
  451. struct sde_hw_cdm *hw_cdm;
  452. struct sde_hw_ctl *ctl;
  453. const int num_wb = 1;
  454. if (!phys_enc) {
  455. SDE_ERROR("invalid encoder\n");
  456. return;
  457. }
  458. if (phys_enc->in_clone_mode) {
  459. SDE_DEBUG("in CWB mode. early return\n");
  460. return;
  461. }
  462. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  463. hw_wb = wb_enc->hw_wb;
  464. hw_cdm = phys_enc->hw_cdm;
  465. ctl = phys_enc->hw_ctl;
  466. if (test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&
  467. (phys_enc->hw_ctl &&
  468. phys_enc->hw_ctl->ops.setup_intf_cfg_v1)) {
  469. struct sde_hw_intf_cfg_v1 *intf_cfg_v1 = &phys_enc->intf_cfg_v1;
  470. struct sde_hw_pingpong *hw_pp = phys_enc->hw_pp;
  471. enum sde_3d_blend_mode mode_3d;
  472. memset(intf_cfg_v1, 0, sizeof(struct sde_hw_intf_cfg_v1));
  473. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  474. intf_cfg_v1->intf_count = SDE_NONE;
  475. intf_cfg_v1->wb_count = num_wb;
  476. intf_cfg_v1->wb[0] = hw_wb->idx;
  477. if (SDE_FORMAT_IS_YUV(format)) {
  478. intf_cfg_v1->cdm_count = num_wb;
  479. intf_cfg_v1->cdm[0] = hw_cdm->idx;
  480. }
  481. if (mode_3d && hw_pp && hw_pp->merge_3d &&
  482. intf_cfg_v1->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  483. intf_cfg_v1->merge_3d[intf_cfg_v1->merge_3d_count++] =
  484. hw_pp->merge_3d->idx;
  485. if (hw_pp && hw_pp->ops.setup_3d_mode)
  486. hw_pp->ops.setup_3d_mode(hw_pp, mode_3d);
  487. /* setup which pp blk will connect to this wb */
  488. if (hw_pp && hw_wb->ops.bind_pingpong_blk)
  489. hw_wb->ops.bind_pingpong_blk(hw_wb, true,
  490. hw_pp->idx);
  491. phys_enc->hw_ctl->ops.setup_intf_cfg_v1(phys_enc->hw_ctl,
  492. intf_cfg_v1);
  493. } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
  494. struct sde_hw_intf_cfg *intf_cfg = &phys_enc->intf_cfg;
  495. memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
  496. intf_cfg->intf = SDE_NONE;
  497. intf_cfg->wb = hw_wb->idx;
  498. intf_cfg->mode_3d =
  499. sde_encoder_helper_get_3d_blend_mode(phys_enc);
  500. phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl,
  501. intf_cfg);
  502. }
  503. }
  504. static void _sde_enc_phys_wb_detect_cwb(struct sde_encoder_phys *phys_enc,
  505. struct drm_crtc_state *crtc_state)
  506. {
  507. struct drm_encoder *encoder;
  508. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  509. const struct sde_wb_cfg *wb_cfg = wb_enc->hw_wb->caps;
  510. phys_enc->in_clone_mode = false;
  511. /* Check if WB has CWB support */
  512. if (!(wb_cfg->features & BIT(SDE_WB_HAS_CWB)))
  513. return;
  514. /* if any other encoder is connected to same crtc enable clone mode*/
  515. drm_for_each_encoder(encoder, crtc_state->crtc->dev) {
  516. if (encoder->crtc != crtc_state->crtc)
  517. continue;
  518. if (phys_enc->parent != encoder) {
  519. phys_enc->in_clone_mode = true;
  520. break;
  521. }
  522. }
  523. SDE_DEBUG("detect CWB - status:%d\n", phys_enc->in_clone_mode);
  524. }
  525. static int _sde_enc_phys_wb_validate_cwb(struct sde_encoder_phys *phys_enc,
  526. struct drm_crtc_state *crtc_state,
  527. struct drm_connector_state *conn_state)
  528. {
  529. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc_state);
  530. struct sde_rect wb_roi = {0,};
  531. struct sde_rect pu_roi = {0,};
  532. int data_pt;
  533. int ds_outw = 0;
  534. int ds_outh = 0;
  535. int ds_in_use = false;
  536. int i = 0;
  537. int ret = 0;
  538. if (!phys_enc->in_clone_mode) {
  539. SDE_DEBUG("not in CWB mode. early return\n");
  540. goto exit;
  541. }
  542. ret = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
  543. if (ret) {
  544. SDE_ERROR("failed to get roi %d\n", ret);
  545. goto exit;
  546. }
  547. data_pt = sde_crtc_get_property(cstate, CRTC_PROP_CAPTURE_OUTPUT);
  548. /* compute cumulative ds output dimensions if in use */
  549. for (i = 0; i < cstate->num_ds; i++)
  550. if (cstate->ds_cfg[i].scl3_cfg.enable) {
  551. ds_in_use = true;
  552. ds_outw += cstate->ds_cfg[i].scl3_cfg.dst_width;
  553. ds_outh = cstate->ds_cfg[i].scl3_cfg.dst_height;
  554. }
  555. /* if ds in use check wb roi against ds output dimensions */
  556. if ((data_pt == CAPTURE_DSPP_OUT) && ds_in_use &&
  557. ((wb_roi.w != ds_outw) || (wb_roi.h != ds_outh))) {
  558. SDE_ERROR("invalid wb roi with dest scalar [%dx%d vs %dx%d]\n",
  559. wb_roi.w, wb_roi.h, ds_outw, ds_outh);
  560. ret = -EINVAL;
  561. goto exit;
  562. }
  563. /* validate conn roi against pu rect */
  564. if (cstate->user_roi_list.num_rects) {
  565. sde_kms_rect_merge_rectangles(&cstate->user_roi_list, &pu_roi);
  566. if (wb_roi.w != pu_roi.w || wb_roi.h != pu_roi.h) {
  567. SDE_ERROR("invalid wb roi with pu [%dx%d vs %dx%d]\n",
  568. wb_roi.w, wb_roi.h, pu_roi.w, pu_roi.h);
  569. ret = -EINVAL;
  570. goto exit;
  571. }
  572. }
  573. exit:
  574. return ret;
  575. }
  576. /**
  577. * sde_encoder_phys_wb_atomic_check - verify and fixup given atomic states
  578. * @phys_enc: Pointer to physical encoder
  579. * @crtc_state: Pointer to CRTC atomic state
  580. * @conn_state: Pointer to connector atomic state
  581. */
  582. static int sde_encoder_phys_wb_atomic_check(
  583. struct sde_encoder_phys *phys_enc,
  584. struct drm_crtc_state *crtc_state,
  585. struct drm_connector_state *conn_state)
  586. {
  587. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  588. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  589. const struct sde_wb_cfg *wb_cfg = hw_wb->caps;
  590. struct drm_framebuffer *fb;
  591. const struct sde_format *fmt;
  592. struct sde_rect wb_roi;
  593. const struct drm_display_mode *mode = &crtc_state->mode;
  594. int rc;
  595. SDE_DEBUG("[atomic_check:%d,%d,\"%s\",%d,%d]\n",
  596. hw_wb->idx - WB_0, mode->base.id, mode->name,
  597. mode->hdisplay, mode->vdisplay);
  598. if (!conn_state || !conn_state->connector) {
  599. SDE_ERROR("invalid connector state\n");
  600. return -EINVAL;
  601. } else if (conn_state->connector->status !=
  602. connector_status_connected) {
  603. SDE_ERROR("connector not connected %d\n",
  604. conn_state->connector->status);
  605. return -EINVAL;
  606. }
  607. _sde_enc_phys_wb_detect_cwb(phys_enc, crtc_state);
  608. memset(&wb_roi, 0, sizeof(struct sde_rect));
  609. rc = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
  610. if (rc) {
  611. SDE_ERROR("failed to get roi %d\n", rc);
  612. return rc;
  613. }
  614. SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi.x, wb_roi.y,
  615. wb_roi.w, wb_roi.h);
  616. /* bypass check if commit with no framebuffer */
  617. fb = sde_wb_connector_state_get_output_fb(conn_state);
  618. if (!fb) {
  619. SDE_DEBUG("no output framebuffer\n");
  620. return 0;
  621. }
  622. SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
  623. fb->width, fb->height);
  624. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  625. if (!fmt) {
  626. SDE_ERROR("unsupported output pixel format:%x\n",
  627. fb->format->format);
  628. return -EINVAL;
  629. }
  630. SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->format->format,
  631. fb->modifier);
  632. if (SDE_FORMAT_IS_YUV(fmt) &&
  633. !(wb_cfg->features & BIT(SDE_WB_YUV_CONFIG))) {
  634. SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
  635. return -EINVAL;
  636. }
  637. if (SDE_FORMAT_IS_UBWC(fmt) &&
  638. !(wb_cfg->features & BIT(SDE_WB_UBWC))) {
  639. SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
  640. return -EINVAL;
  641. }
  642. if (SDE_FORMAT_IS_YUV(fmt) != !!phys_enc->hw_cdm)
  643. crtc_state->mode_changed = true;
  644. if (wb_roi.w && wb_roi.h) {
  645. if (wb_roi.w != mode->hdisplay) {
  646. SDE_ERROR("invalid roi w=%d, mode w=%d\n", wb_roi.w,
  647. mode->hdisplay);
  648. return -EINVAL;
  649. } else if (wb_roi.h != mode->vdisplay) {
  650. SDE_ERROR("invalid roi h=%d, mode h=%d\n", wb_roi.h,
  651. mode->vdisplay);
  652. return -EINVAL;
  653. } else if (wb_roi.x + wb_roi.w > fb->width) {
  654. SDE_ERROR("invalid roi x=%d, w=%d, fb w=%d\n",
  655. wb_roi.x, wb_roi.w, fb->width);
  656. return -EINVAL;
  657. } else if (wb_roi.y + wb_roi.h > fb->height) {
  658. SDE_ERROR("invalid roi y=%d, h=%d, fb h=%d\n",
  659. wb_roi.y, wb_roi.h, fb->height);
  660. return -EINVAL;
  661. } else if (wb_roi.w > wb_cfg->sblk->maxlinewidth) {
  662. SDE_ERROR("invalid roi w=%d, maxlinewidth=%u\n",
  663. wb_roi.w, wb_cfg->sblk->maxlinewidth);
  664. return -EINVAL;
  665. }
  666. } else {
  667. if (wb_roi.x || wb_roi.y) {
  668. SDE_ERROR("invalid roi x=%d, y=%d\n",
  669. wb_roi.x, wb_roi.y);
  670. return -EINVAL;
  671. } else if (fb->width != mode->hdisplay) {
  672. SDE_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
  673. mode->hdisplay);
  674. return -EINVAL;
  675. } else if (fb->height != mode->vdisplay) {
  676. SDE_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
  677. mode->vdisplay);
  678. return -EINVAL;
  679. } else if (fb->width > wb_cfg->sblk->maxlinewidth) {
  680. SDE_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
  681. fb->width, wb_cfg->sblk->maxlinewidth);
  682. return -EINVAL;
  683. }
  684. }
  685. rc = _sde_enc_phys_wb_validate_cwb(phys_enc, crtc_state, conn_state);
  686. if (rc) {
  687. SDE_ERROR("failed in cwb validation %d\n", rc);
  688. return rc;
  689. }
  690. return rc;
  691. }
  692. static void _sde_encoder_phys_wb_update_cwb_flush(
  693. struct sde_encoder_phys *phys_enc)
  694. {
  695. struct sde_encoder_phys_wb *wb_enc;
  696. struct sde_hw_wb *hw_wb;
  697. struct sde_hw_ctl *hw_ctl;
  698. struct sde_hw_cdm *hw_cdm;
  699. struct sde_hw_pingpong *hw_pp;
  700. struct sde_crtc *crtc;
  701. struct sde_crtc_state *crtc_state;
  702. int i = 0;
  703. int cwb_capture_mode = 0;
  704. enum sde_cwb cwb_idx = 0;
  705. enum sde_cwb src_pp_idx = 0;
  706. bool dspp_out = false;
  707. bool need_merge = false;
  708. if (!phys_enc->in_clone_mode) {
  709. SDE_DEBUG("not in CWB mode. early return\n");
  710. return;
  711. }
  712. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  713. crtc = to_sde_crtc(wb_enc->crtc);
  714. crtc_state = to_sde_crtc_state(wb_enc->crtc->state);
  715. cwb_capture_mode = sde_crtc_get_property(crtc_state,
  716. CRTC_PROP_CAPTURE_OUTPUT);
  717. hw_pp = phys_enc->hw_pp;
  718. hw_wb = wb_enc->hw_wb;
  719. hw_cdm = phys_enc->hw_cdm;
  720. /* In CWB mode, program actual source master sde_hw_ctl from crtc */
  721. hw_ctl = crtc->mixers[0].hw_ctl;
  722. if (!hw_ctl || !hw_wb || !hw_pp) {
  723. SDE_ERROR("[wb] HW resource not available for CWB\n");
  724. return;
  725. }
  726. /* treating LM idx of primary display ctl path as source ping-pong idx*/
  727. src_pp_idx = (enum sde_cwb)crtc->mixers[0].hw_lm->idx;
  728. cwb_idx = (enum sde_cwb)hw_pp->idx;
  729. dspp_out = (cwb_capture_mode == CAPTURE_DSPP_OUT);
  730. need_merge = (crtc->num_mixers > 1) ? true : false;
  731. if (src_pp_idx > CWB_0 || ((cwb_idx + crtc->num_mixers) > CWB_MAX)) {
  732. SDE_ERROR("invalid hw config for CWB\n");
  733. return;
  734. }
  735. if (hw_ctl->ops.update_bitmask_wb)
  736. hw_ctl->ops.update_bitmask_wb(hw_ctl, hw_wb->idx, 1);
  737. if (hw_ctl->ops.update_bitmask_cdm && hw_cdm)
  738. hw_ctl->ops.update_bitmask_cdm(hw_ctl, hw_cdm->idx, 1);
  739. if (test_bit(SDE_WB_CWB_CTRL, &hw_wb->caps->features)) {
  740. for (i = 0; i < crtc->num_mixers; i++) {
  741. cwb_idx = (enum sde_cwb) (hw_pp->idx + i);
  742. src_pp_idx = (enum sde_cwb) (src_pp_idx + i);
  743. if (hw_wb->ops.program_cwb_ctrl)
  744. hw_wb->ops.program_cwb_ctrl(hw_wb, cwb_idx,
  745. src_pp_idx, dspp_out);
  746. if (hw_ctl->ops.update_bitmask_cwb)
  747. hw_ctl->ops.update_bitmask_cwb(hw_ctl,
  748. cwb_idx, 1);
  749. }
  750. if (need_merge && hw_ctl->ops.update_bitmask_merge3d
  751. && hw_pp && hw_pp->merge_3d)
  752. hw_ctl->ops.update_bitmask_merge3d(hw_ctl,
  753. hw_pp->merge_3d->idx, 1);
  754. } else {
  755. phys_enc->hw_mdptop->ops.set_cwb_ppb_cntl(phys_enc->hw_mdptop,
  756. need_merge, dspp_out);
  757. }
  758. }
  759. /**
  760. * _sde_encoder_phys_wb_update_flush - flush hardware update
  761. * @phys_enc: Pointer to physical encoder
  762. */
  763. static void _sde_encoder_phys_wb_update_flush(struct sde_encoder_phys *phys_enc)
  764. {
  765. struct sde_encoder_phys_wb *wb_enc;
  766. struct sde_hw_wb *hw_wb;
  767. struct sde_hw_ctl *hw_ctl;
  768. struct sde_hw_cdm *hw_cdm;
  769. struct sde_hw_pingpong *hw_pp;
  770. struct sde_ctl_flush_cfg pending_flush = {0,};
  771. if (!phys_enc)
  772. return;
  773. wb_enc = to_sde_encoder_phys_wb(phys_enc);
  774. hw_wb = wb_enc->hw_wb;
  775. hw_cdm = phys_enc->hw_cdm;
  776. hw_pp = phys_enc->hw_pp;
  777. hw_ctl = phys_enc->hw_ctl;
  778. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  779. if (phys_enc->in_clone_mode) {
  780. SDE_DEBUG("in CWB mode. early return\n");
  781. return;
  782. }
  783. if (!hw_ctl) {
  784. SDE_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
  785. return;
  786. }
  787. if (hw_ctl->ops.update_bitmask_wb)
  788. hw_ctl->ops.update_bitmask_wb(hw_ctl, hw_wb->idx, 1);
  789. if (hw_ctl->ops.update_bitmask_cdm && hw_cdm)
  790. hw_ctl->ops.update_bitmask_cdm(hw_ctl, hw_cdm->idx, 1);
  791. if (hw_ctl->ops.update_bitmask_merge3d && hw_pp && hw_pp->merge_3d)
  792. hw_ctl->ops.update_bitmask_merge3d(hw_ctl,
  793. hw_pp->merge_3d->idx, 1);
  794. if (hw_ctl->ops.get_pending_flush)
  795. hw_ctl->ops.get_pending_flush(hw_ctl,
  796. &pending_flush);
  797. SDE_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
  798. hw_ctl->idx - CTL_0, pending_flush.pending_flush_mask,
  799. hw_wb->idx - WB_0);
  800. }
  801. /**
  802. * sde_encoder_phys_wb_setup - setup writeback encoder
  803. * @phys_enc: Pointer to physical encoder
  804. */
  805. static void sde_encoder_phys_wb_setup(
  806. struct sde_encoder_phys *phys_enc)
  807. {
  808. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  809. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  810. struct drm_display_mode mode = phys_enc->cached_mode;
  811. struct drm_framebuffer *fb;
  812. struct sde_rect *wb_roi = &wb_enc->wb_roi;
  813. SDE_DEBUG("[mode_set:%d,%d,\"%s\",%d,%d]\n",
  814. hw_wb->idx - WB_0, mode.base.id, mode.name,
  815. mode.hdisplay, mode.vdisplay);
  816. memset(wb_roi, 0, sizeof(struct sde_rect));
  817. /* clear writeback framebuffer - will be updated in setup_fb */
  818. wb_enc->wb_fb = NULL;
  819. wb_enc->wb_aspace = NULL;
  820. if (phys_enc->enable_state == SDE_ENC_DISABLING) {
  821. fb = wb_enc->fb_disable;
  822. wb_roi->w = 0;
  823. wb_roi->h = 0;
  824. } else {
  825. fb = sde_wb_get_output_fb(wb_enc->wb_dev);
  826. sde_wb_get_output_roi(wb_enc->wb_dev, wb_roi);
  827. }
  828. if (!fb) {
  829. SDE_DEBUG("no output framebuffer\n");
  830. return;
  831. }
  832. SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
  833. fb->width, fb->height);
  834. if (wb_roi->w == 0 || wb_roi->h == 0) {
  835. wb_roi->x = 0;
  836. wb_roi->y = 0;
  837. wb_roi->w = fb->width;
  838. wb_roi->h = fb->height;
  839. }
  840. SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi->x, wb_roi->y,
  841. wb_roi->w, wb_roi->h);
  842. wb_enc->wb_fmt = sde_get_sde_format_ext(fb->format->format,
  843. fb->modifier);
  844. if (!wb_enc->wb_fmt) {
  845. SDE_ERROR("unsupported output pixel format: %d\n",
  846. fb->format->format);
  847. return;
  848. }
  849. SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->format->format,
  850. fb->modifier);
  851. sde_encoder_phys_wb_set_ot_limit(phys_enc);
  852. sde_encoder_phys_wb_set_qos_remap(phys_enc);
  853. sde_encoder_phys_wb_set_qos(phys_enc);
  854. sde_encoder_phys_setup_cdm(phys_enc, fb, wb_enc->wb_fmt, wb_roi);
  855. sde_encoder_phys_wb_setup_fb(phys_enc, fb, wb_roi);
  856. sde_encoder_phys_wb_setup_cdp(phys_enc, wb_enc->wb_fmt);
  857. _sde_encoder_phys_wb_setup_cwb(phys_enc, true);
  858. }
  859. static void _sde_encoder_phys_wb_frame_done_helper(void *arg, bool frame_error)
  860. {
  861. struct sde_encoder_phys_wb *wb_enc = arg;
  862. struct sde_encoder_phys *phys_enc = &wb_enc->base;
  863. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  864. u32 event = frame_error ? SDE_ENCODER_FRAME_EVENT_ERROR : 0;
  865. SDE_DEBUG("[wb:%d,%u]\n", hw_wb->idx - WB_0, wb_enc->frame_count);
  866. /* don't notify upper layer for internal commit */
  867. if (phys_enc->enable_state == SDE_ENC_DISABLING)
  868. goto complete;
  869. if (phys_enc->parent_ops.handle_frame_done &&
  870. atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0)) {
  871. event |= SDE_ENCODER_FRAME_EVENT_DONE |
  872. SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE;
  873. if (!phys_enc->in_clone_mode)
  874. event |= SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  875. phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
  876. phys_enc, event);
  877. }
  878. if (phys_enc->parent_ops.handle_vblank_virt)
  879. phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
  880. phys_enc);
  881. SDE_EVT32_IRQ(DRMID(phys_enc->parent), hw_wb->idx - WB_0, event,
  882. frame_error);
  883. complete:
  884. wake_up_all(&phys_enc->pending_kickoff_wq);
  885. }
  886. /**
  887. * sde_encoder_phys_wb_done_irq - Pingpong overflow interrupt handler for CWB
  888. * @arg: Pointer to writeback encoder
  889. * @irq_idx: interrupt index
  890. */
  891. static void sde_encoder_phys_cwb_ovflow(void *arg, int irq_idx)
  892. {
  893. _sde_encoder_phys_wb_frame_done_helper(arg, true);
  894. }
  895. /**
  896. * sde_encoder_phys_wb_done_irq - writeback interrupt handler
  897. * @arg: Pointer to writeback encoder
  898. * @irq_idx: interrupt index
  899. */
  900. static void sde_encoder_phys_wb_done_irq(void *arg, int irq_idx)
  901. {
  902. _sde_encoder_phys_wb_frame_done_helper(arg, false);
  903. }
  904. /**
  905. * sde_encoder_phys_wb_irq_ctrl - irq control of WB
  906. * @phys: Pointer to physical encoder
  907. * @enable: indicates enable or disable interrupts
  908. */
  909. static void sde_encoder_phys_wb_irq_ctrl(
  910. struct sde_encoder_phys *phys, bool enable)
  911. {
  912. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys);
  913. int index = 0, refcount;
  914. int ret = 0, pp = 0;
  915. if (!wb_enc)
  916. return;
  917. if (wb_enc->bypass_irqreg)
  918. return;
  919. pp = phys->hw_pp->idx - PINGPONG_0;
  920. if ((pp + CRTC_DUAL_MIXERS) >= PINGPONG_MAX) {
  921. SDE_ERROR("invalid pingpong index for WB or CWB\n");
  922. return;
  923. }
  924. refcount = atomic_read(&phys->wbirq_refcount);
  925. if (enable && atomic_inc_return(&phys->wbirq_refcount) == 1) {
  926. sde_encoder_helper_register_irq(phys, INTR_IDX_WB_DONE);
  927. if (ret)
  928. atomic_dec_return(&phys->wbirq_refcount);
  929. for (index = 0; index < CRTC_DUAL_MIXERS; index++)
  930. if (cwb_irq_tbl[index + pp] != SDE_NONE)
  931. sde_encoder_helper_register_irq(phys,
  932. cwb_irq_tbl[index + pp]);
  933. } else if (!enable &&
  934. atomic_dec_return(&phys->wbirq_refcount) == 0) {
  935. sde_encoder_helper_unregister_irq(phys, INTR_IDX_WB_DONE);
  936. if (ret)
  937. atomic_inc_return(&phys->wbirq_refcount);
  938. for (index = 0; index < CRTC_DUAL_MIXERS; index++)
  939. if (cwb_irq_tbl[index + pp] != SDE_NONE)
  940. sde_encoder_helper_unregister_irq(phys,
  941. cwb_irq_tbl[index + pp]);
  942. }
  943. }
  944. /**
  945. * sde_encoder_phys_wb_mode_set - set display mode
  946. * @phys_enc: Pointer to physical encoder
  947. * @mode: Pointer to requested display mode
  948. * @adj_mode: Pointer to adjusted display mode
  949. */
  950. static void sde_encoder_phys_wb_mode_set(
  951. struct sde_encoder_phys *phys_enc,
  952. struct drm_display_mode *mode,
  953. struct drm_display_mode *adj_mode)
  954. {
  955. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  956. struct sde_rm *rm = &phys_enc->sde_kms->rm;
  957. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  958. struct sde_rm_hw_iter iter;
  959. int i, instance;
  960. phys_enc->cached_mode = *adj_mode;
  961. instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
  962. SDE_DEBUG("[mode_set_cache:%d,%d,\"%s\",%d,%d]\n",
  963. hw_wb->idx - WB_0, mode->base.id,
  964. mode->name, mode->hdisplay, mode->vdisplay);
  965. phys_enc->hw_ctl = NULL;
  966. phys_enc->hw_cdm = NULL;
  967. /* Retrieve previously allocated HW Resources. CTL shouldn't fail */
  968. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
  969. for (i = 0; i <= instance; i++) {
  970. sde_rm_get_hw(rm, &iter);
  971. if (i == instance)
  972. phys_enc->hw_ctl = (struct sde_hw_ctl *) iter.hw;
  973. }
  974. if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
  975. SDE_ERROR("failed init ctl: %ld\n",
  976. (!phys_enc->hw_ctl) ?
  977. -EINVAL : PTR_ERR(phys_enc->hw_ctl));
  978. phys_enc->hw_ctl = NULL;
  979. return;
  980. }
  981. /* CDM is optional */
  982. sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CDM);
  983. for (i = 0; i <= instance; i++) {
  984. sde_rm_get_hw(rm, &iter);
  985. if (i == instance)
  986. phys_enc->hw_cdm = (struct sde_hw_cdm *) iter.hw;
  987. }
  988. if (IS_ERR(phys_enc->hw_cdm)) {
  989. SDE_ERROR("CDM required but not allocated: %ld\n",
  990. PTR_ERR(phys_enc->hw_cdm));
  991. phys_enc->hw_cdm = NULL;
  992. }
  993. }
  994. static int sde_encoder_phys_wb_frame_timeout(struct sde_encoder_phys *phys_enc)
  995. {
  996. u32 event = 0;
  997. while (atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0) &&
  998. phys_enc->parent_ops.handle_frame_done) {
  999. event = SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE
  1000. | SDE_ENCODER_FRAME_EVENT_ERROR;
  1001. if (!phys_enc->in_clone_mode)
  1002. event |= SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
  1003. phys_enc->parent_ops.handle_frame_done(
  1004. phys_enc->parent, phys_enc, event);
  1005. SDE_EVT32(DRMID(phys_enc->parent), event,
  1006. atomic_read(&phys_enc->pending_retire_fence_cnt));
  1007. }
  1008. return event;
  1009. }
  1010. static int _sde_encoder_phys_wb_wait_for_commit_done(
  1011. struct sde_encoder_phys *phys_enc, bool is_disable)
  1012. {
  1013. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1014. u32 event = 0;
  1015. u64 wb_time = 0;
  1016. int rc = 0;
  1017. struct sde_encoder_wait_info wait_info;
  1018. /* Return EWOULDBLOCK since we know the wait isn't necessary */
  1019. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  1020. SDE_ERROR("encoder already disabled\n");
  1021. return -EWOULDBLOCK;
  1022. }
  1023. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
  1024. wb_enc->kickoff_count, !!wb_enc->wb_fb, is_disable,
  1025. phys_enc->in_clone_mode);
  1026. if (!is_disable && phys_enc->in_clone_mode &&
  1027. (atomic_read(&phys_enc->pending_retire_fence_cnt) <= 1))
  1028. goto skip_wait;
  1029. /* signal completion if commit with no framebuffer */
  1030. if (!wb_enc->wb_fb) {
  1031. SDE_DEBUG("no output framebuffer\n");
  1032. _sde_encoder_phys_wb_frame_done_helper(wb_enc, false);
  1033. }
  1034. wait_info.wq = &phys_enc->pending_kickoff_wq;
  1035. wait_info.atomic_cnt = &phys_enc->pending_retire_fence_cnt;
  1036. wait_info.timeout_ms = max_t(u32, wb_enc->wbdone_timeout,
  1037. KICKOFF_TIMEOUT_MS);
  1038. rc = sde_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_WB_DONE,
  1039. &wait_info);
  1040. if (rc == -ETIMEDOUT) {
  1041. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1042. wb_enc->frame_count, SDE_EVTLOG_ERROR);
  1043. SDE_ERROR("wb:%d kickoff timed out\n", WBID(wb_enc));
  1044. event = sde_encoder_phys_wb_frame_timeout(phys_enc);
  1045. }
  1046. /* cleanup writeback framebuffer */
  1047. if (wb_enc->wb_fb && wb_enc->wb_aspace) {
  1048. msm_framebuffer_cleanup(wb_enc->wb_fb, wb_enc->wb_aspace);
  1049. wb_enc->wb_fb = NULL;
  1050. wb_enc->wb_aspace = NULL;
  1051. }
  1052. skip_wait:
  1053. /* remove vote for iommu/clk/bus */
  1054. wb_enc->frame_count++;
  1055. if (!rc) {
  1056. wb_enc->end_time = ktime_get();
  1057. wb_time = (u64)ktime_to_us(wb_enc->end_time) -
  1058. (u64)ktime_to_us(wb_enc->start_time);
  1059. SDE_DEBUG("wb:%d took %llu us\n", WBID(wb_enc), wb_time);
  1060. }
  1061. /* cleanup previous buffer if pending */
  1062. if (wb_enc->cwb_old_fb && wb_enc->cwb_old_aspace) {
  1063. msm_framebuffer_cleanup(wb_enc->cwb_old_fb, wb_enc->cwb_old_aspace);
  1064. wb_enc->cwb_old_fb = NULL;
  1065. wb_enc->cwb_old_aspace = NULL;
  1066. }
  1067. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
  1068. wb_time, event, rc);
  1069. return rc;
  1070. }
  1071. /**
  1072. * sde_encoder_phys_wb_wait_for_commit_done - wait until request is committed
  1073. * @phys_enc: Pointer to physical encoder
  1074. */
  1075. static int sde_encoder_phys_wb_wait_for_commit_done(
  1076. struct sde_encoder_phys *phys_enc)
  1077. {
  1078. return _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, false);
  1079. }
  1080. /**
  1081. * sde_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
  1082. * @phys_enc: Pointer to physical encoder
  1083. * @params: kickoff parameters
  1084. * Returns: Zero on success
  1085. */
  1086. static int sde_encoder_phys_wb_prepare_for_kickoff(
  1087. struct sde_encoder_phys *phys_enc,
  1088. struct sde_encoder_kickoff_params *params)
  1089. {
  1090. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1091. SDE_DEBUG("[wb:%d,%u]\n", wb_enc->hw_wb->idx - WB_0,
  1092. wb_enc->kickoff_count);
  1093. if (phys_enc->in_clone_mode) {
  1094. wb_enc->cwb_old_fb = wb_enc->wb_fb;
  1095. wb_enc->cwb_old_aspace = wb_enc->wb_aspace;
  1096. }
  1097. wb_enc->kickoff_count++;
  1098. /* set OT limit & enable traffic shaper */
  1099. sde_encoder_phys_wb_setup(phys_enc);
  1100. _sde_encoder_phys_wb_update_flush(phys_enc);
  1101. _sde_encoder_phys_wb_update_cwb_flush(phys_enc);
  1102. /* vote for iommu/clk/bus */
  1103. wb_enc->start_time = ktime_get();
  1104. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1105. wb_enc->kickoff_count, wb_enc->frame_count,
  1106. phys_enc->in_clone_mode);
  1107. return 0;
  1108. }
  1109. /**
  1110. * sde_encoder_phys_wb_trigger_flush - trigger flush processing
  1111. * @phys_enc: Pointer to physical encoder
  1112. */
  1113. static void sde_encoder_phys_wb_trigger_flush(struct sde_encoder_phys *phys_enc)
  1114. {
  1115. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1116. if (!phys_enc || !wb_enc->hw_wb) {
  1117. SDE_ERROR("invalid encoder\n");
  1118. return;
  1119. }
  1120. /*
  1121. * Bail out iff in CWB mode. In case of CWB, primary control-path
  1122. * which is actually driving would trigger the flush
  1123. */
  1124. if (phys_enc->in_clone_mode) {
  1125. SDE_DEBUG("in CWB mode. early return\n");
  1126. return;
  1127. }
  1128. SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
  1129. /* clear pending flush if commit with no framebuffer */
  1130. if (!wb_enc->wb_fb) {
  1131. SDE_DEBUG("no output framebuffer\n");
  1132. return;
  1133. }
  1134. sde_encoder_helper_trigger_flush(phys_enc);
  1135. }
  1136. /**
  1137. * sde_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
  1138. * @phys_enc: Pointer to physical encoder
  1139. */
  1140. static void sde_encoder_phys_wb_handle_post_kickoff(
  1141. struct sde_encoder_phys *phys_enc)
  1142. {
  1143. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1144. SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
  1145. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc));
  1146. }
  1147. /**
  1148. * _sde_encoder_phys_wb_init_internal_fb - create fb for internal commit
  1149. * @wb_enc: Pointer to writeback encoder
  1150. * @pixel_format: DRM pixel format
  1151. * @width: Desired fb width
  1152. * @height: Desired fb height
  1153. * @pitch: Desired fb pitch
  1154. */
  1155. static int _sde_encoder_phys_wb_init_internal_fb(
  1156. struct sde_encoder_phys_wb *wb_enc,
  1157. uint32_t pixel_format, uint32_t width,
  1158. uint32_t height, uint32_t pitch)
  1159. {
  1160. struct drm_device *dev;
  1161. struct drm_framebuffer *fb;
  1162. struct drm_mode_fb_cmd2 mode_cmd;
  1163. uint32_t size;
  1164. int nplanes, i, ret;
  1165. struct msm_gem_address_space *aspace;
  1166. if (!wb_enc || !wb_enc->base.parent || !wb_enc->base.sde_kms) {
  1167. SDE_ERROR("invalid params\n");
  1168. return -EINVAL;
  1169. }
  1170. aspace = wb_enc->base.sde_kms->aspace[SDE_IOMMU_DOMAIN_UNSECURE];
  1171. if (!aspace) {
  1172. SDE_ERROR("invalid address space\n");
  1173. return -EINVAL;
  1174. }
  1175. dev = wb_enc->base.sde_kms->dev;
  1176. if (!dev) {
  1177. SDE_ERROR("invalid dev\n");
  1178. return -EINVAL;
  1179. }
  1180. memset(&mode_cmd, 0, sizeof(mode_cmd));
  1181. mode_cmd.pixel_format = pixel_format;
  1182. mode_cmd.width = width;
  1183. mode_cmd.height = height;
  1184. mode_cmd.pitches[0] = pitch;
  1185. size = sde_format_get_framebuffer_size(pixel_format,
  1186. mode_cmd.width, mode_cmd.height,
  1187. mode_cmd.pitches, 0);
  1188. if (!size) {
  1189. SDE_DEBUG("not creating zero size buffer\n");
  1190. return -EINVAL;
  1191. }
  1192. /* allocate gem tracking object */
  1193. nplanes = drm_format_num_planes(pixel_format);
  1194. if (nplanes >= SDE_MAX_PLANES) {
  1195. SDE_ERROR("requested format has too many planes\n");
  1196. return -EINVAL;
  1197. }
  1198. wb_enc->bo_disable[0] = msm_gem_new(dev, size,
  1199. MSM_BO_SCANOUT | MSM_BO_WC);
  1200. if (IS_ERR_OR_NULL(wb_enc->bo_disable[0])) {
  1201. ret = PTR_ERR(wb_enc->bo_disable[0]);
  1202. wb_enc->bo_disable[0] = NULL;
  1203. SDE_ERROR("failed to create bo, %d\n", ret);
  1204. return ret;
  1205. }
  1206. for (i = 0; i < nplanes; ++i) {
  1207. wb_enc->bo_disable[i] = wb_enc->bo_disable[0];
  1208. mode_cmd.pitches[i] = width *
  1209. drm_format_plane_cpp(pixel_format, i);
  1210. }
  1211. fb = msm_framebuffer_init(dev, &mode_cmd, wb_enc->bo_disable);
  1212. if (IS_ERR_OR_NULL(fb)) {
  1213. ret = PTR_ERR(fb);
  1214. drm_gem_object_put(wb_enc->bo_disable[0]);
  1215. wb_enc->bo_disable[0] = NULL;
  1216. SDE_ERROR("failed to init fb, %d\n", ret);
  1217. return ret;
  1218. }
  1219. /* prepare the backing buffer now so that it's available later */
  1220. ret = msm_framebuffer_prepare(fb, aspace);
  1221. if (!ret)
  1222. wb_enc->fb_disable = fb;
  1223. return ret;
  1224. }
  1225. /**
  1226. * _sde_encoder_phys_wb_destroy_internal_fb - deconstruct internal fb
  1227. * @wb_enc: Pointer to writeback encoder
  1228. */
  1229. static void _sde_encoder_phys_wb_destroy_internal_fb(
  1230. struct sde_encoder_phys_wb *wb_enc)
  1231. {
  1232. if (!wb_enc)
  1233. return;
  1234. if (wb_enc->fb_disable) {
  1235. drm_framebuffer_unregister_private(wb_enc->fb_disable);
  1236. drm_framebuffer_remove(wb_enc->fb_disable);
  1237. wb_enc->fb_disable = NULL;
  1238. }
  1239. if (wb_enc->bo_disable[0]) {
  1240. drm_gem_object_put(wb_enc->bo_disable[0]);
  1241. wb_enc->bo_disable[0] = NULL;
  1242. }
  1243. }
  1244. /**
  1245. * sde_encoder_phys_wb_enable - enable writeback encoder
  1246. * @phys_enc: Pointer to physical encoder
  1247. */
  1248. static void sde_encoder_phys_wb_enable(struct sde_encoder_phys *phys_enc)
  1249. {
  1250. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1251. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1252. struct drm_device *dev;
  1253. struct drm_connector *connector;
  1254. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1255. if (!wb_enc->base.parent || !wb_enc->base.parent->dev) {
  1256. SDE_ERROR("invalid drm device\n");
  1257. return;
  1258. }
  1259. dev = wb_enc->base.parent->dev;
  1260. /* find associated writeback connector */
  1261. connector = phys_enc->connector;
  1262. if (!connector || connector->encoder != phys_enc->parent) {
  1263. SDE_ERROR("failed to find writeback connector\n");
  1264. return;
  1265. }
  1266. wb_enc->wb_dev = sde_wb_connector_get_wb(connector);
  1267. phys_enc->enable_state = SDE_ENC_ENABLED;
  1268. /*
  1269. * cache the crtc in wb_enc on enable for duration of use case
  1270. * for correctly servicing asynchronous irq events and timers
  1271. */
  1272. wb_enc->crtc = phys_enc->parent->crtc;
  1273. }
  1274. /**
  1275. * sde_encoder_phys_wb_disable - disable writeback encoder
  1276. * @phys_enc: Pointer to physical encoder
  1277. */
  1278. static void sde_encoder_phys_wb_disable(struct sde_encoder_phys *phys_enc)
  1279. {
  1280. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1281. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1282. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1283. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  1284. SDE_ERROR("encoder is already disabled\n");
  1285. return;
  1286. }
  1287. SDE_DEBUG("[wait_for_done: wb:%d, frame:%u, kickoff:%u]\n",
  1288. hw_wb->idx - WB_0, wb_enc->frame_count,
  1289. wb_enc->kickoff_count);
  1290. _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, true);
  1291. if (!phys_enc->hw_ctl || !phys_enc->parent ||
  1292. !phys_enc->sde_kms || !wb_enc->fb_disable) {
  1293. SDE_DEBUG("invalid enc, skipping extra commit\n");
  1294. goto exit;
  1295. }
  1296. /* avoid reset frame for CWB */
  1297. if (phys_enc->in_clone_mode) {
  1298. _sde_encoder_phys_wb_setup_cwb(phys_enc, false);
  1299. phys_enc->in_clone_mode = false;
  1300. goto exit;
  1301. }
  1302. /* reset h/w before final flush */
  1303. if (phys_enc->hw_ctl->ops.clear_pending_flush)
  1304. phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
  1305. /*
  1306. * New CTL reset sequence from 5.0 MDP onwards.
  1307. * If has_3d_merge_reset is not set, legacy reset
  1308. * sequence is executed.
  1309. */
  1310. if (hw_wb->catalog->has_3d_merge_reset) {
  1311. sde_encoder_helper_phys_disable(phys_enc, wb_enc);
  1312. goto exit;
  1313. }
  1314. if (sde_encoder_helper_reset_mixers(phys_enc, NULL))
  1315. goto exit;
  1316. phys_enc->enable_state = SDE_ENC_DISABLING;
  1317. sde_encoder_phys_wb_prepare_for_kickoff(phys_enc, NULL);
  1318. sde_encoder_phys_wb_irq_ctrl(phys_enc, true);
  1319. if (phys_enc->hw_ctl->ops.trigger_flush)
  1320. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  1321. sde_encoder_helper_trigger_start(phys_enc);
  1322. _sde_encoder_phys_wb_wait_for_commit_done(phys_enc, true);
  1323. sde_encoder_phys_wb_irq_ctrl(phys_enc, false);
  1324. exit:
  1325. /*
  1326. * frame count and kickoff count are only used for debug purpose. Frame
  1327. * count can be more than kickoff count at the end of disable call due
  1328. * to extra frame_done wait. It does not cause any issue because
  1329. * frame_done wait is based on retire_fence count. Leaving these
  1330. * counters for debugging purpose.
  1331. */
  1332. if (wb_enc->frame_count != wb_enc->kickoff_count) {
  1333. SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
  1334. wb_enc->kickoff_count, wb_enc->frame_count,
  1335. phys_enc->in_clone_mode);
  1336. wb_enc->frame_count = wb_enc->kickoff_count;
  1337. }
  1338. phys_enc->enable_state = SDE_ENC_DISABLED;
  1339. wb_enc->crtc = NULL;
  1340. }
  1341. /**
  1342. * sde_encoder_phys_wb_get_hw_resources - get hardware resources
  1343. * @phys_enc: Pointer to physical encoder
  1344. * @hw_res: Pointer to encoder resources
  1345. */
  1346. static void sde_encoder_phys_wb_get_hw_resources(
  1347. struct sde_encoder_phys *phys_enc,
  1348. struct sde_encoder_hw_resources *hw_res,
  1349. struct drm_connector_state *conn_state)
  1350. {
  1351. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1352. struct sde_hw_wb *hw_wb;
  1353. struct drm_framebuffer *fb;
  1354. const struct sde_format *fmt = NULL;
  1355. if (!phys_enc) {
  1356. SDE_ERROR("invalid encoder\n");
  1357. return;
  1358. }
  1359. fb = sde_wb_connector_state_get_output_fb(conn_state);
  1360. if (fb) {
  1361. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  1362. if (!fmt) {
  1363. SDE_ERROR("unsupported output pixel format:%d\n",
  1364. fb->format->format);
  1365. return;
  1366. }
  1367. }
  1368. hw_wb = wb_enc->hw_wb;
  1369. hw_res->wbs[hw_wb->idx - WB_0] = phys_enc->intf_mode;
  1370. hw_res->needs_cdm = fmt ? SDE_FORMAT_IS_YUV(fmt) : false;
  1371. SDE_DEBUG("[wb:%d] intf_mode=%d needs_cdm=%d\n", hw_wb->idx - WB_0,
  1372. hw_res->wbs[hw_wb->idx - WB_0],
  1373. hw_res->needs_cdm);
  1374. }
  1375. #ifdef CONFIG_DEBUG_FS
  1376. /**
  1377. * sde_encoder_phys_wb_init_debugfs - initialize writeback encoder debugfs
  1378. * @phys_enc: Pointer to physical encoder
  1379. * @debugfs_root: Pointer to virtual encoder's debugfs_root dir
  1380. */
  1381. static int sde_encoder_phys_wb_init_debugfs(
  1382. struct sde_encoder_phys *phys_enc, struct dentry *debugfs_root)
  1383. {
  1384. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1385. if (!phys_enc || !wb_enc->hw_wb || !debugfs_root)
  1386. return -EINVAL;
  1387. if (!debugfs_create_u32("wbdone_timeout", 0600,
  1388. debugfs_root, &wb_enc->wbdone_timeout)) {
  1389. SDE_ERROR("failed to create debugfs/wbdone_timeout\n");
  1390. return -ENOMEM;
  1391. }
  1392. return 0;
  1393. }
  1394. #else
  1395. static int sde_encoder_phys_wb_init_debugfs(
  1396. struct sde_encoder_phys *phys_enc, struct dentry *debugfs_root)
  1397. {
  1398. return 0;
  1399. }
  1400. #endif
  1401. static int sde_encoder_phys_wb_late_register(struct sde_encoder_phys *phys_enc,
  1402. struct dentry *debugfs_root)
  1403. {
  1404. return sde_encoder_phys_wb_init_debugfs(phys_enc, debugfs_root);
  1405. }
  1406. /**
  1407. * sde_encoder_phys_wb_destroy - destroy writeback encoder
  1408. * @phys_enc: Pointer to physical encoder
  1409. */
  1410. static void sde_encoder_phys_wb_destroy(struct sde_encoder_phys *phys_enc)
  1411. {
  1412. struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
  1413. struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
  1414. SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
  1415. if (!phys_enc)
  1416. return;
  1417. _sde_encoder_phys_wb_destroy_internal_fb(wb_enc);
  1418. kfree(wb_enc);
  1419. }
  1420. /**
  1421. * sde_encoder_phys_wb_init_ops - initialize writeback operations
  1422. * @ops: Pointer to encoder operation table
  1423. */
  1424. static void sde_encoder_phys_wb_init_ops(struct sde_encoder_phys_ops *ops)
  1425. {
  1426. ops->late_register = sde_encoder_phys_wb_late_register;
  1427. ops->is_master = sde_encoder_phys_wb_is_master;
  1428. ops->mode_set = sde_encoder_phys_wb_mode_set;
  1429. ops->enable = sde_encoder_phys_wb_enable;
  1430. ops->disable = sde_encoder_phys_wb_disable;
  1431. ops->destroy = sde_encoder_phys_wb_destroy;
  1432. ops->atomic_check = sde_encoder_phys_wb_atomic_check;
  1433. ops->get_hw_resources = sde_encoder_phys_wb_get_hw_resources;
  1434. ops->wait_for_commit_done = sde_encoder_phys_wb_wait_for_commit_done;
  1435. ops->prepare_for_kickoff = sde_encoder_phys_wb_prepare_for_kickoff;
  1436. ops->handle_post_kickoff = sde_encoder_phys_wb_handle_post_kickoff;
  1437. ops->trigger_flush = sde_encoder_phys_wb_trigger_flush;
  1438. ops->trigger_start = sde_encoder_helper_trigger_start;
  1439. ops->hw_reset = sde_encoder_helper_hw_reset;
  1440. ops->irq_control = sde_encoder_phys_wb_irq_ctrl;
  1441. }
  1442. /**
  1443. * sde_encoder_phys_wb_init - initialize writeback encoder
  1444. * @init: Pointer to init info structure with initialization params
  1445. */
  1446. struct sde_encoder_phys *sde_encoder_phys_wb_init(
  1447. struct sde_enc_phys_init_params *p)
  1448. {
  1449. struct sde_encoder_phys *phys_enc;
  1450. struct sde_encoder_phys_wb *wb_enc;
  1451. struct sde_hw_mdp *hw_mdp;
  1452. struct sde_encoder_irq *irq;
  1453. int ret = 0;
  1454. SDE_DEBUG("\n");
  1455. if (!p || !p->parent) {
  1456. SDE_ERROR("invalid params\n");
  1457. ret = -EINVAL;
  1458. goto fail_alloc;
  1459. }
  1460. wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL);
  1461. if (!wb_enc) {
  1462. SDE_ERROR("failed to allocate wb enc\n");
  1463. ret = -ENOMEM;
  1464. goto fail_alloc;
  1465. }
  1466. wb_enc->wbdone_timeout = KICKOFF_TIMEOUT_MS;
  1467. phys_enc = &wb_enc->base;
  1468. if (p->sde_kms->vbif[VBIF_NRT]) {
  1469. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE] =
  1470. p->sde_kms->aspace[MSM_SMMU_DOMAIN_NRT_UNSECURE];
  1471. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] =
  1472. p->sde_kms->aspace[MSM_SMMU_DOMAIN_NRT_SECURE];
  1473. } else {
  1474. wb_enc->aspace[SDE_IOMMU_DOMAIN_UNSECURE] =
  1475. p->sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  1476. wb_enc->aspace[SDE_IOMMU_DOMAIN_SECURE] =
  1477. p->sde_kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  1478. }
  1479. hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
  1480. if (IS_ERR_OR_NULL(hw_mdp)) {
  1481. ret = PTR_ERR(hw_mdp);
  1482. SDE_ERROR("failed to init hw_top: %d\n", ret);
  1483. goto fail_mdp_init;
  1484. }
  1485. phys_enc->hw_mdptop = hw_mdp;
  1486. /**
  1487. * hw_wb resource permanently assigned to this encoder
  1488. * Other resources allocated at atomic commit time by use case
  1489. */
  1490. if (p->wb_idx != SDE_NONE) {
  1491. struct sde_rm_hw_iter iter;
  1492. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_WB);
  1493. while (sde_rm_get_hw(&p->sde_kms->rm, &iter)) {
  1494. struct sde_hw_wb *hw_wb = (struct sde_hw_wb *)iter.hw;
  1495. if (hw_wb->idx == p->wb_idx) {
  1496. wb_enc->hw_wb = hw_wb;
  1497. break;
  1498. }
  1499. }
  1500. if (!wb_enc->hw_wb) {
  1501. ret = -EINVAL;
  1502. SDE_ERROR("failed to init hw_wb%d\n", p->wb_idx - WB_0);
  1503. goto fail_wb_init;
  1504. }
  1505. } else {
  1506. ret = -EINVAL;
  1507. SDE_ERROR("invalid wb_idx\n");
  1508. goto fail_wb_check;
  1509. }
  1510. sde_encoder_phys_wb_init_ops(&phys_enc->ops);
  1511. phys_enc->parent = p->parent;
  1512. phys_enc->parent_ops = p->parent_ops;
  1513. phys_enc->sde_kms = p->sde_kms;
  1514. phys_enc->split_role = p->split_role;
  1515. phys_enc->intf_mode = INTF_MODE_WB_LINE;
  1516. phys_enc->intf_idx = p->intf_idx;
  1517. phys_enc->enc_spinlock = p->enc_spinlock;
  1518. phys_enc->vblank_ctl_lock = p->vblank_ctl_lock;
  1519. atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
  1520. atomic_set(&phys_enc->wbirq_refcount, 0);
  1521. init_waitqueue_head(&phys_enc->pending_kickoff_wq);
  1522. irq = &phys_enc->irq[INTR_IDX_WB_DONE];
  1523. INIT_LIST_HEAD(&irq->cb.list);
  1524. irq->name = "wb_done";
  1525. irq->hw_idx = wb_enc->hw_wb->idx;
  1526. irq->irq_idx = -1;
  1527. irq->intr_type = sde_encoder_phys_wb_get_intr_type(wb_enc->hw_wb);
  1528. irq->intr_idx = INTR_IDX_WB_DONE;
  1529. irq->cb.arg = wb_enc;
  1530. irq->cb.func = sde_encoder_phys_wb_done_irq;
  1531. irq = &phys_enc->irq[INTR_IDX_PP1_OVFL];
  1532. INIT_LIST_HEAD(&irq->cb.list);
  1533. irq->name = "pp1_overflow";
  1534. irq->hw_idx = CWB_1;
  1535. irq->irq_idx = -1;
  1536. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1537. irq->intr_idx = INTR_IDX_PP1_OVFL;
  1538. irq->cb.arg = wb_enc;
  1539. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1540. irq = &phys_enc->irq[INTR_IDX_PP2_OVFL];
  1541. INIT_LIST_HEAD(&irq->cb.list);
  1542. irq->name = "pp2_overflow";
  1543. irq->hw_idx = CWB_2;
  1544. irq->irq_idx = -1;
  1545. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1546. irq->intr_idx = INTR_IDX_PP2_OVFL;
  1547. irq->cb.arg = wb_enc;
  1548. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1549. irq = &phys_enc->irq[INTR_IDX_PP3_OVFL];
  1550. INIT_LIST_HEAD(&irq->cb.list);
  1551. irq->name = "pp3_overflow";
  1552. irq->hw_idx = CWB_3;
  1553. irq->irq_idx = -1;
  1554. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1555. irq->intr_idx = INTR_IDX_PP3_OVFL;
  1556. irq->cb.arg = wb_enc;
  1557. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1558. irq = &phys_enc->irq[INTR_IDX_PP4_OVFL];
  1559. INIT_LIST_HEAD(&irq->cb.list);
  1560. irq->name = "pp4_overflow";
  1561. irq->hw_idx = CWB_4;
  1562. irq->irq_idx = -1;
  1563. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1564. irq->intr_idx = INTR_IDX_PP4_OVFL;
  1565. irq->cb.arg = wb_enc;
  1566. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1567. irq = &phys_enc->irq[INTR_IDX_PP5_OVFL];
  1568. INIT_LIST_HEAD(&irq->cb.list);
  1569. irq->name = "pp5_overflow";
  1570. irq->hw_idx = CWB_5;
  1571. irq->irq_idx = -1;
  1572. irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;
  1573. irq->intr_idx = INTR_IDX_PP5_OVFL;
  1574. irq->cb.arg = wb_enc;
  1575. irq->cb.func = sde_encoder_phys_cwb_ovflow;
  1576. /* create internal buffer for disable logic */
  1577. if (_sde_encoder_phys_wb_init_internal_fb(wb_enc,
  1578. DRM_FORMAT_RGB888, 2, 1, 6)) {
  1579. SDE_ERROR("failed to init internal fb\n");
  1580. goto fail_wb_init;
  1581. }
  1582. SDE_DEBUG("Created sde_encoder_phys_wb for wb %d\n",
  1583. wb_enc->hw_wb->idx - WB_0);
  1584. return phys_enc;
  1585. fail_wb_init:
  1586. fail_wb_check:
  1587. fail_mdp_init:
  1588. kfree(wb_enc);
  1589. fail_alloc:
  1590. return ERR_PTR(ret);
  1591. }