qcedev.c 74 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * QTI CE device driver.
  4. *
  5. * Copyright (c) 2010-2021, The Linux Foundation. All rights reserved.
  6. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  7. */
  8. #include <linux/mman.h>
  9. #include <linux/module.h>
  10. #include <linux/device.h>
  11. #include <linux/types.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/kernel.h>
  15. #include <linux/dmapool.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/init.h>
  19. #include <linux/module.h>
  20. #include <linux/fs.h>
  21. #include <linux/uaccess.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/scatterlist.h>
  24. #include <linux/crypto.h>
  25. #include "linux/qcedev.h"
  26. #include <linux/interconnect.h>
  27. #include <linux/delay.h>
  28. #include "linux/compat_qcedev.h"
  29. #include <crypto/hash.h>
  30. #include "qcedevi.h"
  31. #include "qce.h"
  32. #include "qcedev_smmu.h"
  33. #include "qcom_crypto_device.h"
  34. #include <linux/compat.h>
  35. #define CACHE_LINE_SIZE 64
  36. #define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
  37. #define MAX_CEHW_REQ_TRANSFER_SIZE (128*32*1024)
  38. /*
  39. * Max wait time once a crypto request is submitted.
  40. */
  41. #define MAX_CRYPTO_WAIT_TIME 1500
  42. /*
  43. * Max wait time once a offload crypto request is submitted.
  44. * This is low due to expected timeout and key pause errors.
  45. * This is temporary, and we can use the 1500 value once the
  46. * core irqs are enabled.
  47. */
  48. #define MAX_OFFLOAD_CRYPTO_WAIT_TIME 20
  49. #define MAX_REQUEST_TIME 5000
  50. enum qcedev_req_status {
  51. QCEDEV_REQ_CURRENT = 0,
  52. QCEDEV_REQ_WAITING = 1,
  53. QCEDEV_REQ_SUBMITTED = 2,
  54. QCEDEV_REQ_DONE = 3,
  55. };
  56. static uint8_t _std_init_vector_sha1_uint8[] = {
  57. 0x67, 0x45, 0x23, 0x01, 0xEF, 0xCD, 0xAB, 0x89,
  58. 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76,
  59. 0xC3, 0xD2, 0xE1, 0xF0
  60. };
  61. /* standard initialization vector for SHA-256, source: FIPS 180-2 */
  62. static uint8_t _std_init_vector_sha256_uint8[] = {
  63. 0x6A, 0x09, 0xE6, 0x67, 0xBB, 0x67, 0xAE, 0x85,
  64. 0x3C, 0x6E, 0xF3, 0x72, 0xA5, 0x4F, 0xF5, 0x3A,
  65. 0x51, 0x0E, 0x52, 0x7F, 0x9B, 0x05, 0x68, 0x8C,
  66. 0x1F, 0x83, 0xD9, 0xAB, 0x5B, 0xE0, 0xCD, 0x19
  67. };
  68. #define QCEDEV_CTX_KEY_MASK 0x000000ff
  69. #define QCEDEV_CTX_USE_HW_KEY 0x00000001
  70. #define QCEDEV_CTX_USE_PIPE_KEY 0x00000002
  71. static DEFINE_MUTEX(send_cmd_lock);
  72. static DEFINE_MUTEX(qcedev_sent_bw_req);
  73. static DEFINE_MUTEX(hash_access_lock);
  74. static dev_t qcedev_device_no;
  75. static struct class *driver_class;
  76. static struct device *class_dev;
  77. static const struct of_device_id qcedev_match[] = {
  78. { .compatible = "qcom,qcedev"},
  79. { .compatible = "qcom,qcedev,context-bank"},
  80. {}
  81. };
  82. MODULE_DEVICE_TABLE(of, qcedev_match);
  83. static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
  84. {
  85. unsigned int control_flag;
  86. int ret = 0;
  87. if (podev->ce_support.req_bw_before_clk) {
  88. if (enable)
  89. control_flag = QCE_BW_REQUEST_FIRST;
  90. else
  91. control_flag = QCE_CLK_DISABLE_FIRST;
  92. } else {
  93. if (enable)
  94. control_flag = QCE_CLK_ENABLE_FIRST;
  95. else
  96. control_flag = QCE_BW_REQUEST_RESET_FIRST;
  97. }
  98. switch (control_flag) {
  99. case QCE_CLK_ENABLE_FIRST:
  100. ret = qce_enable_clk(podev->qce);
  101. if (ret) {
  102. pr_err("%s Unable enable clk\n", __func__);
  103. return ret;
  104. }
  105. ret = icc_set_bw(podev->icc_path,
  106. podev->icc_avg_bw, podev->icc_peak_bw);
  107. if (ret) {
  108. pr_err("%s Unable to set high bw\n", __func__);
  109. ret = qce_disable_clk(podev->qce);
  110. if (ret)
  111. pr_err("%s Unable disable clk\n", __func__);
  112. return ret;
  113. }
  114. break;
  115. case QCE_BW_REQUEST_FIRST:
  116. ret = icc_set_bw(podev->icc_path,
  117. podev->icc_avg_bw, podev->icc_peak_bw);
  118. if (ret) {
  119. pr_err("%s Unable to set high bw\n", __func__);
  120. return ret;
  121. }
  122. ret = qce_enable_clk(podev->qce);
  123. if (ret) {
  124. pr_err("%s Unable enable clk\n", __func__);
  125. ret = icc_set_bw(podev->icc_path, 0, 0);
  126. if (ret)
  127. pr_err("%s Unable to set low bw\n", __func__);
  128. return ret;
  129. }
  130. break;
  131. case QCE_CLK_DISABLE_FIRST:
  132. ret = qce_disable_clk(podev->qce);
  133. if (ret) {
  134. pr_err("%s Unable to disable clk\n", __func__);
  135. return ret;
  136. }
  137. ret = icc_set_bw(podev->icc_path, 0, 0);
  138. if (ret) {
  139. pr_err("%s Unable to set low bw\n", __func__);
  140. ret = qce_enable_clk(podev->qce);
  141. if (ret)
  142. pr_err("%s Unable enable clk\n", __func__);
  143. return ret;
  144. }
  145. break;
  146. case QCE_BW_REQUEST_RESET_FIRST:
  147. ret = icc_set_bw(podev->icc_path, 0, 0);
  148. if (ret) {
  149. pr_err("%s Unable to set low bw\n", __func__);
  150. return ret;
  151. }
  152. ret = qce_disable_clk(podev->qce);
  153. if (ret) {
  154. pr_err("%s Unable to disable clk\n", __func__);
  155. ret = icc_set_bw(podev->icc_path,
  156. podev->icc_avg_bw, podev->icc_peak_bw);
  157. if (ret)
  158. pr_err("%s Unable to set high bw\n", __func__);
  159. return ret;
  160. }
  161. break;
  162. default:
  163. return -ENOENT;
  164. }
  165. return 0;
  166. }
  167. static void qcedev_ce_high_bw_req(struct qcedev_control *podev,
  168. bool high_bw_req)
  169. {
  170. int ret = 0;
  171. if(podev == NULL) return;
  172. mutex_lock(&qcedev_sent_bw_req);
  173. if (high_bw_req) {
  174. if (podev->high_bw_req_count == 0) {
  175. ret = qcedev_control_clocks(podev, true);
  176. if (ret)
  177. goto exit_unlock_mutex;
  178. ret = qce_set_irqs(podev->qce, true);
  179. if (ret) {
  180. pr_err("%s: could not enable bam irqs, ret = %d",
  181. __func__, ret);
  182. qcedev_control_clocks(podev, false);
  183. goto exit_unlock_mutex;
  184. }
  185. }
  186. podev->high_bw_req_count++;
  187. } else {
  188. if (podev->high_bw_req_count == 1) {
  189. ret = qce_set_irqs(podev->qce, false);
  190. if (ret) {
  191. pr_err("%s: could not disable bam irqs, ret = %d",
  192. __func__, ret);
  193. goto exit_unlock_mutex;
  194. }
  195. ret = qcedev_control_clocks(podev, false);
  196. if (ret)
  197. goto exit_unlock_mutex;
  198. }
  199. podev->high_bw_req_count--;
  200. }
  201. exit_unlock_mutex:
  202. mutex_unlock(&qcedev_sent_bw_req);
  203. }
  204. #define QCEDEV_MAGIC 0x56434544 /* "qced" */
  205. static int qcedev_open(struct inode *inode, struct file *file);
  206. static int qcedev_release(struct inode *inode, struct file *file);
  207. static int start_cipher_req(struct qcedev_control *podev,
  208. int *current_req_info);
  209. static int start_offload_cipher_req(struct qcedev_control *podev,
  210. int *current_req_info);
  211. static int start_sha_req(struct qcedev_control *podev,
  212. int *current_req_info);
  213. static const struct file_operations qcedev_fops = {
  214. .owner = THIS_MODULE,
  215. .unlocked_ioctl = qcedev_ioctl,
  216. #ifdef CONFIG_COMPAT
  217. .compat_ioctl = compat_qcedev_ioctl,
  218. #endif
  219. .open = qcedev_open,
  220. .release = qcedev_release,
  221. };
  222. static struct qcedev_control qce_dev[] = {
  223. {
  224. .magic = QCEDEV_MAGIC,
  225. },
  226. };
  227. #define MAX_QCE_DEVICE ARRAY_SIZE(qce_dev)
  228. #define DEBUG_MAX_FNAME 16
  229. #define DEBUG_MAX_RW_BUF 1024
  230. struct qcedev_stat {
  231. u32 qcedev_dec_success;
  232. u32 qcedev_dec_fail;
  233. u32 qcedev_enc_success;
  234. u32 qcedev_enc_fail;
  235. u32 qcedev_sha_success;
  236. u32 qcedev_sha_fail;
  237. };
  238. static struct qcedev_stat _qcedev_stat;
  239. static struct dentry *_debug_dent;
  240. static char _debug_read_buf[DEBUG_MAX_RW_BUF];
  241. static int _debug_qcedev;
  242. static struct qcedev_control *qcedev_minor_to_control(unsigned int n)
  243. {
  244. int i;
  245. for (i = 0; i < MAX_QCE_DEVICE; i++) {
  246. if (qce_dev[i].minor == n)
  247. return &qce_dev[n];
  248. }
  249. return NULL;
  250. }
  251. static int qcedev_open(struct inode *inode, struct file *file)
  252. {
  253. struct qcedev_handle *handle;
  254. struct qcedev_control *podev;
  255. podev = qcedev_minor_to_control(MINOR(inode->i_rdev));
  256. if (podev == NULL) {
  257. pr_err("%s: no such device %d\n", __func__,
  258. MINOR(inode->i_rdev));
  259. return -ENOENT;
  260. }
  261. handle = kzalloc(sizeof(struct qcedev_handle), GFP_KERNEL);
  262. if (handle == NULL)
  263. return -ENOMEM;
  264. handle->cntl = podev;
  265. file->private_data = handle;
  266. qcedev_ce_high_bw_req(podev, true);
  267. mutex_init(&handle->registeredbufs.lock);
  268. INIT_LIST_HEAD(&handle->registeredbufs.list);
  269. return 0;
  270. }
  271. static int qcedev_release(struct inode *inode, struct file *file)
  272. {
  273. struct qcedev_control *podev;
  274. struct qcedev_handle *handle;
  275. handle = file->private_data;
  276. podev = handle->cntl;
  277. if (podev != NULL && podev->magic != QCEDEV_MAGIC) {
  278. pr_err("%s: invalid handle %pK\n",
  279. __func__, podev);
  280. }
  281. if (podev)
  282. qcedev_ce_high_bw_req(podev, false);
  283. if (qcedev_unmap_all_buffers(handle))
  284. pr_err("%s: failed to unmap all ion buffers\n", __func__);
  285. kfree_sensitive(handle);
  286. file->private_data = NULL;
  287. return 0;
  288. }
  289. static void req_done(unsigned long data)
  290. {
  291. struct qcedev_control *podev = (struct qcedev_control *)data;
  292. struct qcedev_async_req *areq;
  293. unsigned long flags = 0;
  294. struct qcedev_async_req *new_req = NULL;
  295. spin_lock_irqsave(&podev->lock, flags);
  296. areq = podev->active_command;
  297. podev->active_command = NULL;
  298. if (areq) {
  299. if (!areq->timed_out)
  300. complete(&areq->complete);
  301. areq->state = QCEDEV_REQ_DONE;
  302. }
  303. /* Look through queued requests and wake up the corresponding thread */
  304. if (!list_empty(&podev->ready_commands)) {
  305. new_req = container_of(podev->ready_commands.next,
  306. struct qcedev_async_req, list);
  307. list_del(&new_req->list);
  308. new_req->state = QCEDEV_REQ_CURRENT;
  309. wake_up_interruptible(&new_req->wait_q);
  310. }
  311. spin_unlock_irqrestore(&podev->lock, flags);
  312. }
  313. void qcedev_sha_req_cb(void *cookie, unsigned char *digest,
  314. unsigned char *authdata, int ret)
  315. {
  316. struct qcedev_sha_req *areq;
  317. struct qcedev_control *pdev;
  318. struct qcedev_handle *handle;
  319. uint32_t *auth32 = (uint32_t *)authdata;
  320. areq = (struct qcedev_sha_req *) cookie;
  321. if (!areq || !areq->cookie)
  322. return;
  323. handle = (struct qcedev_handle *) areq->cookie;
  324. pdev = handle->cntl;
  325. if (!pdev)
  326. return;
  327. if (digest)
  328. memcpy(&handle->sha_ctxt.digest[0], digest, 32);
  329. if (authdata) {
  330. handle->sha_ctxt.auth_data[0] = auth32[0];
  331. handle->sha_ctxt.auth_data[1] = auth32[1];
  332. }
  333. tasklet_schedule(&pdev->done_tasklet);
  334. };
  335. void qcedev_cipher_req_cb(void *cookie, unsigned char *icv,
  336. unsigned char *iv, int ret)
  337. {
  338. struct qcedev_cipher_req *areq;
  339. struct qcedev_handle *handle;
  340. struct qcedev_control *podev;
  341. struct qcedev_async_req *qcedev_areq;
  342. areq = (struct qcedev_cipher_req *) cookie;
  343. if (!areq || !areq->cookie)
  344. return;
  345. handle = (struct qcedev_handle *) areq->cookie;
  346. podev = handle->cntl;
  347. if (!podev)
  348. return;
  349. qcedev_areq = podev->active_command;
  350. if (iv)
  351. memcpy(&qcedev_areq->cipher_op_req.iv[0], iv,
  352. qcedev_areq->cipher_op_req.ivlen);
  353. tasklet_schedule(&podev->done_tasklet);
  354. };
  355. static int start_cipher_req(struct qcedev_control *podev,
  356. int *current_req_info)
  357. {
  358. struct qcedev_async_req *qcedev_areq;
  359. struct qce_req creq;
  360. int ret = 0;
  361. memset(&creq, 0, sizeof(creq));
  362. /* start the command on the podev->active_command */
  363. qcedev_areq = podev->active_command;
  364. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  365. if (qcedev_areq->cipher_op_req.use_pmem == QCEDEV_USE_PMEM) {
  366. pr_err("%s: Use of PMEM is not supported\n", __func__);
  367. goto unsupported;
  368. }
  369. creq.pmem = NULL;
  370. switch (qcedev_areq->cipher_op_req.alg) {
  371. case QCEDEV_ALG_DES:
  372. creq.alg = CIPHER_ALG_DES;
  373. break;
  374. case QCEDEV_ALG_3DES:
  375. creq.alg = CIPHER_ALG_3DES;
  376. break;
  377. case QCEDEV_ALG_AES:
  378. creq.alg = CIPHER_ALG_AES;
  379. break;
  380. default:
  381. return -EINVAL;
  382. }
  383. switch (qcedev_areq->cipher_op_req.mode) {
  384. case QCEDEV_AES_MODE_CBC:
  385. case QCEDEV_DES_MODE_CBC:
  386. creq.mode = QCE_MODE_CBC;
  387. break;
  388. case QCEDEV_AES_MODE_ECB:
  389. case QCEDEV_DES_MODE_ECB:
  390. creq.mode = QCE_MODE_ECB;
  391. break;
  392. case QCEDEV_AES_MODE_CTR:
  393. creq.mode = QCE_MODE_CTR;
  394. break;
  395. case QCEDEV_AES_MODE_XTS:
  396. creq.mode = QCE_MODE_XTS;
  397. break;
  398. default:
  399. return -EINVAL;
  400. }
  401. if ((creq.alg == CIPHER_ALG_AES) &&
  402. (creq.mode == QCE_MODE_CTR)) {
  403. creq.dir = QCE_ENCRYPT;
  404. } else {
  405. if (qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC)
  406. creq.dir = QCE_ENCRYPT;
  407. else
  408. creq.dir = QCE_DECRYPT;
  409. }
  410. creq.iv = &qcedev_areq->cipher_op_req.iv[0];
  411. creq.ivsize = qcedev_areq->cipher_op_req.ivlen;
  412. creq.iv_ctr_size = 0;
  413. creq.enckey = &qcedev_areq->cipher_op_req.enckey[0];
  414. creq.encklen = qcedev_areq->cipher_op_req.encklen;
  415. creq.cryptlen = qcedev_areq->cipher_op_req.data_len;
  416. if (qcedev_areq->cipher_op_req.encklen == 0) {
  417. if ((qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC_NO_KEY)
  418. || (qcedev_areq->cipher_op_req.op ==
  419. QCEDEV_OPER_DEC_NO_KEY))
  420. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  421. else {
  422. int i;
  423. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  424. if (qcedev_areq->cipher_op_req.enckey[i] != 0)
  425. break;
  426. }
  427. if ((podev->platform_support.hw_key_support == 1) &&
  428. (i == QCEDEV_MAX_KEY_SIZE))
  429. creq.op = QCE_REQ_ABLK_CIPHER;
  430. else {
  431. ret = -EINVAL;
  432. goto unsupported;
  433. }
  434. }
  435. } else {
  436. creq.op = QCE_REQ_ABLK_CIPHER;
  437. }
  438. creq.qce_cb = qcedev_cipher_req_cb;
  439. creq.areq = (void *)&qcedev_areq->cipher_req;
  440. creq.flags = 0;
  441. creq.offload_op = QCE_OFFLOAD_NONE;
  442. ret = qce_ablk_cipher_req(podev->qce, &creq);
  443. *current_req_info = creq.current_req_info;
  444. unsupported:
  445. qcedev_areq->err = ret ? -ENXIO : 0;
  446. return ret;
  447. };
  448. void qcedev_offload_cipher_req_cb(void *cookie, unsigned char *icv,
  449. unsigned char *iv, int ret)
  450. {
  451. struct qcedev_cipher_req *areq;
  452. struct qcedev_handle *handle;
  453. struct qcedev_control *podev;
  454. struct qcedev_async_req *qcedev_areq;
  455. areq = (struct qcedev_cipher_req *) cookie;
  456. if (!areq || !areq->cookie)
  457. return;
  458. handle = (struct qcedev_handle *) areq->cookie;
  459. podev = handle->cntl;
  460. if (!podev)
  461. return;
  462. qcedev_areq = podev->active_command;
  463. if (iv)
  464. memcpy(&qcedev_areq->offload_cipher_op_req.iv[0], iv,
  465. qcedev_areq->offload_cipher_op_req.ivlen);
  466. tasklet_schedule(&podev->done_tasklet);
  467. }
  468. static int start_offload_cipher_req(struct qcedev_control *podev,
  469. int *current_req_info)
  470. {
  471. struct qcedev_async_req *qcedev_areq;
  472. struct qce_req creq;
  473. u8 patt_sz = 0, proc_data_sz = 0;
  474. int ret = 0;
  475. memset(&creq, 0, sizeof(creq));
  476. /* Start the command on the podev->active_command */
  477. qcedev_areq = podev->active_command;
  478. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  479. switch (qcedev_areq->offload_cipher_op_req.alg) {
  480. case QCEDEV_ALG_AES:
  481. creq.alg = CIPHER_ALG_AES;
  482. break;
  483. default:
  484. return -EINVAL;
  485. }
  486. switch (qcedev_areq->offload_cipher_op_req.mode) {
  487. case QCEDEV_AES_MODE_CBC:
  488. creq.mode = QCE_MODE_CBC;
  489. break;
  490. case QCEDEV_AES_MODE_CTR:
  491. creq.mode = QCE_MODE_CTR;
  492. break;
  493. default:
  494. return -EINVAL;
  495. }
  496. if (qcedev_areq->offload_cipher_op_req.is_copy_op ||
  497. qcedev_areq->offload_cipher_op_req.encrypt) {
  498. creq.dir = QCE_ENCRYPT;
  499. } else {
  500. switch(qcedev_areq->offload_cipher_op_req.op) {
  501. case QCEDEV_OFFLOAD_HLOS_HLOS:
  502. case QCEDEV_OFFLOAD_HLOS_HLOS_1:
  503. case QCEDEV_OFFLOAD_HLOS_CPB:
  504. case QCEDEV_OFFLOAD_HLOS_CPB_1:
  505. creq.dir = QCE_DECRYPT;
  506. break;
  507. case QCEDEV_OFFLOAD_CPB_HLOS:
  508. creq.dir = QCE_ENCRYPT;
  509. break;
  510. default:
  511. return -EINVAL;
  512. }
  513. }
  514. creq.iv = &qcedev_areq->offload_cipher_op_req.iv[0];
  515. creq.ivsize = qcedev_areq->offload_cipher_op_req.ivlen;
  516. creq.iv_ctr_size = qcedev_areq->offload_cipher_op_req.iv_ctr_size;
  517. creq.encklen = qcedev_areq->offload_cipher_op_req.encklen;
  518. /* OFFLOAD use cases use PIPE keys so no need to set keys */
  519. creq.flags = QCEDEV_CTX_USE_PIPE_KEY;
  520. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  521. creq.offload_op = (int)qcedev_areq->offload_cipher_op_req.op;
  522. if (qcedev_areq->offload_cipher_op_req.is_copy_op)
  523. creq.is_copy_op = true;
  524. creq.cryptlen = qcedev_areq->offload_cipher_op_req.data_len;
  525. creq.qce_cb = qcedev_offload_cipher_req_cb;
  526. creq.areq = (void *)&qcedev_areq->cipher_req;
  527. patt_sz = qcedev_areq->offload_cipher_op_req.pattern_info.patt_sz;
  528. proc_data_sz =
  529. qcedev_areq->offload_cipher_op_req.pattern_info.proc_data_sz;
  530. creq.is_pattern_valid =
  531. qcedev_areq->offload_cipher_op_req.is_pattern_valid;
  532. if (creq.is_pattern_valid) {
  533. creq.pattern_info = 0x1;
  534. if (patt_sz)
  535. creq.pattern_info |= (patt_sz - 1) << 4;
  536. if (proc_data_sz)
  537. creq.pattern_info |= (proc_data_sz - 1) << 8;
  538. creq.pattern_info |=
  539. qcedev_areq->offload_cipher_op_req.pattern_info.patt_offset << 12;
  540. }
  541. creq.block_offset = qcedev_areq->offload_cipher_op_req.block_offset;
  542. ret = qce_ablk_cipher_req(podev->qce, &creq);
  543. *current_req_info = creq.current_req_info;
  544. qcedev_areq->err = ret ? -ENXIO : 0;
  545. return ret;
  546. }
  547. static int start_sha_req(struct qcedev_control *podev,
  548. int *current_req_info)
  549. {
  550. struct qcedev_async_req *qcedev_areq;
  551. struct qce_sha_req sreq;
  552. int ret = 0;
  553. struct qcedev_handle *handle;
  554. /* start the command on the podev->active_command */
  555. qcedev_areq = podev->active_command;
  556. handle = qcedev_areq->handle;
  557. switch (qcedev_areq->sha_op_req.alg) {
  558. case QCEDEV_ALG_SHA1:
  559. sreq.alg = QCE_HASH_SHA1;
  560. break;
  561. case QCEDEV_ALG_SHA256:
  562. sreq.alg = QCE_HASH_SHA256;
  563. break;
  564. case QCEDEV_ALG_SHA1_HMAC:
  565. if (podev->ce_support.sha_hmac) {
  566. sreq.alg = QCE_HASH_SHA1_HMAC;
  567. sreq.authkey = &handle->sha_ctxt.authkey[0];
  568. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  569. } else {
  570. sreq.alg = QCE_HASH_SHA1;
  571. sreq.authkey = NULL;
  572. }
  573. break;
  574. case QCEDEV_ALG_SHA256_HMAC:
  575. if (podev->ce_support.sha_hmac) {
  576. sreq.alg = QCE_HASH_SHA256_HMAC;
  577. sreq.authkey = &handle->sha_ctxt.authkey[0];
  578. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  579. } else {
  580. sreq.alg = QCE_HASH_SHA256;
  581. sreq.authkey = NULL;
  582. }
  583. break;
  584. case QCEDEV_ALG_AES_CMAC:
  585. sreq.alg = QCE_HASH_AES_CMAC;
  586. sreq.authkey = &handle->sha_ctxt.authkey[0];
  587. sreq.authklen = qcedev_areq->sha_op_req.authklen;
  588. break;
  589. default:
  590. pr_err("Algorithm %d not supported, exiting\n",
  591. qcedev_areq->sha_op_req.alg);
  592. return -EINVAL;
  593. }
  594. qcedev_areq->sha_req.cookie = handle;
  595. sreq.qce_cb = qcedev_sha_req_cb;
  596. if (qcedev_areq->sha_op_req.alg != QCEDEV_ALG_AES_CMAC) {
  597. sreq.auth_data[0] = handle->sha_ctxt.auth_data[0];
  598. sreq.auth_data[1] = handle->sha_ctxt.auth_data[1];
  599. sreq.auth_data[2] = handle->sha_ctxt.auth_data[2];
  600. sreq.auth_data[3] = handle->sha_ctxt.auth_data[3];
  601. sreq.digest = &handle->sha_ctxt.digest[0];
  602. sreq.first_blk = handle->sha_ctxt.first_blk;
  603. sreq.last_blk = handle->sha_ctxt.last_blk;
  604. }
  605. sreq.size = qcedev_areq->sha_req.sreq.nbytes;
  606. sreq.src = qcedev_areq->sha_req.sreq.src;
  607. sreq.areq = (void *)&qcedev_areq->sha_req;
  608. sreq.flags = 0;
  609. ret = qce_process_sha_req(podev->qce, &sreq);
  610. *current_req_info = sreq.current_req_info;
  611. qcedev_areq->err = ret ? -ENXIO : 0;
  612. return ret;
  613. };
  614. static void qcedev_check_crypto_status(
  615. struct qcedev_async_req *qcedev_areq, void *handle)
  616. {
  617. struct qce_error error = {0};
  618. qcedev_areq->offload_cipher_op_req.err = QCEDEV_OFFLOAD_NO_ERROR;
  619. qce_get_crypto_status(handle, &error);
  620. if (error.timer_error) {
  621. qcedev_areq->offload_cipher_op_req.err =
  622. QCEDEV_OFFLOAD_KEY_TIMER_EXPIRED_ERROR;
  623. } else if (error.key_paused) {
  624. qcedev_areq->offload_cipher_op_req.err =
  625. QCEDEV_OFFLOAD_KEY_PAUSE_ERROR;
  626. } else if (error.generic_error) {
  627. qcedev_areq->offload_cipher_op_req.err =
  628. QCEDEV_OFFLOAD_GENERIC_ERROR;
  629. }
  630. return;
  631. }
  632. #define MAX_RETRIES 333
  633. static int submit_req(struct qcedev_async_req *qcedev_areq,
  634. struct qcedev_handle *handle)
  635. {
  636. struct qcedev_control *podev;
  637. unsigned long flags = 0;
  638. int ret = 0;
  639. struct qcedev_stat *pstat;
  640. int current_req_info = 0;
  641. int wait = MAX_CRYPTO_WAIT_TIME;
  642. struct qcedev_async_req *new_req = NULL;
  643. int retries = 0;
  644. int req_wait = MAX_REQUEST_TIME;
  645. unsigned int crypto_wait = 0;
  646. qcedev_areq->err = 0;
  647. podev = handle->cntl;
  648. init_waitqueue_head(&qcedev_areq->wait_q);
  649. spin_lock_irqsave(&podev->lock, flags);
  650. /*
  651. * Service only one crypto request at a time.
  652. * Any other new requests are queued in ready_commands and woken up
  653. * only when the active command has finished successfully or when the
  654. * request times out or when the command failed when setting up.
  655. */
  656. do {
  657. if (podev->active_command == NULL) {
  658. podev->active_command = qcedev_areq;
  659. qcedev_areq->state = QCEDEV_REQ_SUBMITTED;
  660. switch (qcedev_areq->op_type) {
  661. case QCEDEV_CRYPTO_OPER_CIPHER:
  662. ret = start_cipher_req(podev,
  663. &current_req_info);
  664. crypto_wait = MAX_CRYPTO_WAIT_TIME;
  665. break;
  666. case QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER:
  667. ret = start_offload_cipher_req(podev,
  668. &current_req_info);
  669. crypto_wait = MAX_OFFLOAD_CRYPTO_WAIT_TIME;
  670. break;
  671. default:
  672. crypto_wait = MAX_CRYPTO_WAIT_TIME;
  673. ret = start_sha_req(podev,
  674. &current_req_info);
  675. break;
  676. }
  677. } else {
  678. list_add_tail(&qcedev_areq->list,
  679. &podev->ready_commands);
  680. qcedev_areq->state = QCEDEV_REQ_WAITING;
  681. req_wait = wait_event_interruptible_lock_irq_timeout(
  682. qcedev_areq->wait_q,
  683. (qcedev_areq->state == QCEDEV_REQ_CURRENT),
  684. podev->lock,
  685. msecs_to_jiffies(MAX_REQUEST_TIME));
  686. if ((req_wait == 0) || (req_wait == -ERESTARTSYS)) {
  687. pr_err("%s: request timed out, req_wait = %d\n",
  688. __func__, req_wait);
  689. list_del(&qcedev_areq->list);
  690. podev->active_command = NULL;
  691. spin_unlock_irqrestore(&podev->lock, flags);
  692. return qcedev_areq->err;
  693. }
  694. }
  695. } while (qcedev_areq->state != QCEDEV_REQ_SUBMITTED);
  696. if (ret != 0) {
  697. podev->active_command = NULL;
  698. /*
  699. * Look through queued requests and wake up the corresponding
  700. * thread.
  701. */
  702. if (!list_empty(&podev->ready_commands)) {
  703. new_req = container_of(podev->ready_commands.next,
  704. struct qcedev_async_req, list);
  705. list_del(&new_req->list);
  706. new_req->state = QCEDEV_REQ_CURRENT;
  707. wake_up_interruptible(&new_req->wait_q);
  708. }
  709. }
  710. spin_unlock_irqrestore(&podev->lock, flags);
  711. qcedev_areq->timed_out = false;
  712. if (ret == 0)
  713. wait = wait_for_completion_timeout(&qcedev_areq->complete,
  714. msecs_to_jiffies(crypto_wait));
  715. if (!wait) {
  716. /*
  717. * This means wait timed out, and the callback routine was not
  718. * exercised. The callback sequence does some housekeeping which
  719. * would be missed here, hence having a call to qce here to do
  720. * that.
  721. */
  722. pr_err("%s: wait timed out, req info = %d\n", __func__,
  723. current_req_info);
  724. spin_lock_irqsave(&podev->lock, flags);
  725. qcedev_areq->timed_out = true;
  726. spin_unlock_irqrestore(&podev->lock, flags);
  727. qcedev_check_crypto_status(qcedev_areq, podev->qce);
  728. if (qcedev_areq->offload_cipher_op_req.err ==
  729. QCEDEV_OFFLOAD_NO_ERROR) {
  730. pr_err("%s: no error, wait for request to be done", __func__);
  731. while (qcedev_areq->state != QCEDEV_REQ_DONE &&
  732. retries < MAX_RETRIES) {
  733. usleep_range(3000, 5000);
  734. retries++;
  735. pr_err("%s: waiting for req state to be done, retries = %d",
  736. __func__, retries);
  737. }
  738. return 0;
  739. }
  740. ret = qce_manage_timeout(podev->qce, current_req_info);
  741. if (ret)
  742. pr_err("%s: error during manage timeout", __func__);
  743. req_done((unsigned long) podev);
  744. if (qcedev_areq->offload_cipher_op_req.err !=
  745. QCEDEV_OFFLOAD_NO_ERROR)
  746. return 0;
  747. }
  748. if (ret)
  749. qcedev_areq->err = -EIO;
  750. pstat = &_qcedev_stat;
  751. if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER) {
  752. switch (qcedev_areq->cipher_op_req.op) {
  753. case QCEDEV_OPER_DEC:
  754. if (qcedev_areq->err)
  755. pstat->qcedev_dec_fail++;
  756. else
  757. pstat->qcedev_dec_success++;
  758. break;
  759. case QCEDEV_OPER_ENC:
  760. if (qcedev_areq->err)
  761. pstat->qcedev_enc_fail++;
  762. else
  763. pstat->qcedev_enc_success++;
  764. break;
  765. default:
  766. break;
  767. }
  768. } else if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER) {
  769. //Do nothing
  770. } else {
  771. if (qcedev_areq->err)
  772. pstat->qcedev_sha_fail++;
  773. else
  774. pstat->qcedev_sha_success++;
  775. }
  776. return qcedev_areq->err;
  777. }
  778. static int qcedev_sha_init(struct qcedev_async_req *areq,
  779. struct qcedev_handle *handle)
  780. {
  781. struct qcedev_sha_ctxt *sha_ctxt = &handle->sha_ctxt;
  782. memset(sha_ctxt, 0, sizeof(struct qcedev_sha_ctxt));
  783. sha_ctxt->first_blk = 1;
  784. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  785. (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)) {
  786. memcpy(&sha_ctxt->digest[0],
  787. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  788. sha_ctxt->diglen = SHA1_DIGEST_SIZE;
  789. } else {
  790. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA256) ||
  791. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)) {
  792. memcpy(&sha_ctxt->digest[0],
  793. &_std_init_vector_sha256_uint8[0],
  794. SHA256_DIGEST_SIZE);
  795. sha_ctxt->diglen = SHA256_DIGEST_SIZE;
  796. }
  797. }
  798. sha_ctxt->init_done = true;
  799. return 0;
  800. }
  801. static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq,
  802. struct qcedev_handle *handle,
  803. struct scatterlist *sg_src)
  804. {
  805. int err = 0;
  806. int i = 0;
  807. uint32_t total;
  808. uint8_t *user_src = NULL;
  809. uint8_t *k_src = NULL;
  810. uint8_t *k_buf_src = NULL;
  811. uint32_t buf_size = 0;
  812. uint8_t *k_align_src = NULL;
  813. uint32_t sha_pad_len = 0;
  814. uint32_t trailing_buf_len = 0;
  815. uint32_t t_buf = handle->sha_ctxt.trailing_buf_len;
  816. uint32_t sha_block_size;
  817. total = qcedev_areq->sha_op_req.data_len + t_buf;
  818. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1)
  819. sha_block_size = SHA1_BLOCK_SIZE;
  820. else
  821. sha_block_size = SHA256_BLOCK_SIZE;
  822. if (total <= sha_block_size) {
  823. uint32_t len = qcedev_areq->sha_op_req.data_len;
  824. i = 0;
  825. k_src = &handle->sha_ctxt.trailing_buf[t_buf];
  826. /* Copy data from user src(s) */
  827. while (len > 0) {
  828. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  829. if (user_src && copy_from_user(k_src,
  830. (void __user *)user_src,
  831. qcedev_areq->sha_op_req.data[i].len))
  832. return -EFAULT;
  833. len -= qcedev_areq->sha_op_req.data[i].len;
  834. k_src += qcedev_areq->sha_op_req.data[i].len;
  835. i++;
  836. }
  837. handle->sha_ctxt.trailing_buf_len = total;
  838. return 0;
  839. }
  840. buf_size = total + CACHE_LINE_SIZE * 2;
  841. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  842. if (k_buf_src == NULL)
  843. return -ENOMEM;
  844. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  845. CACHE_LINE_SIZE);
  846. k_src = k_align_src;
  847. /* check for trailing buffer from previous updates and append it */
  848. if (t_buf > 0) {
  849. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  850. t_buf);
  851. k_src += t_buf;
  852. }
  853. /* Copy data from user src(s) */
  854. user_src = qcedev_areq->sha_op_req.data[0].vaddr;
  855. if (user_src && copy_from_user(k_src,
  856. (void __user *)user_src,
  857. qcedev_areq->sha_op_req.data[0].len)) {
  858. memset(k_buf_src, 0, buf_size);
  859. kfree(k_buf_src);
  860. return -EFAULT;
  861. }
  862. k_src += qcedev_areq->sha_op_req.data[0].len;
  863. for (i = 1; i < qcedev_areq->sha_op_req.entries; i++) {
  864. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  865. if (user_src && copy_from_user(k_src,
  866. (void __user *)user_src,
  867. qcedev_areq->sha_op_req.data[i].len)) {
  868. memset(k_buf_src, 0, buf_size);
  869. kfree(k_buf_src);
  870. return -EFAULT;
  871. }
  872. k_src += qcedev_areq->sha_op_req.data[i].len;
  873. }
  874. /* get new trailing buffer */
  875. sha_pad_len = ALIGN(total, CE_SHA_BLOCK_SIZE) - total;
  876. trailing_buf_len = CE_SHA_BLOCK_SIZE - sha_pad_len;
  877. qcedev_areq->sha_req.sreq.src = sg_src;
  878. sg_init_one(qcedev_areq->sha_req.sreq.src, k_align_src,
  879. total-trailing_buf_len);
  880. qcedev_areq->sha_req.sreq.nbytes = total - trailing_buf_len;
  881. /* update sha_ctxt trailing buf content to new trailing buf */
  882. if (trailing_buf_len > 0) {
  883. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  884. memcpy(&handle->sha_ctxt.trailing_buf[0],
  885. (k_src - trailing_buf_len),
  886. trailing_buf_len);
  887. }
  888. handle->sha_ctxt.trailing_buf_len = trailing_buf_len;
  889. err = submit_req(qcedev_areq, handle);
  890. handle->sha_ctxt.last_blk = 0;
  891. handle->sha_ctxt.first_blk = 0;
  892. memset(k_buf_src, 0, buf_size);
  893. kfree(k_buf_src);
  894. return err;
  895. }
  896. static int qcedev_sha_update(struct qcedev_async_req *qcedev_areq,
  897. struct qcedev_handle *handle,
  898. struct scatterlist *sg_src)
  899. {
  900. int err = 0;
  901. int i = 0;
  902. int j = 0;
  903. int k = 0;
  904. int num_entries = 0;
  905. uint32_t total = 0;
  906. if (!handle->sha_ctxt.init_done) {
  907. pr_err("%s Init was not called\n", __func__);
  908. return -EINVAL;
  909. }
  910. if (qcedev_areq->sha_op_req.data_len > QCE_MAX_OPER_DATA) {
  911. struct qcedev_sha_op_req *saved_req;
  912. struct qcedev_sha_op_req req;
  913. struct qcedev_sha_op_req *sreq = &qcedev_areq->sha_op_req;
  914. uint32_t req_size = 0;
  915. req_size = sizeof(struct qcedev_sha_op_req);
  916. /* save the original req structure */
  917. saved_req =
  918. kmalloc(req_size, GFP_KERNEL);
  919. if (saved_req == NULL) {
  920. pr_err("%s:Can't Allocate mem:saved_req 0x%lx\n",
  921. __func__, (uintptr_t)saved_req);
  922. return -ENOMEM;
  923. }
  924. memcpy(&req, sreq, sizeof(*sreq));
  925. memcpy(saved_req, sreq, sizeof(*sreq));
  926. i = 0;
  927. /* Address 32 KB at a time */
  928. while ((i < req.entries) && (err == 0)) {
  929. if (sreq->data[i].len > QCE_MAX_OPER_DATA) {
  930. sreq->data[0].len = QCE_MAX_OPER_DATA;
  931. if (i > 0) {
  932. sreq->data[0].vaddr =
  933. sreq->data[i].vaddr;
  934. }
  935. sreq->data_len = QCE_MAX_OPER_DATA;
  936. sreq->entries = 1;
  937. err = qcedev_sha_update_max_xfer(qcedev_areq,
  938. handle, sg_src);
  939. sreq->data[i].len = req.data[i].len -
  940. QCE_MAX_OPER_DATA;
  941. sreq->data[i].vaddr = req.data[i].vaddr +
  942. QCE_MAX_OPER_DATA;
  943. req.data[i].vaddr = sreq->data[i].vaddr;
  944. req.data[i].len = sreq->data[i].len;
  945. } else {
  946. total = 0;
  947. for (j = i; j < req.entries; j++) {
  948. num_entries++;
  949. if ((total + sreq->data[j].len) >=
  950. QCE_MAX_OPER_DATA) {
  951. sreq->data[j].len =
  952. (QCE_MAX_OPER_DATA - total);
  953. total = QCE_MAX_OPER_DATA;
  954. break;
  955. }
  956. total += sreq->data[j].len;
  957. }
  958. sreq->data_len = total;
  959. if (i > 0)
  960. for (k = 0; k < num_entries; k++) {
  961. sreq->data[k].len =
  962. sreq->data[i+k].len;
  963. sreq->data[k].vaddr =
  964. sreq->data[i+k].vaddr;
  965. }
  966. sreq->entries = num_entries;
  967. i = j;
  968. err = qcedev_sha_update_max_xfer(qcedev_areq,
  969. handle, sg_src);
  970. num_entries = 0;
  971. sreq->data[i].vaddr = req.data[i].vaddr +
  972. sreq->data[i].len;
  973. sreq->data[i].len = req.data[i].len -
  974. sreq->data[i].len;
  975. req.data[i].vaddr = sreq->data[i].vaddr;
  976. req.data[i].len = sreq->data[i].len;
  977. if (sreq->data[i].len == 0)
  978. i++;
  979. }
  980. } /* end of while ((i < req.entries) && (err == 0)) */
  981. /* Restore the original req structure */
  982. for (i = 0; i < saved_req->entries; i++) {
  983. sreq->data[i].len = saved_req->data[i].len;
  984. sreq->data[i].vaddr = saved_req->data[i].vaddr;
  985. }
  986. sreq->entries = saved_req->entries;
  987. sreq->data_len = saved_req->data_len;
  988. memset(saved_req, 0, req_size);
  989. kfree(saved_req);
  990. } else
  991. err = qcedev_sha_update_max_xfer(qcedev_areq, handle, sg_src);
  992. return err;
  993. }
  994. static int qcedev_sha_final(struct qcedev_async_req *qcedev_areq,
  995. struct qcedev_handle *handle)
  996. {
  997. int err = 0;
  998. struct scatterlist sg_src;
  999. uint32_t total;
  1000. uint8_t *k_buf_src = NULL;
  1001. uint32_t buf_size = 0;
  1002. uint8_t *k_align_src = NULL;
  1003. if (!handle->sha_ctxt.init_done) {
  1004. pr_err("%s Init was not called\n", __func__);
  1005. return -EINVAL;
  1006. }
  1007. handle->sha_ctxt.last_blk = 1;
  1008. total = handle->sha_ctxt.trailing_buf_len;
  1009. buf_size = total + CACHE_LINE_SIZE * 2;
  1010. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1011. if (k_buf_src == NULL)
  1012. return -ENOMEM;
  1013. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  1014. CACHE_LINE_SIZE);
  1015. memcpy(k_align_src, &handle->sha_ctxt.trailing_buf[0], total);
  1016. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  1017. sg_init_one(qcedev_areq->sha_req.sreq.src, k_align_src, total);
  1018. qcedev_areq->sha_req.sreq.nbytes = total;
  1019. err = submit_req(qcedev_areq, handle);
  1020. handle->sha_ctxt.first_blk = 0;
  1021. handle->sha_ctxt.last_blk = 0;
  1022. handle->sha_ctxt.auth_data[0] = 0;
  1023. handle->sha_ctxt.auth_data[1] = 0;
  1024. handle->sha_ctxt.trailing_buf_len = 0;
  1025. handle->sha_ctxt.init_done = false;
  1026. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  1027. memset(k_buf_src, 0, buf_size);
  1028. kfree(k_buf_src);
  1029. qcedev_areq->sha_req.sreq.src = NULL;
  1030. return err;
  1031. }
  1032. static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq,
  1033. struct qcedev_handle *handle,
  1034. struct scatterlist *sg_src)
  1035. {
  1036. int err = 0;
  1037. int i = 0;
  1038. uint32_t total;
  1039. uint8_t *user_src = NULL;
  1040. uint8_t *k_src = NULL;
  1041. uint8_t *k_buf_src = NULL;
  1042. uint32_t buf_size = 0;
  1043. total = qcedev_areq->sha_op_req.data_len;
  1044. if ((qcedev_areq->sha_op_req.authklen != QCEDEV_AES_KEY_128) &&
  1045. (qcedev_areq->sha_op_req.authklen != QCEDEV_AES_KEY_256)) {
  1046. pr_err("%s: unsupported key length\n", __func__);
  1047. return -EINVAL;
  1048. }
  1049. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  1050. (void __user *)qcedev_areq->sha_op_req.authkey,
  1051. qcedev_areq->sha_op_req.authklen))
  1052. return -EFAULT;
  1053. if (total > U32_MAX - CACHE_LINE_SIZE * 2)
  1054. return -EINVAL;
  1055. buf_size = total + CACHE_LINE_SIZE * 2;
  1056. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1057. if (k_buf_src == NULL)
  1058. return -ENOMEM;
  1059. k_src = k_buf_src;
  1060. /* Copy data from user src(s) */
  1061. user_src = qcedev_areq->sha_op_req.data[0].vaddr;
  1062. for (i = 0; i < qcedev_areq->sha_op_req.entries; i++) {
  1063. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  1064. if (user_src && copy_from_user(k_src, (void __user *)user_src,
  1065. qcedev_areq->sha_op_req.data[i].len)) {
  1066. memset(k_buf_src, 0, buf_size);
  1067. kfree(k_buf_src);
  1068. return -EFAULT;
  1069. }
  1070. k_src += qcedev_areq->sha_op_req.data[i].len;
  1071. }
  1072. qcedev_areq->sha_req.sreq.src = sg_src;
  1073. sg_init_one(qcedev_areq->sha_req.sreq.src, k_buf_src, total);
  1074. qcedev_areq->sha_req.sreq.nbytes = total;
  1075. handle->sha_ctxt.diglen = qcedev_areq->sha_op_req.diglen;
  1076. err = submit_req(qcedev_areq, handle);
  1077. memset(k_buf_src, 0, buf_size);
  1078. kfree(k_buf_src);
  1079. return err;
  1080. }
  1081. static int qcedev_set_hmac_auth_key(struct qcedev_async_req *areq,
  1082. struct qcedev_handle *handle,
  1083. struct scatterlist *sg_src)
  1084. {
  1085. int err = 0;
  1086. if (areq->sha_op_req.authklen <= QCEDEV_MAX_KEY_SIZE) {
  1087. qcedev_sha_init(areq, handle);
  1088. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  1089. (void __user *)areq->sha_op_req.authkey,
  1090. areq->sha_op_req.authklen))
  1091. return -EFAULT;
  1092. } else {
  1093. struct qcedev_async_req authkey_areq;
  1094. uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
  1095. init_completion(&authkey_areq.complete);
  1096. authkey_areq.sha_op_req.entries = 1;
  1097. authkey_areq.sha_op_req.data[0].vaddr =
  1098. areq->sha_op_req.authkey;
  1099. authkey_areq.sha_op_req.data[0].len = areq->sha_op_req.authklen;
  1100. authkey_areq.sha_op_req.data_len = areq->sha_op_req.authklen;
  1101. authkey_areq.sha_op_req.diglen = 0;
  1102. authkey_areq.handle = handle;
  1103. memset(&authkey_areq.sha_op_req.digest[0], 0,
  1104. QCEDEV_MAX_SHA_DIGEST);
  1105. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  1106. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA1;
  1107. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)
  1108. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA256;
  1109. authkey_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
  1110. qcedev_sha_init(&authkey_areq, handle);
  1111. err = qcedev_sha_update(&authkey_areq, handle, sg_src);
  1112. if (!err)
  1113. err = qcedev_sha_final(&authkey_areq, handle);
  1114. else
  1115. return err;
  1116. memcpy(&authkey[0], &handle->sha_ctxt.digest[0],
  1117. handle->sha_ctxt.diglen);
  1118. qcedev_sha_init(areq, handle);
  1119. memcpy(&handle->sha_ctxt.authkey[0], &authkey[0],
  1120. handle->sha_ctxt.diglen);
  1121. }
  1122. return err;
  1123. }
  1124. static int qcedev_hmac_get_ohash(struct qcedev_async_req *qcedev_areq,
  1125. struct qcedev_handle *handle)
  1126. {
  1127. int err = 0;
  1128. struct scatterlist sg_src;
  1129. uint8_t *k_src = NULL;
  1130. uint32_t sha_block_size = 0;
  1131. uint32_t sha_digest_size = 0;
  1132. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  1133. sha_digest_size = SHA1_DIGEST_SIZE;
  1134. sha_block_size = SHA1_BLOCK_SIZE;
  1135. } else {
  1136. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  1137. sha_digest_size = SHA256_DIGEST_SIZE;
  1138. sha_block_size = SHA256_BLOCK_SIZE;
  1139. }
  1140. }
  1141. k_src = kmalloc(sha_block_size, GFP_KERNEL);
  1142. if (k_src == NULL)
  1143. return -ENOMEM;
  1144. /* check for trailing buffer from previous updates and append it */
  1145. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  1146. handle->sha_ctxt.trailing_buf_len);
  1147. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  1148. sg_init_one(qcedev_areq->sha_req.sreq.src, k_src, sha_block_size);
  1149. qcedev_areq->sha_req.sreq.nbytes = sha_block_size;
  1150. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  1151. memcpy(&handle->sha_ctxt.trailing_buf[0], &handle->sha_ctxt.digest[0],
  1152. sha_digest_size);
  1153. handle->sha_ctxt.trailing_buf_len = sha_digest_size;
  1154. handle->sha_ctxt.first_blk = 1;
  1155. handle->sha_ctxt.last_blk = 0;
  1156. handle->sha_ctxt.auth_data[0] = 0;
  1157. handle->sha_ctxt.auth_data[1] = 0;
  1158. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  1159. memcpy(&handle->sha_ctxt.digest[0],
  1160. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  1161. handle->sha_ctxt.diglen = SHA1_DIGEST_SIZE;
  1162. }
  1163. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  1164. memcpy(&handle->sha_ctxt.digest[0],
  1165. &_std_init_vector_sha256_uint8[0], SHA256_DIGEST_SIZE);
  1166. handle->sha_ctxt.diglen = SHA256_DIGEST_SIZE;
  1167. }
  1168. err = submit_req(qcedev_areq, handle);
  1169. handle->sha_ctxt.last_blk = 0;
  1170. handle->sha_ctxt.first_blk = 0;
  1171. memset(k_src, 0, sha_block_size);
  1172. kfree(k_src);
  1173. qcedev_areq->sha_req.sreq.src = NULL;
  1174. return err;
  1175. }
  1176. static int qcedev_hmac_update_iokey(struct qcedev_async_req *areq,
  1177. struct qcedev_handle *handle, bool ikey)
  1178. {
  1179. int i;
  1180. uint32_t constant;
  1181. uint32_t sha_block_size;
  1182. if (ikey)
  1183. constant = 0x36;
  1184. else
  1185. constant = 0x5c;
  1186. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  1187. sha_block_size = SHA1_BLOCK_SIZE;
  1188. else
  1189. sha_block_size = SHA256_BLOCK_SIZE;
  1190. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  1191. for (i = 0; i < sha_block_size; i++)
  1192. handle->sha_ctxt.trailing_buf[i] =
  1193. (handle->sha_ctxt.authkey[i] ^ constant);
  1194. handle->sha_ctxt.trailing_buf_len = sha_block_size;
  1195. return 0;
  1196. }
  1197. static int qcedev_hmac_init(struct qcedev_async_req *areq,
  1198. struct qcedev_handle *handle,
  1199. struct scatterlist *sg_src)
  1200. {
  1201. int err;
  1202. struct qcedev_control *podev = handle->cntl;
  1203. err = qcedev_set_hmac_auth_key(areq, handle, sg_src);
  1204. if (err)
  1205. return err;
  1206. if (!podev->ce_support.sha_hmac)
  1207. qcedev_hmac_update_iokey(areq, handle, true);
  1208. return 0;
  1209. }
  1210. static int qcedev_hmac_final(struct qcedev_async_req *areq,
  1211. struct qcedev_handle *handle)
  1212. {
  1213. int err;
  1214. struct qcedev_control *podev = handle->cntl;
  1215. err = qcedev_sha_final(areq, handle);
  1216. if (podev->ce_support.sha_hmac)
  1217. return err;
  1218. qcedev_hmac_update_iokey(areq, handle, false);
  1219. err = qcedev_hmac_get_ohash(areq, handle);
  1220. if (err)
  1221. return err;
  1222. err = qcedev_sha_final(areq, handle);
  1223. return err;
  1224. }
  1225. static int qcedev_hash_init(struct qcedev_async_req *areq,
  1226. struct qcedev_handle *handle,
  1227. struct scatterlist *sg_src)
  1228. {
  1229. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1230. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1231. return qcedev_sha_init(areq, handle);
  1232. else
  1233. return qcedev_hmac_init(areq, handle, sg_src);
  1234. }
  1235. static int qcedev_hash_update(struct qcedev_async_req *qcedev_areq,
  1236. struct qcedev_handle *handle,
  1237. struct scatterlist *sg_src)
  1238. {
  1239. return qcedev_sha_update(qcedev_areq, handle, sg_src);
  1240. }
  1241. static int qcedev_hash_final(struct qcedev_async_req *areq,
  1242. struct qcedev_handle *handle)
  1243. {
  1244. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1245. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1246. return qcedev_sha_final(areq, handle);
  1247. else
  1248. return qcedev_hmac_final(areq, handle);
  1249. }
  1250. static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
  1251. int *di, struct qcedev_handle *handle,
  1252. uint8_t *k_align_src)
  1253. {
  1254. int err = 0;
  1255. int i = 0;
  1256. int dst_i = *di;
  1257. struct scatterlist sg_src;
  1258. uint32_t byteoffset = 0;
  1259. uint8_t *user_src = NULL;
  1260. uint8_t *k_align_dst = k_align_src;
  1261. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1262. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1263. byteoffset = areq->cipher_op_req.byteoffset;
  1264. user_src = areq->cipher_op_req.vbuf.src[0].vaddr;
  1265. if (user_src && copy_from_user((k_align_src + byteoffset),
  1266. (void __user *)user_src,
  1267. areq->cipher_op_req.vbuf.src[0].len))
  1268. return -EFAULT;
  1269. k_align_src += byteoffset + areq->cipher_op_req.vbuf.src[0].len;
  1270. for (i = 1; i < areq->cipher_op_req.entries; i++) {
  1271. user_src = areq->cipher_op_req.vbuf.src[i].vaddr;
  1272. if (user_src && copy_from_user(k_align_src,
  1273. (void __user *)user_src,
  1274. areq->cipher_op_req.vbuf.src[i].len)) {
  1275. return -EFAULT;
  1276. }
  1277. k_align_src += areq->cipher_op_req.vbuf.src[i].len;
  1278. }
  1279. /* restore src beginning */
  1280. k_align_src = k_align_dst;
  1281. areq->cipher_op_req.data_len += byteoffset;
  1282. areq->cipher_req.creq.src = (struct scatterlist *) &sg_src;
  1283. areq->cipher_req.creq.dst = (struct scatterlist *) &sg_src;
  1284. /* In place encryption/decryption */
  1285. sg_init_one(areq->cipher_req.creq.src,
  1286. k_align_dst,
  1287. areq->cipher_op_req.data_len);
  1288. areq->cipher_req.creq.cryptlen = areq->cipher_op_req.data_len;
  1289. areq->cipher_req.creq.iv = areq->cipher_op_req.iv;
  1290. areq->cipher_op_req.entries = 1;
  1291. err = submit_req(areq, handle);
  1292. /* copy data to destination buffer*/
  1293. creq->data_len -= byteoffset;
  1294. while (creq->data_len > 0) {
  1295. if (creq->vbuf.dst[dst_i].len <= creq->data_len) {
  1296. if (err == 0 && copy_to_user(
  1297. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1298. (k_align_dst + byteoffset),
  1299. creq->vbuf.dst[dst_i].len)) {
  1300. err = -EFAULT;
  1301. goto exit;
  1302. }
  1303. k_align_dst += creq->vbuf.dst[dst_i].len;
  1304. creq->data_len -= creq->vbuf.dst[dst_i].len;
  1305. dst_i++;
  1306. } else {
  1307. if (err == 0 && copy_to_user(
  1308. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1309. (k_align_dst + byteoffset),
  1310. creq->data_len)) {
  1311. err = -EFAULT;
  1312. goto exit;
  1313. }
  1314. k_align_dst += creq->data_len;
  1315. creq->vbuf.dst[dst_i].len -= creq->data_len;
  1316. creq->vbuf.dst[dst_i].vaddr += creq->data_len;
  1317. creq->data_len = 0;
  1318. }
  1319. }
  1320. *di = dst_i;
  1321. exit:
  1322. areq->cipher_req.creq.src = NULL;
  1323. areq->cipher_req.creq.dst = NULL;
  1324. return err;
  1325. };
  1326. static int qcedev_vbuf_ablk_cipher(struct qcedev_async_req *areq,
  1327. struct qcedev_handle *handle)
  1328. {
  1329. int err = 0;
  1330. int di = 0;
  1331. int i = 0;
  1332. int j = 0;
  1333. int k = 0;
  1334. uint32_t byteoffset = 0;
  1335. int num_entries = 0;
  1336. uint32_t total = 0;
  1337. uint32_t len;
  1338. uint8_t *k_buf_src = NULL;
  1339. uint32_t buf_size = 0;
  1340. uint8_t *k_align_src = NULL;
  1341. uint32_t max_data_xfer;
  1342. struct qcedev_cipher_op_req *saved_req;
  1343. uint32_t req_size = 0;
  1344. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1345. total = 0;
  1346. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1347. byteoffset = areq->cipher_op_req.byteoffset;
  1348. buf_size = QCE_MAX_OPER_DATA + CACHE_LINE_SIZE * 2;
  1349. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1350. if (k_buf_src == NULL)
  1351. return -ENOMEM;
  1352. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  1353. CACHE_LINE_SIZE);
  1354. max_data_xfer = QCE_MAX_OPER_DATA - byteoffset;
  1355. req_size = sizeof(struct qcedev_cipher_op_req);
  1356. saved_req = kmemdup(creq, req_size, GFP_KERNEL);
  1357. if (saved_req == NULL) {
  1358. memset(k_buf_src, 0, buf_size);
  1359. kfree(k_buf_src);
  1360. return -ENOMEM;
  1361. }
  1362. if (areq->cipher_op_req.data_len > max_data_xfer) {
  1363. struct qcedev_cipher_op_req req;
  1364. /* save the original req structure */
  1365. memcpy(&req, creq, sizeof(struct qcedev_cipher_op_req));
  1366. i = 0;
  1367. /* Address 32 KB at a time */
  1368. while ((i < req.entries) && (err == 0)) {
  1369. if (creq->vbuf.src[i].len > max_data_xfer) {
  1370. creq->vbuf.src[0].len = max_data_xfer;
  1371. if (i > 0) {
  1372. creq->vbuf.src[0].vaddr =
  1373. creq->vbuf.src[i].vaddr;
  1374. }
  1375. creq->data_len = max_data_xfer;
  1376. creq->entries = 1;
  1377. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1378. &di, handle, k_align_src);
  1379. if (err < 0) {
  1380. memset(saved_req, 0, req_size);
  1381. memset(k_buf_src, 0, buf_size);
  1382. kfree(k_buf_src);
  1383. kfree(saved_req);
  1384. return err;
  1385. }
  1386. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1387. max_data_xfer;
  1388. creq->vbuf.src[i].vaddr =
  1389. req.vbuf.src[i].vaddr +
  1390. max_data_xfer;
  1391. req.vbuf.src[i].vaddr =
  1392. creq->vbuf.src[i].vaddr;
  1393. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1394. } else {
  1395. total = areq->cipher_op_req.byteoffset;
  1396. for (j = i; j < req.entries; j++) {
  1397. num_entries++;
  1398. if ((total + creq->vbuf.src[j].len)
  1399. >= max_data_xfer) {
  1400. creq->vbuf.src[j].len =
  1401. max_data_xfer - total;
  1402. total = max_data_xfer;
  1403. break;
  1404. }
  1405. total += creq->vbuf.src[j].len;
  1406. }
  1407. creq->data_len = total;
  1408. if (i > 0)
  1409. for (k = 0; k < num_entries; k++) {
  1410. creq->vbuf.src[k].len =
  1411. creq->vbuf.src[i+k].len;
  1412. creq->vbuf.src[k].vaddr =
  1413. creq->vbuf.src[i+k].vaddr;
  1414. }
  1415. creq->entries = num_entries;
  1416. i = j;
  1417. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1418. &di, handle, k_align_src);
  1419. if (err < 0) {
  1420. memset(saved_req, 0, req_size);
  1421. memset(k_buf_src, 0, buf_size);
  1422. kfree(k_buf_src);
  1423. kfree(saved_req);
  1424. return err;
  1425. }
  1426. num_entries = 0;
  1427. areq->cipher_op_req.byteoffset = 0;
  1428. creq->vbuf.src[i].vaddr = req.vbuf.src[i].vaddr
  1429. + creq->vbuf.src[i].len;
  1430. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1431. creq->vbuf.src[i].len;
  1432. req.vbuf.src[i].vaddr =
  1433. creq->vbuf.src[i].vaddr;
  1434. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1435. if (creq->vbuf.src[i].len == 0)
  1436. i++;
  1437. }
  1438. areq->cipher_op_req.byteoffset = 0;
  1439. max_data_xfer = QCE_MAX_OPER_DATA;
  1440. byteoffset = 0;
  1441. } /* end of while ((i < req.entries) && (err == 0)) */
  1442. } else
  1443. err = qcedev_vbuf_ablk_cipher_max_xfer(areq, &di, handle,
  1444. k_align_src);
  1445. /* Restore the original req structure */
  1446. for (i = 0; i < saved_req->entries; i++) {
  1447. creq->vbuf.src[i].len = saved_req->vbuf.src[i].len;
  1448. creq->vbuf.src[i].vaddr = saved_req->vbuf.src[i].vaddr;
  1449. }
  1450. for (len = 0, i = 0; len < saved_req->data_len; i++) {
  1451. creq->vbuf.dst[i].len = saved_req->vbuf.dst[i].len;
  1452. creq->vbuf.dst[i].vaddr = saved_req->vbuf.dst[i].vaddr;
  1453. len += saved_req->vbuf.dst[i].len;
  1454. }
  1455. creq->entries = saved_req->entries;
  1456. creq->data_len = saved_req->data_len;
  1457. creq->byteoffset = saved_req->byteoffset;
  1458. memset(saved_req, 0, req_size);
  1459. memset(k_buf_src, 0, buf_size);
  1460. kfree(saved_req);
  1461. kfree(k_buf_src);
  1462. return err;
  1463. }
  1464. static int qcedev_smmu_ablk_offload_cipher(struct qcedev_async_req *areq,
  1465. struct qcedev_handle *handle)
  1466. {
  1467. int i = 0;
  1468. int err = 0;
  1469. size_t byteoffset = 0;
  1470. size_t transfer_data_len = 0;
  1471. size_t pending_data_len = 0;
  1472. size_t max_data_xfer = MAX_CEHW_REQ_TRANSFER_SIZE - byteoffset;
  1473. uint8_t *user_src = NULL;
  1474. uint8_t *user_dst = NULL;
  1475. struct scatterlist sg_src;
  1476. struct scatterlist sg_dst;
  1477. if (areq->offload_cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1478. byteoffset = areq->offload_cipher_op_req.byteoffset;
  1479. /*
  1480. * areq has two components:
  1481. * a) Request that comes from userspace i.e. offload_cipher_op_req
  1482. * b) Request that QCE understands - skcipher i.e. cipher_req.creq
  1483. * skcipher has sglist pointers src and dest that would carry
  1484. * data to/from CE.
  1485. */
  1486. areq->cipher_req.creq.src = &sg_src;
  1487. areq->cipher_req.creq.dst = &sg_dst;
  1488. sg_init_table(&sg_src, 1);
  1489. sg_init_table(&sg_dst, 1);
  1490. for (i = 0; i < areq->offload_cipher_op_req.entries; i++) {
  1491. transfer_data_len = 0;
  1492. pending_data_len = areq->offload_cipher_op_req.vbuf.src[i].len;
  1493. user_src = areq->offload_cipher_op_req.vbuf.src[i].vaddr;
  1494. user_src += byteoffset;
  1495. user_dst = areq->offload_cipher_op_req.vbuf.dst[i].vaddr;
  1496. user_dst += byteoffset;
  1497. areq->cipher_req.creq.iv = areq->offload_cipher_op_req.iv;
  1498. while (pending_data_len) {
  1499. transfer_data_len = min(max_data_xfer,
  1500. pending_data_len);
  1501. sg_src.dma_address = (dma_addr_t)user_src;
  1502. sg_dst.dma_address = (dma_addr_t)user_dst;
  1503. areq->cipher_req.creq.cryptlen = transfer_data_len;
  1504. sg_src.length = transfer_data_len;
  1505. sg_dst.length = transfer_data_len;
  1506. err = submit_req(areq, handle);
  1507. if (err) {
  1508. pr_err("%s: Error processing req, err = %d\n",
  1509. __func__, err);
  1510. goto exit;
  1511. }
  1512. /* update data len to be processed */
  1513. pending_data_len -= transfer_data_len;
  1514. user_src += transfer_data_len;
  1515. user_dst += transfer_data_len;
  1516. }
  1517. }
  1518. exit:
  1519. areq->cipher_req.creq.src = NULL;
  1520. areq->cipher_req.creq.dst = NULL;
  1521. return err;
  1522. }
  1523. static int qcedev_check_cipher_key(struct qcedev_cipher_op_req *req,
  1524. struct qcedev_control *podev)
  1525. {
  1526. /* if intending to use HW key make sure key fields are set
  1527. * correctly and HW key is indeed supported in target
  1528. */
  1529. if (req->encklen == 0) {
  1530. int i;
  1531. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  1532. if (req->enckey[i]) {
  1533. pr_err("%s: Invalid key: non-zero key input\n",
  1534. __func__);
  1535. goto error;
  1536. }
  1537. }
  1538. if ((req->op != QCEDEV_OPER_ENC_NO_KEY) &&
  1539. (req->op != QCEDEV_OPER_DEC_NO_KEY))
  1540. if (!podev->platform_support.hw_key_support) {
  1541. pr_err("%s: Invalid op %d\n", __func__,
  1542. (uint32_t)req->op);
  1543. goto error;
  1544. }
  1545. } else {
  1546. if (req->encklen == QCEDEV_AES_KEY_192) {
  1547. if (!podev->ce_support.aes_key_192) {
  1548. pr_err("%s: AES-192 not supported\n", __func__);
  1549. goto error;
  1550. }
  1551. } else {
  1552. /* if not using HW key make sure key
  1553. * length is valid
  1554. */
  1555. if (req->mode == QCEDEV_AES_MODE_XTS) {
  1556. if ((req->encklen != QCEDEV_AES_KEY_128*2) &&
  1557. (req->encklen != QCEDEV_AES_KEY_256*2)) {
  1558. pr_err("%s: unsupported key size: %d\n",
  1559. __func__, req->encklen);
  1560. goto error;
  1561. }
  1562. } else {
  1563. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1564. (req->encklen != QCEDEV_AES_KEY_256)) {
  1565. pr_err("%s: unsupported key size %d\n",
  1566. __func__, req->encklen);
  1567. goto error;
  1568. }
  1569. }
  1570. }
  1571. }
  1572. return 0;
  1573. error:
  1574. return -EINVAL;
  1575. }
  1576. static int qcedev_check_cipher_params(struct qcedev_cipher_op_req *req,
  1577. struct qcedev_control *podev)
  1578. {
  1579. uint32_t total = 0;
  1580. uint32_t i;
  1581. if (req->use_pmem) {
  1582. pr_err("%s: Use of PMEM is not supported\n", __func__);
  1583. goto error;
  1584. }
  1585. if ((req->entries == 0) || (req->data_len == 0) ||
  1586. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1587. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1588. goto error;
  1589. }
  1590. if ((req->alg >= QCEDEV_ALG_LAST) ||
  1591. (req->mode >= QCEDEV_AES_DES_MODE_LAST)) {
  1592. pr_err("%s: Invalid algorithm %d\n", __func__,
  1593. (uint32_t)req->alg);
  1594. goto error;
  1595. }
  1596. if ((req->mode == QCEDEV_AES_MODE_XTS) &&
  1597. (!podev->ce_support.aes_xts)) {
  1598. pr_err("%s: XTS algorithm is not supported\n", __func__);
  1599. goto error;
  1600. }
  1601. if (req->alg == QCEDEV_ALG_AES) {
  1602. if (qcedev_check_cipher_key(req, podev))
  1603. goto error;
  1604. }
  1605. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1606. if (req->byteoffset) {
  1607. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1608. pr_err("%s: Operation on byte offset not supported\n",
  1609. __func__);
  1610. goto error;
  1611. }
  1612. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1613. pr_err("%s: Invalid byte offset\n", __func__);
  1614. goto error;
  1615. }
  1616. total = req->byteoffset;
  1617. for (i = 0; i < req->entries; i++) {
  1618. if (total > U32_MAX - req->vbuf.src[i].len) {
  1619. pr_err("%s:Integer overflow on total src len\n",
  1620. __func__);
  1621. goto error;
  1622. }
  1623. total += req->vbuf.src[i].len;
  1624. }
  1625. }
  1626. if (req->data_len < req->byteoffset) {
  1627. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1628. __func__, req->data_len, req->byteoffset);
  1629. goto error;
  1630. }
  1631. /* Ensure IV size */
  1632. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1633. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1634. goto error;
  1635. }
  1636. /* Ensure Key size */
  1637. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1638. pr_err("%s: Klen is not correct: %u\n", __func__, req->encklen);
  1639. goto error;
  1640. }
  1641. /* Ensure zer ivlen for ECB mode */
  1642. if (req->ivlen > 0) {
  1643. if ((req->mode == QCEDEV_AES_MODE_ECB) ||
  1644. (req->mode == QCEDEV_DES_MODE_ECB)) {
  1645. pr_err("%s: Expecting a zero length IV\n", __func__);
  1646. goto error;
  1647. }
  1648. } else {
  1649. if ((req->mode != QCEDEV_AES_MODE_ECB) &&
  1650. (req->mode != QCEDEV_DES_MODE_ECB)) {
  1651. pr_err("%s: Expecting a non-zero ength IV\n", __func__);
  1652. goto error;
  1653. }
  1654. }
  1655. /* Check for sum of all dst length is equal to data_len */
  1656. for (i = 0, total = 0; i < req->entries; i++) {
  1657. if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
  1658. pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
  1659. __func__, i, req->vbuf.dst[i].len);
  1660. goto error;
  1661. }
  1662. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1663. pr_err("%s: Integer overflow on total req dst vbuf length\n",
  1664. __func__);
  1665. goto error;
  1666. }
  1667. total += req->vbuf.dst[i].len;
  1668. }
  1669. if (total != req->data_len) {
  1670. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1671. __func__, i, total, req->data_len);
  1672. goto error;
  1673. }
  1674. /* Check for sum of all src length is equal to data_len */
  1675. for (i = 0, total = 0; i < req->entries; i++) {
  1676. if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
  1677. pr_err("%s: NULL req src vbuf[%d] with length %d\n",
  1678. __func__, i, req->vbuf.src[i].len);
  1679. goto error;
  1680. }
  1681. if (req->vbuf.src[i].len > U32_MAX - total) {
  1682. pr_err("%s: Integer overflow on total req src vbuf length\n",
  1683. __func__);
  1684. goto error;
  1685. }
  1686. total += req->vbuf.src[i].len;
  1687. }
  1688. if (total != req->data_len) {
  1689. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1690. __func__, total, req->data_len);
  1691. goto error;
  1692. }
  1693. return 0;
  1694. error:
  1695. return -EINVAL;
  1696. }
  1697. static int qcedev_check_sha_params(struct qcedev_sha_op_req *req,
  1698. struct qcedev_control *podev)
  1699. {
  1700. uint32_t total = 0;
  1701. uint32_t i;
  1702. if ((req->alg == QCEDEV_ALG_AES_CMAC) &&
  1703. (!podev->ce_support.cmac)) {
  1704. pr_err("%s: CMAC not supported\n", __func__);
  1705. goto sha_error;
  1706. }
  1707. if ((!req->entries) || (req->entries > QCEDEV_MAX_BUFFERS)) {
  1708. pr_err("%s: Invalid num entries (%d)\n",
  1709. __func__, req->entries);
  1710. goto sha_error;
  1711. }
  1712. if (req->alg >= QCEDEV_ALG_SHA_ALG_LAST) {
  1713. pr_err("%s: Invalid algorithm (%d)\n", __func__, req->alg);
  1714. goto sha_error;
  1715. }
  1716. if ((req->alg == QCEDEV_ALG_SHA1_HMAC) ||
  1717. (req->alg == QCEDEV_ALG_SHA256_HMAC)) {
  1718. if (req->authkey == NULL) {
  1719. pr_err("%s: Invalid authkey pointer\n", __func__);
  1720. goto sha_error;
  1721. }
  1722. if (req->authklen <= 0) {
  1723. pr_err("%s: Invalid authkey length (%d)\n",
  1724. __func__, req->authklen);
  1725. goto sha_error;
  1726. }
  1727. }
  1728. if (req->alg == QCEDEV_ALG_AES_CMAC) {
  1729. if ((req->authklen != QCEDEV_AES_KEY_128) &&
  1730. (req->authklen != QCEDEV_AES_KEY_256)) {
  1731. pr_err("%s: unsupported key length\n", __func__);
  1732. goto sha_error;
  1733. }
  1734. }
  1735. /* Check for sum of all src length is equal to data_len */
  1736. for (i = 0, total = 0; i < req->entries; i++) {
  1737. if (req->data[i].len > U32_MAX - total) {
  1738. pr_err("%s: Integer overflow on total req buf length\n",
  1739. __func__);
  1740. goto sha_error;
  1741. }
  1742. total += req->data[i].len;
  1743. }
  1744. if (total != req->data_len) {
  1745. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1746. __func__, total, req->data_len);
  1747. goto sha_error;
  1748. }
  1749. return 0;
  1750. sha_error:
  1751. return -EINVAL;
  1752. }
  1753. static int qcedev_check_offload_cipher_key(struct qcedev_offload_cipher_op_req *req,
  1754. struct qcedev_control *podev)
  1755. {
  1756. if (req->encklen == 0)
  1757. return -EINVAL;
  1758. /* AES-192 is not a valid option for OFFLOAD use case */
  1759. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1760. (req->encklen != QCEDEV_AES_KEY_256)) {
  1761. pr_err("%s: unsupported key size %d\n",
  1762. __func__, req->encklen);
  1763. goto error;
  1764. }
  1765. return 0;
  1766. error:
  1767. return -EINVAL;
  1768. }
  1769. static int qcedev_check_offload_cipher_params(struct qcedev_offload_cipher_op_req *req,
  1770. struct qcedev_control *podev)
  1771. {
  1772. uint32_t total = 0;
  1773. int i = 0;
  1774. if ((req->entries == 0) || (req->data_len == 0) ||
  1775. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1776. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1777. goto error;
  1778. }
  1779. if ((req->alg != QCEDEV_ALG_AES) ||
  1780. (req->mode > QCEDEV_AES_MODE_CTR)) {
  1781. pr_err("%s: Invalid algorithm %d\n", __func__,
  1782. (uint32_t)req->alg);
  1783. goto error;
  1784. }
  1785. if (qcedev_check_offload_cipher_key(req, podev))
  1786. goto error;
  1787. if (req->block_offset >= AES_CE_BLOCK_SIZE)
  1788. goto error;
  1789. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1790. if (req->byteoffset) {
  1791. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1792. pr_err("%s: Operation on byte offset not supported\n",
  1793. __func__);
  1794. goto error;
  1795. }
  1796. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1797. pr_err("%s: Invalid byte offset\n", __func__);
  1798. goto error;
  1799. }
  1800. total = req->byteoffset;
  1801. for (i = 0; i < req->entries; i++) {
  1802. if (total > U32_MAX - req->vbuf.src[i].len) {
  1803. pr_err("%s:Int overflow on total src len\n",
  1804. __func__);
  1805. goto error;
  1806. }
  1807. total += req->vbuf.src[i].len;
  1808. }
  1809. }
  1810. if (req->data_len < req->byteoffset) {
  1811. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1812. __func__, req->data_len, req->byteoffset);
  1813. goto error;
  1814. }
  1815. /* Ensure IV size */
  1816. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1817. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1818. goto error;
  1819. }
  1820. /* Ensure Key size */
  1821. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1822. pr_err("%s: Klen is not correct: %u\n", __func__,
  1823. req->encklen);
  1824. goto error;
  1825. }
  1826. /* Check for sum of all dst length is equal to data_len */
  1827. for (i = 0, total = 0; i < req->entries; i++) {
  1828. if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
  1829. pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
  1830. __func__, i, req->vbuf.dst[i].len);
  1831. goto error;
  1832. }
  1833. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1834. pr_err("%s: Int overflow on total req dst vbuf len\n",
  1835. __func__);
  1836. goto error;
  1837. }
  1838. total += req->vbuf.dst[i].len;
  1839. }
  1840. if (total != req->data_len) {
  1841. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1842. __func__, i, total, req->data_len);
  1843. goto error;
  1844. }
  1845. /* Check for sum of all src length is equal to data_len */
  1846. for (i = 0, total = 0; i < req->entries; i++) {
  1847. if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
  1848. pr_err("%s: NULL req src vbuf[%d] with length %d\n",
  1849. __func__, i, req->vbuf.src[i].len);
  1850. goto error;
  1851. }
  1852. if (req->vbuf.src[i].len > U32_MAX - total) {
  1853. pr_err("%s: Int overflow on total req src vbuf len\n",
  1854. __func__);
  1855. goto error;
  1856. }
  1857. total += req->vbuf.src[i].len;
  1858. }
  1859. if (total != req->data_len) {
  1860. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1861. __func__, total, req->data_len);
  1862. goto error;
  1863. }
  1864. return 0;
  1865. error:
  1866. return -EINVAL;
  1867. }
  1868. long qcedev_ioctl(struct file *file,
  1869. unsigned int cmd, unsigned long arg)
  1870. {
  1871. int err = 0;
  1872. struct qcedev_handle *handle;
  1873. struct qcedev_control *podev;
  1874. struct qcedev_async_req *qcedev_areq;
  1875. struct qcedev_stat *pstat;
  1876. qcedev_areq = kzalloc(sizeof(struct qcedev_async_req), GFP_KERNEL);
  1877. if (!qcedev_areq)
  1878. return -ENOMEM;
  1879. handle = file->private_data;
  1880. podev = handle->cntl;
  1881. qcedev_areq->handle = handle;
  1882. if (podev == NULL || podev->magic != QCEDEV_MAGIC) {
  1883. pr_err("%s: invalid handle %pK\n",
  1884. __func__, podev);
  1885. err = -ENOENT;
  1886. goto exit_free_qcedev_areq;
  1887. }
  1888. /* Verify user arguments. */
  1889. if (_IOC_TYPE(cmd) != QCEDEV_IOC_MAGIC) {
  1890. err = -ENOTTY;
  1891. goto exit_free_qcedev_areq;
  1892. }
  1893. init_completion(&qcedev_areq->complete);
  1894. pstat = &_qcedev_stat;
  1895. switch (cmd) {
  1896. case QCEDEV_IOCTL_ENC_REQ:
  1897. case QCEDEV_IOCTL_DEC_REQ:
  1898. if (copy_from_user(&qcedev_areq->cipher_op_req,
  1899. (void __user *)arg,
  1900. sizeof(struct qcedev_cipher_op_req))) {
  1901. err = -EFAULT;
  1902. goto exit_free_qcedev_areq;
  1903. }
  1904. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_CIPHER;
  1905. if (qcedev_check_cipher_params(&qcedev_areq->cipher_op_req,
  1906. podev)) {
  1907. err = -EINVAL;
  1908. goto exit_free_qcedev_areq;
  1909. }
  1910. err = qcedev_vbuf_ablk_cipher(qcedev_areq, handle);
  1911. if (err)
  1912. goto exit_free_qcedev_areq;
  1913. if (copy_to_user((void __user *)arg,
  1914. &qcedev_areq->cipher_op_req,
  1915. sizeof(struct qcedev_cipher_op_req))) {
  1916. err = -EFAULT;
  1917. goto exit_free_qcedev_areq;
  1918. }
  1919. break;
  1920. case QCEDEV_IOCTL_OFFLOAD_OP_REQ:
  1921. if (copy_from_user(&qcedev_areq->offload_cipher_op_req,
  1922. (void __user *)arg,
  1923. sizeof(struct qcedev_offload_cipher_op_req))) {
  1924. err = -EFAULT;
  1925. goto exit_free_qcedev_areq;
  1926. }
  1927. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER;
  1928. if (qcedev_check_offload_cipher_params(
  1929. &qcedev_areq->offload_cipher_op_req, podev)) {
  1930. err = -EINVAL;
  1931. goto exit_free_qcedev_areq;
  1932. }
  1933. qcedev_areq->offload_cipher_op_req.err = QCEDEV_OFFLOAD_NO_ERROR;
  1934. err = qcedev_smmu_ablk_offload_cipher(qcedev_areq, handle);
  1935. if (err)
  1936. goto exit_free_qcedev_areq;
  1937. if (copy_to_user((void __user *)arg,
  1938. &qcedev_areq->offload_cipher_op_req,
  1939. sizeof(struct qcedev_offload_cipher_op_req))) {
  1940. err = -EFAULT;
  1941. goto exit_free_qcedev_areq;
  1942. }
  1943. break;
  1944. case QCEDEV_IOCTL_SHA_INIT_REQ:
  1945. {
  1946. struct scatterlist sg_src;
  1947. if (copy_from_user(&qcedev_areq->sha_op_req,
  1948. (void __user *)arg,
  1949. sizeof(struct qcedev_sha_op_req))) {
  1950. err = -EFAULT;
  1951. goto exit_free_qcedev_areq;
  1952. }
  1953. mutex_lock(&hash_access_lock);
  1954. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  1955. mutex_unlock(&hash_access_lock);
  1956. err = -EINVAL;
  1957. goto exit_free_qcedev_areq;
  1958. }
  1959. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  1960. err = qcedev_hash_init(qcedev_areq, handle, &sg_src);
  1961. if (err) {
  1962. mutex_unlock(&hash_access_lock);
  1963. goto exit_free_qcedev_areq;
  1964. }
  1965. mutex_unlock(&hash_access_lock);
  1966. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  1967. sizeof(struct qcedev_sha_op_req))) {
  1968. err = -EFAULT;
  1969. goto exit_free_qcedev_areq;
  1970. }
  1971. handle->sha_ctxt.init_done = true;
  1972. }
  1973. break;
  1974. case QCEDEV_IOCTL_GET_CMAC_REQ:
  1975. if (!podev->ce_support.cmac) {
  1976. err = -ENOTTY;
  1977. goto exit_free_qcedev_areq;
  1978. }
  1979. fallthrough;
  1980. case QCEDEV_IOCTL_SHA_UPDATE_REQ:
  1981. {
  1982. struct scatterlist sg_src;
  1983. if (copy_from_user(&qcedev_areq->sha_op_req,
  1984. (void __user *)arg,
  1985. sizeof(struct qcedev_sha_op_req))) {
  1986. err = -EFAULT;
  1987. goto exit_free_qcedev_areq;
  1988. }
  1989. mutex_lock(&hash_access_lock);
  1990. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  1991. mutex_unlock(&hash_access_lock);
  1992. err = -EINVAL;
  1993. goto exit_free_qcedev_areq;
  1994. }
  1995. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  1996. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_AES_CMAC) {
  1997. err = qcedev_hash_cmac(qcedev_areq, handle, &sg_src);
  1998. if (err) {
  1999. mutex_unlock(&hash_access_lock);
  2000. goto exit_free_qcedev_areq;
  2001. }
  2002. } else {
  2003. if (!handle->sha_ctxt.init_done) {
  2004. pr_err("%s Init was not called\n", __func__);
  2005. mutex_unlock(&hash_access_lock);
  2006. err = -EINVAL;
  2007. goto exit_free_qcedev_areq;
  2008. }
  2009. err = qcedev_hash_update(qcedev_areq, handle, &sg_src);
  2010. if (err) {
  2011. mutex_unlock(&hash_access_lock);
  2012. goto exit_free_qcedev_areq;
  2013. }
  2014. }
  2015. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2016. pr_err("Invalid sha_ctxt.diglen %d\n",
  2017. handle->sha_ctxt.diglen);
  2018. mutex_unlock(&hash_access_lock);
  2019. err = -EINVAL;
  2020. goto exit_free_qcedev_areq;
  2021. }
  2022. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2023. &handle->sha_ctxt.digest[0],
  2024. handle->sha_ctxt.diglen);
  2025. mutex_unlock(&hash_access_lock);
  2026. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2027. sizeof(struct qcedev_sha_op_req))) {
  2028. err = -EFAULT;
  2029. goto exit_free_qcedev_areq;
  2030. }
  2031. }
  2032. break;
  2033. case QCEDEV_IOCTL_SHA_FINAL_REQ:
  2034. if (!handle->sha_ctxt.init_done) {
  2035. pr_err("%s Init was not called\n", __func__);
  2036. err = -EINVAL;
  2037. goto exit_free_qcedev_areq;
  2038. }
  2039. if (copy_from_user(&qcedev_areq->sha_op_req,
  2040. (void __user *)arg,
  2041. sizeof(struct qcedev_sha_op_req))) {
  2042. err = -EFAULT;
  2043. goto exit_free_qcedev_areq;
  2044. }
  2045. mutex_lock(&hash_access_lock);
  2046. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  2047. mutex_unlock(&hash_access_lock);
  2048. err = -EINVAL;
  2049. goto exit_free_qcedev_areq;
  2050. }
  2051. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  2052. err = qcedev_hash_final(qcedev_areq, handle);
  2053. if (err) {
  2054. mutex_unlock(&hash_access_lock);
  2055. goto exit_free_qcedev_areq;
  2056. }
  2057. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2058. pr_err("Invalid sha_ctxt.diglen %d\n",
  2059. handle->sha_ctxt.diglen);
  2060. mutex_unlock(&hash_access_lock);
  2061. err = -EINVAL;
  2062. goto exit_free_qcedev_areq;
  2063. }
  2064. qcedev_areq->sha_op_req.diglen = handle->sha_ctxt.diglen;
  2065. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2066. &handle->sha_ctxt.digest[0],
  2067. handle->sha_ctxt.diglen);
  2068. mutex_unlock(&hash_access_lock);
  2069. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2070. sizeof(struct qcedev_sha_op_req))) {
  2071. err = -EFAULT;
  2072. goto exit_free_qcedev_areq;
  2073. }
  2074. handle->sha_ctxt.init_done = false;
  2075. break;
  2076. case QCEDEV_IOCTL_GET_SHA_REQ:
  2077. {
  2078. struct scatterlist sg_src;
  2079. if (copy_from_user(&qcedev_areq->sha_op_req,
  2080. (void __user *)arg,
  2081. sizeof(struct qcedev_sha_op_req))) {
  2082. err = -EFAULT;
  2083. goto exit_free_qcedev_areq;
  2084. }
  2085. mutex_lock(&hash_access_lock);
  2086. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  2087. mutex_unlock(&hash_access_lock);
  2088. err = -EINVAL;
  2089. goto exit_free_qcedev_areq;
  2090. }
  2091. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  2092. qcedev_hash_init(qcedev_areq, handle, &sg_src);
  2093. err = qcedev_hash_update(qcedev_areq, handle, &sg_src);
  2094. if (err) {
  2095. mutex_unlock(&hash_access_lock);
  2096. goto exit_free_qcedev_areq;
  2097. }
  2098. err = qcedev_hash_final(qcedev_areq, handle);
  2099. if (err) {
  2100. mutex_unlock(&hash_access_lock);
  2101. goto exit_free_qcedev_areq;
  2102. }
  2103. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2104. pr_err("Invalid sha_ctxt.diglen %d\n",
  2105. handle->sha_ctxt.diglen);
  2106. mutex_unlock(&hash_access_lock);
  2107. err = -EINVAL;
  2108. goto exit_free_qcedev_areq;
  2109. }
  2110. qcedev_areq->sha_op_req.diglen = handle->sha_ctxt.diglen;
  2111. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2112. &handle->sha_ctxt.digest[0],
  2113. handle->sha_ctxt.diglen);
  2114. mutex_unlock(&hash_access_lock);
  2115. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2116. sizeof(struct qcedev_sha_op_req))) {
  2117. err = -EFAULT;
  2118. goto exit_free_qcedev_areq;
  2119. }
  2120. }
  2121. break;
  2122. case QCEDEV_IOCTL_MAP_BUF_REQ:
  2123. {
  2124. unsigned long long vaddr = 0;
  2125. struct qcedev_map_buf_req map_buf = { {0} };
  2126. int i = 0;
  2127. if (copy_from_user(&map_buf,
  2128. (void __user *)arg, sizeof(map_buf))) {
  2129. err = -EFAULT;
  2130. goto exit_free_qcedev_areq;
  2131. }
  2132. if (map_buf.num_fds > ARRAY_SIZE(map_buf.fd)) {
  2133. pr_err("%s: err: num_fds = %d exceeds max value\n",
  2134. __func__, map_buf.num_fds);
  2135. err = -EINVAL;
  2136. goto exit_free_qcedev_areq;
  2137. }
  2138. for (i = 0; i < map_buf.num_fds; i++) {
  2139. err = qcedev_check_and_map_buffer(handle,
  2140. map_buf.fd[i],
  2141. map_buf.fd_offset[i],
  2142. map_buf.fd_size[i],
  2143. &vaddr);
  2144. if (err) {
  2145. pr_err(
  2146. "%s: err: failed to map fd(%d) - %d\n",
  2147. __func__, map_buf.fd[i], err);
  2148. goto exit_free_qcedev_areq;
  2149. }
  2150. map_buf.buf_vaddr[i] = vaddr;
  2151. pr_info("%s: info: vaddr = %llx\n, fd = %d",
  2152. __func__, vaddr, map_buf.fd[i]);
  2153. }
  2154. if (copy_to_user((void __user *)arg, &map_buf,
  2155. sizeof(map_buf))) {
  2156. err = -EFAULT;
  2157. goto exit_free_qcedev_areq;
  2158. }
  2159. break;
  2160. }
  2161. case QCEDEV_IOCTL_UNMAP_BUF_REQ:
  2162. {
  2163. struct qcedev_unmap_buf_req unmap_buf = { { 0 } };
  2164. int i = 0;
  2165. if (copy_from_user(&unmap_buf,
  2166. (void __user *)arg, sizeof(unmap_buf))) {
  2167. err = -EFAULT;
  2168. goto exit_free_qcedev_areq;
  2169. }
  2170. if (unmap_buf.num_fds > ARRAY_SIZE(unmap_buf.fd)) {
  2171. pr_err("%s: err: num_fds = %d exceeds max value\n",
  2172. __func__, unmap_buf.num_fds);
  2173. err = -EINVAL;
  2174. goto exit_free_qcedev_areq;
  2175. }
  2176. for (i = 0; i < unmap_buf.num_fds; i++) {
  2177. err = qcedev_check_and_unmap_buffer(handle,
  2178. unmap_buf.fd[i]);
  2179. if (err) {
  2180. pr_err(
  2181. "%s: err: failed to unmap fd(%d) - %d\n",
  2182. __func__,
  2183. unmap_buf.fd[i], err);
  2184. goto exit_free_qcedev_areq;
  2185. }
  2186. }
  2187. break;
  2188. }
  2189. default:
  2190. err = -ENOTTY;
  2191. goto exit_free_qcedev_areq;
  2192. }
  2193. exit_free_qcedev_areq:
  2194. kfree(qcedev_areq);
  2195. return err;
  2196. }
  2197. static int qcedev_probe_device(struct platform_device *pdev)
  2198. {
  2199. void *handle = NULL;
  2200. int rc = 0;
  2201. struct qcedev_control *podev;
  2202. struct msm_ce_hw_support *platform_support;
  2203. podev = &qce_dev[0];
  2204. rc = alloc_chrdev_region(&qcedev_device_no, 0, 1, QCEDEV_DEV);
  2205. if (rc < 0) {
  2206. pr_err("alloc_chrdev_region failed %d\n", rc);
  2207. return rc;
  2208. }
  2209. driver_class = class_create(THIS_MODULE, QCEDEV_DEV);
  2210. if (IS_ERR(driver_class)) {
  2211. rc = -ENOMEM;
  2212. pr_err("class_create failed %d\n", rc);
  2213. goto exit_unreg_chrdev_region;
  2214. }
  2215. class_dev = device_create(driver_class, NULL, qcedev_device_no, NULL,
  2216. QCEDEV_DEV);
  2217. if (IS_ERR(class_dev)) {
  2218. pr_err("class_device_create failed %d\n", rc);
  2219. rc = -ENOMEM;
  2220. goto exit_destroy_class;
  2221. }
  2222. cdev_init(&podev->cdev, &qcedev_fops);
  2223. podev->cdev.owner = THIS_MODULE;
  2224. rc = cdev_add(&podev->cdev, MKDEV(MAJOR(qcedev_device_no), 0), 1);
  2225. if (rc < 0) {
  2226. pr_err("cdev_add failed %d\n", rc);
  2227. goto exit_destroy_device;
  2228. }
  2229. podev->minor = 0;
  2230. podev->high_bw_req_count = 0;
  2231. INIT_LIST_HEAD(&podev->ready_commands);
  2232. podev->active_command = NULL;
  2233. INIT_LIST_HEAD(&podev->context_banks);
  2234. spin_lock_init(&podev->lock);
  2235. tasklet_init(&podev->done_tasklet, req_done, (unsigned long)podev);
  2236. podev->icc_path = of_icc_get(&pdev->dev, "data_path");
  2237. if (IS_ERR(podev->icc_path)) {
  2238. rc = PTR_ERR(podev->icc_path);
  2239. pr_err("%s Failed to get icc path with error %d\n",
  2240. __func__, rc);
  2241. goto exit_del_cdev;
  2242. }
  2243. /*
  2244. * HLOS crypto vote values from DTSI. If no values specified, use
  2245. * nominal values.
  2246. */
  2247. if (of_property_read_u32((&pdev->dev)->of_node,
  2248. "qcom,icc_avg_bw",
  2249. &podev->icc_avg_bw)) {
  2250. pr_warn("%s: No icc avg BW set, using default\n", __func__);
  2251. podev->icc_avg_bw = CRYPTO_AVG_BW;
  2252. }
  2253. if (of_property_read_u32((&pdev->dev)->of_node,
  2254. "qcom,icc_peak_bw",
  2255. &podev->icc_peak_bw)) {
  2256. pr_warn("%s: No icc peak BW set, using default\n", __func__);
  2257. podev->icc_peak_bw = CRYPTO_PEAK_BW;
  2258. }
  2259. rc = icc_set_bw(podev->icc_path, podev->icc_avg_bw,
  2260. podev->icc_peak_bw);
  2261. if (rc) {
  2262. pr_err("%s Unable to set high bandwidth\n", __func__);
  2263. goto exit_unregister_bus_scale;
  2264. }
  2265. handle = qce_open(pdev, &rc);
  2266. if (handle == NULL) {
  2267. rc = -ENODEV;
  2268. goto exit_scale_busbandwidth;
  2269. }
  2270. podev->qce = handle;
  2271. rc = qce_set_irqs(podev->qce, false);
  2272. if (rc) {
  2273. pr_err("%s: could not disable bam irqs, ret = %d",
  2274. __func__, rc);
  2275. goto exit_scale_busbandwidth;
  2276. }
  2277. rc = icc_set_bw(podev->icc_path, 0, 0);
  2278. if (rc) {
  2279. pr_err("%s Unable to set to low bandwidth\n", __func__);
  2280. goto exit_qce_close;
  2281. }
  2282. podev->pdev = pdev;
  2283. platform_set_drvdata(pdev, podev);
  2284. qce_hw_support(podev->qce, &podev->ce_support);
  2285. if (podev->ce_support.bam) {
  2286. podev->platform_support.ce_shared = 0;
  2287. podev->platform_support.shared_ce_resource = 0;
  2288. podev->platform_support.hw_key_support =
  2289. podev->ce_support.hw_key;
  2290. podev->platform_support.sha_hmac = 1;
  2291. } else {
  2292. platform_support =
  2293. (struct msm_ce_hw_support *)pdev->dev.platform_data;
  2294. podev->platform_support.ce_shared = platform_support->ce_shared;
  2295. podev->platform_support.shared_ce_resource =
  2296. platform_support->shared_ce_resource;
  2297. podev->platform_support.hw_key_support =
  2298. platform_support->hw_key_support;
  2299. podev->platform_support.sha_hmac = platform_support->sha_hmac;
  2300. }
  2301. podev->mem_client = qcedev_mem_new_client(MEM_ION);
  2302. if (!podev->mem_client) {
  2303. pr_err("%s: err: qcedev_mem_new_client failed\n", __func__);
  2304. goto exit_qce_close;
  2305. }
  2306. rc = of_platform_populate(pdev->dev.of_node, qcedev_match,
  2307. NULL, &pdev->dev);
  2308. if (rc) {
  2309. pr_err("%s: err: of_platform_populate failed: %d\n",
  2310. __func__, rc);
  2311. goto exit_mem_new_client;
  2312. }
  2313. return 0;
  2314. exit_mem_new_client:
  2315. if (podev->mem_client)
  2316. qcedev_mem_delete_client(podev->mem_client);
  2317. podev->mem_client = NULL;
  2318. exit_qce_close:
  2319. if (handle)
  2320. qce_close(handle);
  2321. exit_scale_busbandwidth:
  2322. icc_set_bw(podev->icc_path, 0, 0);
  2323. exit_unregister_bus_scale:
  2324. if (podev->icc_path)
  2325. icc_put(podev->icc_path);
  2326. exit_del_cdev:
  2327. cdev_del(&podev->cdev);
  2328. exit_destroy_device:
  2329. device_destroy(driver_class, qcedev_device_no);
  2330. exit_destroy_class:
  2331. class_destroy(driver_class);
  2332. exit_unreg_chrdev_region:
  2333. unregister_chrdev_region(qcedev_device_no, 1);
  2334. podev->icc_path = NULL;
  2335. platform_set_drvdata(pdev, NULL);
  2336. podev->pdev = NULL;
  2337. podev->qce = NULL;
  2338. return rc;
  2339. }
  2340. static int qcedev_probe(struct platform_device *pdev)
  2341. {
  2342. if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcedev"))
  2343. return qcedev_probe_device(pdev);
  2344. else if (of_device_is_compatible(pdev->dev.of_node,
  2345. "qcom,qcedev,context-bank"))
  2346. return qcedev_parse_context_bank(pdev);
  2347. return -EINVAL;
  2348. };
  2349. static int qcedev_remove(struct platform_device *pdev)
  2350. {
  2351. struct qcedev_control *podev;
  2352. podev = platform_get_drvdata(pdev);
  2353. if (!podev)
  2354. return 0;
  2355. qcedev_ce_high_bw_req(podev, true);
  2356. if (podev->qce)
  2357. qce_close(podev->qce);
  2358. qcedev_ce_high_bw_req(podev, false);
  2359. if (podev->icc_path)
  2360. icc_put(podev->icc_path);
  2361. tasklet_kill(&podev->done_tasklet);
  2362. cdev_del(&podev->cdev);
  2363. device_destroy(driver_class, qcedev_device_no);
  2364. class_destroy(driver_class);
  2365. unregister_chrdev_region(qcedev_device_no, 1);
  2366. return 0;
  2367. };
  2368. static int qcedev_suspend(struct platform_device *pdev, pm_message_t state)
  2369. {
  2370. struct qcedev_control *podev;
  2371. int ret;
  2372. podev = platform_get_drvdata(pdev);
  2373. if (!podev)
  2374. return 0;
  2375. mutex_lock(&qcedev_sent_bw_req);
  2376. if (podev->high_bw_req_count) {
  2377. ret = qce_set_irqs(podev->qce, false);
  2378. if (ret) {
  2379. pr_err("%s: could not disable bam irqs, ret = %d",
  2380. __func__, ret);
  2381. goto suspend_exit;
  2382. }
  2383. ret = qcedev_control_clocks(podev, false);
  2384. if (ret)
  2385. goto suspend_exit;
  2386. }
  2387. suspend_exit:
  2388. mutex_unlock(&qcedev_sent_bw_req);
  2389. return 0;
  2390. }
  2391. static int qcedev_resume(struct platform_device *pdev)
  2392. {
  2393. struct qcedev_control *podev;
  2394. int ret;
  2395. podev = platform_get_drvdata(pdev);
  2396. if (!podev)
  2397. return 0;
  2398. mutex_lock(&qcedev_sent_bw_req);
  2399. if (podev->high_bw_req_count) {
  2400. ret = qcedev_control_clocks(podev, true);
  2401. if (ret)
  2402. goto resume_exit;
  2403. ret = qce_set_irqs(podev->qce, true);
  2404. if (ret) {
  2405. pr_err("%s: could not enable bam irqs, ret = %d",
  2406. __func__, ret);
  2407. qcedev_control_clocks(podev, false);
  2408. }
  2409. }
  2410. resume_exit:
  2411. mutex_unlock(&qcedev_sent_bw_req);
  2412. return 0;
  2413. }
  2414. static struct platform_driver qcedev_plat_driver = {
  2415. .probe = qcedev_probe,
  2416. .remove = qcedev_remove,
  2417. .suspend = qcedev_suspend,
  2418. .resume = qcedev_resume,
  2419. .driver = {
  2420. .name = "qce",
  2421. .of_match_table = qcedev_match,
  2422. },
  2423. };
  2424. static int _disp_stats(int id)
  2425. {
  2426. struct qcedev_stat *pstat;
  2427. int len = 0;
  2428. pstat = &_qcedev_stat;
  2429. len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1,
  2430. "\nQTI QCE dev driver %d Statistics:\n",
  2431. id + 1);
  2432. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2433. " Encryption operation success : %d\n",
  2434. pstat->qcedev_enc_success);
  2435. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2436. " Encryption operation fail : %d\n",
  2437. pstat->qcedev_enc_fail);
  2438. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2439. " Decryption operation success : %d\n",
  2440. pstat->qcedev_dec_success);
  2441. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2442. " Encryption operation fail : %d\n",
  2443. pstat->qcedev_dec_fail);
  2444. return len;
  2445. }
  2446. static ssize_t _debug_stats_read(struct file *file, char __user *buf,
  2447. size_t count, loff_t *ppos)
  2448. {
  2449. ssize_t rc = -EINVAL;
  2450. int qcedev = *((int *) file->private_data);
  2451. int len;
  2452. len = _disp_stats(qcedev);
  2453. if (len <= count)
  2454. rc = simple_read_from_buffer((void __user *) buf, len,
  2455. ppos, (void *) _debug_read_buf, len);
  2456. return rc;
  2457. }
  2458. static ssize_t _debug_stats_write(struct file *file, const char __user *buf,
  2459. size_t count, loff_t *ppos)
  2460. {
  2461. memset((char *)&_qcedev_stat, 0, sizeof(struct qcedev_stat));
  2462. return count;
  2463. };
  2464. static const struct file_operations _debug_stats_ops = {
  2465. .open = simple_open,
  2466. .read = _debug_stats_read,
  2467. .write = _debug_stats_write,
  2468. };
  2469. static int _qcedev_debug_init(void)
  2470. {
  2471. int rc;
  2472. char name[DEBUG_MAX_FNAME];
  2473. struct dentry *dent;
  2474. _debug_dent = debugfs_create_dir("qcedev", NULL);
  2475. if (IS_ERR(_debug_dent)) {
  2476. pr_debug("qcedev debugfs_create_dir fail, error %ld\n",
  2477. PTR_ERR(_debug_dent));
  2478. return PTR_ERR(_debug_dent);
  2479. }
  2480. snprintf(name, DEBUG_MAX_FNAME-1, "stats-%d", 1);
  2481. _debug_qcedev = 0;
  2482. dent = debugfs_create_file(name, 0644, _debug_dent,
  2483. &_debug_qcedev, &_debug_stats_ops);
  2484. if (dent == NULL) {
  2485. pr_debug("qcedev debugfs_create_file fail, error %ld\n",
  2486. PTR_ERR(dent));
  2487. rc = PTR_ERR(dent);
  2488. goto err;
  2489. }
  2490. return 0;
  2491. err:
  2492. debugfs_remove_recursive(_debug_dent);
  2493. return rc;
  2494. }
  2495. static int qcedev_init(void)
  2496. {
  2497. _qcedev_debug_init();
  2498. return platform_driver_register(&qcedev_plat_driver);
  2499. }
  2500. static void qcedev_exit(void)
  2501. {
  2502. debugfs_remove_recursive(_debug_dent);
  2503. platform_driver_unregister(&qcedev_plat_driver);
  2504. }
  2505. MODULE_LICENSE("GPL v2");
  2506. MODULE_DESCRIPTION("QTI DEV Crypto driver");
  2507. MODULE_IMPORT_NS(DMA_BUF);
  2508. module_init(qcedev_init);
  2509. module_exit(qcedev_exit);