cam_soc_util.c 116 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/of.h>
  7. #include <linux/clk.h>
  8. #include <linux/slab.h>
  9. #include <linux/gpio.h>
  10. #include <linux/of_gpio.h>
  11. #include "cam_soc_util.h"
  12. #include "cam_debug_util.h"
  13. #include "cam_cx_ipeak.h"
  14. #include "cam_mem_mgr.h"
  15. #include "cam_presil_hw_access.h"
  16. #include "cam_compat.h"
  17. #if IS_ENABLED(CONFIG_QCOM_CRM)
  18. #include <soc/qcom/crm.h>
  19. #include <linux/clk/qcom.h>
  20. #endif
  21. #define CAM_TO_MASK(bitn) (1 << (int)(bitn))
  22. #define CAM_IS_BIT_SET(mask, bit) ((mask) & CAM_TO_MASK(bit))
  23. #define CAM_SET_BIT(mask, bit) ((mask) |= CAM_TO_MASK(bit))
  24. #define CAM_CLEAR_BIT(mask, bit) ((mask) &= ~CAM_TO_MASK(bit))
  25. #define CAM_SS_START_PRESIL 0x08c00000
  26. #define CAM_SS_START 0x0ac00000
  27. #define CAM_CLK_DIRNAME "clk"
  28. static uint skip_mmrm_set_rate;
  29. module_param(skip_mmrm_set_rate, uint, 0644);
  30. /**
  31. * struct cam_clk_wrapper_clk: This represents an entry corresponding to a
  32. * shared clock in Clk wrapper. Clients that share
  33. * the same clock are registered to this clk entry
  34. * and set rate from them is consolidated before
  35. * setting it to clk driver.
  36. *
  37. * @list: List pointer to point to next shared clk entry
  38. * @clk_id: Clk Id of this clock
  39. * @curr_clk_rate: Current clock rate set for this clock
  40. * @client_list: List of clients registered to this shared clock entry
  41. * @num_clients: Number of registered clients
  42. * @active_clients: Number of active clients
  43. * @mmrm_client: MMRM Client handle for src clock
  44. * @soc_info: soc_info of client with which mmrm handle is created.
  45. * This is used as unique identifier for a client and mmrm
  46. * callback data. When client corresponds to this soc_info is
  47. * unregistered, need to unregister mmrm handle as well.
  48. * @is_nrt_dev: Whether this clock corresponds to NRT device
  49. * @min_clk_rate: Minimum clk rate that this clock supports
  50. **/
  51. struct cam_clk_wrapper_clk {
  52. struct list_head list;
  53. uint32_t clk_id;
  54. int64_t curr_clk_rate;
  55. struct list_head client_list;
  56. uint32_t num_clients;
  57. uint32_t active_clients;
  58. void *mmrm_handle;
  59. struct cam_hw_soc_info *soc_info;
  60. bool is_nrt_dev;
  61. int64_t min_clk_rate;
  62. };
  63. /**
  64. * struct cam_clk_wrapper_client: This represents a client (device) that wants
  65. * to share the clock with some other client.
  66. *
  67. * @list: List pointer to point to next client that share the
  68. * same clock
  69. * @soc_info: soc_info of client. This is used as unique identifier
  70. * for a client
  71. * @clk: Clk handle
  72. * @curr_clk_rate: Current clock rate set for this client
  73. **/
  74. struct cam_clk_wrapper_client {
  75. struct list_head list;
  76. struct cam_hw_soc_info *soc_info;
  77. struct clk *clk;
  78. int64_t curr_clk_rate;
  79. };
  80. static char supported_clk_info[256];
  81. static DEFINE_MUTEX(wrapper_lock);
  82. static LIST_HEAD(wrapper_clk_list);
  83. #define CAM_IS_VALID_CESTA_IDX(idx) ((idx >= 0) && (idx < CAM_CESTA_MAX_CLIENTS))
  84. #define CAM_CRM_DEV_IDENTIFIER "cam_crm"
  85. const struct device *cam_cesta_crm_dev;
  86. #if IS_ENABLED(CONFIG_QCOM_CRM) && IS_ENABLED(CONFIG_SPECTRA_USE_CLK_CRM_API)
  87. static int cam_soc_util_set_hw_client_rate_through_mmrm(
  88. void *mmrm_handle, long low_val, long high_val,
  89. uint32_t num_hw_blocks, int cesta_client_idx);
  90. #endif
  91. #if IS_ENABLED(CONFIG_QCOM_CRM)
  92. static inline const struct device *cam_wrapper_crm_get_device(
  93. const char *name)
  94. {
  95. if (debug_bypass_drivers & CAM_BYPASS_CESTA) {
  96. CAM_WARN(CAM_UTIL, "Bypass crm get device");
  97. return (const struct device *)BYPASS_VALUE;
  98. }
  99. return crm_get_device(name);
  100. }
  101. static inline int cam_wrapper_crm_write_pwr_states(const struct device *dev,
  102. u32 drv_id)
  103. {
  104. if (debug_bypass_drivers & CAM_BYPASS_CESTA) {
  105. CAM_WARN(CAM_UTIL, "Bypass crm write pwr states");
  106. return 0;
  107. }
  108. return crm_write_pwr_states(cam_cesta_crm_dev, drv_id);
  109. }
  110. #endif
  111. #if IS_ENABLED(CONFIG_QCOM_CRM) && IS_ENABLED(CONFIG_SPECTRA_USE_CLK_CRM_API)
  112. static inline int cam_wrapper_qcom_clk_crm_set_rate(struct clk *clk,
  113. enum crm_drv_type client_type, u32 client_idx,
  114. u32 pwr_st, unsigned long rate)
  115. {
  116. if (debug_bypass_drivers & CAM_BYPASS_CESTA) {
  117. CAM_WARN(CAM_UTIL, "Bypass qcom clk crm set rate");
  118. return 0;
  119. }
  120. return qcom_clk_crm_set_rate(clk, client_type, client_idx, pwr_st, rate);
  121. }
  122. #endif
  123. static inline int cam_wrapper_clk_set_rate(struct clk *clk, unsigned long rate)
  124. {
  125. if (debug_bypass_drivers & CAM_BYPASS_CLKS) {
  126. CAM_WARN(CAM_UTIL, "Bypass clk set rate");
  127. return 0;
  128. }
  129. return clk_set_rate(clk, rate);
  130. }
  131. static inline long cam_wrapper_clk_round_rate(struct clk *clk, unsigned long rate)
  132. {
  133. if (debug_bypass_drivers & CAM_BYPASS_CLKS) {
  134. CAM_WARN(CAM_UTIL, "Bypass clk round rate");
  135. return rate;
  136. }
  137. return clk_round_rate(clk, rate);
  138. }
  139. inline unsigned long cam_wrapper_clk_get_rate(struct clk *clk)
  140. {
  141. if (debug_bypass_drivers & CAM_BYPASS_CLKS) {
  142. CAM_WARN(CAM_UTIL, "Bypass clk get rate");
  143. return DEFAULT_CLK_VALUE;
  144. }
  145. return clk_get_rate(clk);
  146. }
  147. static inline struct clk *cam_wrapper_clk_get(struct device *dev, const char *id)
  148. {
  149. if (debug_bypass_drivers & CAM_BYPASS_CLKS) {
  150. CAM_WARN(CAM_UTIL, "Bypass clk get");
  151. return (struct clk *)BYPASS_VALUE;
  152. }
  153. return clk_get(dev, id);
  154. }
  155. static inline void cam_wrapper_clk_put(struct clk *clk)
  156. {
  157. if (debug_bypass_drivers & CAM_BYPASS_CLKS) {
  158. CAM_WARN(CAM_UTIL, "Bypass clk put");
  159. return;
  160. }
  161. clk_put(clk);
  162. }
  163. static inline struct clk *cam_wrapper_of_clk_get_from_provider(
  164. struct of_phandle_args *clkspec)
  165. {
  166. if (debug_bypass_drivers & CAM_BYPASS_CLKS) {
  167. CAM_WARN(CAM_UTIL, "Bypass of clk get from provider");
  168. return (struct clk *)BYPASS_VALUE;
  169. }
  170. return of_clk_get_from_provider(clkspec);
  171. }
  172. static inline int cam_wrapper_clk_prepare_enable(struct clk *clk)
  173. {
  174. if (debug_bypass_drivers & CAM_BYPASS_CLKS) {
  175. CAM_WARN(CAM_UTIL, "Bypass clk prepare enable");
  176. return 0;
  177. }
  178. return clk_prepare_enable(clk);
  179. }
  180. static inline void cam_wrapper_clk_disable_unprepare(struct clk *clk)
  181. {
  182. if (debug_bypass_drivers & CAM_BYPASS_CLKS) {
  183. CAM_WARN(CAM_UTIL, "Bypass clk disable unprepare");
  184. return;
  185. }
  186. clk_disable_unprepare(clk);
  187. }
  188. static inline struct regulator *cam_wrapper_regulator_get(struct device *dev,
  189. const char *id)
  190. {
  191. if (debug_bypass_drivers & CAM_BYPASS_RGLTR) {
  192. CAM_WARN(CAM_UTIL, "Bypass regulator get");
  193. return (struct regulator *)BYPASS_VALUE;
  194. }
  195. return regulator_get(dev, id);
  196. }
  197. static inline void cam_wrapper_regulator_put(struct regulator *regulator)
  198. {
  199. if (debug_bypass_drivers & CAM_BYPASS_RGLTR) {
  200. CAM_WARN(CAM_UTIL, "Bypass regulator put");
  201. return;
  202. }
  203. regulator_put(regulator);
  204. }
  205. static inline int cam_wrapper_regulator_disable(struct regulator *regulator)
  206. {
  207. if (debug_bypass_drivers & CAM_BYPASS_RGLTR) {
  208. CAM_WARN(CAM_UTIL, "Bypass regulator disable");
  209. return 0;
  210. }
  211. return regulator_disable(regulator);
  212. }
  213. static inline int cam_wrapper_regulator_enable(struct regulator *regulator)
  214. {
  215. if (debug_bypass_drivers & CAM_BYPASS_RGLTR) {
  216. CAM_WARN(CAM_UTIL, "Bypass regulator enable");
  217. return 0;
  218. }
  219. return regulator_enable(regulator);
  220. }
  221. static inline int cam_wrapper_regulator_set_voltage(
  222. struct regulator *regulator, int min_uV, int max_uV)
  223. {
  224. if (debug_bypass_drivers & CAM_BYPASS_RGLTR) {
  225. CAM_WARN(CAM_UTIL, "Bypass regulator set voltage");
  226. return 0;
  227. }
  228. return regulator_set_voltage(regulator, min_uV, max_uV);
  229. }
  230. static inline int cam_wrapper_regulator_count_voltages(
  231. struct regulator *regulator)
  232. {
  233. if (debug_bypass_drivers & CAM_BYPASS_RGLTR) {
  234. CAM_WARN(CAM_UTIL, "Bypass regulator count voltages");
  235. return 0;
  236. }
  237. return regulator_count_voltages(regulator);
  238. }
  239. inline int cam_wrapper_regulator_set_load(
  240. struct regulator *regulator, int uA_load)
  241. {
  242. if (debug_bypass_drivers & CAM_BYPASS_RGLTR) {
  243. CAM_WARN(CAM_UTIL, "Bypass regulator set load");
  244. return 0;
  245. }
  246. return regulator_set_load(regulator, uA_load);
  247. }
  248. inline int cam_wrapper_regulator_set_mode(
  249. struct regulator *regulator, unsigned int mode)
  250. {
  251. if (debug_bypass_drivers & CAM_BYPASS_RGLTR_MODE) {
  252. CAM_WARN(CAM_UTIL, "Bypass regulator set mode");
  253. return 0;
  254. }
  255. return regulator_set_mode(regulator, mode);
  256. }
  257. static inline int cam_wrapper_regulator_is_enabled(
  258. struct regulator *regulator)
  259. {
  260. if (debug_bypass_drivers & CAM_BYPASS_RGLTR) {
  261. CAM_WARN(CAM_UTIL, "Bypass regulator is enabled");
  262. return 0;
  263. }
  264. return regulator_is_enabled(regulator);
  265. }
  266. inline void cam_soc_util_set_bypass_drivers(
  267. uint32_t bypass_drivers)
  268. {
  269. debug_bypass_drivers = bypass_drivers;
  270. CAM_INFO(CAM_UTIL, "bypass drivers %d", debug_bypass_drivers);
  271. }
  272. #if IS_ENABLED(CONFIG_QCOM_CRM)
  273. inline int cam_soc_util_cesta_populate_crm_device(void)
  274. {
  275. cam_cesta_crm_dev = cam_wrapper_crm_get_device(CAM_CRM_DEV_IDENTIFIER);
  276. if (!cam_cesta_crm_dev) {
  277. CAM_ERR(CAM_UTIL, "Failed to get cesta crm dev for %s", CAM_CRM_DEV_IDENTIFIER);
  278. return -ENODEV;
  279. }
  280. return 0;
  281. }
  282. int cam_soc_util_cesta_channel_switch(uint32_t cesta_client_idx, const char *identifier)
  283. {
  284. int rc = 0;
  285. if (!cam_cesta_crm_dev) {
  286. CAM_ERR(CAM_UTIL, "camera cesta crm device is null");
  287. return -EINVAL;
  288. }
  289. if (!CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  290. CAM_ERR(CAM_UTIL, "Invalid client index for camera cesta idx: %d max: %d",
  291. cesta_client_idx, CAM_CESTA_MAX_CLIENTS);
  292. return -EINVAL;
  293. }
  294. CAM_DBG(CAM_PERF, "CESTA Channel switch : hw client idx %d identifier=%s",
  295. cesta_client_idx, identifier);
  296. rc = cam_wrapper_crm_write_pwr_states(cam_cesta_crm_dev, cesta_client_idx);
  297. if (rc) {
  298. CAM_ERR(CAM_UTIL,
  299. "Failed to trigger cesta channel switch cesta_client_idx: %u rc: %d",
  300. cesta_client_idx, rc);
  301. return rc;
  302. }
  303. return rc;
  304. }
  305. #else
  306. inline int cam_soc_util_cesta_populate_crm_device(void)
  307. {
  308. CAM_ERR(CAM_UTIL, "Not supported");
  309. return -EOPNOTSUPP;
  310. }
  311. inline int cam_soc_util_cesta_channel_switch(uint32_t cesta_client_idx, const char *identifier)
  312. {
  313. CAM_ERR(CAM_UTIL, "Not supported, cesta_client_idx=%d, identifier=%s",
  314. cesta_client_idx, identifier);
  315. return -EOPNOTSUPP;
  316. }
  317. #endif
  318. #if IS_ENABLED(CONFIG_QCOM_CRM) && IS_ENABLED(CONFIG_SPECTRA_USE_CLK_CRM_API)
  319. static int cam_soc_util_set_cesta_clk_rate(struct cam_hw_soc_info *soc_info,
  320. uint32_t cesta_client_idx, unsigned long high_val, unsigned long low_val,
  321. unsigned long *applied_high_val, unsigned long *applied_low_val)
  322. {
  323. int32_t src_clk_idx;
  324. struct clk *clk = NULL;
  325. int rc = 0;
  326. if (!soc_info || (soc_info->src_clk_idx < 0) ||
  327. (soc_info->src_clk_idx >= CAM_SOC_MAX_CLK)) {
  328. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d",
  329. soc_info ? soc_info->src_clk_idx : -1);
  330. return -EINVAL;
  331. }
  332. if (!CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  333. CAM_ERR(CAM_UTIL, "Invalid client index for camera cesta idx: %d max: %d",
  334. cesta_client_idx, CAM_CESTA_MAX_CLIENTS);
  335. return -EINVAL;
  336. }
  337. /* Only source clocks are supported by this API to set HW client clock votes */
  338. src_clk_idx = soc_info->src_clk_idx;
  339. clk = soc_info->clk[src_clk_idx];
  340. if (!skip_mmrm_set_rate && soc_info->mmrm_handle) {
  341. CAM_DBG(CAM_UTIL, "cesta mmrm hw client: set %s, high-rate %lld low-rate %lld",
  342. soc_info->clk_name[src_clk_idx], high_val, low_val);
  343. rc = cam_soc_util_set_hw_client_rate_through_mmrm(
  344. soc_info->mmrm_handle, low_val, high_val, 1,
  345. cesta_client_idx);
  346. if (rc) {
  347. CAM_ERR(CAM_UTIL,
  348. "set_sw_client_rate through mmrm failed on %s clk_id %d low_val %llu high_val %llu client idx=%d",
  349. soc_info->clk_name[src_clk_idx], soc_info->clk_id[src_clk_idx],
  350. low_val, high_val, cesta_client_idx);
  351. return rc;
  352. }
  353. goto end;
  354. }
  355. CAM_DBG(CAM_UTIL, "%s Requested clk rate [high low]: [%llu %llu] cesta_client_idx: %d",
  356. soc_info->clk_name[src_clk_idx], high_val, low_val, cesta_client_idx);
  357. rc = cam_wrapper_qcom_clk_crm_set_rate(
  358. clk, CRM_HW_DRV, cesta_client_idx, CRM_PWR_STATE1, high_val);
  359. if (rc) {
  360. CAM_ERR(CAM_UTIL,
  361. "Failed in setting cesta high clk rate, client idx: %u pwr state: %u clk_val: %llu rc: %d",
  362. cesta_client_idx, CRM_PWR_STATE1, high_val, rc);
  363. return rc;
  364. }
  365. rc = cam_wrapper_qcom_clk_crm_set_rate(
  366. clk, CRM_HW_DRV, cesta_client_idx, CRM_PWR_STATE0, low_val);
  367. if (rc) {
  368. CAM_ERR(CAM_UTIL,
  369. "Failed in setting cesta low clk rate, client idx: %u pwr state: %u clk_val: %llu rc: %d",
  370. cesta_client_idx, CRM_PWR_STATE0, low_val, rc);
  371. return rc;
  372. }
  373. end:
  374. if (applied_high_val)
  375. *applied_high_val = high_val;
  376. if (applied_low_val)
  377. *applied_low_val = low_val;
  378. return rc;
  379. }
  380. #if IS_REACHABLE(CONFIG_MSM_MMRM)
  381. int cam_soc_util_set_hw_client_rate_through_mmrm(
  382. void *mmrm_handle, long low_val, long high_val,
  383. uint32_t num_hw_blocks, int cesta_client_idx)
  384. {
  385. int rc = 0;
  386. struct mmrm_client_data client_data;
  387. client_data.num_hw_blocks = num_hw_blocks;
  388. client_data.crm_drv_idx = cesta_client_idx;
  389. client_data.drv_type = MMRM_CRM_HW_DRV;
  390. client_data.pwr_st = CRM_PWR_STATE1;
  391. client_data.flags = 0;
  392. CAM_DBG(CAM_UTIL,
  393. "hw client mmrm=%pK, high_val %ld, low_val %ld, num_blocks=%d, pwr_state: %u, client_idx: %d",
  394. mmrm_handle, high_val, low_val, num_hw_blocks, CRM_PWR_STATE1, cesta_client_idx);
  395. rc = mmrm_client_set_value((struct mmrm_client *)mmrm_handle,
  396. &client_data, high_val);
  397. if (rc) {
  398. CAM_ERR(CAM_UTIL, "Set high rate failed rate %ld rc %d",
  399. high_val, rc);
  400. return rc;
  401. }
  402. /* We vote a second time for pwr_st = low */
  403. client_data.pwr_st = CRM_PWR_STATE0;
  404. rc = mmrm_client_set_value((struct mmrm_client *)mmrm_handle,
  405. &client_data, low_val);
  406. if (rc)
  407. CAM_ERR(CAM_UTIL, "Set low rate failed rate %ld rc %d", low_val, rc);
  408. return rc;
  409. }
  410. #else
  411. int cam_soc_util_set_hw_client_rate_through_mmrm(
  412. void *mmrm_handle, long low_val, long high_val,
  413. uint32_t num_hw_blocks, int cesta_client_idx)
  414. {
  415. return 0;
  416. }
  417. #endif
  418. #else
  419. static inline int cam_soc_util_set_cesta_clk_rate(struct cam_hw_soc_info *soc_info,
  420. uint32_t cesta_client_idx, unsigned long high_val, unsigned long low_val,
  421. unsigned long *applied_high_val, unsigned long *applied_low_val)
  422. {
  423. CAM_ERR(CAM_UTIL, "Not supported, dev=%s, cesta_client_idx=%d, high_val=%ld, low_val=%ld",
  424. soc_info->dev_name, cesta_client_idx, high_val, low_val);
  425. return -EOPNOTSUPP;
  426. }
  427. #endif
  428. #if IS_REACHABLE(CONFIG_MSM_MMRM)
  429. bool cam_is_mmrm_supported_on_current_chip(void)
  430. {
  431. bool is_supported;
  432. is_supported = mmrm_client_check_scaling_supported(MMRM_CLIENT_CLOCK,
  433. MMRM_CLIENT_DOMAIN_CAMERA);
  434. CAM_DBG(CAM_UTIL, "is mmrm supported: %s",
  435. CAM_BOOL_TO_YESNO(is_supported));;
  436. return is_supported;
  437. }
  438. int cam_mmrm_notifier_callback(
  439. struct mmrm_client_notifier_data *notifier_data)
  440. {
  441. if (!notifier_data) {
  442. CAM_ERR(CAM_UTIL, "Invalid notifier data");
  443. return -EBADR;
  444. }
  445. if (notifier_data->cb_type == MMRM_CLIENT_RESOURCE_VALUE_CHANGE) {
  446. struct cam_hw_soc_info *soc_info = notifier_data->pvt_data;
  447. CAM_WARN(CAM_UTIL, "Dev %s Clk %s value change from %ld to %ld",
  448. soc_info->dev_name,
  449. (soc_info->src_clk_idx == -1) ? "No src clk" :
  450. soc_info->clk_name[soc_info->src_clk_idx],
  451. notifier_data->cb_data.val_chng.old_val,
  452. notifier_data->cb_data.val_chng.new_val);
  453. }
  454. return 0;
  455. }
  456. int cam_soc_util_register_mmrm_client(
  457. uint32_t clk_id, struct clk *clk, bool is_nrt_dev,
  458. struct cam_hw_soc_info *soc_info, const char *clk_name,
  459. void **mmrm_handle)
  460. {
  461. struct mmrm_client *mmrm_client;
  462. struct mmrm_client_desc desc = { };
  463. if (!mmrm_handle) {
  464. CAM_ERR(CAM_UTIL, "Invalid mmrm input");
  465. return -EINVAL;
  466. }
  467. *mmrm_handle = (void *)NULL;
  468. if (debug_bypass_drivers & CAM_BYPASS_CLKS) {
  469. CAM_WARN(CAM_UTIL, "Bypass register mmrm client");
  470. return 0;
  471. }
  472. if (!cam_is_mmrm_supported_on_current_chip())
  473. return 0;
  474. desc.client_type = MMRM_CLIENT_CLOCK;
  475. desc.client_info.desc.client_domain = MMRM_CLIENT_DOMAIN_CAMERA;
  476. desc.client_info.desc.client_id = clk_id;
  477. desc.client_info.desc.clk = clk;
  478. #if IS_ENABLED(CONFIG_QCOM_CRM) && IS_ENABLED(CONFIG_SPECTRA_USE_CLK_CRM_API)
  479. if (soc_info->is_clk_drv_en) {
  480. desc.client_info.desc.hw_drv_instances = CAM_CESTA_MAX_CLIENTS;
  481. desc.client_info.desc.num_pwr_states = CAM_NUM_PWR_STATES;
  482. } else {
  483. desc.client_info.desc.hw_drv_instances = 0;
  484. desc.client_info.desc.num_pwr_states = 0;
  485. }
  486. #endif
  487. snprintf((char *)desc.client_info.desc.name,
  488. sizeof(desc.client_info.desc.name), "%s_%s",
  489. soc_info->dev_name, clk_name);
  490. desc.priority = is_nrt_dev ?
  491. MMRM_CLIENT_PRIOR_LOW : MMRM_CLIENT_PRIOR_HIGH;
  492. desc.pvt_data = soc_info;
  493. desc.notifier_callback_fn = cam_mmrm_notifier_callback;
  494. mmrm_client = mmrm_client_register(&desc);
  495. if (!mmrm_client) {
  496. CAM_ERR(CAM_UTIL, "MMRM Register failed Dev %s clk %s id %d",
  497. soc_info->dev_name, clk_name, clk_id);
  498. return -EINVAL;
  499. }
  500. CAM_DBG(CAM_UTIL,
  501. "MMRM Register success Dev %s is_nrt_dev %d clk %s id %d handle=%pK",
  502. soc_info->dev_name, is_nrt_dev, clk_name, clk_id, mmrm_client);
  503. *mmrm_handle = (void *)mmrm_client;
  504. return 0;
  505. }
  506. int cam_soc_util_unregister_mmrm_client(
  507. void *mmrm_handle)
  508. {
  509. int rc = 0;
  510. CAM_DBG(CAM_UTIL, "MMRM UnRegister handle=%pK", mmrm_handle);
  511. if (mmrm_handle) {
  512. rc = mmrm_client_deregister((struct mmrm_client *)mmrm_handle);
  513. if (rc)
  514. CAM_ERR(CAM_UTIL,
  515. "Failed in deregister handle=%pK, rc %d",
  516. mmrm_handle, rc);
  517. }
  518. return rc;
  519. }
  520. static int cam_soc_util_set_sw_client_rate_through_mmrm(
  521. void *mmrm_handle, bool is_nrt_dev, long min_rate,
  522. long req_rate, uint32_t num_hw_blocks)
  523. {
  524. int rc = 0;
  525. struct mmrm_client_data client_data;
  526. struct mmrm_client_res_value val;
  527. client_data.num_hw_blocks = num_hw_blocks;
  528. client_data.flags = 0;
  529. #if IS_ENABLED(CONFIG_QCOM_CRM) && IS_ENABLED(CONFIG_SPECTRA_USE_CLK_CRM_API)
  530. client_data.drv_type = MMRM_CRM_SW_DRV;
  531. #endif
  532. CAM_DBG(CAM_UTIL,
  533. "sw client mmrm=%pK, nrt=%d, min_rate=%ld req_rate %ld, num_blocks=%d",
  534. mmrm_handle, is_nrt_dev, min_rate, req_rate, num_hw_blocks);
  535. if (is_nrt_dev) {
  536. val.min = min_rate;
  537. val.cur = req_rate;
  538. rc = mmrm_client_set_value_in_range(
  539. (struct mmrm_client *)mmrm_handle, &client_data, &val);
  540. } else {
  541. rc = mmrm_client_set_value(
  542. (struct mmrm_client *)mmrm_handle,
  543. &client_data, req_rate);
  544. }
  545. if (rc)
  546. CAM_ERR(CAM_UTIL, "Set rate failed rate %ld rc %d",
  547. req_rate, rc);
  548. return rc;
  549. }
  550. #else
  551. int cam_soc_util_register_mmrm_client(
  552. uint32_t clk_id, struct clk *clk, bool is_nrt_dev,
  553. struct cam_hw_soc_info *soc_info, const char *clk_name,
  554. void **mmrm_handle)
  555. {
  556. if (!mmrm_handle) {
  557. CAM_ERR(CAM_UTIL, "Invalid mmrm input");
  558. return -EINVAL;
  559. }
  560. *mmrm_handle = NULL;
  561. return 0;
  562. }
  563. int cam_soc_util_unregister_mmrm_client(
  564. void *mmrm_handle)
  565. {
  566. return 0;
  567. }
  568. static int cam_soc_util_set_sw_client_rate_through_mmrm(
  569. void *mmrm_handle, bool is_nrt_dev, long min_rate,
  570. long req_rate, uint32_t num_hw_blocks)
  571. {
  572. return 0;
  573. }
  574. #endif
  575. static int cam_soc_util_clk_wrapper_register_entry(
  576. uint32_t clk_id, struct clk *clk, bool is_src_clk,
  577. struct cam_hw_soc_info *soc_info, int64_t min_clk_rate,
  578. const char *clk_name)
  579. {
  580. struct cam_clk_wrapper_clk *wrapper_clk;
  581. struct cam_clk_wrapper_client *wrapper_client;
  582. bool clock_found = false;
  583. int rc = 0;
  584. mutex_lock(&wrapper_lock);
  585. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  586. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  587. wrapper_clk->clk_id, wrapper_clk->num_clients);
  588. if (wrapper_clk->clk_id == clk_id) {
  589. clock_found = true;
  590. list_for_each_entry(wrapper_client,
  591. &wrapper_clk->client_list, list) {
  592. CAM_DBG(CAM_UTIL,
  593. "Clk id %d entry client %s",
  594. wrapper_clk->clk_id,
  595. wrapper_client->soc_info->dev_name);
  596. if (wrapper_client->soc_info == soc_info) {
  597. CAM_ERR(CAM_UTIL,
  598. "Register with same soc info, clk id %d, client %s",
  599. clk_id, soc_info->dev_name);
  600. rc = -EINVAL;
  601. goto end;
  602. }
  603. }
  604. break;
  605. }
  606. }
  607. if (!clock_found) {
  608. CAM_DBG(CAM_UTIL, "Adding new entry for clk id %d", clk_id);
  609. wrapper_clk = kzalloc(sizeof(struct cam_clk_wrapper_clk),
  610. GFP_KERNEL);
  611. if (!wrapper_clk) {
  612. CAM_ERR(CAM_UTIL,
  613. "Failed in allocating new clk entry %d",
  614. clk_id);
  615. rc = -ENOMEM;
  616. goto end;
  617. }
  618. wrapper_clk->clk_id = clk_id;
  619. INIT_LIST_HEAD(&wrapper_clk->list);
  620. INIT_LIST_HEAD(&wrapper_clk->client_list);
  621. list_add_tail(&wrapper_clk->list, &wrapper_clk_list);
  622. }
  623. wrapper_client = kzalloc(sizeof(struct cam_clk_wrapper_client),
  624. GFP_KERNEL);
  625. if (!wrapper_client) {
  626. CAM_ERR(CAM_UTIL, "Failed in allocating new client entry %d",
  627. clk_id);
  628. rc = -ENOMEM;
  629. goto end;
  630. }
  631. wrapper_client->soc_info = soc_info;
  632. wrapper_client->clk = clk;
  633. if (is_src_clk && !wrapper_clk->mmrm_handle) {
  634. wrapper_clk->is_nrt_dev = soc_info->is_nrt_dev;
  635. wrapper_clk->min_clk_rate = min_clk_rate;
  636. wrapper_clk->soc_info = soc_info;
  637. rc = cam_soc_util_register_mmrm_client(clk_id, clk,
  638. wrapper_clk->is_nrt_dev, soc_info, clk_name,
  639. &wrapper_clk->mmrm_handle);
  640. if (rc) {
  641. CAM_ERR(CAM_UTIL,
  642. "Failed in register mmrm client Dev %s clk id %d",
  643. soc_info->dev_name, clk_id);
  644. kfree(wrapper_client);
  645. goto end;
  646. }
  647. }
  648. INIT_LIST_HEAD(&wrapper_client->list);
  649. list_add_tail(&wrapper_client->list, &wrapper_clk->client_list);
  650. wrapper_clk->num_clients++;
  651. CAM_DBG(CAM_UTIL,
  652. "Adding new client %s for clk[%s] id %d, num clients %d",
  653. soc_info->dev_name, clk_name, clk_id, wrapper_clk->num_clients);
  654. end:
  655. mutex_unlock(&wrapper_lock);
  656. return rc;
  657. }
  658. static int cam_soc_util_clk_wrapper_unregister_entry(
  659. uint32_t clk_id, struct cam_hw_soc_info *soc_info)
  660. {
  661. struct cam_clk_wrapper_clk *wrapper_clk;
  662. struct cam_clk_wrapper_client *wrapper_client;
  663. bool clock_found = false;
  664. bool client_found = false;
  665. int rc = 0;
  666. mutex_lock(&wrapper_lock);
  667. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  668. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  669. wrapper_clk->clk_id, wrapper_clk->num_clients);
  670. if (wrapper_clk->clk_id == clk_id) {
  671. clock_found = true;
  672. list_for_each_entry(wrapper_client,
  673. &wrapper_clk->client_list, list) {
  674. CAM_DBG(CAM_UTIL, "Clk id %d entry client %s",
  675. wrapper_clk->clk_id,
  676. wrapper_client->soc_info->dev_name);
  677. if (wrapper_client->soc_info == soc_info) {
  678. client_found = true;
  679. break;
  680. }
  681. }
  682. break;
  683. }
  684. }
  685. if (!clock_found) {
  686. CAM_ERR(CAM_UTIL, "Shared clk id %d entry not found", clk_id);
  687. rc = -EINVAL;
  688. goto end;
  689. }
  690. if (!client_found) {
  691. CAM_ERR(CAM_UTIL,
  692. "Client %pK for Shared clk id %d entry not found",
  693. soc_info, clk_id);
  694. rc = -EINVAL;
  695. goto end;
  696. }
  697. wrapper_clk->num_clients--;
  698. if (wrapper_clk->mmrm_handle && (wrapper_clk->soc_info == soc_info)) {
  699. cam_soc_util_unregister_mmrm_client(wrapper_clk->mmrm_handle);
  700. wrapper_clk->mmrm_handle = NULL;
  701. wrapper_clk->soc_info = NULL;
  702. }
  703. list_del_init(&wrapper_client->list);
  704. kfree(wrapper_client);
  705. CAM_DBG(CAM_UTIL, "Unregister client %s for clk id %d, num clients %d",
  706. soc_info->dev_name, clk_id, wrapper_clk->num_clients);
  707. if (!wrapper_clk->num_clients) {
  708. list_del_init(&wrapper_clk->list);
  709. kfree(wrapper_clk);
  710. }
  711. end:
  712. mutex_unlock(&wrapper_lock);
  713. return rc;
  714. }
  715. static int cam_soc_util_clk_wrapper_set_clk_rate(
  716. uint32_t clk_id, struct cam_hw_soc_info *soc_info,
  717. struct clk *clk, int64_t clk_rate)
  718. {
  719. struct cam_clk_wrapper_clk *wrapper_clk;
  720. struct cam_clk_wrapper_client *wrapper_client;
  721. bool clk_found = false;
  722. bool client_found = false;
  723. int rc = 0;
  724. int64_t final_clk_rate = 0;
  725. uint32_t active_clients = 0;
  726. if (!soc_info || !clk) {
  727. CAM_ERR(CAM_UTIL, "Invalid param soc_info %pK clk %pK",
  728. soc_info, clk);
  729. return -EINVAL;
  730. }
  731. mutex_lock(&wrapper_lock);
  732. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  733. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  734. wrapper_clk->clk_id, wrapper_clk->num_clients);
  735. if (wrapper_clk->clk_id == clk_id) {
  736. clk_found = true;
  737. break;
  738. }
  739. }
  740. if (!clk_found) {
  741. CAM_ERR(CAM_UTIL, "Clk entry not found id %d client %s",
  742. clk_id, soc_info->dev_name);
  743. rc = -EINVAL;
  744. goto end;
  745. }
  746. list_for_each_entry(wrapper_client, &wrapper_clk->client_list, list) {
  747. CAM_DBG(CAM_UTIL, "Clk id %d client %s, clk rate %lld",
  748. wrapper_clk->clk_id, wrapper_client->soc_info->dev_name,
  749. wrapper_client->curr_clk_rate);
  750. if (wrapper_client->soc_info == soc_info) {
  751. client_found = true;
  752. CAM_DBG(CAM_UTIL,
  753. "Clk enable clk id %d, client %s curr %ld new %ld",
  754. clk_id, wrapper_client->soc_info->dev_name,
  755. wrapper_client->curr_clk_rate, clk_rate);
  756. wrapper_client->curr_clk_rate = clk_rate;
  757. }
  758. if (wrapper_client->curr_clk_rate > 0)
  759. active_clients++;
  760. if (final_clk_rate < wrapper_client->curr_clk_rate)
  761. final_clk_rate = wrapper_client->curr_clk_rate;
  762. }
  763. if (!client_found) {
  764. CAM_ERR(CAM_UTIL,
  765. "Wrapper clk enable without client entry clk id %d client %s",
  766. clk_id, soc_info->dev_name);
  767. rc = -EINVAL;
  768. goto end;
  769. }
  770. CAM_DBG(CAM_UTIL,
  771. "Clk id %d, client %s, clients rate %ld, curr %ld final %ld",
  772. wrapper_clk->clk_id, soc_info->dev_name, clk_rate,
  773. wrapper_clk->curr_clk_rate, final_clk_rate);
  774. if ((final_clk_rate != wrapper_clk->curr_clk_rate) ||
  775. (active_clients != wrapper_clk->active_clients)) {
  776. bool set_rate_finish = false;
  777. if (!skip_mmrm_set_rate && wrapper_clk->mmrm_handle) {
  778. rc = cam_soc_util_set_sw_client_rate_through_mmrm(
  779. wrapper_clk->mmrm_handle,
  780. wrapper_clk->is_nrt_dev,
  781. wrapper_clk->min_clk_rate,
  782. final_clk_rate, active_clients);
  783. if (rc) {
  784. CAM_ERR(CAM_UTIL,
  785. "set_rate through mmrm failed clk_id %d, rate=%ld",
  786. wrapper_clk->clk_id, final_clk_rate);
  787. goto end;
  788. }
  789. set_rate_finish = true;
  790. }
  791. if (!set_rate_finish && final_clk_rate &&
  792. (final_clk_rate != wrapper_clk->curr_clk_rate)) {
  793. rc = cam_wrapper_clk_set_rate(clk, final_clk_rate);
  794. if (rc) {
  795. CAM_ERR(CAM_UTIL, "set_rate failed on clk %d",
  796. wrapper_clk->clk_id);
  797. goto end;
  798. }
  799. }
  800. wrapper_clk->curr_clk_rate = final_clk_rate;
  801. wrapper_clk->active_clients = active_clients;
  802. }
  803. end:
  804. mutex_unlock(&wrapper_lock);
  805. return rc;
  806. }
  807. int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info,
  808. int64_t clk_rate, int clk_idx, int32_t *clk_lvl)
  809. {
  810. int i;
  811. long clk_rate_round;
  812. if (!soc_info || (clk_idx < 0) || (clk_idx >= CAM_SOC_MAX_CLK)) {
  813. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d", clk_idx);
  814. *clk_lvl = -1;
  815. return -EINVAL;
  816. }
  817. clk_rate_round = cam_wrapper_clk_round_rate(
  818. soc_info->clk[clk_idx], clk_rate);
  819. if (clk_rate_round < 0) {
  820. CAM_ERR(CAM_UTIL, "round failed rc = %ld",
  821. clk_rate_round);
  822. *clk_lvl = -1;
  823. return -EINVAL;
  824. }
  825. if (debug_bypass_drivers & CAM_BYPASS_CLKS) {
  826. CAM_WARN(CAM_UTIL, "Bypass get clk level");
  827. *clk_lvl = CAM_NOMINAL_VOTE;
  828. return 0;
  829. }
  830. for (i = 0; i < CAM_MAX_VOTE; i++) {
  831. if ((soc_info->clk_level_valid[i]) &&
  832. (soc_info->clk_rate[i][clk_idx] >=
  833. clk_rate_round)) {
  834. CAM_DBG(CAM_UTIL,
  835. "soc = %d round rate = %ld actual = %lld",
  836. soc_info->clk_rate[i][clk_idx],
  837. clk_rate_round, clk_rate);
  838. *clk_lvl = i;
  839. return 0;
  840. }
  841. }
  842. CAM_WARN(CAM_UTIL, "Invalid clock rate %ld", clk_rate_round);
  843. *clk_lvl = -1;
  844. return -EINVAL;
  845. }
  846. const char *cam_soc_util_get_string_from_level(enum cam_vote_level level)
  847. {
  848. switch (level) {
  849. case CAM_SUSPEND_VOTE:
  850. return "";
  851. case CAM_MINSVS_VOTE:
  852. return "MINSVS[1]";
  853. case CAM_LOWSVS_VOTE:
  854. return "LOWSVS[2]";
  855. case CAM_SVS_VOTE:
  856. return "SVS[3]";
  857. case CAM_SVSL1_VOTE:
  858. return "SVSL1[4]";
  859. case CAM_NOMINAL_VOTE:
  860. return "NOM[5]";
  861. case CAM_NOMINALL1_VOTE:
  862. return "NOML1[6]";
  863. case CAM_TURBO_VOTE:
  864. return "TURBO[7]";
  865. default:
  866. return "";
  867. }
  868. }
  869. /**
  870. * cam_soc_util_get_supported_clk_levels()
  871. *
  872. * @brief: Returns the string of all the supported clk levels for
  873. * the given device
  874. *
  875. * @soc_info: Device soc information
  876. *
  877. * @return: String containing all supported clk levels
  878. */
  879. static const char *cam_soc_util_get_supported_clk_levels(
  880. struct cam_hw_soc_info *soc_info)
  881. {
  882. int i = 0;
  883. scnprintf(supported_clk_info, sizeof(supported_clk_info), "Supported levels: ");
  884. for (i = 0; i < CAM_MAX_VOTE; i++) {
  885. if (soc_info->clk_level_valid[i] == true) {
  886. strlcat(supported_clk_info,
  887. cam_soc_util_get_string_from_level(i),
  888. sizeof(supported_clk_info));
  889. strlcat(supported_clk_info, " ",
  890. sizeof(supported_clk_info));
  891. }
  892. }
  893. strlcat(supported_clk_info, "\n", sizeof(supported_clk_info));
  894. return supported_clk_info;
  895. }
  896. static int cam_soc_util_clk_lvl_options_open(struct inode *inode,
  897. struct file *file)
  898. {
  899. file->private_data = inode->i_private;
  900. return 0;
  901. }
  902. static ssize_t cam_soc_util_clk_lvl_options_read(struct file *file,
  903. char __user *clk_info, size_t size_t, loff_t *loff_t)
  904. {
  905. struct cam_hw_soc_info *soc_info =
  906. (struct cam_hw_soc_info *)file->private_data;
  907. const char *display_string =
  908. cam_soc_util_get_supported_clk_levels(soc_info);
  909. return simple_read_from_buffer(clk_info, size_t, loff_t, display_string,
  910. strlen(display_string));
  911. }
  912. static const struct file_operations cam_soc_util_clk_lvl_options = {
  913. .open = cam_soc_util_clk_lvl_options_open,
  914. .read = cam_soc_util_clk_lvl_options_read,
  915. };
  916. static int cam_soc_util_set_clk_lvl_override(void *data, u64 val)
  917. {
  918. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  919. if ((val <= CAM_SUSPEND_VOTE) || (val >= CAM_MAX_VOTE)) {
  920. CAM_WARN(CAM_UTIL, "Invalid clk lvl override %d", val);
  921. return 0;
  922. }
  923. if (soc_info->clk_level_valid[val])
  924. soc_info->clk_level_override_high = val;
  925. else
  926. soc_info->clk_level_override_high = 0;
  927. return 0;
  928. }
  929. static int cam_soc_util_get_clk_lvl_override(void *data, u64 *val)
  930. {
  931. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  932. *val = soc_info->clk_level_override_high;
  933. return 0;
  934. }
  935. static int cam_soc_util_set_clk_lvl_override_low(void *data, u64 val)
  936. {
  937. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  938. if ((val <= CAM_SUSPEND_VOTE) || (val >= CAM_MAX_VOTE)) {
  939. CAM_WARN(CAM_UTIL, "Invalid clk lvl override %d", val);
  940. return 0;
  941. }
  942. if (soc_info->clk_level_valid[val])
  943. soc_info->clk_level_override_low = val;
  944. else
  945. soc_info->clk_level_override_low = 0;
  946. return 0;
  947. }
  948. static int cam_soc_util_get_clk_lvl_override_low(void *data, u64 *val)
  949. {
  950. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  951. *val = soc_info->clk_level_override_low;
  952. return 0;
  953. }
  954. DEFINE_SIMPLE_ATTRIBUTE(cam_soc_util_clk_lvl_control,
  955. cam_soc_util_get_clk_lvl_override, cam_soc_util_set_clk_lvl_override, "%08llu");
  956. DEFINE_SIMPLE_ATTRIBUTE(cam_soc_util_clk_lvl_control_low,
  957. cam_soc_util_get_clk_lvl_override_low, cam_soc_util_set_clk_lvl_override_low, "%08llu");
  958. /**
  959. * cam_soc_util_create_clk_lvl_debugfs()
  960. *
  961. * @brief: Creates debugfs files to view/control device clk rates
  962. *
  963. * @soc_info: Device soc information
  964. *
  965. * @return: Success or failure
  966. */
  967. static int cam_soc_util_create_clk_lvl_debugfs(struct cam_hw_soc_info *soc_info)
  968. {
  969. int rc = 0;
  970. struct dentry *clkdirptr = NULL;
  971. if (!cam_debugfs_available())
  972. return 0;
  973. if (soc_info->dentry) {
  974. CAM_DBG(CAM_UTIL, "Debugfs entry for %s already exists",
  975. soc_info->dev_name);
  976. goto end;
  977. }
  978. rc = cam_debugfs_lookup_subdir(CAM_CLK_DIRNAME, &clkdirptr);
  979. if (rc) {
  980. rc = cam_debugfs_create_subdir(CAM_CLK_DIRNAME, &clkdirptr);
  981. if (rc) {
  982. CAM_ERR(CAM_UTIL, "DebugFS could not create clk directory!");
  983. rc = -ENOENT;
  984. goto end;
  985. }
  986. }
  987. soc_info->dentry = debugfs_create_dir(soc_info->dev_name, clkdirptr);
  988. if (IS_ERR_OR_NULL(soc_info->dentry)) {
  989. CAM_ERR(CAM_UTIL, "DebugFS could not create directory for dev:%s!",
  990. soc_info->dev_name);
  991. rc = -ENOENT;
  992. goto end;
  993. }
  994. /* Store parent inode for cleanup in caller */
  995. debugfs_create_file("clk_lvl_options", 0444,
  996. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_options);
  997. debugfs_create_file("clk_lvl_control", 0644,
  998. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_control);
  999. debugfs_create_file("clk_lvl_control_low", 0644,
  1000. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_control_low);
  1001. end:
  1002. return rc;
  1003. }
  1004. int cam_soc_util_get_level_from_string(const char *string,
  1005. enum cam_vote_level *level)
  1006. {
  1007. if (!level)
  1008. return -EINVAL;
  1009. if (!strcmp(string, "suspend")) {
  1010. *level = CAM_SUSPEND_VOTE;
  1011. } else if (!strcmp(string, "minsvs")) {
  1012. *level = CAM_MINSVS_VOTE;
  1013. } else if (!strcmp(string, "lowsvs")) {
  1014. *level = CAM_LOWSVS_VOTE;
  1015. } else if (!strcmp(string, "svs")) {
  1016. *level = CAM_SVS_VOTE;
  1017. } else if (!strcmp(string, "svs_l1")) {
  1018. *level = CAM_SVSL1_VOTE;
  1019. } else if (!strcmp(string, "nominal")) {
  1020. *level = CAM_NOMINAL_VOTE;
  1021. } else if (!strcmp(string, "nominal_l1")) {
  1022. *level = CAM_NOMINALL1_VOTE;
  1023. } else if (!strcmp(string, "turbo")) {
  1024. *level = CAM_TURBO_VOTE;
  1025. } else {
  1026. CAM_ERR(CAM_UTIL, "Invalid string %s", string);
  1027. return -EINVAL;
  1028. }
  1029. return 0;
  1030. }
  1031. /**
  1032. * cam_soc_util_get_clk_level_to_apply()
  1033. *
  1034. * @brief: Get the clock level to apply. If the requested level
  1035. * is not valid, bump the level to next available valid
  1036. * level. If no higher level found, return failure.
  1037. *
  1038. * @soc_info: Device soc struct to be populated
  1039. * @req_level: Requested level
  1040. * @apply_level Level to apply
  1041. *
  1042. * @return: success or failure
  1043. */
  1044. static int cam_soc_util_get_clk_level_to_apply(
  1045. struct cam_hw_soc_info *soc_info, enum cam_vote_level req_level,
  1046. enum cam_vote_level *apply_level)
  1047. {
  1048. if (req_level >= CAM_MAX_VOTE) {
  1049. CAM_ERR(CAM_UTIL, "Invalid clock level parameter %d",
  1050. req_level);
  1051. return -EINVAL;
  1052. }
  1053. if (soc_info->clk_level_valid[req_level] == true) {
  1054. *apply_level = req_level;
  1055. } else {
  1056. int i;
  1057. for (i = (req_level + 1); i < CAM_MAX_VOTE; i++)
  1058. if (soc_info->clk_level_valid[i] == true) {
  1059. *apply_level = i;
  1060. break;
  1061. }
  1062. if (i == CAM_MAX_VOTE) {
  1063. CAM_ERR(CAM_UTIL,
  1064. "No valid clock level found to apply, req=%d",
  1065. req_level);
  1066. return -EINVAL;
  1067. }
  1068. }
  1069. CAM_DBG(CAM_UTIL, "Req level %s, Applying %s",
  1070. cam_soc_util_get_string_from_level(req_level),
  1071. cam_soc_util_get_string_from_level(*apply_level));
  1072. return 0;
  1073. }
  1074. int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info)
  1075. {
  1076. int i, rc = 0;
  1077. if (!soc_info) {
  1078. CAM_ERR(CAM_UTIL, "Invalid arguments");
  1079. return -EINVAL;
  1080. }
  1081. for (i = 0; i < soc_info->irq_count; i++) {
  1082. if (soc_info->irq_num[i] < 0) {
  1083. CAM_ERR(CAM_UTIL, "No IRQ line available for irq: %s dev: %s",
  1084. soc_info->irq_name[i], soc_info->dev_name);
  1085. rc = -ENODEV;
  1086. goto disable_irq;
  1087. }
  1088. enable_irq(soc_info->irq_num[i]);
  1089. }
  1090. return rc;
  1091. disable_irq:
  1092. for (i = i - 1; i >= 0; i--)
  1093. disable_irq(soc_info->irq_num[i]);
  1094. return rc;
  1095. }
  1096. int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info)
  1097. {
  1098. int i, rc = 0;
  1099. if (!soc_info) {
  1100. CAM_ERR(CAM_UTIL, "Invalid arguments");
  1101. return -EINVAL;
  1102. }
  1103. for (i = 0; i < soc_info->irq_count; i++) {
  1104. if (soc_info->irq_num[i] < 0) {
  1105. CAM_ERR(CAM_UTIL, "No IRQ line available irq: %s dev:",
  1106. soc_info->irq_name[i], soc_info->dev_name);
  1107. rc = -ENODEV;
  1108. continue;
  1109. }
  1110. disable_irq(soc_info->irq_num[i]);
  1111. }
  1112. return rc;
  1113. }
  1114. long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
  1115. uint32_t clk_index, unsigned long clk_rate)
  1116. {
  1117. if (!soc_info || (clk_index >= soc_info->num_clk) || (clk_rate == 0)) {
  1118. CAM_ERR(CAM_UTIL, "Invalid input params %pK, %d %lu",
  1119. soc_info, clk_index, clk_rate);
  1120. return clk_rate;
  1121. }
  1122. return cam_wrapper_clk_round_rate(soc_info->clk[clk_index], clk_rate);
  1123. }
  1124. /**
  1125. * cam_soc_util_set_clk_rate()
  1126. *
  1127. * @brief: Sets the given rate for the clk requested for
  1128. *
  1129. * @clk: Clock structure information for which rate is to be set
  1130. * @clk_name: Name of the clock for which rate is being set
  1131. * @clk_rate: Clock rate to be set
  1132. * @shared_clk: Whether this is a shared clk
  1133. * @is_src_clk: Whether this is source clk
  1134. * @clk_id: Clock ID
  1135. * @applied_clk_rate: Final clock rate set to the clk
  1136. *
  1137. * @return: Success or failure
  1138. */
  1139. static int cam_soc_util_set_clk_rate(struct cam_hw_soc_info *soc_info,
  1140. struct clk *clk, const char *clk_name,
  1141. int64_t clk_rate, bool shared_clk, bool is_src_clk, uint32_t clk_id,
  1142. unsigned long *applied_clk_rate)
  1143. {
  1144. int rc = 0;
  1145. long clk_rate_round = -1;
  1146. bool set_rate = false;
  1147. if (!clk_name) {
  1148. CAM_ERR(CAM_UTIL, "Invalid input clk %pK clk_name %pK",
  1149. clk, clk_name);
  1150. return -EINVAL;
  1151. }
  1152. CAM_DBG(CAM_UTIL, "set %s, rate %lld", clk_name, clk_rate);
  1153. if (!clk)
  1154. return 0;
  1155. if (clk_rate > 0) {
  1156. clk_rate_round = cam_wrapper_clk_round_rate(clk, clk_rate);
  1157. CAM_DBG(CAM_UTIL, "new_rate %ld", clk_rate_round);
  1158. if (clk_rate_round < 0) {
  1159. CAM_ERR(CAM_UTIL, "round failed for clock %s rc = %ld",
  1160. clk_name, clk_rate_round);
  1161. return clk_rate_round;
  1162. }
  1163. set_rate = true;
  1164. } else if (clk_rate == INIT_RATE) {
  1165. clk_rate_round = cam_wrapper_clk_get_rate(clk);
  1166. CAM_DBG(CAM_UTIL, "init new_rate %ld", clk_rate_round);
  1167. if (clk_rate_round == 0) {
  1168. clk_rate_round = cam_wrapper_clk_round_rate(clk, 0);
  1169. if (clk_rate_round <= 0) {
  1170. CAM_ERR(CAM_UTIL, "round rate failed on %s",
  1171. clk_name);
  1172. return clk_rate_round;
  1173. }
  1174. }
  1175. set_rate = true;
  1176. }
  1177. if (set_rate) {
  1178. if (shared_clk) {
  1179. CAM_DBG(CAM_UTIL,
  1180. "Dev %s clk %s id %d Set Shared clk %ld",
  1181. soc_info->dev_name, clk_name, clk_id,
  1182. clk_rate_round);
  1183. cam_soc_util_clk_wrapper_set_clk_rate(
  1184. clk_id, soc_info, clk, clk_rate_round);
  1185. } else {
  1186. bool set_rate_finish = false;
  1187. CAM_DBG(CAM_UTIL,
  1188. "Dev %s clk %s clk_id %d src_idx %d src_clk_id %d",
  1189. soc_info->dev_name, clk_name, clk_id,
  1190. soc_info->src_clk_idx,
  1191. (soc_info->src_clk_idx == -1) ? -1 :
  1192. soc_info->clk_id[soc_info->src_clk_idx]);
  1193. if (is_src_clk && soc_info->mmrm_handle &&
  1194. !skip_mmrm_set_rate) {
  1195. uint32_t idx = soc_info->src_clk_idx;
  1196. uint32_t min_level = soc_info->lowest_clk_level;
  1197. rc = cam_soc_util_set_sw_client_rate_through_mmrm(
  1198. soc_info->mmrm_handle,
  1199. soc_info->is_nrt_dev,
  1200. soc_info->clk_rate[min_level][idx],
  1201. clk_rate_round, 1);
  1202. if (rc) {
  1203. CAM_ERR(CAM_UTIL,
  1204. "set_sw_client_rate through mmrm failed on %s clk_id %d, rate=%ld",
  1205. clk_name, clk_id, clk_rate_round);
  1206. return rc;
  1207. }
  1208. set_rate_finish = true;
  1209. }
  1210. if (!set_rate_finish) {
  1211. rc = cam_wrapper_clk_set_rate(clk, clk_rate_round);
  1212. if (rc) {
  1213. CAM_ERR(CAM_UTIL, "set_rate failed on %s", clk_name);
  1214. return rc;
  1215. }
  1216. }
  1217. }
  1218. }
  1219. if (applied_clk_rate)
  1220. *applied_clk_rate = clk_rate_round;
  1221. return rc;
  1222. }
  1223. int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info, int cesta_client_idx,
  1224. unsigned long clk_rate_high, unsigned long clk_rate_low)
  1225. {
  1226. int rc = 0;
  1227. int i = 0;
  1228. int32_t src_clk_idx;
  1229. int32_t scl_clk_idx;
  1230. struct clk *clk = NULL;
  1231. int32_t apply_level;
  1232. uint32_t clk_level_override_high = 0, clk_level_override_low = 0;
  1233. if (!soc_info || (soc_info->src_clk_idx < 0) ||
  1234. (soc_info->src_clk_idx >= CAM_SOC_MAX_CLK)) {
  1235. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d",
  1236. soc_info ? soc_info->src_clk_idx : -1);
  1237. return -EINVAL;
  1238. }
  1239. src_clk_idx = soc_info->src_clk_idx;
  1240. clk_level_override_high = soc_info->clk_level_override_high;
  1241. clk_level_override_low = soc_info->clk_level_override_low;
  1242. if (clk_level_override_high && clk_rate_high)
  1243. clk_rate_high = soc_info->clk_rate[clk_level_override_high][src_clk_idx];
  1244. if (clk_level_override_low && clk_rate_low)
  1245. clk_rate_low = soc_info->clk_rate[clk_level_override_low][src_clk_idx];
  1246. clk = soc_info->clk[src_clk_idx];
  1247. rc = cam_soc_util_get_clk_level(soc_info, clk_rate_high, src_clk_idx,
  1248. &apply_level);
  1249. if (rc || (apply_level < 0) || (apply_level >= CAM_MAX_VOTE)) {
  1250. CAM_ERR(CAM_UTIL,
  1251. "set %s, rate %lld dev_name = %s apply level = %d",
  1252. soc_info->clk_name[src_clk_idx], clk_rate_high,
  1253. soc_info->dev_name, apply_level);
  1254. return -EINVAL;
  1255. }
  1256. CAM_DBG(CAM_UTIL,
  1257. "set %s, cesta_client_idx: %d rate [%ld %ld] dev_name = %s apply level = %d",
  1258. soc_info->clk_name[src_clk_idx], cesta_client_idx, clk_rate_high, clk_rate_low,
  1259. soc_info->dev_name, apply_level);
  1260. if ((soc_info->cam_cx_ipeak_enable) && (clk_rate_high > 0)) {
  1261. cam_cx_ipeak_update_vote_cx_ipeak(soc_info,
  1262. apply_level);
  1263. }
  1264. if (soc_info->is_clk_drv_en && CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  1265. rc = cam_soc_util_set_cesta_clk_rate(soc_info, cesta_client_idx, clk_rate_high,
  1266. clk_rate_low,
  1267. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].high,
  1268. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].low);
  1269. if (rc) {
  1270. CAM_ERR(CAM_UTIL,
  1271. "Failed in setting cesta clk rates[high low]:[%ld %ld] client_idx:%d rc:%d",
  1272. clk_rate_high, clk_rate_low, cesta_client_idx, rc);
  1273. return rc;
  1274. }
  1275. goto end;
  1276. }
  1277. rc = cam_soc_util_set_clk_rate(soc_info, clk,
  1278. soc_info->clk_name[src_clk_idx], clk_rate_high,
  1279. CAM_IS_BIT_SET(soc_info->shared_clk_mask, src_clk_idx),
  1280. true, soc_info->clk_id[src_clk_idx],
  1281. &soc_info->applied_src_clk_rates.sw_client);
  1282. if (rc) {
  1283. CAM_ERR(CAM_UTIL,
  1284. "SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d",
  1285. soc_info->clk_name[src_clk_idx], clk_rate_high,
  1286. soc_info->dev_name, rc);
  1287. return rc;
  1288. }
  1289. /* set clk rate for scalable clk if available */
  1290. for (i = 0; i < soc_info->scl_clk_count; i++) {
  1291. scl_clk_idx = soc_info->scl_clk_idx[i];
  1292. if (scl_clk_idx < 0) {
  1293. CAM_DBG(CAM_UTIL, "Scl clk index invalid");
  1294. continue;
  1295. }
  1296. clk = soc_info->clk[scl_clk_idx];
  1297. rc = cam_soc_util_set_clk_rate(soc_info, clk,
  1298. soc_info->clk_name[scl_clk_idx],
  1299. soc_info->clk_rate[apply_level][scl_clk_idx],
  1300. CAM_IS_BIT_SET(soc_info->shared_clk_mask, scl_clk_idx),
  1301. false, soc_info->clk_id[scl_clk_idx],
  1302. NULL);
  1303. if (rc) {
  1304. CAM_WARN(CAM_UTIL,
  1305. "SET_RATE Failed: scl clk: %s, rate %d dev_name = %s, rc: %d",
  1306. soc_info->clk_name[scl_clk_idx],
  1307. soc_info->clk_rate[apply_level][scl_clk_idx],
  1308. soc_info->dev_name, rc);
  1309. }
  1310. }
  1311. end:
  1312. return 0;
  1313. }
  1314. int cam_soc_util_put_optional_clk(struct cam_hw_soc_info *soc_info,
  1315. int32_t clk_indx)
  1316. {
  1317. if (clk_indx < 0) {
  1318. CAM_ERR(CAM_UTIL, "Invalid params clk %d", clk_indx);
  1319. return -EINVAL;
  1320. }
  1321. if (CAM_IS_BIT_SET(soc_info->optional_shared_clk_mask, clk_indx))
  1322. cam_soc_util_clk_wrapper_unregister_entry(
  1323. soc_info->optional_clk_id[clk_indx], soc_info);
  1324. cam_wrapper_clk_put(soc_info->optional_clk[clk_indx]);
  1325. soc_info->optional_clk[clk_indx] = NULL;
  1326. return 0;
  1327. }
  1328. static struct clk *cam_soc_util_option_clk_get(struct device_node *np,
  1329. int index, uint32_t *clk_id)
  1330. {
  1331. struct of_phandle_args clkspec;
  1332. struct clk *clk;
  1333. int rc;
  1334. if (index < 0)
  1335. return ERR_PTR(-EINVAL);
  1336. rc = of_parse_phandle_with_args(np, "clocks-option", "#clock-cells",
  1337. index, &clkspec);
  1338. if (rc)
  1339. return ERR_PTR(rc);
  1340. clk = cam_wrapper_of_clk_get_from_provider(&clkspec);
  1341. *clk_id = clkspec.args[0];
  1342. of_node_put(clkspec.np);
  1343. return clk;
  1344. }
  1345. int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
  1346. const char *clk_name, int32_t *clk_index)
  1347. {
  1348. int index = 0;
  1349. int rc = 0;
  1350. struct device_node *of_node = NULL;
  1351. uint32_t shared_clk_val;
  1352. if (!soc_info || !clk_name || !clk_index) {
  1353. CAM_ERR(CAM_UTIL,
  1354. "Invalid params soc_info %pK clk_name %s clk_index %pK",
  1355. soc_info, clk_name, clk_index);
  1356. return -EINVAL;
  1357. }
  1358. of_node = soc_info->dev->of_node;
  1359. index = of_property_match_string(of_node, "clock-names-option",
  1360. clk_name);
  1361. if (index < 0) {
  1362. CAM_DBG(CAM_UTIL, "No clk data for %s", clk_name);
  1363. *clk_index = -1;
  1364. return -EINVAL;
  1365. }
  1366. if (index >= CAM_SOC_MAX_OPT_CLK) {
  1367. CAM_ERR(CAM_UTIL, "Insufficient optional clk entries %d %d",
  1368. index, CAM_SOC_MAX_OPT_CLK);
  1369. return -EINVAL;
  1370. }
  1371. of_property_read_string_index(of_node, "clock-names-option",
  1372. index, &(soc_info->optional_clk_name[index]));
  1373. soc_info->optional_clk[index] = cam_soc_util_option_clk_get(of_node,
  1374. index, &soc_info->optional_clk_id[index]);
  1375. if (IS_ERR(soc_info->optional_clk[index])) {
  1376. CAM_ERR(CAM_UTIL, "No clk named %s found. Dev %s", clk_name,
  1377. soc_info->dev_name);
  1378. *clk_index = -1;
  1379. return -EFAULT;
  1380. }
  1381. *clk_index = index;
  1382. rc = of_property_read_u32_index(of_node, "clock-rates-option",
  1383. index, &soc_info->optional_clk_rate[index]);
  1384. if (rc) {
  1385. CAM_ERR(CAM_UTIL,
  1386. "Error reading clock-rates clk_name %s index %d",
  1387. clk_name, index);
  1388. goto error;
  1389. }
  1390. /*
  1391. * Option clocks are assumed to be available to single Device here.
  1392. * Hence use INIT_RATE instead of NO_SET_RATE.
  1393. */
  1394. soc_info->optional_clk_rate[index] =
  1395. (soc_info->optional_clk_rate[index] == 0) ?
  1396. (int32_t)INIT_RATE : soc_info->optional_clk_rate[index];
  1397. CAM_DBG(CAM_UTIL, "clk_name %s index %d clk_rate %d",
  1398. clk_name, *clk_index, soc_info->optional_clk_rate[index]);
  1399. rc = of_property_read_u32_index(of_node, "shared-clks-option",
  1400. index, &shared_clk_val);
  1401. if (rc) {
  1402. CAM_DBG(CAM_UTIL, "Not shared clk %s index %d",
  1403. clk_name, index);
  1404. } else if (shared_clk_val > 1) {
  1405. CAM_WARN(CAM_UTIL, "Invalid shared clk val %d", shared_clk_val);
  1406. } else {
  1407. CAM_DBG(CAM_UTIL,
  1408. "Dev %s shared clk %s index %d, clk id %d, shared_clk_val %d",
  1409. soc_info->dev_name, clk_name, index,
  1410. soc_info->optional_clk_id[index], shared_clk_val);
  1411. if (shared_clk_val) {
  1412. CAM_SET_BIT(soc_info->optional_shared_clk_mask, index);
  1413. /* Create a wrapper entry if this is a shared clock */
  1414. CAM_DBG(CAM_UTIL,
  1415. "Dev %s, clk %s, id %d register wrapper entry for shared clk",
  1416. soc_info->dev_name,
  1417. soc_info->optional_clk_name[index],
  1418. soc_info->optional_clk_id[index]);
  1419. rc = cam_soc_util_clk_wrapper_register_entry(
  1420. soc_info->optional_clk_id[index],
  1421. soc_info->optional_clk[index], false,
  1422. soc_info,
  1423. soc_info->optional_clk_rate[index],
  1424. soc_info->optional_clk_name[index]);
  1425. if (rc) {
  1426. CAM_ERR(CAM_UTIL,
  1427. "Failed in registering shared clk Dev %s id %d",
  1428. soc_info->dev_name,
  1429. soc_info->optional_clk_id[index]);
  1430. goto error;
  1431. }
  1432. }
  1433. }
  1434. return 0;
  1435. error:
  1436. cam_wrapper_clk_put(soc_info->optional_clk[index]);
  1437. soc_info->optional_clk_rate[index] = 0;
  1438. soc_info->optional_clk[index] = NULL;
  1439. *clk_index = -1;
  1440. return rc;
  1441. }
  1442. int cam_soc_util_clk_enable(struct cam_hw_soc_info *soc_info, int cesta_client_idx,
  1443. bool optional_clk, int32_t clk_idx, int32_t apply_level)
  1444. {
  1445. int rc = 0;
  1446. struct clk *clk;
  1447. const char *clk_name;
  1448. unsigned long clk_rate;
  1449. uint32_t shared_clk_mask;
  1450. uint32_t clk_id;
  1451. bool is_src_clk = false;
  1452. if (!soc_info || (clk_idx < 0) || (apply_level >= CAM_MAX_VOTE)) {
  1453. CAM_ERR(CAM_UTIL, "Invalid param %d %d", clk_idx, apply_level);
  1454. return -EINVAL;
  1455. }
  1456. if (optional_clk) {
  1457. clk = soc_info->optional_clk[clk_idx];
  1458. clk_name = soc_info->optional_clk_name[clk_idx];
  1459. clk_rate = (apply_level == -1) ?
  1460. 0 : soc_info->optional_clk_rate[clk_idx];
  1461. shared_clk_mask = soc_info->optional_shared_clk_mask;
  1462. clk_id = soc_info->optional_clk_id[clk_idx];
  1463. } else {
  1464. clk = soc_info->clk[clk_idx];
  1465. clk_name = soc_info->clk_name[clk_idx];
  1466. clk_rate = (apply_level == -1) ?
  1467. 0 : soc_info->clk_rate[apply_level][clk_idx];
  1468. shared_clk_mask = soc_info->shared_clk_mask;
  1469. clk_id = soc_info->clk_id[clk_idx];
  1470. if (clk_idx == soc_info->src_clk_idx)
  1471. is_src_clk = true;
  1472. }
  1473. if (!clk)
  1474. return 0;
  1475. if (is_src_clk && soc_info->is_clk_drv_en && CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  1476. rc = cam_soc_util_set_cesta_clk_rate(soc_info, cesta_client_idx, clk_rate, clk_rate,
  1477. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].high,
  1478. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].low);
  1479. if (rc) {
  1480. CAM_ERR(CAM_UTIL,
  1481. "[%s] Failed in setting cesta clk rates[high low]:[%ld %ld] client_idx:%d rc:%d",
  1482. soc_info->dev_name, clk_rate, clk_rate, cesta_client_idx, rc);
  1483. return rc;
  1484. }
  1485. rc = cam_soc_util_cesta_channel_switch(cesta_client_idx, soc_info->dev_name);
  1486. if (rc) {
  1487. CAM_ERR(CAM_UTIL,
  1488. "[%s] Failed to apply power states for cesta client:%d rc:%d",
  1489. soc_info->dev_name, cesta_client_idx, rc);
  1490. return rc;
  1491. }
  1492. } else {
  1493. rc = cam_soc_util_set_clk_rate(soc_info, clk, clk_name, clk_rate,
  1494. CAM_IS_BIT_SET(shared_clk_mask, clk_idx), is_src_clk, clk_id,
  1495. &soc_info->applied_src_clk_rates.sw_client);
  1496. if (rc) {
  1497. CAM_ERR(CAM_UTIL, "[%s] Failed in setting clk rate %ld rc:%d",
  1498. soc_info->dev_name, clk_rate, rc);
  1499. return rc;
  1500. }
  1501. }
  1502. CAM_DBG(CAM_UTIL, "[%s] : clk enable %s", soc_info->dev_name, clk_name);
  1503. rc = cam_wrapper_clk_prepare_enable(clk);
  1504. if (rc) {
  1505. CAM_ERR(CAM_UTIL, "enable failed for %s: rc(%d)", clk_name, rc);
  1506. return rc;
  1507. }
  1508. return rc;
  1509. }
  1510. int cam_soc_util_clk_disable(struct cam_hw_soc_info *soc_info, int cesta_client_idx,
  1511. bool optional_clk, int32_t clk_idx)
  1512. {
  1513. int rc = 0;
  1514. struct clk *clk;
  1515. const char *clk_name;
  1516. uint32_t shared_clk_mask;
  1517. uint32_t clk_id;
  1518. if (!soc_info || (clk_idx < 0)) {
  1519. CAM_ERR(CAM_UTIL, "Invalid param %d", clk_idx);
  1520. return -EINVAL;
  1521. }
  1522. if (optional_clk) {
  1523. clk = soc_info->optional_clk[clk_idx];
  1524. clk_name = soc_info->optional_clk_name[clk_idx];
  1525. shared_clk_mask = soc_info->optional_shared_clk_mask;
  1526. clk_id = soc_info->optional_clk_id[clk_idx];
  1527. } else {
  1528. clk = soc_info->clk[clk_idx];
  1529. clk_name = soc_info->clk_name[clk_idx];
  1530. shared_clk_mask = soc_info->shared_clk_mask;
  1531. clk_id = soc_info->clk_id[clk_idx];
  1532. }
  1533. CAM_DBG(CAM_UTIL, "disable %s", clk_name);
  1534. if (!clk)
  1535. return 0;
  1536. cam_wrapper_clk_disable_unprepare(clk);
  1537. if ((clk_idx == soc_info->src_clk_idx) && soc_info->is_clk_drv_en &&
  1538. CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  1539. rc = cam_soc_util_set_cesta_clk_rate(soc_info, cesta_client_idx, 0, 0,
  1540. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].high,
  1541. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].low);
  1542. if (rc) {
  1543. CAM_ERR(CAM_UTIL,
  1544. "Failed in setting cesta clk rates[high low]:[0 0] client_idx:%d rc:%d",
  1545. cesta_client_idx, rc);
  1546. return rc;
  1547. }
  1548. rc = cam_soc_util_cesta_channel_switch(cesta_client_idx, soc_info->dev_name);
  1549. if (rc) {
  1550. CAM_ERR(CAM_CSIPHY,
  1551. "Failed to apply power states for cesta_client_idx:%d rc:%d",
  1552. cesta_client_idx, rc);
  1553. return rc;
  1554. }
  1555. } else {
  1556. if (CAM_IS_BIT_SET(shared_clk_mask, clk_idx)) {
  1557. CAM_DBG(CAM_UTIL,
  1558. "Dev %s clk %s Disabling Shared clk, set 0 rate",
  1559. soc_info->dev_name, clk_name);
  1560. cam_soc_util_clk_wrapper_set_clk_rate(clk_id, soc_info, clk, 0);
  1561. } else if (soc_info->mmrm_handle && (!skip_mmrm_set_rate) &&
  1562. (soc_info->src_clk_idx == clk_idx)) {
  1563. CAM_DBG(CAM_UTIL, "Dev %s Disabling %s clk, set 0 rate",
  1564. soc_info->dev_name, clk_name);
  1565. cam_soc_util_set_sw_client_rate_through_mmrm(
  1566. soc_info->mmrm_handle,
  1567. soc_info->is_nrt_dev,
  1568. 0, 0, 1);
  1569. }
  1570. }
  1571. return 0;
  1572. }
  1573. /**
  1574. * cam_soc_util_clk_enable_default()
  1575. *
  1576. * @brief: This function enables the default clocks present
  1577. * in soc_info
  1578. *
  1579. * @soc_info: Device soc struct to be populated
  1580. * @cesta_client_idx: CESTA Client idx for hw client based src clocks
  1581. * @clk_level: Clk level to apply while enabling
  1582. *
  1583. * @return: success or failure
  1584. */
  1585. int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
  1586. int cesta_client_idx, enum cam_vote_level clk_level)
  1587. {
  1588. int i, rc = 0;
  1589. enum cam_vote_level apply_level;
  1590. if ((soc_info->num_clk == 0) ||
  1591. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  1592. CAM_ERR(CAM_UTIL, "Invalid number of clock %d",
  1593. soc_info->num_clk);
  1594. return -EINVAL;
  1595. }
  1596. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level,
  1597. &apply_level);
  1598. if (rc) {
  1599. CAM_ERR(CAM_UTIL, "[%s] : failed to get level clk_level=%d, rc=%d",
  1600. soc_info->dev_name, clk_level, rc);
  1601. return rc;
  1602. }
  1603. if (soc_info->cam_cx_ipeak_enable)
  1604. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level);
  1605. CAM_DBG(CAM_UTIL, "Dev[%s] : cesta client %d, request level %s, apply level %s",
  1606. soc_info->dev_name, cesta_client_idx,
  1607. cam_soc_util_get_string_from_level(clk_level),
  1608. cam_soc_util_get_string_from_level(apply_level));
  1609. memset(&soc_info->applied_src_clk_rates, 0, sizeof(struct cam_soc_util_clk_rates));
  1610. for (i = 0; i < soc_info->num_clk; i++) {
  1611. rc = cam_soc_util_clk_enable(soc_info, cesta_client_idx, false, i, apply_level);
  1612. if (rc) {
  1613. CAM_ERR(CAM_UTIL,
  1614. "[%s] : failed to enable clk apply_level=%d, rc=%d, cesta_client_idx=%d",
  1615. soc_info->dev_name, apply_level, rc, cesta_client_idx);
  1616. goto clk_disable;
  1617. }
  1618. if (soc_info->cam_cx_ipeak_enable)
  1619. CAM_DBG(CAM_UTIL,
  1620. "dev name = %s clk name = %s idx = %d apply_level = %d clc idx = %d",
  1621. soc_info->dev_name, soc_info->clk_name[i], i, apply_level, i);
  1622. }
  1623. return rc;
  1624. clk_disable:
  1625. if (soc_info->cam_cx_ipeak_enable)
  1626. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
  1627. for (i--; i >= 0; i--) {
  1628. cam_soc_util_clk_disable(soc_info, cesta_client_idx, false, i);
  1629. }
  1630. return rc;
  1631. }
  1632. /**
  1633. * cam_soc_util_clk_disable_default()
  1634. *
  1635. * @brief: This function disables the default clocks present
  1636. * in soc_info
  1637. *
  1638. * @soc_info: device soc struct to be populated
  1639. * @cesta_client_idx: CESTA Client idx for hw client based src clocks
  1640. *
  1641. * @return: success or failure
  1642. */
  1643. void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info,
  1644. int cesta_client_idx)
  1645. {
  1646. int i;
  1647. if (soc_info->num_clk == 0)
  1648. return;
  1649. if (soc_info->cam_cx_ipeak_enable)
  1650. cam_cx_ipeak_unvote_cx_ipeak(soc_info);
  1651. for (i = soc_info->num_clk - 1; i >= 0; i--)
  1652. cam_soc_util_clk_disable(soc_info, cesta_client_idx, false, i);
  1653. }
  1654. /**
  1655. * cam_soc_util_get_dt_clk_info()
  1656. *
  1657. * @brief: Parse the DT and populate the Clock properties
  1658. *
  1659. * @soc_info: device soc struct to be populated
  1660. * @src_clk_str name of src clock that has rate control
  1661. *
  1662. * @return: success or failure
  1663. */
  1664. static int cam_soc_util_get_dt_clk_info(struct cam_hw_soc_info *soc_info)
  1665. {
  1666. struct device_node *of_node = NULL;
  1667. int count;
  1668. int num_clk_rates, num_clk_levels;
  1669. int i, j, rc;
  1670. int32_t num_clk_level_strings;
  1671. const char *src_clk_str = NULL;
  1672. const char *scl_clk_str = NULL;
  1673. const char *clk_control_debugfs = NULL;
  1674. const char *clk_cntl_lvl_string = NULL;
  1675. enum cam_vote_level level;
  1676. int shared_clk_cnt;
  1677. struct of_phandle_args clk_args = {0};
  1678. if (!soc_info || !soc_info->dev)
  1679. return -EINVAL;
  1680. of_node = soc_info->dev->of_node;
  1681. if (!of_property_read_bool(of_node, "use-shared-clk")) {
  1682. CAM_DBG(CAM_UTIL, "No shared clk parameter defined");
  1683. soc_info->use_shared_clk = false;
  1684. } else {
  1685. soc_info->use_shared_clk = true;
  1686. }
  1687. count = of_property_count_strings(of_node, "clock-names");
  1688. CAM_DBG(CAM_UTIL, "E: dev_name = %s count = %d",
  1689. soc_info->dev_name, count);
  1690. if (count > CAM_SOC_MAX_CLK) {
  1691. CAM_ERR(CAM_UTIL, "invalid count of clocks, count=%d", count);
  1692. rc = -EINVAL;
  1693. return rc;
  1694. }
  1695. if (count <= 0) {
  1696. CAM_DBG(CAM_UTIL, "No clock-names found");
  1697. count = 0;
  1698. soc_info->num_clk = count;
  1699. return 0;
  1700. }
  1701. soc_info->num_clk = count;
  1702. for (i = 0; i < count; i++) {
  1703. rc = of_property_read_string_index(of_node, "clock-names",
  1704. i, &(soc_info->clk_name[i]));
  1705. CAM_DBG(CAM_UTIL, "clock-names[%d] = %s",
  1706. i, soc_info->clk_name[i]);
  1707. if (rc) {
  1708. CAM_ERR(CAM_UTIL,
  1709. "i= %d count= %d reading clock-names failed",
  1710. i, count);
  1711. return rc;
  1712. }
  1713. }
  1714. num_clk_rates = of_property_count_u32_elems(of_node, "clock-rates");
  1715. if (num_clk_rates <= 0) {
  1716. CAM_ERR(CAM_UTIL, "reading clock-rates count failed");
  1717. return -EINVAL;
  1718. }
  1719. if ((num_clk_rates % soc_info->num_clk) != 0) {
  1720. CAM_ERR(CAM_UTIL,
  1721. "mismatch clk/rates, No of clocks=%d, No of rates=%d",
  1722. soc_info->num_clk, num_clk_rates);
  1723. return -EINVAL;
  1724. }
  1725. num_clk_levels = (num_clk_rates / soc_info->num_clk);
  1726. num_clk_level_strings = of_property_count_strings(of_node,
  1727. "clock-cntl-level");
  1728. if (num_clk_level_strings != num_clk_levels) {
  1729. CAM_ERR(CAM_UTIL,
  1730. "Mismatch No of levels=%d, No of level string=%d",
  1731. num_clk_levels, num_clk_level_strings);
  1732. return -EINVAL;
  1733. }
  1734. soc_info->lowest_clk_level = CAM_TURBO_VOTE;
  1735. for (i = 0; i < num_clk_levels; i++) {
  1736. rc = of_property_read_string_index(of_node,
  1737. "clock-cntl-level", i, &clk_cntl_lvl_string);
  1738. if (rc) {
  1739. CAM_ERR(CAM_UTIL,
  1740. "Error reading clock-cntl-level, rc=%d", rc);
  1741. return rc;
  1742. }
  1743. rc = cam_soc_util_get_level_from_string(clk_cntl_lvl_string,
  1744. &level);
  1745. if (rc)
  1746. return rc;
  1747. CAM_DBG(CAM_UTIL,
  1748. "[%d] : %s %d", i, clk_cntl_lvl_string, level);
  1749. soc_info->clk_level_valid[level] = true;
  1750. for (j = 0; j < soc_info->num_clk; j++) {
  1751. rc = of_property_read_u32_index(of_node, "clock-rates",
  1752. ((i * soc_info->num_clk) + j),
  1753. &soc_info->clk_rate[level][j]);
  1754. if (rc) {
  1755. CAM_ERR(CAM_UTIL,
  1756. "Error reading clock-rates, rc=%d",
  1757. rc);
  1758. return rc;
  1759. }
  1760. soc_info->clk_rate[level][j] =
  1761. (soc_info->clk_rate[level][j] == 0) ?
  1762. (int32_t)NO_SET_RATE :
  1763. soc_info->clk_rate[level][j];
  1764. CAM_DBG(CAM_UTIL, "soc_info->clk_rate[%d][%d] = %d",
  1765. level, j,
  1766. soc_info->clk_rate[level][j]);
  1767. }
  1768. if ((level > CAM_MINSVS_VOTE) &&
  1769. (level < soc_info->lowest_clk_level))
  1770. soc_info->lowest_clk_level = level;
  1771. }
  1772. soc_info->src_clk_idx = -1;
  1773. rc = of_property_read_string_index(of_node, "src-clock-name", 0,
  1774. &src_clk_str);
  1775. if (rc || !src_clk_str) {
  1776. CAM_DBG(CAM_UTIL, "No src_clk_str found");
  1777. rc = 0;
  1778. goto end;
  1779. }
  1780. for (i = 0; i < soc_info->num_clk; i++) {
  1781. if (strcmp(soc_info->clk_name[i], src_clk_str) == 0) {
  1782. soc_info->src_clk_idx = i;
  1783. CAM_DBG(CAM_UTIL, "src clock = %s, index = %d",
  1784. src_clk_str, i);
  1785. }
  1786. rc = of_parse_phandle_with_args(of_node, "clocks",
  1787. "#clock-cells", i, &clk_args);
  1788. if (rc) {
  1789. CAM_ERR(CAM_CPAS,
  1790. "failed to clock info rc=%d", rc);
  1791. rc = -EINVAL;
  1792. goto end;
  1793. }
  1794. soc_info->clk_id[i] = clk_args.args[0];
  1795. of_node_put(clk_args.np);
  1796. CAM_DBG(CAM_UTIL, "Dev %s clk %s id %d",
  1797. soc_info->dev_name, soc_info->clk_name[i],
  1798. soc_info->clk_id[i]);
  1799. }
  1800. CAM_DBG(CAM_UTIL, "Dev %s src_clk_idx %d, lowest_clk_level %d",
  1801. soc_info->dev_name, soc_info->src_clk_idx,
  1802. soc_info->lowest_clk_level);
  1803. soc_info->shared_clk_mask = 0;
  1804. shared_clk_cnt = of_property_count_u32_elems(of_node, "shared-clks");
  1805. if (shared_clk_cnt <= 0) {
  1806. CAM_DBG(CAM_UTIL, "Dev %s, no shared clks", soc_info->dev_name);
  1807. } else if (shared_clk_cnt != count) {
  1808. CAM_ERR(CAM_UTIL, "Dev %s, incorrect shared clock count %d %d",
  1809. soc_info->dev_name, shared_clk_cnt, count);
  1810. rc = -EINVAL;
  1811. goto end;
  1812. } else {
  1813. uint32_t shared_clk_val;
  1814. for (i = 0; i < shared_clk_cnt; i++) {
  1815. rc = of_property_read_u32_index(of_node,
  1816. "shared-clks", i, &shared_clk_val);
  1817. if (rc || (shared_clk_val > 1)) {
  1818. CAM_ERR(CAM_UTIL,
  1819. "Incorrect shared clk info at %d, val=%d, count=%d",
  1820. i, shared_clk_val, shared_clk_cnt);
  1821. rc = -EINVAL;
  1822. goto end;
  1823. }
  1824. if (shared_clk_val)
  1825. CAM_SET_BIT(soc_info->shared_clk_mask, i);
  1826. }
  1827. CAM_DBG(CAM_UTIL, "Dev %s shared clk mask 0x%x",
  1828. soc_info->dev_name, soc_info->shared_clk_mask);
  1829. }
  1830. /* scalable clk info parsing */
  1831. soc_info->scl_clk_count = 0;
  1832. soc_info->scl_clk_count = of_property_count_strings(of_node,
  1833. "scl-clk-names");
  1834. if ((soc_info->scl_clk_count <= 0) ||
  1835. (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) {
  1836. if (soc_info->scl_clk_count == -EINVAL) {
  1837. CAM_DBG(CAM_UTIL, "scl_clk_name prop not avialable");
  1838. } else if ((soc_info->scl_clk_count == -ENODATA) ||
  1839. (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) {
  1840. CAM_ERR(CAM_UTIL, "Invalid scl_clk_count: %d",
  1841. soc_info->scl_clk_count);
  1842. return -EINVAL;
  1843. }
  1844. CAM_DBG(CAM_UTIL, "Invalid scl_clk count: %d",
  1845. soc_info->scl_clk_count);
  1846. soc_info->scl_clk_count = -1;
  1847. } else {
  1848. CAM_DBG(CAM_UTIL, "No of scalable clocks: %d",
  1849. soc_info->scl_clk_count);
  1850. for (i = 0; i < soc_info->scl_clk_count; i++) {
  1851. rc = of_property_read_string_index(of_node,
  1852. "scl-clk-names", i,
  1853. (const char **)&scl_clk_str);
  1854. if (rc || !scl_clk_str) {
  1855. CAM_WARN(CAM_UTIL, "scl_clk_str is NULL");
  1856. soc_info->scl_clk_idx[i] = -1;
  1857. continue;
  1858. }
  1859. for (j = 0; j < soc_info->num_clk; j++) {
  1860. if (strnstr(scl_clk_str, soc_info->clk_name[j],
  1861. strlen(scl_clk_str))) {
  1862. soc_info->scl_clk_idx[i] = j;
  1863. CAM_DBG(CAM_UTIL,
  1864. "scl clock = %s, index = %d",
  1865. scl_clk_str, j);
  1866. break;
  1867. }
  1868. }
  1869. }
  1870. }
  1871. rc = of_property_read_string_index(of_node,
  1872. "clock-control-debugfs", 0, &clk_control_debugfs);
  1873. if (rc || !clk_control_debugfs) {
  1874. CAM_DBG(CAM_UTIL, "No clock_control_debugfs property found");
  1875. rc = 0;
  1876. goto end;
  1877. }
  1878. if (strcmp("true", clk_control_debugfs) == 0)
  1879. soc_info->clk_control_enable = true;
  1880. CAM_DBG(CAM_UTIL, "X: dev_name = %s count = %d",
  1881. soc_info->dev_name, count);
  1882. end:
  1883. return rc;
  1884. }
  1885. int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
  1886. int cesta_client_idx, enum cam_vote_level clk_level_high,
  1887. enum cam_vote_level clk_level_low, bool do_not_set_src_clk)
  1888. {
  1889. int i, rc = 0;
  1890. enum cam_vote_level apply_level_high;
  1891. enum cam_vote_level apply_level_low = CAM_LOWSVS_VOTE;
  1892. unsigned long applied_clk_rate;
  1893. if ((soc_info->num_clk == 0) ||
  1894. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  1895. CAM_ERR(CAM_UTIL, "Invalid number of clock %d", soc_info->num_clk);
  1896. return -EINVAL;
  1897. }
  1898. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level_high,
  1899. &apply_level_high);
  1900. if (rc) {
  1901. CAM_ERR(CAM_UTIL, "[%s] : failed to get level clk_level_high=%d, rc=%d",
  1902. soc_info->dev_name, clk_level_high, rc);
  1903. return rc;
  1904. }
  1905. if (soc_info->is_clk_drv_en && CAM_IS_VALID_CESTA_IDX(cesta_client_idx)) {
  1906. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level_low,
  1907. &apply_level_low);
  1908. if (rc) {
  1909. CAM_ERR(CAM_UTIL, "[%s] : failed to get level clk_level_low=%d, rc=%d",
  1910. soc_info->dev_name, clk_level_low, rc);
  1911. return rc;
  1912. }
  1913. }
  1914. if (soc_info->cam_cx_ipeak_enable)
  1915. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level_high);
  1916. for (i = 0; i < soc_info->num_clk; i++) {
  1917. if (do_not_set_src_clk && (i == soc_info->src_clk_idx)) {
  1918. CAM_DBG(CAM_UTIL, "Skipping set rate for src clk %s",
  1919. soc_info->clk_name[i]);
  1920. continue;
  1921. }
  1922. if (soc_info->is_clk_drv_en && CAM_IS_VALID_CESTA_IDX(cesta_client_idx) &&
  1923. (i == soc_info->src_clk_idx)) {
  1924. rc = cam_soc_util_set_cesta_clk_rate(soc_info, cesta_client_idx,
  1925. soc_info->clk_rate[apply_level_high][i],
  1926. soc_info->clk_rate[apply_level_low][i],
  1927. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].high,
  1928. &soc_info->applied_src_clk_rates.hw_client[cesta_client_idx].low);
  1929. if (rc) {
  1930. CAM_ERR(CAM_UTIL,
  1931. "Failed to set the req clk level[high low]: [%s %s] cesta_client_idx: %d",
  1932. cam_soc_util_get_string_from_level(apply_level_high),
  1933. cam_soc_util_get_string_from_level(apply_level_low),
  1934. cesta_client_idx);
  1935. break;
  1936. }
  1937. continue;
  1938. }
  1939. CAM_DBG(CAM_UTIL, "Set rate for clk %s rate %d", soc_info->clk_name[i],
  1940. soc_info->clk_rate[apply_level_high][i]);
  1941. rc = cam_soc_util_set_clk_rate(soc_info, soc_info->clk[i],
  1942. soc_info->clk_name[i],
  1943. soc_info->clk_rate[apply_level_high][i],
  1944. CAM_IS_BIT_SET(soc_info->shared_clk_mask, i),
  1945. (i == soc_info->src_clk_idx) ? true : false,
  1946. soc_info->clk_id[i],
  1947. &applied_clk_rate);
  1948. if (rc < 0) {
  1949. CAM_DBG(CAM_UTIL,
  1950. "dev name = %s clk_name = %s idx = %d apply_level = %s",
  1951. soc_info->dev_name, soc_info->clk_name[i],
  1952. i, cam_soc_util_get_string_from_level(apply_level_high));
  1953. if (soc_info->cam_cx_ipeak_enable)
  1954. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
  1955. break;
  1956. }
  1957. if (i == soc_info->src_clk_idx)
  1958. soc_info->applied_src_clk_rates.sw_client = applied_clk_rate;
  1959. }
  1960. return rc;
  1961. };
  1962. static int cam_soc_util_get_dt_gpio_req_tbl(struct device_node *of_node,
  1963. struct cam_soc_gpio_data *gconf, uint16_t *gpio_array,
  1964. uint16_t gpio_array_size)
  1965. {
  1966. int32_t rc = 0, i = 0;
  1967. uint32_t count = 0;
  1968. uint32_t *val_array = NULL;
  1969. if (!of_get_property(of_node, "gpio-req-tbl-num", &count))
  1970. return 0;
  1971. count /= sizeof(uint32_t);
  1972. if (!count) {
  1973. CAM_ERR(CAM_UTIL, "gpio-req-tbl-num 0");
  1974. return 0;
  1975. }
  1976. val_array = kcalloc(count, sizeof(uint32_t), GFP_KERNEL);
  1977. if (!val_array)
  1978. return -ENOMEM;
  1979. gconf->cam_gpio_req_tbl = kcalloc(count, sizeof(struct gpio),
  1980. GFP_KERNEL);
  1981. if (!gconf->cam_gpio_req_tbl) {
  1982. rc = -ENOMEM;
  1983. goto free_val_array;
  1984. }
  1985. gconf->cam_gpio_req_tbl_size = count;
  1986. rc = of_property_read_u32_array(of_node, "gpio-req-tbl-num",
  1987. val_array, count);
  1988. if (rc) {
  1989. CAM_ERR(CAM_UTIL, "failed in reading gpio-req-tbl-num, rc = %d",
  1990. rc);
  1991. goto free_gpio_req_tbl;
  1992. }
  1993. for (i = 0; i < count; i++) {
  1994. if (val_array[i] >= gpio_array_size) {
  1995. CAM_ERR(CAM_UTIL, "gpio req tbl index %d invalid",
  1996. val_array[i]);
  1997. goto free_gpio_req_tbl;
  1998. }
  1999. gconf->cam_gpio_req_tbl[i].gpio = gpio_array[val_array[i]];
  2000. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].gpio = %d", i,
  2001. gconf->cam_gpio_req_tbl[i].gpio);
  2002. }
  2003. rc = of_property_read_u32_array(of_node, "gpio-req-tbl-flags",
  2004. val_array, count);
  2005. if (rc) {
  2006. CAM_ERR(CAM_UTIL, "Failed in gpio-req-tbl-flags, rc %d", rc);
  2007. goto free_gpio_req_tbl;
  2008. }
  2009. for (i = 0; i < count; i++) {
  2010. gconf->cam_gpio_req_tbl[i].flags = val_array[i];
  2011. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].flags = %ld", i,
  2012. gconf->cam_gpio_req_tbl[i].flags);
  2013. }
  2014. for (i = 0; i < count; i++) {
  2015. rc = of_property_read_string_index(of_node,
  2016. "gpio-req-tbl-label", i,
  2017. &gconf->cam_gpio_req_tbl[i].label);
  2018. if (rc) {
  2019. CAM_ERR(CAM_UTIL, "Failed rc %d", rc);
  2020. goto free_gpio_req_tbl;
  2021. }
  2022. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].label = %s", i,
  2023. gconf->cam_gpio_req_tbl[i].label);
  2024. }
  2025. kfree(val_array);
  2026. return rc;
  2027. free_gpio_req_tbl:
  2028. kfree(gconf->cam_gpio_req_tbl);
  2029. free_val_array:
  2030. kfree(val_array);
  2031. gconf->cam_gpio_req_tbl_size = 0;
  2032. return rc;
  2033. }
  2034. static int cam_soc_util_get_gpio_info(struct cam_hw_soc_info *soc_info)
  2035. {
  2036. int32_t rc = 0, i = 0;
  2037. uint16_t *gpio_array = NULL;
  2038. int16_t gpio_array_size = 0;
  2039. struct cam_soc_gpio_data *gconf = NULL;
  2040. struct device_node *of_node = NULL;
  2041. if (!soc_info || !soc_info->dev)
  2042. return -EINVAL;
  2043. of_node = soc_info->dev->of_node;
  2044. /* Validate input parameters */
  2045. if (!of_node) {
  2046. CAM_ERR(CAM_UTIL, "Invalid param of_node");
  2047. return -EINVAL;
  2048. }
  2049. gpio_array_size = of_gpio_count(of_node);
  2050. if (gpio_array_size <= 0)
  2051. return 0;
  2052. CAM_DBG(CAM_UTIL, "gpio count %d", gpio_array_size);
  2053. gpio_array = kcalloc(gpio_array_size, sizeof(uint16_t), GFP_KERNEL);
  2054. if (!gpio_array) {
  2055. rc = -ENOMEM;
  2056. goto err;
  2057. }
  2058. for (i = 0; i < gpio_array_size; i++) {
  2059. gpio_array[i] = of_get_gpio(of_node, i);
  2060. CAM_DBG(CAM_UTIL, "gpio_array[%d] = %d", i, gpio_array[i]);
  2061. }
  2062. gconf = kzalloc(sizeof(*gconf), GFP_KERNEL);
  2063. if (!gconf) {
  2064. rc = -ENOMEM;
  2065. goto free_gpio_array;
  2066. }
  2067. rc = cam_soc_util_get_dt_gpio_req_tbl(of_node, gconf, gpio_array,
  2068. gpio_array_size);
  2069. if (rc) {
  2070. CAM_ERR(CAM_UTIL, "failed in msm_camera_get_dt_gpio_req_tbl");
  2071. goto free_gpio_conf;
  2072. }
  2073. gconf->cam_gpio_common_tbl = kcalloc(gpio_array_size,
  2074. sizeof(struct gpio), GFP_KERNEL);
  2075. if (!gconf->cam_gpio_common_tbl) {
  2076. rc = -ENOMEM;
  2077. goto free_gpio_conf;
  2078. }
  2079. for (i = 0; i < gpio_array_size; i++)
  2080. gconf->cam_gpio_common_tbl[i].gpio = gpio_array[i];
  2081. gconf->cam_gpio_common_tbl_size = gpio_array_size;
  2082. soc_info->gpio_data = gconf;
  2083. kfree(gpio_array);
  2084. return rc;
  2085. free_gpio_conf:
  2086. kfree(gconf);
  2087. free_gpio_array:
  2088. kfree(gpio_array);
  2089. err:
  2090. soc_info->gpio_data = NULL;
  2091. return rc;
  2092. }
  2093. static int cam_soc_util_request_gpio_table(
  2094. struct cam_hw_soc_info *soc_info, bool gpio_en)
  2095. {
  2096. int rc = 0, i = 0;
  2097. uint8_t size = 0;
  2098. struct cam_soc_gpio_data *gpio_conf =
  2099. soc_info->gpio_data;
  2100. struct gpio *gpio_tbl = NULL;
  2101. if (!gpio_conf) {
  2102. CAM_DBG(CAM_UTIL, "No GPIO entry");
  2103. return 0;
  2104. }
  2105. if (gpio_conf->cam_gpio_common_tbl_size <= 0) {
  2106. CAM_ERR(CAM_UTIL, "GPIO table size is invalid");
  2107. return -EINVAL;
  2108. }
  2109. size = gpio_conf->cam_gpio_req_tbl_size;
  2110. gpio_tbl = gpio_conf->cam_gpio_req_tbl;
  2111. if (!gpio_tbl || !size) {
  2112. CAM_ERR(CAM_UTIL, "Invalid gpio_tbl %pK / size %d",
  2113. gpio_tbl, size);
  2114. return -EINVAL;
  2115. }
  2116. for (i = 0; i < size; i++) {
  2117. CAM_DBG(CAM_UTIL, "i=%d, gpio=%d dir=%ld", i,
  2118. gpio_tbl[i].gpio, gpio_tbl[i].flags);
  2119. }
  2120. if (gpio_en) {
  2121. for (i = 0; i < size; i++) {
  2122. rc = gpio_request_one(gpio_tbl[i].gpio,
  2123. gpio_tbl[i].flags, gpio_tbl[i].label);
  2124. if (rc) {
  2125. /*
  2126. * After GPIO request fails, contine to
  2127. * apply new gpios, outout a error message
  2128. * for driver bringup debug
  2129. */
  2130. CAM_ERR(CAM_UTIL, "gpio %d:%s request fails",
  2131. gpio_tbl[i].gpio, gpio_tbl[i].label);
  2132. }
  2133. }
  2134. } else {
  2135. gpio_free_array(gpio_tbl, size);
  2136. }
  2137. return rc;
  2138. }
  2139. static int cam_soc_util_get_dt_regulator_info
  2140. (struct cam_hw_soc_info *soc_info)
  2141. {
  2142. int rc = 0, count = 0, i = 0;
  2143. struct device_node *of_node = NULL;
  2144. if (!soc_info || !soc_info->dev) {
  2145. CAM_ERR(CAM_UTIL, "Invalid parameters");
  2146. return -EINVAL;
  2147. }
  2148. of_node = soc_info->dev->of_node;
  2149. soc_info->num_rgltr = 0;
  2150. count = of_property_count_strings(of_node, "regulator-names");
  2151. if (count != -EINVAL) {
  2152. if (count <= 0) {
  2153. CAM_ERR(CAM_UTIL, "no regulators found");
  2154. return -EINVAL;
  2155. }
  2156. soc_info->num_rgltr = count;
  2157. } else {
  2158. CAM_DBG(CAM_UTIL, "No regulators node found");
  2159. return 0;
  2160. }
  2161. if (soc_info->num_rgltr > CAM_SOC_MAX_REGULATOR) {
  2162. CAM_ERR(CAM_UTIL, "Invalid regulator count:%d",
  2163. soc_info->num_rgltr);
  2164. return -EINVAL;
  2165. }
  2166. for (i = 0; i < soc_info->num_rgltr; i++) {
  2167. rc = of_property_read_string_index(of_node,
  2168. "regulator-names", i, &soc_info->rgltr_name[i]);
  2169. CAM_DBG(CAM_UTIL, "rgltr_name[%d] = %s",
  2170. i, soc_info->rgltr_name[i]);
  2171. if (rc) {
  2172. CAM_ERR(CAM_UTIL, "no regulator resource at cnt=%d", i);
  2173. return -ENODEV;
  2174. }
  2175. }
  2176. if (!of_property_read_bool(of_node, "rgltr-cntrl-support")) {
  2177. CAM_DBG(CAM_UTIL, "No regulator control parameter defined");
  2178. soc_info->rgltr_ctrl_support = false;
  2179. return 0;
  2180. }
  2181. soc_info->rgltr_ctrl_support = true;
  2182. rc = of_property_read_u32_array(of_node, "rgltr-min-voltage",
  2183. soc_info->rgltr_min_volt, soc_info->num_rgltr);
  2184. if (rc) {
  2185. CAM_ERR(CAM_UTIL, "No minimum volatage value found, rc=%d", rc);
  2186. return -EINVAL;
  2187. }
  2188. rc = of_property_read_u32_array(of_node, "rgltr-max-voltage",
  2189. soc_info->rgltr_max_volt, soc_info->num_rgltr);
  2190. if (rc) {
  2191. CAM_ERR(CAM_UTIL, "No maximum volatage value found, rc=%d", rc);
  2192. return -EINVAL;
  2193. }
  2194. rc = of_property_read_u32_array(of_node, "rgltr-load-current",
  2195. soc_info->rgltr_op_mode, soc_info->num_rgltr);
  2196. if (rc) {
  2197. CAM_ERR(CAM_UTIL, "No Load curent found rc=%d", rc);
  2198. return -EINVAL;
  2199. }
  2200. return rc;
  2201. }
  2202. #ifdef CONFIG_CAM_PRESIL
  2203. static uint32_t next_dummy_irq_line_num = 0x000f;
  2204. struct resource dummy_irq_line[512];
  2205. #endif
  2206. int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info)
  2207. {
  2208. struct device_node *of_node = NULL;
  2209. int count = 0, i = 0, rc = 0;
  2210. if (!soc_info || !soc_info->dev)
  2211. return -EINVAL;
  2212. of_node = soc_info->dev->of_node;
  2213. rc = of_property_read_u32(of_node, "cell-index", &soc_info->index);
  2214. if (rc) {
  2215. CAM_ERR(CAM_UTIL, "device %s failed to read cell-index",
  2216. soc_info->dev_name);
  2217. return rc;
  2218. }
  2219. count = of_property_count_strings(of_node, "reg-names");
  2220. if (count <= 0) {
  2221. CAM_DBG(CAM_UTIL, "no reg-names found for: %s",
  2222. soc_info->dev_name);
  2223. count = 0;
  2224. }
  2225. soc_info->num_mem_block = count;
  2226. for (i = 0; i < soc_info->num_mem_block; i++) {
  2227. rc = of_property_read_string_index(of_node, "reg-names", i,
  2228. &soc_info->mem_block_name[i]);
  2229. if (rc) {
  2230. CAM_ERR(CAM_UTIL, "failed to read reg-names at %d", i);
  2231. return rc;
  2232. }
  2233. soc_info->mem_block[i] =
  2234. platform_get_resource_byname(soc_info->pdev,
  2235. IORESOURCE_MEM, soc_info->mem_block_name[i]);
  2236. if (!soc_info->mem_block[i]) {
  2237. CAM_ERR(CAM_UTIL, "no mem resource by name %s",
  2238. soc_info->mem_block_name[i]);
  2239. rc = -ENODEV;
  2240. return rc;
  2241. }
  2242. }
  2243. rc = of_property_read_string(of_node, "label", &soc_info->label_name);
  2244. if (rc)
  2245. CAM_DBG(CAM_UTIL, "Label is not available in the node: %d", rc);
  2246. if (soc_info->num_mem_block > 0) {
  2247. rc = of_property_read_u32_array(of_node, "reg-cam-base",
  2248. soc_info->mem_block_cam_base, soc_info->num_mem_block);
  2249. if (rc) {
  2250. CAM_ERR(CAM_UTIL, "Error reading register offsets");
  2251. return rc;
  2252. }
  2253. }
  2254. count = of_property_count_strings(of_node, "interrupt-names");
  2255. if (count <= 0) {
  2256. CAM_DBG(CAM_UTIL, "No interrupt line present for: %s", soc_info->dev_name);
  2257. soc_info->irq_count = 0;
  2258. } else {
  2259. if (count > CAM_SOC_MAX_IRQ_LINES_PER_DEV) {
  2260. CAM_ERR(CAM_UTIL,
  2261. "Number of interrupt: %d exceeds maximum allowable interrupts: %d",
  2262. count, CAM_SOC_MAX_IRQ_LINES_PER_DEV);
  2263. return -EINVAL;
  2264. }
  2265. soc_info->irq_count = count;
  2266. for (i = 0; i < soc_info->irq_count; i++) {
  2267. rc = of_property_read_string_index(of_node, "interrupt-names",
  2268. i, &soc_info->irq_name[i]);
  2269. if (rc) {
  2270. CAM_ERR(CAM_UTIL, "failed to read interrupt name at %d", i);
  2271. return rc;
  2272. }
  2273. }
  2274. rc = cam_compat_util_get_irq(soc_info);
  2275. if (rc < 0) {
  2276. CAM_ERR(CAM_UTIL, "get irq resource failed: %d for: %s",
  2277. rc, soc_info->dev_name);
  2278. #ifndef CONFIG_CAM_PRESIL
  2279. return rc;
  2280. #else
  2281. /* Pre-sil for new devices not present on old */
  2282. for (i = 0; i < soc_info->irq_count; i++) {
  2283. soc_info->irq_line[i] =
  2284. &dummy_irq_line[next_dummy_irq_line_num++];
  2285. CAM_DBG(CAM_PRESIL,
  2286. "interrupt line for dev %s irq name %s number %d",
  2287. soc_info->dev_name, soc_info->irq_name[i],
  2288. soc_info->irq_line[i]->start);
  2289. }
  2290. #endif
  2291. }
  2292. }
  2293. rc = of_property_read_string_index(of_node, "compatible", 0,
  2294. (const char **)&soc_info->compatible);
  2295. if (rc)
  2296. CAM_DBG(CAM_UTIL, "No compatible string present for: %s",
  2297. soc_info->dev_name);
  2298. soc_info->is_nrt_dev = false;
  2299. if (of_property_read_bool(of_node, "nrt-device"))
  2300. soc_info->is_nrt_dev = true;
  2301. CAM_DBG(CAM_UTIL, "Dev %s, nrt_dev %d",
  2302. soc_info->dev_name, soc_info->is_nrt_dev);
  2303. rc = cam_soc_util_get_dt_regulator_info(soc_info);
  2304. if (rc)
  2305. return rc;
  2306. rc = cam_soc_util_get_dt_clk_info(soc_info);
  2307. if (rc)
  2308. return rc;
  2309. rc = cam_soc_util_get_gpio_info(soc_info);
  2310. if (rc)
  2311. return rc;
  2312. if (of_find_property(of_node, "qcom,cam-cx-ipeak", NULL))
  2313. rc = cam_cx_ipeak_register_cx_ipeak(soc_info);
  2314. return rc;
  2315. }
  2316. /**
  2317. * cam_soc_util_get_regulator()
  2318. *
  2319. * @brief: Get regulator resource named vdd
  2320. *
  2321. * @dev: Device associated with regulator
  2322. * @reg: Return pointer to be filled with regulator on success
  2323. * @rgltr_name: Name of regulator to get
  2324. *
  2325. * @return: 0 for Success, negative value for failure
  2326. */
  2327. static int cam_soc_util_get_regulator(struct device *dev,
  2328. struct regulator **reg, const char *rgltr_name)
  2329. {
  2330. int rc = 0;
  2331. *reg = cam_wrapper_regulator_get(dev, rgltr_name);
  2332. if (IS_ERR_OR_NULL(*reg)) {
  2333. rc = PTR_ERR(*reg);
  2334. rc = rc ? rc : -EINVAL;
  2335. CAM_ERR(CAM_UTIL, "Regulator %s get failed %d", rgltr_name, rc);
  2336. *reg = NULL;
  2337. }
  2338. return rc;
  2339. }
  2340. int cam_soc_util_regulator_disable(struct regulator *rgltr,
  2341. const char *rgltr_name, uint32_t rgltr_min_volt,
  2342. uint32_t rgltr_max_volt, uint32_t rgltr_op_mode,
  2343. uint32_t rgltr_delay_ms)
  2344. {
  2345. int32_t rc = 0;
  2346. if (!rgltr) {
  2347. CAM_ERR(CAM_UTIL, "Invalid NULL parameter");
  2348. return -EINVAL;
  2349. }
  2350. rc = cam_wrapper_regulator_disable(rgltr);
  2351. if (rc) {
  2352. CAM_ERR(CAM_UTIL, "%s regulator disable failed", rgltr_name);
  2353. return rc;
  2354. }
  2355. if (rgltr_delay_ms > 20)
  2356. msleep(rgltr_delay_ms);
  2357. else if (rgltr_delay_ms)
  2358. usleep_range(rgltr_delay_ms * 1000,
  2359. (rgltr_delay_ms * 1000) + 1000);
  2360. if (cam_wrapper_regulator_count_voltages(rgltr) > 0) {
  2361. cam_wrapper_regulator_set_load(rgltr, 0);
  2362. cam_wrapper_regulator_set_voltage(rgltr, 0, rgltr_max_volt);
  2363. }
  2364. return rc;
  2365. }
  2366. int cam_soc_util_regulator_enable(struct regulator *rgltr,
  2367. const char *rgltr_name,
  2368. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  2369. uint32_t rgltr_op_mode, uint32_t rgltr_delay)
  2370. {
  2371. int32_t rc = 0;
  2372. if (!rgltr) {
  2373. CAM_ERR(CAM_UTIL, "Invalid NULL parameter");
  2374. return -EINVAL;
  2375. }
  2376. if (cam_wrapper_regulator_count_voltages(rgltr) > 0) {
  2377. CAM_DBG(CAM_UTIL, "[%s] voltage min=%d, max=%d",
  2378. rgltr_name, rgltr_min_volt, rgltr_max_volt);
  2379. rc = cam_wrapper_regulator_set_voltage(
  2380. rgltr, rgltr_min_volt, rgltr_max_volt);
  2381. if (rc) {
  2382. CAM_ERR(CAM_UTIL, "%s set voltage failed", rgltr_name);
  2383. return rc;
  2384. }
  2385. rc = cam_wrapper_regulator_set_load(rgltr, rgltr_op_mode);
  2386. if (rc) {
  2387. CAM_ERR(CAM_UTIL, "%s set optimum mode failed",
  2388. rgltr_name);
  2389. return rc;
  2390. }
  2391. }
  2392. rc = cam_wrapper_regulator_enable(rgltr);
  2393. if (rc) {
  2394. CAM_ERR(CAM_UTIL, "%s regulator_enable failed", rgltr_name);
  2395. return rc;
  2396. }
  2397. if (rgltr_delay > 20)
  2398. msleep(rgltr_delay);
  2399. else if (rgltr_delay)
  2400. usleep_range(rgltr_delay * 1000,
  2401. (rgltr_delay * 1000) + 1000);
  2402. return rc;
  2403. }
  2404. int cam_soc_util_select_pinctrl_state(struct cam_hw_soc_info *soc_info,
  2405. int pctrl_idx, bool active)
  2406. {
  2407. int rc = 0;
  2408. struct cam_soc_pinctrl_info *pctrl_info = &soc_info->pinctrl_info;
  2409. if (pctrl_idx >= CAM_SOC_MAX_PINCTRL_MAP) {
  2410. CAM_ERR(CAM_UTIL, "Invalid Map idx: %d max supported: %d",
  2411. pctrl_idx, CAM_SOC_MAX_PINCTRL_MAP);
  2412. return -EINVAL;
  2413. }
  2414. if (pctrl_info->pctrl_state[pctrl_idx].gpio_state_active &&
  2415. active &&
  2416. !pctrl_info->pctrl_state[pctrl_idx].is_active) {
  2417. rc = pinctrl_select_state(pctrl_info->pinctrl,
  2418. pctrl_info->pctrl_state[pctrl_idx].gpio_state_active);
  2419. if (rc)
  2420. CAM_ERR(CAM_UTIL,
  2421. "Pinctrl active state transition failed: rc: %d",
  2422. rc);
  2423. else {
  2424. pctrl_info->pctrl_state[pctrl_idx].is_active = true;
  2425. CAM_DBG(CAM_UTIL, "Pctrl_idx: %d is in active state",
  2426. pctrl_idx);
  2427. }
  2428. }
  2429. if (pctrl_info->pctrl_state[pctrl_idx].gpio_state_suspend &&
  2430. !active &&
  2431. pctrl_info->pctrl_state[pctrl_idx].is_active) {
  2432. rc = pinctrl_select_state(pctrl_info->pinctrl,
  2433. pctrl_info->pctrl_state[pctrl_idx].gpio_state_suspend);
  2434. if (rc)
  2435. CAM_ERR(CAM_UTIL,
  2436. "Pinctrl suspend state transition failed: rc: %d",
  2437. rc);
  2438. else {
  2439. pctrl_info->pctrl_state[pctrl_idx].is_active = false;
  2440. CAM_DBG(CAM_UTIL, "Pctrl_idx: %d is in suspend state",
  2441. pctrl_idx);
  2442. }
  2443. }
  2444. return rc;
  2445. }
  2446. static int cam_soc_util_request_pinctrl(
  2447. struct cam_hw_soc_info *soc_info)
  2448. {
  2449. struct cam_soc_pinctrl_info *device_pctrl = &soc_info->pinctrl_info;
  2450. struct device *dev = soc_info->dev;
  2451. struct device_node *of_node = dev->of_node;
  2452. uint32_t i = 0;
  2453. int rc = 0;
  2454. const char *name;
  2455. uint32_t idx;
  2456. char pctrl_active[50];
  2457. char pctrl_suspend[50];
  2458. int32_t num_of_map_idx = 0;
  2459. int32_t num_of_string = 0;
  2460. device_pctrl->pinctrl = devm_pinctrl_get(dev);
  2461. if (IS_ERR_OR_NULL(device_pctrl->pinctrl)) {
  2462. CAM_DBG(CAM_UTIL, "Pinctrl not available");
  2463. device_pctrl->pinctrl = NULL;
  2464. return 0;
  2465. }
  2466. num_of_map_idx = of_property_count_u32_elems(
  2467. of_node, "pctrl-idx-mapping");
  2468. if (num_of_map_idx <= 0) {
  2469. CAM_ERR(CAM_UTIL,
  2470. "Reading pctrl-idx-mapping failed");
  2471. return -EINVAL;
  2472. }
  2473. num_of_string = of_property_count_strings(
  2474. of_node, "pctrl-map-names");
  2475. if (num_of_string <= 0) {
  2476. CAM_ERR(CAM_UTIL, "no pinctrl-mapping found for: %s",
  2477. soc_info->dev_name);
  2478. device_pctrl->pinctrl = NULL;
  2479. return -EINVAL;
  2480. }
  2481. if (num_of_map_idx != num_of_string) {
  2482. CAM_ERR(CAM_UTIL,
  2483. "Incorrect inputs mapping-idx count: %d mapping-names: %d",
  2484. num_of_map_idx, num_of_string);
  2485. device_pctrl->pinctrl = NULL;
  2486. return -EINVAL;
  2487. }
  2488. if (num_of_map_idx > CAM_SOC_MAX_PINCTRL_MAP) {
  2489. CAM_ERR(CAM_UTIL, "Invalid mapping %u max supported: %d",
  2490. num_of_map_idx, CAM_SOC_MAX_PINCTRL_MAP);
  2491. return -EINVAL;
  2492. }
  2493. for (i = 0; i < num_of_map_idx; i++) {
  2494. of_property_read_u32_index(of_node,
  2495. "pctrl-idx-mapping", i, &idx);
  2496. if (idx >= CAM_SOC_MAX_PINCTRL_MAP) {
  2497. CAM_ERR(CAM_UTIL, "Invalid Index: %d max supported: %d",
  2498. idx, CAM_SOC_MAX_PINCTRL_MAP);
  2499. return -EINVAL;
  2500. }
  2501. rc = of_property_read_string_index(
  2502. of_node, "pctrl-map-names", i, &name);
  2503. if (rc) {
  2504. CAM_ERR(CAM_UTIL,
  2505. "failed to read pinctrl-mapping at %d", i);
  2506. return rc;
  2507. }
  2508. snprintf(pctrl_active, sizeof(pctrl_active),
  2509. "%s%s", name, "_active");
  2510. CAM_DBG(CAM_UTIL, "pctrl_active at index: %d name: %s",
  2511. i, pctrl_active);
  2512. snprintf(pctrl_suspend, sizeof(pctrl_suspend),
  2513. "%s%s", name, "_suspend");
  2514. CAM_DBG(CAM_UTIL, "pctrl_suspend at index: %d name: %s",
  2515. i, pctrl_suspend);
  2516. device_pctrl->pctrl_state[idx].gpio_state_active =
  2517. pinctrl_lookup_state(device_pctrl->pinctrl,
  2518. pctrl_active);
  2519. if (IS_ERR_OR_NULL(
  2520. device_pctrl->pctrl_state[idx].gpio_state_active)) {
  2521. CAM_ERR(CAM_UTIL,
  2522. "Failed to get the active state pinctrl handle");
  2523. device_pctrl->pctrl_state[idx].gpio_state_active =
  2524. NULL;
  2525. return -EINVAL;
  2526. }
  2527. device_pctrl->pctrl_state[idx].gpio_state_suspend =
  2528. pinctrl_lookup_state(device_pctrl->pinctrl,
  2529. pctrl_suspend);
  2530. if (IS_ERR_OR_NULL(
  2531. device_pctrl->pctrl_state[idx].gpio_state_suspend)) {
  2532. CAM_ERR(CAM_UTIL,
  2533. "Failed to get the active state pinctrl handle");
  2534. device_pctrl->pctrl_state[idx].gpio_state_suspend = NULL;
  2535. return -EINVAL;
  2536. }
  2537. }
  2538. return 0;
  2539. }
  2540. static void cam_soc_util_release_pinctrl(struct cam_hw_soc_info *soc_info)
  2541. {
  2542. if (soc_info->pinctrl_info.pinctrl)
  2543. devm_pinctrl_put(soc_info->pinctrl_info.pinctrl);
  2544. }
  2545. static void cam_soc_util_regulator_disable_default(
  2546. struct cam_hw_soc_info *soc_info)
  2547. {
  2548. int j = 0;
  2549. uint32_t num_rgltr = soc_info->num_rgltr;
  2550. for (j = num_rgltr-1; j >= 0; j--) {
  2551. if (soc_info->rgltr_ctrl_support == true) {
  2552. cam_soc_util_regulator_disable(soc_info->rgltr[j],
  2553. soc_info->rgltr_name[j],
  2554. soc_info->rgltr_min_volt[j],
  2555. soc_info->rgltr_max_volt[j],
  2556. soc_info->rgltr_op_mode[j],
  2557. soc_info->rgltr_delay[j]);
  2558. } else {
  2559. if (soc_info->rgltr[j])
  2560. cam_wrapper_regulator_disable(soc_info->rgltr[j]);
  2561. }
  2562. }
  2563. }
  2564. static int cam_soc_util_regulator_enable_default(
  2565. struct cam_hw_soc_info *soc_info)
  2566. {
  2567. int j = 0, rc = 0;
  2568. uint32_t num_rgltr = soc_info->num_rgltr;
  2569. if (num_rgltr > CAM_SOC_MAX_REGULATOR) {
  2570. CAM_ERR(CAM_UTIL,
  2571. "%s has invalid regulator number %d",
  2572. soc_info->dev_name, num_rgltr);
  2573. return -EINVAL;
  2574. }
  2575. for (j = 0; j < num_rgltr; j++) {
  2576. CAM_DBG(CAM_UTIL, "[%s] : start regulator %s enable, rgltr_ctrl_support %d",
  2577. soc_info->dev_name, soc_info->rgltr_name[j], soc_info->rgltr_ctrl_support);
  2578. if (soc_info->rgltr_ctrl_support == true) {
  2579. rc = cam_soc_util_regulator_enable(soc_info->rgltr[j],
  2580. soc_info->rgltr_name[j],
  2581. soc_info->rgltr_min_volt[j],
  2582. soc_info->rgltr_max_volt[j],
  2583. soc_info->rgltr_op_mode[j],
  2584. soc_info->rgltr_delay[j]);
  2585. } else {
  2586. if (soc_info->rgltr[j])
  2587. rc = cam_wrapper_regulator_enable(soc_info->rgltr[j]);
  2588. }
  2589. if (rc) {
  2590. CAM_ERR(CAM_UTIL, "%s enable failed",
  2591. soc_info->rgltr_name[j]);
  2592. goto disable_rgltr;
  2593. }
  2594. }
  2595. return rc;
  2596. disable_rgltr:
  2597. for (j--; j >= 0; j--) {
  2598. if (soc_info->rgltr_ctrl_support == true) {
  2599. cam_soc_util_regulator_disable(soc_info->rgltr[j],
  2600. soc_info->rgltr_name[j],
  2601. soc_info->rgltr_min_volt[j],
  2602. soc_info->rgltr_max_volt[j],
  2603. soc_info->rgltr_op_mode[j],
  2604. soc_info->rgltr_delay[j]);
  2605. } else {
  2606. if (soc_info->rgltr[j])
  2607. cam_wrapper_regulator_disable(soc_info->rgltr[j]);
  2608. }
  2609. }
  2610. return rc;
  2611. }
  2612. static bool cam_soc_util_is_presil_address_space(unsigned long mem_block_start)
  2613. {
  2614. if(mem_block_start >= CAM_SS_START_PRESIL && mem_block_start < CAM_SS_START)
  2615. return true;
  2616. return false;
  2617. }
  2618. #ifndef CONFIG_CAM_PRESIL
  2619. void __iomem * cam_soc_util_get_mem_base(
  2620. unsigned long mem_block_start,
  2621. unsigned long mem_block_size,
  2622. const char *mem_block_name,
  2623. uint32_t reserve_mem)
  2624. {
  2625. void __iomem * mem_base;
  2626. if (reserve_mem) {
  2627. if (!request_mem_region(mem_block_start,
  2628. mem_block_size,
  2629. mem_block_name)) {
  2630. CAM_ERR(CAM_UTIL,
  2631. "Error Mem region request Failed:%s",
  2632. mem_block_name);
  2633. return NULL;
  2634. }
  2635. }
  2636. mem_base = ioremap(mem_block_start, mem_block_size);
  2637. if (!mem_base) {
  2638. CAM_ERR(CAM_UTIL, "get mem base failed");
  2639. }
  2640. return mem_base;
  2641. }
  2642. int cam_soc_util_request_irq(struct device *dev,
  2643. unsigned int irq_line_start,
  2644. irq_handler_t handler,
  2645. unsigned long irqflags,
  2646. const char *irq_name,
  2647. void *irq_data,
  2648. unsigned long mem_block_start)
  2649. {
  2650. int rc;
  2651. rc = devm_request_irq(dev,
  2652. irq_line_start,
  2653. handler,
  2654. IRQF_TRIGGER_RISING,
  2655. irq_name,
  2656. irq_data);
  2657. if (rc) {
  2658. CAM_ERR(CAM_UTIL, "irq request fail rc %d", rc);
  2659. return -EBUSY;
  2660. }
  2661. disable_irq(irq_line_start);
  2662. return rc;
  2663. }
  2664. #else
  2665. void __iomem * cam_soc_util_get_mem_base(
  2666. unsigned long mem_block_start,
  2667. unsigned long mem_block_size,
  2668. const char *mem_block_name,
  2669. uint32_t reserve_mem)
  2670. {
  2671. void __iomem * mem_base;
  2672. if(cam_soc_util_is_presil_address_space(mem_block_start))
  2673. mem_base = (void __iomem *)mem_block_start;
  2674. else {
  2675. if (reserve_mem) {
  2676. if (!request_mem_region(mem_block_start,
  2677. mem_block_size,
  2678. mem_block_name)) {
  2679. CAM_ERR(CAM_UTIL,
  2680. "Error Mem region request Failed:%s",
  2681. mem_block_name);
  2682. return NULL;
  2683. }
  2684. }
  2685. mem_base = ioremap(mem_block_start, mem_block_size);
  2686. }
  2687. if (!mem_base) {
  2688. CAM_ERR(CAM_UTIL, "get mem base failed");
  2689. }
  2690. return mem_base;
  2691. }
  2692. int cam_soc_util_request_irq(struct device *dev,
  2693. unsigned int irq_line_start,
  2694. irq_handler_t handler,
  2695. unsigned long irqflags,
  2696. const char *irq_name,
  2697. void *irq_data,
  2698. unsigned long mem_block_start)
  2699. {
  2700. int rc;
  2701. if(cam_soc_util_is_presil_address_space(mem_block_start)) {
  2702. rc = devm_request_irq(dev,
  2703. irq_line_start,
  2704. handler,
  2705. irqflags,
  2706. irq_name,
  2707. irq_data);
  2708. if (rc) {
  2709. CAM_ERR(CAM_UTIL, "presil irq request fail");
  2710. return -EBUSY;
  2711. }
  2712. disable_irq(irq_line_start);
  2713. rc = !(cam_presil_subscribe_device_irq(irq_line_start,
  2714. handler, irq_data, irq_name));
  2715. CAM_DBG(CAM_PRESIL, "Subscribe presil IRQ: rc=%d NUM=%d Name=%s handler=0x%x",
  2716. rc, irq_line_start, irq_name, handler);
  2717. if (rc) {
  2718. CAM_ERR(CAM_UTIL, "presil irq request fail");
  2719. return -EBUSY;
  2720. }
  2721. } else {
  2722. rc = devm_request_irq(dev,
  2723. irq_line_start,
  2724. handler,
  2725. irqflags,
  2726. irq_name,
  2727. irq_data);
  2728. if (rc) {
  2729. CAM_ERR(CAM_UTIL, "irq request fail");
  2730. return -EBUSY;
  2731. }
  2732. disable_irq(irq_line_start);
  2733. CAM_INFO(CAM_UTIL, "Subscribe for non-presil IRQ success");
  2734. }
  2735. CAM_INFO(CAM_UTIL, "returning IRQ for mem_block_start 0x%0x rc %d",
  2736. mem_block_start, rc);
  2737. return rc;
  2738. }
  2739. #endif
  2740. int cam_soc_util_request_platform_resource(
  2741. struct cam_hw_soc_info *soc_info,
  2742. irq_handler_t handler, void **irq_data)
  2743. {
  2744. int i = 0, rc = 0;
  2745. if (!soc_info || !soc_info->dev) {
  2746. CAM_ERR(CAM_UTIL, "Invalid parameters");
  2747. return -EINVAL;
  2748. }
  2749. if (unlikely(soc_info->irq_count > CAM_SOC_MAX_IRQ_LINES_PER_DEV)) {
  2750. CAM_ERR(CAM_UTIL, "Invalid irq count: %u Max IRQ per device: %d",
  2751. soc_info->irq_count, CAM_SOC_MAX_IRQ_LINES_PER_DEV);
  2752. return -EINVAL;
  2753. }
  2754. for (i = 0; i < soc_info->num_mem_block; i++) {
  2755. soc_info->reg_map[i].mem_base = cam_soc_util_get_mem_base(
  2756. soc_info->mem_block[i]->start,
  2757. resource_size(soc_info->mem_block[i]),
  2758. soc_info->mem_block_name[i],
  2759. soc_info->reserve_mem);
  2760. if (!soc_info->reg_map[i].mem_base) {
  2761. CAM_ERR(CAM_UTIL, "i= %d base NULL", i);
  2762. rc = -ENOMEM;
  2763. goto unmap_base;
  2764. }
  2765. soc_info->reg_map[i].mem_cam_base =
  2766. soc_info->mem_block_cam_base[i];
  2767. soc_info->reg_map[i].size =
  2768. resource_size(soc_info->mem_block[i]);
  2769. soc_info->num_reg_map++;
  2770. }
  2771. for (i = 0; i < soc_info->num_rgltr; i++) {
  2772. if (soc_info->rgltr_name[i] == NULL) {
  2773. CAM_ERR(CAM_UTIL, "can't find regulator name");
  2774. goto put_regulator;
  2775. }
  2776. rc = cam_soc_util_get_regulator(soc_info->dev,
  2777. &soc_info->rgltr[i],
  2778. soc_info->rgltr_name[i]);
  2779. if (rc)
  2780. goto put_regulator;
  2781. }
  2782. for (i = 0; i < soc_info->irq_count; i++) {
  2783. rc = cam_soc_util_request_irq(soc_info->dev, soc_info->irq_num[i],
  2784. handler, IRQF_TRIGGER_RISING, soc_info->irq_name[i],
  2785. irq_data[i], soc_info->mem_block[0]->start);
  2786. if (rc) {
  2787. CAM_ERR(CAM_UTIL, "irq request fail for irq name: %s dev: %s",
  2788. soc_info->irq_name[i], soc_info->dev_name);
  2789. rc = -EBUSY;
  2790. goto put_irq;
  2791. }
  2792. soc_info->irq_data[i] = irq_data[i];
  2793. }
  2794. /* Get Clock */
  2795. for (i = 0; i < soc_info->num_clk; i++) {
  2796. soc_info->clk[i] = cam_wrapper_clk_get(soc_info->dev,
  2797. soc_info->clk_name[i]);
  2798. if (IS_ERR(soc_info->clk[i])) {
  2799. CAM_ERR(CAM_UTIL, "get failed for %s",
  2800. soc_info->clk_name[i]);
  2801. rc = -ENOENT;
  2802. goto put_clk;
  2803. } else if (!soc_info->clk[i]) {
  2804. CAM_DBG(CAM_UTIL, "%s handle is NULL skip get",
  2805. soc_info->clk_name[i]);
  2806. continue;
  2807. }
  2808. /* Create a wrapper entry if this is a shared clock */
  2809. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i)) {
  2810. uint32_t min_level = soc_info->lowest_clk_level;
  2811. CAM_DBG(CAM_UTIL,
  2812. "Dev %s, clk %s, id %d register wrapper entry for shared clk",
  2813. soc_info->dev_name, soc_info->clk_name[i],
  2814. soc_info->clk_id[i]);
  2815. rc = cam_soc_util_clk_wrapper_register_entry(
  2816. soc_info->clk_id[i], soc_info->clk[i],
  2817. (i == soc_info->src_clk_idx) ? true : false,
  2818. soc_info, soc_info->clk_rate[min_level][i],
  2819. soc_info->clk_name[i]);
  2820. if (rc) {
  2821. CAM_ERR(CAM_UTIL,
  2822. "Failed in registering shared clk Dev %s id %d",
  2823. soc_info->dev_name,
  2824. soc_info->clk_id[i]);
  2825. cam_wrapper_clk_put(soc_info->clk[i]);
  2826. soc_info->clk[i] = NULL;
  2827. goto put_clk;
  2828. }
  2829. } else if (i == soc_info->src_clk_idx) {
  2830. rc = cam_soc_util_register_mmrm_client(
  2831. soc_info->clk_id[i], soc_info->clk[i],
  2832. soc_info->is_nrt_dev,
  2833. soc_info, soc_info->clk_name[i],
  2834. &soc_info->mmrm_handle);
  2835. if (rc) {
  2836. CAM_ERR(CAM_UTIL,
  2837. "Failed in register mmrm client Dev %s clk id %d",
  2838. soc_info->dev_name,
  2839. soc_info->clk_id[i]);
  2840. cam_wrapper_clk_put(soc_info->clk[i]);
  2841. soc_info->clk[i] = NULL;
  2842. goto put_clk;
  2843. }
  2844. }
  2845. }
  2846. rc = cam_soc_util_request_pinctrl(soc_info);
  2847. if (rc) {
  2848. CAM_ERR(CAM_UTIL, "Failed in requesting Pinctrl, rc: %d", rc);
  2849. goto put_clk;
  2850. }
  2851. rc = cam_soc_util_request_gpio_table(soc_info, true);
  2852. if (rc) {
  2853. CAM_ERR(CAM_UTIL, "Failed in request gpio table, rc=%d", rc);
  2854. goto put_clk;
  2855. }
  2856. if (soc_info->clk_control_enable)
  2857. cam_soc_util_create_clk_lvl_debugfs(soc_info);
  2858. return rc;
  2859. put_clk:
  2860. if (soc_info->mmrm_handle) {
  2861. cam_soc_util_unregister_mmrm_client(soc_info->mmrm_handle);
  2862. soc_info->mmrm_handle = NULL;
  2863. }
  2864. for (i = i - 1; i >= 0; i--) {
  2865. if (soc_info->clk[i]) {
  2866. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i))
  2867. cam_soc_util_clk_wrapper_unregister_entry(
  2868. soc_info->clk_id[i], soc_info);
  2869. cam_wrapper_clk_put(soc_info->clk[i]);
  2870. soc_info->clk[i] = NULL;
  2871. }
  2872. }
  2873. put_irq:
  2874. if (i == -1)
  2875. i = soc_info->irq_count;
  2876. for (i = i - 1; i >= 0; i--) {
  2877. if (soc_info->irq_num[i] > 0)
  2878. disable_irq(soc_info->irq_num[i]);
  2879. }
  2880. put_regulator:
  2881. if (i == -1)
  2882. i = soc_info->num_rgltr;
  2883. for (i = i - 1; i >= 0; i--) {
  2884. if (soc_info->rgltr[i]) {
  2885. cam_wrapper_regulator_disable(soc_info->rgltr[i]);
  2886. cam_wrapper_regulator_put(soc_info->rgltr[i]);
  2887. soc_info->rgltr[i] = NULL;
  2888. }
  2889. }
  2890. unmap_base:
  2891. if (i == -1)
  2892. i = soc_info->num_reg_map;
  2893. for (i = i - 1; i >= 0; i--) {
  2894. if (soc_info->reserve_mem)
  2895. release_mem_region(soc_info->mem_block[i]->start,
  2896. resource_size(soc_info->mem_block[i]));
  2897. iounmap(soc_info->reg_map[i].mem_base);
  2898. soc_info->reg_map[i].mem_base = NULL;
  2899. soc_info->reg_map[i].size = 0;
  2900. }
  2901. return rc;
  2902. }
  2903. int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info)
  2904. {
  2905. int i;
  2906. bool b_ret = false;
  2907. if (!soc_info || !soc_info->dev) {
  2908. CAM_ERR(CAM_UTIL, "Invalid parameter");
  2909. return -EINVAL;
  2910. }
  2911. if (soc_info->mmrm_handle) {
  2912. cam_soc_util_unregister_mmrm_client(soc_info->mmrm_handle);
  2913. soc_info->mmrm_handle = NULL;
  2914. }
  2915. for (i = soc_info->num_clk - 1; i >= 0; i--) {
  2916. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i))
  2917. cam_soc_util_clk_wrapper_unregister_entry(
  2918. soc_info->clk_id[i], soc_info);
  2919. if (!soc_info->clk[i]) {
  2920. CAM_DBG(CAM_UTIL, "%s handle is NULL skip put",
  2921. soc_info->clk_name[i]);
  2922. continue;
  2923. }
  2924. cam_wrapper_clk_put(soc_info->clk[i]);
  2925. soc_info->clk[i] = NULL;
  2926. }
  2927. for (i = soc_info->num_rgltr - 1; i >= 0; i--) {
  2928. if (soc_info->rgltr[i]) {
  2929. cam_wrapper_regulator_put(soc_info->rgltr[i]);
  2930. soc_info->rgltr[i] = NULL;
  2931. }
  2932. }
  2933. for (i = soc_info->num_reg_map - 1; i >= 0; i--) {
  2934. iounmap(soc_info->reg_map[i].mem_base);
  2935. soc_info->reg_map[i].mem_base = NULL;
  2936. soc_info->reg_map[i].size = 0;
  2937. }
  2938. for (i = soc_info->irq_count; i >= 0; i--) {
  2939. if (soc_info->irq_num[i] > 0) {
  2940. if (cam_presil_mode_enabled()) {
  2941. if (cam_soc_util_is_presil_address_space(
  2942. soc_info->mem_block[0]->start)) {
  2943. b_ret = cam_presil_unsubscribe_device_irq(
  2944. soc_info->irq_line[i]->start);
  2945. CAM_DBG(CAM_PRESIL,
  2946. "UnSubscribe IRQ: Ret=%d NUM=%d Name=%s",
  2947. b_ret, soc_info->irq_line[i]->start,
  2948. soc_info->irq_name[i]);
  2949. }
  2950. }
  2951. disable_irq(soc_info->irq_num[i]);
  2952. }
  2953. }
  2954. cam_soc_util_release_pinctrl(soc_info);
  2955. /* release for gpio */
  2956. cam_soc_util_request_gpio_table(soc_info, false);
  2957. soc_info->dentry = NULL;
  2958. return 0;
  2959. }
  2960. int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info,
  2961. int cesta_client_idx, bool enable_clocks, enum cam_vote_level clk_level,
  2962. bool irq_enable)
  2963. {
  2964. int rc = 0, i;
  2965. if (!soc_info)
  2966. return -EINVAL;
  2967. rc = cam_soc_util_regulator_enable_default(soc_info);
  2968. if (rc) {
  2969. CAM_ERR(CAM_UTIL, "Regulators enable failed");
  2970. return rc;
  2971. }
  2972. if (enable_clocks) {
  2973. rc = cam_soc_util_clk_enable_default(soc_info, cesta_client_idx, clk_level);
  2974. if (rc)
  2975. goto disable_regulator;
  2976. }
  2977. if (irq_enable) {
  2978. for (i = 0; i < soc_info->irq_count; i++) {
  2979. if (soc_info->irq_num[i] < 0) {
  2980. CAM_ERR(CAM_UTIL, "No IRQ line available for irq: %s dev: %s",
  2981. soc_info->irq_name[i], soc_info->dev_name);
  2982. rc = -ENODEV;
  2983. goto disable_irq;
  2984. }
  2985. enable_irq(soc_info->irq_num[i]);
  2986. }
  2987. }
  2988. return rc;
  2989. disable_irq:
  2990. if (irq_enable) {
  2991. for (i = i - 1; i >= 0; i--)
  2992. disable_irq(soc_info->irq_num[i]);
  2993. }
  2994. if (enable_clocks)
  2995. cam_soc_util_clk_disable_default(soc_info, cesta_client_idx);
  2996. disable_regulator:
  2997. cam_soc_util_regulator_disable_default(soc_info);
  2998. return rc;
  2999. }
  3000. int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
  3001. int cesta_client_idx, bool disable_clocks, bool disable_irq)
  3002. {
  3003. int rc = 0;
  3004. if (!soc_info)
  3005. return -EINVAL;
  3006. if (disable_irq)
  3007. rc |= cam_soc_util_irq_disable(soc_info);
  3008. if (disable_clocks)
  3009. cam_soc_util_clk_disable_default(soc_info, cesta_client_idx);
  3010. cam_soc_util_regulator_disable_default(soc_info);
  3011. return rc;
  3012. }
  3013. int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
  3014. uint32_t base_index, uint32_t offset, int size)
  3015. {
  3016. void __iomem *base_addr = NULL;
  3017. CAM_DBG(CAM_UTIL, "base_idx %u size=%d", base_index, size);
  3018. if (!soc_info || base_index >= soc_info->num_reg_map ||
  3019. size <= 0 || (offset + size) >=
  3020. CAM_SOC_GET_REG_MAP_SIZE(soc_info, base_index))
  3021. return -EINVAL;
  3022. base_addr = CAM_SOC_GET_REG_MAP_START(soc_info, base_index);
  3023. /*
  3024. * All error checking already done above,
  3025. * hence ignoring the return value below.
  3026. */
  3027. cam_io_dump(base_addr, offset, size);
  3028. return 0;
  3029. }
  3030. static int cam_soc_util_dump_cont_reg_range(
  3031. struct cam_hw_soc_info *soc_info,
  3032. struct cam_reg_range_read_desc *reg_read, uint32_t base_idx,
  3033. struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
  3034. {
  3035. int i = 0, rc = 0;
  3036. uint32_t write_idx = 0;
  3037. if (!soc_info || !dump_out_buf || !reg_read || !cmd_buf_end) {
  3038. CAM_ERR(CAM_UTIL,
  3039. "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK cmd_buf_end: %pK",
  3040. soc_info, dump_out_buf, reg_read, cmd_buf_end);
  3041. rc = -EINVAL;
  3042. goto end;
  3043. }
  3044. if ((reg_read->num_values) && ((reg_read->num_values > U32_MAX / 2) ||
  3045. (sizeof(uint32_t) > ((U32_MAX -
  3046. sizeof(struct cam_reg_dump_out_buffer) -
  3047. dump_out_buf->bytes_written) /
  3048. (reg_read->num_values * 2))))) {
  3049. CAM_ERR(CAM_UTIL,
  3050. "Integer Overflow bytes_written: [%u] num_values: [%u]",
  3051. dump_out_buf->bytes_written, reg_read->num_values);
  3052. rc = -EOVERFLOW;
  3053. goto end;
  3054. }
  3055. if ((cmd_buf_end - (uintptr_t)dump_out_buf) <=
  3056. (uintptr_t)(sizeof(struct cam_reg_dump_out_buffer)
  3057. - sizeof(uint32_t) + dump_out_buf->bytes_written +
  3058. (reg_read->num_values * 2 * sizeof(uint32_t)))) {
  3059. CAM_ERR(CAM_UTIL,
  3060. "Insufficient space in out buffer num_values: [%d] cmd_buf_end: %pK dump_out_buf: %pK",
  3061. reg_read->num_values, cmd_buf_end,
  3062. (uintptr_t)dump_out_buf);
  3063. rc = -EINVAL;
  3064. goto end;
  3065. }
  3066. write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
  3067. for (i = 0; i < reg_read->num_values; i++) {
  3068. if ((reg_read->offset + (i * sizeof(uint32_t))) >
  3069. (uint32_t)soc_info->reg_map[base_idx].size) {
  3070. CAM_ERR(CAM_UTIL,
  3071. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  3072. (reg_read->offset + (i * sizeof(uint32_t))),
  3073. (uint32_t)soc_info->reg_map[base_idx].size);
  3074. rc = -EINVAL;
  3075. goto end;
  3076. }
  3077. dump_out_buf->dump_data[write_idx++] = reg_read->offset +
  3078. (i * sizeof(uint32_t));
  3079. dump_out_buf->dump_data[write_idx++] =
  3080. cam_soc_util_r(soc_info, base_idx,
  3081. (reg_read->offset + (i * sizeof(uint32_t))));
  3082. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  3083. }
  3084. end:
  3085. return rc;
  3086. }
  3087. static int cam_soc_util_dump_dmi_reg_range(
  3088. struct cam_hw_soc_info *soc_info,
  3089. struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
  3090. struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
  3091. {
  3092. int i = 0, rc = 0;
  3093. uint32_t write_idx = 0;
  3094. if (!soc_info || !dump_out_buf || !dmi_read || !cmd_buf_end) {
  3095. CAM_ERR(CAM_UTIL,
  3096. "Invalid input args soc_info: %pK, dump_out_buffer: %pK",
  3097. soc_info, dump_out_buf);
  3098. rc = -EINVAL;
  3099. goto end;
  3100. }
  3101. if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX ||
  3102. dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) {
  3103. CAM_ERR(CAM_UTIL,
  3104. "Invalid number of requested writes, pre: %d post: %d",
  3105. dmi_read->num_pre_writes, dmi_read->num_post_writes);
  3106. rc = -EINVAL;
  3107. goto end;
  3108. }
  3109. if ((dmi_read->num_pre_writes + dmi_read->dmi_data_read.num_values)
  3110. && ((dmi_read->num_pre_writes > U32_MAX / 2) ||
  3111. (dmi_read->dmi_data_read.num_values > U32_MAX / 2) ||
  3112. ((dmi_read->num_pre_writes * 2) > U32_MAX -
  3113. (dmi_read->dmi_data_read.num_values * 2)) ||
  3114. (sizeof(uint32_t) > ((U32_MAX -
  3115. sizeof(struct cam_reg_dump_out_buffer) -
  3116. dump_out_buf->bytes_written) / ((dmi_read->num_pre_writes +
  3117. dmi_read->dmi_data_read.num_values) * 2))))) {
  3118. CAM_ERR(CAM_UTIL,
  3119. "Integer Overflow bytes_written: [%u] num_pre_writes: [%u] num_values: [%u]",
  3120. dump_out_buf->bytes_written, dmi_read->num_pre_writes,
  3121. dmi_read->dmi_data_read.num_values);
  3122. rc = -EOVERFLOW;
  3123. goto end;
  3124. }
  3125. if ((cmd_buf_end - (uintptr_t)dump_out_buf) <=
  3126. (uintptr_t)(
  3127. sizeof(struct cam_reg_dump_out_buffer) - sizeof(uint32_t) +
  3128. (dump_out_buf->bytes_written +
  3129. (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) +
  3130. (dmi_read->dmi_data_read.num_values * 2 *
  3131. sizeof(uint32_t))))) {
  3132. CAM_ERR(CAM_UTIL,
  3133. "Insufficient space in out buffer num_read_val: [%d] num_write_val: [%d] cmd_buf_end: %pK dump_out_buf: %pK",
  3134. dmi_read->dmi_data_read.num_values,
  3135. dmi_read->num_pre_writes, cmd_buf_end,
  3136. (uintptr_t)dump_out_buf);
  3137. rc = -EINVAL;
  3138. goto end;
  3139. }
  3140. write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
  3141. for (i = 0; i < dmi_read->num_pre_writes; i++) {
  3142. if (dmi_read->pre_read_config[i].offset >
  3143. (uint32_t)soc_info->reg_map[base_idx].size) {
  3144. CAM_ERR(CAM_UTIL,
  3145. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  3146. dmi_read->pre_read_config[i].offset,
  3147. (uint32_t)soc_info->reg_map[base_idx].size);
  3148. rc = -EINVAL;
  3149. goto end;
  3150. }
  3151. cam_soc_util_w_mb(soc_info, base_idx,
  3152. dmi_read->pre_read_config[i].offset,
  3153. dmi_read->pre_read_config[i].value);
  3154. dump_out_buf->dump_data[write_idx++] =
  3155. dmi_read->pre_read_config[i].offset;
  3156. dump_out_buf->dump_data[write_idx++] =
  3157. dmi_read->pre_read_config[i].value;
  3158. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  3159. }
  3160. if (dmi_read->dmi_data_read.offset >
  3161. (uint32_t)soc_info->reg_map[base_idx].size) {
  3162. CAM_ERR(CAM_UTIL,
  3163. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  3164. dmi_read->dmi_data_read.offset,
  3165. (uint32_t)soc_info->reg_map[base_idx].size);
  3166. rc = -EINVAL;
  3167. goto end;
  3168. }
  3169. for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
  3170. dump_out_buf->dump_data[write_idx++] =
  3171. dmi_read->dmi_data_read.offset;
  3172. dump_out_buf->dump_data[write_idx++] =
  3173. cam_soc_util_r_mb(soc_info, base_idx,
  3174. dmi_read->dmi_data_read.offset);
  3175. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  3176. }
  3177. for (i = 0; i < dmi_read->num_post_writes; i++) {
  3178. if (dmi_read->post_read_config[i].offset >
  3179. (uint32_t)soc_info->reg_map[base_idx].size) {
  3180. CAM_ERR(CAM_UTIL,
  3181. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  3182. dmi_read->post_read_config[i].offset,
  3183. (uint32_t)soc_info->reg_map[base_idx].size);
  3184. rc = -EINVAL;
  3185. goto end;
  3186. }
  3187. cam_soc_util_w_mb(soc_info, base_idx,
  3188. dmi_read->post_read_config[i].offset,
  3189. dmi_read->post_read_config[i].value);
  3190. }
  3191. end:
  3192. return rc;
  3193. }
  3194. static int cam_soc_util_dump_dmi_reg_range_user_buf(
  3195. struct cam_hw_soc_info *soc_info,
  3196. struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
  3197. struct cam_hw_soc_dump_args *dump_args)
  3198. {
  3199. int i;
  3200. int rc;
  3201. size_t buf_len = 0;
  3202. uint8_t *dst;
  3203. size_t remain_len;
  3204. uint32_t min_len;
  3205. uint32_t *waddr, *start;
  3206. uintptr_t cpu_addr;
  3207. struct cam_hw_soc_dump_header *hdr;
  3208. if (!soc_info || !dump_args || !dmi_read) {
  3209. CAM_ERR(CAM_UTIL,
  3210. "Invalid input args soc_info: %pK, dump_args: %pK",
  3211. soc_info, dump_args);
  3212. return -EINVAL;
  3213. }
  3214. if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX ||
  3215. dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) {
  3216. CAM_ERR(CAM_UTIL,
  3217. "Invalid number of requested writes, pre: %d post: %d",
  3218. dmi_read->num_pre_writes, dmi_read->num_post_writes);
  3219. return -EINVAL;
  3220. }
  3221. rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len);
  3222. if (rc) {
  3223. CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d",
  3224. dump_args->buf_handle, rc);
  3225. return rc;
  3226. }
  3227. if (buf_len <= dump_args->offset) {
  3228. CAM_WARN(CAM_UTIL, "Dump offset overshoot offset %zu len %zu",
  3229. dump_args->offset, buf_len);
  3230. rc = -ENOSPC;
  3231. goto end;
  3232. }
  3233. remain_len = buf_len - dump_args->offset;
  3234. min_len = (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) +
  3235. (dmi_read->dmi_data_read.num_values * 2 * sizeof(uint32_t)) +
  3236. sizeof(uint32_t);
  3237. if (remain_len < min_len) {
  3238. CAM_WARN(CAM_UTIL,
  3239. "Dump Buffer exhaust read %d write %d remain %zu min %u",
  3240. dmi_read->dmi_data_read.num_values,
  3241. dmi_read->num_pre_writes, remain_len,
  3242. min_len);
  3243. rc = -ENOSPC;
  3244. goto end;
  3245. }
  3246. dst = (uint8_t *)cpu_addr + dump_args->offset;
  3247. hdr = (struct cam_hw_soc_dump_header *)dst;
  3248. memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header));
  3249. scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN,
  3250. "DMI_DUMP:");
  3251. waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header));
  3252. start = waddr;
  3253. hdr->word_size = sizeof(uint32_t);
  3254. *waddr = soc_info->index;
  3255. waddr++;
  3256. for (i = 0; i < dmi_read->num_pre_writes; i++) {
  3257. if (dmi_read->pre_read_config[i].offset >
  3258. (uint32_t)soc_info->reg_map[base_idx].size) {
  3259. CAM_ERR(CAM_UTIL,
  3260. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  3261. dmi_read->pre_read_config[i].offset,
  3262. (uint32_t)soc_info->reg_map[base_idx].size);
  3263. rc = -EINVAL;
  3264. goto end;
  3265. }
  3266. cam_soc_util_w_mb(soc_info, base_idx,
  3267. dmi_read->pre_read_config[i].offset,
  3268. dmi_read->pre_read_config[i].value);
  3269. *waddr++ = dmi_read->pre_read_config[i].offset;
  3270. *waddr++ = dmi_read->pre_read_config[i].value;
  3271. }
  3272. if (dmi_read->dmi_data_read.offset >
  3273. (uint32_t)soc_info->reg_map[base_idx].size) {
  3274. CAM_ERR(CAM_UTIL,
  3275. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  3276. dmi_read->dmi_data_read.offset,
  3277. (uint32_t)soc_info->reg_map[base_idx].size);
  3278. rc = -EINVAL;
  3279. goto end;
  3280. }
  3281. for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
  3282. *waddr++ = dmi_read->dmi_data_read.offset;
  3283. *waddr++ = cam_soc_util_r_mb(soc_info, base_idx,
  3284. dmi_read->dmi_data_read.offset);
  3285. }
  3286. for (i = 0; i < dmi_read->num_post_writes; i++) {
  3287. if (dmi_read->post_read_config[i].offset >
  3288. (uint32_t)soc_info->reg_map[base_idx].size) {
  3289. CAM_ERR(CAM_UTIL,
  3290. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  3291. dmi_read->post_read_config[i].offset,
  3292. (uint32_t)soc_info->reg_map[base_idx].size);
  3293. rc = -EINVAL;
  3294. goto end;
  3295. }
  3296. cam_soc_util_w_mb(soc_info, base_idx,
  3297. dmi_read->post_read_config[i].offset,
  3298. dmi_read->post_read_config[i].value);
  3299. }
  3300. hdr->size = (waddr - start) * hdr->word_size;
  3301. dump_args->offset += hdr->size +
  3302. sizeof(struct cam_hw_soc_dump_header);
  3303. end:
  3304. cam_mem_put_cpu_buf(dump_args->buf_handle);
  3305. return rc;
  3306. }
  3307. static int cam_soc_util_dump_cont_reg_range_user_buf(
  3308. struct cam_hw_soc_info *soc_info,
  3309. struct cam_reg_range_read_desc *reg_read,
  3310. uint32_t base_idx,
  3311. struct cam_hw_soc_dump_args *dump_args)
  3312. {
  3313. int i;
  3314. int rc = 0;
  3315. size_t buf_len;
  3316. uint8_t *dst;
  3317. size_t remain_len;
  3318. uint32_t min_len;
  3319. uint32_t *waddr, *start;
  3320. uintptr_t cpu_addr;
  3321. struct cam_hw_soc_dump_header *hdr;
  3322. if (!soc_info || !dump_args || !reg_read) {
  3323. CAM_ERR(CAM_UTIL,
  3324. "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK",
  3325. soc_info, dump_args, reg_read);
  3326. return -EINVAL;
  3327. }
  3328. rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len);
  3329. if (rc) {
  3330. CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d",
  3331. dump_args->buf_handle, rc);
  3332. return rc;
  3333. }
  3334. if (buf_len <= dump_args->offset) {
  3335. CAM_WARN(CAM_UTIL, "Dump offset overshoot %zu %zu",
  3336. dump_args->offset, buf_len);
  3337. rc = -ENOSPC;
  3338. goto end;
  3339. }
  3340. remain_len = buf_len - dump_args->offset;
  3341. min_len = (reg_read->num_values * 2 * sizeof(uint32_t)) +
  3342. sizeof(struct cam_hw_soc_dump_header) + sizeof(uint32_t);
  3343. if (remain_len < min_len) {
  3344. CAM_WARN(CAM_UTIL,
  3345. "Dump Buffer exhaust read_values %d remain %zu min %u",
  3346. reg_read->num_values,
  3347. remain_len,
  3348. min_len);
  3349. rc = -ENOSPC;
  3350. goto end;
  3351. }
  3352. dst = (uint8_t *)cpu_addr + dump_args->offset;
  3353. hdr = (struct cam_hw_soc_dump_header *)dst;
  3354. memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header));
  3355. scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN, "%s_REG:",
  3356. soc_info->dev_name);
  3357. waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header));
  3358. start = waddr;
  3359. hdr->word_size = sizeof(uint32_t);
  3360. *waddr = soc_info->index;
  3361. waddr++;
  3362. for (i = 0; i < reg_read->num_values; i++) {
  3363. if ((reg_read->offset + (i * sizeof(uint32_t))) >
  3364. (uint32_t)soc_info->reg_map[base_idx].size) {
  3365. CAM_ERR(CAM_UTIL,
  3366. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  3367. (reg_read->offset + (i * sizeof(uint32_t))),
  3368. (uint32_t)soc_info->reg_map[base_idx].size);
  3369. rc = -EINVAL;
  3370. goto end;
  3371. }
  3372. waddr[0] = reg_read->offset + (i * sizeof(uint32_t));
  3373. waddr[1] = cam_soc_util_r(soc_info, base_idx,
  3374. (reg_read->offset + (i * sizeof(uint32_t))));
  3375. waddr += 2;
  3376. }
  3377. hdr->size = (waddr - start) * hdr->word_size;
  3378. dump_args->offset += hdr->size +
  3379. sizeof(struct cam_hw_soc_dump_header);
  3380. end:
  3381. cam_mem_put_cpu_buf(dump_args->buf_handle);
  3382. return rc;
  3383. }
  3384. static int cam_soc_util_user_reg_dump(
  3385. struct cam_reg_dump_desc *reg_dump_desc,
  3386. struct cam_hw_soc_dump_args *dump_args,
  3387. struct cam_hw_soc_info *soc_info,
  3388. uint32_t reg_base_idx)
  3389. {
  3390. int rc = 0;
  3391. int i;
  3392. struct cam_reg_read_info *reg_read_info = NULL;
  3393. if (!dump_args || !reg_dump_desc || !soc_info) {
  3394. CAM_ERR(CAM_UTIL,
  3395. "Invalid input parameters %pK %pK %pK",
  3396. dump_args, reg_dump_desc, soc_info);
  3397. return -EINVAL;
  3398. }
  3399. for (i = 0; i < reg_dump_desc->num_read_range; i++) {
  3400. reg_read_info = &reg_dump_desc->read_range[i];
  3401. if (reg_read_info->type ==
  3402. CAM_REG_DUMP_READ_TYPE_CONT_RANGE) {
  3403. rc = cam_soc_util_dump_cont_reg_range_user_buf(
  3404. soc_info,
  3405. &reg_read_info->reg_read,
  3406. reg_base_idx,
  3407. dump_args);
  3408. } else if (reg_read_info->type ==
  3409. CAM_REG_DUMP_READ_TYPE_DMI) {
  3410. rc = cam_soc_util_dump_dmi_reg_range_user_buf(
  3411. soc_info,
  3412. &reg_read_info->dmi_read,
  3413. reg_base_idx,
  3414. dump_args);
  3415. } else {
  3416. CAM_ERR(CAM_UTIL,
  3417. "Invalid Reg dump read type: %d",
  3418. reg_read_info->type);
  3419. rc = -EINVAL;
  3420. goto end;
  3421. }
  3422. if (rc) {
  3423. CAM_ERR(CAM_UTIL,
  3424. "Reg range read failed rc: %d reg_base_idx: %d",
  3425. rc, reg_base_idx);
  3426. goto end;
  3427. }
  3428. }
  3429. end:
  3430. return rc;
  3431. }
  3432. int cam_soc_util_reg_dump_to_cmd_buf(void *ctx,
  3433. struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id,
  3434. cam_soc_util_regspace_data_cb reg_data_cb,
  3435. struct cam_hw_soc_dump_args *soc_dump_args,
  3436. bool user_triggered_dump)
  3437. {
  3438. int rc = 0, i, j;
  3439. uintptr_t cpu_addr = 0;
  3440. uintptr_t cmd_buf_start = 0;
  3441. uintptr_t cmd_in_data_end = 0;
  3442. uintptr_t cmd_buf_end = 0;
  3443. uint32_t reg_base_type = 0;
  3444. size_t buf_size = 0, remain_len = 0;
  3445. struct cam_reg_dump_input_info *reg_input_info = NULL;
  3446. struct cam_reg_dump_desc *reg_dump_desc = NULL;
  3447. struct cam_reg_dump_out_buffer *dump_out_buf = NULL;
  3448. struct cam_reg_read_info *reg_read_info = NULL;
  3449. struct cam_hw_soc_info *soc_info;
  3450. uint32_t reg_base_idx = 0;
  3451. if (!ctx || !cmd_desc || !reg_data_cb) {
  3452. CAM_ERR(CAM_UTIL, "Invalid args to reg dump [%pK] [%pK]",
  3453. cmd_desc, reg_data_cb);
  3454. return -EINVAL;
  3455. }
  3456. if (!cmd_desc->length || !cmd_desc->size) {
  3457. CAM_ERR(CAM_UTIL, "Invalid cmd buf size %d %d",
  3458. cmd_desc->length, cmd_desc->size);
  3459. return -EINVAL;
  3460. }
  3461. rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, &cpu_addr, &buf_size);
  3462. if (rc || !cpu_addr || (buf_size == 0)) {
  3463. CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK",
  3464. rc, (void *)cpu_addr);
  3465. if (rc)
  3466. return rc;
  3467. goto end;
  3468. }
  3469. CAM_DBG(CAM_UTIL, "Get cpu buf success req_id: %llu buf_size: %zu",
  3470. req_id, buf_size);
  3471. if ((buf_size < sizeof(uint32_t)) ||
  3472. ((size_t)cmd_desc->offset > (buf_size - sizeof(uint32_t)))) {
  3473. CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu",
  3474. (size_t)cmd_desc->offset);
  3475. rc = -EINVAL;
  3476. goto end;
  3477. }
  3478. remain_len = buf_size - (size_t)cmd_desc->offset;
  3479. if ((remain_len < (size_t)cmd_desc->size) || (cmd_desc->size <
  3480. cmd_desc->length)) {
  3481. CAM_ERR(CAM_UTIL,
  3482. "Invalid params for cmd buf len: %zu size: %zu remain_len: %zu",
  3483. (size_t)cmd_desc->length, (size_t)cmd_desc->length,
  3484. remain_len);
  3485. rc = -EINVAL;
  3486. goto end;
  3487. }
  3488. cmd_buf_start = cpu_addr + (uintptr_t)cmd_desc->offset;
  3489. cmd_in_data_end = cmd_buf_start + (uintptr_t)cmd_desc->length;
  3490. cmd_buf_end = cmd_buf_start + (uintptr_t)cmd_desc->size;
  3491. if ((cmd_buf_end <= cmd_buf_start) ||
  3492. (cmd_in_data_end <= cmd_buf_start)) {
  3493. CAM_ERR(CAM_UTIL,
  3494. "Invalid length or size for cmd buf: [%zu] [%zu]",
  3495. (size_t)cmd_desc->length, (size_t)cmd_desc->size);
  3496. rc = -EINVAL;
  3497. goto end;
  3498. }
  3499. CAM_DBG(CAM_UTIL,
  3500. "Buffer params start [%pK] input_end [%pK] buf_end [%pK]",
  3501. cmd_buf_start, cmd_in_data_end, cmd_buf_end);
  3502. reg_input_info = (struct cam_reg_dump_input_info *) cmd_buf_start;
  3503. if ((reg_input_info->num_dump_sets > 1) && (sizeof(uint32_t) >
  3504. ((U32_MAX - sizeof(struct cam_reg_dump_input_info)) /
  3505. (reg_input_info->num_dump_sets - 1)))) {
  3506. CAM_ERR(CAM_UTIL,
  3507. "Integer Overflow req_id: [%llu] num_dump_sets: [%u]",
  3508. req_id, reg_input_info->num_dump_sets);
  3509. rc = -EOVERFLOW;
  3510. goto end;
  3511. }
  3512. if ((!reg_input_info->num_dump_sets) ||
  3513. ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t)
  3514. (sizeof(struct cam_reg_dump_input_info) +
  3515. ((reg_input_info->num_dump_sets - 1) * sizeof(uint32_t))))) {
  3516. CAM_ERR(CAM_UTIL,
  3517. "Invalid number of dump sets, req_id: [%llu] num_dump_sets: [%u]",
  3518. req_id, reg_input_info->num_dump_sets);
  3519. rc = -EINVAL;
  3520. goto end;
  3521. }
  3522. CAM_DBG(CAM_UTIL,
  3523. "reg_input_info req_id: %llu ctx %pK num_dump_sets: %d",
  3524. req_id, ctx, reg_input_info->num_dump_sets);
  3525. for (i = 0; i < reg_input_info->num_dump_sets; i++) {
  3526. if ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t)
  3527. reg_input_info->dump_set_offsets[i]) {
  3528. CAM_ERR(CAM_UTIL,
  3529. "Invalid dump set offset: [%pK], cmd_buf_start: [%pK] cmd_in_data_end: [%pK]",
  3530. (uintptr_t)reg_input_info->dump_set_offsets[i],
  3531. cmd_buf_start, cmd_in_data_end);
  3532. rc = -EINVAL;
  3533. goto end;
  3534. }
  3535. reg_dump_desc = (struct cam_reg_dump_desc *)
  3536. (cmd_buf_start +
  3537. (uintptr_t)reg_input_info->dump_set_offsets[i]);
  3538. if ((reg_dump_desc->num_read_range > 1) &&
  3539. (sizeof(struct cam_reg_read_info) > ((U32_MAX -
  3540. sizeof(struct cam_reg_dump_desc)) /
  3541. (reg_dump_desc->num_read_range - 1)))) {
  3542. CAM_ERR(CAM_UTIL,
  3543. "Integer Overflow req_id: [%llu] num_read_range: [%u]",
  3544. req_id, reg_dump_desc->num_read_range);
  3545. rc = -EOVERFLOW;
  3546. goto end;
  3547. }
  3548. if ((!reg_dump_desc->num_read_range) ||
  3549. ((cmd_in_data_end - (uintptr_t)reg_dump_desc) <=
  3550. (uintptr_t)(sizeof(struct cam_reg_dump_desc) +
  3551. ((reg_dump_desc->num_read_range - 1) *
  3552. sizeof(struct cam_reg_read_info))))) {
  3553. CAM_ERR(CAM_UTIL,
  3554. "Invalid number of read ranges, req_id: [%llu] num_read_range: [%d]",
  3555. req_id, reg_dump_desc->num_read_range);
  3556. rc = -EINVAL;
  3557. goto end;
  3558. }
  3559. if ((cmd_buf_end - cmd_buf_start) <= (uintptr_t)
  3560. (reg_dump_desc->dump_buffer_offset +
  3561. sizeof(struct cam_reg_dump_out_buffer))) {
  3562. CAM_ERR(CAM_UTIL,
  3563. "Invalid out buffer offset: [%pK], cmd_buf_start: [%pK] cmd_buf_end: [%pK]",
  3564. (uintptr_t)reg_dump_desc->dump_buffer_offset,
  3565. cmd_buf_start, cmd_buf_end);
  3566. rc = -EINVAL;
  3567. goto end;
  3568. }
  3569. reg_base_type = reg_dump_desc->reg_base_type;
  3570. if (reg_base_type == 0 || reg_base_type >
  3571. CAM_REG_DUMP_BASE_TYPE_SFE_RIGHT) {
  3572. CAM_ERR(CAM_UTIL,
  3573. "Invalid Reg dump base type: %d",
  3574. reg_base_type);
  3575. rc = -EINVAL;
  3576. goto end;
  3577. }
  3578. rc = reg_data_cb(reg_base_type, ctx, &soc_info, &reg_base_idx);
  3579. if (rc || !soc_info) {
  3580. CAM_ERR(CAM_UTIL,
  3581. "Reg space data callback failed rc: %d soc_info: [%pK]",
  3582. rc, soc_info);
  3583. rc = -EINVAL;
  3584. goto end;
  3585. }
  3586. if (reg_base_idx > soc_info->num_reg_map) {
  3587. CAM_ERR(CAM_UTIL,
  3588. "Invalid reg base idx: %d num reg map: %d",
  3589. reg_base_idx, soc_info->num_reg_map);
  3590. rc = -EINVAL;
  3591. goto end;
  3592. }
  3593. CAM_DBG(CAM_UTIL,
  3594. "Reg data callback success req_id: %llu base_type: %d base_idx: %d num_read_range: %d",
  3595. req_id, reg_base_type, reg_base_idx,
  3596. reg_dump_desc->num_read_range);
  3597. /* If the dump request is triggered by user space
  3598. * buffer will be different from the buffer which is received
  3599. * in init packet. In this case, dump the data to the
  3600. * user provided buffer and exit.
  3601. */
  3602. if (user_triggered_dump) {
  3603. rc = cam_soc_util_user_reg_dump(reg_dump_desc,
  3604. soc_dump_args, soc_info, reg_base_idx);
  3605. CAM_INFO(CAM_UTIL,
  3606. "%s reg_base_idx %d dumped offset %u",
  3607. soc_info->dev_name, reg_base_idx,
  3608. soc_dump_args->offset);
  3609. goto end;
  3610. }
  3611. /* Below code is executed when data is dumped to the
  3612. * out buffer received in init packet
  3613. */
  3614. dump_out_buf = (struct cam_reg_dump_out_buffer *)
  3615. (cmd_buf_start +
  3616. (uintptr_t)reg_dump_desc->dump_buffer_offset);
  3617. dump_out_buf->req_id = req_id;
  3618. dump_out_buf->bytes_written = 0;
  3619. for (j = 0; j < reg_dump_desc->num_read_range; j++) {
  3620. CAM_DBG(CAM_UTIL,
  3621. "Number of bytes written to cmd buffer: %u req_id: %llu",
  3622. dump_out_buf->bytes_written, req_id);
  3623. reg_read_info = &reg_dump_desc->read_range[j];
  3624. if (reg_read_info->type ==
  3625. CAM_REG_DUMP_READ_TYPE_CONT_RANGE) {
  3626. rc = cam_soc_util_dump_cont_reg_range(soc_info,
  3627. &reg_read_info->reg_read, reg_base_idx,
  3628. dump_out_buf, cmd_buf_end);
  3629. } else if (reg_read_info->type ==
  3630. CAM_REG_DUMP_READ_TYPE_DMI) {
  3631. rc = cam_soc_util_dump_dmi_reg_range(soc_info,
  3632. &reg_read_info->dmi_read, reg_base_idx,
  3633. dump_out_buf, cmd_buf_end);
  3634. } else {
  3635. CAM_ERR(CAM_UTIL,
  3636. "Invalid Reg dump read type: %d",
  3637. reg_read_info->type);
  3638. rc = -EINVAL;
  3639. goto end;
  3640. }
  3641. if (rc) {
  3642. CAM_ERR(CAM_UTIL,
  3643. "Reg range read failed rc: %d reg_base_idx: %d dump_out_buf: %pK",
  3644. rc, reg_base_idx, dump_out_buf);
  3645. goto end;
  3646. }
  3647. }
  3648. }
  3649. end:
  3650. cam_mem_put_cpu_buf(cmd_desc->mem_handle);
  3651. return rc;
  3652. }
  3653. /**
  3654. * cam_soc_util_print_clk_freq()
  3655. *
  3656. * @brief: This function gets the clk rates for each clk from clk
  3657. * driver and prints in log
  3658. *
  3659. * @soc_info: Device soc struct to be populated
  3660. *
  3661. * @return: success or failure
  3662. */
  3663. int cam_soc_util_print_clk_freq(struct cam_hw_soc_info *soc_info)
  3664. {
  3665. int i;
  3666. unsigned long clk_rate = 0;
  3667. if (!soc_info) {
  3668. CAM_ERR(CAM_UTIL, "Invalid soc info");
  3669. return -EINVAL;
  3670. }
  3671. if ((soc_info->num_clk == 0) ||
  3672. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  3673. CAM_ERR(CAM_UTIL, "[%s] Invalid number of clock %d",
  3674. soc_info->dev_name, soc_info->num_clk);
  3675. return -EINVAL;
  3676. }
  3677. for (i = 0; i < soc_info->num_clk; i++) {
  3678. clk_rate = cam_wrapper_clk_get_rate(soc_info->clk[i]);
  3679. CAM_INFO(CAM_UTIL,
  3680. "[%s] idx = %d clk name = %s clk_rate=%lld",
  3681. soc_info->dev_name, i, soc_info->clk_name[i],
  3682. clk_rate);
  3683. }
  3684. return 0;
  3685. }
  3686. inline unsigned long cam_soc_util_get_applied_src_clk(
  3687. struct cam_hw_soc_info *soc_info, bool is_max)
  3688. {
  3689. unsigned long clk_rate;
  3690. /*
  3691. * For CRMC type, exa - ife, csid, cphy
  3692. * final clk = max(hw_client_0, hw_client_1, hw_client_2, sw_client)
  3693. * For CRMB type, exa - camnoc axi
  3694. * final clk = max(hw_client_0 + hw_client_1 + hw_client_2, sw_client)
  3695. */
  3696. if (is_max) {
  3697. clk_rate = max(soc_info->applied_src_clk_rates.hw_client[0].high,
  3698. soc_info->applied_src_clk_rates.hw_client[1].high);
  3699. clk_rate = max(clk_rate, soc_info->applied_src_clk_rates.hw_client[2].high);
  3700. clk_rate = max(clk_rate, soc_info->applied_src_clk_rates.sw_client);
  3701. } else {
  3702. clk_rate = max((soc_info->applied_src_clk_rates.hw_client[0].high +
  3703. soc_info->applied_src_clk_rates.hw_client[1].high +
  3704. soc_info->applied_src_clk_rates.hw_client[2].high),
  3705. soc_info->applied_src_clk_rates.sw_client);
  3706. }
  3707. return clk_rate;
  3708. }
  3709. int cam_soc_util_regulators_enabled(struct cam_hw_soc_info *soc_info)
  3710. {
  3711. int j = 0, rc = 0;
  3712. int enabled_cnt = 0;
  3713. for (j = 0; j < soc_info->num_rgltr; j++) {
  3714. if (soc_info->rgltr[j]) {
  3715. rc = cam_wrapper_regulator_is_enabled(soc_info->rgltr[j]);
  3716. if (rc < 0) {
  3717. CAM_ERR(CAM_UTIL, "%s regulator_is_enabled failed",
  3718. soc_info->rgltr_name[j]);
  3719. } else if (rc > 0) {
  3720. CAM_DBG(CAM_UTIL, "%s regulator enabled",
  3721. soc_info->rgltr_name[j]);
  3722. enabled_cnt++;
  3723. } else {
  3724. CAM_DBG(CAM_UTIL, "%s regulator is disabled",
  3725. soc_info->rgltr_name[j]);
  3726. }
  3727. }
  3728. }
  3729. return enabled_cnt;
  3730. }