dsi_ctrl_hw_cmn.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/delay.h>
  6. #include <linux/iopoll.h>
  7. #include "dsi_catalog.h"
  8. #include "dsi_ctrl_hw.h"
  9. #include "dsi_ctrl_reg.h"
  10. #include "dsi_hw.h"
  11. #include "dsi_panel.h"
  12. #include "dsi_catalog.h"
  13. #include "sde_dbg.h"
  14. #include "sde_dsc_helper.h"
  15. #include "sde_vdc_helper.h"
  16. #define MMSS_MISC_CLAMP_REG_OFF 0x0014
  17. #define DSI_CTRL_DYNAMIC_FORCE_ON (0x23F|BIT(8)|BIT(9)|BIT(11)|BIT(21))
  18. #define DSI_CTRL_CMD_MISR_ENABLE BIT(28)
  19. #define DSI_CTRL_VIDEO_MISR_ENABLE BIT(16)
  20. #define DSI_CTRL_DMA_LINK_SEL (BIT(12)|BIT(13))
  21. #define DSI_CTRL_MDP0_LINK_SEL (BIT(20)|BIT(22))
  22. static bool dsi_dsc_compression_enabled(struct dsi_mode_info *mode)
  23. {
  24. return (mode->dsc_enabled && mode->dsc);
  25. }
  26. static bool dsi_vdc_compression_enabled(struct dsi_mode_info *mode)
  27. {
  28. return (mode->vdc_enabled && mode->vdc);
  29. }
  30. static bool dsi_compression_enabled(struct dsi_mode_info *mode)
  31. {
  32. return (dsi_dsc_compression_enabled(mode) ||
  33. dsi_vdc_compression_enabled(mode));
  34. }
  35. /* Unsupported formats default to RGB888 */
  36. static const u8 cmd_mode_format_map[DSI_PIXEL_FORMAT_MAX] = {
  37. 0x6, 0x7, 0x8, 0x8, 0x0, 0x3, 0x4 };
  38. static const u8 video_mode_format_map[DSI_PIXEL_FORMAT_MAX] = {
  39. 0x0, 0x1, 0x2, 0x3, 0x3, 0x3, 0x3 };
  40. /**
  41. * dsi_split_link_setup() - setup dsi split link configurations
  42. * @ctrl: Pointer to the controller host hardware.
  43. * @cfg: DSI host configuration that is common to both video and
  44. * command modes.
  45. */
  46. static void dsi_split_link_setup(struct dsi_ctrl_hw *ctrl,
  47. struct dsi_host_common_cfg *cfg)
  48. {
  49. u32 reg;
  50. if (!cfg->split_link.enabled)
  51. return;
  52. reg = DSI_R32(ctrl, DSI_SPLIT_LINK);
  53. /* DMA_LINK_SEL */
  54. reg &= ~(0x7 << 12);
  55. reg |= DSI_CTRL_DMA_LINK_SEL;
  56. /* MDP0_LINK_SEL */
  57. reg &= ~(0x7 << 20);
  58. reg |= DSI_CTRL_MDP0_LINK_SEL;
  59. /* COMMAND_INPUT_SWAP|VIDEO_INPUT_SWAP */
  60. if (cfg->split_link.sublink_swap) {
  61. if (cfg->split_link.panel_mode == DSI_OP_CMD_MODE)
  62. reg |= BIT(8);
  63. else
  64. reg |= BIT(4);
  65. }
  66. /* EN */
  67. reg |= 0x1;
  68. /* DSI_SPLIT_LINK */
  69. DSI_W32(ctrl, DSI_SPLIT_LINK, reg);
  70. wmb(); /* make sure split link is asserted */
  71. }
  72. /**
  73. * dsi_setup_trigger_controls() - setup dsi trigger configurations
  74. * @ctrl: Pointer to the controller host hardware.
  75. * @cfg: DSI host configuration that is common to both video and
  76. * command modes.
  77. */
  78. static void dsi_setup_trigger_controls(struct dsi_ctrl_hw *ctrl,
  79. struct dsi_host_common_cfg *cfg)
  80. {
  81. u32 reg = 0;
  82. const u8 trigger_map[DSI_TRIGGER_MAX] = {
  83. 0x0, 0x2, 0x1, 0x4, 0x5, 0x6 };
  84. reg |= (cfg->te_mode == DSI_TE_ON_EXT_PIN) ? BIT(31) : 0;
  85. reg |= (trigger_map[cfg->dma_cmd_trigger] & 0x7);
  86. reg |= (trigger_map[cfg->mdp_cmd_trigger] & 0x7) << 4;
  87. DSI_W32(ctrl, DSI_TRIG_CTRL, reg);
  88. }
  89. /**
  90. * dsi_ctrl_hw_cmn_host_setup() - setup dsi host configuration
  91. * @ctrl: Pointer to the controller host hardware.
  92. * @cfg: DSI host configuration that is common to both video and
  93. * command modes.
  94. */
  95. void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,
  96. struct dsi_host_common_cfg *cfg)
  97. {
  98. u32 reg_value = 0;
  99. dsi_setup_trigger_controls(ctrl, cfg);
  100. dsi_split_link_setup(ctrl, cfg);
  101. /* Setup clocking timing controls */
  102. reg_value = ((cfg->t_clk_post & 0x3F) << 8);
  103. reg_value |= (cfg->t_clk_pre & 0x3F);
  104. DSI_W32(ctrl, DSI_CLKOUT_TIMING_CTRL, reg_value);
  105. /* EOT packet control */
  106. reg_value = cfg->append_tx_eot ? 1 : 0;
  107. reg_value |= (cfg->ignore_rx_eot ? (1 << 4) : 0);
  108. DSI_W32(ctrl, DSI_EOT_PACKET_CTRL, reg_value);
  109. /* Turn on dsi clocks */
  110. DSI_W32(ctrl, DSI_CLK_CTRL, 0x23F);
  111. /* Setup DSI control register */
  112. reg_value = DSI_R32(ctrl, DSI_CTRL);
  113. reg_value |= (cfg->en_crc_check ? BIT(24) : 0);
  114. reg_value |= (cfg->en_ecc_check ? BIT(20) : 0);
  115. reg_value |= BIT(8); /* Clock lane */
  116. reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_3) ? BIT(7) : 0);
  117. reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_2) ? BIT(6) : 0);
  118. reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_1) ? BIT(5) : 0);
  119. reg_value |= ((cfg->data_lanes & DSI_DATA_LANE_0) ? BIT(4) : 0);
  120. DSI_W32(ctrl, DSI_CTRL, reg_value);
  121. if (cfg->phy_type == DSI_PHY_TYPE_CPHY)
  122. DSI_W32(ctrl, DSI_CPHY_MODE_CTRL, BIT(0));
  123. if (ctrl->phy_isolation_enabled)
  124. DSI_W32(ctrl, DSI_DEBUG_CTRL, BIT(28));
  125. DSI_CTRL_HW_DBG(ctrl, "Host configuration complete\n");
  126. }
  127. /**
  128. * ulps_request() - request ulps entry for specified lanes
  129. * @ctrl: Pointer to the controller host hardware.
  130. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  131. * to enter ULPS.
  132. *
  133. * Caller should check if lanes are in ULPS mode by calling
  134. * get_lanes_in_ulps() operation.
  135. */
  136. void dsi_ctrl_hw_cmn_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes)
  137. {
  138. u32 reg = 0;
  139. reg = DSI_R32(ctrl, DSI_LANE_CTRL);
  140. if (lanes & DSI_CLOCK_LANE)
  141. reg |= BIT(4);
  142. if (lanes & DSI_DATA_LANE_0)
  143. reg |= BIT(0);
  144. if (lanes & DSI_DATA_LANE_1)
  145. reg |= BIT(1);
  146. if (lanes & DSI_DATA_LANE_2)
  147. reg |= BIT(2);
  148. if (lanes & DSI_DATA_LANE_3)
  149. reg |= BIT(3);
  150. /*
  151. * ULPS entry request. Wait for short time to make sure
  152. * that the lanes enter ULPS. Recommended as per HPG.
  153. */
  154. DSI_W32(ctrl, DSI_LANE_CTRL, reg);
  155. usleep_range(100, 110);
  156. DSI_CTRL_HW_DBG(ctrl, "ULPS requested for lanes 0x%x\n", lanes);
  157. }
  158. /**
  159. * ulps_exit() - exit ULPS on specified lanes
  160. * @ctrl: Pointer to the controller host hardware.
  161. * @lanes: ORed list of lanes (enum dsi_data_lanes) which need
  162. * to exit ULPS.
  163. *
  164. * Caller should check if lanes are in active mode by calling
  165. * get_lanes_in_ulps() operation.
  166. */
  167. void dsi_ctrl_hw_cmn_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes)
  168. {
  169. u32 reg = 0;
  170. u32 prev_reg = 0;
  171. prev_reg = DSI_R32(ctrl, DSI_LANE_CTRL);
  172. prev_reg &= BIT(24);
  173. if (lanes & DSI_CLOCK_LANE)
  174. reg |= BIT(12);
  175. if (lanes & DSI_DATA_LANE_0)
  176. reg |= BIT(8);
  177. if (lanes & DSI_DATA_LANE_1)
  178. reg |= BIT(9);
  179. if (lanes & DSI_DATA_LANE_2)
  180. reg |= BIT(10);
  181. if (lanes & DSI_DATA_LANE_3)
  182. reg |= BIT(11);
  183. /*
  184. * ULPS Exit Request
  185. * Hardware requirement is to wait for at least 1ms
  186. */
  187. DSI_W32(ctrl, DSI_LANE_CTRL, reg | prev_reg);
  188. usleep_range(1000, 1010);
  189. /*
  190. * Sometimes when exiting ULPS, it is possible that some DSI
  191. * lanes are not in the stop state which could lead to DSI
  192. * commands not going through. To avoid this, force the lanes
  193. * to be in stop state.
  194. */
  195. DSI_W32(ctrl, DSI_LANE_CTRL, (reg << 8) | prev_reg);
  196. wmb(); /* ensure lanes are put to stop state */
  197. DSI_W32(ctrl, DSI_LANE_CTRL, 0x0 | prev_reg);
  198. wmb(); /* ensure lanes are put to stop state */
  199. DSI_CTRL_HW_DBG(ctrl, "ULPS exit request for lanes=0x%x\n", lanes);
  200. }
  201. /**
  202. * get_lanes_in_ulps() - returns the list of lanes in ULPS mode
  203. * @ctrl: Pointer to the controller host hardware.
  204. *
  205. * Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS
  206. * state. If 0 is returned, all the lanes are active.
  207. *
  208. * Return: List of lanes in ULPS state.
  209. */
  210. u32 dsi_ctrl_hw_cmn_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl)
  211. {
  212. u32 reg = 0;
  213. u32 lanes = 0;
  214. reg = DSI_R32(ctrl, DSI_LANE_STATUS);
  215. if (!(reg & BIT(8)))
  216. lanes |= DSI_DATA_LANE_0;
  217. if (!(reg & BIT(9)))
  218. lanes |= DSI_DATA_LANE_1;
  219. if (!(reg & BIT(10)))
  220. lanes |= DSI_DATA_LANE_2;
  221. if (!(reg & BIT(11)))
  222. lanes |= DSI_DATA_LANE_3;
  223. if (!(reg & BIT(12)))
  224. lanes |= DSI_CLOCK_LANE;
  225. DSI_CTRL_HW_DBG(ctrl, "lanes in ulps = 0x%x\n", lanes);
  226. return lanes;
  227. }
  228. /**
  229. * phy_sw_reset() - perform a soft reset on the PHY.
  230. * @ctrl: Pointer to the controller host hardware.
  231. */
  232. void dsi_ctrl_hw_cmn_phy_sw_reset(struct dsi_ctrl_hw *ctrl)
  233. {
  234. DSI_W32(ctrl, DSI_PHY_SW_RESET, BIT(24)|BIT(0));
  235. wmb(); /* make sure reset is asserted */
  236. udelay(1000);
  237. DSI_W32(ctrl, DSI_PHY_SW_RESET, 0x0);
  238. wmb(); /* ensure reset is cleared before waiting */
  239. udelay(100);
  240. DSI_CTRL_HW_DBG(ctrl, "phy sw reset done\n");
  241. }
  242. /**
  243. * soft_reset() - perform a soft reset on DSI controller
  244. * @ctrl: Pointer to the controller host hardware.
  245. *
  246. * The video, command and controller engines will be disabled before the
  247. * reset is triggered and re-enabled after the reset is complete.
  248. *
  249. * If the reset is done while MDP timing engine is turned on, the video
  250. * enigne should be re-enabled only during the vertical blanking time.
  251. */
  252. void dsi_ctrl_hw_cmn_soft_reset(struct dsi_ctrl_hw *ctrl)
  253. {
  254. u32 reg = 0;
  255. u32 reg_ctrl = 0;
  256. /* Clear DSI_EN, VIDEO_MODE_EN, CMD_MODE_EN */
  257. reg_ctrl = DSI_R32(ctrl, DSI_CTRL);
  258. DSI_W32(ctrl, DSI_CTRL, reg_ctrl & ~0x7);
  259. wmb(); /* wait controller to be disabled before reset */
  260. /* Force enable PCLK, BYTECLK, AHBM_HCLK */
  261. reg = DSI_R32(ctrl, DSI_CLK_CTRL);
  262. DSI_W32(ctrl, DSI_CLK_CTRL, reg | DSI_CTRL_DYNAMIC_FORCE_ON);
  263. wmb(); /* wait for clocks to be enabled */
  264. /* Trigger soft reset */
  265. DSI_W32(ctrl, DSI_SOFT_RESET, 0x1);
  266. wmb(); /* wait for reset to assert before waiting */
  267. udelay(1);
  268. DSI_W32(ctrl, DSI_SOFT_RESET, 0x0);
  269. wmb(); /* ensure reset is cleared */
  270. /* Disable force clock on */
  271. DSI_W32(ctrl, DSI_CLK_CTRL, reg);
  272. wmb(); /* make sure clocks are restored */
  273. /* Re-enable DSI controller */
  274. DSI_W32(ctrl, DSI_CTRL, reg_ctrl);
  275. wmb(); /* make sure DSI controller is enabled again */
  276. DSI_CTRL_HW_DBG(ctrl, "ctrl soft reset done\n");
  277. SDE_EVT32(ctrl->index);
  278. }
  279. /**
  280. * setup_misr() - Setup frame MISR
  281. * @ctrl: Pointer to the controller host hardware.
  282. * @panel_mode: CMD or VIDEO mode indicator
  283. * @enable: Enable/disable MISR.
  284. * @frame_count: Number of frames to accumulate MISR.
  285. */
  286. void dsi_ctrl_hw_cmn_setup_misr(struct dsi_ctrl_hw *ctrl,
  287. enum dsi_op_mode panel_mode,
  288. bool enable,
  289. u32 frame_count)
  290. {
  291. u32 addr;
  292. u32 config = 0;
  293. if (panel_mode == DSI_OP_CMD_MODE) {
  294. addr = DSI_MISR_CMD_CTRL;
  295. if (enable)
  296. config = DSI_CTRL_CMD_MISR_ENABLE;
  297. } else {
  298. addr = DSI_MISR_VIDEO_CTRL;
  299. if (enable)
  300. config = DSI_CTRL_VIDEO_MISR_ENABLE;
  301. if (frame_count > 255)
  302. frame_count = 255;
  303. config |= frame_count << 8;
  304. }
  305. DSI_CTRL_HW_DBG(ctrl, "MISR ctrl: 0x%x\n", config);
  306. DSI_W32(ctrl, addr, config);
  307. wmb(); /* make sure MISR is configured */
  308. }
  309. /**
  310. * collect_misr() - Read frame MISR
  311. * @ctrl: Pointer to the controller host hardware.
  312. * @panel_mode: CMD or VIDEO mode indicator
  313. */
  314. u32 dsi_ctrl_hw_cmn_collect_misr(struct dsi_ctrl_hw *ctrl,
  315. enum dsi_op_mode panel_mode)
  316. {
  317. u32 addr;
  318. u32 enabled;
  319. u32 misr = 0;
  320. if (panel_mode == DSI_OP_CMD_MODE) {
  321. addr = DSI_MISR_CMD_MDP0_32BIT;
  322. enabled = DSI_R32(ctrl, DSI_MISR_CMD_CTRL) &
  323. DSI_CTRL_CMD_MISR_ENABLE;
  324. } else {
  325. addr = DSI_MISR_VIDEO_32BIT;
  326. enabled = DSI_R32(ctrl, DSI_MISR_VIDEO_CTRL) &
  327. DSI_CTRL_VIDEO_MISR_ENABLE;
  328. }
  329. if (enabled)
  330. misr = DSI_R32(ctrl, addr);
  331. DSI_CTRL_HW_DBG(ctrl, "MISR enabled %x value: 0x%x\n", enabled, misr);
  332. return misr;
  333. }
  334. /**
  335. * set_timing_db() - enable/disable Timing DB register
  336. * @ctrl: Pointer to controller host hardware.
  337. * @enable: Enable/Disable flag.
  338. *
  339. * Enable or Disabe the Timing DB register.
  340. */
  341. void dsi_ctrl_hw_cmn_set_timing_db(struct dsi_ctrl_hw *ctrl,
  342. bool enable)
  343. {
  344. if (enable)
  345. DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x1);
  346. else
  347. DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x0);
  348. wmb(); /* make sure timing db registers are set */
  349. DSI_CTRL_HW_DBG(ctrl, "ctrl timing DB set:%d\n", enable);
  350. SDE_EVT32(ctrl->index, enable);
  351. }
  352. /**
  353. * get_dce_params() - get the dce params
  354. * @mode: mode information.
  355. * @width: width to be filled up
  356. * @bytes_per_pkt: Bytes per packet to be filled up
  357. * @pkt_per_line: Packet per line parameter
  358. * @eol_byte_num: End-of-line byte number
  359. *
  360. * Get the compression parameters based on compression type.
  361. */
  362. static void dsi_ctrl_hw_cmn_get_vid_dce_params(struct dsi_mode_info *mode,
  363. u32 *width, u32 *bytes_per_pkt, u32 *pkt_per_line,
  364. u32 *eol_byte_num)
  365. {
  366. if (dsi_dsc_compression_enabled(mode)) {
  367. *width = mode->dsc->pclk_per_line;
  368. *bytes_per_pkt = mode->dsc->bytes_per_pkt;
  369. *pkt_per_line = mode->dsc->pkt_per_line;
  370. *eol_byte_num = mode->dsc->eol_byte_num;
  371. } else if (dsi_vdc_compression_enabled(mode)) {
  372. *width = mode->vdc->pclk_per_line;
  373. *bytes_per_pkt = mode->vdc->bytes_per_pkt;
  374. *pkt_per_line = mode->vdc->pkt_per_line;
  375. *eol_byte_num = mode->vdc->eol_byte_num;
  376. }
  377. }
  378. /**
  379. * set_video_timing() - set up the timing for video frame
  380. * @ctrl: Pointer to controller host hardware.
  381. * @mode: Video mode information.
  382. *
  383. * Set up the video timing parameters for the DSI video mode operation.
  384. */
  385. void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl,
  386. struct dsi_mode_info *mode)
  387. {
  388. u32 reg = 0;
  389. u32 hs_start = 0;
  390. u32 hs_end, active_h_start, active_h_end, h_total, width = 0;
  391. u32 bytes_per_pkt = 0, pkt_per_line = 0, eol_byte_num = 0;
  392. u32 vs_start = 0, vs_end = 0;
  393. u32 vpos_start = 0, vpos_end, active_v_start, active_v_end, v_total;
  394. if (dsi_compression_enabled(mode)) {
  395. dsi_ctrl_hw_cmn_get_vid_dce_params(mode,
  396. &width, &bytes_per_pkt,
  397. &pkt_per_line, &eol_byte_num);
  398. reg = bytes_per_pkt << 16;
  399. /* data type of compressed image */
  400. reg |= (0x0b << 8);
  401. /*
  402. * pkt_per_line:
  403. * 0 == 1 pkt
  404. * 1 == 2 pkt
  405. * 2 == 4 pkt
  406. * 3 pkt is not supported
  407. */
  408. reg |= (pkt_per_line >> 1) << 6;
  409. reg |= eol_byte_num << 4;
  410. reg |= 1;
  411. DSI_W32(ctrl, DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
  412. if (ctrl->widebus_support) {
  413. reg = DSI_R32(ctrl, DSI_VIDEO_MODE_CTRL);
  414. reg |= BIT(25);
  415. DSI_W32(ctrl, DSI_VIDEO_MODE_CTRL, reg);
  416. }
  417. mode->h_active = DIV_ROUND_UP(mode->h_active *
  418. mode->pclk_scale.numer,
  419. mode->pclk_scale.denom);
  420. } else {
  421. width = mode->h_active;
  422. }
  423. hs_end = mode->h_sync_width;
  424. active_h_start = mode->h_sync_width + mode->h_back_porch;
  425. active_h_end = active_h_start + width;
  426. h_total = (mode->h_sync_width + mode->h_back_porch + width +
  427. mode->h_front_porch) - 1;
  428. vpos_end = mode->v_sync_width;
  429. active_v_start = mode->v_sync_width + mode->v_back_porch;
  430. active_v_end = active_v_start + mode->v_active;
  431. v_total = (mode->v_sync_width + mode->v_back_porch + mode->v_active +
  432. mode->v_front_porch) - 1;
  433. reg = ((active_h_end & 0xFFFF) << 16) | (active_h_start & 0xFFFF);
  434. DSI_W32(ctrl, DSI_VIDEO_MODE_ACTIVE_H, reg);
  435. reg = ((active_v_end & 0xFFFF) << 16) | (active_v_start & 0xFFFF);
  436. DSI_W32(ctrl, DSI_VIDEO_MODE_ACTIVE_V, reg);
  437. reg = ((v_total & 0xFFFF) << 16) | (h_total & 0xFFFF);
  438. DSI_W32(ctrl, DSI_VIDEO_MODE_TOTAL, reg);
  439. reg = ((hs_end & 0xFFFF) << 16) | (hs_start & 0xFFFF);
  440. DSI_W32(ctrl, DSI_VIDEO_MODE_HSYNC, reg);
  441. reg = ((vs_end & 0xFFFF) << 16) | (vs_start & 0xFFFF);
  442. DSI_W32(ctrl, DSI_VIDEO_MODE_VSYNC, reg);
  443. reg = ((vpos_end & 0xFFFF) << 16) | (vpos_start & 0xFFFF);
  444. DSI_W32(ctrl, DSI_VIDEO_MODE_VSYNC_VPOS, reg);
  445. /* TODO: HS TIMER value? */
  446. DSI_W32(ctrl, DSI_HS_TIMER_CTRL, 0x3FD08);
  447. DSI_W32(ctrl, DSI_MISR_VIDEO_CTRL, 0x10100);
  448. DSI_W32(ctrl, DSI_DSI_TIMING_FLUSH, 0x1);
  449. DSI_CTRL_HW_DBG(ctrl, "ctrl video parameters updated\n");
  450. SDE_EVT32(v_total, h_total);
  451. }
  452. /**
  453. * setup_cmd_stream() - set up parameters for command pixel streams
  454. * @ctrl: Pointer to controller host hardware.
  455. * @mode: Pointer to mode information.
  456. * @cfg: DSI host configuration that is common to both
  457. * video and command modes.
  458. * @vc_id: stream_id
  459. *
  460. * Setup parameters for command mode pixel stream size.
  461. */
  462. void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,
  463. struct dsi_mode_info *mode,
  464. struct dsi_host_common_cfg *cfg,
  465. u32 vc_id,
  466. struct dsi_rect *roi)
  467. {
  468. u32 width_final = 0, stride_final = 0;
  469. u32 height_final = 0;
  470. u32 stream_total = 0, stream_ctrl = 0;
  471. u32 reg_ctrl = 0, reg_ctrl2 = 0, data = 0;
  472. u32 reg = 0, offset = 0;
  473. int pic_width = 0, this_frame_slices = 0, intf_ip_w = 0;
  474. u32 pkt_per_line = 0, eol_byte_num = 0, bytes_in_slice = 0;
  475. if (roi && (!roi->w || !roi->h))
  476. return;
  477. if (dsi_dsc_compression_enabled(mode)) {
  478. struct msm_display_dsc_info dsc;
  479. pic_width = roi ? roi->w : mode->h_active;
  480. memcpy(&dsc, mode->dsc, sizeof(dsc));
  481. this_frame_slices = pic_width / dsc.config.slice_width;
  482. intf_ip_w = this_frame_slices * dsc.config.slice_width;
  483. sde_dsc_populate_dsc_private_params(&dsc, intf_ip_w);
  484. width_final = dsc.bytes_per_pkt * dsc.pkt_per_line;
  485. stride_final = dsc.bytes_per_pkt;
  486. pkt_per_line = dsc.pkt_per_line;
  487. eol_byte_num = dsc.eol_byte_num;
  488. bytes_in_slice = dsc.bytes_in_slice;
  489. } else if (dsi_vdc_compression_enabled(mode)) {
  490. struct msm_display_vdc_info vdc;
  491. pic_width = roi ? roi->w : mode->h_active;
  492. memcpy(&vdc, mode->vdc, sizeof(vdc));
  493. this_frame_slices = pic_width / vdc.slice_width;
  494. intf_ip_w = this_frame_slices * vdc.slice_width;
  495. sde_vdc_intf_prog_params(&vdc, intf_ip_w);
  496. width_final = vdc.bytes_per_pkt * vdc.pkt_per_line;
  497. stride_final = vdc.bytes_per_pkt;
  498. pkt_per_line = vdc.pkt_per_line;
  499. eol_byte_num = vdc.eol_byte_num;
  500. bytes_in_slice = vdc.bytes_in_slice;
  501. } else if (roi) {
  502. width_final = roi->w;
  503. stride_final = roi->w * 3;
  504. height_final = roi->h;
  505. } else {
  506. width_final = mode->h_active;
  507. stride_final = mode->h_active * 3;
  508. height_final = mode->v_active;
  509. }
  510. if (dsi_compression_enabled(mode)) {
  511. pic_width = roi ? roi->w : mode->h_active;
  512. height_final = roi ? roi->h : mode->v_active;
  513. if (ctrl->widebus_support) {
  514. width_final = DIV_ROUND_UP(width_final, 6);
  515. reg = DSI_R32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2);
  516. reg |= BIT(20);
  517. DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2, reg);
  518. } else {
  519. width_final = DIV_ROUND_UP(width_final, 3);
  520. }
  521. reg_ctrl = DSI_R32(ctrl, DSI_COMMAND_COMPRESSION_MODE_CTRL);
  522. reg_ctrl2 = DSI_R32(ctrl, DSI_COMMAND_COMPRESSION_MODE_CTRL2);
  523. if (vc_id != 0)
  524. offset = 16;
  525. reg = 0x39 << 8;
  526. /*
  527. * pkt_per_line:
  528. * 0 == 1 pkt
  529. * 1 == 2 pkt
  530. * 2 == 4 pkt
  531. * 3 pkt is not supported
  532. */
  533. reg |= (pkt_per_line >> 1) << 6;
  534. reg |= eol_byte_num << 4;
  535. reg |= 1;
  536. reg_ctrl &= ~(0xFFFF << offset);
  537. reg_ctrl |= (reg << offset);
  538. reg_ctrl2 &= ~(0xFFFF << offset);
  539. reg_ctrl2 |= (bytes_in_slice << offset);
  540. DSI_CTRL_HW_DBG(ctrl, "reg_ctrl 0x%x reg_ctrl2 0x%x\n",
  541. reg_ctrl, reg_ctrl2);
  542. }
  543. /* HS Timer value */
  544. DSI_W32(ctrl, DSI_HS_TIMER_CTRL, 0x3FD08);
  545. stream_ctrl = (stride_final + 1) << 16;
  546. stream_ctrl |= (vc_id & 0x3) << 8;
  547. stream_ctrl |= 0x39; /* packet data type */
  548. DSI_W32(ctrl, DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl);
  549. DSI_W32(ctrl, DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
  550. DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM0_CTRL, stream_ctrl);
  551. DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM1_CTRL, stream_ctrl);
  552. stream_total = (height_final << 16) | width_final;
  553. DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM0_TOTAL, stream_total);
  554. DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_STREAM1_TOTAL, stream_total);
  555. if (ctrl->null_insertion_enabled) {
  556. /* enable null packet insertion */
  557. data = (vc_id << 1);
  558. data |= 0 << 16;
  559. data |= 0x1;
  560. DSI_W32(ctrl, DSI_COMMAND_MODE_NULL_INSERTION_CTRL, data);
  561. }
  562. DSI_CTRL_HW_DBG(ctrl, "stream_ctrl 0x%x stream_total 0x%x\n",
  563. stream_ctrl, stream_total);
  564. }
  565. /**
  566. * setup_avr() - set the AVR_SUPPORT_ENABLE bit in DSI_VIDEO_MODE_CTRL
  567. * @ctrl: Pointer to controller host hardware.
  568. * @enable: Controls whether this bit is set or cleared
  569. *
  570. * Set or clear the AVR_SUPPORT_ENABLE bit in DSI_VIDEO_MODE_CTRL.
  571. */
  572. void dsi_ctrl_hw_cmn_setup_avr(struct dsi_ctrl_hw *ctrl, bool enable)
  573. {
  574. u32 reg = DSI_R32(ctrl, DSI_VIDEO_MODE_CTRL);
  575. if (enable)
  576. reg |= BIT(29);
  577. else
  578. reg &= ~BIT(29);
  579. DSI_W32(ctrl, DSI_VIDEO_MODE_CTRL, reg);
  580. DSI_CTRL_HW_DBG(ctrl, "AVR %s\n", enable ? "enabled" : "disabled");
  581. }
  582. /**
  583. * video_engine_setup() - Setup dsi host controller for video mode
  584. * @ctrl: Pointer to controller host hardware.
  585. * @common_cfg: Common configuration parameters.
  586. * @cfg: Video mode configuration.
  587. *
  588. * Set up DSI video engine with a specific configuration. Controller and
  589. * video engine are not enabled as part of this function.
  590. */
  591. void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl,
  592. struct dsi_host_common_cfg *common_cfg,
  593. struct dsi_video_engine_cfg *cfg)
  594. {
  595. u32 reg = 0;
  596. reg |= (cfg->last_line_interleave_en ? BIT(31) : 0);
  597. reg |= (cfg->pulse_mode_hsa_he ? BIT(28) : 0);
  598. reg |= (cfg->hfp_lp11_en ? BIT(24) : 0);
  599. reg |= (cfg->hbp_lp11_en ? BIT(20) : 0);
  600. reg |= (cfg->hsa_lp11_en ? BIT(16) : 0);
  601. reg |= (cfg->eof_bllp_lp11_en ? BIT(15) : 0);
  602. reg |= (cfg->bllp_lp11_en ? BIT(12) : 0);
  603. reg |= (cfg->traffic_mode & 0x3) << 8;
  604. reg |= (cfg->vc_id & 0x3);
  605. reg |= (video_mode_format_map[common_cfg->dst_format] & 0x3) << 4;
  606. DSI_W32(ctrl, DSI_VIDEO_MODE_CTRL, reg);
  607. reg = (common_cfg->swap_mode & 0x7) << 12;
  608. reg |= (common_cfg->bit_swap_red ? BIT(0) : 0);
  609. reg |= (common_cfg->bit_swap_green ? BIT(4) : 0);
  610. reg |= (common_cfg->bit_swap_blue ? BIT(8) : 0);
  611. DSI_W32(ctrl, DSI_VIDEO_MODE_DATA_CTRL, reg);
  612. /* Disable Timing double buffering */
  613. DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x0);
  614. DSI_CTRL_HW_DBG(ctrl, "Video engine setup done\n");
  615. }
  616. /**
  617. * cmd_engine_setup() - setup dsi host controller for command mode
  618. * @ctrl: Pointer to the controller host hardware.
  619. * @common_cfg: Common configuration parameters.
  620. * @cfg: Command mode configuration.
  621. *
  622. * Setup DSI CMD engine with a specific configuration. Controller and
  623. * command engine are not enabled as part of this function.
  624. */
  625. void dsi_ctrl_hw_cmn_cmd_engine_setup(struct dsi_ctrl_hw *ctrl,
  626. struct dsi_host_common_cfg *common_cfg,
  627. struct dsi_cmd_engine_cfg *cfg)
  628. {
  629. u32 reg = 0;
  630. reg = (cfg->max_cmd_packets_interleave & 0xF) << 20;
  631. reg |= (common_cfg->bit_swap_red ? BIT(4) : 0);
  632. reg |= (common_cfg->bit_swap_green ? BIT(8) : 0);
  633. reg |= (common_cfg->bit_swap_blue ? BIT(12) : 0);
  634. reg |= cmd_mode_format_map[common_cfg->dst_format];
  635. DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL, reg);
  636. reg = DSI_R32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2);
  637. reg |= BIT(16);
  638. DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2, reg);
  639. reg = cfg->wr_mem_start & 0xFF;
  640. reg |= (cfg->wr_mem_continue & 0xFF) << 8;
  641. reg |= (cfg->insert_dcs_command ? BIT(16) : 0);
  642. DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL, reg);
  643. DSI_CTRL_HW_DBG(ctrl, "Cmd engine setup done\n");
  644. }
  645. /**
  646. * video_engine_en() - enable DSI video engine
  647. * @ctrl: Pointer to controller host hardware.
  648. * @on: Enable/disabel video engine.
  649. */
  650. void dsi_ctrl_hw_cmn_video_engine_en(struct dsi_ctrl_hw *ctrl, bool on)
  651. {
  652. u32 reg = 0;
  653. /* Set/Clear VIDEO_MODE_EN bit */
  654. reg = DSI_R32(ctrl, DSI_CTRL);
  655. if (on)
  656. reg |= BIT(1);
  657. else
  658. reg &= ~BIT(1);
  659. DSI_W32(ctrl, DSI_CTRL, reg);
  660. DSI_CTRL_HW_DBG(ctrl, "Video engine = %d\n", on);
  661. }
  662. /**
  663. * ctrl_en() - enable DSI controller engine
  664. * @ctrl: Pointer to the controller host hardware.
  665. * @on: turn on/off the DSI controller engine.
  666. */
  667. void dsi_ctrl_hw_cmn_ctrl_en(struct dsi_ctrl_hw *ctrl, bool on)
  668. {
  669. u32 reg = 0;
  670. u32 clk_ctrl;
  671. clk_ctrl = DSI_R32(ctrl, DSI_CLK_CTRL);
  672. DSI_W32(ctrl, DSI_CLK_CTRL, clk_ctrl | DSI_CTRL_DYNAMIC_FORCE_ON);
  673. wmb(); /* wait for clocks to enable */
  674. /* Set/Clear DSI_EN bit */
  675. reg = DSI_R32(ctrl, DSI_CTRL);
  676. if (on)
  677. reg |= BIT(0);
  678. else
  679. reg &= ~BIT(0);
  680. DSI_W32(ctrl, DSI_CTRL, reg);
  681. wmb(); /* wait for DSI_EN update before disabling clocks */
  682. DSI_W32(ctrl, DSI_CLK_CTRL, clk_ctrl);
  683. wmb(); /* make sure clocks are restored */
  684. DSI_CTRL_HW_DBG(ctrl, "Controller engine = %d\n", on);
  685. }
  686. /**
  687. * cmd_engine_en() - enable DSI controller command engine
  688. * @ctrl: Pointer to the controller host hardware.
  689. * @on: Turn on/off the DSI command engine.
  690. */
  691. void dsi_ctrl_hw_cmn_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on)
  692. {
  693. u32 reg = 0;
  694. /* Set/Clear CMD_MODE_EN bit */
  695. reg = DSI_R32(ctrl, DSI_CTRL);
  696. if (on)
  697. reg |= BIT(2);
  698. else
  699. reg &= ~BIT(2);
  700. DSI_W32(ctrl, DSI_CTRL, reg);
  701. DSI_CTRL_HW_DBG(ctrl, "command engine = %d\n", on);
  702. }
  703. /**
  704. * kickoff_command() - transmits commands stored in memory
  705. * @ctrl: Pointer to the controller host hardware.
  706. * @cmd: Command information.
  707. * @flags: Modifiers for command transmission.
  708. *
  709. * The controller hardware is programmed with address and size of the
  710. * command buffer. The transmission is kicked off if
  711. * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is
  712. * set, caller should make a separate call to trigger_command_dma() to
  713. * transmit the command.
  714. */
  715. void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl,
  716. struct dsi_ctrl_cmd_dma_info *cmd,
  717. u32 flags)
  718. {
  719. u32 reg = 0;
  720. /*Set BROADCAST_EN and EMBEDDED_MODE */
  721. reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL);
  722. if (cmd->en_broadcast)
  723. reg |= BIT(31);
  724. else
  725. reg &= ~BIT(31);
  726. if (cmd->is_master)
  727. reg |= BIT(30);
  728. else
  729. reg &= ~BIT(30);
  730. if (cmd->use_lpm)
  731. reg |= BIT(26);
  732. else
  733. reg &= ~BIT(26);
  734. reg |= BIT(28);/* Select embedded mode */
  735. reg &= ~BIT(24);/* packet type */
  736. reg &= ~BIT(29);/* WC_SEL to 0 */
  737. DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg);
  738. reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL);
  739. reg |= BIT(20);/* Disable write watermark*/
  740. reg |= BIT(16);/* Disable read watermark */
  741. DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg);
  742. DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset);
  743. DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, (cmd->length & 0xFFFFFF));
  744. /* wait for writes to complete before kick off */
  745. wmb();
  746. if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER))
  747. DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
  748. }
  749. /**
  750. * kickoff_fifo_command() - transmits a command using FIFO in dsi
  751. * hardware.
  752. * @ctrl: Pointer to the controller host hardware.
  753. * @cmd: Command information.
  754. * @flags: Modifiers for command transmission.
  755. *
  756. * The controller hardware FIFO is programmed with command header and
  757. * payload. The transmission is kicked off if
  758. * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is
  759. * set, caller should make a separate call to trigger_command_dma() to
  760. * transmit the command.
  761. */
  762. void dsi_ctrl_hw_cmn_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl,
  763. struct dsi_ctrl_cmd_dma_fifo_info *cmd,
  764. u32 flags)
  765. {
  766. u32 reg = 0, i = 0;
  767. u32 *ptr = cmd->command;
  768. /*
  769. * Set CMD_DMA_TPG_EN, TPG_DMA_FIFO_MODE and
  770. * CMD_DMA_PATTERN_SEL = custom pattern stored in TPG DMA FIFO
  771. */
  772. reg = (BIT(1) | BIT(2) | (0x3 << 16));
  773. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
  774. /*
  775. * Program the FIFO with command buffer. Hardware requires an extra
  776. * DWORD (set to zero) if the length of command buffer is odd DWORDS.
  777. */
  778. for (i = 0; i < cmd->size; i += 4) {
  779. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL, *ptr);
  780. ptr++;
  781. }
  782. if ((cmd->size / 4) & 0x1)
  783. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL, 0);
  784. /*Set BROADCAST_EN and EMBEDDED_MODE */
  785. reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL);
  786. if (cmd->en_broadcast)
  787. reg |= BIT(31);
  788. else
  789. reg &= ~BIT(31);
  790. if (cmd->is_master)
  791. reg |= BIT(30);
  792. else
  793. reg &= ~BIT(30);
  794. if (cmd->use_lpm)
  795. reg |= BIT(26);
  796. else
  797. reg &= ~BIT(26);
  798. reg |= BIT(28);
  799. DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg);
  800. DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, (cmd->size & 0xFFFFFFFF));
  801. /* Finish writes before command trigger */
  802. wmb();
  803. if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER))
  804. DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
  805. DSI_CTRL_HW_DBG(ctrl, "size=%d, trigger = %d\n", cmd->size,
  806. (flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER) ? false : true);
  807. }
  808. void dsi_ctrl_hw_cmn_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl)
  809. {
  810. /* disable cmd dma tpg */
  811. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, 0x0);
  812. DSI_W32(ctrl, DSI_TPG_DMA_FIFO_RESET, 0x1);
  813. udelay(1);
  814. DSI_W32(ctrl, DSI_TPG_DMA_FIFO_RESET, 0x0);
  815. }
  816. /**
  817. * trigger_command_dma() - trigger transmission of command buffer.
  818. * @ctrl: Pointer to the controller host hardware.
  819. *
  820. * This trigger can be only used if there was a prior call to
  821. * kickoff_command() of kickoff_fifo_command() with
  822. * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag.
  823. */
  824. void dsi_ctrl_hw_cmn_trigger_command_dma(struct dsi_ctrl_hw *ctrl)
  825. {
  826. DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
  827. }
  828. /**
  829. * clear_rdbk_reg() - clear previously read panel data.
  830. * @ctrl: Pointer to the controller host hardware.
  831. *
  832. * This function is called before sending DSI Rx command to
  833. * panel in order to clear if any stale data remaining from
  834. * previous read operation.
  835. */
  836. void dsi_ctrl_hw_cmn_clear_rdbk_reg(struct dsi_ctrl_hw *ctrl)
  837. {
  838. DSI_W32(ctrl, DSI_RDBK_DATA_CTRL, 0x1);
  839. wmb(); /* ensure read back register is reset */
  840. DSI_W32(ctrl, DSI_RDBK_DATA_CTRL, 0x0);
  841. wmb(); /* ensure read back register is cleared */
  842. }
  843. /**
  844. * get_cmd_read_data() - get data read from the peripheral
  845. * @ctrl: Pointer to the controller host hardware.
  846. * @rd_buf: Buffer where data will be read into.
  847. * @total_read_len: Number of bytes to read.
  848. *
  849. * return: number of bytes read.
  850. */
  851. u32 dsi_ctrl_hw_cmn_get_cmd_read_data(struct dsi_ctrl_hw *ctrl,
  852. u8 *rd_buf,
  853. u32 read_offset,
  854. u32 rx_byte,
  855. u32 pkt_size,
  856. u32 *hw_read_cnt)
  857. {
  858. u32 *lp, *temp, data;
  859. int i, j = 0, cnt, off;
  860. u32 read_cnt;
  861. u32 repeated_bytes = 0;
  862. u8 reg[16] = {0};
  863. bool ack_err = false;
  864. lp = (u32 *)rd_buf;
  865. temp = (u32 *)reg;
  866. cnt = (rx_byte + 3) >> 2;
  867. if (cnt > 4)
  868. cnt = 4;
  869. read_cnt = (DSI_R32(ctrl, DSI_RDBK_DATA_CTRL) >> 16);
  870. ack_err = (rx_byte == 4) ? (read_cnt == 8) :
  871. ((read_cnt - 4) == (pkt_size + 6));
  872. if (ack_err)
  873. read_cnt -= 4;
  874. if (!read_cnt) {
  875. DSI_CTRL_HW_ERR(ctrl, "Panel detected error, no data read\n");
  876. return 0;
  877. }
  878. if (read_cnt > 16) {
  879. int bytes_shifted, data_lost = 0, rem_header = 0;
  880. bytes_shifted = read_cnt - rx_byte;
  881. if (bytes_shifted >= 4)
  882. data_lost = bytes_shifted - 4; /* remove DCS header */
  883. else
  884. rem_header = 4 - bytes_shifted; /* remaining header */
  885. repeated_bytes = (read_offset - 4) - data_lost + rem_header;
  886. }
  887. off = DSI_RDBK_DATA0;
  888. off += ((cnt - 1) * 4);
  889. for (i = 0; i < cnt; i++) {
  890. data = DSI_R32(ctrl, off);
  891. if (!repeated_bytes)
  892. *lp++ = ntohl(data);
  893. else
  894. *temp++ = ntohl(data);
  895. off -= 4;
  896. }
  897. if (repeated_bytes) {
  898. for (i = repeated_bytes; i < 16; i++)
  899. rd_buf[j++] = reg[i];
  900. }
  901. *hw_read_cnt = read_cnt;
  902. DSI_CTRL_HW_DBG(ctrl, "Read %d bytes\n", rx_byte);
  903. return rx_byte;
  904. }
  905. /**
  906. * poll_dma_status() - API to poll DMA status
  907. * @ctrl: Pointer to the controller host hardware.
  908. *
  909. * Return: DMA status.
  910. */
  911. u32 dsi_ctrl_hw_cmn_poll_dma_status(struct dsi_ctrl_hw *ctrl)
  912. {
  913. int rc = 0;
  914. u32 status;
  915. u32 const delay_us = 10;
  916. u32 const timeout_us = 5000;
  917. rc = DSI_READ_POLL_TIMEOUT_ATOMIC(ctrl, DSI_INT_CTRL, status,
  918. ((status & DSI_CMD_MODE_DMA_DONE) > 0), delay_us, timeout_us);
  919. if (rc) {
  920. DSI_CTRL_HW_DBG(ctrl, "CMD_MODE_DMA_DONE failed\n");
  921. status = 0;
  922. }
  923. return status;
  924. }
  925. /**
  926. * get_interrupt_status() - returns the interrupt status
  927. * @ctrl: Pointer to the controller host hardware.
  928. *
  929. * Returns the ORed list of interrupts(enum dsi_status_int_type) that
  930. * are active. This list does not include any error interrupts. Caller
  931. * should call get_error_status for error interrupts.
  932. *
  933. * Return: List of active interrupts.
  934. */
  935. u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl)
  936. {
  937. u32 reg = 0;
  938. u32 ints = 0;
  939. reg = DSI_R32(ctrl, DSI_INT_CTRL);
  940. if (reg & BIT(0))
  941. ints |= DSI_CMD_MODE_DMA_DONE;
  942. if (reg & BIT(8))
  943. ints |= DSI_CMD_FRAME_DONE;
  944. if (reg & BIT(10))
  945. ints |= DSI_CMD_STREAM0_FRAME_DONE;
  946. if (reg & BIT(12))
  947. ints |= DSI_CMD_STREAM1_FRAME_DONE;
  948. if (reg & BIT(14))
  949. ints |= DSI_CMD_STREAM2_FRAME_DONE;
  950. if (reg & BIT(16))
  951. ints |= DSI_VIDEO_MODE_FRAME_DONE;
  952. if (reg & BIT(20))
  953. ints |= DSI_BTA_DONE;
  954. if (reg & BIT(28))
  955. ints |= DSI_DYN_REFRESH_DONE;
  956. if (reg & BIT(30))
  957. ints |= DSI_DESKEW_DONE;
  958. if (reg & BIT(24))
  959. ints |= DSI_ERROR;
  960. DSI_CTRL_HW_DBG(ctrl, "Interrupt status = 0x%x, INT_CTRL=0x%x\n",
  961. ints, reg);
  962. return ints;
  963. }
  964. /**
  965. * clear_interrupt_status() - clears the specified interrupts
  966. * @ctrl: Pointer to the controller host hardware.
  967. * @ints: List of interrupts to be cleared.
  968. */
  969. void dsi_ctrl_hw_cmn_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints)
  970. {
  971. u32 reg = 0;
  972. reg = DSI_R32(ctrl, DSI_INT_CTRL);
  973. if (ints & DSI_CMD_MODE_DMA_DONE)
  974. reg |= BIT(0);
  975. if (ints & DSI_CMD_FRAME_DONE)
  976. reg |= BIT(8);
  977. if (ints & DSI_CMD_STREAM0_FRAME_DONE)
  978. reg |= BIT(10);
  979. if (ints & DSI_CMD_STREAM1_FRAME_DONE)
  980. reg |= BIT(12);
  981. if (ints & DSI_CMD_STREAM2_FRAME_DONE)
  982. reg |= BIT(14);
  983. if (ints & DSI_VIDEO_MODE_FRAME_DONE)
  984. reg |= BIT(16);
  985. if (ints & DSI_BTA_DONE)
  986. reg |= BIT(20);
  987. if (ints & DSI_DYN_REFRESH_DONE)
  988. reg |= BIT(28);
  989. if (ints & DSI_DESKEW_DONE)
  990. reg |= BIT(30);
  991. /*
  992. * Do not clear error status.
  993. * It will be cleared as part of
  994. * error handler function.
  995. */
  996. reg &= ~BIT(24);
  997. DSI_W32(ctrl, DSI_INT_CTRL, reg);
  998. DSI_CTRL_HW_DBG(ctrl, "Clear interrupts, ints = 0x%x, INT_CTRL=0x%x\n",
  999. ints, reg);
  1000. }
  1001. /**
  1002. * enable_status_interrupts() - enable the specified interrupts
  1003. * @ctrl: Pointer to the controller host hardware.
  1004. * @ints: List of interrupts to be enabled.
  1005. *
  1006. * Enables the specified interrupts. This list will override the
  1007. * previous interrupts enabled through this function. Caller has to
  1008. * maintain the state of the interrupts enabled. To disable all
  1009. * interrupts, set ints to 0.
  1010. */
  1011. void dsi_ctrl_hw_cmn_enable_status_interrupts(
  1012. struct dsi_ctrl_hw *ctrl, u32 ints)
  1013. {
  1014. u32 reg = 0;
  1015. /* Do not change value of DSI_ERROR_MASK bit */
  1016. reg |= (DSI_R32(ctrl, DSI_INT_CTRL) & BIT(25));
  1017. if (ints & DSI_CMD_MODE_DMA_DONE)
  1018. reg |= BIT(1);
  1019. if (ints & DSI_CMD_FRAME_DONE)
  1020. reg |= BIT(9);
  1021. if (ints & DSI_CMD_STREAM0_FRAME_DONE)
  1022. reg |= BIT(11);
  1023. if (ints & DSI_CMD_STREAM1_FRAME_DONE)
  1024. reg |= BIT(13);
  1025. if (ints & DSI_CMD_STREAM2_FRAME_DONE)
  1026. reg |= BIT(15);
  1027. if (ints & DSI_VIDEO_MODE_FRAME_DONE)
  1028. reg |= BIT(17);
  1029. if (ints & DSI_BTA_DONE)
  1030. reg |= BIT(21);
  1031. if (ints & DSI_DYN_REFRESH_DONE)
  1032. reg |= BIT(29);
  1033. if (ints & DSI_DESKEW_DONE)
  1034. reg |= BIT(31);
  1035. DSI_W32(ctrl, DSI_INT_CTRL, reg);
  1036. DSI_CTRL_HW_DBG(ctrl, "Enable interrupts 0x%x, INT_CTRL=0x%x\n", ints,
  1037. reg);
  1038. }
  1039. /**
  1040. * get_error_status() - returns the error status
  1041. * @ctrl: Pointer to the controller host hardware.
  1042. *
  1043. * Returns the ORed list of errors(enum dsi_error_int_type) that are
  1044. * active. This list does not include any status interrupts. Caller
  1045. * should call get_interrupt_status for status interrupts.
  1046. *
  1047. * Return: List of active error interrupts.
  1048. */
  1049. u64 dsi_ctrl_hw_cmn_get_error_status(struct dsi_ctrl_hw *ctrl)
  1050. {
  1051. u32 dln0_phy_err;
  1052. u32 fifo_status;
  1053. u32 ack_error;
  1054. u32 timeout_errors;
  1055. u32 clk_error;
  1056. u32 dsi_status;
  1057. u64 errors = 0, shift = 0x1;
  1058. dln0_phy_err = DSI_R32(ctrl, DSI_DLN0_PHY_ERR);
  1059. if (dln0_phy_err & BIT(0))
  1060. errors |= DSI_DLN0_ESC_ENTRY_ERR;
  1061. if (dln0_phy_err & BIT(4))
  1062. errors |= DSI_DLN0_ESC_SYNC_ERR;
  1063. if (dln0_phy_err & BIT(8))
  1064. errors |= DSI_DLN0_LP_CONTROL_ERR;
  1065. if (dln0_phy_err & BIT(12))
  1066. errors |= DSI_DLN0_LP0_CONTENTION;
  1067. if (dln0_phy_err & BIT(16))
  1068. errors |= DSI_DLN0_LP1_CONTENTION;
  1069. fifo_status = DSI_R32(ctrl, DSI_FIFO_STATUS);
  1070. if (fifo_status & BIT(7))
  1071. errors |= DSI_CMD_MDP_FIFO_UNDERFLOW;
  1072. if (fifo_status & BIT(10))
  1073. errors |= DSI_CMD_DMA_FIFO_UNDERFLOW;
  1074. if (fifo_status & BIT(18))
  1075. errors |= DSI_DLN0_HS_FIFO_OVERFLOW;
  1076. if (fifo_status & BIT(19))
  1077. errors |= DSI_DLN0_HS_FIFO_UNDERFLOW;
  1078. if (fifo_status & BIT(22))
  1079. errors |= DSI_DLN1_HS_FIFO_OVERFLOW;
  1080. if (fifo_status & BIT(23))
  1081. errors |= DSI_DLN1_HS_FIFO_UNDERFLOW;
  1082. if (fifo_status & BIT(26))
  1083. errors |= DSI_DLN2_HS_FIFO_OVERFLOW;
  1084. if (fifo_status & BIT(27))
  1085. errors |= DSI_DLN2_HS_FIFO_UNDERFLOW;
  1086. if (fifo_status & BIT(30))
  1087. errors |= DSI_DLN3_HS_FIFO_OVERFLOW;
  1088. if (fifo_status & BIT(31))
  1089. errors |= DSI_DLN3_HS_FIFO_UNDERFLOW;
  1090. ack_error = DSI_R32(ctrl, DSI_ACK_ERR_STATUS);
  1091. if (ack_error & BIT(16))
  1092. errors |= DSI_RDBK_SINGLE_ECC_ERR;
  1093. if (ack_error & BIT(17))
  1094. errors |= DSI_RDBK_MULTI_ECC_ERR;
  1095. if (ack_error & BIT(20))
  1096. errors |= DSI_RDBK_CRC_ERR;
  1097. if (ack_error & BIT(23))
  1098. errors |= DSI_RDBK_INCOMPLETE_PKT;
  1099. if (ack_error & BIT(24))
  1100. errors |= DSI_PERIPH_ERROR_PKT;
  1101. if (ack_error & BIT(15))
  1102. errors |= (shift << DSI_EINT_PANEL_SPECIFIC_ERR);
  1103. timeout_errors = DSI_R32(ctrl, DSI_TIMEOUT_STATUS);
  1104. if (timeout_errors & BIT(0))
  1105. errors |= DSI_HS_TX_TIMEOUT;
  1106. if (timeout_errors & BIT(4))
  1107. errors |= DSI_LP_RX_TIMEOUT;
  1108. if (timeout_errors & BIT(8))
  1109. errors |= DSI_BTA_TIMEOUT;
  1110. clk_error = DSI_R32(ctrl, DSI_CLK_STATUS);
  1111. if (clk_error & BIT(16))
  1112. errors |= DSI_PLL_UNLOCK;
  1113. dsi_status = DSI_R32(ctrl, DSI_STATUS);
  1114. if (dsi_status & BIT(31))
  1115. errors |= DSI_INTERLEAVE_OP_CONTENTION;
  1116. DSI_CTRL_HW_DBG(ctrl, "Error status = 0x%llx, phy=0x%x, fifo=0x%x\n",
  1117. errors, dln0_phy_err, fifo_status);
  1118. DSI_CTRL_HW_DBG(ctrl, "ack=0x%x, timeout=0x%x, clk=0x%x, dsi=0x%x\n",
  1119. ack_error, timeout_errors, clk_error, dsi_status);
  1120. return errors;
  1121. }
  1122. /**
  1123. * clear_error_status() - clears the specified errors
  1124. * @ctrl: Pointer to the controller host hardware.
  1125. * @errors: List of errors to be cleared.
  1126. */
  1127. void dsi_ctrl_hw_cmn_clear_error_status(struct dsi_ctrl_hw *ctrl, u64 errors)
  1128. {
  1129. u32 dln0_phy_err = 0;
  1130. u32 fifo_status = 0;
  1131. u32 ack_error = 0;
  1132. u32 timeout_error = 0;
  1133. u32 clk_error = 0;
  1134. u32 dsi_status = 0;
  1135. if (errors & DSI_RDBK_SINGLE_ECC_ERR)
  1136. ack_error |= BIT(16);
  1137. if (errors & DSI_RDBK_MULTI_ECC_ERR)
  1138. ack_error |= BIT(17);
  1139. if (errors & DSI_RDBK_CRC_ERR)
  1140. ack_error |= BIT(20);
  1141. if (errors & DSI_RDBK_INCOMPLETE_PKT)
  1142. ack_error |= BIT(23);
  1143. if (errors & DSI_PERIPH_ERROR_PKT)
  1144. ack_error |= BIT(24);
  1145. if (errors & DSI_PANEL_SPECIFIC_ERR)
  1146. ack_error |= BIT(15);
  1147. if (errors & DSI_LP_RX_TIMEOUT)
  1148. timeout_error |= BIT(4);
  1149. if (errors & DSI_HS_TX_TIMEOUT)
  1150. timeout_error |= BIT(0);
  1151. if (errors & DSI_BTA_TIMEOUT)
  1152. timeout_error |= BIT(8);
  1153. if (errors & DSI_PLL_UNLOCK)
  1154. clk_error |= BIT(16);
  1155. if (errors & DSI_DLN0_LP0_CONTENTION)
  1156. dln0_phy_err |= BIT(12);
  1157. if (errors & DSI_DLN0_LP1_CONTENTION)
  1158. dln0_phy_err |= BIT(16);
  1159. if (errors & DSI_DLN0_ESC_ENTRY_ERR)
  1160. dln0_phy_err |= BIT(0);
  1161. if (errors & DSI_DLN0_ESC_SYNC_ERR)
  1162. dln0_phy_err |= BIT(4);
  1163. if (errors & DSI_DLN0_LP_CONTROL_ERR)
  1164. dln0_phy_err |= BIT(8);
  1165. if (errors & DSI_CMD_DMA_FIFO_UNDERFLOW)
  1166. fifo_status |= BIT(10);
  1167. if (errors & DSI_CMD_MDP_FIFO_UNDERFLOW)
  1168. fifo_status |= BIT(7);
  1169. if (errors & DSI_DLN0_HS_FIFO_OVERFLOW)
  1170. fifo_status |= BIT(18);
  1171. if (errors & DSI_DLN1_HS_FIFO_OVERFLOW)
  1172. fifo_status |= BIT(22);
  1173. if (errors & DSI_DLN2_HS_FIFO_OVERFLOW)
  1174. fifo_status |= BIT(26);
  1175. if (errors & DSI_DLN3_HS_FIFO_OVERFLOW)
  1176. fifo_status |= BIT(30);
  1177. if (errors & DSI_DLN0_HS_FIFO_UNDERFLOW)
  1178. fifo_status |= BIT(19);
  1179. if (errors & DSI_DLN1_HS_FIFO_UNDERFLOW)
  1180. fifo_status |= BIT(23);
  1181. if (errors & DSI_DLN2_HS_FIFO_UNDERFLOW)
  1182. fifo_status |= BIT(27);
  1183. if (errors & DSI_DLN3_HS_FIFO_UNDERFLOW)
  1184. fifo_status |= BIT(31);
  1185. if (errors & DSI_INTERLEAVE_OP_CONTENTION)
  1186. dsi_status |= BIT(31);
  1187. DSI_W32(ctrl, DSI_DLN0_PHY_ERR, dln0_phy_err);
  1188. DSI_W32(ctrl, DSI_FIFO_STATUS, fifo_status);
  1189. /* Writing of an extra 0 is needed to clear ack error bits */
  1190. DSI_W32(ctrl, DSI_ACK_ERR_STATUS, ack_error);
  1191. wmb(); /* make sure register is committed */
  1192. DSI_W32(ctrl, DSI_ACK_ERR_STATUS, 0x0);
  1193. DSI_W32(ctrl, DSI_TIMEOUT_STATUS, timeout_error);
  1194. DSI_W32(ctrl, DSI_CLK_STATUS, clk_error);
  1195. DSI_W32(ctrl, DSI_STATUS, dsi_status);
  1196. DSI_CTRL_HW_DBG(ctrl, "clear errors = 0x%llx, phy=0x%x, fifo=0x%x\n",
  1197. errors, dln0_phy_err, fifo_status);
  1198. DSI_CTRL_HW_DBG(ctrl, "ack=0x%x, timeout=0x%x, clk=0x%x, dsi=0x%x\n",
  1199. ack_error, timeout_error, clk_error, dsi_status);
  1200. }
  1201. /**
  1202. * enable_error_interrupts() - enable the specified interrupts
  1203. * @ctrl: Pointer to the controller host hardware.
  1204. * @errors: List of errors to be enabled.
  1205. *
  1206. * Enables the specified interrupts. This list will override the
  1207. * previous interrupts enabled through this function. Caller has to
  1208. * maintain the state of the interrupts enabled. To disable all
  1209. * interrupts, set errors to 0.
  1210. */
  1211. void dsi_ctrl_hw_cmn_enable_error_interrupts(struct dsi_ctrl_hw *ctrl,
  1212. u64 errors)
  1213. {
  1214. u32 int_ctrl = 0;
  1215. u32 int_mask0 = 0x7FFF3BFF;
  1216. int_ctrl = DSI_R32(ctrl, DSI_INT_CTRL);
  1217. if (errors)
  1218. int_ctrl |= BIT(25);
  1219. else
  1220. int_ctrl &= ~BIT(25);
  1221. if (errors & DSI_RDBK_SINGLE_ECC_ERR)
  1222. int_mask0 &= ~BIT(0);
  1223. if (errors & DSI_RDBK_MULTI_ECC_ERR)
  1224. int_mask0 &= ~BIT(1);
  1225. if (errors & DSI_RDBK_CRC_ERR)
  1226. int_mask0 &= ~BIT(2);
  1227. if (errors & DSI_RDBK_INCOMPLETE_PKT)
  1228. int_mask0 &= ~BIT(3);
  1229. if (errors & DSI_PERIPH_ERROR_PKT)
  1230. int_mask0 &= ~BIT(4);
  1231. if (errors & DSI_LP_RX_TIMEOUT)
  1232. int_mask0 &= ~BIT(5);
  1233. if (errors & DSI_HS_TX_TIMEOUT)
  1234. int_mask0 &= ~BIT(6);
  1235. if (errors & DSI_BTA_TIMEOUT)
  1236. int_mask0 &= ~BIT(7);
  1237. if (errors & DSI_PLL_UNLOCK)
  1238. int_mask0 &= ~BIT(28);
  1239. if (errors & DSI_DLN0_LP0_CONTENTION)
  1240. int_mask0 &= ~BIT(24);
  1241. if (errors & DSI_DLN0_LP1_CONTENTION)
  1242. int_mask0 &= ~BIT(25);
  1243. if (errors & DSI_DLN0_ESC_ENTRY_ERR)
  1244. int_mask0 &= ~BIT(21);
  1245. if (errors & DSI_DLN0_ESC_SYNC_ERR)
  1246. int_mask0 &= ~BIT(22);
  1247. if (errors & DSI_DLN0_LP_CONTROL_ERR)
  1248. int_mask0 &= ~BIT(23);
  1249. if (errors & DSI_CMD_DMA_FIFO_UNDERFLOW)
  1250. int_mask0 &= ~BIT(9);
  1251. if (errors & DSI_CMD_MDP_FIFO_UNDERFLOW)
  1252. int_mask0 &= ~BIT(11);
  1253. if (errors & DSI_DLN0_HS_FIFO_OVERFLOW)
  1254. int_mask0 &= ~BIT(16);
  1255. if (errors & DSI_DLN1_HS_FIFO_OVERFLOW)
  1256. int_mask0 &= ~BIT(17);
  1257. if (errors & DSI_DLN2_HS_FIFO_OVERFLOW)
  1258. int_mask0 &= ~BIT(18);
  1259. if (errors & DSI_DLN3_HS_FIFO_OVERFLOW)
  1260. int_mask0 &= ~BIT(19);
  1261. if (errors & DSI_DLN0_HS_FIFO_UNDERFLOW)
  1262. int_mask0 &= ~BIT(26);
  1263. if (errors & DSI_DLN1_HS_FIFO_UNDERFLOW)
  1264. int_mask0 &= ~BIT(27);
  1265. if (errors & DSI_DLN2_HS_FIFO_UNDERFLOW)
  1266. int_mask0 &= ~BIT(29);
  1267. if (errors & DSI_DLN3_HS_FIFO_UNDERFLOW)
  1268. int_mask0 &= ~BIT(30);
  1269. if (errors & DSI_INTERLEAVE_OP_CONTENTION)
  1270. int_mask0 &= ~BIT(8);
  1271. DSI_W32(ctrl, DSI_INT_CTRL, int_ctrl);
  1272. DSI_W32(ctrl, DSI_ERR_INT_MASK0, int_mask0);
  1273. DSI_CTRL_HW_DBG(ctrl, "[DSI_%d] enable errors = 0x%llx, int_mask0=0x%x\n",
  1274. ctrl->index, errors, int_mask0);
  1275. }
  1276. /**
  1277. * video_test_pattern_setup() - setup test pattern engine for video mode
  1278. * @ctrl: Pointer to the controller host hardware.
  1279. * @type: Type of test pattern.
  1280. * @init_val: Initial value to use for generating test pattern.
  1281. */
  1282. void dsi_ctrl_hw_cmn_video_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
  1283. enum dsi_test_pattern type,
  1284. u32 init_val)
  1285. {
  1286. u32 reg = 0;
  1287. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, init_val);
  1288. switch (type) {
  1289. case DSI_TEST_PATTERN_FIXED:
  1290. reg |= (0x2 << 4);
  1291. break;
  1292. case DSI_TEST_PATTERN_INC:
  1293. reg |= (0x1 << 4);
  1294. break;
  1295. case DSI_TEST_PATTERN_POLY:
  1296. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_POLY, 0xF0F0F);
  1297. break;
  1298. default:
  1299. break;
  1300. }
  1301. DSI_W32(ctrl, DSI_TPG_MAIN_CONTROL, 0x100);
  1302. DSI_W32(ctrl, DSI_TPG_VIDEO_CONFIG, 0x5);
  1303. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
  1304. DSI_CTRL_HW_DBG(ctrl, "Video test pattern setup done\n");
  1305. }
  1306. /**
  1307. * cmd_test_pattern_setup() - setup test patttern engine for cmd mode
  1308. * @ctrl: Pointer to the controller host hardware.
  1309. * @type: Type of test pattern.
  1310. * @init_val: Initial value to use for generating test pattern.
  1311. * @stream_id: Stream Id on which packets are generated.
  1312. */
  1313. void dsi_ctrl_hw_cmn_cmd_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
  1314. enum dsi_test_pattern type,
  1315. u32 init_val,
  1316. u32 stream_id)
  1317. {
  1318. u32 reg = 0;
  1319. u32 init_offset;
  1320. u32 poly_offset;
  1321. u32 pattern_sel_shift;
  1322. switch (stream_id) {
  1323. case 0:
  1324. init_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0;
  1325. poly_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM0_POLY;
  1326. pattern_sel_shift = 8;
  1327. break;
  1328. case 1:
  1329. init_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL1;
  1330. poly_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM1_POLY;
  1331. pattern_sel_shift = 12;
  1332. break;
  1333. case 2:
  1334. init_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL2;
  1335. poly_offset = DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM2_POLY;
  1336. pattern_sel_shift = 20;
  1337. break;
  1338. default:
  1339. return;
  1340. }
  1341. DSI_W32(ctrl, init_offset, init_val);
  1342. switch (type) {
  1343. case DSI_TEST_PATTERN_FIXED:
  1344. reg |= (0x2 << pattern_sel_shift);
  1345. break;
  1346. case DSI_TEST_PATTERN_INC:
  1347. reg |= (0x1 << pattern_sel_shift);
  1348. break;
  1349. case DSI_TEST_PATTERN_POLY:
  1350. DSI_W32(ctrl, poly_offset, 0xF0F0F);
  1351. break;
  1352. default:
  1353. break;
  1354. }
  1355. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
  1356. DSI_CTRL_HW_DBG(ctrl, "Cmd test pattern setup done\n");
  1357. }
  1358. /**
  1359. * test_pattern_enable() - enable test pattern engine
  1360. * @ctrl: Pointer to the controller host hardware.
  1361. * @enable: Enable/Disable test pattern engine.
  1362. */
  1363. void dsi_ctrl_hw_cmn_test_pattern_enable(struct dsi_ctrl_hw *ctrl,
  1364. bool enable)
  1365. {
  1366. u32 reg = DSI_R32(ctrl, DSI_TEST_PATTERN_GEN_CTRL);
  1367. if (enable)
  1368. reg |= BIT(0);
  1369. else
  1370. reg &= ~BIT(0);
  1371. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
  1372. DSI_CTRL_HW_DBG(ctrl, "Test pattern enable=%d\n", enable);
  1373. }
  1374. /**
  1375. * trigger_cmd_test_pattern() - trigger a command mode frame update with
  1376. * test pattern
  1377. * @ctrl: Pointer to the controller host hardware.
  1378. * @stream_id: Stream on which frame update is sent.
  1379. */
  1380. void dsi_ctrl_hw_cmn_trigger_cmd_test_pattern(struct dsi_ctrl_hw *ctrl,
  1381. u32 stream_id)
  1382. {
  1383. switch (stream_id) {
  1384. case 0:
  1385. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 0x1);
  1386. break;
  1387. case 1:
  1388. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_STREAM1_TRIGGER, 0x1);
  1389. break;
  1390. case 2:
  1391. DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CMD_STREAM2_TRIGGER, 0x1);
  1392. break;
  1393. default:
  1394. break;
  1395. }
  1396. DSI_CTRL_HW_DBG(ctrl, "Cmd Test pattern trigger\n");
  1397. }
  1398. void dsi_ctrl_hw_dln0_phy_err(struct dsi_ctrl_hw *ctrl)
  1399. {
  1400. u32 status = 0;
  1401. /*
  1402. * Clear out any phy errors prior to exiting ULPS
  1403. * This fixes certain instances where phy does not exit
  1404. * ULPS cleanly. Also, do not print error during such cases.
  1405. */
  1406. status = DSI_R32(ctrl, DSI_DLN0_PHY_ERR);
  1407. if (status & 0x011111) {
  1408. DSI_W32(ctrl, DSI_DLN0_PHY_ERR, status);
  1409. DSI_CTRL_HW_ERR(ctrl, "phy_err_status = %x\n", status);
  1410. }
  1411. }
  1412. void dsi_ctrl_hw_cmn_phy_reset_config(struct dsi_ctrl_hw *ctrl,
  1413. bool enable)
  1414. {
  1415. u32 reg = 0;
  1416. reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
  1417. /* Mask/unmask disable PHY reset bit */
  1418. if (enable)
  1419. reg |= BIT(30);
  1420. else
  1421. reg &= ~BIT(30);
  1422. DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
  1423. }
  1424. int dsi_ctrl_hw_cmn_ctrl_reset(struct dsi_ctrl_hw *ctrl,
  1425. int mask)
  1426. {
  1427. int rc = 0;
  1428. u32 data;
  1429. DSI_CTRL_HW_DBG(ctrl, "DSI CTRL and PHY reset, mask=%d\n", mask);
  1430. data = DSI_R32(ctrl, 0x0004);
  1431. /* Disable DSI video mode */
  1432. DSI_W32(ctrl, 0x004, (data & ~BIT(1)));
  1433. wmb(); /* ensure register committed */
  1434. /* Disable DSI controller */
  1435. DSI_W32(ctrl, 0x004, (data & ~(BIT(0) | BIT(1))));
  1436. wmb(); /* ensure register committed */
  1437. /* "Force On" all dynamic clocks */
  1438. DSI_W32(ctrl, 0x11c, 0x100a00);
  1439. /* DSI_SW_RESET */
  1440. DSI_W32(ctrl, 0x118, 0x1);
  1441. wmb(); /* ensure register is committed */
  1442. DSI_W32(ctrl, 0x118, 0x0);
  1443. wmb(); /* ensure register is committed */
  1444. /* Remove "Force On" all dynamic clocks */
  1445. DSI_W32(ctrl, 0x11c, 0x00);
  1446. /* Enable DSI controller */
  1447. DSI_W32(ctrl, 0x004, (data & ~BIT(1)));
  1448. wmb(); /* ensure register committed */
  1449. return rc;
  1450. }
  1451. void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en)
  1452. {
  1453. u32 reg = 0;
  1454. u32 fifo_status = 0, timeout_status = 0;
  1455. u32 overflow_clear = BIT(10) | BIT(18) | BIT(22) | BIT(26) | BIT(30);
  1456. u32 underflow_clear = BIT(19) | BIT(23) | BIT(27) | BIT(31);
  1457. u32 lp_rx_clear = BIT(4);
  1458. reg = DSI_R32(ctrl, 0x10c);
  1459. /*
  1460. * Before unmasking we should clear the corresponding error status bits
  1461. * that might have been set while we masked these errors. Since these
  1462. * are sticky bits, these errors will trigger the moment we unmask
  1463. * the error bits.
  1464. */
  1465. if (idx & BIT(DSI_FIFO_OVERFLOW)) {
  1466. if (en) {
  1467. reg |= (0x1f << 16);
  1468. reg |= BIT(9);
  1469. } else {
  1470. reg &= ~(0x1f << 16);
  1471. reg &= ~BIT(9);
  1472. fifo_status = DSI_R32(ctrl, 0x00c);
  1473. DSI_W32(ctrl, 0x00c, fifo_status | overflow_clear);
  1474. }
  1475. }
  1476. if (idx & BIT(DSI_FIFO_UNDERFLOW)) {
  1477. if (en)
  1478. reg |= (0x1b << 26);
  1479. else {
  1480. reg &= ~(0x1b << 26);
  1481. fifo_status = DSI_R32(ctrl, 0x00c);
  1482. DSI_W32(ctrl, 0x00c, fifo_status | underflow_clear);
  1483. }
  1484. }
  1485. if (idx & BIT(DSI_LP_Rx_TIMEOUT)) {
  1486. if (en)
  1487. reg |= (0x7 << 23);
  1488. else {
  1489. reg &= ~(0x7 << 23);
  1490. timeout_status = DSI_R32(ctrl, 0x0c0);
  1491. DSI_W32(ctrl, 0x0c0, timeout_status | lp_rx_clear);
  1492. }
  1493. }
  1494. if (idx & BIT(DSI_PLL_UNLOCK_ERR)) {
  1495. if (en)
  1496. reg |= BIT(28);
  1497. else
  1498. reg &= ~BIT(28);
  1499. }
  1500. DSI_W32(ctrl, 0x10c, reg);
  1501. wmb(); /* ensure error is masked */
  1502. }
  1503. void dsi_ctrl_hw_cmn_error_intr_ctrl(struct dsi_ctrl_hw *ctrl, bool en)
  1504. {
  1505. u32 reg = 0;
  1506. u32 dsi_total_mask = 0x2222AA02;
  1507. reg = DSI_R32(ctrl, 0x110);
  1508. reg &= dsi_total_mask;
  1509. if (en)
  1510. reg |= (BIT(24) | BIT(25));
  1511. else
  1512. reg &= ~BIT(25);
  1513. DSI_W32(ctrl, 0x110, reg);
  1514. wmb(); /* ensure error is masked */
  1515. }
  1516. u32 dsi_ctrl_hw_cmn_get_error_mask(struct dsi_ctrl_hw *ctrl)
  1517. {
  1518. u32 reg = 0;
  1519. reg = DSI_R32(ctrl, 0x10c);
  1520. return reg;
  1521. }
  1522. u32 dsi_ctrl_hw_cmn_get_hw_version(struct dsi_ctrl_hw *ctrl)
  1523. {
  1524. u32 reg = 0;
  1525. reg = DSI_R32(ctrl, 0x0);
  1526. return reg;
  1527. }
  1528. int dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl_hw *ctrl)
  1529. {
  1530. int rc = 0, val = 0;
  1531. u32 cmd_mode_mdp_busy_mask = BIT(2);
  1532. u32 const sleep_us = 2 * 1000;
  1533. u32 const timeout_us = 200 * 1000;
  1534. rc = DSI_READ_POLL_TIMEOUT(ctrl, DSI_STATUS, val,
  1535. !(val & cmd_mode_mdp_busy_mask), sleep_us, timeout_us);
  1536. if (rc)
  1537. DSI_CTRL_HW_ERR(ctrl, "timed out waiting for idle\n");
  1538. return rc;
  1539. }
  1540. void dsi_ctrl_hw_cmn_hs_req_sel(struct dsi_ctrl_hw *ctrl, bool sel_phy)
  1541. {
  1542. u32 reg = 0;
  1543. reg = DSI_R32(ctrl, DSI_LANE_CTRL);
  1544. if (sel_phy)
  1545. reg &= ~BIT(24);
  1546. else
  1547. reg |= BIT(24);
  1548. DSI_W32(ctrl, DSI_LANE_CTRL, reg);
  1549. wmb(); /* make sure request is set */
  1550. }
  1551. void dsi_ctrl_hw_cmn_set_continuous_clk(struct dsi_ctrl_hw *ctrl, bool enable)
  1552. {
  1553. u32 reg = 0;
  1554. reg = DSI_R32(ctrl, DSI_LANE_CTRL);
  1555. if (enable)
  1556. reg |= BIT(28);
  1557. else
  1558. reg &= ~BIT(28);
  1559. DSI_W32(ctrl, DSI_LANE_CTRL, reg);
  1560. wmb(); /* make sure request is set */
  1561. }
  1562. int dsi_ctrl_hw_cmn_wait4dynamic_refresh_done(struct dsi_ctrl_hw *ctrl)
  1563. {
  1564. int rc;
  1565. u32 const sleep_us = 1000;
  1566. u32 const timeout_us = 84000; /* approximately 5 vsyncs */
  1567. u32 reg = 0, dyn_refresh_done = BIT(28);
  1568. rc = DSI_READ_POLL_TIMEOUT(ctrl, DSI_INT_CTRL, reg,
  1569. (reg & dyn_refresh_done), sleep_us, timeout_us);
  1570. if (rc) {
  1571. DSI_CTRL_HW_ERR(ctrl, "wait4dynamic refresh timedout %d\n", rc);
  1572. return rc;
  1573. }
  1574. /* ack dynamic refresh done status */
  1575. reg = DSI_R32(ctrl, DSI_INT_CTRL);
  1576. reg |= dyn_refresh_done;
  1577. DSI_W32(ctrl, DSI_INT_CTRL, reg);
  1578. return 0;
  1579. }
  1580. bool dsi_ctrl_hw_cmn_vid_engine_busy(struct dsi_ctrl_hw *ctrl)
  1581. {
  1582. u32 reg = 0, video_engine_busy = BIT(3);
  1583. int rc;
  1584. u32 const sleep_us = 1000;
  1585. u32 const timeout_us = 50000;
  1586. rc = DSI_READ_POLL_TIMEOUT(ctrl, DSI_STATUS, reg,
  1587. !(reg & video_engine_busy), sleep_us, timeout_us);
  1588. if (rc)
  1589. return true;
  1590. return false;
  1591. }