dp_tx.c 129 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. /* TODO Add support in TSO */
  44. #define DP_DESC_NUM_FRAG(x) 0
  45. /* disable TQM_BYPASS */
  46. #define TQM_BYPASS_WAR 0
  47. /* invalid peer id for reinject*/
  48. #define DP_INVALID_PEER 0XFFFE
  49. /*mapping between hal encrypt type and cdp_sec_type*/
  50. #define MAX_CDP_SEC_TYPE 12
  51. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  52. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  53. HAL_TX_ENCRYPT_TYPE_WEP_128,
  54. HAL_TX_ENCRYPT_TYPE_WEP_104,
  55. HAL_TX_ENCRYPT_TYPE_WEP_40,
  56. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  57. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  59. HAL_TX_ENCRYPT_TYPE_WAPI,
  60. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  62. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  63. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  64. #ifdef QCA_TX_LIMIT_CHECK
  65. /**
  66. * dp_tx_limit_check - Check if allocated tx descriptors reached
  67. * soc max limit and pdev max limit
  68. * @vdev: DP vdev handle
  69. *
  70. * Return: true if allocated tx descriptors reached max configured value, else
  71. * false
  72. */
  73. static inline bool
  74. dp_tx_limit_check(struct dp_vdev *vdev)
  75. {
  76. struct dp_pdev *pdev = vdev->pdev;
  77. struct dp_soc *soc = pdev->soc;
  78. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  79. soc->num_tx_allowed) {
  80. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  81. "%s: queued packets are more than max tx, drop the frame",
  82. __func__);
  83. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  84. return true;
  85. }
  86. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  87. pdev->num_tx_allowed) {
  88. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  89. "%s: queued packets are more than max tx, drop the frame",
  90. __func__);
  91. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  92. return true;
  93. }
  94. return false;
  95. }
  96. /**
  97. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  98. * reached soc max limit
  99. * @vdev: DP vdev handle
  100. *
  101. * Return: true if allocated tx descriptors reached max configured value, else
  102. * false
  103. */
  104. static inline bool
  105. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  106. {
  107. struct dp_pdev *pdev = vdev->pdev;
  108. struct dp_soc *soc = pdev->soc;
  109. if (qdf_atomic_read(&soc->num_tx_exception) >=
  110. soc->num_msdu_exception_desc) {
  111. dp_info("exc packets are more than max drop the exc pkt");
  112. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  113. return true;
  114. }
  115. return false;
  116. }
  117. /**
  118. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  119. * @vdev: DP pdev handle
  120. *
  121. * Return: void
  122. */
  123. static inline void
  124. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  125. {
  126. struct dp_soc *soc = pdev->soc;
  127. qdf_atomic_inc(&pdev->num_tx_outstanding);
  128. qdf_atomic_inc(&soc->num_tx_outstanding);
  129. }
  130. /**
  131. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  132. * @vdev: DP pdev handle
  133. *
  134. * Return: void
  135. */
  136. static inline void
  137. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  138. {
  139. struct dp_soc *soc = pdev->soc;
  140. qdf_atomic_dec(&pdev->num_tx_outstanding);
  141. qdf_atomic_dec(&soc->num_tx_outstanding);
  142. }
  143. #else //QCA_TX_LIMIT_CHECK
  144. static inline bool
  145. dp_tx_limit_check(struct dp_vdev *vdev)
  146. {
  147. return false;
  148. }
  149. static inline bool
  150. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  151. {
  152. return false;
  153. }
  154. static inline void
  155. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  156. {
  157. qdf_atomic_inc(&pdev->num_tx_outstanding);
  158. }
  159. static inline void
  160. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  161. {
  162. qdf_atomic_dec(&pdev->num_tx_outstanding);
  163. }
  164. #endif //QCA_TX_LIMIT_CHECK
  165. #if defined(FEATURE_TSO)
  166. /**
  167. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  168. *
  169. * @soc - core txrx main context
  170. * @seg_desc - tso segment descriptor
  171. * @num_seg_desc - tso number segment descriptor
  172. */
  173. static void dp_tx_tso_unmap_segment(
  174. struct dp_soc *soc,
  175. struct qdf_tso_seg_elem_t *seg_desc,
  176. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  177. {
  178. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  179. if (qdf_unlikely(!seg_desc)) {
  180. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  181. __func__, __LINE__);
  182. qdf_assert(0);
  183. } else if (qdf_unlikely(!num_seg_desc)) {
  184. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  185. __func__, __LINE__);
  186. qdf_assert(0);
  187. } else {
  188. bool is_last_seg;
  189. /* no tso segment left to do dma unmap */
  190. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  191. return;
  192. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  193. true : false;
  194. qdf_nbuf_unmap_tso_segment(soc->osdev,
  195. seg_desc, is_last_seg);
  196. num_seg_desc->num_seg.tso_cmn_num_seg--;
  197. }
  198. }
  199. /**
  200. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  201. * back to the freelist
  202. *
  203. * @soc - soc device handle
  204. * @tx_desc - Tx software descriptor
  205. */
  206. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  207. struct dp_tx_desc_s *tx_desc)
  208. {
  209. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  210. if (qdf_unlikely(!tx_desc->tso_desc)) {
  211. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  212. "%s %d TSO desc is NULL!",
  213. __func__, __LINE__);
  214. qdf_assert(0);
  215. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  216. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  217. "%s %d TSO num desc is NULL!",
  218. __func__, __LINE__);
  219. qdf_assert(0);
  220. } else {
  221. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  222. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  223. /* Add the tso num segment into the free list */
  224. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  225. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  226. tx_desc->tso_num_desc);
  227. tx_desc->tso_num_desc = NULL;
  228. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  229. }
  230. /* Add the tso segment into the free list*/
  231. dp_tx_tso_desc_free(soc,
  232. tx_desc->pool_id, tx_desc->tso_desc);
  233. tx_desc->tso_desc = NULL;
  234. }
  235. }
  236. #else
  237. static void dp_tx_tso_unmap_segment(
  238. struct dp_soc *soc,
  239. struct qdf_tso_seg_elem_t *seg_desc,
  240. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  241. {
  242. }
  243. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  244. struct dp_tx_desc_s *tx_desc)
  245. {
  246. }
  247. #endif
  248. /**
  249. * dp_tx_desc_release() - Release Tx Descriptor
  250. * @tx_desc : Tx Descriptor
  251. * @desc_pool_id: Descriptor Pool ID
  252. *
  253. * Deallocate all resources attached to Tx descriptor and free the Tx
  254. * descriptor.
  255. *
  256. * Return:
  257. */
  258. static void
  259. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  260. {
  261. struct dp_pdev *pdev = tx_desc->pdev;
  262. struct dp_soc *soc;
  263. uint8_t comp_status = 0;
  264. qdf_assert(pdev);
  265. soc = pdev->soc;
  266. dp_tx_outstanding_dec(pdev);
  267. if (tx_desc->frm_type == dp_tx_frm_tso)
  268. dp_tx_tso_desc_release(soc, tx_desc);
  269. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  270. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  271. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  272. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  273. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  274. qdf_atomic_dec(&soc->num_tx_exception);
  275. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  276. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  277. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  278. soc->hal_soc);
  279. else
  280. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  281. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  282. "Tx Completion Release desc %d status %d outstanding %d",
  283. tx_desc->id, comp_status,
  284. qdf_atomic_read(&pdev->num_tx_outstanding));
  285. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  286. return;
  287. }
  288. /**
  289. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  290. * @vdev: DP vdev Handle
  291. * @nbuf: skb
  292. * @msdu_info: msdu_info required to create HTT metadata
  293. *
  294. * Prepares and fills HTT metadata in the frame pre-header for special frames
  295. * that should be transmitted using varying transmit parameters.
  296. * There are 2 VDEV modes that currently needs this special metadata -
  297. * 1) Mesh Mode
  298. * 2) DSRC Mode
  299. *
  300. * Return: HTT metadata size
  301. *
  302. */
  303. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  304. struct dp_tx_msdu_info_s *msdu_info)
  305. {
  306. uint32_t *meta_data = msdu_info->meta_data;
  307. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  308. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  309. uint8_t htt_desc_size;
  310. /* Size rounded of multiple of 8 bytes */
  311. uint8_t htt_desc_size_aligned;
  312. uint8_t *hdr = NULL;
  313. /*
  314. * Metadata - HTT MSDU Extension header
  315. */
  316. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  317. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  318. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  319. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  320. meta_data[0])) {
  321. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  322. htt_desc_size_aligned)) {
  323. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  324. htt_desc_size_aligned);
  325. if (!nbuf) {
  326. /*
  327. * qdf_nbuf_realloc_headroom won't do skb_clone
  328. * as skb_realloc_headroom does. so, no free is
  329. * needed here.
  330. */
  331. DP_STATS_INC(vdev,
  332. tx_i.dropped.headroom_insufficient,
  333. 1);
  334. qdf_print(" %s[%d] skb_realloc_headroom failed",
  335. __func__, __LINE__);
  336. return 0;
  337. }
  338. }
  339. /* Fill and add HTT metaheader */
  340. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  341. if (!hdr) {
  342. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  343. "Error in filling HTT metadata");
  344. return 0;
  345. }
  346. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  347. } else if (vdev->opmode == wlan_op_mode_ocb) {
  348. /* Todo - Add support for DSRC */
  349. }
  350. return htt_desc_size_aligned;
  351. }
  352. /**
  353. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  354. * @tso_seg: TSO segment to process
  355. * @ext_desc: Pointer to MSDU extension descriptor
  356. *
  357. * Return: void
  358. */
  359. #if defined(FEATURE_TSO)
  360. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  361. void *ext_desc)
  362. {
  363. uint8_t num_frag;
  364. uint32_t tso_flags;
  365. /*
  366. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  367. * tcp_flag_mask
  368. *
  369. * Checksum enable flags are set in TCL descriptor and not in Extension
  370. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  371. */
  372. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  373. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  374. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  375. tso_seg->tso_flags.ip_len);
  376. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  377. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  378. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  379. uint32_t lo = 0;
  380. uint32_t hi = 0;
  381. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  382. (tso_seg->tso_frags[num_frag].length));
  383. qdf_dmaaddr_to_32s(
  384. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  385. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  386. tso_seg->tso_frags[num_frag].length);
  387. }
  388. return;
  389. }
  390. #else
  391. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  392. void *ext_desc)
  393. {
  394. return;
  395. }
  396. #endif
  397. #if defined(FEATURE_TSO)
  398. /**
  399. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  400. * allocated and free them
  401. *
  402. * @soc: soc handle
  403. * @free_seg: list of tso segments
  404. * @msdu_info: msdu descriptor
  405. *
  406. * Return - void
  407. */
  408. static void dp_tx_free_tso_seg_list(
  409. struct dp_soc *soc,
  410. struct qdf_tso_seg_elem_t *free_seg,
  411. struct dp_tx_msdu_info_s *msdu_info)
  412. {
  413. struct qdf_tso_seg_elem_t *next_seg;
  414. while (free_seg) {
  415. next_seg = free_seg->next;
  416. dp_tx_tso_desc_free(soc,
  417. msdu_info->tx_queue.desc_pool_id,
  418. free_seg);
  419. free_seg = next_seg;
  420. }
  421. }
  422. /**
  423. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  424. * allocated and free them
  425. *
  426. * @soc: soc handle
  427. * @free_num_seg: list of tso number segments
  428. * @msdu_info: msdu descriptor
  429. * Return - void
  430. */
  431. static void dp_tx_free_tso_num_seg_list(
  432. struct dp_soc *soc,
  433. struct qdf_tso_num_seg_elem_t *free_num_seg,
  434. struct dp_tx_msdu_info_s *msdu_info)
  435. {
  436. struct qdf_tso_num_seg_elem_t *next_num_seg;
  437. while (free_num_seg) {
  438. next_num_seg = free_num_seg->next;
  439. dp_tso_num_seg_free(soc,
  440. msdu_info->tx_queue.desc_pool_id,
  441. free_num_seg);
  442. free_num_seg = next_num_seg;
  443. }
  444. }
  445. /**
  446. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  447. * do dma unmap for each segment
  448. *
  449. * @soc: soc handle
  450. * @free_seg: list of tso segments
  451. * @num_seg_desc: tso number segment descriptor
  452. *
  453. * Return - void
  454. */
  455. static void dp_tx_unmap_tso_seg_list(
  456. struct dp_soc *soc,
  457. struct qdf_tso_seg_elem_t *free_seg,
  458. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  459. {
  460. struct qdf_tso_seg_elem_t *next_seg;
  461. if (qdf_unlikely(!num_seg_desc)) {
  462. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  463. return;
  464. }
  465. while (free_seg) {
  466. next_seg = free_seg->next;
  467. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  468. free_seg = next_seg;
  469. }
  470. }
  471. #ifdef FEATURE_TSO_STATS
  472. /**
  473. * dp_tso_get_stats_idx: Retrieve the tso packet id
  474. * @pdev - pdev handle
  475. *
  476. * Return: id
  477. */
  478. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  479. {
  480. uint32_t stats_idx;
  481. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  482. % CDP_MAX_TSO_PACKETS);
  483. return stats_idx;
  484. }
  485. #else
  486. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  487. {
  488. return 0;
  489. }
  490. #endif /* FEATURE_TSO_STATS */
  491. /**
  492. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  493. * free the tso segments descriptor and
  494. * tso num segments descriptor
  495. *
  496. * @soc: soc handle
  497. * @msdu_info: msdu descriptor
  498. * @tso_seg_unmap: flag to show if dma unmap is necessary
  499. *
  500. * Return - void
  501. */
  502. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  503. struct dp_tx_msdu_info_s *msdu_info,
  504. bool tso_seg_unmap)
  505. {
  506. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  507. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  508. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  509. tso_info->tso_num_seg_list;
  510. /* do dma unmap for each segment */
  511. if (tso_seg_unmap)
  512. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  513. /* free all tso number segment descriptor though looks only have 1 */
  514. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  515. /* free all tso segment descriptor */
  516. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  517. }
  518. /**
  519. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  520. * @vdev: virtual device handle
  521. * @msdu: network buffer
  522. * @msdu_info: meta data associated with the msdu
  523. *
  524. * Return: QDF_STATUS_SUCCESS success
  525. */
  526. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  527. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  528. {
  529. struct qdf_tso_seg_elem_t *tso_seg;
  530. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  531. struct dp_soc *soc = vdev->pdev->soc;
  532. struct dp_pdev *pdev = vdev->pdev;
  533. struct qdf_tso_info_t *tso_info;
  534. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  535. tso_info = &msdu_info->u.tso_info;
  536. tso_info->curr_seg = NULL;
  537. tso_info->tso_seg_list = NULL;
  538. tso_info->num_segs = num_seg;
  539. msdu_info->frm_type = dp_tx_frm_tso;
  540. tso_info->tso_num_seg_list = NULL;
  541. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  542. while (num_seg) {
  543. tso_seg = dp_tx_tso_desc_alloc(
  544. soc, msdu_info->tx_queue.desc_pool_id);
  545. if (tso_seg) {
  546. tso_seg->next = tso_info->tso_seg_list;
  547. tso_info->tso_seg_list = tso_seg;
  548. num_seg--;
  549. } else {
  550. dp_err_rl("Failed to alloc tso seg desc");
  551. DP_STATS_INC_PKT(vdev->pdev,
  552. tso_stats.tso_no_mem_dropped, 1,
  553. qdf_nbuf_len(msdu));
  554. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  555. return QDF_STATUS_E_NOMEM;
  556. }
  557. }
  558. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  559. tso_num_seg = dp_tso_num_seg_alloc(soc,
  560. msdu_info->tx_queue.desc_pool_id);
  561. if (tso_num_seg) {
  562. tso_num_seg->next = tso_info->tso_num_seg_list;
  563. tso_info->tso_num_seg_list = tso_num_seg;
  564. } else {
  565. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  566. __func__);
  567. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  568. return QDF_STATUS_E_NOMEM;
  569. }
  570. msdu_info->num_seg =
  571. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  572. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  573. msdu_info->num_seg);
  574. if (!(msdu_info->num_seg)) {
  575. /*
  576. * Free allocated TSO seg desc and number seg desc,
  577. * do unmap for segments if dma map has done.
  578. */
  579. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  580. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  581. return QDF_STATUS_E_INVAL;
  582. }
  583. tso_info->curr_seg = tso_info->tso_seg_list;
  584. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  585. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  586. msdu, msdu_info->num_seg);
  587. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  588. tso_info->msdu_stats_idx);
  589. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  590. return QDF_STATUS_SUCCESS;
  591. }
  592. #else
  593. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  594. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  595. {
  596. return QDF_STATUS_E_NOMEM;
  597. }
  598. #endif
  599. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  600. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  601. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  602. /**
  603. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  604. * @vdev: DP Vdev handle
  605. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  606. * @desc_pool_id: Descriptor Pool ID
  607. *
  608. * Return:
  609. */
  610. static
  611. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  612. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  613. {
  614. uint8_t i;
  615. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  616. struct dp_tx_seg_info_s *seg_info;
  617. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  618. struct dp_soc *soc = vdev->pdev->soc;
  619. /* Allocate an extension descriptor */
  620. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  621. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  622. if (!msdu_ext_desc) {
  623. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  624. return NULL;
  625. }
  626. if (msdu_info->exception_fw &&
  627. qdf_unlikely(vdev->mesh_vdev)) {
  628. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  629. &msdu_info->meta_data[0],
  630. sizeof(struct htt_tx_msdu_desc_ext2_t));
  631. qdf_atomic_inc(&soc->num_tx_exception);
  632. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  633. }
  634. switch (msdu_info->frm_type) {
  635. case dp_tx_frm_sg:
  636. case dp_tx_frm_me:
  637. case dp_tx_frm_raw:
  638. seg_info = msdu_info->u.sg_info.curr_seg;
  639. /* Update the buffer pointers in MSDU Extension Descriptor */
  640. for (i = 0; i < seg_info->frag_cnt; i++) {
  641. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  642. seg_info->frags[i].paddr_lo,
  643. seg_info->frags[i].paddr_hi,
  644. seg_info->frags[i].len);
  645. }
  646. break;
  647. case dp_tx_frm_tso:
  648. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  649. &cached_ext_desc[0]);
  650. break;
  651. default:
  652. break;
  653. }
  654. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  655. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  656. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  657. msdu_ext_desc->vaddr);
  658. return msdu_ext_desc;
  659. }
  660. /**
  661. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  662. *
  663. * @skb: skb to be traced
  664. * @msdu_id: msdu_id of the packet
  665. * @vdev_id: vdev_id of the packet
  666. *
  667. * Return: None
  668. */
  669. #ifdef DP_DISABLE_TX_PKT_TRACE
  670. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  671. uint8_t vdev_id)
  672. {
  673. }
  674. #else
  675. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  676. uint8_t vdev_id)
  677. {
  678. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  679. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  680. DPTRACE(qdf_dp_trace_ptr(skb,
  681. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  682. QDF_TRACE_DEFAULT_PDEV_ID,
  683. qdf_nbuf_data_addr(skb),
  684. sizeof(qdf_nbuf_data(skb)),
  685. msdu_id, vdev_id));
  686. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  687. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  688. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  689. msdu_id, QDF_TX));
  690. }
  691. #endif
  692. /**
  693. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  694. * @vdev: DP vdev handle
  695. * @nbuf: skb
  696. * @desc_pool_id: Descriptor pool ID
  697. * @meta_data: Metadata to the fw
  698. * @tx_exc_metadata: Handle that holds exception path metadata
  699. * Allocate and prepare Tx descriptor with msdu information.
  700. *
  701. * Return: Pointer to Tx Descriptor on success,
  702. * NULL on failure
  703. */
  704. static
  705. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  706. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  707. struct dp_tx_msdu_info_s *msdu_info,
  708. struct cdp_tx_exception_metadata *tx_exc_metadata)
  709. {
  710. uint8_t align_pad;
  711. uint8_t is_exception = 0;
  712. uint8_t htt_hdr_size;
  713. struct dp_tx_desc_s *tx_desc;
  714. struct dp_pdev *pdev = vdev->pdev;
  715. struct dp_soc *soc = pdev->soc;
  716. if (dp_tx_limit_check(vdev))
  717. return NULL;
  718. /* Allocate software Tx descriptor */
  719. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  720. if (qdf_unlikely(!tx_desc)) {
  721. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  722. return NULL;
  723. }
  724. dp_tx_outstanding_inc(pdev);
  725. /* Initialize the SW tx descriptor */
  726. tx_desc->nbuf = nbuf;
  727. tx_desc->frm_type = dp_tx_frm_std;
  728. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  729. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  730. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  731. tx_desc->vdev = vdev;
  732. tx_desc->pdev = pdev;
  733. tx_desc->msdu_ext_desc = NULL;
  734. tx_desc->pkt_offset = 0;
  735. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  736. if (qdf_unlikely(vdev->multipass_en)) {
  737. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  738. goto failure;
  739. }
  740. /*
  741. * For special modes (vdev_type == ocb or mesh), data frames should be
  742. * transmitted using varying transmit parameters (tx spec) which include
  743. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  744. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  745. * These frames are sent as exception packets to firmware.
  746. *
  747. * HW requirement is that metadata should always point to a
  748. * 8-byte aligned address. So we add alignment pad to start of buffer.
  749. * HTT Metadata should be ensured to be multiple of 8-bytes,
  750. * to get 8-byte aligned start address along with align_pad added
  751. *
  752. * |-----------------------------|
  753. * | |
  754. * |-----------------------------| <-----Buffer Pointer Address given
  755. * | | ^ in HW descriptor (aligned)
  756. * | HTT Metadata | |
  757. * | | |
  758. * | | | Packet Offset given in descriptor
  759. * | | |
  760. * |-----------------------------| |
  761. * | Alignment Pad | v
  762. * |-----------------------------| <----- Actual buffer start address
  763. * | SKB Data | (Unaligned)
  764. * | |
  765. * | |
  766. * | |
  767. * | |
  768. * | |
  769. * |-----------------------------|
  770. */
  771. if (qdf_unlikely((msdu_info->exception_fw)) ||
  772. (vdev->opmode == wlan_op_mode_ocb) ||
  773. (tx_exc_metadata &&
  774. tx_exc_metadata->is_tx_sniffer)) {
  775. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  776. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  777. DP_STATS_INC(vdev,
  778. tx_i.dropped.headroom_insufficient, 1);
  779. goto failure;
  780. }
  781. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  782. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  783. "qdf_nbuf_push_head failed");
  784. goto failure;
  785. }
  786. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  787. msdu_info);
  788. if (htt_hdr_size == 0)
  789. goto failure;
  790. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  791. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  792. is_exception = 1;
  793. }
  794. #if !TQM_BYPASS_WAR
  795. if (is_exception || tx_exc_metadata)
  796. #endif
  797. {
  798. /* Temporary WAR due to TQM VP issues */
  799. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  800. qdf_atomic_inc(&soc->num_tx_exception);
  801. }
  802. return tx_desc;
  803. failure:
  804. dp_tx_desc_release(tx_desc, desc_pool_id);
  805. return NULL;
  806. }
  807. /**
  808. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  809. * @vdev: DP vdev handle
  810. * @nbuf: skb
  811. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  812. * @desc_pool_id : Descriptor Pool ID
  813. *
  814. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  815. * information. For frames wth fragments, allocate and prepare
  816. * an MSDU extension descriptor
  817. *
  818. * Return: Pointer to Tx Descriptor on success,
  819. * NULL on failure
  820. */
  821. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  822. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  823. uint8_t desc_pool_id)
  824. {
  825. struct dp_tx_desc_s *tx_desc;
  826. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  827. struct dp_pdev *pdev = vdev->pdev;
  828. struct dp_soc *soc = pdev->soc;
  829. if (dp_tx_limit_check(vdev))
  830. return NULL;
  831. /* Allocate software Tx descriptor */
  832. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  833. if (!tx_desc) {
  834. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  835. return NULL;
  836. }
  837. dp_tx_outstanding_inc(pdev);
  838. /* Initialize the SW tx descriptor */
  839. tx_desc->nbuf = nbuf;
  840. tx_desc->frm_type = msdu_info->frm_type;
  841. tx_desc->tx_encap_type = vdev->tx_encap_type;
  842. tx_desc->vdev = vdev;
  843. tx_desc->pdev = pdev;
  844. tx_desc->pkt_offset = 0;
  845. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  846. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  847. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  848. /* Handle scattered frames - TSO/SG/ME */
  849. /* Allocate and prepare an extension descriptor for scattered frames */
  850. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  851. if (!msdu_ext_desc) {
  852. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  853. "%s Tx Extension Descriptor Alloc Fail",
  854. __func__);
  855. goto failure;
  856. }
  857. #if TQM_BYPASS_WAR
  858. /* Temporary WAR due to TQM VP issues */
  859. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  860. qdf_atomic_inc(&soc->num_tx_exception);
  861. #endif
  862. if (qdf_unlikely(msdu_info->exception_fw))
  863. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  864. tx_desc->msdu_ext_desc = msdu_ext_desc;
  865. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  866. return tx_desc;
  867. failure:
  868. dp_tx_desc_release(tx_desc, desc_pool_id);
  869. return NULL;
  870. }
  871. /**
  872. * dp_tx_prepare_raw() - Prepare RAW packet TX
  873. * @vdev: DP vdev handle
  874. * @nbuf: buffer pointer
  875. * @seg_info: Pointer to Segment info Descriptor to be prepared
  876. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  877. * descriptor
  878. *
  879. * Return:
  880. */
  881. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  882. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  883. {
  884. qdf_nbuf_t curr_nbuf = NULL;
  885. uint16_t total_len = 0;
  886. qdf_dma_addr_t paddr;
  887. int32_t i;
  888. int32_t mapped_buf_num = 0;
  889. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  890. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  891. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  892. /* Continue only if frames are of DATA type */
  893. if (!DP_FRAME_IS_DATA(qos_wh)) {
  894. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  895. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  896. "Pkt. recd is of not data type");
  897. goto error;
  898. }
  899. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  900. if (vdev->raw_mode_war &&
  901. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  902. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  903. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  904. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  905. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  906. if (QDF_STATUS_SUCCESS !=
  907. qdf_nbuf_map_nbytes_single(vdev->osdev,
  908. curr_nbuf,
  909. QDF_DMA_TO_DEVICE,
  910. curr_nbuf->len)) {
  911. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  912. "%s dma map error ", __func__);
  913. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  914. mapped_buf_num = i;
  915. goto error;
  916. }
  917. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  918. seg_info->frags[i].paddr_lo = paddr;
  919. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  920. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  921. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  922. total_len += qdf_nbuf_len(curr_nbuf);
  923. }
  924. seg_info->frag_cnt = i;
  925. seg_info->total_len = total_len;
  926. seg_info->next = NULL;
  927. sg_info->curr_seg = seg_info;
  928. msdu_info->frm_type = dp_tx_frm_raw;
  929. msdu_info->num_seg = 1;
  930. return nbuf;
  931. error:
  932. i = 0;
  933. while (nbuf) {
  934. curr_nbuf = nbuf;
  935. if (i < mapped_buf_num) {
  936. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  937. QDF_DMA_TO_DEVICE,
  938. curr_nbuf->len);
  939. i++;
  940. }
  941. nbuf = qdf_nbuf_next(nbuf);
  942. qdf_nbuf_free(curr_nbuf);
  943. }
  944. return NULL;
  945. }
  946. /**
  947. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  948. * @soc: DP soc handle
  949. * @nbuf: Buffer pointer
  950. *
  951. * unmap the chain of nbufs that belong to this RAW frame.
  952. *
  953. * Return: None
  954. */
  955. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  956. qdf_nbuf_t nbuf)
  957. {
  958. qdf_nbuf_t cur_nbuf = nbuf;
  959. do {
  960. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  961. QDF_DMA_TO_DEVICE,
  962. cur_nbuf->len);
  963. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  964. } while (cur_nbuf);
  965. }
  966. #ifdef VDEV_PEER_PROTOCOL_COUNT
  967. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  968. { \
  969. qdf_nbuf_t nbuf_local; \
  970. struct dp_vdev *vdev_local = vdev_hdl; \
  971. do { \
  972. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  973. break; \
  974. nbuf_local = nbuf; \
  975. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  976. htt_cmn_pkt_type_raw)) \
  977. break; \
  978. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  979. break; \
  980. else if (qdf_nbuf_is_tso((nbuf_local))) \
  981. break; \
  982. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  983. (nbuf_local), \
  984. NULL, 1, 0); \
  985. } while (0); \
  986. }
  987. #else
  988. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  989. #endif
  990. /**
  991. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  992. * @soc: DP Soc Handle
  993. * @vdev: DP vdev handle
  994. * @tx_desc: Tx Descriptor Handle
  995. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  996. * @fw_metadata: Metadata to send to Target Firmware along with frame
  997. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  998. * @tx_exc_metadata: Handle that holds exception path meta data
  999. *
  1000. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1001. * from software Tx descriptor
  1002. *
  1003. * Return: QDF_STATUS_SUCCESS: success
  1004. * QDF_STATUS_E_RESOURCES: Error return
  1005. */
  1006. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1007. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  1008. uint16_t fw_metadata, uint8_t ring_id,
  1009. struct cdp_tx_exception_metadata
  1010. *tx_exc_metadata)
  1011. {
  1012. uint8_t type;
  1013. void *hal_tx_desc;
  1014. uint32_t *hal_tx_desc_cached;
  1015. /*
  1016. * Setting it initialization statically here to avoid
  1017. * a memset call jump with qdf_mem_set call
  1018. */
  1019. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1020. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1021. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1022. tx_exc_metadata->sec_type : vdev->sec_type);
  1023. /* Return Buffer Manager ID */
  1024. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1025. hal_ring_handle_t hal_ring_hdl = NULL;
  1026. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1027. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1028. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1029. return QDF_STATUS_E_RESOURCES;
  1030. }
  1031. hal_tx_desc_cached = (void *) cached_desc;
  1032. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1033. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1034. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1035. if (tx_desc->msdu_ext_desc->flags &
  1036. DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1037. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1038. else
  1039. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1040. } else {
  1041. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1042. tx_desc->pkt_offset;
  1043. type = HAL_TX_BUF_TYPE_BUFFER;
  1044. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1045. }
  1046. qdf_assert_always(tx_desc->dma_addr);
  1047. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1048. tx_desc->dma_addr, bm_id, tx_desc->id,
  1049. type);
  1050. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1051. vdev->lmac_id);
  1052. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1053. vdev->search_type);
  1054. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1055. vdev->bss_ast_idx);
  1056. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1057. vdev->dscp_tid_map_id);
  1058. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1059. sec_type_map[sec_type]);
  1060. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1061. (vdev->bss_ast_hash & 0xF));
  1062. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1063. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1064. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1065. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1066. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1067. vdev->hal_desc_addr_search_flags);
  1068. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1069. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1070. /* verify checksum offload configuration*/
  1071. if (vdev->csum_enabled &&
  1072. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1073. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1074. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1075. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1076. }
  1077. if (tid != HTT_TX_EXT_TID_INVALID)
  1078. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1079. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1080. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1081. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1082. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1083. soc->wlan_cfg_ctx)))
  1084. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1085. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1086. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1087. tx_desc->pkt_offset, tx_desc->id);
  1088. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1089. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1090. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1091. "%s %d : HAL RING Access Failed -- %pK",
  1092. __func__, __LINE__, hal_ring_hdl);
  1093. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1094. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1095. return status;
  1096. }
  1097. /* Sync cached descriptor with HW */
  1098. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1099. if (qdf_unlikely(!hal_tx_desc)) {
  1100. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1101. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1102. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1103. goto ring_access_fail;
  1104. }
  1105. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1106. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1107. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1108. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1109. status = QDF_STATUS_SUCCESS;
  1110. ring_access_fail:
  1111. if (hif_pm_runtime_get(soc->hif_handle,
  1112. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1113. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1114. hif_pm_runtime_put(soc->hif_handle,
  1115. RTPM_ID_DW_TX_HW_ENQUEUE);
  1116. } else {
  1117. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1118. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1119. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1120. }
  1121. return status;
  1122. }
  1123. /**
  1124. * dp_cce_classify() - Classify the frame based on CCE rules
  1125. * @vdev: DP vdev handle
  1126. * @nbuf: skb
  1127. *
  1128. * Classify frames based on CCE rules
  1129. * Return: bool( true if classified,
  1130. * else false)
  1131. */
  1132. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1133. {
  1134. qdf_ether_header_t *eh = NULL;
  1135. uint16_t ether_type;
  1136. qdf_llc_t *llcHdr;
  1137. qdf_nbuf_t nbuf_clone = NULL;
  1138. qdf_dot3_qosframe_t *qos_wh = NULL;
  1139. /* for mesh packets don't do any classification */
  1140. if (qdf_unlikely(vdev->mesh_vdev))
  1141. return false;
  1142. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1143. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1144. ether_type = eh->ether_type;
  1145. llcHdr = (qdf_llc_t *)(nbuf->data +
  1146. sizeof(qdf_ether_header_t));
  1147. } else {
  1148. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1149. /* For encrypted packets don't do any classification */
  1150. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1151. return false;
  1152. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1153. if (qdf_unlikely(
  1154. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1155. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1156. ether_type = *(uint16_t *)(nbuf->data
  1157. + QDF_IEEE80211_4ADDR_HDR_LEN
  1158. + sizeof(qdf_llc_t)
  1159. - sizeof(ether_type));
  1160. llcHdr = (qdf_llc_t *)(nbuf->data +
  1161. QDF_IEEE80211_4ADDR_HDR_LEN);
  1162. } else {
  1163. ether_type = *(uint16_t *)(nbuf->data
  1164. + QDF_IEEE80211_3ADDR_HDR_LEN
  1165. + sizeof(qdf_llc_t)
  1166. - sizeof(ether_type));
  1167. llcHdr = (qdf_llc_t *)(nbuf->data +
  1168. QDF_IEEE80211_3ADDR_HDR_LEN);
  1169. }
  1170. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1171. && (ether_type ==
  1172. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1173. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1174. return true;
  1175. }
  1176. }
  1177. return false;
  1178. }
  1179. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1180. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1181. sizeof(*llcHdr));
  1182. nbuf_clone = qdf_nbuf_clone(nbuf);
  1183. if (qdf_unlikely(nbuf_clone)) {
  1184. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1185. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1186. qdf_nbuf_pull_head(nbuf_clone,
  1187. sizeof(qdf_net_vlanhdr_t));
  1188. }
  1189. }
  1190. } else {
  1191. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1192. nbuf_clone = qdf_nbuf_clone(nbuf);
  1193. if (qdf_unlikely(nbuf_clone)) {
  1194. qdf_nbuf_pull_head(nbuf_clone,
  1195. sizeof(qdf_net_vlanhdr_t));
  1196. }
  1197. }
  1198. }
  1199. if (qdf_unlikely(nbuf_clone))
  1200. nbuf = nbuf_clone;
  1201. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1202. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1203. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1204. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1205. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1206. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1207. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1208. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1209. if (qdf_unlikely(nbuf_clone))
  1210. qdf_nbuf_free(nbuf_clone);
  1211. return true;
  1212. }
  1213. if (qdf_unlikely(nbuf_clone))
  1214. qdf_nbuf_free(nbuf_clone);
  1215. return false;
  1216. }
  1217. /**
  1218. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1219. * @vdev: DP vdev handle
  1220. * @nbuf: skb
  1221. *
  1222. * Extract the DSCP or PCP information from frame and map into TID value.
  1223. *
  1224. * Return: void
  1225. */
  1226. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1227. struct dp_tx_msdu_info_s *msdu_info)
  1228. {
  1229. uint8_t tos = 0, dscp_tid_override = 0;
  1230. uint8_t *hdr_ptr, *L3datap;
  1231. uint8_t is_mcast = 0;
  1232. qdf_ether_header_t *eh = NULL;
  1233. qdf_ethervlan_header_t *evh = NULL;
  1234. uint16_t ether_type;
  1235. qdf_llc_t *llcHdr;
  1236. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1237. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1238. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1239. eh = (qdf_ether_header_t *)nbuf->data;
  1240. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1241. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1242. } else {
  1243. qdf_dot3_qosframe_t *qos_wh =
  1244. (qdf_dot3_qosframe_t *) nbuf->data;
  1245. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1246. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1247. return;
  1248. }
  1249. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1250. ether_type = eh->ether_type;
  1251. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1252. /*
  1253. * Check if packet is dot3 or eth2 type.
  1254. */
  1255. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1256. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1257. sizeof(*llcHdr));
  1258. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1259. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1260. sizeof(*llcHdr);
  1261. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1262. + sizeof(*llcHdr) +
  1263. sizeof(qdf_net_vlanhdr_t));
  1264. } else {
  1265. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1266. sizeof(*llcHdr);
  1267. }
  1268. } else {
  1269. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1270. evh = (qdf_ethervlan_header_t *) eh;
  1271. ether_type = evh->ether_type;
  1272. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1273. }
  1274. }
  1275. /*
  1276. * Find priority from IP TOS DSCP field
  1277. */
  1278. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1279. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1280. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1281. /* Only for unicast frames */
  1282. if (!is_mcast) {
  1283. /* send it on VO queue */
  1284. msdu_info->tid = DP_VO_TID;
  1285. }
  1286. } else {
  1287. /*
  1288. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1289. * from TOS byte.
  1290. */
  1291. tos = ip->ip_tos;
  1292. dscp_tid_override = 1;
  1293. }
  1294. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1295. /* TODO
  1296. * use flowlabel
  1297. *igmpmld cases to be handled in phase 2
  1298. */
  1299. unsigned long ver_pri_flowlabel;
  1300. unsigned long pri;
  1301. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1302. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1303. DP_IPV6_PRIORITY_SHIFT;
  1304. tos = pri;
  1305. dscp_tid_override = 1;
  1306. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1307. msdu_info->tid = DP_VO_TID;
  1308. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1309. /* Only for unicast frames */
  1310. if (!is_mcast) {
  1311. /* send ucast arp on VO queue */
  1312. msdu_info->tid = DP_VO_TID;
  1313. }
  1314. }
  1315. /*
  1316. * Assign all MCAST packets to BE
  1317. */
  1318. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1319. if (is_mcast) {
  1320. tos = 0;
  1321. dscp_tid_override = 1;
  1322. }
  1323. }
  1324. if (dscp_tid_override == 1) {
  1325. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1326. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1327. }
  1328. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1329. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1330. return;
  1331. }
  1332. /**
  1333. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1334. * @vdev: DP vdev handle
  1335. * @nbuf: skb
  1336. *
  1337. * Software based TID classification is required when more than 2 DSCP-TID
  1338. * mapping tables are needed.
  1339. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1340. *
  1341. * Return: void
  1342. */
  1343. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1344. struct dp_tx_msdu_info_s *msdu_info)
  1345. {
  1346. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1347. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1348. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1349. return;
  1350. /* for mesh packets don't do any classification */
  1351. if (qdf_unlikely(vdev->mesh_vdev))
  1352. return;
  1353. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1354. }
  1355. #ifdef FEATURE_WLAN_TDLS
  1356. /**
  1357. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1358. * @tx_desc: TX descriptor
  1359. *
  1360. * Return: None
  1361. */
  1362. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1363. {
  1364. if (tx_desc->vdev) {
  1365. if (tx_desc->vdev->is_tdls_frame) {
  1366. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1367. tx_desc->vdev->is_tdls_frame = false;
  1368. }
  1369. }
  1370. }
  1371. /**
  1372. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1373. * @soc: dp_soc handle
  1374. * @tx_desc: TX descriptor
  1375. * @vdev: datapath vdev handle
  1376. *
  1377. * Return: None
  1378. */
  1379. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1380. struct dp_tx_desc_s *tx_desc,
  1381. struct dp_vdev *vdev)
  1382. {
  1383. struct hal_tx_completion_status ts = {0};
  1384. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1385. if (qdf_unlikely(!vdev)) {
  1386. dp_err_rl("vdev is null!");
  1387. goto error;
  1388. }
  1389. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1390. if (vdev->tx_non_std_data_callback.func) {
  1391. qdf_nbuf_set_next(nbuf, NULL);
  1392. vdev->tx_non_std_data_callback.func(
  1393. vdev->tx_non_std_data_callback.ctxt,
  1394. nbuf, ts.status);
  1395. return;
  1396. } else {
  1397. dp_err_rl("callback func is null");
  1398. }
  1399. error:
  1400. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1401. qdf_nbuf_free(nbuf);
  1402. }
  1403. /**
  1404. * dp_tx_msdu_single_map() - do nbuf map
  1405. * @vdev: DP vdev handle
  1406. * @tx_desc: DP TX descriptor pointer
  1407. * @nbuf: skb pointer
  1408. *
  1409. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1410. * operation done in other component.
  1411. *
  1412. * Return: QDF_STATUS
  1413. */
  1414. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1415. struct dp_tx_desc_s *tx_desc,
  1416. qdf_nbuf_t nbuf)
  1417. {
  1418. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1419. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1420. nbuf,
  1421. QDF_DMA_TO_DEVICE,
  1422. nbuf->len);
  1423. else
  1424. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1425. QDF_DMA_TO_DEVICE);
  1426. }
  1427. #else
  1428. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1429. {
  1430. }
  1431. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1432. struct dp_tx_desc_s *tx_desc,
  1433. struct dp_vdev *vdev)
  1434. {
  1435. }
  1436. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1437. struct dp_tx_desc_s *tx_desc,
  1438. qdf_nbuf_t nbuf)
  1439. {
  1440. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1441. nbuf,
  1442. QDF_DMA_TO_DEVICE,
  1443. nbuf->len);
  1444. }
  1445. #endif
  1446. /**
  1447. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1448. * @vdev: DP vdev handle
  1449. * @nbuf: skb
  1450. *
  1451. * Return: 1 if frame needs to be dropped else 0
  1452. */
  1453. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1454. {
  1455. struct dp_pdev *pdev = NULL;
  1456. struct dp_ast_entry *src_ast_entry = NULL;
  1457. struct dp_ast_entry *dst_ast_entry = NULL;
  1458. struct dp_soc *soc = NULL;
  1459. qdf_assert(vdev);
  1460. pdev = vdev->pdev;
  1461. qdf_assert(pdev);
  1462. soc = pdev->soc;
  1463. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1464. (soc, dstmac, vdev->pdev->pdev_id);
  1465. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1466. (soc, srcmac, vdev->pdev->pdev_id);
  1467. if (dst_ast_entry && src_ast_entry) {
  1468. if (dst_ast_entry->peer_id ==
  1469. src_ast_entry->peer_id)
  1470. return 1;
  1471. }
  1472. return 0;
  1473. }
  1474. /**
  1475. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1476. * @vdev: DP vdev handle
  1477. * @nbuf: skb
  1478. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1479. * @meta_data: Metadata to the fw
  1480. * @tx_q: Tx queue to be used for this Tx frame
  1481. * @peer_id: peer_id of the peer in case of NAWDS frames
  1482. * @tx_exc_metadata: Handle that holds exception path metadata
  1483. *
  1484. * Return: NULL on success,
  1485. * nbuf when it fails to send
  1486. */
  1487. qdf_nbuf_t
  1488. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1489. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1490. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1491. {
  1492. struct dp_pdev *pdev = vdev->pdev;
  1493. struct dp_soc *soc = pdev->soc;
  1494. struct dp_tx_desc_s *tx_desc;
  1495. QDF_STATUS status;
  1496. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1497. uint16_t htt_tcl_metadata = 0;
  1498. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1499. uint8_t tid = msdu_info->tid;
  1500. struct cdp_tid_tx_stats *tid_stats = NULL;
  1501. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1502. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1503. msdu_info, tx_exc_metadata);
  1504. if (!tx_desc) {
  1505. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1506. vdev, tx_q->desc_pool_id);
  1507. drop_code = TX_DESC_ERR;
  1508. goto fail_return;
  1509. }
  1510. if (qdf_unlikely(soc->cce_disable)) {
  1511. if (dp_cce_classify(vdev, nbuf) == true) {
  1512. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1513. tid = DP_VO_TID;
  1514. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1515. }
  1516. }
  1517. dp_tx_update_tdls_flags(tx_desc);
  1518. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1519. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1520. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1521. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1522. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1523. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1524. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1525. peer_id);
  1526. } else
  1527. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1528. if (msdu_info->exception_fw)
  1529. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1530. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1531. !pdev->enhanced_stats_en);
  1532. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1533. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1534. /* Handle failure */
  1535. dp_err("qdf_nbuf_map failed");
  1536. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1537. drop_code = TX_DMA_MAP_ERR;
  1538. goto release_desc;
  1539. }
  1540. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1541. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1542. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1543. if (status != QDF_STATUS_SUCCESS) {
  1544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1545. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1546. __func__, tx_desc, tx_q->ring_id);
  1547. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1548. QDF_DMA_TO_DEVICE,
  1549. nbuf->len);
  1550. drop_code = TX_HW_ENQUEUE;
  1551. goto release_desc;
  1552. }
  1553. return NULL;
  1554. release_desc:
  1555. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1556. fail_return:
  1557. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1558. tid_stats = &pdev->stats.tid_stats.
  1559. tid_tx_stats[tx_q->ring_id][tid];
  1560. tid_stats->swdrop_cnt[drop_code]++;
  1561. return nbuf;
  1562. }
  1563. /**
  1564. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1565. * @vdev: DP vdev handle
  1566. * @nbuf: skb
  1567. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1568. *
  1569. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1570. *
  1571. * Return: NULL on success,
  1572. * nbuf when it fails to send
  1573. */
  1574. #if QDF_LOCK_STATS
  1575. noinline
  1576. #else
  1577. #endif
  1578. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1579. struct dp_tx_msdu_info_s *msdu_info)
  1580. {
  1581. uint32_t i;
  1582. struct dp_pdev *pdev = vdev->pdev;
  1583. struct dp_soc *soc = pdev->soc;
  1584. struct dp_tx_desc_s *tx_desc;
  1585. bool is_cce_classified = false;
  1586. QDF_STATUS status;
  1587. uint16_t htt_tcl_metadata = 0;
  1588. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1589. struct cdp_tid_tx_stats *tid_stats = NULL;
  1590. if (qdf_unlikely(soc->cce_disable)) {
  1591. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1592. if (is_cce_classified) {
  1593. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1594. msdu_info->tid = DP_VO_TID;
  1595. }
  1596. }
  1597. if (msdu_info->frm_type == dp_tx_frm_me)
  1598. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1599. i = 0;
  1600. /* Print statement to track i and num_seg */
  1601. /*
  1602. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1603. * descriptors using information in msdu_info
  1604. */
  1605. while (i < msdu_info->num_seg) {
  1606. /*
  1607. * Setup Tx descriptor for an MSDU, and MSDU extension
  1608. * descriptor
  1609. */
  1610. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1611. tx_q->desc_pool_id);
  1612. if (!tx_desc) {
  1613. if (msdu_info->frm_type == dp_tx_frm_me) {
  1614. dp_tx_me_free_buf(pdev,
  1615. (void *)(msdu_info->u.sg_info
  1616. .curr_seg->frags[0].vaddr));
  1617. i++;
  1618. continue;
  1619. }
  1620. goto done;
  1621. }
  1622. if (msdu_info->frm_type == dp_tx_frm_me) {
  1623. tx_desc->me_buffer =
  1624. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1625. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1626. }
  1627. if (is_cce_classified)
  1628. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1629. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1630. if (msdu_info->exception_fw) {
  1631. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1632. }
  1633. /*
  1634. * Enqueue the Tx MSDU descriptor to HW for transmit
  1635. */
  1636. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1637. htt_tcl_metadata, tx_q->ring_id, NULL);
  1638. if (status != QDF_STATUS_SUCCESS) {
  1639. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1640. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1641. __func__, tx_desc, tx_q->ring_id);
  1642. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1643. tid_stats = &pdev->stats.tid_stats.
  1644. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1645. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1646. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1647. if (msdu_info->frm_type == dp_tx_frm_me) {
  1648. i++;
  1649. continue;
  1650. }
  1651. goto done;
  1652. }
  1653. /*
  1654. * TODO
  1655. * if tso_info structure can be modified to have curr_seg
  1656. * as first element, following 2 blocks of code (for TSO and SG)
  1657. * can be combined into 1
  1658. */
  1659. /*
  1660. * For frames with multiple segments (TSO, ME), jump to next
  1661. * segment.
  1662. */
  1663. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1664. if (msdu_info->u.tso_info.curr_seg->next) {
  1665. msdu_info->u.tso_info.curr_seg =
  1666. msdu_info->u.tso_info.curr_seg->next;
  1667. /*
  1668. * If this is a jumbo nbuf, then increment the number of
  1669. * nbuf users for each additional segment of the msdu.
  1670. * This will ensure that the skb is freed only after
  1671. * receiving tx completion for all segments of an nbuf
  1672. */
  1673. qdf_nbuf_inc_users(nbuf);
  1674. /* Check with MCL if this is needed */
  1675. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1676. }
  1677. }
  1678. /*
  1679. * For Multicast-Unicast converted packets,
  1680. * each converted frame (for a client) is represented as
  1681. * 1 segment
  1682. */
  1683. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1684. (msdu_info->frm_type == dp_tx_frm_me)) {
  1685. if (msdu_info->u.sg_info.curr_seg->next) {
  1686. msdu_info->u.sg_info.curr_seg =
  1687. msdu_info->u.sg_info.curr_seg->next;
  1688. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1689. }
  1690. }
  1691. i++;
  1692. }
  1693. nbuf = NULL;
  1694. done:
  1695. return nbuf;
  1696. }
  1697. /**
  1698. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1699. * for SG frames
  1700. * @vdev: DP vdev handle
  1701. * @nbuf: skb
  1702. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1703. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1704. *
  1705. * Return: NULL on success,
  1706. * nbuf when it fails to send
  1707. */
  1708. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1709. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1710. {
  1711. uint32_t cur_frag, nr_frags;
  1712. qdf_dma_addr_t paddr;
  1713. struct dp_tx_sg_info_s *sg_info;
  1714. sg_info = &msdu_info->u.sg_info;
  1715. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1716. if (QDF_STATUS_SUCCESS !=
  1717. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1718. QDF_DMA_TO_DEVICE, nbuf->len)) {
  1719. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1720. "dma map error");
  1721. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1722. qdf_nbuf_free(nbuf);
  1723. return NULL;
  1724. }
  1725. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1726. seg_info->frags[0].paddr_lo = paddr;
  1727. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1728. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1729. seg_info->frags[0].vaddr = (void *) nbuf;
  1730. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1731. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1732. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1733. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1734. "frag dma map error");
  1735. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1736. qdf_nbuf_free(nbuf);
  1737. return NULL;
  1738. }
  1739. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1740. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1741. seg_info->frags[cur_frag + 1].paddr_hi =
  1742. ((uint64_t) paddr) >> 32;
  1743. seg_info->frags[cur_frag + 1].len =
  1744. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1745. }
  1746. seg_info->frag_cnt = (cur_frag + 1);
  1747. seg_info->total_len = qdf_nbuf_len(nbuf);
  1748. seg_info->next = NULL;
  1749. sg_info->curr_seg = seg_info;
  1750. msdu_info->frm_type = dp_tx_frm_sg;
  1751. msdu_info->num_seg = 1;
  1752. return nbuf;
  1753. }
  1754. /**
  1755. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1756. * @vdev: DP vdev handle
  1757. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1758. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1759. *
  1760. * Return: NULL on failure,
  1761. * nbuf when extracted successfully
  1762. */
  1763. static
  1764. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1765. struct dp_tx_msdu_info_s *msdu_info,
  1766. uint16_t ppdu_cookie)
  1767. {
  1768. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1769. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1770. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1771. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1772. (msdu_info->meta_data[5], 1);
  1773. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1774. (msdu_info->meta_data[5], 1);
  1775. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1776. (msdu_info->meta_data[6], ppdu_cookie);
  1777. msdu_info->exception_fw = 1;
  1778. msdu_info->is_tx_sniffer = 1;
  1779. }
  1780. #ifdef MESH_MODE_SUPPORT
  1781. /**
  1782. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1783. and prepare msdu_info for mesh frames.
  1784. * @vdev: DP vdev handle
  1785. * @nbuf: skb
  1786. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1787. *
  1788. * Return: NULL on failure,
  1789. * nbuf when extracted successfully
  1790. */
  1791. static
  1792. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1793. struct dp_tx_msdu_info_s *msdu_info)
  1794. {
  1795. struct meta_hdr_s *mhdr;
  1796. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1797. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1798. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1799. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1800. msdu_info->exception_fw = 0;
  1801. goto remove_meta_hdr;
  1802. }
  1803. msdu_info->exception_fw = 1;
  1804. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1805. meta_data->host_tx_desc_pool = 1;
  1806. meta_data->update_peer_cache = 1;
  1807. meta_data->learning_frame = 1;
  1808. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1809. meta_data->power = mhdr->power;
  1810. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1811. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1812. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1813. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1814. meta_data->dyn_bw = 1;
  1815. meta_data->valid_pwr = 1;
  1816. meta_data->valid_mcs_mask = 1;
  1817. meta_data->valid_nss_mask = 1;
  1818. meta_data->valid_preamble_type = 1;
  1819. meta_data->valid_retries = 1;
  1820. meta_data->valid_bw_info = 1;
  1821. }
  1822. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1823. meta_data->encrypt_type = 0;
  1824. meta_data->valid_encrypt_type = 1;
  1825. meta_data->learning_frame = 0;
  1826. }
  1827. meta_data->valid_key_flags = 1;
  1828. meta_data->key_flags = (mhdr->keyix & 0x3);
  1829. remove_meta_hdr:
  1830. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1831. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1832. "qdf_nbuf_pull_head failed");
  1833. qdf_nbuf_free(nbuf);
  1834. return NULL;
  1835. }
  1836. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1837. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1838. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1839. " tid %d to_fw %d",
  1840. __func__, msdu_info->meta_data[0],
  1841. msdu_info->meta_data[1],
  1842. msdu_info->meta_data[2],
  1843. msdu_info->meta_data[3],
  1844. msdu_info->meta_data[4],
  1845. msdu_info->meta_data[5],
  1846. msdu_info->tid, msdu_info->exception_fw);
  1847. return nbuf;
  1848. }
  1849. #else
  1850. static
  1851. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1852. struct dp_tx_msdu_info_s *msdu_info)
  1853. {
  1854. return nbuf;
  1855. }
  1856. #endif
  1857. /**
  1858. * dp_check_exc_metadata() - Checks if parameters are valid
  1859. * @tx_exc - holds all exception path parameters
  1860. *
  1861. * Returns true when all the parameters are valid else false
  1862. *
  1863. */
  1864. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1865. {
  1866. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1867. HTT_INVALID_TID);
  1868. bool invalid_encap_type =
  1869. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1870. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1871. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1872. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1873. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1874. tx_exc->ppdu_cookie == 0);
  1875. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1876. invalid_cookie) {
  1877. return false;
  1878. }
  1879. return true;
  1880. }
  1881. /**
  1882. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1883. * @soc: DP soc handle
  1884. * @vdev_id: id of DP vdev handle
  1885. * @nbuf: skb
  1886. * @tx_exc_metadata: Handle that holds exception path meta data
  1887. *
  1888. * Entry point for Core Tx layer (DP_TX) invoked from
  1889. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1890. *
  1891. * Return: NULL on success,
  1892. * nbuf when it fails to send
  1893. */
  1894. qdf_nbuf_t
  1895. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1896. qdf_nbuf_t nbuf,
  1897. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1898. {
  1899. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1900. qdf_ether_header_t *eh = NULL;
  1901. struct dp_tx_msdu_info_s msdu_info;
  1902. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  1903. DP_MOD_ID_TX_EXCEPTION);
  1904. if (qdf_unlikely(!vdev))
  1905. goto fail;
  1906. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1907. if (!tx_exc_metadata)
  1908. goto fail;
  1909. msdu_info.tid = tx_exc_metadata->tid;
  1910. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1911. dp_verbose_debug("skb %pM", nbuf->data);
  1912. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1913. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1914. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1915. "Invalid parameters in exception path");
  1916. goto fail;
  1917. }
  1918. /* Basic sanity checks for unsupported packets */
  1919. /* MESH mode */
  1920. if (qdf_unlikely(vdev->mesh_vdev)) {
  1921. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1922. "Mesh mode is not supported in exception path");
  1923. goto fail;
  1924. }
  1925. /* TSO or SG */
  1926. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1927. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1928. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1929. "TSO and SG are not supported in exception path");
  1930. goto fail;
  1931. }
  1932. /* RAW */
  1933. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1934. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1935. "Raw frame is not supported in exception path");
  1936. goto fail;
  1937. }
  1938. /* Mcast enhancement*/
  1939. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1940. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1941. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1942. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1943. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1944. }
  1945. }
  1946. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1947. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1948. qdf_nbuf_len(nbuf));
  1949. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1950. tx_exc_metadata->ppdu_cookie);
  1951. }
  1952. /*
  1953. * Get HW Queue to use for this frame.
  1954. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1955. * dedicated for data and 1 for command.
  1956. * "queue_id" maps to one hardware ring.
  1957. * With each ring, we also associate a unique Tx descriptor pool
  1958. * to minimize lock contention for these resources.
  1959. */
  1960. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1961. /*
  1962. * Check exception descriptors
  1963. */
  1964. if (dp_tx_exception_limit_check(vdev))
  1965. goto fail;
  1966. /* Single linear frame */
  1967. /*
  1968. * If nbuf is a simple linear frame, use send_single function to
  1969. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1970. * SRNG. There is no need to setup a MSDU extension descriptor.
  1971. */
  1972. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1973. tx_exc_metadata->peer_id, tx_exc_metadata);
  1974. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  1975. return nbuf;
  1976. fail:
  1977. if (vdev)
  1978. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  1979. dp_verbose_debug("pkt send failed");
  1980. return nbuf;
  1981. }
  1982. /**
  1983. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1984. * @soc: DP soc handle
  1985. * @vdev_id: DP vdev handle
  1986. * @nbuf: skb
  1987. *
  1988. * Entry point for Core Tx layer (DP_TX) invoked from
  1989. * hard_start_xmit in OSIF/HDD
  1990. *
  1991. * Return: NULL on success,
  1992. * nbuf when it fails to send
  1993. */
  1994. #ifdef MESH_MODE_SUPPORT
  1995. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1996. qdf_nbuf_t nbuf)
  1997. {
  1998. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1999. struct meta_hdr_s *mhdr;
  2000. qdf_nbuf_t nbuf_mesh = NULL;
  2001. qdf_nbuf_t nbuf_clone = NULL;
  2002. struct dp_vdev *vdev;
  2003. uint8_t no_enc_frame = 0;
  2004. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2005. if (!nbuf_mesh) {
  2006. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2007. "qdf_nbuf_unshare failed");
  2008. return nbuf;
  2009. }
  2010. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2011. if (!vdev) {
  2012. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2013. "vdev is NULL for vdev_id %d", vdev_id);
  2014. return nbuf;
  2015. }
  2016. nbuf = nbuf_mesh;
  2017. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2018. if ((vdev->sec_type != cdp_sec_type_none) &&
  2019. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2020. no_enc_frame = 1;
  2021. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2022. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2023. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2024. !no_enc_frame) {
  2025. nbuf_clone = qdf_nbuf_clone(nbuf);
  2026. if (!nbuf_clone) {
  2027. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2028. "qdf_nbuf_clone failed");
  2029. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2030. return nbuf;
  2031. }
  2032. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2033. }
  2034. if (nbuf_clone) {
  2035. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2036. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2037. } else {
  2038. qdf_nbuf_free(nbuf_clone);
  2039. }
  2040. }
  2041. if (no_enc_frame)
  2042. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2043. else
  2044. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2045. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2046. if ((!nbuf) && no_enc_frame) {
  2047. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2048. }
  2049. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2050. return nbuf;
  2051. }
  2052. #else
  2053. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2054. qdf_nbuf_t nbuf)
  2055. {
  2056. return dp_tx_send(soc, vdev_id, nbuf);
  2057. }
  2058. #endif
  2059. /**
  2060. * dp_tx_nawds_handler() - NAWDS handler
  2061. *
  2062. * @soc: DP soc handle
  2063. * @vdev_id: id of DP vdev handle
  2064. * @msdu_info: msdu_info required to create HTT metadata
  2065. * @nbuf: skb
  2066. *
  2067. * This API transfers the multicast frames with the peer id
  2068. * on NAWDS enabled peer.
  2069. * Return: none
  2070. */
  2071. static inline
  2072. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2073. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2074. {
  2075. struct dp_peer *peer = NULL;
  2076. qdf_nbuf_t nbuf_clone = NULL;
  2077. uint16_t peer_id = DP_INVALID_PEER;
  2078. uint16_t sa_peer_id = DP_INVALID_PEER;
  2079. struct dp_ast_entry *ast_entry = NULL;
  2080. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2081. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2082. qdf_spin_lock_bh(&soc->ast_lock);
  2083. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2084. (soc,
  2085. (uint8_t *)(eh->ether_shost),
  2086. vdev->pdev->pdev_id);
  2087. if (ast_entry)
  2088. sa_peer_id = ast_entry->peer_id;
  2089. qdf_spin_unlock_bh(&soc->ast_lock);
  2090. }
  2091. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2092. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2093. if (!peer->bss_peer && peer->nawds_enabled) {
  2094. peer_id = peer->peer_id;
  2095. /* Multicast packets needs to be
  2096. * dropped in case of intra bss forwarding
  2097. */
  2098. if (sa_peer_id == peer->peer_id) {
  2099. QDF_TRACE(QDF_MODULE_ID_DP,
  2100. QDF_TRACE_LEVEL_DEBUG,
  2101. " %s: multicast packet", __func__);
  2102. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2103. continue;
  2104. }
  2105. nbuf_clone = qdf_nbuf_clone(nbuf);
  2106. if (!nbuf_clone) {
  2107. QDF_TRACE(QDF_MODULE_ID_DP,
  2108. QDF_TRACE_LEVEL_ERROR,
  2109. FL("nbuf clone failed"));
  2110. break;
  2111. }
  2112. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2113. msdu_info, peer_id,
  2114. NULL);
  2115. if (nbuf_clone) {
  2116. QDF_TRACE(QDF_MODULE_ID_DP,
  2117. QDF_TRACE_LEVEL_DEBUG,
  2118. FL("pkt send failed"));
  2119. qdf_nbuf_free(nbuf_clone);
  2120. } else {
  2121. if (peer_id != DP_INVALID_PEER)
  2122. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2123. 1, qdf_nbuf_len(nbuf));
  2124. }
  2125. }
  2126. }
  2127. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2128. }
  2129. /**
  2130. * dp_tx_send() - Transmit a frame on a given VAP
  2131. * @soc: DP soc handle
  2132. * @vdev_id: id of DP vdev handle
  2133. * @nbuf: skb
  2134. *
  2135. * Entry point for Core Tx layer (DP_TX) invoked from
  2136. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2137. * cases
  2138. *
  2139. * Return: NULL on success,
  2140. * nbuf when it fails to send
  2141. */
  2142. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2143. qdf_nbuf_t nbuf)
  2144. {
  2145. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2146. uint16_t peer_id = HTT_INVALID_PEER;
  2147. /*
  2148. * doing a memzero is causing additional function call overhead
  2149. * so doing static stack clearing
  2150. */
  2151. struct dp_tx_msdu_info_s msdu_info = {0};
  2152. struct dp_vdev *vdev = NULL;
  2153. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2154. return nbuf;
  2155. /*
  2156. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2157. * this in per packet path.
  2158. *
  2159. * As in this path vdev memory is already protected with netdev
  2160. * tx lock
  2161. */
  2162. vdev = soc->vdev_id_map[vdev_id];
  2163. if (qdf_unlikely(!vdev))
  2164. return nbuf;
  2165. dp_verbose_debug("skb %pM", nbuf->data);
  2166. /*
  2167. * Set Default Host TID value to invalid TID
  2168. * (TID override disabled)
  2169. */
  2170. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2171. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2172. if (qdf_unlikely(vdev->mesh_vdev)) {
  2173. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2174. &msdu_info);
  2175. if (!nbuf_mesh) {
  2176. dp_verbose_debug("Extracting mesh metadata failed");
  2177. return nbuf;
  2178. }
  2179. nbuf = nbuf_mesh;
  2180. }
  2181. /*
  2182. * Get HW Queue to use for this frame.
  2183. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2184. * dedicated for data and 1 for command.
  2185. * "queue_id" maps to one hardware ring.
  2186. * With each ring, we also associate a unique Tx descriptor pool
  2187. * to minimize lock contention for these resources.
  2188. */
  2189. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2190. /*
  2191. * TCL H/W supports 2 DSCP-TID mapping tables.
  2192. * Table 1 - Default DSCP-TID mapping table
  2193. * Table 2 - 1 DSCP-TID override table
  2194. *
  2195. * If we need a different DSCP-TID mapping for this vap,
  2196. * call tid_classify to extract DSCP/ToS from frame and
  2197. * map to a TID and store in msdu_info. This is later used
  2198. * to fill in TCL Input descriptor (per-packet TID override).
  2199. */
  2200. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2201. /*
  2202. * Classify the frame and call corresponding
  2203. * "prepare" function which extracts the segment (TSO)
  2204. * and fragmentation information (for TSO , SG, ME, or Raw)
  2205. * into MSDU_INFO structure which is later used to fill
  2206. * SW and HW descriptors.
  2207. */
  2208. if (qdf_nbuf_is_tso(nbuf)) {
  2209. dp_verbose_debug("TSO frame %pK", vdev);
  2210. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2211. qdf_nbuf_len(nbuf));
  2212. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2213. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2214. qdf_nbuf_len(nbuf));
  2215. return nbuf;
  2216. }
  2217. goto send_multiple;
  2218. }
  2219. /* SG */
  2220. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2221. struct dp_tx_seg_info_s seg_info = {0};
  2222. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2223. if (!nbuf)
  2224. return NULL;
  2225. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2226. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2227. qdf_nbuf_len(nbuf));
  2228. goto send_multiple;
  2229. }
  2230. #ifdef ATH_SUPPORT_IQUE
  2231. /* Mcast to Ucast Conversion*/
  2232. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2233. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2234. qdf_nbuf_data(nbuf);
  2235. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2236. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2237. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2238. DP_STATS_INC_PKT(vdev,
  2239. tx_i.mcast_en.mcast_pkt, 1,
  2240. qdf_nbuf_len(nbuf));
  2241. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2242. QDF_STATUS_SUCCESS) {
  2243. return NULL;
  2244. }
  2245. }
  2246. }
  2247. #endif
  2248. /* RAW */
  2249. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2250. struct dp_tx_seg_info_s seg_info = {0};
  2251. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2252. if (!nbuf)
  2253. return NULL;
  2254. dp_verbose_debug("Raw frame %pK", vdev);
  2255. goto send_multiple;
  2256. }
  2257. if (qdf_unlikely(vdev->nawds_enabled)) {
  2258. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2259. qdf_nbuf_data(nbuf);
  2260. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2261. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2262. peer_id = DP_INVALID_PEER;
  2263. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2264. 1, qdf_nbuf_len(nbuf));
  2265. }
  2266. /* Single linear frame */
  2267. /*
  2268. * If nbuf is a simple linear frame, use send_single function to
  2269. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2270. * SRNG. There is no need to setup a MSDU extension descriptor.
  2271. */
  2272. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2273. return nbuf;
  2274. send_multiple:
  2275. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2276. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2277. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2278. return nbuf;
  2279. }
  2280. /**
  2281. * dp_tx_reinject_handler() - Tx Reinject Handler
  2282. * @tx_desc: software descriptor head pointer
  2283. * @status : Tx completion status from HTT descriptor
  2284. *
  2285. * This function reinjects frames back to Target.
  2286. * Todo - Host queue needs to be added
  2287. *
  2288. * Return: none
  2289. */
  2290. static
  2291. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2292. {
  2293. struct dp_vdev *vdev;
  2294. struct dp_peer *peer = NULL;
  2295. uint32_t peer_id = HTT_INVALID_PEER;
  2296. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2297. qdf_nbuf_t nbuf_copy = NULL;
  2298. struct dp_tx_msdu_info_s msdu_info;
  2299. struct dp_soc *soc = NULL;
  2300. #ifdef WDS_VENDOR_EXTENSION
  2301. int is_mcast = 0, is_ucast = 0;
  2302. int num_peers_3addr = 0;
  2303. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2304. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2305. #endif
  2306. vdev = tx_desc->vdev;
  2307. soc = vdev->pdev->soc;
  2308. qdf_assert(vdev);
  2309. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2310. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2311. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2312. "%s Tx reinject path", __func__);
  2313. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2314. qdf_nbuf_len(tx_desc->nbuf));
  2315. #ifdef WDS_VENDOR_EXTENSION
  2316. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2317. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2318. } else {
  2319. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2320. }
  2321. is_ucast = !is_mcast;
  2322. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2323. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2324. if (peer->bss_peer)
  2325. continue;
  2326. /* Detect wds peers that use 3-addr framing for mcast.
  2327. * if there are any, the bss_peer is used to send the
  2328. * the mcast frame using 3-addr format. all wds enabled
  2329. * peers that use 4-addr framing for mcast frames will
  2330. * be duplicated and sent as 4-addr frames below.
  2331. */
  2332. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2333. num_peers_3addr = 1;
  2334. break;
  2335. }
  2336. }
  2337. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2338. #endif
  2339. if (qdf_unlikely(vdev->mesh_vdev)) {
  2340. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2341. } else {
  2342. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2343. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2344. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2345. #ifdef WDS_VENDOR_EXTENSION
  2346. /*
  2347. * . if 3-addr STA, then send on BSS Peer
  2348. * . if Peer WDS enabled and accept 4-addr mcast,
  2349. * send mcast on that peer only
  2350. * . if Peer WDS enabled and accept 4-addr ucast,
  2351. * send ucast on that peer only
  2352. */
  2353. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2354. (peer->wds_enabled &&
  2355. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2356. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2357. #else
  2358. ((peer->bss_peer &&
  2359. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2360. #endif
  2361. peer_id = DP_INVALID_PEER;
  2362. nbuf_copy = qdf_nbuf_copy(nbuf);
  2363. if (!nbuf_copy) {
  2364. QDF_TRACE(QDF_MODULE_ID_DP,
  2365. QDF_TRACE_LEVEL_DEBUG,
  2366. FL("nbuf copy failed"));
  2367. break;
  2368. }
  2369. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2370. nbuf_copy,
  2371. &msdu_info,
  2372. peer_id,
  2373. NULL);
  2374. if (nbuf_copy) {
  2375. QDF_TRACE(QDF_MODULE_ID_DP,
  2376. QDF_TRACE_LEVEL_DEBUG,
  2377. FL("pkt send failed"));
  2378. qdf_nbuf_free(nbuf_copy);
  2379. }
  2380. }
  2381. }
  2382. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2383. }
  2384. qdf_nbuf_free(nbuf);
  2385. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2386. }
  2387. /**
  2388. * dp_tx_inspect_handler() - Tx Inspect Handler
  2389. * @tx_desc: software descriptor head pointer
  2390. * @status : Tx completion status from HTT descriptor
  2391. *
  2392. * Handles Tx frames sent back to Host for inspection
  2393. * (ProxyARP)
  2394. *
  2395. * Return: none
  2396. */
  2397. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2398. {
  2399. struct dp_soc *soc;
  2400. struct dp_pdev *pdev = tx_desc->pdev;
  2401. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2402. "%s Tx inspect path",
  2403. __func__);
  2404. qdf_assert(pdev);
  2405. soc = pdev->soc;
  2406. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2407. qdf_nbuf_len(tx_desc->nbuf));
  2408. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2409. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2410. }
  2411. #ifdef FEATURE_PERPKT_INFO
  2412. /**
  2413. * dp_get_completion_indication_for_stack() - send completion to stack
  2414. * @soc : dp_soc handle
  2415. * @pdev: dp_pdev handle
  2416. * @peer: dp peer handle
  2417. * @ts: transmit completion status structure
  2418. * @netbuf: Buffer pointer for free
  2419. *
  2420. * This function is used for indication whether buffer needs to be
  2421. * sent to stack for freeing or not
  2422. */
  2423. QDF_STATUS
  2424. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2425. struct dp_pdev *pdev,
  2426. struct dp_peer *peer,
  2427. struct hal_tx_completion_status *ts,
  2428. qdf_nbuf_t netbuf,
  2429. uint64_t time_latency)
  2430. {
  2431. struct tx_capture_hdr *ppdu_hdr;
  2432. uint16_t peer_id = ts->peer_id;
  2433. uint32_t ppdu_id = ts->ppdu_id;
  2434. uint8_t first_msdu = ts->first_msdu;
  2435. uint8_t last_msdu = ts->last_msdu;
  2436. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2437. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2438. !pdev->latency_capture_enable))
  2439. return QDF_STATUS_E_NOSUPPORT;
  2440. if (!peer) {
  2441. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2442. FL("Peer Invalid"));
  2443. return QDF_STATUS_E_INVAL;
  2444. }
  2445. if (pdev->mcopy_mode) {
  2446. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2447. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2448. * for each MPDU
  2449. */
  2450. if (pdev->mcopy_mode == M_COPY) {
  2451. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2452. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2453. return QDF_STATUS_E_INVAL;
  2454. }
  2455. }
  2456. if (!first_msdu)
  2457. return QDF_STATUS_E_INVAL;
  2458. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2459. pdev->m_copy_id.tx_peer_id = peer_id;
  2460. }
  2461. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2462. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2463. if (!netbuf) {
  2464. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2465. FL("No headroom"));
  2466. return QDF_STATUS_E_NOMEM;
  2467. }
  2468. }
  2469. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  2470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2471. FL("No headroom"));
  2472. return QDF_STATUS_E_NOMEM;
  2473. }
  2474. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2475. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2476. QDF_MAC_ADDR_SIZE);
  2477. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2478. QDF_MAC_ADDR_SIZE);
  2479. ppdu_hdr->ppdu_id = ppdu_id;
  2480. ppdu_hdr->peer_id = peer_id;
  2481. ppdu_hdr->first_msdu = first_msdu;
  2482. ppdu_hdr->last_msdu = last_msdu;
  2483. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2484. ppdu_hdr->tsf = ts->tsf;
  2485. ppdu_hdr->time_latency = time_latency;
  2486. }
  2487. return QDF_STATUS_SUCCESS;
  2488. }
  2489. /**
  2490. * dp_send_completion_to_stack() - send completion to stack
  2491. * @soc : dp_soc handle
  2492. * @pdev: dp_pdev handle
  2493. * @peer_id: peer_id of the peer for which completion came
  2494. * @ppdu_id: ppdu_id
  2495. * @netbuf: Buffer pointer for free
  2496. *
  2497. * This function is used to send completion to stack
  2498. * to free buffer
  2499. */
  2500. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2501. uint16_t peer_id, uint32_t ppdu_id,
  2502. qdf_nbuf_t netbuf)
  2503. {
  2504. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2505. netbuf, peer_id,
  2506. WDI_NO_VAL, pdev->pdev_id);
  2507. }
  2508. #else
  2509. static QDF_STATUS
  2510. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2511. struct dp_pdev *pdev,
  2512. struct dp_peer *peer,
  2513. struct hal_tx_completion_status *ts,
  2514. qdf_nbuf_t netbuf,
  2515. uint64_t time_latency)
  2516. {
  2517. return QDF_STATUS_E_NOSUPPORT;
  2518. }
  2519. static void
  2520. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2521. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2522. {
  2523. }
  2524. #endif
  2525. /**
  2526. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2527. * @soc: Soc handle
  2528. * @desc: software Tx descriptor to be processed
  2529. *
  2530. * Return: none
  2531. */
  2532. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2533. struct dp_tx_desc_s *desc)
  2534. {
  2535. struct dp_vdev *vdev = desc->vdev;
  2536. qdf_nbuf_t nbuf = desc->nbuf;
  2537. /* nbuf already freed in vdev detach path */
  2538. if (!nbuf)
  2539. return;
  2540. /* If it is TDLS mgmt, don't unmap or free the frame */
  2541. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2542. return dp_non_std_tx_comp_free_buff(soc, desc, vdev);
  2543. /* 0 : MSDU buffer, 1 : MLE */
  2544. if (desc->msdu_ext_desc) {
  2545. /* TSO free */
  2546. if (hal_tx_ext_desc_get_tso_enable(
  2547. desc->msdu_ext_desc->vaddr)) {
  2548. /* unmap eash TSO seg before free the nbuf */
  2549. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2550. desc->tso_num_desc);
  2551. qdf_nbuf_free(nbuf);
  2552. return;
  2553. }
  2554. }
  2555. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2556. QDF_DMA_TO_DEVICE, nbuf->len);
  2557. if (qdf_unlikely(!vdev)) {
  2558. qdf_nbuf_free(nbuf);
  2559. return;
  2560. }
  2561. if (qdf_likely(!vdev->mesh_vdev))
  2562. qdf_nbuf_free(nbuf);
  2563. else {
  2564. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2565. qdf_nbuf_free(nbuf);
  2566. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2567. } else
  2568. vdev->osif_tx_free_ext((nbuf));
  2569. }
  2570. }
  2571. #ifdef MESH_MODE_SUPPORT
  2572. /**
  2573. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2574. * in mesh meta header
  2575. * @tx_desc: software descriptor head pointer
  2576. * @ts: pointer to tx completion stats
  2577. * Return: none
  2578. */
  2579. static
  2580. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2581. struct hal_tx_completion_status *ts)
  2582. {
  2583. struct meta_hdr_s *mhdr;
  2584. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2585. if (!tx_desc->msdu_ext_desc) {
  2586. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2587. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2588. "netbuf %pK offset %d",
  2589. netbuf, tx_desc->pkt_offset);
  2590. return;
  2591. }
  2592. }
  2593. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2594. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2595. "netbuf %pK offset %lu", netbuf,
  2596. sizeof(struct meta_hdr_s));
  2597. return;
  2598. }
  2599. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2600. mhdr->rssi = ts->ack_frame_rssi;
  2601. mhdr->band = tx_desc->pdev->operating_channel.band;
  2602. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2603. }
  2604. #else
  2605. static
  2606. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2607. struct hal_tx_completion_status *ts)
  2608. {
  2609. }
  2610. #endif
  2611. #ifdef QCA_PEER_EXT_STATS
  2612. /*
  2613. * dp_tx_compute_tid_delay() - Compute per TID delay
  2614. * @stats: Per TID delay stats
  2615. * @tx_desc: Software Tx descriptor
  2616. *
  2617. * Compute the software enqueue and hw enqueue delays and
  2618. * update the respective histograms
  2619. *
  2620. * Return: void
  2621. */
  2622. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  2623. struct dp_tx_desc_s *tx_desc)
  2624. {
  2625. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  2626. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2627. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  2628. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2629. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2630. timestamp_hw_enqueue = tx_desc->timestamp;
  2631. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2632. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2633. timestamp_hw_enqueue);
  2634. /*
  2635. * Update the Tx software enqueue delay and HW enque-Completion delay.
  2636. */
  2637. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  2638. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  2639. }
  2640. /*
  2641. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  2642. * @peer: DP peer context
  2643. * @tx_desc: Tx software descriptor
  2644. * @tid: Transmission ID
  2645. * @ring_id: Rx CPU context ID/CPU_ID
  2646. *
  2647. * Update the peer extended stats. These are enhanced other
  2648. * delay stats per msdu level.
  2649. *
  2650. * Return: void
  2651. */
  2652. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2653. struct dp_tx_desc_s *tx_desc,
  2654. uint8_t tid, uint8_t ring_id)
  2655. {
  2656. struct dp_pdev *pdev = peer->vdev->pdev;
  2657. struct dp_soc *soc = NULL;
  2658. struct cdp_peer_ext_stats *pext_stats = NULL;
  2659. soc = pdev->soc;
  2660. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  2661. return;
  2662. pext_stats = peer->pext_stats;
  2663. qdf_assert(pext_stats);
  2664. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  2665. /*
  2666. * For non-TID packets use the TID 9
  2667. */
  2668. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2669. tid = CDP_MAX_DATA_TIDS - 1;
  2670. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  2671. tx_desc);
  2672. }
  2673. #else
  2674. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2675. struct dp_tx_desc_s *tx_desc,
  2676. uint8_t tid, uint8_t ring_id)
  2677. {
  2678. }
  2679. #endif
  2680. /**
  2681. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2682. * to pass in correct fields
  2683. *
  2684. * @vdev: pdev handle
  2685. * @tx_desc: tx descriptor
  2686. * @tid: tid value
  2687. * @ring_id: TCL or WBM ring number for transmit path
  2688. * Return: none
  2689. */
  2690. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2691. struct dp_tx_desc_s *tx_desc,
  2692. uint8_t tid, uint8_t ring_id)
  2693. {
  2694. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2695. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2696. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2697. return;
  2698. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2699. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2700. timestamp_hw_enqueue = tx_desc->timestamp;
  2701. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2702. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2703. timestamp_hw_enqueue);
  2704. interframe_delay = (uint32_t)(timestamp_ingress -
  2705. vdev->prev_tx_enq_tstamp);
  2706. /*
  2707. * Delay in software enqueue
  2708. */
  2709. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2710. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2711. /*
  2712. * Delay between packet enqueued to HW and Tx completion
  2713. */
  2714. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2715. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2716. /*
  2717. * Update interframe delay stats calculated at hardstart receive point.
  2718. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2719. * interframe delay will not be calculate correctly for 1st frame.
  2720. * On the other side, this will help in avoiding extra per packet check
  2721. * of !vdev->prev_tx_enq_tstamp.
  2722. */
  2723. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2724. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2725. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2726. }
  2727. #ifdef DISABLE_DP_STATS
  2728. static
  2729. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2730. {
  2731. }
  2732. #else
  2733. static
  2734. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2735. {
  2736. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  2737. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  2738. if (subtype != QDF_PROTO_INVALID)
  2739. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  2740. }
  2741. #endif
  2742. /**
  2743. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2744. * per wbm ring
  2745. *
  2746. * @tx_desc: software descriptor head pointer
  2747. * @ts: Tx completion status
  2748. * @peer: peer handle
  2749. * @ring_id: ring number
  2750. *
  2751. * Return: None
  2752. */
  2753. static inline void
  2754. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2755. struct hal_tx_completion_status *ts,
  2756. struct dp_peer *peer, uint8_t ring_id)
  2757. {
  2758. struct dp_pdev *pdev = peer->vdev->pdev;
  2759. struct dp_soc *soc = NULL;
  2760. uint8_t mcs, pkt_type;
  2761. uint8_t tid = ts->tid;
  2762. uint32_t length;
  2763. struct cdp_tid_tx_stats *tid_stats;
  2764. if (!pdev)
  2765. return;
  2766. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2767. tid = CDP_MAX_DATA_TIDS - 1;
  2768. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2769. soc = pdev->soc;
  2770. mcs = ts->mcs;
  2771. pkt_type = ts->pkt_type;
  2772. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2773. dp_err("Release source is not from TQM");
  2774. return;
  2775. }
  2776. length = qdf_nbuf_len(tx_desc->nbuf);
  2777. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2778. if (qdf_unlikely(pdev->delay_stats_flag))
  2779. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2780. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2781. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2782. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2783. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2784. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2785. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2786. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2787. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2788. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2789. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2790. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2791. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2792. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2793. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2794. /*
  2795. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2796. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2797. * are no completions for failed cases. Hence updating tx_failed from
  2798. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2799. * then this has to be removed
  2800. */
  2801. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2802. peer->stats.tx.dropped.fw_rem_notx +
  2803. peer->stats.tx.dropped.fw_rem_tx +
  2804. peer->stats.tx.dropped.age_out +
  2805. peer->stats.tx.dropped.fw_reason1 +
  2806. peer->stats.tx.dropped.fw_reason2 +
  2807. peer->stats.tx.dropped.fw_reason3;
  2808. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2809. tid_stats->tqm_status_cnt[ts->status]++;
  2810. }
  2811. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2812. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  2813. return;
  2814. }
  2815. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2816. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2817. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2818. /*
  2819. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2820. * Return from here if HTT PPDU events are enabled.
  2821. */
  2822. if (!(soc->process_tx_status))
  2823. return;
  2824. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2825. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2826. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2827. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2828. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2829. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2830. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2831. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2832. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2833. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2834. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2835. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2836. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2837. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2838. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2839. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2840. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2841. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2842. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2843. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2844. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2845. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2846. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2847. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2848. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2849. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2850. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2851. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2852. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2853. &peer->stats, ts->peer_id,
  2854. UPDATE_PEER_STATS, pdev->pdev_id);
  2855. #endif
  2856. }
  2857. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2858. /**
  2859. * dp_tx_flow_pool_lock() - take flow pool lock
  2860. * @soc: core txrx main context
  2861. * @tx_desc: tx desc
  2862. *
  2863. * Return: None
  2864. */
  2865. static inline
  2866. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2867. struct dp_tx_desc_s *tx_desc)
  2868. {
  2869. struct dp_tx_desc_pool_s *pool;
  2870. uint8_t desc_pool_id;
  2871. desc_pool_id = tx_desc->pool_id;
  2872. pool = &soc->tx_desc[desc_pool_id];
  2873. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2874. }
  2875. /**
  2876. * dp_tx_flow_pool_unlock() - release flow pool lock
  2877. * @soc: core txrx main context
  2878. * @tx_desc: tx desc
  2879. *
  2880. * Return: None
  2881. */
  2882. static inline
  2883. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2884. struct dp_tx_desc_s *tx_desc)
  2885. {
  2886. struct dp_tx_desc_pool_s *pool;
  2887. uint8_t desc_pool_id;
  2888. desc_pool_id = tx_desc->pool_id;
  2889. pool = &soc->tx_desc[desc_pool_id];
  2890. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2891. }
  2892. #else
  2893. static inline
  2894. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2895. {
  2896. }
  2897. static inline
  2898. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2899. {
  2900. }
  2901. #endif
  2902. /**
  2903. * dp_tx_notify_completion() - Notify tx completion for this desc
  2904. * @soc: core txrx main context
  2905. * @tx_desc: tx desc
  2906. * @netbuf: buffer
  2907. * @status: tx status
  2908. *
  2909. * Return: none
  2910. */
  2911. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2912. struct dp_tx_desc_s *tx_desc,
  2913. qdf_nbuf_t netbuf,
  2914. uint8_t status)
  2915. {
  2916. void *osif_dev;
  2917. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2918. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  2919. qdf_assert(tx_desc);
  2920. dp_tx_flow_pool_lock(soc, tx_desc);
  2921. if (!tx_desc->vdev ||
  2922. !tx_desc->vdev->osif_vdev) {
  2923. dp_tx_flow_pool_unlock(soc, tx_desc);
  2924. return;
  2925. }
  2926. osif_dev = tx_desc->vdev->osif_vdev;
  2927. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2928. dp_tx_flow_pool_unlock(soc, tx_desc);
  2929. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  2930. flag |= BIT(QDF_TX_RX_STATUS_OK);
  2931. if (tx_compl_cbk)
  2932. tx_compl_cbk(netbuf, osif_dev, flag);
  2933. }
  2934. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2935. * @pdev: pdev handle
  2936. * @tid: tid value
  2937. * @txdesc_ts: timestamp from txdesc
  2938. * @ppdu_id: ppdu id
  2939. *
  2940. * Return: none
  2941. */
  2942. #ifdef FEATURE_PERPKT_INFO
  2943. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2944. struct dp_peer *peer,
  2945. uint8_t tid,
  2946. uint64_t txdesc_ts,
  2947. uint32_t ppdu_id)
  2948. {
  2949. uint64_t delta_ms;
  2950. struct cdp_tx_sojourn_stats *sojourn_stats;
  2951. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2952. return;
  2953. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2954. tid >= CDP_DATA_TID_MAX))
  2955. return;
  2956. if (qdf_unlikely(!pdev->sojourn_buf))
  2957. return;
  2958. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2959. qdf_nbuf_data(pdev->sojourn_buf);
  2960. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2961. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2962. txdesc_ts;
  2963. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2964. delta_ms);
  2965. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2966. sojourn_stats->num_msdus[tid] = 1;
  2967. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2968. peer->avg_sojourn_msdu[tid].internal;
  2969. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2970. pdev->sojourn_buf, HTT_INVALID_PEER,
  2971. WDI_NO_VAL, pdev->pdev_id);
  2972. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2973. sojourn_stats->num_msdus[tid] = 0;
  2974. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2975. }
  2976. #else
  2977. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2978. struct dp_peer *peer,
  2979. uint8_t tid,
  2980. uint64_t txdesc_ts,
  2981. uint32_t ppdu_id)
  2982. {
  2983. }
  2984. #endif
  2985. /**
  2986. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2987. * @soc: DP Soc handle
  2988. * @tx_desc: software Tx descriptor
  2989. * @ts : Tx completion status from HAL/HTT descriptor
  2990. *
  2991. * Return: none
  2992. */
  2993. static inline void
  2994. dp_tx_comp_process_desc(struct dp_soc *soc,
  2995. struct dp_tx_desc_s *desc,
  2996. struct hal_tx_completion_status *ts,
  2997. struct dp_peer *peer)
  2998. {
  2999. uint64_t time_latency = 0;
  3000. /*
  3001. * m_copy/tx_capture modes are not supported for
  3002. * scatter gather packets
  3003. */
  3004. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3005. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3006. desc->timestamp);
  3007. }
  3008. if (!(desc->msdu_ext_desc)) {
  3009. if (QDF_STATUS_SUCCESS ==
  3010. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3011. return;
  3012. }
  3013. if (QDF_STATUS_SUCCESS ==
  3014. dp_get_completion_indication_for_stack(soc,
  3015. desc->pdev,
  3016. peer, ts,
  3017. desc->nbuf,
  3018. time_latency)) {
  3019. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3020. QDF_DMA_TO_DEVICE,
  3021. desc->nbuf->len);
  3022. dp_send_completion_to_stack(soc,
  3023. desc->pdev,
  3024. ts->peer_id,
  3025. ts->ppdu_id,
  3026. desc->nbuf);
  3027. return;
  3028. }
  3029. }
  3030. dp_tx_comp_free_buf(soc, desc);
  3031. }
  3032. #ifdef DISABLE_DP_STATS
  3033. /**
  3034. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3035. * @soc: core txrx main context
  3036. * @tx_desc: tx desc
  3037. * @status: tx status
  3038. *
  3039. * Return: none
  3040. */
  3041. static inline
  3042. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3043. struct dp_tx_desc_s *tx_desc,
  3044. uint8_t status)
  3045. {
  3046. }
  3047. #else
  3048. static inline
  3049. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3050. struct dp_tx_desc_s *tx_desc,
  3051. uint8_t status)
  3052. {
  3053. void *osif_dev;
  3054. ol_txrx_stats_rx_fp stats_cbk;
  3055. uint8_t pkt_type;
  3056. qdf_assert(tx_desc);
  3057. if (!tx_desc->vdev ||
  3058. !tx_desc->vdev->osif_vdev ||
  3059. !tx_desc->vdev->stats_cb)
  3060. return;
  3061. osif_dev = tx_desc->vdev->osif_vdev;
  3062. stats_cbk = tx_desc->vdev->stats_cb;
  3063. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3064. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3065. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3066. &pkt_type);
  3067. }
  3068. #endif
  3069. /**
  3070. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3071. * @soc: DP soc handle
  3072. * @tx_desc: software descriptor head pointer
  3073. * @ts: Tx completion status
  3074. * @peer: peer handle
  3075. * @ring_id: ring number
  3076. *
  3077. * Return: none
  3078. */
  3079. static inline
  3080. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3081. struct dp_tx_desc_s *tx_desc,
  3082. struct hal_tx_completion_status *ts,
  3083. struct dp_peer *peer, uint8_t ring_id)
  3084. {
  3085. uint32_t length;
  3086. qdf_ether_header_t *eh;
  3087. struct dp_vdev *vdev = tx_desc->vdev;
  3088. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3089. uint8_t dp_status;
  3090. if (!vdev || !nbuf) {
  3091. dp_info_rl("invalid tx descriptor. vdev or nbuf NULL");
  3092. goto out;
  3093. }
  3094. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3095. length = qdf_nbuf_len(nbuf);
  3096. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3097. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3098. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3099. QDF_TRACE_DEFAULT_PDEV_ID,
  3100. qdf_nbuf_data_addr(nbuf),
  3101. sizeof(qdf_nbuf_data(nbuf)),
  3102. tx_desc->id,
  3103. dp_status));
  3104. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3105. "-------------------- \n"
  3106. "Tx Completion Stats: \n"
  3107. "-------------------- \n"
  3108. "ack_frame_rssi = %d \n"
  3109. "first_msdu = %d \n"
  3110. "last_msdu = %d \n"
  3111. "msdu_part_of_amsdu = %d \n"
  3112. "rate_stats valid = %d \n"
  3113. "bw = %d \n"
  3114. "pkt_type = %d \n"
  3115. "stbc = %d \n"
  3116. "ldpc = %d \n"
  3117. "sgi = %d \n"
  3118. "mcs = %d \n"
  3119. "ofdma = %d \n"
  3120. "tones_in_ru = %d \n"
  3121. "tsf = %d \n"
  3122. "ppdu_id = %d \n"
  3123. "transmit_cnt = %d \n"
  3124. "tid = %d \n"
  3125. "peer_id = %d\n",
  3126. ts->ack_frame_rssi, ts->first_msdu,
  3127. ts->last_msdu, ts->msdu_part_of_amsdu,
  3128. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3129. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3130. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3131. ts->transmit_cnt, ts->tid, ts->peer_id);
  3132. /* Update SoC level stats */
  3133. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3134. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3135. if (!peer) {
  3136. dp_err_rl("peer is null or deletion in progress");
  3137. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3138. goto out;
  3139. }
  3140. dp_tx_update_connectivity_stats(soc, tx_desc, ts->status);
  3141. /* Update per-packet stats for mesh mode */
  3142. if (qdf_unlikely(vdev->mesh_vdev) &&
  3143. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3144. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3145. /* Update peer level stats */
  3146. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3147. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3148. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3149. if ((peer->vdev->tx_encap_type ==
  3150. htt_cmn_pkt_type_ethernet) &&
  3151. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3152. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3153. }
  3154. }
  3155. } else {
  3156. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3157. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3158. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3159. if (qdf_unlikely(peer->in_twt)) {
  3160. DP_STATS_INC_PKT(peer,
  3161. tx.tx_success_twt,
  3162. 1, length);
  3163. }
  3164. }
  3165. }
  3166. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3167. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3168. #ifdef QCA_SUPPORT_RDK_STATS
  3169. if (soc->wlanstats_enabled)
  3170. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3171. tx_desc->timestamp,
  3172. ts->ppdu_id);
  3173. #endif
  3174. out:
  3175. return;
  3176. }
  3177. /**
  3178. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3179. * @soc: core txrx main context
  3180. * @comp_head: software descriptor head pointer
  3181. * @ring_id: ring number
  3182. *
  3183. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3184. * and release the software descriptors after processing is complete
  3185. *
  3186. * Return: none
  3187. */
  3188. static void
  3189. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3190. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3191. {
  3192. struct dp_tx_desc_s *desc;
  3193. struct dp_tx_desc_s *next;
  3194. struct hal_tx_completion_status ts;
  3195. struct dp_peer *peer;
  3196. qdf_nbuf_t netbuf;
  3197. desc = comp_head;
  3198. while (desc) {
  3199. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3200. struct dp_pdev *pdev = desc->pdev;
  3201. peer = dp_peer_get_ref_by_id(soc, desc->peer_id,
  3202. DP_MOD_ID_TX_COMP);
  3203. if (qdf_likely(peer)) {
  3204. /*
  3205. * Increment peer statistics
  3206. * Minimal statistics update done here
  3207. */
  3208. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3209. desc->length);
  3210. if (desc->tx_status !=
  3211. HAL_TX_TQM_RR_FRAME_ACKED)
  3212. peer->stats.tx.tx_failed++;
  3213. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3214. }
  3215. qdf_assert(pdev);
  3216. dp_tx_outstanding_dec(pdev);
  3217. /*
  3218. * Calling a QDF WRAPPER here is creating signifcant
  3219. * performance impact so avoided the wrapper call here
  3220. */
  3221. next = desc->next;
  3222. qdf_mem_unmap_nbytes_single(soc->osdev,
  3223. desc->dma_addr,
  3224. QDF_DMA_TO_DEVICE,
  3225. desc->length);
  3226. qdf_nbuf_free(desc->nbuf);
  3227. dp_tx_desc_free(soc, desc, desc->pool_id);
  3228. desc = next;
  3229. continue;
  3230. }
  3231. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3232. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3233. DP_MOD_ID_TX_COMP);
  3234. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3235. netbuf = desc->nbuf;
  3236. /* check tx complete notification */
  3237. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3238. dp_tx_notify_completion(soc, desc, netbuf, ts.status);
  3239. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3240. if (peer)
  3241. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3242. next = desc->next;
  3243. dp_tx_desc_release(desc, desc->pool_id);
  3244. desc = next;
  3245. }
  3246. }
  3247. /**
  3248. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3249. * @tx_desc: software descriptor head pointer
  3250. * @status : Tx completion status from HTT descriptor
  3251. * @ring_id: ring number
  3252. *
  3253. * This function will process HTT Tx indication messages from Target
  3254. *
  3255. * Return: none
  3256. */
  3257. static
  3258. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3259. uint8_t ring_id)
  3260. {
  3261. uint8_t tx_status;
  3262. struct dp_pdev *pdev;
  3263. struct dp_vdev *vdev;
  3264. struct dp_soc *soc;
  3265. struct hal_tx_completion_status ts = {0};
  3266. uint32_t *htt_desc = (uint32_t *)status;
  3267. struct dp_peer *peer;
  3268. struct cdp_tid_tx_stats *tid_stats = NULL;
  3269. struct htt_soc *htt_handle;
  3270. /*
  3271. * If the descriptor is already freed in vdev_detach,
  3272. * continue to next descriptor
  3273. */
  3274. if (!tx_desc->vdev && !tx_desc->flags) {
  3275. QDF_TRACE(QDF_MODULE_ID_DP,
  3276. QDF_TRACE_LEVEL_INFO,
  3277. "Descriptor freed in vdev_detach %d",
  3278. tx_desc->id);
  3279. return;
  3280. }
  3281. pdev = tx_desc->pdev;
  3282. soc = pdev->soc;
  3283. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3284. QDF_TRACE(QDF_MODULE_ID_DP,
  3285. QDF_TRACE_LEVEL_INFO,
  3286. "pdev in down state %d",
  3287. tx_desc->id);
  3288. dp_tx_comp_free_buf(soc, tx_desc);
  3289. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3290. return;
  3291. }
  3292. qdf_assert(tx_desc->pdev);
  3293. vdev = tx_desc->vdev;
  3294. if (!vdev)
  3295. return;
  3296. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3297. htt_handle = (struct htt_soc *)soc->htt_handle;
  3298. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3299. switch (tx_status) {
  3300. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3301. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3302. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3303. {
  3304. uint8_t tid;
  3305. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3306. ts.peer_id =
  3307. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3308. htt_desc[2]);
  3309. ts.tid =
  3310. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3311. htt_desc[2]);
  3312. } else {
  3313. ts.peer_id = HTT_INVALID_PEER;
  3314. ts.tid = HTT_INVALID_TID;
  3315. }
  3316. ts.ppdu_id =
  3317. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3318. htt_desc[1]);
  3319. ts.ack_frame_rssi =
  3320. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3321. htt_desc[1]);
  3322. ts.tsf = htt_desc[3];
  3323. ts.first_msdu = 1;
  3324. ts.last_msdu = 1;
  3325. tid = ts.tid;
  3326. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3327. tid = CDP_MAX_DATA_TIDS - 1;
  3328. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3329. if (qdf_unlikely(pdev->delay_stats_flag))
  3330. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3331. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3332. tid_stats->htt_status_cnt[tx_status]++;
  3333. }
  3334. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3335. DP_MOD_ID_TX_COMP);
  3336. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3337. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3338. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3339. if (qdf_likely(peer))
  3340. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3341. break;
  3342. }
  3343. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3344. {
  3345. dp_tx_reinject_handler(tx_desc, status);
  3346. break;
  3347. }
  3348. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3349. {
  3350. dp_tx_inspect_handler(tx_desc, status);
  3351. break;
  3352. }
  3353. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3354. {
  3355. dp_tx_mec_handler(vdev, status);
  3356. break;
  3357. }
  3358. default:
  3359. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3360. "%s Invalid HTT tx_status %d\n",
  3361. __func__, tx_status);
  3362. break;
  3363. }
  3364. }
  3365. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3366. static inline
  3367. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3368. {
  3369. bool limit_hit = false;
  3370. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3371. limit_hit =
  3372. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3373. if (limit_hit)
  3374. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3375. return limit_hit;
  3376. }
  3377. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3378. {
  3379. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3380. }
  3381. #else
  3382. static inline
  3383. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3384. {
  3385. return false;
  3386. }
  3387. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3388. {
  3389. return false;
  3390. }
  3391. #endif
  3392. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3393. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3394. uint32_t quota)
  3395. {
  3396. void *tx_comp_hal_desc;
  3397. uint8_t buffer_src;
  3398. uint8_t pool_id;
  3399. uint32_t tx_desc_id;
  3400. struct dp_tx_desc_s *tx_desc = NULL;
  3401. struct dp_tx_desc_s *head_desc = NULL;
  3402. struct dp_tx_desc_s *tail_desc = NULL;
  3403. uint32_t num_processed = 0;
  3404. uint32_t count;
  3405. uint32_t num_avail_for_reap = 0;
  3406. bool force_break = false;
  3407. DP_HIST_INIT();
  3408. more_data:
  3409. /* Re-initialize local variables to be re-used */
  3410. head_desc = NULL;
  3411. tail_desc = NULL;
  3412. count = 0;
  3413. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3414. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3415. return 0;
  3416. }
  3417. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3418. if (num_avail_for_reap >= quota)
  3419. num_avail_for_reap = quota;
  3420. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3421. /* Find head descriptor from completion ring */
  3422. while (qdf_likely(num_avail_for_reap)) {
  3423. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3424. if (qdf_unlikely(!tx_comp_hal_desc))
  3425. break;
  3426. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3427. /* If this buffer was not released by TQM or FW, then it is not
  3428. * Tx completion indication, assert */
  3429. if (qdf_unlikely(buffer_src !=
  3430. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3431. (qdf_unlikely(buffer_src !=
  3432. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3433. uint8_t wbm_internal_error;
  3434. dp_err_rl(
  3435. "Tx comp release_src != TQM | FW but from %d",
  3436. buffer_src);
  3437. hal_dump_comp_desc(tx_comp_hal_desc);
  3438. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3439. /* When WBM sees NULL buffer_addr_info in any of
  3440. * ingress rings it sends an error indication,
  3441. * with wbm_internal_error=1, to a specific ring.
  3442. * The WBM2SW ring used to indicate these errors is
  3443. * fixed in HW, and that ring is being used as Tx
  3444. * completion ring. These errors are not related to
  3445. * Tx completions, and should just be ignored
  3446. */
  3447. wbm_internal_error = hal_get_wbm_internal_error(
  3448. soc->hal_soc,
  3449. tx_comp_hal_desc);
  3450. if (wbm_internal_error) {
  3451. dp_err_rl("Tx comp wbm_internal_error!!");
  3452. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3453. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3454. buffer_src)
  3455. dp_handle_wbm_internal_error(
  3456. soc,
  3457. tx_comp_hal_desc,
  3458. hal_tx_comp_get_buffer_type(
  3459. tx_comp_hal_desc));
  3460. } else {
  3461. dp_err_rl("Tx comp wbm_internal_error false");
  3462. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3463. }
  3464. continue;
  3465. }
  3466. /* Get descriptor id */
  3467. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3468. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3469. DP_TX_DESC_ID_POOL_OS;
  3470. /* Find Tx descriptor */
  3471. tx_desc = dp_tx_desc_find(soc, pool_id,
  3472. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3473. DP_TX_DESC_ID_PAGE_OS,
  3474. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3475. DP_TX_DESC_ID_OFFSET_OS);
  3476. /*
  3477. * If the release source is FW, process the HTT status
  3478. */
  3479. if (qdf_unlikely(buffer_src ==
  3480. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3481. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3482. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3483. htt_tx_status);
  3484. dp_tx_process_htt_completion(tx_desc,
  3485. htt_tx_status, ring_id);
  3486. } else {
  3487. /*
  3488. * If the fast completion mode is enabled extended
  3489. * metadata from descriptor is not copied
  3490. */
  3491. if (qdf_likely(tx_desc->flags &
  3492. DP_TX_DESC_FLAG_SIMPLE)) {
  3493. tx_desc->peer_id =
  3494. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3495. tx_desc->tx_status =
  3496. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3497. goto add_to_pool;
  3498. }
  3499. /*
  3500. * If the descriptor is already freed in vdev_detach,
  3501. * continue to next descriptor
  3502. */
  3503. if (qdf_unlikely(!tx_desc->vdev) &&
  3504. qdf_unlikely(!tx_desc->flags)) {
  3505. QDF_TRACE(QDF_MODULE_ID_DP,
  3506. QDF_TRACE_LEVEL_INFO,
  3507. "Descriptor freed in vdev_detach %d",
  3508. tx_desc_id);
  3509. continue;
  3510. }
  3511. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3512. QDF_TRACE(QDF_MODULE_ID_DP,
  3513. QDF_TRACE_LEVEL_INFO,
  3514. "pdev in down state %d",
  3515. tx_desc_id);
  3516. dp_tx_comp_free_buf(soc, tx_desc);
  3517. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3518. goto next_desc;
  3519. }
  3520. /* Pool id is not matching. Error */
  3521. if (tx_desc->pool_id != pool_id) {
  3522. QDF_TRACE(QDF_MODULE_ID_DP,
  3523. QDF_TRACE_LEVEL_FATAL,
  3524. "Tx Comp pool id %d not matched %d",
  3525. pool_id, tx_desc->pool_id);
  3526. qdf_assert_always(0);
  3527. }
  3528. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3529. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3530. QDF_TRACE(QDF_MODULE_ID_DP,
  3531. QDF_TRACE_LEVEL_FATAL,
  3532. "Txdesc invalid, flgs = %x,id = %d",
  3533. tx_desc->flags, tx_desc_id);
  3534. qdf_assert_always(0);
  3535. }
  3536. /* Collect hw completion contents */
  3537. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3538. &tx_desc->comp, 1);
  3539. add_to_pool:
  3540. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3541. /* First ring descriptor on the cycle */
  3542. if (!head_desc) {
  3543. head_desc = tx_desc;
  3544. tail_desc = tx_desc;
  3545. }
  3546. tail_desc->next = tx_desc;
  3547. tx_desc->next = NULL;
  3548. tail_desc = tx_desc;
  3549. }
  3550. next_desc:
  3551. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3552. /*
  3553. * Processed packet count is more than given quota
  3554. * stop to processing
  3555. */
  3556. count++;
  3557. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3558. break;
  3559. }
  3560. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3561. /* Process the reaped descriptors */
  3562. if (head_desc)
  3563. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3564. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3565. if (num_processed >= quota)
  3566. force_break = true;
  3567. if (!force_break &&
  3568. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3569. hal_ring_hdl)) {
  3570. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3571. if (!hif_exec_should_yield(soc->hif_handle,
  3572. int_ctx->dp_intr_id))
  3573. goto more_data;
  3574. }
  3575. }
  3576. DP_TX_HIST_STATS_PER_PDEV();
  3577. return num_processed;
  3578. }
  3579. #ifdef FEATURE_WLAN_TDLS
  3580. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3581. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3582. {
  3583. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3584. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3585. DP_MOD_ID_TDLS);
  3586. if (!vdev) {
  3587. dp_err("vdev handle for id %d is NULL", vdev_id);
  3588. return NULL;
  3589. }
  3590. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3591. vdev->is_tdls_frame = true;
  3592. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  3593. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3594. }
  3595. #endif
  3596. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  3597. {
  3598. struct wlan_cfg_dp_soc_ctxt *cfg;
  3599. struct dp_soc *soc;
  3600. soc = vdev->pdev->soc;
  3601. if (!soc)
  3602. return;
  3603. cfg = soc->wlan_cfg_ctx;
  3604. if (!cfg)
  3605. return;
  3606. if (vdev->opmode == wlan_op_mode_ndi)
  3607. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  3608. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  3609. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  3610. (vdev->subtype == wlan_op_subtype_p2p_go))
  3611. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  3612. else
  3613. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  3614. }
  3615. /**
  3616. * dp_tx_vdev_attach() - attach vdev to dp tx
  3617. * @vdev: virtual device instance
  3618. *
  3619. * Return: QDF_STATUS_SUCCESS: success
  3620. * QDF_STATUS_E_RESOURCES: Error return
  3621. */
  3622. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3623. {
  3624. int pdev_id;
  3625. /*
  3626. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3627. */
  3628. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3629. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3630. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3631. vdev->vdev_id);
  3632. pdev_id =
  3633. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3634. vdev->pdev->pdev_id);
  3635. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3636. /*
  3637. * Set HTT Extension Valid bit to 0 by default
  3638. */
  3639. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3640. dp_tx_vdev_update_search_flags(vdev);
  3641. dp_tx_vdev_update_feature_flags(vdev);
  3642. return QDF_STATUS_SUCCESS;
  3643. }
  3644. #ifndef FEATURE_WDS
  3645. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3646. {
  3647. return false;
  3648. }
  3649. #endif
  3650. /**
  3651. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3652. * @vdev: virtual device instance
  3653. *
  3654. * Return: void
  3655. *
  3656. */
  3657. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3658. {
  3659. struct dp_soc *soc = vdev->pdev->soc;
  3660. /*
  3661. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3662. * for TDLS link
  3663. *
  3664. * Enable AddrY (SA based search) only for non-WDS STA and
  3665. * ProxySTA VAP (in HKv1) modes.
  3666. *
  3667. * In all other VAP modes, only DA based search should be
  3668. * enabled
  3669. */
  3670. if (vdev->opmode == wlan_op_mode_sta &&
  3671. vdev->tdls_link_connected)
  3672. vdev->hal_desc_addr_search_flags =
  3673. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3674. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3675. !dp_tx_da_search_override(vdev))
  3676. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3677. else
  3678. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3679. /* Set search type only when peer map v2 messaging is enabled
  3680. * as we will have the search index (AST hash) only when v2 is
  3681. * enabled
  3682. */
  3683. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3684. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3685. else
  3686. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3687. }
  3688. static inline bool
  3689. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3690. struct dp_vdev *vdev,
  3691. struct dp_tx_desc_s *tx_desc)
  3692. {
  3693. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3694. return false;
  3695. /*
  3696. * if vdev is given, then only check whether desc
  3697. * vdev match. if vdev is NULL, then check whether
  3698. * desc pdev match.
  3699. */
  3700. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3701. }
  3702. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3703. /**
  3704. * dp_tx_desc_flush() - release resources associated
  3705. * to TX Desc
  3706. *
  3707. * @dp_pdev: Handle to DP pdev structure
  3708. * @vdev: virtual device instance
  3709. * NULL: no specific Vdev is required and check all allcated TX desc
  3710. * on this pdev.
  3711. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3712. *
  3713. * @force_free:
  3714. * true: flush the TX desc.
  3715. * false: only reset the Vdev in each allocated TX desc
  3716. * that associated to current Vdev.
  3717. *
  3718. * This function will go through the TX desc pool to flush
  3719. * the outstanding TX data or reset Vdev to NULL in associated TX
  3720. * Desc.
  3721. */
  3722. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3723. bool force_free)
  3724. {
  3725. uint8_t i;
  3726. uint32_t j;
  3727. uint32_t num_desc, page_id, offset;
  3728. uint16_t num_desc_per_page;
  3729. struct dp_soc *soc = pdev->soc;
  3730. struct dp_tx_desc_s *tx_desc = NULL;
  3731. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3732. if (!vdev && !force_free) {
  3733. dp_err("Reset TX desc vdev, Vdev param is required!");
  3734. return;
  3735. }
  3736. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3737. tx_desc_pool = &soc->tx_desc[i];
  3738. if (!(tx_desc_pool->pool_size) ||
  3739. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3740. !(tx_desc_pool->desc_pages.cacheable_pages))
  3741. continue;
  3742. /*
  3743. * Add flow pool lock protection in case pool is freed
  3744. * due to all tx_desc is recycled when handle TX completion.
  3745. * this is not necessary when do force flush as:
  3746. * a. double lock will happen if dp_tx_desc_release is
  3747. * also trying to acquire it.
  3748. * b. dp interrupt has been disabled before do force TX desc
  3749. * flush in dp_pdev_deinit().
  3750. */
  3751. if (!force_free)
  3752. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  3753. num_desc = tx_desc_pool->pool_size;
  3754. num_desc_per_page =
  3755. tx_desc_pool->desc_pages.num_element_per_page;
  3756. for (j = 0; j < num_desc; j++) {
  3757. page_id = j / num_desc_per_page;
  3758. offset = j % num_desc_per_page;
  3759. if (qdf_unlikely(!(tx_desc_pool->
  3760. desc_pages.cacheable_pages)))
  3761. break;
  3762. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3763. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3764. /*
  3765. * Free TX desc if force free is
  3766. * required, otherwise only reset vdev
  3767. * in this TX desc.
  3768. */
  3769. if (force_free) {
  3770. dp_tx_comp_free_buf(soc, tx_desc);
  3771. dp_tx_desc_release(tx_desc, i);
  3772. } else {
  3773. tx_desc->vdev = NULL;
  3774. }
  3775. }
  3776. }
  3777. if (!force_free)
  3778. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  3779. }
  3780. }
  3781. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3782. /**
  3783. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3784. *
  3785. * @soc: Handle to DP soc structure
  3786. * @tx_desc: pointer of one TX desc
  3787. * @desc_pool_id: TX Desc pool id
  3788. */
  3789. static inline void
  3790. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3791. uint8_t desc_pool_id)
  3792. {
  3793. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3794. tx_desc->vdev = NULL;
  3795. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3796. }
  3797. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3798. bool force_free)
  3799. {
  3800. uint8_t i, num_pool;
  3801. uint32_t j;
  3802. uint32_t num_desc, page_id, offset;
  3803. uint16_t num_desc_per_page;
  3804. struct dp_soc *soc = pdev->soc;
  3805. struct dp_tx_desc_s *tx_desc = NULL;
  3806. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3807. if (!vdev && !force_free) {
  3808. dp_err("Reset TX desc vdev, Vdev param is required!");
  3809. return;
  3810. }
  3811. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3812. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3813. for (i = 0; i < num_pool; i++) {
  3814. tx_desc_pool = &soc->tx_desc[i];
  3815. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3816. continue;
  3817. num_desc_per_page =
  3818. tx_desc_pool->desc_pages.num_element_per_page;
  3819. for (j = 0; j < num_desc; j++) {
  3820. page_id = j / num_desc_per_page;
  3821. offset = j % num_desc_per_page;
  3822. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3823. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3824. if (force_free) {
  3825. dp_tx_comp_free_buf(soc, tx_desc);
  3826. dp_tx_desc_release(tx_desc, i);
  3827. } else {
  3828. dp_tx_desc_reset_vdev(soc, tx_desc,
  3829. i);
  3830. }
  3831. }
  3832. }
  3833. }
  3834. }
  3835. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3836. /**
  3837. * dp_tx_vdev_detach() - detach vdev from dp tx
  3838. * @vdev: virtual device instance
  3839. *
  3840. * Return: QDF_STATUS_SUCCESS: success
  3841. * QDF_STATUS_E_RESOURCES: Error return
  3842. */
  3843. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3844. {
  3845. struct dp_pdev *pdev = vdev->pdev;
  3846. /* Reset TX desc associated to this Vdev as NULL */
  3847. dp_tx_desc_flush(pdev, vdev, false);
  3848. dp_tx_vdev_multipass_deinit(vdev);
  3849. return QDF_STATUS_SUCCESS;
  3850. }
  3851. /**
  3852. * dp_tx_pdev_attach() - attach pdev to dp tx
  3853. * @pdev: physical device instance
  3854. *
  3855. * Return: QDF_STATUS_SUCCESS: success
  3856. * QDF_STATUS_E_RESOURCES: Error return
  3857. */
  3858. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  3859. {
  3860. struct dp_soc *soc = pdev->soc;
  3861. /* Initialize Flow control counters */
  3862. qdf_atomic_init(&pdev->num_tx_outstanding);
  3863. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3864. /* Initialize descriptors in TCL Ring */
  3865. hal_tx_init_data_ring(soc->hal_soc,
  3866. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3867. }
  3868. return QDF_STATUS_SUCCESS;
  3869. }
  3870. /**
  3871. * dp_tx_pdev_detach() - detach pdev from dp tx
  3872. * @pdev: physical device instance
  3873. *
  3874. * Return: QDF_STATUS_SUCCESS: success
  3875. * QDF_STATUS_E_RESOURCES: Error return
  3876. */
  3877. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3878. {
  3879. /* flush TX outstanding data per pdev */
  3880. dp_tx_desc_flush(pdev, NULL, true);
  3881. dp_tx_me_exit(pdev);
  3882. return QDF_STATUS_SUCCESS;
  3883. }
  3884. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3885. /* Pools will be allocated dynamically */
  3886. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3887. int num_desc)
  3888. {
  3889. uint8_t i;
  3890. for (i = 0; i < num_pool; i++) {
  3891. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3892. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3893. }
  3894. return QDF_STATUS_SUCCESS;
  3895. }
  3896. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3897. int num_desc)
  3898. {
  3899. return QDF_STATUS_SUCCESS;
  3900. }
  3901. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  3902. {
  3903. }
  3904. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3905. {
  3906. uint8_t i;
  3907. for (i = 0; i < num_pool; i++)
  3908. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3909. }
  3910. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3911. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3912. int num_desc)
  3913. {
  3914. uint8_t i, count;
  3915. /* Allocate software Tx descriptor pools */
  3916. for (i = 0; i < num_pool; i++) {
  3917. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3918. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3919. FL("Tx Desc Pool alloc %d failed %pK"),
  3920. i, soc);
  3921. goto fail;
  3922. }
  3923. }
  3924. return QDF_STATUS_SUCCESS;
  3925. fail:
  3926. for (count = 0; count < i; count++)
  3927. dp_tx_desc_pool_free(soc, count);
  3928. return QDF_STATUS_E_NOMEM;
  3929. }
  3930. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3931. int num_desc)
  3932. {
  3933. uint8_t i;
  3934. for (i = 0; i < num_pool; i++) {
  3935. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  3936. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3937. FL("Tx Desc Pool init %d failed %pK"),
  3938. i, soc);
  3939. return QDF_STATUS_E_NOMEM;
  3940. }
  3941. }
  3942. return QDF_STATUS_SUCCESS;
  3943. }
  3944. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  3945. {
  3946. uint8_t i;
  3947. for (i = 0; i < num_pool; i++)
  3948. dp_tx_desc_pool_deinit(soc, i);
  3949. }
  3950. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3951. {
  3952. uint8_t i;
  3953. for (i = 0; i < num_pool; i++)
  3954. dp_tx_desc_pool_free(soc, i);
  3955. }
  3956. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3957. /**
  3958. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  3959. * @soc: core txrx main context
  3960. * @num_pool: number of pools
  3961. *
  3962. */
  3963. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  3964. {
  3965. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  3966. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  3967. }
  3968. /**
  3969. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  3970. * @soc: core txrx main context
  3971. * @num_pool: number of pools
  3972. *
  3973. */
  3974. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  3975. {
  3976. dp_tx_tso_desc_pool_free(soc, num_pool);
  3977. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  3978. }
  3979. /**
  3980. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  3981. * @soc: core txrx main context
  3982. *
  3983. * This function frees all tx related descriptors as below
  3984. * 1. Regular TX descriptors (static pools)
  3985. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  3986. * 3. TSO descriptors
  3987. *
  3988. */
  3989. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  3990. {
  3991. uint8_t num_pool;
  3992. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3993. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  3994. dp_tx_ext_desc_pool_free(soc, num_pool);
  3995. dp_tx_delete_static_pools(soc, num_pool);
  3996. }
  3997. /**
  3998. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  3999. * @soc: core txrx main context
  4000. *
  4001. * This function de-initializes all tx related descriptors as below
  4002. * 1. Regular TX descriptors (static pools)
  4003. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4004. * 3. TSO descriptors
  4005. *
  4006. */
  4007. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4008. {
  4009. uint8_t num_pool;
  4010. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4011. dp_tx_flow_control_deinit(soc);
  4012. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4013. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4014. dp_tx_deinit_static_pools(soc, num_pool);
  4015. }
  4016. /**
  4017. * dp_tso_attach() - TSO attach handler
  4018. * @txrx_soc: Opaque Dp handle
  4019. *
  4020. * Reserve TSO descriptor buffers
  4021. *
  4022. * Return: QDF_STATUS_E_FAILURE on failure or
  4023. * QDF_STATUS_SUCCESS on success
  4024. */
  4025. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4026. uint8_t num_pool,
  4027. uint16_t num_desc)
  4028. {
  4029. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4030. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4031. return QDF_STATUS_E_FAILURE;
  4032. }
  4033. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4034. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4035. num_pool, soc);
  4036. return QDF_STATUS_E_FAILURE;
  4037. }
  4038. return QDF_STATUS_SUCCESS;
  4039. }
  4040. /**
  4041. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4042. * @soc: DP soc handle
  4043. * @num_pool: Number of pools
  4044. * @num_desc: Number of descriptors
  4045. *
  4046. * Initialize TSO descriptor pools
  4047. *
  4048. * Return: QDF_STATUS_E_FAILURE on failure or
  4049. * QDF_STATUS_SUCCESS on success
  4050. */
  4051. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4052. uint8_t num_pool,
  4053. uint16_t num_desc)
  4054. {
  4055. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4056. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4057. return QDF_STATUS_E_FAILURE;
  4058. }
  4059. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4060. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4061. num_pool, soc);
  4062. return QDF_STATUS_E_FAILURE;
  4063. }
  4064. return QDF_STATUS_SUCCESS;
  4065. }
  4066. /**
  4067. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4068. * @soc: core txrx main context
  4069. *
  4070. * This function allocates memory for following descriptor pools
  4071. * 1. regular sw tx descriptor pools (static pools)
  4072. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4073. * 3. TSO descriptor pools
  4074. *
  4075. * Return: QDF_STATUS_SUCCESS: success
  4076. * QDF_STATUS_E_RESOURCES: Error return
  4077. */
  4078. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4079. {
  4080. uint8_t num_pool;
  4081. uint32_t num_desc;
  4082. uint32_t num_ext_desc;
  4083. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4084. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4085. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4086. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4087. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4088. __func__, num_pool, num_desc);
  4089. if ((num_pool > MAX_TXDESC_POOLS) ||
  4090. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4091. goto fail1;
  4092. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4093. goto fail1;
  4094. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4095. goto fail2;
  4096. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4097. return QDF_STATUS_SUCCESS;
  4098. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4099. goto fail3;
  4100. return QDF_STATUS_SUCCESS;
  4101. fail3:
  4102. dp_tx_ext_desc_pool_free(soc, num_pool);
  4103. fail2:
  4104. dp_tx_delete_static_pools(soc, num_pool);
  4105. fail1:
  4106. return QDF_STATUS_E_RESOURCES;
  4107. }
  4108. /**
  4109. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4110. * @soc: core txrx main context
  4111. *
  4112. * This function initializes the following TX descriptor pools
  4113. * 1. regular sw tx descriptor pools (static pools)
  4114. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4115. * 3. TSO descriptor pools
  4116. *
  4117. * Return: QDF_STATUS_SUCCESS: success
  4118. * QDF_STATUS_E_RESOURCES: Error return
  4119. */
  4120. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4121. {
  4122. uint8_t num_pool;
  4123. uint32_t num_desc;
  4124. uint32_t num_ext_desc;
  4125. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4126. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4127. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4128. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4129. goto fail1;
  4130. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4131. goto fail2;
  4132. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4133. return QDF_STATUS_SUCCESS;
  4134. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4135. goto fail3;
  4136. dp_tx_flow_control_init(soc);
  4137. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4138. return QDF_STATUS_SUCCESS;
  4139. fail3:
  4140. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4141. fail2:
  4142. dp_tx_deinit_static_pools(soc, num_pool);
  4143. fail1:
  4144. return QDF_STATUS_E_RESOURCES;
  4145. }
  4146. /**
  4147. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4148. * @txrx_soc: dp soc handle
  4149. *
  4150. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4151. * QDF_STATUS_E_FAILURE
  4152. */
  4153. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4154. {
  4155. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4156. uint8_t num_pool;
  4157. uint32_t num_desc;
  4158. uint32_t num_ext_desc;
  4159. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4160. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4161. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4162. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4163. return QDF_STATUS_E_FAILURE;
  4164. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4165. return QDF_STATUS_E_FAILURE;
  4166. return QDF_STATUS_SUCCESS;
  4167. }
  4168. /**
  4169. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4170. * @txrx_soc: dp soc handle
  4171. *
  4172. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4173. */
  4174. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4175. {
  4176. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4177. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4178. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4179. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4180. return QDF_STATUS_SUCCESS;
  4181. }