cam_mem_mgr.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/slab.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/version.h>
  11. #include <linux/debugfs.h>
  12. #include "cam_compat.h"
  13. #include "cam_req_mgr_util.h"
  14. #include "cam_mem_mgr.h"
  15. #include "cam_smmu_api.h"
  16. #include "cam_debug_util.h"
  17. #include "cam_trace.h"
  18. #include "cam_common_util.h"
  19. static struct cam_mem_table tbl;
  20. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  21. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  22. static void cam_mem_mgr_put_dma_heaps(void);
  23. static int cam_mem_mgr_get_dma_heaps(void);
  24. #endif
  25. static void cam_mem_mgr_print_tbl(void)
  26. {
  27. int i;
  28. uint64_t ms, tmp, hrs, min, sec;
  29. struct timespec64 *ts = NULL;
  30. struct timespec64 current_ts;
  31. ktime_get_real_ts64(&(current_ts));
  32. tmp = current_ts.tv_sec;
  33. ms = (current_ts.tv_nsec) / 1000000;
  34. sec = do_div(tmp, 60);
  35. min = do_div(tmp, 60);
  36. hrs = do_div(tmp, 24);
  37. CAM_INFO(CAM_MEM, "***%llu:%llu:%llu:%llu Mem mgr table dump***",
  38. hrs, min, sec, ms);
  39. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  40. if (tbl.bufq[i].active) {
  41. ts = &tbl.bufq[i].timestamp;
  42. tmp = ts->tv_sec;
  43. ms = (ts->tv_nsec) / 1000000;
  44. sec = do_div(tmp, 60);
  45. min = do_div(tmp, 60);
  46. hrs = do_div(tmp, 24);
  47. CAM_INFO(CAM_MEM,
  48. "%llu:%llu:%llu:%llu idx %d fd %d size %llu",
  49. hrs, min, sec, ms, i, tbl.bufq[i].fd,
  50. tbl.bufq[i].len);
  51. }
  52. }
  53. }
  54. static int cam_mem_util_get_dma_dir(uint32_t flags)
  55. {
  56. int rc = -EINVAL;
  57. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  58. rc = DMA_TO_DEVICE;
  59. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  60. rc = DMA_FROM_DEVICE;
  61. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  62. rc = DMA_BIDIRECTIONAL;
  63. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  64. rc = DMA_BIDIRECTIONAL;
  65. return rc;
  66. }
  67. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  68. uintptr_t *vaddr,
  69. size_t *len)
  70. {
  71. int rc = 0;
  72. void *addr;
  73. /*
  74. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  75. * need to be called in pair to avoid stability issue.
  76. */
  77. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  78. if (rc) {
  79. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  80. return rc;
  81. }
  82. addr = dma_buf_vmap(dmabuf);
  83. if (!addr) {
  84. CAM_ERR(CAM_MEM, "kernel map fail");
  85. *vaddr = 0;
  86. *len = 0;
  87. rc = -ENOSPC;
  88. goto fail;
  89. }
  90. *vaddr = (uint64_t)addr;
  91. *len = dmabuf->size;
  92. return 0;
  93. fail:
  94. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  95. return rc;
  96. }
  97. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  98. uint64_t vaddr)
  99. {
  100. int rc = 0;
  101. if (!dmabuf || !vaddr) {
  102. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  103. return -EINVAL;
  104. }
  105. dma_buf_vunmap(dmabuf, (void *)vaddr);
  106. /*
  107. * dma_buf_begin_cpu_access() and
  108. * dma_buf_end_cpu_access() need to be called in pair
  109. * to avoid stability issue.
  110. */
  111. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  112. if (rc) {
  113. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  114. dmabuf);
  115. return rc;
  116. }
  117. return rc;
  118. }
  119. static int cam_mem_mgr_create_debug_fs(void)
  120. {
  121. int rc = 0;
  122. struct dentry *dbgfileptr = NULL;
  123. dbgfileptr = debugfs_create_dir("camera_memmgr", NULL);
  124. if (!dbgfileptr) {
  125. CAM_ERR(CAM_MEM,"DebugFS could not create directory!");
  126. rc = -ENOENT;
  127. goto end;
  128. }
  129. /* Store parent inode for cleanup in caller */
  130. tbl.dentry = dbgfileptr;
  131. dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
  132. tbl.dentry, &tbl.alloc_profile_enable);
  133. if (IS_ERR(dbgfileptr)) {
  134. if (PTR_ERR(dbgfileptr) == -ENODEV)
  135. CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
  136. else
  137. rc = PTR_ERR(dbgfileptr);
  138. }
  139. end:
  140. return rc;
  141. }
  142. int cam_mem_mgr_init(void)
  143. {
  144. int i;
  145. int bitmap_size;
  146. int rc = 0;
  147. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  148. if (cam_smmu_need_force_alloc_cached(&tbl.force_cache_allocs)) {
  149. CAM_ERR(CAM_MEM, "Error in getting force cache alloc flag");
  150. return -EINVAL;
  151. }
  152. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  153. rc = cam_mem_mgr_get_dma_heaps();
  154. if (rc) {
  155. CAM_ERR(CAM_MEM, "Failed in getting dma heaps rc=%d", rc);
  156. return rc;
  157. }
  158. #endif
  159. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  160. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  161. if (!tbl.bitmap) {
  162. rc = -ENOMEM;
  163. goto put_heaps;
  164. }
  165. tbl.bits = bitmap_size * BITS_PER_BYTE;
  166. bitmap_zero(tbl.bitmap, tbl.bits);
  167. /* We need to reserve slot 0 because 0 is invalid */
  168. set_bit(0, tbl.bitmap);
  169. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  170. tbl.bufq[i].fd = -1;
  171. tbl.bufq[i].buf_handle = -1;
  172. }
  173. mutex_init(&tbl.m_lock);
  174. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  175. cam_mem_mgr_create_debug_fs();
  176. return 0;
  177. put_heaps:
  178. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  179. cam_mem_mgr_put_dma_heaps();
  180. #endif
  181. return rc;
  182. }
  183. static int32_t cam_mem_get_slot(void)
  184. {
  185. int32_t idx;
  186. mutex_lock(&tbl.m_lock);
  187. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  188. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  189. mutex_unlock(&tbl.m_lock);
  190. return -ENOMEM;
  191. }
  192. set_bit(idx, tbl.bitmap);
  193. tbl.bufq[idx].active = true;
  194. ktime_get_real_ts64(&(tbl.bufq[idx].timestamp));
  195. mutex_init(&tbl.bufq[idx].q_lock);
  196. mutex_unlock(&tbl.m_lock);
  197. return idx;
  198. }
  199. static void cam_mem_put_slot(int32_t idx)
  200. {
  201. mutex_lock(&tbl.m_lock);
  202. mutex_lock(&tbl.bufq[idx].q_lock);
  203. tbl.bufq[idx].active = false;
  204. tbl.bufq[idx].is_internal = false;
  205. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  206. mutex_unlock(&tbl.bufq[idx].q_lock);
  207. mutex_destroy(&tbl.bufq[idx].q_lock);
  208. clear_bit(idx, tbl.bitmap);
  209. mutex_unlock(&tbl.m_lock);
  210. }
  211. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  212. dma_addr_t *iova_ptr, size_t *len_ptr)
  213. {
  214. int rc = 0, idx;
  215. *len_ptr = 0;
  216. if (!atomic_read(&cam_mem_mgr_state)) {
  217. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  218. return -EINVAL;
  219. }
  220. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  221. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  222. return -ENOENT;
  223. if (!tbl.bufq[idx].active) {
  224. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  225. idx);
  226. return -EAGAIN;
  227. }
  228. mutex_lock(&tbl.bufq[idx].q_lock);
  229. if (buf_handle != tbl.bufq[idx].buf_handle) {
  230. rc = -EINVAL;
  231. goto handle_mismatch;
  232. }
  233. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  234. rc = cam_smmu_get_stage2_iova(mmu_handle,
  235. tbl.bufq[idx].fd,
  236. iova_ptr,
  237. len_ptr);
  238. else
  239. rc = cam_smmu_get_iova(mmu_handle,
  240. tbl.bufq[idx].fd,
  241. iova_ptr,
  242. len_ptr);
  243. if (rc) {
  244. CAM_ERR(CAM_MEM,
  245. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d",
  246. buf_handle, mmu_handle, tbl.bufq[idx].fd);
  247. goto handle_mismatch;
  248. }
  249. CAM_DBG(CAM_MEM,
  250. "handle:0x%x fd:%d iova_ptr:%pK len_ptr:%llu",
  251. mmu_handle, tbl.bufq[idx].fd, iova_ptr, *len_ptr);
  252. handle_mismatch:
  253. mutex_unlock(&tbl.bufq[idx].q_lock);
  254. return rc;
  255. }
  256. EXPORT_SYMBOL(cam_mem_get_io_buf);
  257. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  258. {
  259. int idx;
  260. if (!atomic_read(&cam_mem_mgr_state)) {
  261. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  262. return -EINVAL;
  263. }
  264. if (!atomic_read(&cam_mem_mgr_state)) {
  265. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  266. return -EINVAL;
  267. }
  268. if (!buf_handle || !vaddr_ptr || !len)
  269. return -EINVAL;
  270. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  271. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  272. return -EINVAL;
  273. if (!tbl.bufq[idx].active) {
  274. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  275. idx);
  276. return -EPERM;
  277. }
  278. if (buf_handle != tbl.bufq[idx].buf_handle)
  279. return -EINVAL;
  280. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  281. return -EINVAL;
  282. if (tbl.bufq[idx].kmdvaddr) {
  283. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  284. *len = tbl.bufq[idx].len;
  285. } else {
  286. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  287. buf_handle);
  288. return -EINVAL;
  289. }
  290. return 0;
  291. }
  292. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  293. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  294. {
  295. int rc = 0, idx;
  296. uint32_t cache_dir;
  297. unsigned long dmabuf_flag = 0;
  298. if (!atomic_read(&cam_mem_mgr_state)) {
  299. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  300. return -EINVAL;
  301. }
  302. if (!cmd)
  303. return -EINVAL;
  304. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  305. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  306. return -EINVAL;
  307. mutex_lock(&tbl.bufq[idx].q_lock);
  308. if (!tbl.bufq[idx].active) {
  309. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  310. idx);
  311. rc = -EINVAL;
  312. goto end;
  313. }
  314. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  315. rc = -EINVAL;
  316. goto end;
  317. }
  318. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  319. if (rc) {
  320. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  321. goto end;
  322. }
  323. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  324. CAM_DBG(CAM_MEM, "Calling dmap buf APIs for cache operations");
  325. cache_dir = DMA_BIDIRECTIONAL;
  326. #else
  327. if (dmabuf_flag & ION_FLAG_CACHED) {
  328. switch (cmd->mem_cache_ops) {
  329. case CAM_MEM_CLEAN_CACHE:
  330. cache_dir = DMA_TO_DEVICE;
  331. break;
  332. case CAM_MEM_INV_CACHE:
  333. cache_dir = DMA_FROM_DEVICE;
  334. break;
  335. case CAM_MEM_CLEAN_INV_CACHE:
  336. cache_dir = DMA_BIDIRECTIONAL;
  337. break;
  338. default:
  339. CAM_ERR(CAM_MEM,
  340. "invalid cache ops :%d", cmd->mem_cache_ops);
  341. rc = -EINVAL;
  342. goto end;
  343. }
  344. } else {
  345. CAM_DBG(CAM_MEM, "BUF is not cached");
  346. goto end;
  347. }
  348. #endif
  349. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  350. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  351. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  352. if (rc) {
  353. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  354. goto end;
  355. }
  356. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  357. cache_dir);
  358. if (rc) {
  359. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  360. goto end;
  361. }
  362. end:
  363. mutex_unlock(&tbl.bufq[idx].q_lock);
  364. return rc;
  365. }
  366. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  367. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  368. static void cam_mem_mgr_put_dma_heaps(void)
  369. {
  370. CAM_DBG(CAM_MEM, "Releasing DMA Buf heaps usage");
  371. }
  372. static int cam_mem_mgr_get_dma_heaps(void)
  373. {
  374. int rc = 0;
  375. tbl.system_heap = NULL;
  376. tbl.system_uncached_heap = NULL;
  377. tbl.camera_heap = NULL;
  378. tbl.camera_uncached_heap = NULL;
  379. tbl.secure_display_heap = NULL;
  380. tbl.system_heap = dma_heap_find("qcom,system");
  381. if (IS_ERR_OR_NULL(tbl.system_heap)) {
  382. rc = PTR_ERR(tbl.system_heap);
  383. CAM_ERR(CAM_MEM, "qcom system heap not found, rc=%d", rc);
  384. tbl.system_heap = NULL;
  385. goto put_heaps;
  386. }
  387. tbl.system_uncached_heap = dma_heap_find("qcom,system-uncached");
  388. if (IS_ERR_OR_NULL(tbl.system_uncached_heap)) {
  389. if (tbl.force_cache_allocs) {
  390. /* optional, we anyway do not use uncached */
  391. CAM_DBG(CAM_MEM,
  392. "qcom system-uncached heap not found, err=%d",
  393. PTR_ERR(tbl.system_uncached_heap));
  394. tbl.system_uncached_heap = NULL;
  395. } else {
  396. /* fatal, must need uncached heaps */
  397. rc = PTR_ERR(tbl.system_uncached_heap);
  398. CAM_ERR(CAM_MEM,
  399. "qcom system-uncached heap not found, rc=%d",
  400. rc);
  401. tbl.system_uncached_heap = NULL;
  402. goto put_heaps;
  403. }
  404. }
  405. tbl.secure_display_heap = dma_heap_find("qcom,secure-display");
  406. if (IS_ERR_OR_NULL(tbl.secure_display_heap)) {
  407. rc = PTR_ERR(tbl.secure_display_heap);
  408. CAM_ERR(CAM_MEM, "qcom,secure-display heap not found, rc=%d",
  409. rc);
  410. tbl.secure_display_heap = NULL;
  411. goto put_heaps;
  412. }
  413. tbl.camera_heap = dma_heap_find("qcom,camera");
  414. if (IS_ERR_OR_NULL(tbl.camera_heap)) {
  415. /* optional heap, not a fatal error */
  416. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  417. PTR_ERR(tbl.camera_heap));
  418. tbl.camera_heap = NULL;
  419. }
  420. tbl.camera_uncached_heap = dma_heap_find("qcom,camera-uncached");
  421. if (IS_ERR_OR_NULL(tbl.camera_uncached_heap)) {
  422. /* optional heap, not a fatal error */
  423. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  424. PTR_ERR(tbl.camera_uncached_heap));
  425. tbl.camera_uncached_heap = NULL;
  426. }
  427. CAM_INFO(CAM_MEM,
  428. "Heaps : system=%pK, system_uncached=%pK, camera=%pK, camera-uncached=%pK, secure_display=%pK",
  429. tbl.system_heap, tbl.system_uncached_heap,
  430. tbl.camera_heap, tbl.camera_uncached_heap,
  431. tbl.secure_display_heap);
  432. return 0;
  433. put_heaps:
  434. cam_mem_mgr_put_dma_heaps();
  435. return rc;
  436. }
  437. static int cam_mem_util_get_dma_buf(size_t len,
  438. unsigned int cam_flags,
  439. struct dma_buf **buf)
  440. {
  441. int rc = 0;
  442. struct dma_heap *heap;
  443. struct dma_heap *try_heap = NULL;
  444. struct timespec64 ts1, ts2;
  445. long microsec = 0;
  446. bool use_cached_heap = false;
  447. if (!buf) {
  448. CAM_ERR(CAM_MEM, "Invalid params");
  449. return -EINVAL;
  450. }
  451. if (tbl.alloc_profile_enable)
  452. CAM_GET_TIMESTAMP(ts1);
  453. if ((cam_flags & CAM_MEM_FLAG_CACHE) ||
  454. (tbl.force_cache_allocs &&
  455. (!(cam_flags & CAM_MEM_FLAG_PROTECTED_MODE)))) {
  456. CAM_DBG(CAM_MEM,
  457. "Using CACHED heap, cam_flags=0x%x, force_cache_allocs=%d",
  458. cam_flags, tbl.force_cache_allocs);
  459. use_cached_heap = true;
  460. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  461. use_cached_heap = true;
  462. CAM_DBG(CAM_MEM,
  463. "Using CACHED heap for secure, cam_flags=0x%x, force_cache_allocs=%d",
  464. cam_flags, tbl.force_cache_allocs);
  465. } else {
  466. use_cached_heap = false;
  467. CAM_ERR(CAM_MEM,
  468. "Using UNCACHED heap not supported, cam_flags=0x%x, force_cache_allocs=%d",
  469. cam_flags, tbl.force_cache_allocs);
  470. /*
  471. * Need a better handling based on whether dma-buf-heaps support
  472. * uncached heaps or not. For now, assume not supported.
  473. */
  474. return -EINVAL;
  475. }
  476. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  477. (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  478. heap = tbl.secure_display_heap;
  479. CAM_ERR(CAM_MEM, "Secure CDSP not supported yet");
  480. return -EBADR;
  481. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  482. heap = tbl.secure_display_heap;
  483. CAM_ERR(CAM_MEM, "Secure mode not supported yet");
  484. return -EBADR;
  485. }
  486. if (use_cached_heap) {
  487. try_heap = tbl.camera_heap;
  488. heap = tbl.system_heap;
  489. } else {
  490. try_heap = tbl.camera_uncached_heap;
  491. heap = tbl.system_uncached_heap;
  492. }
  493. CAM_DBG(CAM_MEM, "Using heaps : try=%pK, heap=%pK", try_heap, heap);
  494. *buf = NULL;
  495. if (!try_heap && !heap) {
  496. CAM_ERR(CAM_MEM,
  497. "No heap available for allocation, cant allocate");
  498. return -EINVAL;
  499. }
  500. if (try_heap) {
  501. *buf = dma_heap_buffer_alloc(try_heap, len, O_RDWR, 0);
  502. if (IS_ERR_OR_NULL(*buf)) {
  503. CAM_WARN(CAM_MEM,
  504. "Failed in allocating from try heap, heap=%pK, len=%zu, err=%d",
  505. try_heap, len, PTR_ERR(*buf));
  506. *buf = NULL;
  507. }
  508. }
  509. if (*buf == NULL) {
  510. *buf = dma_heap_buffer_alloc(heap, len, O_RDWR, 0);
  511. if (IS_ERR_OR_NULL(*buf)) {
  512. rc = PTR_ERR(*buf);
  513. CAM_ERR(CAM_MEM,
  514. "Failed in allocating from heap, heap=%pK, len=%zu, err=%d",
  515. heap, len, rc);
  516. *buf = NULL;
  517. return rc;
  518. }
  519. }
  520. CAM_DBG(CAM_MEM, "Allocate success, len=%zu, *buf=%pK", len, *buf);
  521. if (tbl.alloc_profile_enable) {
  522. CAM_GET_TIMESTAMP(ts2);
  523. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  524. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  525. len, microsec);
  526. }
  527. return rc;
  528. }
  529. #else
  530. static int cam_mem_util_get_dma_buf(size_t len,
  531. unsigned int cam_flags,
  532. struct dma_buf **buf)
  533. {
  534. int rc = 0;
  535. unsigned int heap_id;
  536. int32_t ion_flag = 0;
  537. struct timespec64 ts1, ts2;
  538. long microsec = 0;
  539. if (!buf) {
  540. CAM_ERR(CAM_MEM, "Invalid params");
  541. return -EINVAL;
  542. }
  543. if (tbl.alloc_profile_enable)
  544. CAM_GET_TIMESTAMP(ts1);
  545. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  546. (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  547. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  548. ion_flag |=
  549. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  550. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  551. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  552. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  553. } else {
  554. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  555. ION_HEAP(ION_CAMERA_HEAP_ID);
  556. }
  557. if (cam_flags & CAM_MEM_FLAG_CACHE)
  558. ion_flag |= ION_FLAG_CACHED;
  559. else
  560. ion_flag &= ~ION_FLAG_CACHED;
  561. if (tbl.force_cache_allocs && (!(ion_flag & ION_FLAG_SECURE)))
  562. ion_flag |= ION_FLAG_CACHED;
  563. *buf = ion_alloc(len, heap_id, ion_flag);
  564. if (IS_ERR_OR_NULL(*buf))
  565. return -ENOMEM;
  566. if (tbl.alloc_profile_enable) {
  567. CAM_GET_TIMESTAMP(ts2);
  568. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  569. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  570. len, microsec);
  571. }
  572. return rc;
  573. }
  574. #endif
  575. static int cam_mem_util_buffer_alloc(struct cam_mem_mgr_alloc_cmd *cmd,
  576. struct dma_buf **dmabuf,
  577. int *fd)
  578. {
  579. int rc;
  580. struct dma_buf *temp_dmabuf = NULL;
  581. rc = cam_mem_util_get_dma_buf(cmd->len,
  582. cmd->flags,
  583. dmabuf);
  584. if (rc) {
  585. CAM_ERR(CAM_MEM,
  586. "Error allocating dma buf : len=%llu, flags=0x%x",
  587. cmd->len, cmd->flags);
  588. return rc;
  589. }
  590. *fd = dma_buf_fd(*dmabuf, O_CLOEXEC);
  591. if (*fd < 0) {
  592. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  593. rc = -EINVAL;
  594. goto put_buf;
  595. }
  596. CAM_DBG(CAM_MEM, "Alloc success : len=%zu, *dmabuf=%pK, fd=%d",
  597. cmd->len, *dmabuf, *fd);
  598. /*
  599. * increment the ref count so that ref count becomes 2 here
  600. * when we close fd, refcount becomes 1 and when we do
  601. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  602. */
  603. temp_dmabuf = dma_buf_get(*fd);
  604. if (IS_ERR_OR_NULL(temp_dmabuf)) {
  605. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd);
  606. rc = -EINVAL;
  607. goto put_buf;
  608. }
  609. return rc;
  610. put_buf:
  611. dma_buf_put(*dmabuf);
  612. return rc;
  613. }
  614. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  615. {
  616. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  617. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  618. CAM_MEM_MMU_MAX_HANDLE);
  619. return -EINVAL;
  620. }
  621. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  622. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  623. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  624. return -EINVAL;
  625. }
  626. return 0;
  627. }
  628. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  629. {
  630. if (!cmd->flags) {
  631. CAM_ERR(CAM_MEM, "Invalid flags");
  632. return -EINVAL;
  633. }
  634. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  635. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  636. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  637. return -EINVAL;
  638. }
  639. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  640. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  641. CAM_ERR(CAM_MEM,
  642. "Kernel mapping in secure mode not allowed, flags=0x%x",
  643. cmd->flags);
  644. return -EINVAL;
  645. }
  646. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  647. CAM_ERR(CAM_MEM,
  648. "Shared memory buffers are not allowed to be mapped");
  649. return -EINVAL;
  650. }
  651. return 0;
  652. }
  653. static int cam_mem_util_map_hw_va(uint32_t flags,
  654. int32_t *mmu_hdls,
  655. int32_t num_hdls,
  656. int fd,
  657. dma_addr_t *hw_vaddr,
  658. size_t *len,
  659. enum cam_smmu_region_id region,
  660. bool is_internal)
  661. {
  662. int i;
  663. int rc = -1;
  664. int dir = cam_mem_util_get_dma_dir(flags);
  665. bool dis_delayed_unmap = false;
  666. if (dir < 0) {
  667. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  668. return dir;
  669. }
  670. if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP)
  671. dis_delayed_unmap = true;
  672. CAM_DBG(CAM_MEM,
  673. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  674. fd, flags, dir, num_hdls);
  675. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  676. for (i = 0; i < num_hdls; i++) {
  677. rc = cam_smmu_map_stage2_iova(mmu_hdls[i],
  678. fd,
  679. dir,
  680. hw_vaddr,
  681. len);
  682. if (rc < 0) {
  683. CAM_ERR(CAM_MEM,
  684. "Failed to securely map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  685. i, fd, dir, mmu_hdls[i], rc);
  686. goto multi_map_fail;
  687. }
  688. }
  689. } else {
  690. for (i = 0; i < num_hdls; i++) {
  691. rc = cam_smmu_map_user_iova(mmu_hdls[i],
  692. fd,
  693. dis_delayed_unmap,
  694. dir,
  695. (dma_addr_t *)hw_vaddr,
  696. len,
  697. region,
  698. is_internal);
  699. if (rc < 0) {
  700. CAM_ERR(CAM_MEM,
  701. "Failed to map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, region=%d, rc=%d",
  702. i, fd, dir, mmu_hdls[i], region, rc);
  703. goto multi_map_fail;
  704. }
  705. }
  706. }
  707. return rc;
  708. multi_map_fail:
  709. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  710. for (--i; i >= 0; i--)
  711. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  712. else
  713. for (--i; i >= 0; i--)
  714. cam_smmu_unmap_user_iova(mmu_hdls[i],
  715. fd,
  716. CAM_SMMU_REGION_IO);
  717. return rc;
  718. }
  719. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  720. {
  721. int rc;
  722. int32_t idx;
  723. struct dma_buf *dmabuf = NULL;
  724. int fd = -1;
  725. dma_addr_t hw_vaddr = 0;
  726. size_t len;
  727. uintptr_t kvaddr = 0;
  728. size_t klen;
  729. if (!atomic_read(&cam_mem_mgr_state)) {
  730. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  731. return -EINVAL;
  732. }
  733. if (!cmd) {
  734. CAM_ERR(CAM_MEM, " Invalid argument");
  735. return -EINVAL;
  736. }
  737. len = cmd->len;
  738. rc = cam_mem_util_check_alloc_flags(cmd);
  739. if (rc) {
  740. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  741. cmd->flags, rc);
  742. return rc;
  743. }
  744. rc = cam_mem_util_buffer_alloc(cmd,
  745. &dmabuf,
  746. &fd);
  747. if (rc) {
  748. CAM_ERR(CAM_MEM,
  749. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  750. cmd->len, cmd->align, cmd->flags, cmd->num_hdl);
  751. cam_mem_mgr_print_tbl();
  752. return rc;
  753. }
  754. idx = cam_mem_get_slot();
  755. if (idx < 0) {
  756. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  757. rc = -ENOMEM;
  758. goto slot_fail;
  759. }
  760. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  761. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  762. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  763. enum cam_smmu_region_id region;
  764. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  765. region = CAM_SMMU_REGION_IO;
  766. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  767. region = CAM_SMMU_REGION_SHARED;
  768. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  769. region = CAM_SMMU_REGION_SECHEAP;
  770. rc = cam_mem_util_map_hw_va(cmd->flags,
  771. cmd->mmu_hdls,
  772. cmd->num_hdl,
  773. fd,
  774. &hw_vaddr,
  775. &len,
  776. region,
  777. true);
  778. if (rc) {
  779. CAM_ERR(CAM_MEM,
  780. "Failed in map_hw_va len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  781. len, cmd->flags,
  782. fd, region, cmd->num_hdl, rc);
  783. if (rc == -EALREADY) {
  784. if ((size_t)dmabuf->size != len)
  785. rc = -EBADR;
  786. cam_mem_mgr_print_tbl();
  787. }
  788. goto map_hw_fail;
  789. }
  790. }
  791. mutex_lock(&tbl.bufq[idx].q_lock);
  792. tbl.bufq[idx].fd = fd;
  793. tbl.bufq[idx].dma_buf = NULL;
  794. tbl.bufq[idx].flags = cmd->flags;
  795. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  796. tbl.bufq[idx].is_internal = true;
  797. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  798. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  799. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  800. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  801. if (rc) {
  802. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  803. dmabuf, rc);
  804. goto map_kernel_fail;
  805. }
  806. }
  807. if (cmd->flags & CAM_MEM_FLAG_KMD_DEBUG_FLAG)
  808. tbl.dbg_buf_idx = idx;
  809. tbl.bufq[idx].kmdvaddr = kvaddr;
  810. tbl.bufq[idx].vaddr = hw_vaddr;
  811. tbl.bufq[idx].dma_buf = dmabuf;
  812. tbl.bufq[idx].len = cmd->len;
  813. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  814. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  815. sizeof(int32_t) * cmd->num_hdl);
  816. tbl.bufq[idx].is_imported = false;
  817. mutex_unlock(&tbl.bufq[idx].q_lock);
  818. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  819. cmd->out.fd = tbl.bufq[idx].fd;
  820. cmd->out.vaddr = 0;
  821. CAM_DBG(CAM_MEM,
  822. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  823. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  824. tbl.bufq[idx].len);
  825. return rc;
  826. map_kernel_fail:
  827. mutex_unlock(&tbl.bufq[idx].q_lock);
  828. map_hw_fail:
  829. cam_mem_put_slot(idx);
  830. slot_fail:
  831. dma_buf_put(dmabuf);
  832. return rc;
  833. }
  834. static bool cam_mem_util_is_map_internal(int32_t fd)
  835. {
  836. uint32_t i;
  837. bool is_internal = false;
  838. mutex_lock(&tbl.m_lock);
  839. for_each_set_bit(i, tbl.bitmap, tbl.bits) {
  840. if (tbl.bufq[i].fd == fd) {
  841. is_internal = tbl.bufq[i].is_internal;
  842. break;
  843. }
  844. }
  845. mutex_unlock(&tbl.m_lock);
  846. return is_internal;
  847. }
  848. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  849. {
  850. int32_t idx;
  851. int rc;
  852. struct dma_buf *dmabuf;
  853. dma_addr_t hw_vaddr = 0;
  854. size_t len = 0;
  855. bool is_internal = false;
  856. if (!atomic_read(&cam_mem_mgr_state)) {
  857. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  858. return -EINVAL;
  859. }
  860. if (!cmd || (cmd->fd < 0)) {
  861. CAM_ERR(CAM_MEM, "Invalid argument");
  862. return -EINVAL;
  863. }
  864. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  865. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  866. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  867. return -EINVAL;
  868. }
  869. rc = cam_mem_util_check_map_flags(cmd);
  870. if (rc) {
  871. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  872. return rc;
  873. }
  874. dmabuf = dma_buf_get(cmd->fd);
  875. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  876. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  877. return -EINVAL;
  878. }
  879. is_internal = cam_mem_util_is_map_internal(cmd->fd);
  880. idx = cam_mem_get_slot();
  881. if (idx < 0) {
  882. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d, fd=%d",
  883. idx, cmd->fd);
  884. rc = -ENOMEM;
  885. goto slot_fail;
  886. }
  887. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  888. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  889. rc = cam_mem_util_map_hw_va(cmd->flags,
  890. cmd->mmu_hdls,
  891. cmd->num_hdl,
  892. cmd->fd,
  893. &hw_vaddr,
  894. &len,
  895. CAM_SMMU_REGION_IO,
  896. is_internal);
  897. if (rc) {
  898. CAM_ERR(CAM_MEM,
  899. "Failed in map_hw_va, flags=0x%x, fd=%d, len=%llu, region=%d, num_hdl=%d, rc=%d",
  900. cmd->flags, cmd->fd, len,
  901. CAM_SMMU_REGION_IO, cmd->num_hdl, rc);
  902. if (rc == -EALREADY) {
  903. if ((size_t)dmabuf->size != len) {
  904. rc = -EBADR;
  905. cam_mem_mgr_print_tbl();
  906. }
  907. }
  908. goto map_fail;
  909. }
  910. }
  911. mutex_lock(&tbl.bufq[idx].q_lock);
  912. tbl.bufq[idx].fd = cmd->fd;
  913. tbl.bufq[idx].dma_buf = NULL;
  914. tbl.bufq[idx].flags = cmd->flags;
  915. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  916. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  917. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  918. tbl.bufq[idx].kmdvaddr = 0;
  919. if (cmd->num_hdl > 0)
  920. tbl.bufq[idx].vaddr = hw_vaddr;
  921. else
  922. tbl.bufq[idx].vaddr = 0;
  923. tbl.bufq[idx].dma_buf = dmabuf;
  924. tbl.bufq[idx].len = len;
  925. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  926. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  927. sizeof(int32_t) * cmd->num_hdl);
  928. tbl.bufq[idx].is_imported = true;
  929. tbl.bufq[idx].is_internal = is_internal;
  930. mutex_unlock(&tbl.bufq[idx].q_lock);
  931. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  932. cmd->out.vaddr = 0;
  933. cmd->out.size = (uint32_t)len;
  934. CAM_DBG(CAM_MEM,
  935. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  936. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  937. tbl.bufq[idx].len);
  938. return rc;
  939. map_fail:
  940. cam_mem_put_slot(idx);
  941. slot_fail:
  942. dma_buf_put(dmabuf);
  943. return rc;
  944. }
  945. static int cam_mem_util_unmap_hw_va(int32_t idx,
  946. enum cam_smmu_region_id region,
  947. enum cam_smmu_mapping_client client)
  948. {
  949. int i;
  950. uint32_t flags;
  951. int32_t *mmu_hdls;
  952. int num_hdls;
  953. int fd;
  954. int rc = 0;
  955. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  956. CAM_ERR(CAM_MEM, "Incorrect index");
  957. return -EINVAL;
  958. }
  959. flags = tbl.bufq[idx].flags;
  960. mmu_hdls = tbl.bufq[idx].hdls;
  961. num_hdls = tbl.bufq[idx].num_hdl;
  962. fd = tbl.bufq[idx].fd;
  963. CAM_DBG(CAM_MEM,
  964. "unmap_hw_va : idx=%d, fd=%x, flags=0x%x, num_hdls=%d, client=%d",
  965. idx, fd, flags, num_hdls, client);
  966. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  967. for (i = 0; i < num_hdls; i++) {
  968. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  969. if (rc < 0) {
  970. CAM_ERR(CAM_MEM,
  971. "Failed in secure unmap, i=%d, fd=%d, mmu_hdl=%d, rc=%d",
  972. i, fd, mmu_hdls[i], rc);
  973. goto unmap_end;
  974. }
  975. }
  976. } else {
  977. for (i = 0; i < num_hdls; i++) {
  978. if (client == CAM_SMMU_MAPPING_USER) {
  979. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  980. fd, region);
  981. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  982. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  983. tbl.bufq[idx].dma_buf, region);
  984. } else {
  985. CAM_ERR(CAM_MEM,
  986. "invalid caller for unmapping : %d",
  987. client);
  988. rc = -EINVAL;
  989. }
  990. if (rc < 0) {
  991. CAM_ERR(CAM_MEM,
  992. "Failed in unmap, i=%d, fd=%d, mmu_hdl=%d, region=%d, rc=%d",
  993. i, fd, mmu_hdls[i], region, rc);
  994. goto unmap_end;
  995. }
  996. }
  997. }
  998. return rc;
  999. unmap_end:
  1000. CAM_ERR(CAM_MEM, "unmapping failed");
  1001. return rc;
  1002. }
  1003. static void cam_mem_mgr_unmap_active_buf(int idx)
  1004. {
  1005. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1006. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  1007. region = CAM_SMMU_REGION_SHARED;
  1008. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1009. region = CAM_SMMU_REGION_IO;
  1010. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  1011. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)
  1012. cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1013. tbl.bufq[idx].kmdvaddr);
  1014. }
  1015. static int cam_mem_mgr_cleanup_table(void)
  1016. {
  1017. int i;
  1018. mutex_lock(&tbl.m_lock);
  1019. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  1020. if (!tbl.bufq[i].active) {
  1021. CAM_DBG(CAM_MEM,
  1022. "Buffer inactive at idx=%d, continuing", i);
  1023. continue;
  1024. } else {
  1025. CAM_DBG(CAM_MEM,
  1026. "Active buffer at idx=%d, possible leak needs unmapping",
  1027. i);
  1028. cam_mem_mgr_unmap_active_buf(i);
  1029. }
  1030. mutex_lock(&tbl.bufq[i].q_lock);
  1031. if (tbl.bufq[i].dma_buf) {
  1032. dma_buf_put(tbl.bufq[i].dma_buf);
  1033. tbl.bufq[i].dma_buf = NULL;
  1034. }
  1035. tbl.bufq[i].fd = -1;
  1036. tbl.bufq[i].flags = 0;
  1037. tbl.bufq[i].buf_handle = -1;
  1038. tbl.bufq[i].vaddr = 0;
  1039. tbl.bufq[i].len = 0;
  1040. memset(tbl.bufq[i].hdls, 0,
  1041. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  1042. tbl.bufq[i].num_hdl = 0;
  1043. tbl.bufq[i].dma_buf = NULL;
  1044. tbl.bufq[i].active = false;
  1045. tbl.bufq[i].is_internal = false;
  1046. mutex_unlock(&tbl.bufq[i].q_lock);
  1047. mutex_destroy(&tbl.bufq[i].q_lock);
  1048. }
  1049. bitmap_zero(tbl.bitmap, tbl.bits);
  1050. /* We need to reserve slot 0 because 0 is invalid */
  1051. set_bit(0, tbl.bitmap);
  1052. mutex_unlock(&tbl.m_lock);
  1053. return 0;
  1054. }
  1055. void cam_mem_mgr_deinit(void)
  1056. {
  1057. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  1058. cam_mem_mgr_cleanup_table();
  1059. debugfs_remove_recursive(tbl.dentry);
  1060. mutex_lock(&tbl.m_lock);
  1061. bitmap_zero(tbl.bitmap, tbl.bits);
  1062. kfree(tbl.bitmap);
  1063. tbl.bitmap = NULL;
  1064. tbl.dbg_buf_idx = -1;
  1065. mutex_unlock(&tbl.m_lock);
  1066. mutex_destroy(&tbl.m_lock);
  1067. }
  1068. static int cam_mem_util_unmap(int32_t idx,
  1069. enum cam_smmu_mapping_client client)
  1070. {
  1071. int rc = 0;
  1072. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1073. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1074. CAM_ERR(CAM_MEM, "Incorrect index");
  1075. return -EINVAL;
  1076. }
  1077. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  1078. mutex_lock(&tbl.m_lock);
  1079. if ((!tbl.bufq[idx].active) &&
  1080. (tbl.bufq[idx].vaddr) == 0) {
  1081. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  1082. idx);
  1083. mutex_unlock(&tbl.m_lock);
  1084. return 0;
  1085. }
  1086. /* Deactivate the buffer queue to prevent multiple unmap */
  1087. mutex_lock(&tbl.bufq[idx].q_lock);
  1088. tbl.bufq[idx].active = false;
  1089. tbl.bufq[idx].vaddr = 0;
  1090. mutex_unlock(&tbl.bufq[idx].q_lock);
  1091. mutex_unlock(&tbl.m_lock);
  1092. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1093. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  1094. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1095. tbl.bufq[idx].kmdvaddr);
  1096. if (rc)
  1097. CAM_ERR(CAM_MEM,
  1098. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  1099. tbl.bufq[idx].dma_buf,
  1100. (void *) tbl.bufq[idx].kmdvaddr);
  1101. }
  1102. }
  1103. /* SHARED flag gets precedence, all other flags after it */
  1104. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1105. region = CAM_SMMU_REGION_SHARED;
  1106. } else {
  1107. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1108. region = CAM_SMMU_REGION_IO;
  1109. }
  1110. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  1111. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  1112. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  1113. if (cam_mem_util_unmap_hw_va(idx, region, client))
  1114. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  1115. tbl.bufq[idx].dma_buf);
  1116. if (client == CAM_SMMU_MAPPING_KERNEL)
  1117. tbl.bufq[idx].dma_buf = NULL;
  1118. }
  1119. mutex_lock(&tbl.m_lock);
  1120. mutex_lock(&tbl.bufq[idx].q_lock);
  1121. tbl.bufq[idx].flags = 0;
  1122. tbl.bufq[idx].buf_handle = -1;
  1123. memset(tbl.bufq[idx].hdls, 0,
  1124. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  1125. CAM_DBG(CAM_MEM,
  1126. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK",
  1127. idx, tbl.bufq[idx].fd,
  1128. tbl.bufq[idx].is_imported,
  1129. tbl.bufq[idx].dma_buf);
  1130. if (tbl.bufq[idx].dma_buf)
  1131. dma_buf_put(tbl.bufq[idx].dma_buf);
  1132. tbl.bufq[idx].fd = -1;
  1133. tbl.bufq[idx].dma_buf = NULL;
  1134. tbl.bufq[idx].is_imported = false;
  1135. tbl.bufq[idx].is_internal = false;
  1136. tbl.bufq[idx].len = 0;
  1137. tbl.bufq[idx].num_hdl = 0;
  1138. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  1139. mutex_unlock(&tbl.bufq[idx].q_lock);
  1140. mutex_destroy(&tbl.bufq[idx].q_lock);
  1141. clear_bit(idx, tbl.bitmap);
  1142. mutex_unlock(&tbl.m_lock);
  1143. return rc;
  1144. }
  1145. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  1146. {
  1147. int idx;
  1148. int rc;
  1149. if (!atomic_read(&cam_mem_mgr_state)) {
  1150. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1151. return -EINVAL;
  1152. }
  1153. if (!cmd) {
  1154. CAM_ERR(CAM_MEM, "Invalid argument");
  1155. return -EINVAL;
  1156. }
  1157. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  1158. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1159. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  1160. idx);
  1161. return -EINVAL;
  1162. }
  1163. if (!tbl.bufq[idx].active) {
  1164. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1165. return -EINVAL;
  1166. }
  1167. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  1168. CAM_ERR(CAM_MEM,
  1169. "Released buf handle %d not matching within table %d, idx=%d",
  1170. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  1171. return -EINVAL;
  1172. }
  1173. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  1174. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  1175. return rc;
  1176. }
  1177. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  1178. struct cam_mem_mgr_memory_desc *out)
  1179. {
  1180. struct dma_buf *buf = NULL;
  1181. int ion_fd = -1;
  1182. int rc = 0;
  1183. uintptr_t kvaddr;
  1184. dma_addr_t iova = 0;
  1185. size_t request_len = 0;
  1186. uint32_t mem_handle;
  1187. int32_t idx;
  1188. int32_t smmu_hdl = 0;
  1189. int32_t num_hdl = 0;
  1190. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1191. if (!atomic_read(&cam_mem_mgr_state)) {
  1192. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1193. return -EINVAL;
  1194. }
  1195. if (!inp || !out) {
  1196. CAM_ERR(CAM_MEM, "Invalid params");
  1197. return -EINVAL;
  1198. }
  1199. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  1200. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  1201. inp->flags & CAM_MEM_FLAG_CACHE)) {
  1202. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  1203. return -EINVAL;
  1204. }
  1205. rc = cam_mem_util_get_dma_buf(inp->size,
  1206. inp->flags,
  1207. &buf);
  1208. if (rc) {
  1209. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  1210. goto ion_fail;
  1211. } else {
  1212. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1213. }
  1214. /*
  1215. * we are mapping kva always here,
  1216. * update flags so that we do unmap properly
  1217. */
  1218. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  1219. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1220. if (rc) {
  1221. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1222. goto map_fail;
  1223. }
  1224. if (!inp->smmu_hdl) {
  1225. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1226. rc = -EINVAL;
  1227. goto smmu_fail;
  1228. }
  1229. /* SHARED flag gets precedence, all other flags after it */
  1230. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1231. region = CAM_SMMU_REGION_SHARED;
  1232. } else {
  1233. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1234. region = CAM_SMMU_REGION_IO;
  1235. }
  1236. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  1237. buf,
  1238. CAM_SMMU_MAP_RW,
  1239. &iova,
  1240. &request_len,
  1241. region);
  1242. if (rc < 0) {
  1243. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  1244. goto smmu_fail;
  1245. }
  1246. smmu_hdl = inp->smmu_hdl;
  1247. num_hdl = 1;
  1248. idx = cam_mem_get_slot();
  1249. if (idx < 0) {
  1250. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1251. rc = -ENOMEM;
  1252. goto slot_fail;
  1253. }
  1254. mutex_lock(&tbl.bufq[idx].q_lock);
  1255. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1256. tbl.bufq[idx].dma_buf = buf;
  1257. tbl.bufq[idx].fd = -1;
  1258. tbl.bufq[idx].flags = inp->flags;
  1259. tbl.bufq[idx].buf_handle = mem_handle;
  1260. tbl.bufq[idx].kmdvaddr = kvaddr;
  1261. tbl.bufq[idx].vaddr = iova;
  1262. tbl.bufq[idx].len = inp->size;
  1263. tbl.bufq[idx].num_hdl = num_hdl;
  1264. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1265. sizeof(int32_t));
  1266. tbl.bufq[idx].is_imported = false;
  1267. mutex_unlock(&tbl.bufq[idx].q_lock);
  1268. out->kva = kvaddr;
  1269. out->iova = (uint32_t)iova;
  1270. out->smmu_hdl = smmu_hdl;
  1271. out->mem_handle = mem_handle;
  1272. out->len = inp->size;
  1273. out->region = region;
  1274. return rc;
  1275. slot_fail:
  1276. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  1277. buf, region);
  1278. smmu_fail:
  1279. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1280. map_fail:
  1281. dma_buf_put(buf);
  1282. ion_fail:
  1283. return rc;
  1284. }
  1285. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  1286. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  1287. {
  1288. int32_t idx;
  1289. int rc;
  1290. if (!atomic_read(&cam_mem_mgr_state)) {
  1291. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1292. return -EINVAL;
  1293. }
  1294. if (!inp) {
  1295. CAM_ERR(CAM_MEM, "Invalid argument");
  1296. return -EINVAL;
  1297. }
  1298. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1299. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1300. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1301. return -EINVAL;
  1302. }
  1303. if (!tbl.bufq[idx].active) {
  1304. if (tbl.bufq[idx].vaddr == 0) {
  1305. CAM_ERR(CAM_MEM, "buffer is released already");
  1306. return 0;
  1307. }
  1308. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1309. return -EINVAL;
  1310. }
  1311. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1312. CAM_ERR(CAM_MEM,
  1313. "Released buf handle not matching within table");
  1314. return -EINVAL;
  1315. }
  1316. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1317. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1318. return rc;
  1319. }
  1320. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1321. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1322. enum cam_smmu_region_id region,
  1323. struct cam_mem_mgr_memory_desc *out)
  1324. {
  1325. struct dma_buf *buf = NULL;
  1326. int rc = 0;
  1327. int ion_fd = -1;
  1328. dma_addr_t iova = 0;
  1329. size_t request_len = 0;
  1330. uint32_t mem_handle;
  1331. int32_t idx;
  1332. int32_t smmu_hdl = 0;
  1333. int32_t num_hdl = 0;
  1334. if (!atomic_read(&cam_mem_mgr_state)) {
  1335. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1336. return -EINVAL;
  1337. }
  1338. if (!inp || !out) {
  1339. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1340. return -EINVAL;
  1341. }
  1342. if (!inp->smmu_hdl) {
  1343. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1344. return -EINVAL;
  1345. }
  1346. if (region != CAM_SMMU_REGION_SECHEAP) {
  1347. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1348. return -EINVAL;
  1349. }
  1350. rc = cam_mem_util_get_dma_buf(inp->size,
  1351. 0,
  1352. &buf);
  1353. if (rc) {
  1354. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1355. goto ion_fail;
  1356. } else {
  1357. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1358. }
  1359. rc = cam_smmu_reserve_sec_heap(inp->smmu_hdl,
  1360. buf,
  1361. &iova,
  1362. &request_len);
  1363. if (rc) {
  1364. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1365. goto smmu_fail;
  1366. }
  1367. smmu_hdl = inp->smmu_hdl;
  1368. num_hdl = 1;
  1369. idx = cam_mem_get_slot();
  1370. if (idx < 0) {
  1371. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1372. rc = -ENOMEM;
  1373. goto slot_fail;
  1374. }
  1375. mutex_lock(&tbl.bufq[idx].q_lock);
  1376. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1377. tbl.bufq[idx].fd = -1;
  1378. tbl.bufq[idx].dma_buf = buf;
  1379. tbl.bufq[idx].flags = inp->flags;
  1380. tbl.bufq[idx].buf_handle = mem_handle;
  1381. tbl.bufq[idx].kmdvaddr = 0;
  1382. tbl.bufq[idx].vaddr = iova;
  1383. tbl.bufq[idx].len = request_len;
  1384. tbl.bufq[idx].num_hdl = num_hdl;
  1385. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1386. sizeof(int32_t));
  1387. tbl.bufq[idx].is_imported = false;
  1388. mutex_unlock(&tbl.bufq[idx].q_lock);
  1389. out->kva = 0;
  1390. out->iova = (uint32_t)iova;
  1391. out->smmu_hdl = smmu_hdl;
  1392. out->mem_handle = mem_handle;
  1393. out->len = request_len;
  1394. out->region = region;
  1395. return rc;
  1396. slot_fail:
  1397. cam_smmu_release_sec_heap(smmu_hdl);
  1398. smmu_fail:
  1399. dma_buf_put(buf);
  1400. ion_fail:
  1401. return rc;
  1402. }
  1403. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1404. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1405. {
  1406. int32_t idx;
  1407. int rc;
  1408. int32_t smmu_hdl;
  1409. if (!atomic_read(&cam_mem_mgr_state)) {
  1410. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1411. return -EINVAL;
  1412. }
  1413. if (!inp) {
  1414. CAM_ERR(CAM_MEM, "Invalid argument");
  1415. return -EINVAL;
  1416. }
  1417. if (inp->region != CAM_SMMU_REGION_SECHEAP) {
  1418. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1419. return -EINVAL;
  1420. }
  1421. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1422. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1423. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1424. return -EINVAL;
  1425. }
  1426. if (!tbl.bufq[idx].active) {
  1427. if (tbl.bufq[idx].vaddr == 0) {
  1428. CAM_ERR(CAM_MEM, "buffer is released already");
  1429. return 0;
  1430. }
  1431. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1432. return -EINVAL;
  1433. }
  1434. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1435. CAM_ERR(CAM_MEM,
  1436. "Released buf handle not matching within table");
  1437. return -EINVAL;
  1438. }
  1439. if (tbl.bufq[idx].num_hdl != 1) {
  1440. CAM_ERR(CAM_MEM,
  1441. "Sec heap region should have only one smmu hdl");
  1442. return -ENODEV;
  1443. }
  1444. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1445. sizeof(int32_t));
  1446. if (inp->smmu_hdl != smmu_hdl) {
  1447. CAM_ERR(CAM_MEM,
  1448. "Passed SMMU handle doesn't match with internal hdl");
  1449. return -ENODEV;
  1450. }
  1451. rc = cam_smmu_release_sec_heap(inp->smmu_hdl);
  1452. if (rc) {
  1453. CAM_ERR(CAM_MEM,
  1454. "Sec heap region release failed");
  1455. return -ENODEV;
  1456. }
  1457. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1458. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1459. if (rc)
  1460. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1461. return rc;
  1462. }
  1463. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);