qmi.c 109 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/soc/qcom/qmi.h>
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "main.h"
  11. #include "qmi.h"
  12. #include "genl.h"
  13. #define WLFW_SERVICE_INS_ID_V01 1
  14. #define WLFW_CLIENT_ID 0x4b4e454c
  15. #define BDF_FILE_NAME_PREFIX "bdwlan"
  16. #define ELF_BDF_FILE_NAME "bdwlan.elf"
  17. #define ELF_BDF_FILE_NAME_GF "bdwlang.elf"
  18. #define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e"
  19. #define ELF_BDF_FILE_NAME_GF_PREFIX "bdwlang.e"
  20. #define BIN_BDF_FILE_NAME "bdwlan.bin"
  21. #define BIN_BDF_FILE_NAME_GF "bdwlang.bin"
  22. #define BIN_BDF_FILE_NAME_PREFIX "bdwlan.b"
  23. #define BIN_BDF_FILE_NAME_GF_PREFIX "bdwlang.b"
  24. #define REGDB_FILE_NAME "regdb.bin"
  25. #define HDS_FILE_NAME "hds.bin"
  26. #define CHIP_ID_GF_MASK 0x10
  27. #define QDSS_TRACE_CONFIG_FILE "qdss_trace_config"
  28. /*
  29. * Download QDSS config file based on build type. Add build type string to
  30. * file name. Download "qdss_trace_config_debug_v<n>.cfg" for debug build
  31. * and "qdss_trace_config_perf_v<n>.cfg" for perf build.
  32. */
  33. #ifdef CONFIG_CNSS2_DEBUG
  34. #define QDSS_FILE_BUILD_STR "debug_"
  35. #else
  36. #define QDSS_FILE_BUILD_STR "perf_"
  37. #endif
  38. #define HW_V1_NUMBER "v1"
  39. #define HW_V2_NUMBER "v2"
  40. #define CE_MSI_NAME "CE"
  41. #define QMI_WLFW_TIMEOUT_MS (plat_priv->ctrl_params.qmi_timeout)
  42. #define QMI_WLFW_TIMEOUT_JF msecs_to_jiffies(QMI_WLFW_TIMEOUT_MS)
  43. #define COEX_TIMEOUT QMI_WLFW_TIMEOUT_JF
  44. #define IMS_TIMEOUT QMI_WLFW_TIMEOUT_JF
  45. #define QMI_WLFW_MAX_RECV_BUF_SIZE SZ_8K
  46. #define IMSPRIVATE_SERVICE_MAX_MSG_LEN SZ_8K
  47. #define DMS_QMI_MAX_MSG_LEN SZ_256
  48. #define MAX_SHADOW_REG_RESERVED 2
  49. #define MAX_NUM_SHADOW_REG_V3 (QMI_WLFW_MAX_NUM_SHADOW_REG_V3_USAGE_V01 - \
  50. MAX_SHADOW_REG_RESERVED)
  51. #define QMI_WLFW_MAC_READY_TIMEOUT_MS 50
  52. #define QMI_WLFW_MAC_READY_MAX_RETRY 200
  53. // these error values are not defined in <linux/soc/qcom/qmi.h> and fw is sending as error response
  54. #define QMI_ERR_HARDWARE_RESTRICTED_V01 0x0053
  55. #define QMI_ERR_ENOMEM_V01 0x0002
  56. enum nm_modem_bit {
  57. SLEEP_CLOCK_SELECT_INTERNAL_BIT = BIT(1),
  58. HOST_CSTATE_BIT = BIT(2),
  59. };
  60. #ifdef CONFIG_CNSS2_DEBUG
  61. static bool ignore_qmi_failure;
  62. #define CNSS_QMI_ASSERT() CNSS_ASSERT(ignore_qmi_failure)
  63. void cnss_ignore_qmi_failure(bool ignore)
  64. {
  65. ignore_qmi_failure = ignore;
  66. }
  67. #else
  68. #define CNSS_QMI_ASSERT() do { } while (0)
  69. void cnss_ignore_qmi_failure(bool ignore) { }
  70. #endif
  71. static char *cnss_qmi_mode_to_str(enum cnss_driver_mode mode)
  72. {
  73. switch (mode) {
  74. case CNSS_MISSION:
  75. return "MISSION";
  76. case CNSS_FTM:
  77. return "FTM";
  78. case CNSS_EPPING:
  79. return "EPPING";
  80. case CNSS_WALTEST:
  81. return "WALTEST";
  82. case CNSS_OFF:
  83. return "OFF";
  84. case CNSS_CCPM:
  85. return "CCPM";
  86. case CNSS_QVIT:
  87. return "QVIT";
  88. case CNSS_CALIBRATION:
  89. return "CALIBRATION";
  90. default:
  91. return "UNKNOWN";
  92. }
  93. }
  94. static int qmi_send_wait(struct qmi_handle *qmi, void *req, void *rsp,
  95. struct qmi_elem_info *req_ei,
  96. struct qmi_elem_info *rsp_ei,
  97. int req_id, size_t req_len,
  98. unsigned long timeout)
  99. {
  100. struct qmi_txn txn;
  101. int ret;
  102. char *err_msg;
  103. struct qmi_response_type_v01 *resp = rsp;
  104. ret = qmi_txn_init(qmi, &txn, rsp_ei, rsp);
  105. if (ret < 0) {
  106. err_msg = "Qmi fail: fail to init txn,";
  107. goto out;
  108. }
  109. ret = qmi_send_request(qmi, NULL, &txn, req_id,
  110. req_len, req_ei, req);
  111. if (ret < 0) {
  112. qmi_txn_cancel(&txn);
  113. err_msg = "Qmi fail: fail to send req,";
  114. goto out;
  115. }
  116. ret = qmi_txn_wait(&txn, timeout);
  117. if (ret < 0) {
  118. err_msg = "Qmi fail: wait timeout,";
  119. goto out;
  120. } else if (resp->result != QMI_RESULT_SUCCESS_V01) {
  121. err_msg = "Qmi fail: request rejected,";
  122. cnss_pr_err("Qmi fail: respons with error:%d\n",
  123. resp->error);
  124. ret = -resp->result;
  125. goto out;
  126. }
  127. cnss_pr_dbg("req %x success\n", req_id);
  128. return 0;
  129. out:
  130. cnss_pr_err("%s req %x, ret %d\n", err_msg, req_id, ret);
  131. return ret;
  132. }
  133. static int cnss_wlfw_ind_register_send_sync(struct cnss_plat_data *plat_priv)
  134. {
  135. struct wlfw_ind_register_req_msg_v01 *req;
  136. struct wlfw_ind_register_resp_msg_v01 *resp;
  137. struct qmi_txn txn;
  138. int ret = 0;
  139. cnss_pr_dbg("Sending indication register message, state: 0x%lx\n",
  140. plat_priv->driver_state);
  141. req = kzalloc(sizeof(*req), GFP_KERNEL);
  142. if (!req)
  143. return -ENOMEM;
  144. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  145. if (!resp) {
  146. kfree(req);
  147. return -ENOMEM;
  148. }
  149. req->client_id_valid = 1;
  150. req->client_id = WLFW_CLIENT_ID;
  151. req->request_mem_enable_valid = 1;
  152. req->request_mem_enable = 1;
  153. req->fw_mem_ready_enable_valid = 1;
  154. req->fw_mem_ready_enable = 1;
  155. /* fw_ready indication is replaced by fw_init_done in HST/HSP */
  156. req->fw_init_done_enable_valid = 1;
  157. req->fw_init_done_enable = 1;
  158. req->pin_connect_result_enable_valid = 1;
  159. req->pin_connect_result_enable = 1;
  160. req->cal_done_enable_valid = 1;
  161. req->cal_done_enable = 1;
  162. req->qdss_trace_req_mem_enable_valid = 1;
  163. req->qdss_trace_req_mem_enable = 1;
  164. req->qdss_trace_save_enable_valid = 1;
  165. req->qdss_trace_save_enable = 1;
  166. req->qdss_trace_free_enable_valid = 1;
  167. req->qdss_trace_free_enable = 1;
  168. req->respond_get_info_enable_valid = 1;
  169. req->respond_get_info_enable = 1;
  170. req->wfc_call_twt_config_enable_valid = 1;
  171. req->wfc_call_twt_config_enable = 1;
  172. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  173. wlfw_ind_register_resp_msg_v01_ei, resp);
  174. if (ret < 0) {
  175. cnss_pr_err("Failed to initialize txn for indication register request, err: %d\n",
  176. ret);
  177. goto out;
  178. }
  179. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  180. QMI_WLFW_IND_REGISTER_REQ_V01,
  181. WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN,
  182. wlfw_ind_register_req_msg_v01_ei, req);
  183. if (ret < 0) {
  184. qmi_txn_cancel(&txn);
  185. cnss_pr_err("Failed to send indication register request, err: %d\n",
  186. ret);
  187. goto out;
  188. }
  189. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  190. if (ret < 0) {
  191. cnss_pr_err("Failed to wait for response of indication register request, err: %d\n",
  192. ret);
  193. goto out;
  194. }
  195. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  196. cnss_pr_err("Indication register request failed, result: %d, err: %d\n",
  197. resp->resp.result, resp->resp.error);
  198. ret = -resp->resp.result;
  199. goto out;
  200. }
  201. if (resp->fw_status_valid) {
  202. if (resp->fw_status & QMI_WLFW_ALREADY_REGISTERED_V01) {
  203. ret = -EALREADY;
  204. goto qmi_registered;
  205. }
  206. }
  207. kfree(req);
  208. kfree(resp);
  209. return 0;
  210. out:
  211. CNSS_QMI_ASSERT();
  212. qmi_registered:
  213. kfree(req);
  214. kfree(resp);
  215. return ret;
  216. }
  217. static void cnss_wlfw_host_cap_parse_mlo(struct cnss_plat_data *plat_priv,
  218. struct wlfw_host_cap_req_msg_v01 *req)
  219. {
  220. if (plat_priv->device_id == KIWI_DEVICE_ID ||
  221. plat_priv->device_id == MANGO_DEVICE_ID ||
  222. plat_priv->device_id == PEACH_DEVICE_ID) {
  223. req->mlo_capable_valid = 1;
  224. req->mlo_capable = 1;
  225. req->mlo_chip_id_valid = 1;
  226. req->mlo_chip_id = 0;
  227. req->mlo_group_id_valid = 1;
  228. req->mlo_group_id = 0;
  229. req->max_mlo_peer_valid = 1;
  230. /* Max peer number generally won't change for the same device
  231. * but needs to be synced with host driver.
  232. */
  233. req->max_mlo_peer = 32;
  234. req->mlo_num_chips_valid = 1;
  235. req->mlo_num_chips = 1;
  236. req->mlo_chip_info_valid = 1;
  237. req->mlo_chip_info[0].chip_id = 0;
  238. req->mlo_chip_info[0].num_local_links = 2;
  239. req->mlo_chip_info[0].hw_link_id[0] = 0;
  240. req->mlo_chip_info[0].hw_link_id[1] = 1;
  241. req->mlo_chip_info[0].valid_mlo_link_id[0] = 1;
  242. req->mlo_chip_info[0].valid_mlo_link_id[1] = 1;
  243. }
  244. }
  245. static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv)
  246. {
  247. struct wlfw_host_cap_req_msg_v01 *req;
  248. struct wlfw_host_cap_resp_msg_v01 *resp;
  249. struct qmi_txn txn;
  250. int ret = 0;
  251. u64 iova_start = 0, iova_size = 0,
  252. iova_ipa_start = 0, iova_ipa_size = 0;
  253. u64 feature_list = 0;
  254. cnss_pr_dbg("Sending host capability message, state: 0x%lx\n",
  255. plat_priv->driver_state);
  256. req = kzalloc(sizeof(*req), GFP_KERNEL);
  257. if (!req)
  258. return -ENOMEM;
  259. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  260. if (!resp) {
  261. kfree(req);
  262. return -ENOMEM;
  263. }
  264. req->num_clients_valid = 1;
  265. req->num_clients = 1;
  266. cnss_pr_dbg("Number of clients is %d\n", req->num_clients);
  267. req->wake_msi = cnss_bus_get_wake_irq(plat_priv);
  268. if (req->wake_msi) {
  269. cnss_pr_dbg("WAKE MSI base data is %d\n", req->wake_msi);
  270. req->wake_msi_valid = 1;
  271. }
  272. req->bdf_support_valid = 1;
  273. req->bdf_support = 1;
  274. req->m3_support_valid = 1;
  275. req->m3_support = 1;
  276. req->m3_cache_support_valid = 1;
  277. req->m3_cache_support = 1;
  278. req->cal_done_valid = 1;
  279. req->cal_done = plat_priv->cal_done;
  280. cnss_pr_dbg("Calibration done is %d\n", plat_priv->cal_done);
  281. if (plat_priv->sleep_clk) {
  282. req->nm_modem_valid = 1;
  283. /* Notify firmware about the sleep clock selection,
  284. * nm_modem_bit[1] is used for this purpose.
  285. */
  286. req->nm_modem |= SLEEP_CLOCK_SELECT_INTERNAL_BIT;
  287. }
  288. if (plat_priv->supported_link_speed) {
  289. req->pcie_link_info_valid = 1;
  290. req->pcie_link_info.pci_link_speed =
  291. plat_priv->supported_link_speed;
  292. cnss_pr_dbg("Supported link speed in Host Cap %d\n",
  293. plat_priv->supported_link_speed);
  294. }
  295. if (cnss_bus_is_smmu_s1_enabled(plat_priv) &&
  296. !cnss_bus_get_iova(plat_priv, &iova_start, &iova_size) &&
  297. !cnss_bus_get_iova_ipa(plat_priv, &iova_ipa_start,
  298. &iova_ipa_size)) {
  299. req->ddr_range_valid = 1;
  300. req->ddr_range[0].start = iova_start;
  301. req->ddr_range[0].size = iova_size + iova_ipa_size;
  302. cnss_pr_dbg("Sending iova starting 0x%llx with size 0x%llx\n",
  303. req->ddr_range[0].start, req->ddr_range[0].size);
  304. }
  305. req->host_build_type_valid = 1;
  306. req->host_build_type = cnss_get_host_build_type();
  307. cnss_wlfw_host_cap_parse_mlo(plat_priv, req);
  308. ret = cnss_get_feature_list(plat_priv, &feature_list);
  309. if (!ret) {
  310. req->feature_list_valid = 1;
  311. req->feature_list = feature_list;
  312. cnss_pr_dbg("Sending feature list 0x%llx\n",
  313. req->feature_list);
  314. }
  315. if (cnss_get_platform_name(plat_priv, req->platform_name,
  316. QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01))
  317. req->platform_name_valid = 1;
  318. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  319. wlfw_host_cap_resp_msg_v01_ei, resp);
  320. if (ret < 0) {
  321. cnss_pr_err("Failed to initialize txn for host capability request, err: %d\n",
  322. ret);
  323. goto out;
  324. }
  325. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  326. QMI_WLFW_HOST_CAP_REQ_V01,
  327. WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  328. wlfw_host_cap_req_msg_v01_ei, req);
  329. if (ret < 0) {
  330. qmi_txn_cancel(&txn);
  331. cnss_pr_err("Failed to send host capability request, err: %d\n",
  332. ret);
  333. goto out;
  334. }
  335. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  336. if (ret < 0) {
  337. cnss_pr_err("Failed to wait for response of host capability request, err: %d\n",
  338. ret);
  339. goto out;
  340. }
  341. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  342. cnss_pr_err("Host capability request failed, result: %d, err: %d\n",
  343. resp->resp.result, resp->resp.error);
  344. ret = -resp->resp.result;
  345. goto out;
  346. }
  347. kfree(req);
  348. kfree(resp);
  349. return 0;
  350. out:
  351. CNSS_QMI_ASSERT();
  352. kfree(req);
  353. kfree(resp);
  354. return ret;
  355. }
  356. int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv)
  357. {
  358. struct wlfw_respond_mem_req_msg_v01 *req;
  359. struct wlfw_respond_mem_resp_msg_v01 *resp;
  360. struct qmi_txn txn;
  361. struct cnss_fw_mem *fw_mem = plat_priv->fw_mem;
  362. int ret = 0, i;
  363. cnss_pr_dbg("Sending respond memory message, state: 0x%lx\n",
  364. plat_priv->driver_state);
  365. req = kzalloc(sizeof(*req), GFP_KERNEL);
  366. if (!req)
  367. return -ENOMEM;
  368. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  369. if (!resp) {
  370. kfree(req);
  371. return -ENOMEM;
  372. }
  373. if (plat_priv->fw_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  374. cnss_pr_err("Invalid seg len %u\n", plat_priv->fw_mem_seg_len);
  375. ret = -EINVAL;
  376. goto out;
  377. }
  378. req->mem_seg_len = plat_priv->fw_mem_seg_len;
  379. for (i = 0; i < req->mem_seg_len; i++) {
  380. if (!fw_mem[i].pa || !fw_mem[i].size) {
  381. if (fw_mem[i].type == 0) {
  382. cnss_pr_err("Invalid memory for FW type, segment = %d\n",
  383. i);
  384. ret = -EINVAL;
  385. goto out;
  386. }
  387. cnss_pr_err("Memory for FW is not available for type: %u\n",
  388. fw_mem[i].type);
  389. ret = -ENOMEM;
  390. goto out;
  391. }
  392. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  393. fw_mem[i].va, &fw_mem[i].pa,
  394. fw_mem[i].size, fw_mem[i].type);
  395. req->mem_seg[i].addr = fw_mem[i].pa;
  396. req->mem_seg[i].size = fw_mem[i].size;
  397. req->mem_seg[i].type = fw_mem[i].type;
  398. }
  399. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  400. wlfw_respond_mem_resp_msg_v01_ei, resp);
  401. if (ret < 0) {
  402. cnss_pr_err("Failed to initialize txn for respond memory request, err: %d\n",
  403. ret);
  404. goto out;
  405. }
  406. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  407. QMI_WLFW_RESPOND_MEM_REQ_V01,
  408. WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN,
  409. wlfw_respond_mem_req_msg_v01_ei, req);
  410. if (ret < 0) {
  411. qmi_txn_cancel(&txn);
  412. cnss_pr_err("Failed to send respond memory request, err: %d\n",
  413. ret);
  414. goto out;
  415. }
  416. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  417. if (ret < 0) {
  418. cnss_pr_err("Failed to wait for response of respond memory request, err: %d\n",
  419. ret);
  420. goto out;
  421. }
  422. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  423. cnss_pr_err("Respond memory request failed, result: %d, err: %d\n",
  424. resp->resp.result, resp->resp.error);
  425. ret = -resp->resp.result;
  426. goto out;
  427. }
  428. kfree(req);
  429. kfree(resp);
  430. return 0;
  431. out:
  432. CNSS_QMI_ASSERT();
  433. kfree(req);
  434. kfree(resp);
  435. return ret;
  436. }
  437. int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv)
  438. {
  439. struct wlfw_cap_req_msg_v01 *req;
  440. struct wlfw_cap_resp_msg_v01 *resp;
  441. struct qmi_txn txn;
  442. char *fw_build_timestamp;
  443. int ret = 0, i;
  444. cnss_pr_dbg("Sending target capability message, state: 0x%lx\n",
  445. plat_priv->driver_state);
  446. req = kzalloc(sizeof(*req), GFP_KERNEL);
  447. if (!req)
  448. return -ENOMEM;
  449. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  450. if (!resp) {
  451. kfree(req);
  452. return -ENOMEM;
  453. }
  454. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  455. wlfw_cap_resp_msg_v01_ei, resp);
  456. if (ret < 0) {
  457. cnss_pr_err("Failed to initialize txn for target capability request, err: %d\n",
  458. ret);
  459. goto out;
  460. }
  461. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  462. QMI_WLFW_CAP_REQ_V01,
  463. WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  464. wlfw_cap_req_msg_v01_ei, req);
  465. if (ret < 0) {
  466. qmi_txn_cancel(&txn);
  467. cnss_pr_err("Failed to send respond target capability request, err: %d\n",
  468. ret);
  469. goto out;
  470. }
  471. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  472. if (ret < 0) {
  473. cnss_pr_err("Failed to wait for response of target capability request, err: %d\n",
  474. ret);
  475. goto out;
  476. }
  477. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  478. cnss_pr_err("Target capability request failed, result: %d, err: %d\n",
  479. resp->resp.result, resp->resp.error);
  480. ret = -resp->resp.result;
  481. goto out;
  482. }
  483. if (resp->chip_info_valid) {
  484. plat_priv->chip_info.chip_id = resp->chip_info.chip_id;
  485. plat_priv->chip_info.chip_family = resp->chip_info.chip_family;
  486. }
  487. if (resp->board_info_valid)
  488. plat_priv->board_info.board_id = resp->board_info.board_id;
  489. else
  490. plat_priv->board_info.board_id = 0xFF;
  491. if (resp->soc_info_valid)
  492. plat_priv->soc_info.soc_id = resp->soc_info.soc_id;
  493. if (resp->fw_version_info_valid) {
  494. plat_priv->fw_version_info.fw_version =
  495. resp->fw_version_info.fw_version;
  496. fw_build_timestamp = resp->fw_version_info.fw_build_timestamp;
  497. fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN] = '\0';
  498. strlcpy(plat_priv->fw_version_info.fw_build_timestamp,
  499. resp->fw_version_info.fw_build_timestamp,
  500. QMI_WLFW_MAX_TIMESTAMP_LEN + 1);
  501. }
  502. if (resp->fw_build_id_valid) {
  503. resp->fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN] = '\0';
  504. strlcpy(plat_priv->fw_build_id, resp->fw_build_id,
  505. QMI_WLFW_MAX_BUILD_ID_LEN + 1);
  506. }
  507. /* FW will send aop retention volatage for qca6490 */
  508. if (resp->voltage_mv_valid) {
  509. plat_priv->cpr_info.voltage = resp->voltage_mv;
  510. cnss_pr_dbg("Voltage for CPR: %dmV\n",
  511. plat_priv->cpr_info.voltage);
  512. cnss_update_cpr_info(plat_priv);
  513. }
  514. if (resp->time_freq_hz_valid) {
  515. plat_priv->device_freq_hz = resp->time_freq_hz;
  516. cnss_pr_dbg("Device frequency is %d HZ\n",
  517. plat_priv->device_freq_hz);
  518. }
  519. if (resp->otp_version_valid)
  520. plat_priv->otp_version = resp->otp_version;
  521. if (resp->dev_mem_info_valid) {
  522. for (i = 0; i < QMI_WLFW_MAX_DEV_MEM_NUM_V01; i++) {
  523. plat_priv->dev_mem_info[i].start =
  524. resp->dev_mem_info[i].start;
  525. plat_priv->dev_mem_info[i].size =
  526. resp->dev_mem_info[i].size;
  527. cnss_pr_buf("Device memory info[%d]: start = 0x%llx, size = 0x%llx\n",
  528. i, plat_priv->dev_mem_info[i].start,
  529. plat_priv->dev_mem_info[i].size);
  530. }
  531. }
  532. if (resp->fw_caps_valid) {
  533. plat_priv->fw_pcie_gen_switch =
  534. !!(resp->fw_caps & QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01);
  535. plat_priv->fw_aux_uc_support =
  536. !!(resp->fw_caps & QMI_WLFW_AUX_UC_SUPPORT_V01);
  537. cnss_pr_dbg("FW aux uc support capability: %d\n",
  538. plat_priv->fw_aux_uc_support);
  539. plat_priv->fw_caps = resp->fw_caps;
  540. }
  541. if (resp->hang_data_length_valid &&
  542. resp->hang_data_length &&
  543. resp->hang_data_length <= WLFW_MAX_HANG_EVENT_DATA_SIZE)
  544. plat_priv->hang_event_data_len = resp->hang_data_length;
  545. else
  546. plat_priv->hang_event_data_len = 0;
  547. if (resp->hang_data_addr_offset_valid)
  548. plat_priv->hang_data_addr_offset = resp->hang_data_addr_offset;
  549. else
  550. plat_priv->hang_data_addr_offset = 0;
  551. if (resp->hwid_bitmap_valid)
  552. plat_priv->hwid_bitmap = resp->hwid_bitmap;
  553. if (resp->ol_cpr_cfg_valid)
  554. cnss_aop_ol_cpr_cfg_setup(plat_priv, &resp->ol_cpr_cfg);
  555. /* Disable WLAN PDC in AOP firmware for boards which support on chip PMIC
  556. * so AOP will ignore SW_CTRL changes and do not update regulator votes.
  557. **/
  558. for (i = 0; i < plat_priv->on_chip_pmic_devices_count; i++) {
  559. if (plat_priv->board_info.board_id ==
  560. plat_priv->on_chip_pmic_board_ids[i]) {
  561. cnss_pr_dbg("Disabling WLAN PDC for board_id: %02x\n",
  562. plat_priv->board_info.board_id);
  563. ret = cnss_aop_send_msg(plat_priv,
  564. "{class: wlan_pdc, ss: rf, res: pdc, enable: 0}");
  565. if (ret < 0)
  566. cnss_pr_dbg("Failed to Send AOP Msg");
  567. break;
  568. }
  569. }
  570. cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, otp_version: 0x%x\n",
  571. plat_priv->chip_info.chip_id,
  572. plat_priv->chip_info.chip_family,
  573. plat_priv->board_info.board_id, plat_priv->soc_info.soc_id,
  574. plat_priv->otp_version);
  575. cnss_pr_dbg("fw_version: 0x%x, fw_build_timestamp: %s, fw_build_id: %s, hwid_bitmap:0x%x\n",
  576. plat_priv->fw_version_info.fw_version,
  577. plat_priv->fw_version_info.fw_build_timestamp,
  578. plat_priv->fw_build_id,
  579. plat_priv->hwid_bitmap);
  580. cnss_pr_dbg("Hang event params, Length: 0x%x, Offset Address: 0x%x\n",
  581. plat_priv->hang_event_data_len,
  582. plat_priv->hang_data_addr_offset);
  583. kfree(req);
  584. kfree(resp);
  585. return 0;
  586. out:
  587. CNSS_QMI_ASSERT();
  588. kfree(req);
  589. kfree(resp);
  590. return ret;
  591. }
  592. static char *cnss_bdf_type_to_str(enum cnss_bdf_type bdf_type)
  593. {
  594. switch (bdf_type) {
  595. case CNSS_BDF_BIN:
  596. case CNSS_BDF_ELF:
  597. return "BDF";
  598. case CNSS_BDF_REGDB:
  599. return "REGDB";
  600. case CNSS_BDF_HDS:
  601. return "HDS";
  602. default:
  603. return "UNKNOWN";
  604. }
  605. }
  606. static int cnss_get_bdf_file_name(struct cnss_plat_data *plat_priv,
  607. u32 bdf_type, char *filename,
  608. u32 filename_len)
  609. {
  610. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  611. int ret = 0;
  612. switch (bdf_type) {
  613. case CNSS_BDF_ELF:
  614. /* Board ID will be equal or less than 0xFF in GF mask case */
  615. if (plat_priv->board_info.board_id == 0xFF) {
  616. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  617. snprintf(filename_tmp, filename_len,
  618. ELF_BDF_FILE_NAME_GF);
  619. else
  620. snprintf(filename_tmp, filename_len,
  621. ELF_BDF_FILE_NAME);
  622. } else if (plat_priv->board_info.board_id < 0xFF) {
  623. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  624. snprintf(filename_tmp, filename_len,
  625. ELF_BDF_FILE_NAME_GF_PREFIX "%02x",
  626. plat_priv->board_info.board_id);
  627. else
  628. snprintf(filename_tmp, filename_len,
  629. ELF_BDF_FILE_NAME_PREFIX "%02x",
  630. plat_priv->board_info.board_id);
  631. } else {
  632. snprintf(filename_tmp, filename_len,
  633. BDF_FILE_NAME_PREFIX "%02x.e%02x",
  634. plat_priv->board_info.board_id >> 8 & 0xFF,
  635. plat_priv->board_info.board_id & 0xFF);
  636. }
  637. break;
  638. case CNSS_BDF_BIN:
  639. if (plat_priv->board_info.board_id == 0xFF) {
  640. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  641. snprintf(filename_tmp, filename_len,
  642. BIN_BDF_FILE_NAME_GF);
  643. else
  644. snprintf(filename_tmp, filename_len,
  645. BIN_BDF_FILE_NAME);
  646. } else if (plat_priv->board_info.board_id < 0xFF) {
  647. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  648. snprintf(filename_tmp, filename_len,
  649. BIN_BDF_FILE_NAME_GF_PREFIX "%02x",
  650. plat_priv->board_info.board_id);
  651. else
  652. snprintf(filename_tmp, filename_len,
  653. BIN_BDF_FILE_NAME_PREFIX "%02x",
  654. plat_priv->board_info.board_id);
  655. } else {
  656. snprintf(filename_tmp, filename_len,
  657. BDF_FILE_NAME_PREFIX "%02x.b%02x",
  658. plat_priv->board_info.board_id >> 8 & 0xFF,
  659. plat_priv->board_info.board_id & 0xFF);
  660. }
  661. break;
  662. case CNSS_BDF_REGDB:
  663. snprintf(filename_tmp, filename_len, REGDB_FILE_NAME);
  664. break;
  665. case CNSS_BDF_HDS:
  666. snprintf(filename_tmp, filename_len, HDS_FILE_NAME);
  667. break;
  668. default:
  669. cnss_pr_err("Invalid BDF type: %d\n",
  670. plat_priv->ctrl_params.bdf_type);
  671. ret = -EINVAL;
  672. break;
  673. }
  674. if (!ret)
  675. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  676. return ret;
  677. }
  678. int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
  679. u32 bdf_type)
  680. {
  681. struct wlfw_bdf_download_req_msg_v01 *req;
  682. struct wlfw_bdf_download_resp_msg_v01 *resp;
  683. struct qmi_txn txn;
  684. char filename[MAX_FIRMWARE_NAME_LEN];
  685. const struct firmware *fw_entry = NULL;
  686. const u8 *temp;
  687. unsigned int remaining;
  688. int ret = 0;
  689. cnss_pr_dbg("Sending QMI_WLFW_BDF_DOWNLOAD_REQ_V01 message for bdf_type: %d (%s), state: 0x%lx\n",
  690. bdf_type, cnss_bdf_type_to_str(bdf_type), plat_priv->driver_state);
  691. req = kzalloc(sizeof(*req), GFP_KERNEL);
  692. if (!req)
  693. return -ENOMEM;
  694. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  695. if (!resp) {
  696. kfree(req);
  697. return -ENOMEM;
  698. }
  699. ret = cnss_get_bdf_file_name(plat_priv, bdf_type,
  700. filename, sizeof(filename));
  701. if (ret)
  702. goto err_req_fw;
  703. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n", filename);
  704. if (bdf_type == CNSS_BDF_REGDB)
  705. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  706. filename);
  707. else
  708. ret = firmware_request_nowarn(&fw_entry, filename,
  709. &plat_priv->plat_dev->dev);
  710. if (ret) {
  711. cnss_pr_err("Failed to load %s: %s, ret: %d\n",
  712. cnss_bdf_type_to_str(bdf_type), filename, ret);
  713. goto err_req_fw;
  714. }
  715. temp = fw_entry->data;
  716. remaining = fw_entry->size;
  717. cnss_pr_dbg("Downloading %s: %s, size: %u\n",
  718. cnss_bdf_type_to_str(bdf_type), filename, remaining);
  719. while (remaining) {
  720. req->valid = 1;
  721. req->file_id_valid = 1;
  722. req->file_id = plat_priv->board_info.board_id;
  723. req->total_size_valid = 1;
  724. req->total_size = remaining;
  725. req->seg_id_valid = 1;
  726. req->data_valid = 1;
  727. req->end_valid = 1;
  728. req->bdf_type_valid = 1;
  729. req->bdf_type = bdf_type;
  730. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  731. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  732. } else {
  733. req->data_len = remaining;
  734. req->end = 1;
  735. }
  736. memcpy(req->data, temp, req->data_len);
  737. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  738. wlfw_bdf_download_resp_msg_v01_ei, resp);
  739. if (ret < 0) {
  740. cnss_pr_err("Failed to initialize txn for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  741. cnss_bdf_type_to_str(bdf_type), ret);
  742. goto err_send;
  743. }
  744. ret = qmi_send_request
  745. (&plat_priv->qmi_wlfw, NULL, &txn,
  746. QMI_WLFW_BDF_DOWNLOAD_REQ_V01,
  747. WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  748. wlfw_bdf_download_req_msg_v01_ei, req);
  749. if (ret < 0) {
  750. qmi_txn_cancel(&txn);
  751. cnss_pr_err("Failed to send QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  752. cnss_bdf_type_to_str(bdf_type), ret);
  753. goto err_send;
  754. }
  755. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  756. if (ret < 0) {
  757. cnss_pr_err("Timeout while waiting for FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, err: %d\n",
  758. cnss_bdf_type_to_str(bdf_type), ret);
  759. goto err_send;
  760. }
  761. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  762. cnss_pr_err("FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s failed, result: %d, err: %d\n",
  763. cnss_bdf_type_to_str(bdf_type), resp->resp.result,
  764. resp->resp.error);
  765. ret = -resp->resp.result;
  766. goto err_send;
  767. }
  768. remaining -= req->data_len;
  769. temp += req->data_len;
  770. req->seg_id++;
  771. }
  772. release_firmware(fw_entry);
  773. if (resp->host_bdf_data_valid) {
  774. /* QCA6490 enable S3E regulator for IPA configuration only */
  775. if (!(resp->host_bdf_data & QMI_WLFW_HW_XPA_V01))
  776. cnss_enable_int_pow_amp_vreg(plat_priv);
  777. plat_priv->cbc_file_download =
  778. resp->host_bdf_data & QMI_WLFW_CBC_FILE_DOWNLOAD_V01;
  779. cnss_pr_info("Host BDF config: HW_XPA: %d CalDB: %d\n",
  780. resp->host_bdf_data & QMI_WLFW_HW_XPA_V01,
  781. plat_priv->cbc_file_download);
  782. }
  783. kfree(req);
  784. kfree(resp);
  785. return 0;
  786. err_send:
  787. release_firmware(fw_entry);
  788. err_req_fw:
  789. if (!(bdf_type == CNSS_BDF_REGDB ||
  790. test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state) ||
  791. ret == -EAGAIN))
  792. CNSS_QMI_ASSERT();
  793. kfree(req);
  794. kfree(resp);
  795. return ret;
  796. }
  797. int cnss_wlfw_tme_patch_dnld_send_sync(struct cnss_plat_data *plat_priv,
  798. enum wlfw_tme_lite_file_type_v01 file)
  799. {
  800. struct wlfw_tme_lite_info_req_msg_v01 *req;
  801. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  802. struct qmi_txn txn;
  803. struct cnss_fw_mem *tme_lite_mem = &plat_priv->tme_lite_mem;
  804. int ret = 0;
  805. cnss_pr_dbg("Sending TME patch information message, state: 0x%lx\n",
  806. plat_priv->driver_state);
  807. if (plat_priv->device_id != PEACH_DEVICE_ID)
  808. return 0;
  809. req = kzalloc(sizeof(*req), GFP_KERNEL);
  810. if (!req)
  811. return -ENOMEM;
  812. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  813. if (!resp) {
  814. kfree(req);
  815. return -ENOMEM;
  816. }
  817. if (!tme_lite_mem->pa || !tme_lite_mem->size) {
  818. cnss_pr_err("Memory for TME patch is not available\n");
  819. ret = -ENOMEM;
  820. goto out;
  821. }
  822. cnss_pr_dbg("TME-L patch memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  823. tme_lite_mem->va, &tme_lite_mem->pa, tme_lite_mem->size);
  824. req->tme_file = file;
  825. req->addr = plat_priv->tme_lite_mem.pa;
  826. req->size = plat_priv->tme_lite_mem.size;
  827. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  828. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  829. if (ret < 0) {
  830. cnss_pr_err("Failed to initialize txn for TME patch information request, err: %d\n",
  831. ret);
  832. goto out;
  833. }
  834. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  835. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  836. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  837. wlfw_tme_lite_info_req_msg_v01_ei, req);
  838. if (ret < 0) {
  839. qmi_txn_cancel(&txn);
  840. cnss_pr_err("Failed to send TME patch information request, err: %d\n",
  841. ret);
  842. goto out;
  843. }
  844. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  845. if (ret < 0) {
  846. cnss_pr_err("Failed to wait for response of TME patch information request, err: %d\n",
  847. ret);
  848. goto out;
  849. }
  850. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  851. cnss_pr_err("TME patch information request failed, result: %d, err: %d\n",
  852. resp->resp.result, resp->resp.error);
  853. ret = -resp->resp.result;
  854. goto out;
  855. }
  856. kfree(req);
  857. kfree(resp);
  858. return 0;
  859. out:
  860. kfree(req);
  861. kfree(resp);
  862. return ret;
  863. }
  864. int cnss_wlfw_tme_opt_file_dnld_send_sync(struct cnss_plat_data *plat_priv,
  865. enum wlfw_tme_lite_file_type_v01 file)
  866. {
  867. struct wlfw_tme_lite_info_req_msg_v01 *req;
  868. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  869. struct qmi_txn txn;
  870. struct cnss_fw_mem *tme_opt_file_mem = NULL;
  871. char *file_name = NULL;
  872. int ret = 0;
  873. if (plat_priv->device_id != PEACH_DEVICE_ID)
  874. return 0;
  875. cnss_pr_dbg("Sending TME opt file information message, state: 0x%lx\n",
  876. plat_priv->driver_state);
  877. req = kzalloc(sizeof(*req), GFP_KERNEL);
  878. if (!req)
  879. return -ENOMEM;
  880. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  881. if (!resp) {
  882. kfree(req);
  883. return -ENOMEM;
  884. }
  885. if (file == WLFW_TME_LITE_OEM_FUSE_FILE_V01) {
  886. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[0];
  887. file_name = TME_OEM_FUSE_FILE_NAME;
  888. } else if (file == WLFW_TME_LITE_RPR_FILE_V01) {
  889. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[1];
  890. file_name = TME_RPR_FILE_NAME;
  891. } else if (file == WLFW_TME_LITE_DPR_FILE_V01) {
  892. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[2];
  893. file_name = TME_DPR_FILE_NAME;
  894. }
  895. if (!tme_opt_file_mem->pa || !tme_opt_file_mem->size) {
  896. cnss_pr_err("Memory for TME opt file is not available\n");
  897. ret = -ENOMEM;
  898. goto out;
  899. }
  900. cnss_pr_dbg("TME opt file %s memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  901. file_name, tme_opt_file_mem->va, &tme_opt_file_mem->pa, tme_opt_file_mem->size);
  902. req->tme_file = file;
  903. req->addr = tme_opt_file_mem->pa;
  904. req->size = tme_opt_file_mem->size;
  905. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  906. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  907. if (ret < 0) {
  908. cnss_pr_err("Failed to initialize txn for TME opt file information request, err: %d\n",
  909. ret);
  910. goto out;
  911. }
  912. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  913. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  914. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  915. wlfw_tme_lite_info_req_msg_v01_ei, req);
  916. if (ret < 0) {
  917. qmi_txn_cancel(&txn);
  918. cnss_pr_err("Failed to send TME opt file information request, err: %d\n",
  919. ret);
  920. goto out;
  921. }
  922. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  923. if (ret < 0) {
  924. cnss_pr_err("Failed to wait for response of TME opt file information request, err: %d\n",
  925. ret);
  926. goto out;
  927. }
  928. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  929. ret = -resp->resp.result;
  930. if (resp->resp.error == QMI_ERR_HARDWARE_RESTRICTED_V01) {
  931. cnss_pr_err("TME Power On failed\n");
  932. goto out;
  933. } else if (resp->resp.error == QMI_ERR_ENOMEM_V01) {
  934. cnss_pr_err("malloc SRAM failed\n");
  935. goto out;
  936. }
  937. cnss_pr_err("TME opt file information request failed, result: %d, err: %d\n",
  938. resp->resp.result, resp->resp.error);
  939. goto out;
  940. }
  941. kfree(req);
  942. kfree(resp);
  943. return 0;
  944. out:
  945. CNSS_QMI_ASSERT();
  946. kfree(req);
  947. kfree(resp);
  948. return ret;
  949. }
  950. int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv)
  951. {
  952. struct wlfw_m3_info_req_msg_v01 *req;
  953. struct wlfw_m3_info_resp_msg_v01 *resp;
  954. struct qmi_txn txn;
  955. struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem;
  956. int ret = 0;
  957. cnss_pr_dbg("Sending M3 information message, state: 0x%lx\n",
  958. plat_priv->driver_state);
  959. req = kzalloc(sizeof(*req), GFP_KERNEL);
  960. if (!req)
  961. return -ENOMEM;
  962. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  963. if (!resp) {
  964. kfree(req);
  965. return -ENOMEM;
  966. }
  967. if (!m3_mem->pa || !m3_mem->size) {
  968. cnss_pr_err("Memory for M3 is not available\n");
  969. ret = -ENOMEM;
  970. goto out;
  971. }
  972. cnss_pr_dbg("M3 memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  973. m3_mem->va, &m3_mem->pa, m3_mem->size);
  974. req->addr = plat_priv->m3_mem.pa;
  975. req->size = plat_priv->m3_mem.size;
  976. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  977. wlfw_m3_info_resp_msg_v01_ei, resp);
  978. if (ret < 0) {
  979. cnss_pr_err("Failed to initialize txn for M3 information request, err: %d\n",
  980. ret);
  981. goto out;
  982. }
  983. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  984. QMI_WLFW_M3_INFO_REQ_V01,
  985. WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  986. wlfw_m3_info_req_msg_v01_ei, req);
  987. if (ret < 0) {
  988. qmi_txn_cancel(&txn);
  989. cnss_pr_err("Failed to send M3 information request, err: %d\n",
  990. ret);
  991. goto out;
  992. }
  993. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  994. if (ret < 0) {
  995. cnss_pr_err("Failed to wait for response of M3 information request, err: %d\n",
  996. ret);
  997. goto out;
  998. }
  999. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1000. cnss_pr_err("M3 information request failed, result: %d, err: %d\n",
  1001. resp->resp.result, resp->resp.error);
  1002. ret = -resp->resp.result;
  1003. goto out;
  1004. }
  1005. kfree(req);
  1006. kfree(resp);
  1007. return 0;
  1008. out:
  1009. CNSS_QMI_ASSERT();
  1010. kfree(req);
  1011. kfree(resp);
  1012. return ret;
  1013. }
  1014. int cnss_wlfw_aux_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1015. {
  1016. struct wlfw_aux_uc_info_req_msg_v01 *req;
  1017. struct wlfw_aux_uc_info_resp_msg_v01 *resp;
  1018. struct qmi_txn txn;
  1019. struct cnss_fw_mem *aux_mem = &plat_priv->aux_mem;
  1020. int ret = 0;
  1021. cnss_pr_dbg("Sending QMI_WLFW_AUX_UC_INFO_REQ_V01 message, state: 0x%lx\n",
  1022. plat_priv->driver_state);
  1023. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1024. if (!req)
  1025. return -ENOMEM;
  1026. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1027. if (!resp) {
  1028. kfree(req);
  1029. return -ENOMEM;
  1030. }
  1031. if (!aux_mem->pa || !aux_mem->size) {
  1032. cnss_pr_err("Memory for AUX is not available\n");
  1033. ret = -ENOMEM;
  1034. goto out;
  1035. }
  1036. cnss_pr_dbg("AUX memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  1037. aux_mem->va, &aux_mem->pa, aux_mem->size);
  1038. req->addr = plat_priv->aux_mem.pa;
  1039. req->size = plat_priv->aux_mem.size;
  1040. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1041. wlfw_aux_uc_info_resp_msg_v01_ei, resp);
  1042. if (ret < 0) {
  1043. cnss_pr_err("Failed to initialize txn for QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1044. ret);
  1045. goto out;
  1046. }
  1047. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1048. QMI_WLFW_AUX_UC_INFO_REQ_V01,
  1049. WLFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1050. wlfw_aux_uc_info_req_msg_v01_ei, req);
  1051. if (ret < 0) {
  1052. qmi_txn_cancel(&txn);
  1053. cnss_pr_err("Failed to send QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1054. ret);
  1055. goto out;
  1056. }
  1057. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1058. if (ret < 0) {
  1059. cnss_pr_err("Failed to wait for response of QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1060. ret);
  1061. goto out;
  1062. }
  1063. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1064. cnss_pr_err("QMI_WLFW_AUX_UC_INFO_REQ_V01 request failed, result: %d, err: %d\n",
  1065. resp->resp.result, resp->resp.error);
  1066. ret = -resp->resp.result;
  1067. goto out;
  1068. }
  1069. kfree(req);
  1070. kfree(resp);
  1071. return 0;
  1072. out:
  1073. CNSS_QMI_ASSERT();
  1074. kfree(req);
  1075. kfree(resp);
  1076. return ret;
  1077. }
  1078. int cnss_wlfw_wlan_mac_req_send_sync(struct cnss_plat_data *plat_priv,
  1079. u8 *mac, u32 mac_len)
  1080. {
  1081. struct wlfw_mac_addr_req_msg_v01 req;
  1082. struct wlfw_mac_addr_resp_msg_v01 resp = {0};
  1083. struct qmi_txn txn;
  1084. int ret;
  1085. if (!plat_priv || !mac || mac_len != QMI_WLFW_MAC_ADDR_SIZE_V01)
  1086. return -EINVAL;
  1087. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1088. wlfw_mac_addr_resp_msg_v01_ei, &resp);
  1089. if (ret < 0) {
  1090. cnss_pr_err("Failed to initialize txn for mac req, err: %d\n",
  1091. ret);
  1092. ret = -EIO;
  1093. goto out;
  1094. }
  1095. cnss_pr_dbg("Sending WLAN mac req [%pM], state: 0x%lx\n",
  1096. mac, plat_priv->driver_state);
  1097. memcpy(req.mac_addr, mac, mac_len);
  1098. req.mac_addr_valid = 1;
  1099. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1100. QMI_WLFW_MAC_ADDR_REQ_V01,
  1101. WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN,
  1102. wlfw_mac_addr_req_msg_v01_ei, &req);
  1103. if (ret < 0) {
  1104. qmi_txn_cancel(&txn);
  1105. cnss_pr_err("Failed to send mac req, err: %d\n", ret);
  1106. ret = -EIO;
  1107. goto out;
  1108. }
  1109. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1110. if (ret < 0) {
  1111. cnss_pr_err("Failed to wait for resp of mac req, err: %d\n",
  1112. ret);
  1113. ret = -EIO;
  1114. goto out;
  1115. }
  1116. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1117. cnss_pr_err("WLAN mac req failed, result: %d, err: %d\n",
  1118. resp.resp.result);
  1119. ret = -resp.resp.result;
  1120. }
  1121. out:
  1122. return ret;
  1123. }
  1124. int cnss_wlfw_qdss_data_send_sync(struct cnss_plat_data *plat_priv, char *file_name,
  1125. u32 total_size)
  1126. {
  1127. int ret = 0;
  1128. struct wlfw_qdss_trace_data_req_msg_v01 *req;
  1129. struct wlfw_qdss_trace_data_resp_msg_v01 *resp;
  1130. unsigned char *p_qdss_trace_data_temp, *p_qdss_trace_data = NULL;
  1131. unsigned int remaining;
  1132. struct qmi_txn txn;
  1133. cnss_pr_dbg("%s\n", __func__);
  1134. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1135. if (!req)
  1136. return -ENOMEM;
  1137. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1138. if (!resp) {
  1139. kfree(req);
  1140. return -ENOMEM;
  1141. }
  1142. p_qdss_trace_data = kzalloc(total_size, GFP_KERNEL);
  1143. if (!p_qdss_trace_data) {
  1144. ret = ENOMEM;
  1145. goto end;
  1146. }
  1147. remaining = total_size;
  1148. p_qdss_trace_data_temp = p_qdss_trace_data;
  1149. while (remaining && resp->end == 0) {
  1150. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1151. wlfw_qdss_trace_data_resp_msg_v01_ei, resp);
  1152. if (ret < 0) {
  1153. cnss_pr_err("Fail to init txn for QDSS trace resp %d\n",
  1154. ret);
  1155. goto fail;
  1156. }
  1157. ret = qmi_send_request
  1158. (&plat_priv->qmi_wlfw, NULL, &txn,
  1159. QMI_WLFW_QDSS_TRACE_DATA_REQ_V01,
  1160. WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN,
  1161. wlfw_qdss_trace_data_req_msg_v01_ei, req);
  1162. if (ret < 0) {
  1163. qmi_txn_cancel(&txn);
  1164. cnss_pr_err("Fail to send QDSS trace data req %d\n",
  1165. ret);
  1166. goto fail;
  1167. }
  1168. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1169. if (ret < 0) {
  1170. cnss_pr_err("QDSS trace resp wait failed with rc %d\n",
  1171. ret);
  1172. goto fail;
  1173. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1174. cnss_pr_err("QMI QDSS trace request rejected, result:%d error:%d\n",
  1175. resp->resp.result, resp->resp.error);
  1176. ret = -resp->resp.result;
  1177. goto fail;
  1178. } else {
  1179. ret = 0;
  1180. }
  1181. cnss_pr_dbg("%s: response total size %d data len %d",
  1182. __func__, resp->total_size, resp->data_len);
  1183. if ((resp->total_size_valid == 1 &&
  1184. resp->total_size == total_size) &&
  1185. (resp->seg_id_valid == 1 && resp->seg_id == req->seg_id) &&
  1186. (resp->data_valid == 1 &&
  1187. resp->data_len <= QMI_WLFW_MAX_DATA_SIZE_V01) &&
  1188. resp->data_len <= remaining) {
  1189. memcpy(p_qdss_trace_data_temp,
  1190. resp->data, resp->data_len);
  1191. } else {
  1192. cnss_pr_err("%s: Unmatched qdss trace data, Expect total_size %u, seg_id %u, Recv total_size_valid %u, total_size %u, seg_id_valid %u, seg_id %u, data_len_valid %u, data_len %u",
  1193. __func__,
  1194. total_size, req->seg_id,
  1195. resp->total_size_valid,
  1196. resp->total_size,
  1197. resp->seg_id_valid,
  1198. resp->seg_id,
  1199. resp->data_valid,
  1200. resp->data_len);
  1201. ret = -1;
  1202. goto fail;
  1203. }
  1204. remaining -= resp->data_len;
  1205. p_qdss_trace_data_temp += resp->data_len;
  1206. req->seg_id++;
  1207. }
  1208. if (remaining == 0 && (resp->end_valid && resp->end)) {
  1209. ret = cnss_genl_send_msg(p_qdss_trace_data,
  1210. CNSS_GENL_MSG_TYPE_QDSS, file_name,
  1211. total_size);
  1212. if (ret < 0) {
  1213. cnss_pr_err("Fail to save QDSS trace data: %d\n",
  1214. ret);
  1215. ret = -1;
  1216. goto fail;
  1217. }
  1218. } else {
  1219. cnss_pr_err("%s: QDSS trace file corrupted: remaining %u, end_valid %u, end %u",
  1220. __func__,
  1221. remaining, resp->end_valid, resp->end);
  1222. ret = -1;
  1223. goto fail;
  1224. }
  1225. fail:
  1226. kfree(p_qdss_trace_data);
  1227. end:
  1228. kfree(req);
  1229. kfree(resp);
  1230. return ret;
  1231. }
  1232. void cnss_get_qdss_cfg_filename(struct cnss_plat_data *plat_priv,
  1233. char *filename, u32 filename_len,
  1234. bool fallback_file)
  1235. {
  1236. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  1237. char *build_str = QDSS_FILE_BUILD_STR;
  1238. if (fallback_file)
  1239. build_str = "";
  1240. if (plat_priv->device_version.major_version == FW_V2_NUMBER)
  1241. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1242. "_%s%s.cfg", build_str, HW_V2_NUMBER);
  1243. else
  1244. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1245. "_%s%s.cfg", build_str, HW_V1_NUMBER);
  1246. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  1247. }
  1248. int cnss_wlfw_qdss_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1249. {
  1250. struct wlfw_qdss_trace_config_download_req_msg_v01 *req;
  1251. struct wlfw_qdss_trace_config_download_resp_msg_v01 *resp;
  1252. struct qmi_txn txn;
  1253. const struct firmware *fw_entry = NULL;
  1254. const u8 *temp;
  1255. char qdss_cfg_filename[MAX_FIRMWARE_NAME_LEN];
  1256. unsigned int remaining;
  1257. int ret = 0;
  1258. cnss_pr_dbg("Sending QDSS config download message, state: 0x%lx\n",
  1259. plat_priv->driver_state);
  1260. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1261. if (!req)
  1262. return -ENOMEM;
  1263. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1264. if (!resp) {
  1265. kfree(req);
  1266. return -ENOMEM;
  1267. }
  1268. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1269. sizeof(qdss_cfg_filename), false);
  1270. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n",
  1271. qdss_cfg_filename);
  1272. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1273. qdss_cfg_filename);
  1274. if (ret) {
  1275. cnss_pr_dbg("Unable to load %s ret %d, try default file\n",
  1276. qdss_cfg_filename, ret);
  1277. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1278. sizeof(qdss_cfg_filename),
  1279. true);
  1280. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n",
  1281. qdss_cfg_filename);
  1282. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1283. qdss_cfg_filename);
  1284. if (ret) {
  1285. cnss_pr_err("Unable to load %s ret %d\n",
  1286. qdss_cfg_filename, ret);
  1287. goto err_req_fw;
  1288. }
  1289. }
  1290. temp = fw_entry->data;
  1291. remaining = fw_entry->size;
  1292. cnss_pr_dbg("Downloading QDSS: %s, size: %u\n",
  1293. qdss_cfg_filename, remaining);
  1294. while (remaining) {
  1295. req->total_size_valid = 1;
  1296. req->total_size = remaining;
  1297. req->seg_id_valid = 1;
  1298. req->data_valid = 1;
  1299. req->end_valid = 1;
  1300. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1301. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  1302. } else {
  1303. req->data_len = remaining;
  1304. req->end = 1;
  1305. }
  1306. memcpy(req->data, temp, req->data_len);
  1307. ret = qmi_txn_init
  1308. (&plat_priv->qmi_wlfw, &txn,
  1309. wlfw_qdss_trace_config_download_resp_msg_v01_ei,
  1310. resp);
  1311. if (ret < 0) {
  1312. cnss_pr_err("Failed to initialize txn for QDSS download request, err: %d\n",
  1313. ret);
  1314. goto err_send;
  1315. }
  1316. ret = qmi_send_request
  1317. (&plat_priv->qmi_wlfw, NULL, &txn,
  1318. QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01,
  1319. WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  1320. wlfw_qdss_trace_config_download_req_msg_v01_ei, req);
  1321. if (ret < 0) {
  1322. qmi_txn_cancel(&txn);
  1323. cnss_pr_err("Failed to send respond QDSS download request, err: %d\n",
  1324. ret);
  1325. goto err_send;
  1326. }
  1327. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1328. if (ret < 0) {
  1329. cnss_pr_err("Failed to wait for response of QDSS download request, err: %d\n",
  1330. ret);
  1331. goto err_send;
  1332. }
  1333. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1334. cnss_pr_err("QDSS download request failed, result: %d, err: %d\n",
  1335. resp->resp.result, resp->resp.error);
  1336. ret = -resp->resp.result;
  1337. goto err_send;
  1338. }
  1339. remaining -= req->data_len;
  1340. temp += req->data_len;
  1341. req->seg_id++;
  1342. }
  1343. release_firmware(fw_entry);
  1344. kfree(req);
  1345. kfree(resp);
  1346. return 0;
  1347. err_send:
  1348. release_firmware(fw_entry);
  1349. err_req_fw:
  1350. kfree(req);
  1351. kfree(resp);
  1352. return ret;
  1353. }
  1354. static int wlfw_send_qdss_trace_mode_req
  1355. (struct cnss_plat_data *plat_priv,
  1356. enum wlfw_qdss_trace_mode_enum_v01 mode,
  1357. unsigned long long option)
  1358. {
  1359. int rc = 0;
  1360. int tmp = 0;
  1361. struct wlfw_qdss_trace_mode_req_msg_v01 *req;
  1362. struct wlfw_qdss_trace_mode_resp_msg_v01 *resp;
  1363. struct qmi_txn txn;
  1364. if (!plat_priv)
  1365. return -ENODEV;
  1366. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1367. if (!req)
  1368. return -ENOMEM;
  1369. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1370. if (!resp) {
  1371. kfree(req);
  1372. return -ENOMEM;
  1373. }
  1374. req->mode_valid = 1;
  1375. req->mode = mode;
  1376. req->option_valid = 1;
  1377. req->option = option;
  1378. tmp = plat_priv->hw_trc_override;
  1379. req->hw_trc_disable_override_valid = 1;
  1380. req->hw_trc_disable_override =
  1381. (tmp > QMI_PARAM_DISABLE_V01 ? QMI_PARAM_DISABLE_V01 :
  1382. (tmp < 0 ? QMI_PARAM_INVALID_V01 : tmp));
  1383. cnss_pr_dbg("%s: mode %u, option %llu, hw_trc_disable_override: %u",
  1384. __func__, mode, option, req->hw_trc_disable_override);
  1385. rc = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1386. wlfw_qdss_trace_mode_resp_msg_v01_ei, resp);
  1387. if (rc < 0) {
  1388. cnss_pr_err("Fail to init txn for QDSS Mode resp %d\n",
  1389. rc);
  1390. goto out;
  1391. }
  1392. rc = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1393. QMI_WLFW_QDSS_TRACE_MODE_REQ_V01,
  1394. WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1395. wlfw_qdss_trace_mode_req_msg_v01_ei, req);
  1396. if (rc < 0) {
  1397. qmi_txn_cancel(&txn);
  1398. cnss_pr_err("Fail to send QDSS Mode req %d\n", rc);
  1399. goto out;
  1400. }
  1401. rc = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1402. if (rc < 0) {
  1403. cnss_pr_err("QDSS Mode resp wait failed with rc %d\n",
  1404. rc);
  1405. goto out;
  1406. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1407. cnss_pr_err("QMI QDSS Mode request rejected, result:%d error:%d\n",
  1408. resp->resp.result, resp->resp.error);
  1409. rc = -resp->resp.result;
  1410. goto out;
  1411. }
  1412. kfree(resp);
  1413. kfree(req);
  1414. return rc;
  1415. out:
  1416. kfree(resp);
  1417. kfree(req);
  1418. CNSS_QMI_ASSERT();
  1419. return rc;
  1420. }
  1421. int wlfw_qdss_trace_start(struct cnss_plat_data *plat_priv)
  1422. {
  1423. return wlfw_send_qdss_trace_mode_req(plat_priv,
  1424. QMI_WLFW_QDSS_TRACE_ON_V01, 0);
  1425. }
  1426. int wlfw_qdss_trace_stop(struct cnss_plat_data *plat_priv, unsigned long long option)
  1427. {
  1428. return wlfw_send_qdss_trace_mode_req(plat_priv, QMI_WLFW_QDSS_TRACE_OFF_V01,
  1429. option);
  1430. }
  1431. int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv,
  1432. enum cnss_driver_mode mode)
  1433. {
  1434. struct wlfw_wlan_mode_req_msg_v01 *req;
  1435. struct wlfw_wlan_mode_resp_msg_v01 *resp;
  1436. struct qmi_txn txn;
  1437. int ret = 0;
  1438. if (!plat_priv)
  1439. return -ENODEV;
  1440. cnss_pr_dbg("Sending mode message, mode: %s(%d), state: 0x%lx\n",
  1441. cnss_qmi_mode_to_str(mode), mode, plat_priv->driver_state);
  1442. if (mode == CNSS_OFF &&
  1443. test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1444. cnss_pr_dbg("Recovery is in progress, ignore mode off request\n");
  1445. return 0;
  1446. }
  1447. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1448. if (!req)
  1449. return -ENOMEM;
  1450. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1451. if (!resp) {
  1452. kfree(req);
  1453. return -ENOMEM;
  1454. }
  1455. req->mode = (enum wlfw_driver_mode_enum_v01)mode;
  1456. req->hw_debug_valid = 1;
  1457. req->hw_debug = 0;
  1458. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1459. wlfw_wlan_mode_resp_msg_v01_ei, resp);
  1460. if (ret < 0) {
  1461. cnss_pr_err("Failed to initialize txn for mode request, mode: %s(%d), err: %d\n",
  1462. cnss_qmi_mode_to_str(mode), mode, ret);
  1463. goto out;
  1464. }
  1465. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1466. QMI_WLFW_WLAN_MODE_REQ_V01,
  1467. WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1468. wlfw_wlan_mode_req_msg_v01_ei, req);
  1469. if (ret < 0) {
  1470. qmi_txn_cancel(&txn);
  1471. cnss_pr_err("Failed to send mode request, mode: %s(%d), err: %d\n",
  1472. cnss_qmi_mode_to_str(mode), mode, ret);
  1473. goto out;
  1474. }
  1475. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1476. if (ret < 0) {
  1477. cnss_pr_err("Failed to wait for response of mode request, mode: %s(%d), err: %d\n",
  1478. cnss_qmi_mode_to_str(mode), mode, ret);
  1479. goto out;
  1480. }
  1481. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1482. cnss_pr_err("Mode request failed, mode: %s(%d), result: %d, err: %d\n",
  1483. cnss_qmi_mode_to_str(mode), mode, resp->resp.result,
  1484. resp->resp.error);
  1485. ret = -resp->resp.result;
  1486. goto out;
  1487. }
  1488. kfree(req);
  1489. kfree(resp);
  1490. return 0;
  1491. out:
  1492. if (mode == CNSS_OFF) {
  1493. cnss_pr_dbg("WLFW service is disconnected while sending mode off request\n");
  1494. ret = 0;
  1495. } else {
  1496. CNSS_QMI_ASSERT();
  1497. }
  1498. kfree(req);
  1499. kfree(resp);
  1500. return ret;
  1501. }
  1502. int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
  1503. struct cnss_wlan_enable_cfg *config,
  1504. const char *host_version)
  1505. {
  1506. struct wlfw_wlan_cfg_req_msg_v01 *req;
  1507. struct wlfw_wlan_cfg_resp_msg_v01 *resp;
  1508. struct qmi_txn txn;
  1509. u32 i, ce_id, num_vectors, user_base_data, base_vector;
  1510. int ret = 0;
  1511. if (!plat_priv)
  1512. return -ENODEV;
  1513. cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n",
  1514. plat_priv->driver_state);
  1515. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1516. if (!req)
  1517. return -ENOMEM;
  1518. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1519. if (!resp) {
  1520. kfree(req);
  1521. return -ENOMEM;
  1522. }
  1523. req->host_version_valid = 1;
  1524. strlcpy(req->host_version, host_version,
  1525. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  1526. req->tgt_cfg_valid = 1;
  1527. if (config->num_ce_tgt_cfg > QMI_WLFW_MAX_NUM_CE_V01)
  1528. req->tgt_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1529. else
  1530. req->tgt_cfg_len = config->num_ce_tgt_cfg;
  1531. for (i = 0; i < req->tgt_cfg_len; i++) {
  1532. req->tgt_cfg[i].pipe_num = config->ce_tgt_cfg[i].pipe_num;
  1533. req->tgt_cfg[i].pipe_dir = config->ce_tgt_cfg[i].pipe_dir;
  1534. req->tgt_cfg[i].nentries = config->ce_tgt_cfg[i].nentries;
  1535. req->tgt_cfg[i].nbytes_max = config->ce_tgt_cfg[i].nbytes_max;
  1536. req->tgt_cfg[i].flags = config->ce_tgt_cfg[i].flags;
  1537. }
  1538. req->svc_cfg_valid = 1;
  1539. if (config->num_ce_svc_pipe_cfg > QMI_WLFW_MAX_NUM_SVC_V01)
  1540. req->svc_cfg_len = QMI_WLFW_MAX_NUM_SVC_V01;
  1541. else
  1542. req->svc_cfg_len = config->num_ce_svc_pipe_cfg;
  1543. for (i = 0; i < req->svc_cfg_len; i++) {
  1544. req->svc_cfg[i].service_id = config->ce_svc_cfg[i].service_id;
  1545. req->svc_cfg[i].pipe_dir = config->ce_svc_cfg[i].pipe_dir;
  1546. req->svc_cfg[i].pipe_num = config->ce_svc_cfg[i].pipe_num;
  1547. }
  1548. if (plat_priv->device_id != KIWI_DEVICE_ID &&
  1549. plat_priv->device_id != MANGO_DEVICE_ID &&
  1550. plat_priv->device_id != PEACH_DEVICE_ID) {
  1551. if (plat_priv->device_id == QCN7605_DEVICE_ID &&
  1552. config->num_shadow_reg_cfg) {
  1553. req->shadow_reg_valid = 1;
  1554. if (config->num_shadow_reg_cfg >
  1555. QMI_WLFW_MAX_NUM_SHADOW_REG_V01)
  1556. req->shadow_reg_len =
  1557. QMI_WLFW_MAX_NUM_SHADOW_REG_V01;
  1558. else
  1559. req->shadow_reg_len =
  1560. config->num_shadow_reg_cfg;
  1561. memcpy(req->shadow_reg, config->shadow_reg_cfg,
  1562. sizeof(struct wlfw_shadow_reg_cfg_s_v01) *
  1563. req->shadow_reg_len);
  1564. } else {
  1565. req->shadow_reg_v2_valid = 1;
  1566. if (config->num_shadow_reg_v2_cfg >
  1567. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01)
  1568. req->shadow_reg_v2_len =
  1569. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01;
  1570. else
  1571. req->shadow_reg_v2_len =
  1572. config->num_shadow_reg_v2_cfg;
  1573. memcpy(req->shadow_reg_v2, config->shadow_reg_v2_cfg,
  1574. sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01) *
  1575. req->shadow_reg_v2_len);
  1576. }
  1577. } else {
  1578. req->shadow_reg_v3_valid = 1;
  1579. if (config->num_shadow_reg_v3_cfg >
  1580. MAX_NUM_SHADOW_REG_V3)
  1581. req->shadow_reg_v3_len = MAX_NUM_SHADOW_REG_V3;
  1582. else
  1583. req->shadow_reg_v3_len = config->num_shadow_reg_v3_cfg;
  1584. plat_priv->num_shadow_regs_v3 = req->shadow_reg_v3_len;
  1585. cnss_pr_dbg("Shadow reg v3 len: %d\n",
  1586. plat_priv->num_shadow_regs_v3);
  1587. memcpy(req->shadow_reg_v3, config->shadow_reg_v3_cfg,
  1588. sizeof(struct wlfw_shadow_reg_v3_cfg_s_v01) *
  1589. req->shadow_reg_v3_len);
  1590. }
  1591. if (config->rri_over_ddr_cfg_valid) {
  1592. req->rri_over_ddr_cfg_valid = 1;
  1593. req->rri_over_ddr_cfg.base_addr_low =
  1594. config->rri_over_ddr_cfg.base_addr_low;
  1595. req->rri_over_ddr_cfg.base_addr_high =
  1596. config->rri_over_ddr_cfg.base_addr_high;
  1597. }
  1598. if (config->send_msi_ce) {
  1599. ret = cnss_bus_get_msi_assignment(plat_priv,
  1600. CE_MSI_NAME,
  1601. &num_vectors,
  1602. &user_base_data,
  1603. &base_vector);
  1604. if (!ret) {
  1605. req->msi_cfg_valid = 1;
  1606. req->msi_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1607. for (ce_id = 0; ce_id < QMI_WLFW_MAX_NUM_CE_V01;
  1608. ce_id++) {
  1609. req->msi_cfg[ce_id].ce_id = ce_id;
  1610. req->msi_cfg[ce_id].msi_vector =
  1611. (ce_id % num_vectors) + base_vector;
  1612. }
  1613. }
  1614. }
  1615. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1616. wlfw_wlan_cfg_resp_msg_v01_ei, resp);
  1617. if (ret < 0) {
  1618. cnss_pr_err("Failed to initialize txn for WLAN config request, err: %d\n",
  1619. ret);
  1620. goto out;
  1621. }
  1622. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1623. QMI_WLFW_WLAN_CFG_REQ_V01,
  1624. WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN,
  1625. wlfw_wlan_cfg_req_msg_v01_ei, req);
  1626. if (ret < 0) {
  1627. qmi_txn_cancel(&txn);
  1628. cnss_pr_err("Failed to send WLAN config request, err: %d\n",
  1629. ret);
  1630. goto out;
  1631. }
  1632. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1633. if (ret < 0) {
  1634. cnss_pr_err("Failed to wait for response of WLAN config request, err: %d\n",
  1635. ret);
  1636. goto out;
  1637. }
  1638. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1639. cnss_pr_err("WLAN config request failed, result: %d, err: %d\n",
  1640. resp->resp.result, resp->resp.error);
  1641. ret = -resp->resp.result;
  1642. goto out;
  1643. }
  1644. kfree(req);
  1645. kfree(resp);
  1646. return 0;
  1647. out:
  1648. CNSS_QMI_ASSERT();
  1649. kfree(req);
  1650. kfree(resp);
  1651. return ret;
  1652. }
  1653. int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv,
  1654. u32 offset, u32 mem_type,
  1655. u32 data_len, u8 *data)
  1656. {
  1657. struct wlfw_athdiag_read_req_msg_v01 *req;
  1658. struct wlfw_athdiag_read_resp_msg_v01 *resp;
  1659. struct qmi_txn txn;
  1660. int ret = 0;
  1661. if (!plat_priv)
  1662. return -ENODEV;
  1663. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1664. cnss_pr_err("Invalid parameters for athdiag read: data %pK, data_len %u\n",
  1665. data, data_len);
  1666. return -EINVAL;
  1667. }
  1668. cnss_pr_dbg("athdiag read: state 0x%lx, offset %x, mem_type %x, data_len %u\n",
  1669. plat_priv->driver_state, offset, mem_type, data_len);
  1670. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1671. if (!req)
  1672. return -ENOMEM;
  1673. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1674. if (!resp) {
  1675. kfree(req);
  1676. return -ENOMEM;
  1677. }
  1678. req->offset = offset;
  1679. req->mem_type = mem_type;
  1680. req->data_len = data_len;
  1681. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1682. wlfw_athdiag_read_resp_msg_v01_ei, resp);
  1683. if (ret < 0) {
  1684. cnss_pr_err("Failed to initialize txn for athdiag read request, err: %d\n",
  1685. ret);
  1686. goto out;
  1687. }
  1688. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1689. QMI_WLFW_ATHDIAG_READ_REQ_V01,
  1690. WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN,
  1691. wlfw_athdiag_read_req_msg_v01_ei, req);
  1692. if (ret < 0) {
  1693. qmi_txn_cancel(&txn);
  1694. cnss_pr_err("Failed to send athdiag read request, err: %d\n",
  1695. ret);
  1696. goto out;
  1697. }
  1698. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1699. if (ret < 0) {
  1700. cnss_pr_err("Failed to wait for response of athdiag read request, err: %d\n",
  1701. ret);
  1702. goto out;
  1703. }
  1704. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1705. cnss_pr_err("Athdiag read request failed, result: %d, err: %d\n",
  1706. resp->resp.result, resp->resp.error);
  1707. ret = -resp->resp.result;
  1708. goto out;
  1709. }
  1710. if (!resp->data_valid || resp->data_len != data_len) {
  1711. cnss_pr_err("athdiag read data is invalid, data_valid = %u, data_len = %u\n",
  1712. resp->data_valid, resp->data_len);
  1713. ret = -EINVAL;
  1714. goto out;
  1715. }
  1716. memcpy(data, resp->data, resp->data_len);
  1717. kfree(req);
  1718. kfree(resp);
  1719. return 0;
  1720. out:
  1721. kfree(req);
  1722. kfree(resp);
  1723. return ret;
  1724. }
  1725. int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv,
  1726. u32 offset, u32 mem_type,
  1727. u32 data_len, u8 *data)
  1728. {
  1729. struct wlfw_athdiag_write_req_msg_v01 *req;
  1730. struct wlfw_athdiag_write_resp_msg_v01 *resp;
  1731. struct qmi_txn txn;
  1732. int ret = 0;
  1733. if (!plat_priv)
  1734. return -ENODEV;
  1735. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1736. cnss_pr_err("Invalid parameters for athdiag write: data %pK, data_len %u\n",
  1737. data, data_len);
  1738. return -EINVAL;
  1739. }
  1740. cnss_pr_dbg("athdiag write: state 0x%lx, offset %x, mem_type %x, data_len %u, data %pK\n",
  1741. plat_priv->driver_state, offset, mem_type, data_len, data);
  1742. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1743. if (!req)
  1744. return -ENOMEM;
  1745. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1746. if (!resp) {
  1747. kfree(req);
  1748. return -ENOMEM;
  1749. }
  1750. req->offset = offset;
  1751. req->mem_type = mem_type;
  1752. req->data_len = data_len;
  1753. memcpy(req->data, data, data_len);
  1754. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1755. wlfw_athdiag_write_resp_msg_v01_ei, resp);
  1756. if (ret < 0) {
  1757. cnss_pr_err("Failed to initialize txn for athdiag write request, err: %d\n",
  1758. ret);
  1759. goto out;
  1760. }
  1761. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1762. QMI_WLFW_ATHDIAG_WRITE_REQ_V01,
  1763. WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN,
  1764. wlfw_athdiag_write_req_msg_v01_ei, req);
  1765. if (ret < 0) {
  1766. qmi_txn_cancel(&txn);
  1767. cnss_pr_err("Failed to send athdiag write request, err: %d\n",
  1768. ret);
  1769. goto out;
  1770. }
  1771. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1772. if (ret < 0) {
  1773. cnss_pr_err("Failed to wait for response of athdiag write request, err: %d\n",
  1774. ret);
  1775. goto out;
  1776. }
  1777. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1778. cnss_pr_err("Athdiag write request failed, result: %d, err: %d\n",
  1779. resp->resp.result, resp->resp.error);
  1780. ret = -resp->resp.result;
  1781. goto out;
  1782. }
  1783. kfree(req);
  1784. kfree(resp);
  1785. return 0;
  1786. out:
  1787. kfree(req);
  1788. kfree(resp);
  1789. return ret;
  1790. }
  1791. int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv,
  1792. u8 fw_log_mode)
  1793. {
  1794. struct wlfw_ini_req_msg_v01 *req;
  1795. struct wlfw_ini_resp_msg_v01 *resp;
  1796. struct qmi_txn txn;
  1797. int ret = 0;
  1798. if (!plat_priv)
  1799. return -ENODEV;
  1800. cnss_pr_dbg("Sending ini sync request, state: 0x%lx, fw_log_mode: %d\n",
  1801. plat_priv->driver_state, fw_log_mode);
  1802. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1803. if (!req)
  1804. return -ENOMEM;
  1805. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1806. if (!resp) {
  1807. kfree(req);
  1808. return -ENOMEM;
  1809. }
  1810. req->enablefwlog_valid = 1;
  1811. req->enablefwlog = fw_log_mode;
  1812. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1813. wlfw_ini_resp_msg_v01_ei, resp);
  1814. if (ret < 0) {
  1815. cnss_pr_err("Failed to initialize txn for ini request, fw_log_mode: %d, err: %d\n",
  1816. fw_log_mode, ret);
  1817. goto out;
  1818. }
  1819. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1820. QMI_WLFW_INI_REQ_V01,
  1821. WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN,
  1822. wlfw_ini_req_msg_v01_ei, req);
  1823. if (ret < 0) {
  1824. qmi_txn_cancel(&txn);
  1825. cnss_pr_err("Failed to send ini request, fw_log_mode: %d, err: %d\n",
  1826. fw_log_mode, ret);
  1827. goto out;
  1828. }
  1829. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1830. if (ret < 0) {
  1831. cnss_pr_err("Failed to wait for response of ini request, fw_log_mode: %d, err: %d\n",
  1832. fw_log_mode, ret);
  1833. goto out;
  1834. }
  1835. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1836. cnss_pr_err("Ini request failed, fw_log_mode: %d, result: %d, err: %d\n",
  1837. fw_log_mode, resp->resp.result, resp->resp.error);
  1838. ret = -resp->resp.result;
  1839. goto out;
  1840. }
  1841. kfree(req);
  1842. kfree(resp);
  1843. return 0;
  1844. out:
  1845. kfree(req);
  1846. kfree(resp);
  1847. return ret;
  1848. }
  1849. int cnss_wlfw_send_pcie_gen_speed_sync(struct cnss_plat_data *plat_priv)
  1850. {
  1851. struct wlfw_pcie_gen_switch_req_msg_v01 req;
  1852. struct wlfw_pcie_gen_switch_resp_msg_v01 resp = {0};
  1853. struct qmi_txn txn;
  1854. int ret = 0;
  1855. if (!plat_priv)
  1856. return -ENODEV;
  1857. if (plat_priv->pcie_gen_speed == QMI_PCIE_GEN_SPEED_INVALID_V01 ||
  1858. !plat_priv->fw_pcie_gen_switch) {
  1859. cnss_pr_dbg("PCIE Gen speed not setup\n");
  1860. return 0;
  1861. }
  1862. cnss_pr_dbg("Sending PCIE Gen speed: %d state: 0x%lx\n",
  1863. plat_priv->pcie_gen_speed, plat_priv->driver_state);
  1864. req.pcie_speed = (enum wlfw_pcie_gen_speed_v01)
  1865. plat_priv->pcie_gen_speed;
  1866. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1867. wlfw_pcie_gen_switch_resp_msg_v01_ei, &resp);
  1868. if (ret < 0) {
  1869. cnss_pr_err("Failed to initialize txn for PCIE speed switch err: %d\n",
  1870. ret);
  1871. goto out;
  1872. }
  1873. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1874. QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01,
  1875. WLFW_PCIE_GEN_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1876. wlfw_pcie_gen_switch_req_msg_v01_ei, &req);
  1877. if (ret < 0) {
  1878. qmi_txn_cancel(&txn);
  1879. cnss_pr_err("Failed to send PCIE speed switch, err: %d\n", ret);
  1880. goto out;
  1881. }
  1882. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1883. if (ret < 0) {
  1884. cnss_pr_err("Failed to wait for PCIE Gen switch resp, err: %d\n",
  1885. ret);
  1886. goto out;
  1887. }
  1888. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1889. cnss_pr_err("PCIE Gen Switch req failed, Speed: %d, result: %d, err: %d\n",
  1890. plat_priv->pcie_gen_speed, resp.resp.result,
  1891. resp.resp.error);
  1892. ret = -resp.resp.result;
  1893. }
  1894. out:
  1895. /* Reset PCIE Gen speed after one time use */
  1896. plat_priv->pcie_gen_speed = QMI_PCIE_GEN_SPEED_INVALID_V01;
  1897. return ret;
  1898. }
  1899. int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv)
  1900. {
  1901. struct wlfw_antenna_switch_req_msg_v01 *req;
  1902. struct wlfw_antenna_switch_resp_msg_v01 *resp;
  1903. struct qmi_txn txn;
  1904. int ret = 0;
  1905. if (!plat_priv)
  1906. return -ENODEV;
  1907. cnss_pr_dbg("Sending antenna switch sync request, state: 0x%lx\n",
  1908. plat_priv->driver_state);
  1909. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1910. if (!req)
  1911. return -ENOMEM;
  1912. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1913. if (!resp) {
  1914. kfree(req);
  1915. return -ENOMEM;
  1916. }
  1917. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1918. wlfw_antenna_switch_resp_msg_v01_ei, resp);
  1919. if (ret < 0) {
  1920. cnss_pr_err("Failed to initialize txn for antenna switch request, err: %d\n",
  1921. ret);
  1922. goto out;
  1923. }
  1924. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1925. QMI_WLFW_ANTENNA_SWITCH_REQ_V01,
  1926. WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1927. wlfw_antenna_switch_req_msg_v01_ei, req);
  1928. if (ret < 0) {
  1929. qmi_txn_cancel(&txn);
  1930. cnss_pr_err("Failed to send antenna switch request, err: %d\n",
  1931. ret);
  1932. goto out;
  1933. }
  1934. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1935. if (ret < 0) {
  1936. cnss_pr_err("Failed to wait for response of antenna switch request, err: %d\n",
  1937. ret);
  1938. goto out;
  1939. }
  1940. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1941. cnss_pr_dbg("Antenna switch request failed, result: %d, err: %d\n",
  1942. resp->resp.result, resp->resp.error);
  1943. ret = -resp->resp.result;
  1944. goto out;
  1945. }
  1946. if (resp->antenna_valid)
  1947. plat_priv->antenna = resp->antenna;
  1948. cnss_pr_dbg("Antenna valid: %u, antenna 0x%llx\n",
  1949. resp->antenna_valid, resp->antenna);
  1950. kfree(req);
  1951. kfree(resp);
  1952. return 0;
  1953. out:
  1954. kfree(req);
  1955. kfree(resp);
  1956. return ret;
  1957. }
  1958. int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv)
  1959. {
  1960. struct wlfw_antenna_grant_req_msg_v01 *req;
  1961. struct wlfw_antenna_grant_resp_msg_v01 *resp;
  1962. struct qmi_txn txn;
  1963. int ret = 0;
  1964. if (!plat_priv)
  1965. return -ENODEV;
  1966. cnss_pr_dbg("Sending antenna grant sync request, state: 0x%lx, grant 0x%llx\n",
  1967. plat_priv->driver_state, plat_priv->grant);
  1968. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1969. if (!req)
  1970. return -ENOMEM;
  1971. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1972. if (!resp) {
  1973. kfree(req);
  1974. return -ENOMEM;
  1975. }
  1976. req->grant_valid = 1;
  1977. req->grant = plat_priv->grant;
  1978. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1979. wlfw_antenna_grant_resp_msg_v01_ei, resp);
  1980. if (ret < 0) {
  1981. cnss_pr_err("Failed to initialize txn for antenna grant request, err: %d\n",
  1982. ret);
  1983. goto out;
  1984. }
  1985. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1986. QMI_WLFW_ANTENNA_GRANT_REQ_V01,
  1987. WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN,
  1988. wlfw_antenna_grant_req_msg_v01_ei, req);
  1989. if (ret < 0) {
  1990. qmi_txn_cancel(&txn);
  1991. cnss_pr_err("Failed to send antenna grant request, err: %d\n",
  1992. ret);
  1993. goto out;
  1994. }
  1995. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1996. if (ret < 0) {
  1997. cnss_pr_err("Failed to wait for response of antenna grant request, err: %d\n",
  1998. ret);
  1999. goto out;
  2000. }
  2001. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2002. cnss_pr_err("Antenna grant request failed, result: %d, err: %d\n",
  2003. resp->resp.result, resp->resp.error);
  2004. ret = -resp->resp.result;
  2005. goto out;
  2006. }
  2007. kfree(req);
  2008. kfree(resp);
  2009. return 0;
  2010. out:
  2011. kfree(req);
  2012. kfree(resp);
  2013. return ret;
  2014. }
  2015. int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv)
  2016. {
  2017. struct wlfw_qdss_trace_mem_info_req_msg_v01 *req;
  2018. struct wlfw_qdss_trace_mem_info_resp_msg_v01 *resp;
  2019. struct qmi_txn txn;
  2020. struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem;
  2021. int ret = 0;
  2022. int i;
  2023. cnss_pr_dbg("Sending QDSS trace mem info, state: 0x%lx\n",
  2024. plat_priv->driver_state);
  2025. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2026. if (!req)
  2027. return -ENOMEM;
  2028. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2029. if (!resp) {
  2030. kfree(req);
  2031. return -ENOMEM;
  2032. }
  2033. if (plat_priv->qdss_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2034. cnss_pr_err("Invalid seg len %u\n", plat_priv->qdss_mem_seg_len);
  2035. ret = -EINVAL;
  2036. goto out;
  2037. }
  2038. req->mem_seg_len = plat_priv->qdss_mem_seg_len;
  2039. for (i = 0; i < req->mem_seg_len; i++) {
  2040. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  2041. qdss_mem[i].va, &qdss_mem[i].pa,
  2042. qdss_mem[i].size, qdss_mem[i].type);
  2043. req->mem_seg[i].addr = qdss_mem[i].pa;
  2044. req->mem_seg[i].size = qdss_mem[i].size;
  2045. req->mem_seg[i].type = qdss_mem[i].type;
  2046. }
  2047. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2048. wlfw_qdss_trace_mem_info_resp_msg_v01_ei, resp);
  2049. if (ret < 0) {
  2050. cnss_pr_err("Fail to initialize txn for QDSS trace mem request: err %d\n",
  2051. ret);
  2052. goto out;
  2053. }
  2054. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2055. QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01,
  2056. WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2057. wlfw_qdss_trace_mem_info_req_msg_v01_ei, req);
  2058. if (ret < 0) {
  2059. qmi_txn_cancel(&txn);
  2060. cnss_pr_err("Fail to send QDSS trace mem info request: err %d\n",
  2061. ret);
  2062. goto out;
  2063. }
  2064. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2065. if (ret < 0) {
  2066. cnss_pr_err("Fail to wait for response of QDSS trace mem info request, err %d\n",
  2067. ret);
  2068. goto out;
  2069. }
  2070. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2071. cnss_pr_err("QDSS trace mem info request failed, result: %d, err: %d\n",
  2072. resp->resp.result, resp->resp.error);
  2073. ret = -resp->resp.result;
  2074. goto out;
  2075. }
  2076. kfree(req);
  2077. kfree(resp);
  2078. return 0;
  2079. out:
  2080. kfree(req);
  2081. kfree(resp);
  2082. return ret;
  2083. }
  2084. int cnss_wlfw_send_host_wfc_call_status(struct cnss_plat_data *plat_priv,
  2085. struct cnss_wfc_cfg cfg)
  2086. {
  2087. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2088. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2089. struct qmi_txn txn;
  2090. int ret = 0;
  2091. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2092. cnss_pr_err("Drop host WFC indication as FW not initialized\n");
  2093. return -EINVAL;
  2094. }
  2095. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2096. if (!req)
  2097. return -ENOMEM;
  2098. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2099. if (!resp) {
  2100. kfree(req);
  2101. return -ENOMEM;
  2102. }
  2103. req->wfc_call_active_valid = 1;
  2104. req->wfc_call_active = cfg.mode;
  2105. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2106. plat_priv->driver_state);
  2107. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2108. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2109. if (ret < 0) {
  2110. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2111. ret);
  2112. goto out;
  2113. }
  2114. cnss_pr_dbg("Send WFC Mode: %d\n", cfg.mode);
  2115. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2116. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2117. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2118. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2119. if (ret < 0) {
  2120. qmi_txn_cancel(&txn);
  2121. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2122. ret);
  2123. goto out;
  2124. }
  2125. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2126. if (ret < 0) {
  2127. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2128. ret);
  2129. goto out;
  2130. }
  2131. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2132. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2133. resp->resp.result, resp->resp.error);
  2134. ret = -EINVAL;
  2135. goto out;
  2136. }
  2137. ret = 0;
  2138. out:
  2139. kfree(req);
  2140. kfree(resp);
  2141. return ret;
  2142. }
  2143. static int cnss_wlfw_wfc_call_status_send_sync
  2144. (struct cnss_plat_data *plat_priv,
  2145. const struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg)
  2146. {
  2147. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2148. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2149. struct qmi_txn txn;
  2150. int ret = 0;
  2151. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2152. cnss_pr_err("Drop IMS WFC indication as FW not initialized\n");
  2153. return -EINVAL;
  2154. }
  2155. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2156. if (!req)
  2157. return -ENOMEM;
  2158. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2159. if (!resp) {
  2160. kfree(req);
  2161. return -ENOMEM;
  2162. }
  2163. /**
  2164. * WFC Call r1 design has CNSS as pass thru using opaque hex buffer.
  2165. * But in r2 update QMI structure is expanded and as an effect qmi
  2166. * decoded structures have padding. Thus we cannot use buffer design.
  2167. * For backward compatibility for r1 design copy only wfc_call_active
  2168. * value in hex buffer.
  2169. */
  2170. req->wfc_call_status_len = sizeof(ind_msg->wfc_call_active);
  2171. req->wfc_call_status[0] = ind_msg->wfc_call_active;
  2172. /* wfc_call_active is mandatory in IMS indication */
  2173. req->wfc_call_active_valid = 1;
  2174. req->wfc_call_active = ind_msg->wfc_call_active;
  2175. req->all_wfc_calls_held_valid = ind_msg->all_wfc_calls_held_valid;
  2176. req->all_wfc_calls_held = ind_msg->all_wfc_calls_held;
  2177. req->is_wfc_emergency_valid = ind_msg->is_wfc_emergency_valid;
  2178. req->is_wfc_emergency = ind_msg->is_wfc_emergency;
  2179. req->twt_ims_start_valid = ind_msg->twt_ims_start_valid;
  2180. req->twt_ims_start = ind_msg->twt_ims_start;
  2181. req->twt_ims_int_valid = ind_msg->twt_ims_int_valid;
  2182. req->twt_ims_int = ind_msg->twt_ims_int;
  2183. req->media_quality_valid = ind_msg->media_quality_valid;
  2184. req->media_quality =
  2185. (enum wlfw_wfc_media_quality_v01)ind_msg->media_quality;
  2186. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2187. plat_priv->driver_state);
  2188. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2189. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2190. if (ret < 0) {
  2191. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2192. ret);
  2193. goto out;
  2194. }
  2195. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2196. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2197. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2198. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2199. if (ret < 0) {
  2200. qmi_txn_cancel(&txn);
  2201. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2202. ret);
  2203. goto out;
  2204. }
  2205. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2206. if (ret < 0) {
  2207. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2208. ret);
  2209. goto out;
  2210. }
  2211. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2212. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2213. resp->resp.result, resp->resp.error);
  2214. ret = -resp->resp.result;
  2215. goto out;
  2216. }
  2217. ret = 0;
  2218. out:
  2219. kfree(req);
  2220. kfree(resp);
  2221. return ret;
  2222. }
  2223. int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv)
  2224. {
  2225. struct wlfw_dynamic_feature_mask_req_msg_v01 *req;
  2226. struct wlfw_dynamic_feature_mask_resp_msg_v01 *resp;
  2227. struct qmi_txn txn;
  2228. int ret = 0;
  2229. cnss_pr_dbg("Sending dynamic feature mask 0x%llx, state: 0x%lx\n",
  2230. plat_priv->dynamic_feature,
  2231. plat_priv->driver_state);
  2232. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2233. if (!req)
  2234. return -ENOMEM;
  2235. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2236. if (!resp) {
  2237. kfree(req);
  2238. return -ENOMEM;
  2239. }
  2240. req->mask_valid = 1;
  2241. req->mask = plat_priv->dynamic_feature;
  2242. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2243. wlfw_dynamic_feature_mask_resp_msg_v01_ei, resp);
  2244. if (ret < 0) {
  2245. cnss_pr_err("Fail to initialize txn for dynamic feature mask request: err %d\n",
  2246. ret);
  2247. goto out;
  2248. }
  2249. ret = qmi_send_request
  2250. (&plat_priv->qmi_wlfw, NULL, &txn,
  2251. QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01,
  2252. WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN,
  2253. wlfw_dynamic_feature_mask_req_msg_v01_ei, req);
  2254. if (ret < 0) {
  2255. qmi_txn_cancel(&txn);
  2256. cnss_pr_err("Fail to send dynamic feature mask request: err %d\n",
  2257. ret);
  2258. goto out;
  2259. }
  2260. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2261. if (ret < 0) {
  2262. cnss_pr_err("Fail to wait for response of dynamic feature mask request, err %d\n",
  2263. ret);
  2264. goto out;
  2265. }
  2266. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2267. cnss_pr_err("Dynamic feature mask request failed, result: %d, err: %d\n",
  2268. resp->resp.result, resp->resp.error);
  2269. ret = -resp->resp.result;
  2270. goto out;
  2271. }
  2272. out:
  2273. kfree(req);
  2274. kfree(resp);
  2275. return ret;
  2276. }
  2277. int cnss_wlfw_get_info_send_sync(struct cnss_plat_data *plat_priv, int type,
  2278. void *cmd, int cmd_len)
  2279. {
  2280. struct wlfw_get_info_req_msg_v01 *req;
  2281. struct wlfw_get_info_resp_msg_v01 *resp;
  2282. struct qmi_txn txn;
  2283. int ret = 0;
  2284. cnss_pr_buf("Sending get info message, type: %d, cmd length: %d, state: 0x%lx\n",
  2285. type, cmd_len, plat_priv->driver_state);
  2286. if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
  2287. return -EINVAL;
  2288. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2289. if (!req)
  2290. return -ENOMEM;
  2291. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2292. if (!resp) {
  2293. kfree(req);
  2294. return -ENOMEM;
  2295. }
  2296. req->type = type;
  2297. req->data_len = cmd_len;
  2298. memcpy(req->data, cmd, req->data_len);
  2299. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2300. wlfw_get_info_resp_msg_v01_ei, resp);
  2301. if (ret < 0) {
  2302. cnss_pr_err("Failed to initialize txn for get info request, err: %d\n",
  2303. ret);
  2304. goto out;
  2305. }
  2306. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2307. QMI_WLFW_GET_INFO_REQ_V01,
  2308. WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2309. wlfw_get_info_req_msg_v01_ei, req);
  2310. if (ret < 0) {
  2311. qmi_txn_cancel(&txn);
  2312. cnss_pr_err("Failed to send get info request, err: %d\n",
  2313. ret);
  2314. goto out;
  2315. }
  2316. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2317. if (ret < 0) {
  2318. cnss_pr_err("Failed to wait for response of get info request, err: %d\n",
  2319. ret);
  2320. goto out;
  2321. }
  2322. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2323. cnss_pr_err("Get info request failed, result: %d, err: %d\n",
  2324. resp->resp.result, resp->resp.error);
  2325. ret = -resp->resp.result;
  2326. goto out;
  2327. }
  2328. kfree(req);
  2329. kfree(resp);
  2330. return 0;
  2331. out:
  2332. kfree(req);
  2333. kfree(resp);
  2334. return ret;
  2335. }
  2336. unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv)
  2337. {
  2338. return QMI_WLFW_TIMEOUT_MS;
  2339. }
  2340. static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2341. struct sockaddr_qrtr *sq,
  2342. struct qmi_txn *txn, const void *data)
  2343. {
  2344. struct cnss_plat_data *plat_priv =
  2345. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2346. const struct wlfw_request_mem_ind_msg_v01 *ind_msg = data;
  2347. int i;
  2348. cnss_pr_dbg("Received QMI WLFW request memory indication\n");
  2349. if (!txn) {
  2350. cnss_pr_err("Spurious indication\n");
  2351. return;
  2352. }
  2353. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2354. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2355. return;
  2356. }
  2357. plat_priv->fw_mem_seg_len = ind_msg->mem_seg_len;
  2358. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  2359. cnss_pr_dbg("FW requests for memory, size: 0x%x, type: %u\n",
  2360. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2361. plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type;
  2362. plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size;
  2363. if (!plat_priv->fw_mem[i].va &&
  2364. plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
  2365. plat_priv->fw_mem[i].attrs |=
  2366. DMA_ATTR_FORCE_CONTIGUOUS;
  2367. if (plat_priv->fw_mem[i].type == CNSS_MEM_CAL_V01)
  2368. plat_priv->cal_mem = &plat_priv->fw_mem[i];
  2369. }
  2370. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_REQUEST_MEM,
  2371. 0, NULL);
  2372. }
  2373. static void cnss_wlfw_fw_mem_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2374. struct sockaddr_qrtr *sq,
  2375. struct qmi_txn *txn, const void *data)
  2376. {
  2377. struct cnss_plat_data *plat_priv =
  2378. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2379. cnss_pr_dbg("Received QMI WLFW FW memory ready indication\n");
  2380. if (!txn) {
  2381. cnss_pr_err("Spurious indication\n");
  2382. return;
  2383. }
  2384. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_READY,
  2385. 0, NULL);
  2386. }
  2387. /**
  2388. * cnss_wlfw_fw_ready_ind_cb: FW ready indication handler (Helium arch)
  2389. *
  2390. * This event is not required for HST/ HSP as FW calibration done is
  2391. * provided in QMI_WLFW_CAL_DONE_IND_V01
  2392. */
  2393. static void cnss_wlfw_fw_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2394. struct sockaddr_qrtr *sq,
  2395. struct qmi_txn *txn, const void *data)
  2396. {
  2397. struct cnss_plat_data *plat_priv =
  2398. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2399. struct cnss_cal_info *cal_info;
  2400. if (!txn) {
  2401. cnss_pr_err("Spurious indication\n");
  2402. return;
  2403. }
  2404. if (plat_priv->device_id == QCA6390_DEVICE_ID ||
  2405. plat_priv->device_id == QCA6490_DEVICE_ID) {
  2406. cnss_pr_dbg("Ignore FW Ready Indication for HST/HSP");
  2407. return;
  2408. }
  2409. cnss_pr_dbg("Received QMI WLFW FW ready indication.\n");
  2410. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2411. if (!cal_info)
  2412. return;
  2413. cal_info->cal_status = CNSS_CAL_DONE;
  2414. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2415. 0, cal_info);
  2416. }
  2417. static void cnss_wlfw_fw_init_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2418. struct sockaddr_qrtr *sq,
  2419. struct qmi_txn *txn, const void *data)
  2420. {
  2421. struct cnss_plat_data *plat_priv =
  2422. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2423. cnss_pr_dbg("Received QMI WLFW FW initialization done indication\n");
  2424. if (!txn) {
  2425. cnss_pr_err("Spurious indication\n");
  2426. return;
  2427. }
  2428. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_READY, 0, NULL);
  2429. }
  2430. static void cnss_wlfw_pin_result_ind_cb(struct qmi_handle *qmi_wlfw,
  2431. struct sockaddr_qrtr *sq,
  2432. struct qmi_txn *txn, const void *data)
  2433. {
  2434. struct cnss_plat_data *plat_priv =
  2435. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2436. const struct wlfw_pin_connect_result_ind_msg_v01 *ind_msg = data;
  2437. cnss_pr_dbg("Received QMI WLFW pin connect result indication\n");
  2438. if (!txn) {
  2439. cnss_pr_err("Spurious indication\n");
  2440. return;
  2441. }
  2442. if (ind_msg->pwr_pin_result_valid)
  2443. plat_priv->pin_result.fw_pwr_pin_result =
  2444. ind_msg->pwr_pin_result;
  2445. if (ind_msg->phy_io_pin_result_valid)
  2446. plat_priv->pin_result.fw_phy_io_pin_result =
  2447. ind_msg->phy_io_pin_result;
  2448. if (ind_msg->rf_pin_result_valid)
  2449. plat_priv->pin_result.fw_rf_pin_result = ind_msg->rf_pin_result;
  2450. cnss_pr_dbg("Pin connect Result: pwr_pin: 0x%x phy_io_pin: 0x%x rf_io_pin: 0x%x\n",
  2451. ind_msg->pwr_pin_result, ind_msg->phy_io_pin_result,
  2452. ind_msg->rf_pin_result);
  2453. }
  2454. int cnss_wlfw_cal_report_req_send_sync(struct cnss_plat_data *plat_priv,
  2455. u32 cal_file_download_size)
  2456. {
  2457. struct wlfw_cal_report_req_msg_v01 req = {0};
  2458. struct wlfw_cal_report_resp_msg_v01 resp = {0};
  2459. struct qmi_txn txn;
  2460. int ret = 0;
  2461. cnss_pr_dbg("Sending cal file report request. File size: %d, state: 0x%lx\n",
  2462. cal_file_download_size, plat_priv->driver_state);
  2463. req.cal_file_download_size_valid = 1;
  2464. req.cal_file_download_size = cal_file_download_size;
  2465. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2466. wlfw_cal_report_resp_msg_v01_ei, &resp);
  2467. if (ret < 0) {
  2468. cnss_pr_err("Failed to initialize txn for Cal Report request, err: %d\n",
  2469. ret);
  2470. goto out;
  2471. }
  2472. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2473. QMI_WLFW_CAL_REPORT_REQ_V01,
  2474. WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN,
  2475. wlfw_cal_report_req_msg_v01_ei, &req);
  2476. if (ret < 0) {
  2477. qmi_txn_cancel(&txn);
  2478. cnss_pr_err("Failed to send Cal Report request, err: %d\n",
  2479. ret);
  2480. goto out;
  2481. }
  2482. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2483. if (ret < 0) {
  2484. cnss_pr_err("Failed to wait for response of Cal Report request, err: %d\n",
  2485. ret);
  2486. goto out;
  2487. }
  2488. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  2489. cnss_pr_err("Cal Report request failed, result: %d, err: %d\n",
  2490. resp.resp.result, resp.resp.error);
  2491. ret = -resp.resp.result;
  2492. goto out;
  2493. }
  2494. out:
  2495. return ret;
  2496. }
  2497. static void cnss_wlfw_cal_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2498. struct sockaddr_qrtr *sq,
  2499. struct qmi_txn *txn, const void *data)
  2500. {
  2501. struct cnss_plat_data *plat_priv =
  2502. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2503. const struct wlfw_cal_done_ind_msg_v01 *ind = data;
  2504. struct cnss_cal_info *cal_info;
  2505. cnss_pr_dbg("Received Cal done indication. File size: %d\n",
  2506. ind->cal_file_upload_size);
  2507. cnss_pr_info("Calibration took %d ms\n",
  2508. jiffies_to_msecs(jiffies - plat_priv->cal_time));
  2509. if (!txn) {
  2510. cnss_pr_err("Spurious indication\n");
  2511. return;
  2512. }
  2513. if (ind->cal_file_upload_size_valid)
  2514. plat_priv->cal_file_size = ind->cal_file_upload_size;
  2515. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2516. if (!cal_info)
  2517. return;
  2518. cal_info->cal_status = CNSS_CAL_DONE;
  2519. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2520. 0, cal_info);
  2521. }
  2522. static void cnss_wlfw_qdss_trace_req_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2523. struct sockaddr_qrtr *sq,
  2524. struct qmi_txn *txn,
  2525. const void *data)
  2526. {
  2527. struct cnss_plat_data *plat_priv =
  2528. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2529. const struct wlfw_qdss_trace_req_mem_ind_msg_v01 *ind_msg = data;
  2530. int i;
  2531. cnss_pr_dbg("Received QMI WLFW QDSS trace request mem indication\n");
  2532. if (!txn) {
  2533. cnss_pr_err("Spurious indication\n");
  2534. return;
  2535. }
  2536. if (plat_priv->qdss_mem_seg_len) {
  2537. cnss_pr_err("Ignore double allocation for QDSS trace, current len %u\n",
  2538. plat_priv->qdss_mem_seg_len);
  2539. return;
  2540. }
  2541. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2542. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2543. return;
  2544. }
  2545. plat_priv->qdss_mem_seg_len = ind_msg->mem_seg_len;
  2546. for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) {
  2547. cnss_pr_dbg("QDSS requests for memory, size: 0x%x, type: %u\n",
  2548. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2549. plat_priv->qdss_mem[i].type = ind_msg->mem_seg[i].type;
  2550. plat_priv->qdss_mem[i].size = ind_msg->mem_seg[i].size;
  2551. }
  2552. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
  2553. 0, NULL);
  2554. }
  2555. /**
  2556. * cnss_wlfw_fw_mem_file_save_ind_cb: Save given FW mem to filesystem
  2557. *
  2558. * QDSS_TRACE_SAVE_IND feature is overloaded to provide any host allocated
  2559. * fw memory segment for dumping to file system. Only one type of mem can be
  2560. * saved per indication and is provided in mem seg index 0.
  2561. *
  2562. * Return: None
  2563. */
  2564. static void cnss_wlfw_fw_mem_file_save_ind_cb(struct qmi_handle *qmi_wlfw,
  2565. struct sockaddr_qrtr *sq,
  2566. struct qmi_txn *txn,
  2567. const void *data)
  2568. {
  2569. struct cnss_plat_data *plat_priv =
  2570. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2571. const struct wlfw_qdss_trace_save_ind_msg_v01 *ind_msg = data;
  2572. struct cnss_qmi_event_fw_mem_file_save_data *event_data;
  2573. int i = 0;
  2574. if (!txn || !data) {
  2575. cnss_pr_err("Spurious indication\n");
  2576. return;
  2577. }
  2578. cnss_pr_dbg_buf("QMI fw_mem_file_save: source: %d mem_seg: %d type: %u len: %u\n",
  2579. ind_msg->source, ind_msg->mem_seg_valid,
  2580. ind_msg->mem_seg[0].type, ind_msg->mem_seg_len);
  2581. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2582. if (!event_data)
  2583. return;
  2584. event_data->mem_type = ind_msg->mem_seg[0].type;
  2585. event_data->mem_seg_len = ind_msg->mem_seg_len;
  2586. event_data->total_size = ind_msg->total_size;
  2587. if (ind_msg->mem_seg_valid) {
  2588. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_STR_LEN_V01) {
  2589. cnss_pr_err("Invalid seg len indication\n");
  2590. goto free_event_data;
  2591. }
  2592. for (i = 0; i < ind_msg->mem_seg_len; i++) {
  2593. event_data->mem_seg[i].addr = ind_msg->mem_seg[i].addr;
  2594. event_data->mem_seg[i].size = ind_msg->mem_seg[i].size;
  2595. if (event_data->mem_type != ind_msg->mem_seg[i].type) {
  2596. cnss_pr_err("FW Mem file save ind cannot have multiple mem types\n");
  2597. goto free_event_data;
  2598. }
  2599. cnss_pr_dbg_buf("seg-%d: addr 0x%llx size 0x%x\n",
  2600. i, ind_msg->mem_seg[i].addr,
  2601. ind_msg->mem_seg[i].size);
  2602. }
  2603. }
  2604. if (ind_msg->file_name_valid)
  2605. strlcpy(event_data->file_name, ind_msg->file_name,
  2606. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2607. if (ind_msg->source == 1) {
  2608. if (!ind_msg->file_name_valid)
  2609. strlcpy(event_data->file_name, "qdss_trace_wcss_etb",
  2610. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2611. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
  2612. 0, event_data);
  2613. } else {
  2614. if (event_data->mem_type == QMI_WLFW_MEM_QDSS_V01) {
  2615. if (!ind_msg->file_name_valid)
  2616. strlcpy(event_data->file_name, "qdss_trace_ddr",
  2617. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2618. } else {
  2619. if (!ind_msg->file_name_valid)
  2620. strlcpy(event_data->file_name, "fw_mem_dump",
  2621. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2622. }
  2623. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
  2624. 0, event_data);
  2625. }
  2626. return;
  2627. free_event_data:
  2628. kfree(event_data);
  2629. }
  2630. static void cnss_wlfw_qdss_trace_free_ind_cb(struct qmi_handle *qmi_wlfw,
  2631. struct sockaddr_qrtr *sq,
  2632. struct qmi_txn *txn,
  2633. const void *data)
  2634. {
  2635. struct cnss_plat_data *plat_priv =
  2636. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2637. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
  2638. 0, NULL);
  2639. }
  2640. static void cnss_wlfw_respond_get_info_ind_cb(struct qmi_handle *qmi_wlfw,
  2641. struct sockaddr_qrtr *sq,
  2642. struct qmi_txn *txn,
  2643. const void *data)
  2644. {
  2645. struct cnss_plat_data *plat_priv =
  2646. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2647. const struct wlfw_respond_get_info_ind_msg_v01 *ind_msg = data;
  2648. cnss_pr_buf("Received QMI WLFW respond get info indication\n");
  2649. if (!txn) {
  2650. cnss_pr_err("Spurious indication\n");
  2651. return;
  2652. }
  2653. cnss_pr_buf("Extract message with event length: %d, type: %d, is last: %d, seq no: %d\n",
  2654. ind_msg->data_len, ind_msg->type,
  2655. ind_msg->is_last, ind_msg->seq_no);
  2656. if (plat_priv->get_info_cb_ctx && plat_priv->get_info_cb)
  2657. plat_priv->get_info_cb(plat_priv->get_info_cb_ctx,
  2658. (void *)ind_msg->data,
  2659. ind_msg->data_len);
  2660. }
  2661. static int cnss_ims_wfc_call_twt_cfg_send_sync
  2662. (struct cnss_plat_data *plat_priv,
  2663. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg)
  2664. {
  2665. struct ims_private_service_wfc_call_twt_config_req_msg_v01 *req;
  2666. struct ims_private_service_wfc_call_twt_config_rsp_msg_v01 *resp;
  2667. struct qmi_txn txn;
  2668. int ret = 0;
  2669. if (!test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  2670. cnss_pr_err("Drop FW WFC indication as IMS QMI not connected\n");
  2671. return -EINVAL;
  2672. }
  2673. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2674. if (!req)
  2675. return -ENOMEM;
  2676. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2677. if (!resp) {
  2678. kfree(req);
  2679. return -ENOMEM;
  2680. }
  2681. req->twt_sta_start_valid = ind_msg->twt_sta_start_valid;
  2682. req->twt_sta_start = ind_msg->twt_sta_start;
  2683. req->twt_sta_int_valid = ind_msg->twt_sta_int_valid;
  2684. req->twt_sta_int = ind_msg->twt_sta_int;
  2685. req->twt_sta_upo_valid = ind_msg->twt_sta_upo_valid;
  2686. req->twt_sta_upo = ind_msg->twt_sta_upo;
  2687. req->twt_sta_sp_valid = ind_msg->twt_sta_sp_valid;
  2688. req->twt_sta_sp = ind_msg->twt_sta_sp;
  2689. req->twt_sta_dl_valid = req->twt_sta_dl_valid;
  2690. req->twt_sta_dl = req->twt_sta_dl;
  2691. req->twt_sta_config_changed_valid =
  2692. ind_msg->twt_sta_config_changed_valid;
  2693. req->twt_sta_config_changed = ind_msg->twt_sta_config_changed;
  2694. cnss_pr_dbg("CNSS->IMS: TWT_CFG_REQ: state: 0x%lx\n",
  2695. plat_priv->driver_state);
  2696. ret =
  2697. qmi_txn_init(&plat_priv->ims_qmi, &txn,
  2698. ims_private_service_wfc_call_twt_config_rsp_msg_v01_ei,
  2699. resp);
  2700. if (ret < 0) {
  2701. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Txn Init Err: %d\n",
  2702. ret);
  2703. goto out;
  2704. }
  2705. ret =
  2706. qmi_send_request(&plat_priv->ims_qmi, NULL, &txn,
  2707. QMI_IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_V01,
  2708. IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_MSG_V01_MAX_MSG_LEN,
  2709. ims_private_service_wfc_call_twt_config_req_msg_v01_ei, req);
  2710. if (ret < 0) {
  2711. qmi_txn_cancel(&txn);
  2712. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Send Err: %d\n", ret);
  2713. goto out;
  2714. }
  2715. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2716. if (ret < 0) {
  2717. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: QMI Wait Err: %d\n", ret);
  2718. goto out;
  2719. }
  2720. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2721. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: Result: %d Err: %d\n",
  2722. resp->resp.result, resp->resp.error);
  2723. ret = -resp->resp.result;
  2724. goto out;
  2725. }
  2726. ret = 0;
  2727. out:
  2728. kfree(req);
  2729. kfree(resp);
  2730. return ret;
  2731. }
  2732. int cnss_process_twt_cfg_ind_event(struct cnss_plat_data *plat_priv,
  2733. void *data)
  2734. {
  2735. int ret;
  2736. struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2737. ret = cnss_ims_wfc_call_twt_cfg_send_sync(plat_priv, ind_msg);
  2738. kfree(data);
  2739. return ret;
  2740. }
  2741. static void cnss_wlfw_process_twt_cfg_ind(struct qmi_handle *qmi_wlfw,
  2742. struct sockaddr_qrtr *sq,
  2743. struct qmi_txn *txn,
  2744. const void *data)
  2745. {
  2746. struct cnss_plat_data *plat_priv =
  2747. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2748. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2749. struct wlfw_wfc_call_twt_config_ind_msg_v01 *event_data;
  2750. if (!txn) {
  2751. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Spurious indication\n");
  2752. return;
  2753. }
  2754. if (!ind_msg) {
  2755. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Invalid indication\n");
  2756. return;
  2757. }
  2758. cnss_pr_dbg("FW->CNSS: TWT_CFG_IND: %x %llx, %x %x, %x %x, %x %x, %x %x, %x %x\n",
  2759. ind_msg->twt_sta_start_valid, ind_msg->twt_sta_start,
  2760. ind_msg->twt_sta_int_valid, ind_msg->twt_sta_int,
  2761. ind_msg->twt_sta_upo_valid, ind_msg->twt_sta_upo,
  2762. ind_msg->twt_sta_sp_valid, ind_msg->twt_sta_sp,
  2763. ind_msg->twt_sta_dl_valid, ind_msg->twt_sta_dl,
  2764. ind_msg->twt_sta_config_changed_valid,
  2765. ind_msg->twt_sta_config_changed);
  2766. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  2767. if (!event_data)
  2768. return;
  2769. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND, 0,
  2770. event_data);
  2771. }
  2772. static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = {
  2773. {
  2774. .type = QMI_INDICATION,
  2775. .msg_id = QMI_WLFW_REQUEST_MEM_IND_V01,
  2776. .ei = wlfw_request_mem_ind_msg_v01_ei,
  2777. .decoded_size = sizeof(struct wlfw_request_mem_ind_msg_v01),
  2778. .fn = cnss_wlfw_request_mem_ind_cb
  2779. },
  2780. {
  2781. .type = QMI_INDICATION,
  2782. .msg_id = QMI_WLFW_FW_MEM_READY_IND_V01,
  2783. .ei = wlfw_fw_mem_ready_ind_msg_v01_ei,
  2784. .decoded_size = sizeof(struct wlfw_fw_mem_ready_ind_msg_v01),
  2785. .fn = cnss_wlfw_fw_mem_ready_ind_cb
  2786. },
  2787. {
  2788. .type = QMI_INDICATION,
  2789. .msg_id = QMI_WLFW_FW_READY_IND_V01,
  2790. .ei = wlfw_fw_ready_ind_msg_v01_ei,
  2791. .decoded_size = sizeof(struct wlfw_fw_ready_ind_msg_v01),
  2792. .fn = cnss_wlfw_fw_ready_ind_cb
  2793. },
  2794. {
  2795. .type = QMI_INDICATION,
  2796. .msg_id = QMI_WLFW_FW_INIT_DONE_IND_V01,
  2797. .ei = wlfw_fw_init_done_ind_msg_v01_ei,
  2798. .decoded_size = sizeof(struct wlfw_fw_init_done_ind_msg_v01),
  2799. .fn = cnss_wlfw_fw_init_done_ind_cb
  2800. },
  2801. {
  2802. .type = QMI_INDICATION,
  2803. .msg_id = QMI_WLFW_PIN_CONNECT_RESULT_IND_V01,
  2804. .ei = wlfw_pin_connect_result_ind_msg_v01_ei,
  2805. .decoded_size =
  2806. sizeof(struct wlfw_pin_connect_result_ind_msg_v01),
  2807. .fn = cnss_wlfw_pin_result_ind_cb
  2808. },
  2809. {
  2810. .type = QMI_INDICATION,
  2811. .msg_id = QMI_WLFW_CAL_DONE_IND_V01,
  2812. .ei = wlfw_cal_done_ind_msg_v01_ei,
  2813. .decoded_size = sizeof(struct wlfw_cal_done_ind_msg_v01),
  2814. .fn = cnss_wlfw_cal_done_ind_cb
  2815. },
  2816. {
  2817. .type = QMI_INDICATION,
  2818. .msg_id = QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01,
  2819. .ei = wlfw_qdss_trace_req_mem_ind_msg_v01_ei,
  2820. .decoded_size =
  2821. sizeof(struct wlfw_qdss_trace_req_mem_ind_msg_v01),
  2822. .fn = cnss_wlfw_qdss_trace_req_mem_ind_cb
  2823. },
  2824. {
  2825. .type = QMI_INDICATION,
  2826. .msg_id = QMI_WLFW_QDSS_TRACE_SAVE_IND_V01,
  2827. .ei = wlfw_qdss_trace_save_ind_msg_v01_ei,
  2828. .decoded_size =
  2829. sizeof(struct wlfw_qdss_trace_save_ind_msg_v01),
  2830. .fn = cnss_wlfw_fw_mem_file_save_ind_cb
  2831. },
  2832. {
  2833. .type = QMI_INDICATION,
  2834. .msg_id = QMI_WLFW_QDSS_TRACE_FREE_IND_V01,
  2835. .ei = wlfw_qdss_trace_free_ind_msg_v01_ei,
  2836. .decoded_size =
  2837. sizeof(struct wlfw_qdss_trace_free_ind_msg_v01),
  2838. .fn = cnss_wlfw_qdss_trace_free_ind_cb
  2839. },
  2840. {
  2841. .type = QMI_INDICATION,
  2842. .msg_id = QMI_WLFW_RESPOND_GET_INFO_IND_V01,
  2843. .ei = wlfw_respond_get_info_ind_msg_v01_ei,
  2844. .decoded_size =
  2845. sizeof(struct wlfw_respond_get_info_ind_msg_v01),
  2846. .fn = cnss_wlfw_respond_get_info_ind_cb
  2847. },
  2848. {
  2849. .type = QMI_INDICATION,
  2850. .msg_id = QMI_WLFW_WFC_CALL_TWT_CONFIG_IND_V01,
  2851. .ei = wlfw_wfc_call_twt_config_ind_msg_v01_ei,
  2852. .decoded_size =
  2853. sizeof(struct wlfw_wfc_call_twt_config_ind_msg_v01),
  2854. .fn = cnss_wlfw_process_twt_cfg_ind
  2855. },
  2856. {}
  2857. };
  2858. static int cnss_wlfw_connect_to_server(struct cnss_plat_data *plat_priv,
  2859. void *data)
  2860. {
  2861. struct cnss_qmi_event_server_arrive_data *event_data = data;
  2862. struct qmi_handle *qmi_wlfw = &plat_priv->qmi_wlfw;
  2863. struct sockaddr_qrtr sq = { 0 };
  2864. int ret = 0;
  2865. if (!event_data)
  2866. return -EINVAL;
  2867. sq.sq_family = AF_QIPCRTR;
  2868. sq.sq_node = event_data->node;
  2869. sq.sq_port = event_data->port;
  2870. ret = kernel_connect(qmi_wlfw->sock, (struct sockaddr *)&sq,
  2871. sizeof(sq), 0);
  2872. if (ret < 0) {
  2873. cnss_pr_err("Failed to connect to QMI WLFW remote service port\n");
  2874. goto out;
  2875. }
  2876. set_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2877. cnss_pr_info("QMI WLFW service connected, state: 0x%lx\n",
  2878. plat_priv->driver_state);
  2879. kfree(data);
  2880. return 0;
  2881. out:
  2882. CNSS_QMI_ASSERT();
  2883. kfree(data);
  2884. return ret;
  2885. }
  2886. int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data)
  2887. {
  2888. int ret = 0;
  2889. if (!plat_priv)
  2890. return -ENODEV;
  2891. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  2892. cnss_pr_err("Unexpected WLFW server arrive\n");
  2893. CNSS_ASSERT(0);
  2894. return -EINVAL;
  2895. }
  2896. cnss_ignore_qmi_failure(false);
  2897. ret = cnss_wlfw_connect_to_server(plat_priv, data);
  2898. if (ret < 0)
  2899. goto out;
  2900. ret = cnss_wlfw_ind_register_send_sync(plat_priv);
  2901. if (ret < 0) {
  2902. if (ret == -EALREADY)
  2903. ret = 0;
  2904. goto out;
  2905. }
  2906. ret = cnss_wlfw_host_cap_send_sync(plat_priv);
  2907. if (ret < 0)
  2908. goto out;
  2909. return 0;
  2910. out:
  2911. return ret;
  2912. }
  2913. int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv)
  2914. {
  2915. int ret;
  2916. if (!plat_priv)
  2917. return -ENODEV;
  2918. clear_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2919. cnss_pr_info("QMI WLFW service disconnected, state: 0x%lx\n",
  2920. plat_priv->driver_state);
  2921. cnss_qmi_deinit(plat_priv);
  2922. clear_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2923. ret = cnss_qmi_init(plat_priv);
  2924. if (ret < 0) {
  2925. cnss_pr_err("QMI WLFW service registraton failed, ret\n", ret);
  2926. CNSS_ASSERT(0);
  2927. }
  2928. return 0;
  2929. }
  2930. static int wlfw_new_server(struct qmi_handle *qmi_wlfw,
  2931. struct qmi_service *service)
  2932. {
  2933. struct cnss_plat_data *plat_priv =
  2934. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2935. struct cnss_qmi_event_server_arrive_data *event_data;
  2936. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2937. cnss_pr_info("WLFW server delete in progress, Ignore server arrive, state: 0x%lx\n",
  2938. plat_priv->driver_state);
  2939. return 0;
  2940. }
  2941. cnss_pr_dbg("WLFW server arriving: node %u port %u\n",
  2942. service->node, service->port);
  2943. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2944. if (!event_data)
  2945. return -ENOMEM;
  2946. event_data->node = service->node;
  2947. event_data->port = service->port;
  2948. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_ARRIVE,
  2949. 0, event_data);
  2950. return 0;
  2951. }
  2952. static void wlfw_del_server(struct qmi_handle *qmi_wlfw,
  2953. struct qmi_service *service)
  2954. {
  2955. struct cnss_plat_data *plat_priv =
  2956. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2957. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2958. cnss_pr_info("WLFW server delete in progress, Ignore server delete, state: 0x%lx\n",
  2959. plat_priv->driver_state);
  2960. return;
  2961. }
  2962. cnss_pr_dbg("WLFW server exiting\n");
  2963. if (plat_priv) {
  2964. cnss_ignore_qmi_failure(true);
  2965. set_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2966. }
  2967. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_EXIT,
  2968. 0, NULL);
  2969. }
  2970. static struct qmi_ops qmi_wlfw_ops = {
  2971. .new_server = wlfw_new_server,
  2972. .del_server = wlfw_del_server,
  2973. };
  2974. static int cnss_qmi_add_lookup(struct cnss_plat_data *plat_priv)
  2975. {
  2976. unsigned int id = WLFW_SERVICE_INS_ID_V01;
  2977. /* In order to support dual wlan card attach case,
  2978. * need separate qmi service instance id for each dev
  2979. */
  2980. if (cnss_is_dual_wlan_enabled() && plat_priv->qrtr_node_id != 0 &&
  2981. plat_priv->wlfw_service_instance_id != 0)
  2982. id = plat_priv->wlfw_service_instance_id;
  2983. return qmi_add_lookup(&plat_priv->qmi_wlfw, WLFW_SERVICE_ID_V01,
  2984. WLFW_SERVICE_VERS_V01, id);
  2985. }
  2986. int cnss_qmi_init(struct cnss_plat_data *plat_priv)
  2987. {
  2988. int ret = 0;
  2989. cnss_get_qrtr_info(plat_priv);
  2990. ret = qmi_handle_init(&plat_priv->qmi_wlfw,
  2991. QMI_WLFW_MAX_RECV_BUF_SIZE,
  2992. &qmi_wlfw_ops, qmi_wlfw_msg_handlers);
  2993. if (ret < 0) {
  2994. cnss_pr_err("Failed to initialize WLFW QMI handle, err: %d\n",
  2995. ret);
  2996. goto out;
  2997. }
  2998. ret = cnss_qmi_add_lookup(plat_priv);
  2999. if (ret < 0)
  3000. cnss_pr_err("Failed to add WLFW QMI lookup, err: %d\n", ret);
  3001. out:
  3002. return ret;
  3003. }
  3004. void cnss_qmi_deinit(struct cnss_plat_data *plat_priv)
  3005. {
  3006. qmi_handle_release(&plat_priv->qmi_wlfw);
  3007. }
  3008. int cnss_qmi_get_dms_mac(struct cnss_plat_data *plat_priv)
  3009. {
  3010. struct dms_get_mac_address_req_msg_v01 req;
  3011. struct dms_get_mac_address_resp_msg_v01 resp;
  3012. struct qmi_txn txn;
  3013. int ret = 0;
  3014. if (!test_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state)) {
  3015. cnss_pr_err("DMS QMI connection not established\n");
  3016. return -EINVAL;
  3017. }
  3018. cnss_pr_dbg("Requesting DMS MAC address");
  3019. memset(&resp, 0, sizeof(resp));
  3020. ret = qmi_txn_init(&plat_priv->qmi_dms, &txn,
  3021. dms_get_mac_address_resp_msg_v01_ei, &resp);
  3022. if (ret < 0) {
  3023. cnss_pr_err("Failed to initialize txn for dms, err: %d\n",
  3024. ret);
  3025. goto out;
  3026. }
  3027. req.device = DMS_DEVICE_MAC_WLAN_V01;
  3028. ret = qmi_send_request(&plat_priv->qmi_dms, NULL, &txn,
  3029. QMI_DMS_GET_MAC_ADDRESS_REQ_V01,
  3030. DMS_GET_MAC_ADDRESS_REQ_MSG_V01_MAX_MSG_LEN,
  3031. dms_get_mac_address_req_msg_v01_ei, &req);
  3032. if (ret < 0) {
  3033. qmi_txn_cancel(&txn);
  3034. cnss_pr_err("Failed to send QMI_DMS_GET_MAC_ADDRESS_REQ_V01, err: %d\n",
  3035. ret);
  3036. goto out;
  3037. }
  3038. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  3039. if (ret < 0) {
  3040. cnss_pr_err("Failed to wait for QMI_DMS_GET_MAC_ADDRESS_RESP_V01, err: %d\n",
  3041. ret);
  3042. goto out;
  3043. }
  3044. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  3045. cnss_pr_err("QMI_DMS_GET_MAC_ADDRESS_REQ_V01 failed, result: %d, err: %d\n",
  3046. resp.resp.result, resp.resp.error);
  3047. ret = -resp.resp.result;
  3048. goto out;
  3049. }
  3050. if (!resp.mac_address_valid ||
  3051. resp.mac_address_len != QMI_WLFW_MAC_ADDR_SIZE_V01) {
  3052. cnss_pr_err("Invalid MAC address received from DMS\n");
  3053. plat_priv->dms.mac_valid = false;
  3054. goto out;
  3055. }
  3056. plat_priv->dms.mac_valid = true;
  3057. memcpy(plat_priv->dms.mac, resp.mac_address, QMI_WLFW_MAC_ADDR_SIZE_V01);
  3058. cnss_pr_info("Received DMS MAC: [%pM]\n", plat_priv->dms.mac);
  3059. out:
  3060. return ret;
  3061. }
  3062. static int cnss_dms_connect_to_server(struct cnss_plat_data *plat_priv,
  3063. unsigned int node, unsigned int port)
  3064. {
  3065. struct qmi_handle *qmi_dms = &plat_priv->qmi_dms;
  3066. struct sockaddr_qrtr sq = {0};
  3067. int ret = 0;
  3068. sq.sq_family = AF_QIPCRTR;
  3069. sq.sq_node = node;
  3070. sq.sq_port = port;
  3071. ret = kernel_connect(qmi_dms->sock, (struct sockaddr *)&sq,
  3072. sizeof(sq), 0);
  3073. if (ret < 0) {
  3074. cnss_pr_err("Failed to connect to QMI DMS remote service Node: %d Port: %d\n",
  3075. node, port);
  3076. goto out;
  3077. }
  3078. set_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3079. cnss_pr_info("QMI DMS service connected, state: 0x%lx\n",
  3080. plat_priv->driver_state);
  3081. out:
  3082. return ret;
  3083. }
  3084. static int dms_new_server(struct qmi_handle *qmi_dms,
  3085. struct qmi_service *service)
  3086. {
  3087. struct cnss_plat_data *plat_priv =
  3088. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3089. if (!service)
  3090. return -EINVAL;
  3091. return cnss_dms_connect_to_server(plat_priv, service->node,
  3092. service->port);
  3093. }
  3094. static void cnss_dms_server_exit_work(struct work_struct *work)
  3095. {
  3096. int ret;
  3097. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3098. cnss_dms_deinit(plat_priv);
  3099. cnss_pr_info("QMI DMS Server Exit");
  3100. clear_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3101. ret = cnss_dms_init(plat_priv);
  3102. if (ret < 0)
  3103. cnss_pr_err("QMI DMS service registraton failed, ret\n", ret);
  3104. }
  3105. static DECLARE_WORK(cnss_dms_del_work, cnss_dms_server_exit_work);
  3106. static void dms_del_server(struct qmi_handle *qmi_dms,
  3107. struct qmi_service *service)
  3108. {
  3109. struct cnss_plat_data *plat_priv =
  3110. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3111. if (!plat_priv)
  3112. return;
  3113. if (test_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state)) {
  3114. cnss_pr_info("DMS server delete or cnss remove in progress, Ignore server delete: 0x%lx\n",
  3115. plat_priv->driver_state);
  3116. return;
  3117. }
  3118. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3119. clear_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3120. cnss_pr_info("QMI DMS service disconnected, state: 0x%lx\n",
  3121. plat_priv->driver_state);
  3122. schedule_work(&cnss_dms_del_work);
  3123. }
  3124. void cnss_cancel_dms_work(void)
  3125. {
  3126. cancel_work_sync(&cnss_dms_del_work);
  3127. }
  3128. static struct qmi_ops qmi_dms_ops = {
  3129. .new_server = dms_new_server,
  3130. .del_server = dms_del_server,
  3131. };
  3132. int cnss_dms_init(struct cnss_plat_data *plat_priv)
  3133. {
  3134. int ret = 0;
  3135. ret = qmi_handle_init(&plat_priv->qmi_dms, DMS_QMI_MAX_MSG_LEN,
  3136. &qmi_dms_ops, NULL);
  3137. if (ret < 0) {
  3138. cnss_pr_err("Failed to initialize DMS handle, err: %d\n", ret);
  3139. goto out;
  3140. }
  3141. ret = qmi_add_lookup(&plat_priv->qmi_dms, DMS_SERVICE_ID_V01,
  3142. DMS_SERVICE_VERS_V01, 0);
  3143. if (ret < 0)
  3144. cnss_pr_err("Failed to add DMS lookup, err: %d\n", ret);
  3145. out:
  3146. return ret;
  3147. }
  3148. void cnss_dms_deinit(struct cnss_plat_data *plat_priv)
  3149. {
  3150. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3151. qmi_handle_release(&plat_priv->qmi_dms);
  3152. }
  3153. int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv)
  3154. {
  3155. int ret;
  3156. struct coex_antenna_switch_to_wlan_req_msg_v01 *req;
  3157. struct coex_antenna_switch_to_wlan_resp_msg_v01 *resp;
  3158. struct qmi_txn txn;
  3159. if (!plat_priv)
  3160. return -ENODEV;
  3161. cnss_pr_dbg("Sending coex antenna switch_to_wlan\n");
  3162. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3163. if (!req)
  3164. return -ENOMEM;
  3165. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3166. if (!resp) {
  3167. kfree(req);
  3168. return -ENOMEM;
  3169. }
  3170. req->antenna = plat_priv->antenna;
  3171. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3172. coex_antenna_switch_to_wlan_resp_msg_v01_ei, resp);
  3173. if (ret < 0) {
  3174. cnss_pr_err("Fail to init txn for coex antenna switch_to_wlan resp %d\n",
  3175. ret);
  3176. goto out;
  3177. }
  3178. ret = qmi_send_request
  3179. (&plat_priv->coex_qmi, NULL, &txn,
  3180. QMI_COEX_SWITCH_ANTENNA_TO_WLAN_REQ_V01,
  3181. COEX_ANTENNA_SWITCH_TO_WLAN_REQ_MSG_V01_MAX_MSG_LEN,
  3182. coex_antenna_switch_to_wlan_req_msg_v01_ei, req);
  3183. if (ret < 0) {
  3184. qmi_txn_cancel(&txn);
  3185. cnss_pr_err("Fail to send coex antenna switch_to_wlan req %d\n",
  3186. ret);
  3187. goto out;
  3188. }
  3189. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3190. if (ret < 0) {
  3191. cnss_pr_err("Coex antenna switch_to_wlan resp wait failed with ret %d\n",
  3192. ret);
  3193. goto out;
  3194. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3195. cnss_pr_err("Coex antenna switch_to_wlan request rejected, result:%d error:%d\n",
  3196. resp->resp.result, resp->resp.error);
  3197. ret = -resp->resp.result;
  3198. goto out;
  3199. }
  3200. if (resp->grant_valid)
  3201. plat_priv->grant = resp->grant;
  3202. cnss_pr_dbg("Coex antenna grant: 0x%llx\n", resp->grant);
  3203. kfree(resp);
  3204. kfree(req);
  3205. return 0;
  3206. out:
  3207. kfree(resp);
  3208. kfree(req);
  3209. return ret;
  3210. }
  3211. int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv)
  3212. {
  3213. int ret;
  3214. struct coex_antenna_switch_to_mdm_req_msg_v01 *req;
  3215. struct coex_antenna_switch_to_mdm_resp_msg_v01 *resp;
  3216. struct qmi_txn txn;
  3217. if (!plat_priv)
  3218. return -ENODEV;
  3219. cnss_pr_dbg("Sending coex antenna switch_to_mdm\n");
  3220. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3221. if (!req)
  3222. return -ENOMEM;
  3223. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3224. if (!resp) {
  3225. kfree(req);
  3226. return -ENOMEM;
  3227. }
  3228. req->antenna = plat_priv->antenna;
  3229. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3230. coex_antenna_switch_to_mdm_resp_msg_v01_ei, resp);
  3231. if (ret < 0) {
  3232. cnss_pr_err("Fail to init txn for coex antenna switch_to_mdm resp %d\n",
  3233. ret);
  3234. goto out;
  3235. }
  3236. ret = qmi_send_request
  3237. (&plat_priv->coex_qmi, NULL, &txn,
  3238. QMI_COEX_SWITCH_ANTENNA_TO_MDM_REQ_V01,
  3239. COEX_ANTENNA_SWITCH_TO_MDM_REQ_MSG_V01_MAX_MSG_LEN,
  3240. coex_antenna_switch_to_mdm_req_msg_v01_ei, req);
  3241. if (ret < 0) {
  3242. qmi_txn_cancel(&txn);
  3243. cnss_pr_err("Fail to send coex antenna switch_to_mdm req %d\n",
  3244. ret);
  3245. goto out;
  3246. }
  3247. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3248. if (ret < 0) {
  3249. cnss_pr_err("Coex antenna switch_to_mdm resp wait failed with ret %d\n",
  3250. ret);
  3251. goto out;
  3252. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3253. cnss_pr_err("Coex antenna switch_to_mdm request rejected, result:%d error:%d\n",
  3254. resp->resp.result, resp->resp.error);
  3255. ret = -resp->resp.result;
  3256. goto out;
  3257. }
  3258. kfree(resp);
  3259. kfree(req);
  3260. return 0;
  3261. out:
  3262. kfree(resp);
  3263. kfree(req);
  3264. return ret;
  3265. }
  3266. int cnss_send_subsys_restart_level_msg(struct cnss_plat_data *plat_priv)
  3267. {
  3268. int ret;
  3269. struct wlfw_subsys_restart_level_req_msg_v01 req;
  3270. struct wlfw_subsys_restart_level_resp_msg_v01 resp;
  3271. u8 pcss_enabled;
  3272. if (!plat_priv)
  3273. return -ENODEV;
  3274. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  3275. cnss_pr_dbg("Can't send pcss cmd before fw ready\n");
  3276. return 0;
  3277. }
  3278. pcss_enabled = plat_priv->recovery_pcss_enabled;
  3279. cnss_pr_dbg("Sending pcss recovery status: %d\n", pcss_enabled);
  3280. req.restart_level_type_valid = 1;
  3281. req.restart_level_type = pcss_enabled;
  3282. ret = qmi_send_wait(&plat_priv->qmi_wlfw, &req, &resp,
  3283. wlfw_subsys_restart_level_req_msg_v01_ei,
  3284. wlfw_subsys_restart_level_resp_msg_v01_ei,
  3285. QMI_WLFW_SUBSYS_RESTART_LEVEL_REQ_V01,
  3286. WLFW_SUBSYS_RESTART_LEVEL_REQ_MSG_V01_MAX_MSG_LEN,
  3287. QMI_WLFW_TIMEOUT_JF);
  3288. if (ret < 0)
  3289. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  3290. return ret;
  3291. }
  3292. static int coex_new_server(struct qmi_handle *qmi,
  3293. struct qmi_service *service)
  3294. {
  3295. struct cnss_plat_data *plat_priv =
  3296. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3297. struct sockaddr_qrtr sq = { 0 };
  3298. int ret = 0;
  3299. cnss_pr_dbg("COEX server arrive: node %u port %u\n",
  3300. service->node, service->port);
  3301. sq.sq_family = AF_QIPCRTR;
  3302. sq.sq_node = service->node;
  3303. sq.sq_port = service->port;
  3304. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3305. if (ret < 0) {
  3306. cnss_pr_err("Fail to connect to remote service port\n");
  3307. return ret;
  3308. }
  3309. set_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3310. cnss_pr_dbg("COEX Server Connected: 0x%lx\n",
  3311. plat_priv->driver_state);
  3312. return 0;
  3313. }
  3314. static void coex_del_server(struct qmi_handle *qmi,
  3315. struct qmi_service *service)
  3316. {
  3317. struct cnss_plat_data *plat_priv =
  3318. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3319. cnss_pr_dbg("COEX server exit\n");
  3320. clear_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3321. }
  3322. static struct qmi_ops coex_qmi_ops = {
  3323. .new_server = coex_new_server,
  3324. .del_server = coex_del_server,
  3325. };
  3326. int cnss_register_coex_service(struct cnss_plat_data *plat_priv)
  3327. { int ret;
  3328. ret = qmi_handle_init(&plat_priv->coex_qmi,
  3329. COEX_SERVICE_MAX_MSG_LEN,
  3330. &coex_qmi_ops, NULL);
  3331. if (ret < 0)
  3332. return ret;
  3333. ret = qmi_add_lookup(&plat_priv->coex_qmi, COEX_SERVICE_ID_V01,
  3334. COEX_SERVICE_VERS_V01, 0);
  3335. return ret;
  3336. }
  3337. void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv)
  3338. {
  3339. qmi_handle_release(&plat_priv->coex_qmi);
  3340. }
  3341. /* IMS Service */
  3342. int ims_subscribe_for_indication_send_async(struct cnss_plat_data *plat_priv)
  3343. {
  3344. int ret;
  3345. struct ims_private_service_subscribe_for_indications_req_msg_v01 *req;
  3346. struct qmi_txn *txn;
  3347. if (!plat_priv)
  3348. return -ENODEV;
  3349. cnss_pr_dbg("Sending ASYNC ims subscribe for indication\n");
  3350. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3351. if (!req)
  3352. return -ENOMEM;
  3353. req->wfc_call_status_valid = 1;
  3354. req->wfc_call_status = 1;
  3355. txn = &plat_priv->txn;
  3356. ret = qmi_txn_init(&plat_priv->ims_qmi, txn, NULL, NULL);
  3357. if (ret < 0) {
  3358. cnss_pr_err("Fail to init txn for ims subscribe for indication resp %d\n",
  3359. ret);
  3360. goto out;
  3361. }
  3362. ret = qmi_send_request
  3363. (&plat_priv->ims_qmi, NULL, txn,
  3364. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3365. IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_MSG_V01_MAX_MSG_LEN,
  3366. ims_private_service_subscribe_for_indications_req_msg_v01_ei, req);
  3367. if (ret < 0) {
  3368. qmi_txn_cancel(txn);
  3369. cnss_pr_err("Fail to send ims subscribe for indication req %d\n",
  3370. ret);
  3371. goto out;
  3372. }
  3373. kfree(req);
  3374. return 0;
  3375. out:
  3376. kfree(req);
  3377. return ret;
  3378. }
  3379. static void ims_subscribe_for_indication_resp_cb(struct qmi_handle *qmi,
  3380. struct sockaddr_qrtr *sq,
  3381. struct qmi_txn *txn,
  3382. const void *data)
  3383. {
  3384. const
  3385. struct ims_private_service_subscribe_for_indications_rsp_msg_v01 *resp =
  3386. data;
  3387. cnss_pr_dbg("Received IMS subscribe indication response\n");
  3388. if (!txn) {
  3389. cnss_pr_err("spurious response\n");
  3390. return;
  3391. }
  3392. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3393. cnss_pr_err("IMS subscribe for indication request rejected, result:%d error:%d\n",
  3394. resp->resp.result, resp->resp.error);
  3395. txn->result = -resp->resp.result;
  3396. }
  3397. }
  3398. int cnss_process_wfc_call_ind_event(struct cnss_plat_data *plat_priv,
  3399. void *data)
  3400. {
  3401. int ret;
  3402. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3403. ret = cnss_wlfw_wfc_call_status_send_sync(plat_priv, ind_msg);
  3404. kfree(data);
  3405. return ret;
  3406. }
  3407. static void
  3408. cnss_ims_process_wfc_call_ind_cb(struct qmi_handle *ims_qmi,
  3409. struct sockaddr_qrtr *sq,
  3410. struct qmi_txn *txn, const void *data)
  3411. {
  3412. struct cnss_plat_data *plat_priv =
  3413. container_of(ims_qmi, struct cnss_plat_data, ims_qmi);
  3414. const
  3415. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3416. struct ims_private_service_wfc_call_status_ind_msg_v01 *event_data;
  3417. if (!txn) {
  3418. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Spurious indication\n");
  3419. return;
  3420. }
  3421. if (!ind_msg) {
  3422. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Invalid indication\n");
  3423. return;
  3424. }
  3425. cnss_pr_dbg("IMS->CNSS: WFC_CALL_IND: %x, %x %x, %x %x, %x %llx, %x %x, %x %x\n",
  3426. ind_msg->wfc_call_active, ind_msg->all_wfc_calls_held_valid,
  3427. ind_msg->all_wfc_calls_held,
  3428. ind_msg->is_wfc_emergency_valid, ind_msg->is_wfc_emergency,
  3429. ind_msg->twt_ims_start_valid, ind_msg->twt_ims_start,
  3430. ind_msg->twt_ims_int_valid, ind_msg->twt_ims_int,
  3431. ind_msg->media_quality_valid, ind_msg->media_quality);
  3432. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  3433. if (!event_data)
  3434. return;
  3435. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
  3436. 0, event_data);
  3437. }
  3438. static struct qmi_msg_handler qmi_ims_msg_handlers[] = {
  3439. {
  3440. .type = QMI_RESPONSE,
  3441. .msg_id =
  3442. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3443. .ei =
  3444. ims_private_service_subscribe_for_indications_rsp_msg_v01_ei,
  3445. .decoded_size = sizeof(struct
  3446. ims_private_service_subscribe_for_indications_rsp_msg_v01),
  3447. .fn = ims_subscribe_for_indication_resp_cb
  3448. },
  3449. {
  3450. .type = QMI_INDICATION,
  3451. .msg_id = QMI_IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_V01,
  3452. .ei = ims_private_service_wfc_call_status_ind_msg_v01_ei,
  3453. .decoded_size =
  3454. sizeof(struct ims_private_service_wfc_call_status_ind_msg_v01),
  3455. .fn = cnss_ims_process_wfc_call_ind_cb
  3456. },
  3457. {}
  3458. };
  3459. static int ims_new_server(struct qmi_handle *qmi,
  3460. struct qmi_service *service)
  3461. {
  3462. struct cnss_plat_data *plat_priv =
  3463. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3464. struct sockaddr_qrtr sq = { 0 };
  3465. int ret = 0;
  3466. cnss_pr_dbg("IMS server arrive: node %u port %u\n",
  3467. service->node, service->port);
  3468. sq.sq_family = AF_QIPCRTR;
  3469. sq.sq_node = service->node;
  3470. sq.sq_port = service->port;
  3471. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3472. if (ret < 0) {
  3473. cnss_pr_err("Fail to connect to remote service port\n");
  3474. return ret;
  3475. }
  3476. set_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3477. cnss_pr_dbg("IMS Server Connected: 0x%lx\n",
  3478. plat_priv->driver_state);
  3479. ret = ims_subscribe_for_indication_send_async(plat_priv);
  3480. return ret;
  3481. }
  3482. static void ims_del_server(struct qmi_handle *qmi,
  3483. struct qmi_service *service)
  3484. {
  3485. struct cnss_plat_data *plat_priv =
  3486. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3487. cnss_pr_dbg("IMS server exit\n");
  3488. clear_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3489. }
  3490. static struct qmi_ops ims_qmi_ops = {
  3491. .new_server = ims_new_server,
  3492. .del_server = ims_del_server,
  3493. };
  3494. int cnss_register_ims_service(struct cnss_plat_data *plat_priv)
  3495. { int ret;
  3496. ret = qmi_handle_init(&plat_priv->ims_qmi,
  3497. IMSPRIVATE_SERVICE_MAX_MSG_LEN,
  3498. &ims_qmi_ops, qmi_ims_msg_handlers);
  3499. if (ret < 0)
  3500. return ret;
  3501. ret = qmi_add_lookup(&plat_priv->ims_qmi, IMSPRIVATE_SERVICE_ID_V01,
  3502. IMSPRIVATE_SERVICE_VERS_V01, 0);
  3503. return ret;
  3504. }
  3505. void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv)
  3506. {
  3507. qmi_handle_release(&plat_priv->ims_qmi);
  3508. }