wcd938x.c 124 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VARIANT_ENTRY_SIZE 32
  27. #define WCD938X_VERSION_1_0 1
  28. #define WCD938X_VERSION_ENTRY_SIZE 32
  29. #define EAR_RX_PATH_AUX 1
  30. #define ADC_MODE_VAL_HIFI 0x01
  31. #define ADC_MODE_VAL_LO_HIF 0x02
  32. #define ADC_MODE_VAL_NORMAL 0x03
  33. #define ADC_MODE_VAL_LP 0x05
  34. #define ADC_MODE_VAL_ULP1 0x09
  35. #define ADC_MODE_VAL_ULP2 0x0B
  36. #define NUM_ATTEMPTS 5
  37. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  38. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  39. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  40. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  41. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  42. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  43. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  44. SNDRV_PCM_RATE_384000)
  45. /* Fractional Rates */
  46. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  47. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  48. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  49. SNDRV_PCM_FMTBIT_S24_LE |\
  50. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  51. enum {
  52. CODEC_TX = 0,
  53. CODEC_RX,
  54. };
  55. enum {
  56. WCD_ADC1 = 0,
  57. WCD_ADC2,
  58. WCD_ADC3,
  59. WCD_ADC4,
  60. ALLOW_BUCK_DISABLE,
  61. HPH_COMP_DELAY,
  62. HPH_PA_DELAY,
  63. AMIC2_BCS_ENABLE,
  64. WCD_SUPPLIES_LPM_MODE,
  65. WCD_ADC1_MODE,
  66. WCD_ADC2_MODE,
  67. WCD_ADC3_MODE,
  68. WCD_ADC4_MODE,
  69. };
  70. enum {
  71. ADC_MODE_INVALID = 0,
  72. ADC_MODE_HIFI,
  73. ADC_MODE_LO_HIF,
  74. ADC_MODE_NORMAL,
  75. ADC_MODE_LP,
  76. ADC_MODE_ULP1,
  77. ADC_MODE_ULP2,
  78. };
  79. static u8 tx_mode_bit[] = {
  80. [ADC_MODE_INVALID] = 0x00,
  81. [ADC_MODE_HIFI] = 0x01,
  82. [ADC_MODE_LO_HIF] = 0x02,
  83. [ADC_MODE_NORMAL] = 0x04,
  84. [ADC_MODE_LP] = 0x08,
  85. [ADC_MODE_ULP1] = 0x10,
  86. [ADC_MODE_ULP2] = 0x20,
  87. };
  88. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  89. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  90. static int wcd938x_handle_post_irq(void *data);
  91. static int wcd938x_reset(struct device *dev);
  92. static int wcd938x_reset_low(struct device *dev);
  93. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  94. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  95. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  96. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  109. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  110. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  111. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  112. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  113. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  114. };
  115. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  116. .name = "wcd938x",
  117. .irqs = wcd938x_irqs,
  118. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  119. .num_regs = 3,
  120. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  121. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  122. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  123. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  124. .use_ack = 1,
  125. .runtime_pm = false,
  126. .handle_post_irq = wcd938x_handle_post_irq,
  127. .irq_drv_data = NULL,
  128. };
  129. static int wcd938x_handle_post_irq(void *data)
  130. {
  131. struct wcd938x_priv *wcd938x = data;
  132. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  133. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  134. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  135. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  136. wcd938x->tx_swr_dev->slave_irq_pending =
  137. ((sts1 || sts2 || sts3) ? true : false);
  138. return IRQ_HANDLED;
  139. }
  140. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  141. {
  142. int ret = 0;
  143. int bank = 0;
  144. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  145. if (ret)
  146. return -EINVAL;
  147. return ((bank & 0x40) ? 1: 0);
  148. }
  149. static int wcd938x_get_clk_rate(int mode)
  150. {
  151. int rate;
  152. switch (mode) {
  153. case ADC_MODE_ULP2:
  154. rate = SWR_CLK_RATE_0P6MHZ;
  155. break;
  156. case ADC_MODE_ULP1:
  157. rate = SWR_CLK_RATE_1P2MHZ;
  158. break;
  159. case ADC_MODE_LP:
  160. rate = SWR_CLK_RATE_4P8MHZ;
  161. break;
  162. case ADC_MODE_NORMAL:
  163. case ADC_MODE_LO_HIF:
  164. case ADC_MODE_HIFI:
  165. case ADC_MODE_INVALID:
  166. default:
  167. rate = SWR_CLK_RATE_9P6MHZ;
  168. break;
  169. }
  170. return rate;
  171. }
  172. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  173. int rate, int bank)
  174. {
  175. u8 mask = (bank ? 0xF0 : 0x0F);
  176. u8 val = 0;
  177. switch (rate) {
  178. case SWR_CLK_RATE_0P6MHZ:
  179. val = (bank ? 0x60 : 0x06);
  180. break;
  181. case SWR_CLK_RATE_1P2MHZ:
  182. val = (bank ? 0x50 : 0x05);
  183. break;
  184. case SWR_CLK_RATE_2P4MHZ:
  185. val = (bank ? 0x30 : 0x03);
  186. break;
  187. case SWR_CLK_RATE_4P8MHZ:
  188. val = (bank ? 0x10 : 0x01);
  189. break;
  190. case SWR_CLK_RATE_9P6MHZ:
  191. default:
  192. val = 0x00;
  193. break;
  194. }
  195. snd_soc_component_update_bits(component,
  196. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  197. mask, val);
  198. return 0;
  199. }
  200. static int wcd938x_init_reg(struct snd_soc_component *component)
  201. {
  202. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  203. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  204. /* 1 msec delay as per HW requirement */
  205. usleep_range(1000, 1010);
  206. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  207. /* 1 msec delay as per HW requirement */
  208. usleep_range(1000, 1010);
  209. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  210. 0x10, 0x00);
  211. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  212. 0xF0, 0x80);
  213. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  214. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  215. /* 10 msec delay as per HW requirement */
  216. usleep_range(10000, 10010);
  217. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  218. snd_soc_component_update_bits(component,
  219. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  220. 0xF0, 0x00);
  221. snd_soc_component_update_bits(component,
  222. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  223. 0x1F, 0x15);
  224. snd_soc_component_update_bits(component,
  225. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  226. 0x1F, 0x15);
  227. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  228. 0xC0, 0x80);
  229. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  230. 0x02, 0x02);
  231. snd_soc_component_update_bits(component,
  232. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  233. 0xFF, 0x14);
  234. snd_soc_component_update_bits(component,
  235. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  236. 0x1F, 0x08);
  237. snd_soc_component_update_bits(component,
  238. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  239. snd_soc_component_update_bits(component,
  240. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  241. snd_soc_component_update_bits(component,
  242. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  243. snd_soc_component_update_bits(component,
  244. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  245. snd_soc_component_update_bits(component,
  246. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  247. snd_soc_component_update_bits(component,
  248. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  249. snd_soc_component_update_bits(component,
  250. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  251. snd_soc_component_update_bits(component,
  252. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  253. snd_soc_component_update_bits(component,
  254. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  255. snd_soc_component_update_bits(component,
  256. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  257. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  258. ((snd_soc_component_read32(component,
  259. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  260. snd_soc_component_update_bits(component,
  261. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  262. return 0;
  263. }
  264. static int wcd938x_set_port_params(struct snd_soc_component *component,
  265. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  266. u8 *ch_mask, u32 *ch_rate,
  267. u8 *port_type, u8 path)
  268. {
  269. int i, j;
  270. u8 num_ports = 0;
  271. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  272. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  273. switch (path) {
  274. case CODEC_RX:
  275. map = &wcd938x->rx_port_mapping;
  276. num_ports = wcd938x->num_rx_ports;
  277. break;
  278. case CODEC_TX:
  279. map = &wcd938x->tx_port_mapping;
  280. num_ports = wcd938x->num_tx_ports;
  281. break;
  282. default:
  283. dev_err(component->dev, "%s Invalid path selected %u\n",
  284. __func__, path);
  285. return -EINVAL;
  286. }
  287. for (i = 0; i <= num_ports; i++) {
  288. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  289. if ((*map)[i][j].slave_port_type == slv_prt_type)
  290. goto found;
  291. }
  292. }
  293. found:
  294. if (i > num_ports || j == MAX_CH_PER_PORT) {
  295. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  296. __func__, slv_prt_type);
  297. return -EINVAL;
  298. }
  299. *port_id = i;
  300. *num_ch = (*map)[i][j].num_ch;
  301. *ch_mask = (*map)[i][j].ch_mask;
  302. *ch_rate = (*map)[i][j].ch_rate;
  303. *port_type = (*map)[i][j].master_port_type;
  304. return 0;
  305. }
  306. static int wcd938x_parse_port_mapping(struct device *dev,
  307. char *prop, u8 path)
  308. {
  309. u32 *dt_array, map_size, map_length;
  310. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  311. u32 slave_port_type, master_port_type;
  312. u32 i, ch_iter = 0;
  313. int ret = 0;
  314. u8 *num_ports = NULL;
  315. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  316. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  317. switch (path) {
  318. case CODEC_RX:
  319. map = &wcd938x->rx_port_mapping;
  320. num_ports = &wcd938x->num_rx_ports;
  321. break;
  322. case CODEC_TX:
  323. map = &wcd938x->tx_port_mapping;
  324. num_ports = &wcd938x->num_tx_ports;
  325. break;
  326. default:
  327. dev_err(dev, "%s Invalid path selected %u\n",
  328. __func__, path);
  329. return -EINVAL;
  330. }
  331. if (!of_find_property(dev->of_node, prop,
  332. &map_size)) {
  333. dev_err(dev, "missing port mapping prop %s\n", prop);
  334. ret = -EINVAL;
  335. goto err_port_map;
  336. }
  337. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  338. dt_array = kzalloc(map_size, GFP_KERNEL);
  339. if (!dt_array) {
  340. ret = -ENOMEM;
  341. goto err_alloc;
  342. }
  343. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  344. NUM_SWRS_DT_PARAMS * map_length);
  345. if (ret) {
  346. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  347. __func__, prop);
  348. goto err_pdata_fail;
  349. }
  350. for (i = 0; i < map_length; i++) {
  351. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  352. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  353. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  354. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  355. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  356. if (port_num != old_port_num)
  357. ch_iter = 0;
  358. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  359. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  360. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  361. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  362. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  363. old_port_num = port_num;
  364. }
  365. *num_ports = port_num;
  366. kfree(dt_array);
  367. return 0;
  368. err_pdata_fail:
  369. kfree(dt_array);
  370. err_alloc:
  371. err_port_map:
  372. return ret;
  373. }
  374. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  375. u8 slv_port_type, int clk_rate,
  376. u8 enable)
  377. {
  378. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  379. u8 port_id, num_ch, ch_mask;
  380. u8 ch_type = 0;
  381. u32 ch_rate;
  382. int slave_ch_idx;
  383. u8 num_port = 1;
  384. int ret = 0;
  385. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  386. &num_ch, &ch_mask, &ch_rate,
  387. &ch_type, CODEC_TX);
  388. if (ret)
  389. return ret;
  390. if (clk_rate)
  391. ch_rate = clk_rate;
  392. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  393. if (slave_ch_idx != -EINVAL)
  394. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  395. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  396. __func__, slave_ch_idx, ch_type);
  397. if (enable)
  398. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  399. num_port, &ch_mask, &ch_rate,
  400. &num_ch, &ch_type);
  401. else
  402. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  403. num_port, &ch_mask, &ch_type);
  404. return ret;
  405. }
  406. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  407. u8 slv_port_type, u8 enable)
  408. {
  409. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  410. u8 port_id, num_ch, ch_mask, port_type;
  411. u32 ch_rate;
  412. u8 num_port = 1;
  413. int ret = 0;
  414. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  415. &num_ch, &ch_mask, &ch_rate,
  416. &port_type, CODEC_RX);
  417. if (ret)
  418. return ret;
  419. if (enable)
  420. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  421. num_port, &ch_mask, &ch_rate,
  422. &num_ch, &port_type);
  423. else
  424. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  425. num_port, &ch_mask, &port_type);
  426. return ret;
  427. }
  428. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  429. {
  430. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  431. if (wcd938x->rx_clk_cnt == 0) {
  432. snd_soc_component_update_bits(component,
  433. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  434. snd_soc_component_update_bits(component,
  435. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  436. snd_soc_component_update_bits(component,
  437. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  438. snd_soc_component_update_bits(component,
  439. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  440. snd_soc_component_update_bits(component,
  441. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  442. snd_soc_component_update_bits(component,
  443. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  444. snd_soc_component_update_bits(component,
  445. WCD938X_AUX_AUXPA, 0x10, 0x10);
  446. }
  447. wcd938x->rx_clk_cnt++;
  448. return 0;
  449. }
  450. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  451. {
  452. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  453. wcd938x->rx_clk_cnt--;
  454. if (wcd938x->rx_clk_cnt == 0) {
  455. snd_soc_component_update_bits(component,
  456. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  457. snd_soc_component_update_bits(component,
  458. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  459. snd_soc_component_update_bits(component,
  460. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  461. snd_soc_component_update_bits(component,
  462. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  463. snd_soc_component_update_bits(component,
  464. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  465. }
  466. return 0;
  467. }
  468. /*
  469. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  470. * @component: handle to snd_soc_component *
  471. *
  472. * return wcd938x_mbhc handle or error code in case of failure
  473. */
  474. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  475. {
  476. struct wcd938x_priv *wcd938x;
  477. if (!component) {
  478. pr_err("%s: Invalid params, NULL component\n", __func__);
  479. return NULL;
  480. }
  481. wcd938x = snd_soc_component_get_drvdata(component);
  482. if (!wcd938x) {
  483. pr_err("%s: wcd938x is NULL\n", __func__);
  484. return NULL;
  485. }
  486. return wcd938x->mbhc;
  487. }
  488. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  489. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  490. struct snd_kcontrol *kcontrol,
  491. int event)
  492. {
  493. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  494. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  495. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  496. w->name, event);
  497. switch (event) {
  498. case SND_SOC_DAPM_PRE_PMU:
  499. wcd938x_rx_clk_enable(component);
  500. snd_soc_component_update_bits(component,
  501. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  502. snd_soc_component_update_bits(component,
  503. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  504. snd_soc_component_update_bits(component,
  505. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  506. break;
  507. case SND_SOC_DAPM_POST_PMU:
  508. snd_soc_component_update_bits(component,
  509. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  510. if (wcd938x->comp1_enable) {
  511. snd_soc_component_update_bits(component,
  512. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  513. /* 5msec compander delay as per HW requirement */
  514. if (!wcd938x->comp2_enable ||
  515. (snd_soc_component_read32(component,
  516. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  517. usleep_range(5000, 5010);
  518. snd_soc_component_update_bits(component,
  519. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  520. } else {
  521. snd_soc_component_update_bits(component,
  522. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  523. 0x02, 0x00);
  524. snd_soc_component_update_bits(component,
  525. WCD938X_HPH_L_EN, 0x20, 0x20);
  526. }
  527. break;
  528. case SND_SOC_DAPM_POST_PMD:
  529. snd_soc_component_update_bits(component,
  530. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  531. 0x0F, 0x01);
  532. break;
  533. }
  534. return 0;
  535. }
  536. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  537. struct snd_kcontrol *kcontrol,
  538. int event)
  539. {
  540. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  541. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  542. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  543. w->name, event);
  544. switch (event) {
  545. case SND_SOC_DAPM_PRE_PMU:
  546. wcd938x_rx_clk_enable(component);
  547. snd_soc_component_update_bits(component,
  548. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  549. snd_soc_component_update_bits(component,
  550. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  551. snd_soc_component_update_bits(component,
  552. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  553. break;
  554. case SND_SOC_DAPM_POST_PMU:
  555. snd_soc_component_update_bits(component,
  556. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  557. if (wcd938x->comp2_enable) {
  558. snd_soc_component_update_bits(component,
  559. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  560. /* 5msec compander delay as per HW requirement */
  561. if (!wcd938x->comp1_enable ||
  562. (snd_soc_component_read32(component,
  563. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  564. usleep_range(5000, 5010);
  565. snd_soc_component_update_bits(component,
  566. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  567. } else {
  568. snd_soc_component_update_bits(component,
  569. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  570. 0x01, 0x00);
  571. snd_soc_component_update_bits(component,
  572. WCD938X_HPH_R_EN, 0x20, 0x20);
  573. }
  574. break;
  575. case SND_SOC_DAPM_POST_PMD:
  576. snd_soc_component_update_bits(component,
  577. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  578. 0x0F, 0x01);
  579. break;
  580. }
  581. return 0;
  582. }
  583. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  584. struct snd_kcontrol *kcontrol,
  585. int event)
  586. {
  587. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  588. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  589. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  590. w->name, event);
  591. switch (event) {
  592. case SND_SOC_DAPM_PRE_PMU:
  593. wcd938x_rx_clk_enable(component);
  594. wcd938x->ear_rx_path =
  595. snd_soc_component_read32(
  596. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  597. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  598. snd_soc_component_update_bits(component,
  599. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  600. snd_soc_component_update_bits(component,
  601. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  602. snd_soc_component_update_bits(component,
  603. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  604. snd_soc_component_update_bits(component,
  605. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  606. } else {
  607. snd_soc_component_update_bits(component,
  608. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  609. snd_soc_component_update_bits(component,
  610. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  611. if (wcd938x->comp1_enable)
  612. snd_soc_component_update_bits(component,
  613. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  614. 0x02, 0x02);
  615. }
  616. /* 5 msec delay as per HW requirement */
  617. usleep_range(5000, 5010);
  618. if (wcd938x->flyback_cur_det_disable == 0)
  619. snd_soc_component_update_bits(component,
  620. WCD938X_FLYBACK_EN,
  621. 0x04, 0x00);
  622. wcd938x->flyback_cur_det_disable++;
  623. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  624. WCD_CLSH_EVENT_PRE_DAC,
  625. WCD_CLSH_STATE_EAR,
  626. wcd938x->hph_mode);
  627. break;
  628. case SND_SOC_DAPM_POST_PMD:
  629. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  630. snd_soc_component_update_bits(component,
  631. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  632. snd_soc_component_update_bits(component,
  633. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  634. } else {
  635. snd_soc_component_update_bits(component,
  636. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  637. snd_soc_component_update_bits(component,
  638. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  639. if (wcd938x->comp1_enable)
  640. snd_soc_component_update_bits(component,
  641. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  642. 0x02, 0x00);
  643. }
  644. snd_soc_component_update_bits(component,
  645. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  646. snd_soc_component_update_bits(component,
  647. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  648. break;
  649. };
  650. return 0;
  651. }
  652. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  653. struct snd_kcontrol *kcontrol,
  654. int event)
  655. {
  656. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  657. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  658. int ret = 0;
  659. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  660. w->name, event);
  661. switch (event) {
  662. case SND_SOC_DAPM_PRE_PMU:
  663. wcd938x_rx_clk_enable(component);
  664. snd_soc_component_update_bits(component,
  665. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  666. snd_soc_component_update_bits(component,
  667. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  668. snd_soc_component_update_bits(component,
  669. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  670. if (wcd938x->flyback_cur_det_disable == 0)
  671. snd_soc_component_update_bits(component,
  672. WCD938X_FLYBACK_EN,
  673. 0x04, 0x00);
  674. wcd938x->flyback_cur_det_disable++;
  675. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  676. WCD_CLSH_EVENT_PRE_DAC,
  677. WCD_CLSH_STATE_AUX,
  678. wcd938x->hph_mode);
  679. break;
  680. case SND_SOC_DAPM_POST_PMD:
  681. snd_soc_component_update_bits(component,
  682. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  683. break;
  684. };
  685. return ret;
  686. }
  687. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  688. struct snd_kcontrol *kcontrol,
  689. int event)
  690. {
  691. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  692. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  693. int ret = 0;
  694. int hph_mode = wcd938x->hph_mode;
  695. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  696. w->name, event);
  697. switch (event) {
  698. case SND_SOC_DAPM_PRE_PMU:
  699. if (wcd938x->ldoh)
  700. snd_soc_component_update_bits(component,
  701. WCD938X_LDOH_MODE,
  702. 0x80, 0x80);
  703. if (wcd938x->update_wcd_event)
  704. wcd938x->update_wcd_event(wcd938x->handle,
  705. WCD_BOLERO_EVT_RX_MUTE,
  706. (WCD_RX2 << 0x10 | 0x1));
  707. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  708. wcd938x->rx_swr_dev->dev_num,
  709. true);
  710. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  711. WCD_CLSH_EVENT_PRE_DAC,
  712. WCD_CLSH_STATE_HPHR,
  713. hph_mode);
  714. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  715. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  716. hph_mode == CLS_H_ULP) {
  717. snd_soc_component_update_bits(component,
  718. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  719. }
  720. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  721. 0x10, 0x10);
  722. wcd_clsh_set_hph_mode(component, hph_mode);
  723. /* 100 usec delay as per HW requirement */
  724. usleep_range(100, 110);
  725. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  726. snd_soc_component_update_bits(component,
  727. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  728. break;
  729. case SND_SOC_DAPM_POST_PMU:
  730. /*
  731. * 7ms sleep is required if compander is enabled as per
  732. * HW requirement. If compander is disabled, then
  733. * 20ms delay is required.
  734. */
  735. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  736. if (!wcd938x->comp2_enable)
  737. usleep_range(20000, 20100);
  738. else
  739. usleep_range(7000, 7100);
  740. if (hph_mode == CLS_H_LP ||
  741. hph_mode == CLS_H_LOHIFI ||
  742. hph_mode == CLS_H_ULP)
  743. snd_soc_component_update_bits(component,
  744. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  745. 0x00);
  746. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  747. }
  748. snd_soc_component_update_bits(component,
  749. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  750. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  751. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  752. snd_soc_component_update_bits(component,
  753. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  754. if (wcd938x->update_wcd_event)
  755. wcd938x->update_wcd_event(wcd938x->handle,
  756. WCD_BOLERO_EVT_RX_MUTE,
  757. (WCD_RX2 << 0x10));
  758. wcd_enable_irq(&wcd938x->irq_info,
  759. WCD938X_IRQ_HPHR_PDM_WD_INT);
  760. break;
  761. case SND_SOC_DAPM_PRE_PMD:
  762. if (wcd938x->update_wcd_event)
  763. wcd938x->update_wcd_event(wcd938x->handle,
  764. WCD_BOLERO_EVT_RX_MUTE,
  765. (WCD_RX2 << 0x10 | 0x1));
  766. wcd_disable_irq(&wcd938x->irq_info,
  767. WCD938X_IRQ_HPHR_PDM_WD_INT);
  768. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  769. wcd938x->update_wcd_event(wcd938x->handle,
  770. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  771. (WCD_RX2 << 0x10));
  772. /*
  773. * 7ms sleep is required if compander is enabled as per
  774. * HW requirement. If compander is disabled, then
  775. * 20ms delay is required.
  776. */
  777. if (!wcd938x->comp2_enable)
  778. usleep_range(20000, 20100);
  779. else
  780. usleep_range(7000, 7100);
  781. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  782. 0x40, 0x00);
  783. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  784. WCD_EVENT_PRE_HPHR_PA_OFF,
  785. &wcd938x->mbhc->wcd_mbhc);
  786. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  787. break;
  788. case SND_SOC_DAPM_POST_PMD:
  789. /*
  790. * 7ms sleep is required if compander is enabled as per
  791. * HW requirement. If compander is disabled, then
  792. * 20ms delay is required.
  793. */
  794. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  795. if (!wcd938x->comp2_enable)
  796. usleep_range(20000, 20100);
  797. else
  798. usleep_range(7000, 7100);
  799. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  800. }
  801. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  802. WCD_EVENT_POST_HPHR_PA_OFF,
  803. &wcd938x->mbhc->wcd_mbhc);
  804. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  805. 0x10, 0x00);
  806. snd_soc_component_update_bits(component,
  807. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  808. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  809. WCD_CLSH_EVENT_POST_PA,
  810. WCD_CLSH_STATE_HPHR,
  811. hph_mode);
  812. if (wcd938x->ldoh)
  813. snd_soc_component_update_bits(component,
  814. WCD938X_LDOH_MODE,
  815. 0x80, 0x00);
  816. break;
  817. };
  818. return ret;
  819. }
  820. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  821. struct snd_kcontrol *kcontrol,
  822. int event)
  823. {
  824. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  825. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  826. int ret = 0;
  827. int hph_mode = wcd938x->hph_mode;
  828. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  829. w->name, event);
  830. switch (event) {
  831. case SND_SOC_DAPM_PRE_PMU:
  832. if (wcd938x->ldoh)
  833. snd_soc_component_update_bits(component,
  834. WCD938X_LDOH_MODE,
  835. 0x80, 0x80);
  836. if (wcd938x->update_wcd_event)
  837. wcd938x->update_wcd_event(wcd938x->handle,
  838. WCD_BOLERO_EVT_RX_MUTE,
  839. (WCD_RX1 << 0x10 | 0x01));
  840. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  841. wcd938x->rx_swr_dev->dev_num,
  842. true);
  843. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  844. WCD_CLSH_EVENT_PRE_DAC,
  845. WCD_CLSH_STATE_HPHL,
  846. hph_mode);
  847. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  848. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  849. hph_mode == CLS_H_ULP) {
  850. snd_soc_component_update_bits(component,
  851. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  852. }
  853. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  854. 0x20, 0x20);
  855. wcd_clsh_set_hph_mode(component, hph_mode);
  856. /* 100 usec delay as per HW requirement */
  857. usleep_range(100, 110);
  858. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  859. snd_soc_component_update_bits(component,
  860. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  861. break;
  862. case SND_SOC_DAPM_POST_PMU:
  863. /*
  864. * 7ms sleep is required if compander is enabled as per
  865. * HW requirement. If compander is disabled, then
  866. * 20ms delay is required.
  867. */
  868. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  869. if (!wcd938x->comp1_enable)
  870. usleep_range(20000, 20100);
  871. else
  872. usleep_range(7000, 7100);
  873. if (hph_mode == CLS_H_LP ||
  874. hph_mode == CLS_H_LOHIFI ||
  875. hph_mode == CLS_H_ULP)
  876. snd_soc_component_update_bits(component,
  877. WCD938X_HPH_REFBUFF_LP_CTL,
  878. 0x01, 0x00);
  879. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  880. }
  881. snd_soc_component_update_bits(component,
  882. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  883. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  884. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  885. snd_soc_component_update_bits(component,
  886. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  887. if (wcd938x->update_wcd_event)
  888. wcd938x->update_wcd_event(wcd938x->handle,
  889. WCD_BOLERO_EVT_RX_MUTE,
  890. (WCD_RX1 << 0x10));
  891. wcd_enable_irq(&wcd938x->irq_info,
  892. WCD938X_IRQ_HPHL_PDM_WD_INT);
  893. break;
  894. case SND_SOC_DAPM_PRE_PMD:
  895. if (wcd938x->update_wcd_event)
  896. wcd938x->update_wcd_event(wcd938x->handle,
  897. WCD_BOLERO_EVT_RX_MUTE,
  898. (WCD_RX1 << 0x10 | 0x1));
  899. wcd_disable_irq(&wcd938x->irq_info,
  900. WCD938X_IRQ_HPHL_PDM_WD_INT);
  901. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  902. wcd938x->update_wcd_event(wcd938x->handle,
  903. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  904. (WCD_RX1 << 0x10));
  905. /*
  906. * 7ms sleep is required if compander is enabled as per
  907. * HW requirement. If compander is disabled, then
  908. * 20ms delay is required.
  909. */
  910. if (!wcd938x->comp1_enable)
  911. usleep_range(20000, 20100);
  912. else
  913. usleep_range(7000, 7100);
  914. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  915. 0x80, 0x00);
  916. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  917. WCD_EVENT_PRE_HPHL_PA_OFF,
  918. &wcd938x->mbhc->wcd_mbhc);
  919. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  920. break;
  921. case SND_SOC_DAPM_POST_PMD:
  922. /*
  923. * 7ms sleep is required if compander is enabled as per
  924. * HW requirement. If compander is disabled, then
  925. * 20ms delay is required.
  926. */
  927. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  928. if (!wcd938x->comp1_enable)
  929. usleep_range(21000, 21100);
  930. else
  931. usleep_range(7000, 7100);
  932. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  933. }
  934. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  935. WCD_EVENT_POST_HPHL_PA_OFF,
  936. &wcd938x->mbhc->wcd_mbhc);
  937. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  938. 0x20, 0x00);
  939. snd_soc_component_update_bits(component,
  940. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  941. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  942. WCD_CLSH_EVENT_POST_PA,
  943. WCD_CLSH_STATE_HPHL,
  944. hph_mode);
  945. if (wcd938x->ldoh)
  946. snd_soc_component_update_bits(component,
  947. WCD938X_LDOH_MODE,
  948. 0x80, 0x00);
  949. break;
  950. };
  951. return ret;
  952. }
  953. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  954. struct snd_kcontrol *kcontrol,
  955. int event)
  956. {
  957. struct snd_soc_component *component =
  958. snd_soc_dapm_to_component(w->dapm);
  959. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  960. int hph_mode = wcd938x->hph_mode;
  961. int ret = 0;
  962. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  963. w->name, event);
  964. switch (event) {
  965. case SND_SOC_DAPM_PRE_PMU:
  966. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  967. wcd938x->rx_swr_dev->dev_num,
  968. true);
  969. snd_soc_component_update_bits(component,
  970. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  971. break;
  972. case SND_SOC_DAPM_POST_PMU:
  973. /* 1 msec delay as per HW requirement */
  974. usleep_range(1000, 1010);
  975. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  976. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  977. snd_soc_component_update_bits(component,
  978. WCD938X_ANA_RX_SUPPLIES,
  979. 0x02, 0x02);
  980. if (wcd938x->update_wcd_event)
  981. wcd938x->update_wcd_event(wcd938x->handle,
  982. WCD_BOLERO_EVT_RX_MUTE,
  983. (WCD_RX3 << 0x10));
  984. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  985. break;
  986. case SND_SOC_DAPM_PRE_PMD:
  987. wcd_disable_irq(&wcd938x->irq_info,
  988. WCD938X_IRQ_AUX_PDM_WD_INT);
  989. if (wcd938x->update_wcd_event)
  990. wcd938x->update_wcd_event(wcd938x->handle,
  991. WCD_BOLERO_EVT_RX_MUTE,
  992. (WCD_RX3 << 0x10 | 0x1));
  993. break;
  994. case SND_SOC_DAPM_POST_PMD:
  995. /* 1 msec delay as per HW requirement */
  996. usleep_range(1000, 1010);
  997. snd_soc_component_update_bits(component,
  998. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  999. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1000. WCD_CLSH_EVENT_POST_PA,
  1001. WCD_CLSH_STATE_AUX,
  1002. hph_mode);
  1003. wcd938x->flyback_cur_det_disable--;
  1004. if (wcd938x->flyback_cur_det_disable == 0)
  1005. snd_soc_component_update_bits(component,
  1006. WCD938X_FLYBACK_EN,
  1007. 0x04, 0x04);
  1008. break;
  1009. };
  1010. return ret;
  1011. }
  1012. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1013. struct snd_kcontrol *kcontrol,
  1014. int event)
  1015. {
  1016. struct snd_soc_component *component =
  1017. snd_soc_dapm_to_component(w->dapm);
  1018. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1019. int hph_mode = wcd938x->hph_mode;
  1020. int ret = 0;
  1021. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1022. w->name, event);
  1023. switch (event) {
  1024. case SND_SOC_DAPM_PRE_PMU:
  1025. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1026. wcd938x->rx_swr_dev->dev_num,
  1027. true);
  1028. /*
  1029. * Enable watchdog interrupt for HPHL or AUX
  1030. * depending on mux value
  1031. */
  1032. wcd938x->ear_rx_path =
  1033. snd_soc_component_read32(
  1034. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1035. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1036. snd_soc_component_update_bits(component,
  1037. WCD938X_DIGITAL_PDM_WD_CTL2,
  1038. 0x01, 0x01);
  1039. else
  1040. snd_soc_component_update_bits(component,
  1041. WCD938X_DIGITAL_PDM_WD_CTL0,
  1042. 0x07, 0x03);
  1043. if (!wcd938x->comp1_enable)
  1044. snd_soc_component_update_bits(component,
  1045. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1046. break;
  1047. case SND_SOC_DAPM_POST_PMU:
  1048. /* 6 msec delay as per HW requirement */
  1049. usleep_range(6000, 6010);
  1050. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1051. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1052. snd_soc_component_update_bits(component,
  1053. WCD938X_ANA_RX_SUPPLIES,
  1054. 0x02, 0x02);
  1055. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1056. if (wcd938x->update_wcd_event)
  1057. wcd938x->update_wcd_event(wcd938x->handle,
  1058. WCD_BOLERO_EVT_RX_MUTE,
  1059. (WCD_RX3 << 0x10));
  1060. wcd_enable_irq(&wcd938x->irq_info,
  1061. WCD938X_IRQ_AUX_PDM_WD_INT);
  1062. } else {
  1063. if (wcd938x->update_wcd_event)
  1064. wcd938x->update_wcd_event(wcd938x->handle,
  1065. WCD_BOLERO_EVT_RX_MUTE,
  1066. (WCD_RX1 << 0x10));
  1067. wcd_enable_irq(&wcd938x->irq_info,
  1068. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1069. }
  1070. break;
  1071. case SND_SOC_DAPM_PRE_PMD:
  1072. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1073. wcd_disable_irq(&wcd938x->irq_info,
  1074. WCD938X_IRQ_AUX_PDM_WD_INT);
  1075. if (wcd938x->update_wcd_event)
  1076. wcd938x->update_wcd_event(wcd938x->handle,
  1077. WCD_BOLERO_EVT_RX_MUTE,
  1078. (WCD_RX3 << 0x10 | 0x1));
  1079. } else {
  1080. wcd_disable_irq(&wcd938x->irq_info,
  1081. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1082. if (wcd938x->update_wcd_event)
  1083. wcd938x->update_wcd_event(wcd938x->handle,
  1084. WCD_BOLERO_EVT_RX_MUTE,
  1085. (WCD_RX1 << 0x10 | 0x1));
  1086. }
  1087. break;
  1088. case SND_SOC_DAPM_POST_PMD:
  1089. if (!wcd938x->comp1_enable)
  1090. snd_soc_component_update_bits(component,
  1091. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1092. /* 7 msec delay as per HW requirement */
  1093. usleep_range(7000, 7010);
  1094. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1095. snd_soc_component_update_bits(component,
  1096. WCD938X_DIGITAL_PDM_WD_CTL2,
  1097. 0x01, 0x00);
  1098. else
  1099. snd_soc_component_update_bits(component,
  1100. WCD938X_DIGITAL_PDM_WD_CTL0,
  1101. 0x07, 0x00);
  1102. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1103. WCD_CLSH_EVENT_POST_PA,
  1104. WCD_CLSH_STATE_EAR,
  1105. hph_mode);
  1106. wcd938x->flyback_cur_det_disable--;
  1107. if (wcd938x->flyback_cur_det_disable == 0)
  1108. snd_soc_component_update_bits(component,
  1109. WCD938X_FLYBACK_EN,
  1110. 0x04, 0x04);
  1111. break;
  1112. };
  1113. return ret;
  1114. }
  1115. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1116. struct snd_kcontrol *kcontrol,
  1117. int event)
  1118. {
  1119. struct snd_soc_component *component =
  1120. snd_soc_dapm_to_component(w->dapm);
  1121. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1122. int mode = wcd938x->hph_mode;
  1123. int ret = 0;
  1124. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1125. w->name, event);
  1126. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1127. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1128. wcd938x_rx_connect_port(component, CLSH,
  1129. SND_SOC_DAPM_EVENT_ON(event));
  1130. }
  1131. if (SND_SOC_DAPM_EVENT_OFF(event))
  1132. ret = swr_slvdev_datapath_control(
  1133. wcd938x->rx_swr_dev,
  1134. wcd938x->rx_swr_dev->dev_num,
  1135. false);
  1136. return ret;
  1137. }
  1138. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1139. struct snd_kcontrol *kcontrol,
  1140. int event)
  1141. {
  1142. struct snd_soc_component *component =
  1143. snd_soc_dapm_to_component(w->dapm);
  1144. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1145. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1146. w->name, event);
  1147. switch (event) {
  1148. case SND_SOC_DAPM_PRE_PMU:
  1149. wcd938x_rx_connect_port(component, HPH_L, true);
  1150. if (wcd938x->comp1_enable)
  1151. wcd938x_rx_connect_port(component, COMP_L, true);
  1152. break;
  1153. case SND_SOC_DAPM_POST_PMD:
  1154. wcd938x_rx_connect_port(component, HPH_L, false);
  1155. if (wcd938x->comp1_enable)
  1156. wcd938x_rx_connect_port(component, COMP_L, false);
  1157. wcd938x_rx_clk_disable(component);
  1158. snd_soc_component_update_bits(component,
  1159. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1160. 0x01, 0x00);
  1161. break;
  1162. };
  1163. return 0;
  1164. }
  1165. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1166. struct snd_kcontrol *kcontrol, int event)
  1167. {
  1168. struct snd_soc_component *component =
  1169. snd_soc_dapm_to_component(w->dapm);
  1170. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1171. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1172. w->name, event);
  1173. switch (event) {
  1174. case SND_SOC_DAPM_PRE_PMU:
  1175. wcd938x_rx_connect_port(component, HPH_R, true);
  1176. if (wcd938x->comp2_enable)
  1177. wcd938x_rx_connect_port(component, COMP_R, true);
  1178. break;
  1179. case SND_SOC_DAPM_POST_PMD:
  1180. wcd938x_rx_connect_port(component, HPH_R, false);
  1181. if (wcd938x->comp2_enable)
  1182. wcd938x_rx_connect_port(component, COMP_R, false);
  1183. wcd938x_rx_clk_disable(component);
  1184. snd_soc_component_update_bits(component,
  1185. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1186. 0x02, 0x00);
  1187. break;
  1188. };
  1189. return 0;
  1190. }
  1191. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1192. struct snd_kcontrol *kcontrol,
  1193. int event)
  1194. {
  1195. struct snd_soc_component *component =
  1196. snd_soc_dapm_to_component(w->dapm);
  1197. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1198. w->name, event);
  1199. switch (event) {
  1200. case SND_SOC_DAPM_PRE_PMU:
  1201. wcd938x_rx_connect_port(component, LO, true);
  1202. break;
  1203. case SND_SOC_DAPM_POST_PMD:
  1204. wcd938x_rx_connect_port(component, LO, false);
  1205. /* 6 msec delay as per HW requirement */
  1206. usleep_range(6000, 6010);
  1207. wcd938x_rx_clk_disable(component);
  1208. snd_soc_component_update_bits(component,
  1209. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1210. break;
  1211. }
  1212. return 0;
  1213. }
  1214. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1215. struct snd_kcontrol *kcontrol,
  1216. int event)
  1217. {
  1218. struct snd_soc_component *component =
  1219. snd_soc_dapm_to_component(w->dapm);
  1220. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1221. u16 dmic_clk_reg, dmic_clk_en_reg;
  1222. s32 *dmic_clk_cnt;
  1223. u8 dmic_ctl_shift = 0;
  1224. u8 dmic_clk_shift = 0;
  1225. u8 dmic_clk_mask = 0;
  1226. u16 dmic2_left_en = 0;
  1227. int ret = 0;
  1228. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1229. w->name, event);
  1230. switch (w->shift) {
  1231. case 0:
  1232. case 1:
  1233. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1234. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1235. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1236. dmic_clk_mask = 0x0F;
  1237. dmic_clk_shift = 0x00;
  1238. dmic_ctl_shift = 0x00;
  1239. break;
  1240. case 2:
  1241. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1242. case 3:
  1243. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1244. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1245. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1246. dmic_clk_mask = 0xF0;
  1247. dmic_clk_shift = 0x04;
  1248. dmic_ctl_shift = 0x01;
  1249. break;
  1250. case 4:
  1251. case 5:
  1252. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1253. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1254. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1255. dmic_clk_mask = 0x0F;
  1256. dmic_clk_shift = 0x00;
  1257. dmic_ctl_shift = 0x02;
  1258. break;
  1259. case 6:
  1260. case 7:
  1261. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1262. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1263. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1264. dmic_clk_mask = 0xF0;
  1265. dmic_clk_shift = 0x04;
  1266. dmic_ctl_shift = 0x03;
  1267. break;
  1268. default:
  1269. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1270. __func__);
  1271. return -EINVAL;
  1272. };
  1273. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1274. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1275. switch (event) {
  1276. case SND_SOC_DAPM_PRE_PMU:
  1277. snd_soc_component_update_bits(component,
  1278. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1279. (0x01 << dmic_ctl_shift), 0x00);
  1280. /* 250us sleep as per HW requirement */
  1281. usleep_range(250, 260);
  1282. if (dmic2_left_en)
  1283. snd_soc_component_update_bits(component,
  1284. dmic2_left_en, 0x80, 0x80);
  1285. /* Setting DMIC clock rate to 2.4MHz */
  1286. snd_soc_component_update_bits(component,
  1287. dmic_clk_reg, dmic_clk_mask,
  1288. (0x03 << dmic_clk_shift));
  1289. snd_soc_component_update_bits(component,
  1290. dmic_clk_en_reg, 0x08, 0x08);
  1291. /* enable clock scaling */
  1292. snd_soc_component_update_bits(component,
  1293. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1294. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1295. wcd938x->tx_swr_dev->dev_num,
  1296. true);
  1297. break;
  1298. case SND_SOC_DAPM_POST_PMD:
  1299. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1300. wcd938x->tx_swr_dev->dev_num,
  1301. false);
  1302. snd_soc_component_update_bits(component,
  1303. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1304. (0x01 << dmic_ctl_shift),
  1305. (0x01 << dmic_ctl_shift));
  1306. if (dmic2_left_en)
  1307. snd_soc_component_update_bits(component,
  1308. dmic2_left_en, 0x80, 0x00);
  1309. snd_soc_component_update_bits(component,
  1310. dmic_clk_en_reg, 0x08, 0x00);
  1311. break;
  1312. };
  1313. return ret;
  1314. }
  1315. /*
  1316. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1317. * @micb_mv: micbias in mv
  1318. *
  1319. * return register value converted
  1320. */
  1321. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1322. {
  1323. /* min micbias voltage is 1V and maximum is 2.85V */
  1324. if (micb_mv < 1000 || micb_mv > 2850) {
  1325. pr_err("%s: unsupported micbias voltage\n", __func__);
  1326. return -EINVAL;
  1327. }
  1328. return (micb_mv - 1000) / 50;
  1329. }
  1330. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1331. /*
  1332. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1333. * @component: handle to snd_soc_component *
  1334. * @req_volt: micbias voltage to be set
  1335. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1336. *
  1337. * return 0 if adjustment is success or error code in case of failure
  1338. */
  1339. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1340. int req_volt, int micb_num)
  1341. {
  1342. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1343. int cur_vout_ctl, req_vout_ctl;
  1344. int micb_reg, micb_val, micb_en;
  1345. int ret = 0;
  1346. switch (micb_num) {
  1347. case MIC_BIAS_1:
  1348. micb_reg = WCD938X_ANA_MICB1;
  1349. break;
  1350. case MIC_BIAS_2:
  1351. micb_reg = WCD938X_ANA_MICB2;
  1352. break;
  1353. case MIC_BIAS_3:
  1354. micb_reg = WCD938X_ANA_MICB3;
  1355. break;
  1356. case MIC_BIAS_4:
  1357. micb_reg = WCD938X_ANA_MICB4;
  1358. break;
  1359. default:
  1360. return -EINVAL;
  1361. }
  1362. mutex_lock(&wcd938x->micb_lock);
  1363. /*
  1364. * If requested micbias voltage is same as current micbias
  1365. * voltage, then just return. Otherwise, adjust voltage as
  1366. * per requested value. If micbias is already enabled, then
  1367. * to avoid slow micbias ramp-up or down enable pull-up
  1368. * momentarily, change the micbias value and then re-enable
  1369. * micbias.
  1370. */
  1371. micb_val = snd_soc_component_read32(component, micb_reg);
  1372. micb_en = (micb_val & 0xC0) >> 6;
  1373. cur_vout_ctl = micb_val & 0x3F;
  1374. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1375. if (req_vout_ctl < 0) {
  1376. ret = -EINVAL;
  1377. goto exit;
  1378. }
  1379. if (cur_vout_ctl == req_vout_ctl) {
  1380. ret = 0;
  1381. goto exit;
  1382. }
  1383. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1384. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1385. req_volt, micb_en);
  1386. if (micb_en == 0x1)
  1387. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1388. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1389. if (micb_en == 0x1) {
  1390. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1391. /*
  1392. * Add 2ms delay as per HW requirement after enabling
  1393. * micbias
  1394. */
  1395. usleep_range(2000, 2100);
  1396. }
  1397. exit:
  1398. mutex_unlock(&wcd938x->micb_lock);
  1399. return ret;
  1400. }
  1401. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1402. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1403. struct snd_kcontrol *kcontrol,
  1404. int event)
  1405. {
  1406. struct snd_soc_component *component =
  1407. snd_soc_dapm_to_component(w->dapm);
  1408. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1409. int ret = 0;
  1410. int bank = 0;
  1411. u8 mode = 0;
  1412. int i = 0;
  1413. int rate = 0;
  1414. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1415. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1416. switch (event) {
  1417. case SND_SOC_DAPM_PRE_PMU:
  1418. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1419. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1420. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1421. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1422. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1423. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1424. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1425. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1426. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1427. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1428. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1429. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1430. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1431. if (mode != 0) {
  1432. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1433. if (mode & (1 << i)) {
  1434. i++;
  1435. break;
  1436. }
  1437. }
  1438. }
  1439. rate = wcd938x_get_clk_rate(i);
  1440. wcd938x_set_swr_clk_rate(component, rate, bank);
  1441. }
  1442. if (w->shift == ADC2 && !(snd_soc_component_read32(component,
  1443. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1444. if (!wcd938x->bcs_dis)
  1445. wcd938x_tx_connect_port(component, MBHC,
  1446. SWR_CLK_RATE_4P8MHZ, true);
  1447. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1448. }
  1449. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1450. wcd938x_tx_connect_port(component, w->shift, rate,
  1451. true);
  1452. /* Copy clk settings to active bank */
  1453. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1454. } else {
  1455. wcd938x_tx_connect_port(component, w->shift,
  1456. SWR_CLK_RATE_2P4MHZ, true);
  1457. }
  1458. break;
  1459. case SND_SOC_DAPM_POST_PMD:
  1460. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1461. rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
  1462. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1463. }
  1464. wcd938x_tx_connect_port(component, w->shift, 0, false);
  1465. if (w->shift == ADC2 &&
  1466. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1467. if (!wcd938x->bcs_dis)
  1468. wcd938x_tx_connect_port(component, MBHC, 0,
  1469. false);
  1470. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1471. }
  1472. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1473. wcd938x_set_swr_clk_rate(component, rate, bank);
  1474. if (strnstr(w->name, "ADC1", sizeof("ADC1")))
  1475. clear_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1476. else if (strnstr(w->name, "ADC2", sizeof("ADC2")))
  1477. clear_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1478. else if (strnstr(w->name, "ADC3", sizeof("ADC3")))
  1479. clear_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1480. else if (strnstr(w->name, "ADC4", sizeof("ADC4")))
  1481. clear_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1482. break;
  1483. };
  1484. return ret;
  1485. }
  1486. static int wcd938x_get_adc_mode(int val)
  1487. {
  1488. int ret = 0;
  1489. switch (val) {
  1490. case ADC_MODE_INVALID:
  1491. ret = ADC_MODE_VAL_NORMAL;
  1492. break;
  1493. case ADC_MODE_HIFI:
  1494. ret = ADC_MODE_VAL_HIFI;
  1495. break;
  1496. case ADC_MODE_LO_HIF:
  1497. ret = ADC_MODE_VAL_LO_HIF;
  1498. break;
  1499. case ADC_MODE_NORMAL:
  1500. ret = ADC_MODE_VAL_NORMAL;
  1501. break;
  1502. case ADC_MODE_LP:
  1503. ret = ADC_MODE_VAL_LP;
  1504. break;
  1505. case ADC_MODE_ULP1:
  1506. ret = ADC_MODE_VAL_ULP1;
  1507. break;
  1508. case ADC_MODE_ULP2:
  1509. ret = ADC_MODE_VAL_ULP2;
  1510. break;
  1511. default:
  1512. ret = -EINVAL;
  1513. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1514. break;
  1515. }
  1516. return ret;
  1517. }
  1518. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1519. struct snd_kcontrol *kcontrol,
  1520. int event){
  1521. struct snd_soc_component *component =
  1522. snd_soc_dapm_to_component(w->dapm);
  1523. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1524. int clk_rate = 0, ret = 0;
  1525. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1526. w->name, event);
  1527. switch (event) {
  1528. case SND_SOC_DAPM_PRE_PMU:
  1529. snd_soc_component_update_bits(component,
  1530. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1531. snd_soc_component_update_bits(component,
  1532. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1533. set_bit(w->shift, &wcd938x->status_mask);
  1534. clk_rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift]);
  1535. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1536. wcd938x->tx_swr_dev->dev_num,
  1537. true);
  1538. break;
  1539. case SND_SOC_DAPM_POST_PMD:
  1540. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1541. wcd938x->tx_swr_dev->dev_num,
  1542. false);
  1543. snd_soc_component_update_bits(component,
  1544. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1545. clear_bit(w->shift, &wcd938x->status_mask);
  1546. break;
  1547. };
  1548. return ret;
  1549. }
  1550. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1551. bool bcs_disable)
  1552. {
  1553. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1554. if (wcd938x->update_wcd_event) {
  1555. if (bcs_disable)
  1556. wcd938x->update_wcd_event(wcd938x->handle,
  1557. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1558. else
  1559. wcd938x->update_wcd_event(wcd938x->handle,
  1560. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1561. }
  1562. }
  1563. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1564. int channel, int mode)
  1565. {
  1566. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1567. int ret = 0;
  1568. switch (channel) {
  1569. case 0:
  1570. reg = WCD938X_ANA_TX_CH2;
  1571. mask = 0x40;
  1572. break;
  1573. case 1:
  1574. reg = WCD938X_ANA_TX_CH2;
  1575. mask = 0x20;
  1576. break;
  1577. case 2:
  1578. reg = WCD938X_ANA_TX_CH4;
  1579. mask = 0x40;
  1580. break;
  1581. case 3:
  1582. reg = WCD938X_ANA_TX_CH4;
  1583. mask = 0x20;
  1584. break;
  1585. default:
  1586. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1587. ret = -EINVAL;
  1588. break;
  1589. }
  1590. if (!mode)
  1591. val = 0x00;
  1592. else
  1593. val = mask;
  1594. if (!ret)
  1595. snd_soc_component_update_bits(component, reg, mask, val);
  1596. return ret;
  1597. }
  1598. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1599. struct snd_kcontrol *kcontrol, int event)
  1600. {
  1601. struct snd_soc_component *component =
  1602. snd_soc_dapm_to_component(w->dapm);
  1603. int mode;
  1604. int ret = 0;
  1605. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1606. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1607. w->name, event);
  1608. switch (event) {
  1609. case SND_SOC_DAPM_PRE_PMU:
  1610. snd_soc_component_update_bits(component,
  1611. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1612. snd_soc_component_update_bits(component,
  1613. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1614. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1615. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1616. if (mode < 0) {
  1617. dev_info(component->dev,
  1618. "%s: invalid mode, setting to normal mode\n",
  1619. __func__);
  1620. mode = ADC_MODE_VAL_NORMAL;
  1621. }
  1622. switch (w->shift) {
  1623. case 0:
  1624. snd_soc_component_update_bits(component,
  1625. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1626. mode);
  1627. snd_soc_component_update_bits(component,
  1628. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1629. break;
  1630. case 1:
  1631. snd_soc_component_update_bits(component,
  1632. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1633. mode << 4);
  1634. snd_soc_component_update_bits(component,
  1635. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1636. break;
  1637. case 2:
  1638. snd_soc_component_update_bits(component,
  1639. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1640. mode);
  1641. snd_soc_component_update_bits(component,
  1642. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1643. break;
  1644. case 3:
  1645. snd_soc_component_update_bits(component,
  1646. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1647. mode << 4);
  1648. snd_soc_component_update_bits(component,
  1649. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1650. break;
  1651. default:
  1652. break;
  1653. }
  1654. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1655. break;
  1656. case SND_SOC_DAPM_POST_PMD:
  1657. switch (w->shift) {
  1658. case 0:
  1659. snd_soc_component_update_bits(component,
  1660. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1661. 0x00);
  1662. snd_soc_component_update_bits(component,
  1663. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1664. break;
  1665. case 1:
  1666. snd_soc_component_update_bits(component,
  1667. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1668. 0x00);
  1669. snd_soc_component_update_bits(component,
  1670. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1671. break;
  1672. case 2:
  1673. snd_soc_component_update_bits(component,
  1674. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1675. 0x00);
  1676. snd_soc_component_update_bits(component,
  1677. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1678. break;
  1679. case 3:
  1680. snd_soc_component_update_bits(component,
  1681. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1682. 0x00);
  1683. snd_soc_component_update_bits(component,
  1684. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1685. break;
  1686. default:
  1687. break;
  1688. }
  1689. snd_soc_component_update_bits(component,
  1690. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1691. break;
  1692. };
  1693. return ret;
  1694. }
  1695. int wcd938x_micbias_control(struct snd_soc_component *component,
  1696. int micb_num, int req, bool is_dapm)
  1697. {
  1698. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1699. int micb_index = micb_num - 1;
  1700. u16 micb_reg;
  1701. int pre_off_event = 0, post_off_event = 0;
  1702. int post_on_event = 0, post_dapm_off = 0;
  1703. int post_dapm_on = 0;
  1704. int ret = 0;
  1705. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1706. dev_err(component->dev,
  1707. "%s: Invalid micbias index, micb_ind:%d\n",
  1708. __func__, micb_index);
  1709. return -EINVAL;
  1710. }
  1711. if (NULL == wcd938x) {
  1712. dev_err(component->dev,
  1713. "%s: wcd938x private data is NULL\n", __func__);
  1714. return -EINVAL;
  1715. }
  1716. switch (micb_num) {
  1717. case MIC_BIAS_1:
  1718. micb_reg = WCD938X_ANA_MICB1;
  1719. break;
  1720. case MIC_BIAS_2:
  1721. micb_reg = WCD938X_ANA_MICB2;
  1722. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1723. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1724. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1725. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1726. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1727. break;
  1728. case MIC_BIAS_3:
  1729. micb_reg = WCD938X_ANA_MICB3;
  1730. break;
  1731. case MIC_BIAS_4:
  1732. micb_reg = WCD938X_ANA_MICB4;
  1733. break;
  1734. default:
  1735. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1736. __func__, micb_num);
  1737. return -EINVAL;
  1738. };
  1739. mutex_lock(&wcd938x->micb_lock);
  1740. switch (req) {
  1741. case MICB_PULLUP_ENABLE:
  1742. if (!wcd938x->dev_up) {
  1743. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1744. __func__, req);
  1745. ret = -ENODEV;
  1746. goto done;
  1747. }
  1748. wcd938x->pullup_ref[micb_index]++;
  1749. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1750. (wcd938x->micb_ref[micb_index] == 0))
  1751. snd_soc_component_update_bits(component, micb_reg,
  1752. 0xC0, 0x80);
  1753. break;
  1754. case MICB_PULLUP_DISABLE:
  1755. if (wcd938x->pullup_ref[micb_index] > 0)
  1756. wcd938x->pullup_ref[micb_index]--;
  1757. if (!wcd938x->dev_up) {
  1758. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1759. __func__, req);
  1760. ret = -ENODEV;
  1761. goto done;
  1762. }
  1763. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1764. (wcd938x->micb_ref[micb_index] == 0))
  1765. snd_soc_component_update_bits(component, micb_reg,
  1766. 0xC0, 0x00);
  1767. break;
  1768. case MICB_ENABLE:
  1769. if (!wcd938x->dev_up) {
  1770. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1771. __func__, req);
  1772. ret = -ENODEV;
  1773. goto done;
  1774. }
  1775. wcd938x->micb_ref[micb_index]++;
  1776. if (wcd938x->micb_ref[micb_index] == 1) {
  1777. snd_soc_component_update_bits(component,
  1778. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1779. snd_soc_component_update_bits(component,
  1780. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1781. snd_soc_component_update_bits(component,
  1782. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1783. snd_soc_component_update_bits(component,
  1784. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1785. snd_soc_component_update_bits(component,
  1786. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1787. snd_soc_component_update_bits(component,
  1788. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1789. snd_soc_component_update_bits(component,
  1790. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1791. snd_soc_component_update_bits(component,
  1792. micb_reg, 0xC0, 0x40);
  1793. if (post_on_event)
  1794. blocking_notifier_call_chain(
  1795. &wcd938x->mbhc->notifier,
  1796. post_on_event,
  1797. &wcd938x->mbhc->wcd_mbhc);
  1798. }
  1799. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1800. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1801. post_dapm_on,
  1802. &wcd938x->mbhc->wcd_mbhc);
  1803. break;
  1804. case MICB_DISABLE:
  1805. if (wcd938x->micb_ref[micb_index] > 0)
  1806. wcd938x->micb_ref[micb_index]--;
  1807. if (!wcd938x->dev_up) {
  1808. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1809. __func__, req);
  1810. ret = -ENODEV;
  1811. goto done;
  1812. }
  1813. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1814. (wcd938x->pullup_ref[micb_index] > 0))
  1815. snd_soc_component_update_bits(component, micb_reg,
  1816. 0xC0, 0x80);
  1817. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1818. (wcd938x->pullup_ref[micb_index] == 0)) {
  1819. if (pre_off_event && wcd938x->mbhc)
  1820. blocking_notifier_call_chain(
  1821. &wcd938x->mbhc->notifier,
  1822. pre_off_event,
  1823. &wcd938x->mbhc->wcd_mbhc);
  1824. snd_soc_component_update_bits(component, micb_reg,
  1825. 0xC0, 0x00);
  1826. if (post_off_event && wcd938x->mbhc)
  1827. blocking_notifier_call_chain(
  1828. &wcd938x->mbhc->notifier,
  1829. post_off_event,
  1830. &wcd938x->mbhc->wcd_mbhc);
  1831. }
  1832. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1833. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1834. post_dapm_off,
  1835. &wcd938x->mbhc->wcd_mbhc);
  1836. break;
  1837. };
  1838. dev_dbg(component->dev,
  1839. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1840. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1841. wcd938x->pullup_ref[micb_index]);
  1842. done:
  1843. mutex_unlock(&wcd938x->micb_lock);
  1844. return ret;
  1845. }
  1846. EXPORT_SYMBOL(wcd938x_micbias_control);
  1847. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1848. {
  1849. int ret = 0;
  1850. uint8_t devnum = 0;
  1851. int num_retry = NUM_ATTEMPTS;
  1852. do {
  1853. /* retry after 1ms */
  1854. usleep_range(1000, 1010);
  1855. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1856. } while (ret && --num_retry);
  1857. if (ret)
  1858. dev_err(&swr_dev->dev,
  1859. "%s get devnum %d for dev addr %llx failed\n",
  1860. __func__, devnum, swr_dev->addr);
  1861. swr_dev->dev_num = devnum;
  1862. return 0;
  1863. }
  1864. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1865. struct wcd_mbhc_config *mbhc_cfg)
  1866. {
  1867. if (mbhc_cfg->enable_usbc_analog) {
  1868. if (!(snd_soc_component_read32(component, WCD938X_ANA_MBHC_MECH)
  1869. & 0x20))
  1870. return true;
  1871. }
  1872. return false;
  1873. }
  1874. static int wcd938x_event_notify(struct notifier_block *block,
  1875. unsigned long val,
  1876. void *data)
  1877. {
  1878. u16 event = (val & 0xffff);
  1879. int ret = 0;
  1880. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1881. struct snd_soc_component *component = wcd938x->component;
  1882. struct wcd_mbhc *mbhc;
  1883. switch (event) {
  1884. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1885. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1886. snd_soc_component_update_bits(component,
  1887. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1888. set_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1889. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1890. }
  1891. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1892. snd_soc_component_update_bits(component,
  1893. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1894. set_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1895. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1896. }
  1897. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1898. snd_soc_component_update_bits(component,
  1899. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1900. set_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1901. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1902. }
  1903. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1904. snd_soc_component_update_bits(component,
  1905. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1906. set_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1907. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1908. }
  1909. break;
  1910. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1911. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1912. 0xC0, 0x00);
  1913. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1914. 0x80, 0x00);
  1915. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1916. 0x80, 0x00);
  1917. break;
  1918. case BOLERO_WCD_EVT_SSR_DOWN:
  1919. wcd938x->dev_up = false;
  1920. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1921. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1922. wcd938x->usbc_hs_status = get_usbc_hs_status(component,
  1923. mbhc->mbhc_cfg);
  1924. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1925. wcd938x_reset_low(wcd938x->dev);
  1926. break;
  1927. case BOLERO_WCD_EVT_SSR_UP:
  1928. wcd938x_reset(wcd938x->dev);
  1929. /* allow reset to take effect */
  1930. usleep_range(10000, 10010);
  1931. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1932. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1933. wcd938x_init_reg(component);
  1934. regcache_mark_dirty(wcd938x->regmap);
  1935. regcache_sync(wcd938x->regmap);
  1936. /* Initialize MBHC module */
  1937. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1938. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1939. if (ret) {
  1940. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1941. __func__);
  1942. } else {
  1943. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1944. if (wcd938x->usbc_hs_status)
  1945. mdelay(500);
  1946. }
  1947. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1948. wcd938x->dev_up = true;
  1949. break;
  1950. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1951. snd_soc_component_update_bits(component,
  1952. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1953. ((val >> 0x10) << 0x01));
  1954. break;
  1955. default:
  1956. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1957. break;
  1958. }
  1959. return 0;
  1960. }
  1961. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1962. int event)
  1963. {
  1964. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1965. int micb_num;
  1966. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1967. __func__, w->name, event);
  1968. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1969. micb_num = MIC_BIAS_1;
  1970. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1971. micb_num = MIC_BIAS_2;
  1972. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1973. micb_num = MIC_BIAS_3;
  1974. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1975. micb_num = MIC_BIAS_4;
  1976. else
  1977. return -EINVAL;
  1978. switch (event) {
  1979. case SND_SOC_DAPM_PRE_PMU:
  1980. wcd938x_micbias_control(component, micb_num,
  1981. MICB_ENABLE, true);
  1982. break;
  1983. case SND_SOC_DAPM_POST_PMU:
  1984. /* 1 msec delay as per HW requirement */
  1985. usleep_range(1000, 1100);
  1986. break;
  1987. case SND_SOC_DAPM_POST_PMD:
  1988. wcd938x_micbias_control(component, micb_num,
  1989. MICB_DISABLE, true);
  1990. break;
  1991. };
  1992. return 0;
  1993. }
  1994. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1995. struct snd_kcontrol *kcontrol,
  1996. int event)
  1997. {
  1998. return __wcd938x_codec_enable_micbias(w, event);
  1999. }
  2000. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2001. int event)
  2002. {
  2003. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2004. int micb_num;
  2005. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2006. __func__, w->name, event);
  2007. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2008. micb_num = MIC_BIAS_1;
  2009. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2010. micb_num = MIC_BIAS_2;
  2011. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2012. micb_num = MIC_BIAS_3;
  2013. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2014. micb_num = MIC_BIAS_4;
  2015. else
  2016. return -EINVAL;
  2017. switch (event) {
  2018. case SND_SOC_DAPM_PRE_PMU:
  2019. wcd938x_micbias_control(component, micb_num,
  2020. MICB_PULLUP_ENABLE, true);
  2021. break;
  2022. case SND_SOC_DAPM_POST_PMU:
  2023. /* 1 msec delay as per HW requirement */
  2024. usleep_range(1000, 1100);
  2025. break;
  2026. case SND_SOC_DAPM_POST_PMD:
  2027. wcd938x_micbias_control(component, micb_num,
  2028. MICB_PULLUP_DISABLE, true);
  2029. break;
  2030. };
  2031. return 0;
  2032. }
  2033. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2034. struct snd_kcontrol *kcontrol,
  2035. int event)
  2036. {
  2037. return __wcd938x_codec_enable_micbias_pullup(w, event);
  2038. }
  2039. static int wcd938x_wakeup(void *handle, bool enable)
  2040. {
  2041. struct wcd938x_priv *priv;
  2042. int ret = 0;
  2043. if (!handle) {
  2044. pr_err("%s: NULL handle\n", __func__);
  2045. return -EINVAL;
  2046. }
  2047. priv = (struct wcd938x_priv *)handle;
  2048. if (!priv->tx_swr_dev) {
  2049. pr_err("%s: tx swr dev is NULL\n", __func__);
  2050. return -EINVAL;
  2051. }
  2052. mutex_lock(&priv->wakeup_lock);
  2053. if (enable)
  2054. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2055. else
  2056. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2057. mutex_unlock(&priv->wakeup_lock);
  2058. return ret;
  2059. }
  2060. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2061. struct snd_kcontrol *kcontrol,
  2062. int event)
  2063. {
  2064. int ret = 0;
  2065. struct snd_soc_component *component =
  2066. snd_soc_dapm_to_component(w->dapm);
  2067. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2068. switch (event) {
  2069. case SND_SOC_DAPM_PRE_PMU:
  2070. wcd938x_wakeup(wcd938x, true);
  2071. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2072. wcd938x_wakeup(wcd938x, false);
  2073. break;
  2074. case SND_SOC_DAPM_POST_PMD:
  2075. wcd938x_wakeup(wcd938x, true);
  2076. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2077. wcd938x_wakeup(wcd938x, false);
  2078. break;
  2079. }
  2080. return ret;
  2081. }
  2082. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2083. int micb_num, int req)
  2084. {
  2085. int micb_index = micb_num - 1;
  2086. u16 micb_reg;
  2087. if (NULL == wcd938x) {
  2088. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2089. return -EINVAL;
  2090. }
  2091. switch (micb_num) {
  2092. case MIC_BIAS_1:
  2093. micb_reg = WCD938X_ANA_MICB1;
  2094. break;
  2095. case MIC_BIAS_2:
  2096. micb_reg = WCD938X_ANA_MICB2;
  2097. break;
  2098. case MIC_BIAS_3:
  2099. micb_reg = WCD938X_ANA_MICB3;
  2100. break;
  2101. case MIC_BIAS_4:
  2102. micb_reg = WCD938X_ANA_MICB4;
  2103. break;
  2104. default:
  2105. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2106. return -EINVAL;
  2107. };
  2108. mutex_lock(&wcd938x->micb_lock);
  2109. switch (req) {
  2110. case MICB_ENABLE:
  2111. wcd938x->micb_ref[micb_index]++;
  2112. if (wcd938x->micb_ref[micb_index] == 1) {
  2113. regmap_update_bits(wcd938x->regmap,
  2114. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2115. regmap_update_bits(wcd938x->regmap,
  2116. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2117. regmap_update_bits(wcd938x->regmap,
  2118. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2119. regmap_update_bits(wcd938x->regmap,
  2120. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2121. regmap_update_bits(wcd938x->regmap,
  2122. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2123. regmap_update_bits(wcd938x->regmap,
  2124. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2125. regmap_update_bits(wcd938x->regmap,
  2126. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2127. regmap_update_bits(wcd938x->regmap,
  2128. micb_reg, 0xC0, 0x40);
  2129. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2130. }
  2131. break;
  2132. case MICB_PULLUP_ENABLE:
  2133. wcd938x->pullup_ref[micb_index]++;
  2134. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2135. (wcd938x->micb_ref[micb_index] == 0))
  2136. regmap_update_bits(wcd938x->regmap, micb_reg,
  2137. 0xC0, 0x80);
  2138. break;
  2139. case MICB_PULLUP_DISABLE:
  2140. if (wcd938x->pullup_ref[micb_index] > 0)
  2141. wcd938x->pullup_ref[micb_index]--;
  2142. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2143. (wcd938x->micb_ref[micb_index] == 0))
  2144. regmap_update_bits(wcd938x->regmap, micb_reg,
  2145. 0xC0, 0x00);
  2146. break;
  2147. case MICB_DISABLE:
  2148. if (wcd938x->micb_ref[micb_index] > 0)
  2149. wcd938x->micb_ref[micb_index]--;
  2150. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2151. (wcd938x->pullup_ref[micb_index] > 0))
  2152. regmap_update_bits(wcd938x->regmap, micb_reg,
  2153. 0xC0, 0x80);
  2154. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2155. (wcd938x->pullup_ref[micb_index] == 0))
  2156. regmap_update_bits(wcd938x->regmap, micb_reg,
  2157. 0xC0, 0x00);
  2158. break;
  2159. };
  2160. mutex_unlock(&wcd938x->micb_lock);
  2161. return 0;
  2162. }
  2163. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2164. int event, int micb_num)
  2165. {
  2166. struct wcd938x_priv *wcd938x_priv = NULL;
  2167. if(NULL == component) {
  2168. pr_err("%s: wcd938x component is NULL\n", __func__);
  2169. return -EINVAL;
  2170. }
  2171. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2172. pr_err("%s: invalid event: %d\n", __func__, event);
  2173. return -EINVAL;
  2174. }
  2175. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2176. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2177. return -EINVAL;
  2178. }
  2179. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2180. switch (event) {
  2181. case SND_SOC_DAPM_PRE_PMU:
  2182. wcd938x_wakeup(wcd938x_priv, true);
  2183. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2184. wcd938x_wakeup(wcd938x_priv, false);
  2185. break;
  2186. case SND_SOC_DAPM_POST_PMD:
  2187. wcd938x_wakeup(wcd938x_priv, true);
  2188. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2189. wcd938x_wakeup(wcd938x_priv, false);
  2190. break;
  2191. }
  2192. return 0;
  2193. }
  2194. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2195. static inline int wcd938x_tx_path_get(const char *wname,
  2196. unsigned int *path_num)
  2197. {
  2198. int ret = 0;
  2199. char *widget_name = NULL;
  2200. char *w_name = NULL;
  2201. char *path_num_char = NULL;
  2202. char *path_name = NULL;
  2203. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2204. if (!widget_name)
  2205. return -EINVAL;
  2206. w_name = widget_name;
  2207. path_name = strsep(&widget_name, " ");
  2208. if (!path_name) {
  2209. pr_err("%s: Invalid widget name = %s\n",
  2210. __func__, widget_name);
  2211. ret = -EINVAL;
  2212. goto err;
  2213. }
  2214. path_num_char = strpbrk(path_name, "0123");
  2215. if (!path_num_char) {
  2216. pr_err("%s: tx path index not found\n",
  2217. __func__);
  2218. ret = -EINVAL;
  2219. goto err;
  2220. }
  2221. ret = kstrtouint(path_num_char, 10, path_num);
  2222. if (ret < 0)
  2223. pr_err("%s: Invalid tx path = %s\n",
  2224. __func__, w_name);
  2225. err:
  2226. kfree(w_name);
  2227. return ret;
  2228. }
  2229. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2230. struct snd_ctl_elem_value *ucontrol)
  2231. {
  2232. struct snd_soc_component *component =
  2233. snd_soc_kcontrol_component(kcontrol);
  2234. struct wcd938x_priv *wcd938x = NULL;
  2235. int ret = 0;
  2236. unsigned int path = 0;
  2237. if (!component)
  2238. return -EINVAL;
  2239. wcd938x = snd_soc_component_get_drvdata(component);
  2240. if (!wcd938x)
  2241. return -EINVAL;
  2242. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2243. if (ret < 0)
  2244. return ret;
  2245. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2246. return 0;
  2247. }
  2248. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2249. struct snd_ctl_elem_value *ucontrol)
  2250. {
  2251. struct snd_soc_component *component =
  2252. snd_soc_kcontrol_component(kcontrol);
  2253. struct wcd938x_priv *wcd938x = NULL;
  2254. u32 mode_val;
  2255. unsigned int path = 0;
  2256. int ret = 0;
  2257. if (!component)
  2258. return -EINVAL;
  2259. wcd938x = snd_soc_component_get_drvdata(component);
  2260. if (!wcd938x)
  2261. return -EINVAL;
  2262. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2263. if (ret)
  2264. return ret;
  2265. mode_val = ucontrol->value.enumerated.item[0];
  2266. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2267. wcd938x->tx_mode[path] = mode_val;
  2268. return 0;
  2269. }
  2270. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2271. struct snd_ctl_elem_value *ucontrol)
  2272. {
  2273. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2274. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2275. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2276. return 0;
  2277. }
  2278. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2279. struct snd_ctl_elem_value *ucontrol)
  2280. {
  2281. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2282. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2283. u32 mode_val;
  2284. mode_val = ucontrol->value.enumerated.item[0];
  2285. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2286. if (wcd938x->variant == WCD9380) {
  2287. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2288. dev_info(component->dev,
  2289. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2290. __func__);
  2291. mode_val = CLS_H_ULP;
  2292. }
  2293. }
  2294. if (mode_val == CLS_H_NORMAL) {
  2295. dev_info(component->dev,
  2296. "%s:Invalid HPH Mode, default to class_AB\n",
  2297. __func__);
  2298. mode_val = CLS_H_ULP;
  2299. }
  2300. wcd938x->hph_mode = mode_val;
  2301. return 0;
  2302. }
  2303. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2304. struct snd_ctl_elem_value *ucontrol)
  2305. {
  2306. u8 ear_pa_gain = 0;
  2307. struct snd_soc_component *component =
  2308. snd_soc_kcontrol_component(kcontrol);
  2309. ear_pa_gain = snd_soc_component_read32(component,
  2310. WCD938X_ANA_EAR_COMPANDER_CTL);
  2311. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2312. ucontrol->value.integer.value[0] = ear_pa_gain;
  2313. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2314. ear_pa_gain);
  2315. return 0;
  2316. }
  2317. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2318. struct snd_ctl_elem_value *ucontrol)
  2319. {
  2320. u8 ear_pa_gain = 0;
  2321. struct snd_soc_component *component =
  2322. snd_soc_kcontrol_component(kcontrol);
  2323. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2324. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2325. __func__, ucontrol->value.integer.value[0]);
  2326. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2327. if (!wcd938x->comp1_enable) {
  2328. snd_soc_component_update_bits(component,
  2329. WCD938X_ANA_EAR_COMPANDER_CTL,
  2330. 0x7C, ear_pa_gain);
  2331. }
  2332. return 0;
  2333. }
  2334. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2335. struct snd_ctl_elem_value *ucontrol)
  2336. {
  2337. struct snd_soc_component *component =
  2338. snd_soc_kcontrol_component(kcontrol);
  2339. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2340. bool hphr;
  2341. struct soc_multi_mixer_control *mc;
  2342. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2343. hphr = mc->shift;
  2344. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2345. wcd938x->comp1_enable;
  2346. return 0;
  2347. }
  2348. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2349. struct snd_ctl_elem_value *ucontrol)
  2350. {
  2351. struct snd_soc_component *component =
  2352. snd_soc_kcontrol_component(kcontrol);
  2353. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2354. int value = ucontrol->value.integer.value[0];
  2355. bool hphr;
  2356. struct soc_multi_mixer_control *mc;
  2357. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2358. hphr = mc->shift;
  2359. if (hphr)
  2360. wcd938x->comp2_enable = value;
  2361. else
  2362. wcd938x->comp1_enable = value;
  2363. return 0;
  2364. }
  2365. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2366. struct snd_kcontrol *kcontrol,
  2367. int event)
  2368. {
  2369. struct snd_soc_component *component =
  2370. snd_soc_dapm_to_component(w->dapm);
  2371. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2372. struct wcd938x_pdata *pdata = NULL;
  2373. int ret = 0;
  2374. pdata = dev_get_platdata(wcd938x->dev);
  2375. if (!pdata) {
  2376. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2377. return -EINVAL;
  2378. }
  2379. if (!msm_cdc_is_ondemand_supply(wcd938x->dev,
  2380. wcd938x->supplies,
  2381. pdata->regulator,
  2382. pdata->num_supplies,
  2383. "cdc-vdd-buck"))
  2384. return 0;
  2385. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2386. w->name, event);
  2387. switch (event) {
  2388. case SND_SOC_DAPM_PRE_PMU:
  2389. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  2390. dev_dbg(component->dev,
  2391. "%s: buck already in enabled state\n",
  2392. __func__);
  2393. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2394. return 0;
  2395. }
  2396. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  2397. wcd938x->supplies,
  2398. pdata->regulator,
  2399. pdata->num_supplies,
  2400. "cdc-vdd-buck");
  2401. if (ret == -EINVAL) {
  2402. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2403. __func__);
  2404. return ret;
  2405. }
  2406. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2407. /*
  2408. * 200us sleep is required after LDO is enabled as per
  2409. * HW requirement
  2410. */
  2411. usleep_range(200, 250);
  2412. break;
  2413. case SND_SOC_DAPM_POST_PMD:
  2414. set_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2415. break;
  2416. }
  2417. return 0;
  2418. }
  2419. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2420. struct snd_ctl_elem_value *ucontrol)
  2421. {
  2422. struct snd_soc_component *component =
  2423. snd_soc_kcontrol_component(kcontrol);
  2424. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2425. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2426. return 0;
  2427. }
  2428. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2429. struct snd_ctl_elem_value *ucontrol)
  2430. {
  2431. struct snd_soc_component *component =
  2432. snd_soc_kcontrol_component(kcontrol);
  2433. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2434. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2435. return 0;
  2436. }
  2437. const char * const tx_master_ch_text[] = {
  2438. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2439. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2440. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2441. "SWRM_PCM_IN",
  2442. };
  2443. const struct soc_enum tx_master_ch_enum =
  2444. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2445. tx_master_ch_text);
  2446. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2447. {
  2448. u8 ch_type = 0;
  2449. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2450. ch_type = ADC1;
  2451. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2452. ch_type = ADC2;
  2453. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2454. ch_type = ADC3;
  2455. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2456. ch_type = ADC4;
  2457. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2458. ch_type = DMIC0;
  2459. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2460. ch_type = DMIC1;
  2461. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2462. ch_type = MBHC;
  2463. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2464. ch_type = DMIC2;
  2465. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2466. ch_type = DMIC3;
  2467. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2468. ch_type = DMIC4;
  2469. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2470. ch_type = DMIC5;
  2471. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2472. ch_type = DMIC6;
  2473. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2474. ch_type = DMIC7;
  2475. else
  2476. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2477. if (ch_type)
  2478. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2479. else
  2480. *ch_idx = -EINVAL;
  2481. }
  2482. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2483. struct snd_ctl_elem_value *ucontrol)
  2484. {
  2485. struct snd_soc_component *component =
  2486. snd_soc_kcontrol_component(kcontrol);
  2487. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2488. int slave_ch_idx;
  2489. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2490. if (slave_ch_idx != -EINVAL)
  2491. ucontrol->value.integer.value[0] =
  2492. wcd938x_slave_get_master_ch_val(
  2493. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2494. return 0;
  2495. }
  2496. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2497. struct snd_ctl_elem_value *ucontrol)
  2498. {
  2499. struct snd_soc_component *component =
  2500. snd_soc_kcontrol_component(kcontrol);
  2501. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2502. int slave_ch_idx;
  2503. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2504. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2505. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2506. __func__, ucontrol->value.enumerated.item[0]);
  2507. if (slave_ch_idx != -EINVAL)
  2508. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2509. wcd938x_slave_get_master_ch(
  2510. ucontrol->value.enumerated.item[0]);
  2511. return 0;
  2512. }
  2513. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2514. struct snd_ctl_elem_value *ucontrol)
  2515. {
  2516. struct snd_soc_component *component =
  2517. snd_soc_kcontrol_component(kcontrol);
  2518. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2519. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2520. return 0;
  2521. }
  2522. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2523. struct snd_ctl_elem_value *ucontrol)
  2524. {
  2525. struct snd_soc_component *component =
  2526. snd_soc_kcontrol_component(kcontrol);
  2527. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2528. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2529. return 0;
  2530. }
  2531. static const char * const tx_mode_mux_text_wcd9380[] = {
  2532. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2533. };
  2534. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2535. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2536. tx_mode_mux_text_wcd9380);
  2537. static const char * const tx_mode_mux_text[] = {
  2538. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2539. "ADC_ULP1", "ADC_ULP2",
  2540. };
  2541. static const struct soc_enum tx_mode_mux_enum =
  2542. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2543. tx_mode_mux_text);
  2544. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2545. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2546. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2547. "CLS_AB_LOHIFI",
  2548. };
  2549. static const char * const wcd938x_ear_pa_gain_text[] = {
  2550. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2551. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2552. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2553. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2554. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2555. };
  2556. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2557. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2558. rx_hph_mode_mux_text_wcd9380);
  2559. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2560. wcd938x_ear_pa_gain_text);
  2561. static const char * const rx_hph_mode_mux_text[] = {
  2562. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2563. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2564. };
  2565. static const struct soc_enum rx_hph_mode_mux_enum =
  2566. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2567. rx_hph_mode_mux_text);
  2568. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2569. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2570. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2571. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2572. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2573. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2574. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2575. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2576. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2577. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2578. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2579. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2580. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2581. };
  2582. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2583. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2584. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2585. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2586. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2587. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2588. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2589. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2590. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2591. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2592. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2593. };
  2594. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2595. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2596. wcd938x_get_compander, wcd938x_set_compander),
  2597. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2598. wcd938x_get_compander, wcd938x_set_compander),
  2599. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2600. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2601. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2602. wcd938x_bcs_get, wcd938x_bcs_put),
  2603. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2604. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2605. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2606. analog_gain),
  2607. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2608. analog_gain),
  2609. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2610. analog_gain),
  2611. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2612. analog_gain),
  2613. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2614. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2615. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2616. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2617. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2618. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2619. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2620. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2621. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2622. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2623. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2624. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2625. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2626. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2627. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2628. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2629. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2630. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2631. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2632. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2633. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2634. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2635. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2636. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2637. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2638. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2639. };
  2640. static const struct snd_kcontrol_new adc1_switch[] = {
  2641. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2642. };
  2643. static const struct snd_kcontrol_new adc2_switch[] = {
  2644. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2645. };
  2646. static const struct snd_kcontrol_new adc3_switch[] = {
  2647. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2648. };
  2649. static const struct snd_kcontrol_new adc4_switch[] = {
  2650. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2651. };
  2652. static const struct snd_kcontrol_new dmic1_switch[] = {
  2653. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2654. };
  2655. static const struct snd_kcontrol_new dmic2_switch[] = {
  2656. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2657. };
  2658. static const struct snd_kcontrol_new dmic3_switch[] = {
  2659. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2660. };
  2661. static const struct snd_kcontrol_new dmic4_switch[] = {
  2662. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2663. };
  2664. static const struct snd_kcontrol_new dmic5_switch[] = {
  2665. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2666. };
  2667. static const struct snd_kcontrol_new dmic6_switch[] = {
  2668. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2669. };
  2670. static const struct snd_kcontrol_new dmic7_switch[] = {
  2671. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2672. };
  2673. static const struct snd_kcontrol_new dmic8_switch[] = {
  2674. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2675. };
  2676. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2677. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2678. };
  2679. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2680. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2681. };
  2682. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2683. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2684. };
  2685. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2686. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2687. };
  2688. static const char * const adc2_mux_text[] = {
  2689. "INP2", "INP3"
  2690. };
  2691. static const struct soc_enum adc2_enum =
  2692. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2693. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2694. static const struct snd_kcontrol_new tx_adc2_mux =
  2695. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2696. static const char * const adc3_mux_text[] = {
  2697. "INP4", "INP6"
  2698. };
  2699. static const struct soc_enum adc3_enum =
  2700. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2701. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2702. static const struct snd_kcontrol_new tx_adc3_mux =
  2703. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2704. static const char * const adc4_mux_text[] = {
  2705. "INP5", "INP7"
  2706. };
  2707. static const struct soc_enum adc4_enum =
  2708. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2709. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2710. static const struct snd_kcontrol_new tx_adc4_mux =
  2711. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2712. static const char * const rdac3_mux_text[] = {
  2713. "RX1", "RX3"
  2714. };
  2715. static const char * const hdr12_mux_text[] = {
  2716. "NO_HDR12", "HDR12"
  2717. };
  2718. static const struct soc_enum hdr12_enum =
  2719. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2720. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2721. static const struct snd_kcontrol_new tx_hdr12_mux =
  2722. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2723. static const char * const hdr34_mux_text[] = {
  2724. "NO_HDR34", "HDR34"
  2725. };
  2726. static const struct soc_enum hdr34_enum =
  2727. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2728. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2729. static const struct snd_kcontrol_new tx_hdr34_mux =
  2730. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2731. static const struct soc_enum rdac3_enum =
  2732. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2733. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2734. static const struct snd_kcontrol_new rx_rdac3_mux =
  2735. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2736. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2737. /*input widgets*/
  2738. SND_SOC_DAPM_INPUT("AMIC1"),
  2739. SND_SOC_DAPM_INPUT("AMIC2"),
  2740. SND_SOC_DAPM_INPUT("AMIC3"),
  2741. SND_SOC_DAPM_INPUT("AMIC4"),
  2742. SND_SOC_DAPM_INPUT("AMIC5"),
  2743. SND_SOC_DAPM_INPUT("AMIC6"),
  2744. SND_SOC_DAPM_INPUT("AMIC7"),
  2745. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2746. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2747. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2748. /*
  2749. * These dummy widgets are null connected to WCD938x dapm input and
  2750. * output widgets which are not actual path endpoints. This ensures
  2751. * dapm doesnt set these dapm input and output widgets as endpoints.
  2752. */
  2753. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2754. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2755. /*tx widgets*/
  2756. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2757. wcd938x_codec_enable_adc,
  2758. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2759. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2760. wcd938x_codec_enable_adc,
  2761. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2762. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2763. wcd938x_codec_enable_adc,
  2764. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2765. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2766. wcd938x_codec_enable_adc,
  2767. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2768. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2769. wcd938x_codec_enable_dmic,
  2770. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2771. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2772. wcd938x_codec_enable_dmic,
  2773. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2774. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2775. wcd938x_codec_enable_dmic,
  2776. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2777. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2778. wcd938x_codec_enable_dmic,
  2779. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2780. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2781. wcd938x_codec_enable_dmic,
  2782. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2783. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2784. wcd938x_codec_enable_dmic,
  2785. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2786. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2787. wcd938x_codec_enable_dmic,
  2788. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2789. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2790. wcd938x_codec_enable_dmic,
  2791. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2792. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2793. NULL, 0, wcd938x_enable_req,
  2794. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2795. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2796. NULL, 0, wcd938x_enable_req,
  2797. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2798. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2799. NULL, 0, wcd938x_enable_req,
  2800. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2801. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2802. NULL, 0, wcd938x_enable_req,
  2803. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2804. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2805. &tx_adc2_mux),
  2806. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2807. &tx_adc3_mux),
  2808. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2809. &tx_adc4_mux),
  2810. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2811. &tx_hdr12_mux),
  2812. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2813. &tx_hdr34_mux),
  2814. /*tx mixers*/
  2815. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  2816. adc1_switch, ARRAY_SIZE(adc1_switch),
  2817. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2818. SND_SOC_DAPM_POST_PMD),
  2819. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  2820. adc2_switch, ARRAY_SIZE(adc2_switch),
  2821. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2822. SND_SOC_DAPM_POST_PMD),
  2823. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  2824. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2825. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2826. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  2827. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2828. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2829. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  2830. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2831. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2832. SND_SOC_DAPM_POST_PMD),
  2833. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  2834. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2835. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2836. SND_SOC_DAPM_POST_PMD),
  2837. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  2838. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2839. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2840. SND_SOC_DAPM_POST_PMD),
  2841. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  2842. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2843. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2844. SND_SOC_DAPM_POST_PMD),
  2845. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  2846. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2847. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2848. SND_SOC_DAPM_POST_PMD),
  2849. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  2850. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2851. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2852. SND_SOC_DAPM_POST_PMD),
  2853. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  2854. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2855. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2856. SND_SOC_DAPM_POST_PMD),
  2857. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  2858. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2859. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2860. SND_SOC_DAPM_POST_PMD),
  2861. /* micbias widgets*/
  2862. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2863. wcd938x_codec_enable_micbias,
  2864. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2865. SND_SOC_DAPM_POST_PMD),
  2866. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2867. wcd938x_codec_enable_micbias,
  2868. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2869. SND_SOC_DAPM_POST_PMD),
  2870. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2871. wcd938x_codec_enable_micbias,
  2872. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2873. SND_SOC_DAPM_POST_PMD),
  2874. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2875. wcd938x_codec_enable_micbias,
  2876. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2877. SND_SOC_DAPM_POST_PMD),
  2878. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2879. wcd938x_codec_force_enable_micbias,
  2880. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2881. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2882. wcd938x_codec_force_enable_micbias,
  2883. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2884. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2885. wcd938x_codec_force_enable_micbias,
  2886. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2887. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2888. wcd938x_codec_force_enable_micbias,
  2889. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2890. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2891. wcd938x_codec_enable_vdd_buck,
  2892. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2893. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2894. wcd938x_enable_clsh,
  2895. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2896. /*rx widgets*/
  2897. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2898. wcd938x_codec_enable_ear_pa,
  2899. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2900. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2901. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2902. wcd938x_codec_enable_aux_pa,
  2903. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2904. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2905. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2906. wcd938x_codec_enable_hphl_pa,
  2907. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2908. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2909. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2910. wcd938x_codec_enable_hphr_pa,
  2911. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2912. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2913. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2914. wcd938x_codec_hphl_dac_event,
  2915. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2916. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2917. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2918. wcd938x_codec_hphr_dac_event,
  2919. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2920. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2921. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2922. wcd938x_codec_ear_dac_event,
  2923. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2924. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2925. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2926. wcd938x_codec_aux_dac_event,
  2927. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2928. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2929. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2930. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2931. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2932. SND_SOC_DAPM_POST_PMD),
  2933. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2934. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2935. SND_SOC_DAPM_POST_PMD),
  2936. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2937. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2938. SND_SOC_DAPM_POST_PMD),
  2939. /* rx mixer widgets*/
  2940. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2941. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2942. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2943. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2944. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2945. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2946. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2947. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2948. /*output widgets tx*/
  2949. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2950. /*output widgets rx*/
  2951. SND_SOC_DAPM_OUTPUT("EAR"),
  2952. SND_SOC_DAPM_OUTPUT("AUX"),
  2953. SND_SOC_DAPM_OUTPUT("HPHL"),
  2954. SND_SOC_DAPM_OUTPUT("HPHR"),
  2955. /* micbias pull up widgets*/
  2956. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2957. wcd938x_codec_enable_micbias_pullup,
  2958. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2959. SND_SOC_DAPM_POST_PMD),
  2960. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2961. wcd938x_codec_enable_micbias_pullup,
  2962. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2963. SND_SOC_DAPM_POST_PMD),
  2964. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2965. wcd938x_codec_enable_micbias_pullup,
  2966. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2967. SND_SOC_DAPM_POST_PMD),
  2968. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2969. wcd938x_codec_enable_micbias_pullup,
  2970. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2971. SND_SOC_DAPM_POST_PMD),
  2972. };
  2973. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2974. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2975. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2976. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2977. {"ADC1 REQ", NULL, "ADC1"},
  2978. {"ADC1", NULL, "AMIC1"},
  2979. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2980. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2981. {"ADC2 REQ", NULL, "ADC2"},
  2982. {"ADC2", NULL, "HDR12 MUX"},
  2983. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2984. {"HDR12 MUX", "HDR12", "AMIC1"},
  2985. {"ADC2 MUX", "INP3", "AMIC3"},
  2986. {"ADC2 MUX", "INP2", "AMIC2"},
  2987. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2988. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2989. {"ADC3 REQ", NULL, "ADC3"},
  2990. {"ADC3", NULL, "HDR34 MUX"},
  2991. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2992. {"HDR34 MUX", "HDR34", "AMIC5"},
  2993. {"ADC3 MUX", "INP4", "AMIC4"},
  2994. {"ADC3 MUX", "INP6", "AMIC6"},
  2995. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  2996. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2997. {"ADC4 REQ", NULL, "ADC4"},
  2998. {"ADC4", NULL, "ADC4 MUX"},
  2999. {"ADC4 MUX", "INP5", "AMIC5"},
  3000. {"ADC4 MUX", "INP7", "AMIC7"},
  3001. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3002. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3003. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3004. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3005. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3006. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3007. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3008. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3009. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3010. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3011. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3012. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3013. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3014. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3015. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3016. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3017. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3018. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3019. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3020. {"RX1", NULL, "IN1_HPHL"},
  3021. {"RDAC1", NULL, "RX1"},
  3022. {"HPHL_RDAC", "Switch", "RDAC1"},
  3023. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3024. {"HPHL", NULL, "HPHL PGA"},
  3025. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3026. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3027. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3028. {"RX2", NULL, "IN2_HPHR"},
  3029. {"RDAC2", NULL, "RX2"},
  3030. {"HPHR_RDAC", "Switch", "RDAC2"},
  3031. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3032. {"HPHR", NULL, "HPHR PGA"},
  3033. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  3034. {"IN3_AUX", NULL, "VDD_BUCK"},
  3035. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3036. {"RX3", NULL, "IN3_AUX"},
  3037. {"RDAC4", NULL, "RX3"},
  3038. {"AUX_RDAC", "Switch", "RDAC4"},
  3039. {"AUX PGA", NULL, "AUX_RDAC"},
  3040. {"AUX", NULL, "AUX PGA"},
  3041. {"RDAC3_MUX", "RX3", "RX3"},
  3042. {"RDAC3_MUX", "RX1", "RX1"},
  3043. {"RDAC3", NULL, "RDAC3_MUX"},
  3044. {"EAR_RDAC", "Switch", "RDAC3"},
  3045. {"EAR PGA", NULL, "EAR_RDAC"},
  3046. {"EAR", NULL, "EAR PGA"},
  3047. };
  3048. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  3049. void *file_private_data,
  3050. struct file *file,
  3051. char __user *buf, size_t count,
  3052. loff_t pos)
  3053. {
  3054. struct wcd938x_priv *priv;
  3055. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  3056. int len = 0;
  3057. priv = (struct wcd938x_priv *) entry->private_data;
  3058. if (!priv) {
  3059. pr_err("%s: wcd938x priv is null\n", __func__);
  3060. return -EINVAL;
  3061. }
  3062. switch (priv->version) {
  3063. case WCD938X_VERSION_1_0:
  3064. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  3065. break;
  3066. default:
  3067. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3068. }
  3069. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3070. }
  3071. static struct snd_info_entry_ops wcd938x_info_ops = {
  3072. .read = wcd938x_version_read,
  3073. };
  3074. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  3075. void *file_private_data,
  3076. struct file *file,
  3077. char __user *buf, size_t count,
  3078. loff_t pos)
  3079. {
  3080. struct wcd938x_priv *priv;
  3081. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  3082. int len = 0;
  3083. priv = (struct wcd938x_priv *) entry->private_data;
  3084. if (!priv) {
  3085. pr_err("%s: wcd938x priv is null\n", __func__);
  3086. return -EINVAL;
  3087. }
  3088. switch (priv->variant) {
  3089. case WCD9380:
  3090. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  3091. break;
  3092. case WCD9385:
  3093. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  3094. break;
  3095. default:
  3096. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3097. }
  3098. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3099. }
  3100. static struct snd_info_entry_ops wcd938x_variant_ops = {
  3101. .read = wcd938x_variant_read,
  3102. };
  3103. /*
  3104. * wcd938x_get_codec_variant
  3105. * @component: component instance
  3106. *
  3107. * Return: codec variant or -EINVAL in error.
  3108. */
  3109. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  3110. {
  3111. struct wcd938x_priv *priv = NULL;
  3112. if (!component)
  3113. return -EINVAL;
  3114. priv = snd_soc_component_get_drvdata(component);
  3115. if (!priv) {
  3116. dev_err(component->dev,
  3117. "%s:wcd938x not probed\n", __func__);
  3118. return 0;
  3119. }
  3120. return priv->variant;
  3121. }
  3122. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3123. /*
  3124. * wcd938x_info_create_codec_entry - creates wcd938x module
  3125. * @codec_root: The parent directory
  3126. * @component: component instance
  3127. *
  3128. * Creates wcd938x module, variant and version entry under the given
  3129. * parent directory.
  3130. *
  3131. * Return: 0 on success or negative error code on failure.
  3132. */
  3133. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3134. struct snd_soc_component *component)
  3135. {
  3136. struct snd_info_entry *version_entry;
  3137. struct snd_info_entry *variant_entry;
  3138. struct wcd938x_priv *priv;
  3139. struct snd_soc_card *card;
  3140. if (!codec_root || !component)
  3141. return -EINVAL;
  3142. priv = snd_soc_component_get_drvdata(component);
  3143. if (priv->entry) {
  3144. dev_dbg(priv->dev,
  3145. "%s:wcd938x module already created\n", __func__);
  3146. return 0;
  3147. }
  3148. card = component->card;
  3149. priv->entry = snd_info_create_module_entry(codec_root->module,
  3150. "wcd938x", codec_root);
  3151. if (!priv->entry) {
  3152. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3153. __func__);
  3154. return -ENOMEM;
  3155. }
  3156. priv->entry->mode = S_IFDIR | 0555;
  3157. if (snd_info_register(priv->entry) < 0) {
  3158. snd_info_free_entry(priv->entry);
  3159. return -ENOMEM;
  3160. }
  3161. version_entry = snd_info_create_card_entry(card->snd_card,
  3162. "version",
  3163. priv->entry);
  3164. if (!version_entry) {
  3165. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3166. __func__);
  3167. snd_info_free_entry(priv->entry);
  3168. return -ENOMEM;
  3169. }
  3170. version_entry->private_data = priv;
  3171. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3172. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3173. version_entry->c.ops = &wcd938x_info_ops;
  3174. if (snd_info_register(version_entry) < 0) {
  3175. snd_info_free_entry(version_entry);
  3176. snd_info_free_entry(priv->entry);
  3177. return -ENOMEM;
  3178. }
  3179. priv->version_entry = version_entry;
  3180. variant_entry = snd_info_create_card_entry(card->snd_card,
  3181. "variant",
  3182. priv->entry);
  3183. if (!variant_entry) {
  3184. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3185. __func__);
  3186. snd_info_free_entry(version_entry);
  3187. snd_info_free_entry(priv->entry);
  3188. return -ENOMEM;
  3189. }
  3190. variant_entry->private_data = priv;
  3191. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3192. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3193. variant_entry->c.ops = &wcd938x_variant_ops;
  3194. if (snd_info_register(variant_entry) < 0) {
  3195. snd_info_free_entry(variant_entry);
  3196. snd_info_free_entry(version_entry);
  3197. snd_info_free_entry(priv->entry);
  3198. return -ENOMEM;
  3199. }
  3200. priv->variant_entry = variant_entry;
  3201. return 0;
  3202. }
  3203. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3204. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3205. struct wcd938x_pdata *pdata)
  3206. {
  3207. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3208. int rc = 0;
  3209. if (!pdata) {
  3210. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3211. return -ENODEV;
  3212. }
  3213. /* set micbias voltage */
  3214. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3215. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3216. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3217. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3218. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3219. vout_ctl_4 < 0) {
  3220. rc = -EINVAL;
  3221. goto done;
  3222. }
  3223. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3224. vout_ctl_1);
  3225. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3226. vout_ctl_2);
  3227. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3228. vout_ctl_3);
  3229. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3230. vout_ctl_4);
  3231. done:
  3232. return rc;
  3233. }
  3234. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3235. {
  3236. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3237. struct snd_soc_dapm_context *dapm =
  3238. snd_soc_component_get_dapm(component);
  3239. int variant;
  3240. int ret = -EINVAL;
  3241. dev_info(component->dev, "%s()\n", __func__);
  3242. wcd938x = snd_soc_component_get_drvdata(component);
  3243. if (!wcd938x)
  3244. return -EINVAL;
  3245. wcd938x->component = component;
  3246. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3247. variant = (snd_soc_component_read32(component,
  3248. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3249. wcd938x->variant = variant;
  3250. wcd938x->fw_data = devm_kzalloc(component->dev,
  3251. sizeof(*(wcd938x->fw_data)),
  3252. GFP_KERNEL);
  3253. if (!wcd938x->fw_data) {
  3254. dev_err(component->dev, "Failed to allocate fw_data\n");
  3255. ret = -ENOMEM;
  3256. goto err;
  3257. }
  3258. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3259. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3260. WCD9XXX_CODEC_HWDEP_NODE, component);
  3261. if (ret < 0) {
  3262. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3263. goto err_hwdep;
  3264. }
  3265. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3266. if (ret) {
  3267. pr_err("%s: mbhc initialization failed\n", __func__);
  3268. goto err_hwdep;
  3269. }
  3270. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Playback");
  3271. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Capture");
  3272. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3273. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3274. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3275. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3276. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3277. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3278. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3279. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3280. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3281. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3282. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3283. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3284. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3285. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3286. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3287. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3288. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3289. snd_soc_dapm_sync(dapm);
  3290. wcd_cls_h_init(&wcd938x->clsh_info);
  3291. wcd938x_init_reg(component);
  3292. if (wcd938x->variant == WCD9380) {
  3293. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3294. ARRAY_SIZE(wcd9380_snd_controls));
  3295. if (ret < 0) {
  3296. dev_err(component->dev,
  3297. "%s: Failed to add snd ctrls for variant: %d\n",
  3298. __func__, wcd938x->variant);
  3299. goto err_hwdep;
  3300. }
  3301. }
  3302. if (wcd938x->variant == WCD9385) {
  3303. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3304. ARRAY_SIZE(wcd9385_snd_controls));
  3305. if (ret < 0) {
  3306. dev_err(component->dev,
  3307. "%s: Failed to add snd ctrls for variant: %d\n",
  3308. __func__, wcd938x->variant);
  3309. goto err_hwdep;
  3310. }
  3311. }
  3312. wcd938x->version = WCD938X_VERSION_1_0;
  3313. /* Register event notifier */
  3314. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3315. if (wcd938x->register_notifier) {
  3316. ret = wcd938x->register_notifier(wcd938x->handle,
  3317. &wcd938x->nblock,
  3318. true);
  3319. if (ret) {
  3320. dev_err(component->dev,
  3321. "%s: Failed to register notifier %d\n",
  3322. __func__, ret);
  3323. return ret;
  3324. }
  3325. }
  3326. wcd938x->dev_up = true;
  3327. return ret;
  3328. err_hwdep:
  3329. wcd938x->fw_data = NULL;
  3330. err:
  3331. return ret;
  3332. }
  3333. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3334. {
  3335. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3336. if (!wcd938x) {
  3337. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3338. __func__);
  3339. return;
  3340. }
  3341. if (wcd938x->register_notifier)
  3342. wcd938x->register_notifier(wcd938x->handle,
  3343. &wcd938x->nblock,
  3344. false);
  3345. }
  3346. static int wcd938x_soc_codec_suspend(struct snd_soc_component *component)
  3347. {
  3348. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3349. if (!wcd938x)
  3350. return 0;
  3351. wcd938x->dapm_bias_off = true;
  3352. return 0;
  3353. }
  3354. static int wcd938x_soc_codec_resume(struct snd_soc_component *component)
  3355. {
  3356. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3357. if (!wcd938x)
  3358. return 0;
  3359. wcd938x->dapm_bias_off = false;
  3360. return 0;
  3361. }
  3362. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3363. .name = WCD938X_DRV_NAME,
  3364. .probe = wcd938x_soc_codec_probe,
  3365. .remove = wcd938x_soc_codec_remove,
  3366. .controls = wcd938x_snd_controls,
  3367. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3368. .dapm_widgets = wcd938x_dapm_widgets,
  3369. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3370. .dapm_routes = wcd938x_audio_map,
  3371. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3372. .suspend = wcd938x_soc_codec_suspend,
  3373. .resume = wcd938x_soc_codec_resume,
  3374. };
  3375. static int wcd938x_reset(struct device *dev)
  3376. {
  3377. struct wcd938x_priv *wcd938x = NULL;
  3378. int rc = 0;
  3379. int value = 0;
  3380. if (!dev)
  3381. return -ENODEV;
  3382. wcd938x = dev_get_drvdata(dev);
  3383. if (!wcd938x)
  3384. return -EINVAL;
  3385. if (!wcd938x->rst_np) {
  3386. dev_err(dev, "%s: reset gpio device node not specified\n",
  3387. __func__);
  3388. return -EINVAL;
  3389. }
  3390. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3391. if (value > 0)
  3392. return 0;
  3393. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3394. if (rc) {
  3395. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3396. __func__);
  3397. return rc;
  3398. }
  3399. /* 20us sleep required after pulling the reset gpio to LOW */
  3400. usleep_range(20, 30);
  3401. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3402. if (rc) {
  3403. dev_err(dev, "%s: wcd active state request fail!\n",
  3404. __func__);
  3405. return rc;
  3406. }
  3407. /* 20us sleep required after pulling the reset gpio to HIGH */
  3408. usleep_range(20, 30);
  3409. return rc;
  3410. }
  3411. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3412. u32 *val)
  3413. {
  3414. int rc = 0;
  3415. rc = of_property_read_u32(dev->of_node, name, val);
  3416. if (rc)
  3417. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3418. __func__, name, dev->of_node->full_name);
  3419. return rc;
  3420. }
  3421. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3422. struct wcd938x_micbias_setting *mb)
  3423. {
  3424. u32 prop_val = 0;
  3425. int rc = 0;
  3426. /* MB1 */
  3427. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3428. NULL)) {
  3429. rc = wcd938x_read_of_property_u32(dev,
  3430. "qcom,cdc-micbias1-mv",
  3431. &prop_val);
  3432. if (!rc)
  3433. mb->micb1_mv = prop_val;
  3434. } else {
  3435. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3436. __func__);
  3437. }
  3438. /* MB2 */
  3439. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3440. NULL)) {
  3441. rc = wcd938x_read_of_property_u32(dev,
  3442. "qcom,cdc-micbias2-mv",
  3443. &prop_val);
  3444. if (!rc)
  3445. mb->micb2_mv = prop_val;
  3446. } else {
  3447. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3448. __func__);
  3449. }
  3450. /* MB3 */
  3451. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3452. NULL)) {
  3453. rc = wcd938x_read_of_property_u32(dev,
  3454. "qcom,cdc-micbias3-mv",
  3455. &prop_val);
  3456. if (!rc)
  3457. mb->micb3_mv = prop_val;
  3458. } else {
  3459. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3460. __func__);
  3461. }
  3462. /* MB4 */
  3463. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3464. NULL)) {
  3465. rc = wcd938x_read_of_property_u32(dev,
  3466. "qcom,cdc-micbias4-mv",
  3467. &prop_val);
  3468. if (!rc)
  3469. mb->micb4_mv = prop_val;
  3470. } else {
  3471. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3472. __func__);
  3473. }
  3474. }
  3475. static int wcd938x_reset_low(struct device *dev)
  3476. {
  3477. struct wcd938x_priv *wcd938x = NULL;
  3478. int rc = 0;
  3479. if (!dev)
  3480. return -ENODEV;
  3481. wcd938x = dev_get_drvdata(dev);
  3482. if (!wcd938x)
  3483. return -EINVAL;
  3484. if (!wcd938x->rst_np) {
  3485. dev_err(dev, "%s: reset gpio device node not specified\n",
  3486. __func__);
  3487. return -EINVAL;
  3488. }
  3489. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3490. if (rc) {
  3491. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3492. __func__);
  3493. return rc;
  3494. }
  3495. /* 20us sleep required after pulling the reset gpio to LOW */
  3496. usleep_range(20, 30);
  3497. return rc;
  3498. }
  3499. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3500. {
  3501. struct wcd938x_pdata *pdata = NULL;
  3502. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3503. GFP_KERNEL);
  3504. if (!pdata)
  3505. return NULL;
  3506. pdata->rst_np = of_parse_phandle(dev->of_node,
  3507. "qcom,wcd-rst-gpio-node", 0);
  3508. if (!pdata->rst_np) {
  3509. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3510. __func__, "qcom,wcd-rst-gpio-node",
  3511. dev->of_node->full_name);
  3512. return NULL;
  3513. }
  3514. /* Parse power supplies */
  3515. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3516. &pdata->num_supplies);
  3517. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3518. dev_err(dev, "%s: no power supplies defined for codec\n",
  3519. __func__);
  3520. return NULL;
  3521. }
  3522. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3523. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3524. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3525. return pdata;
  3526. }
  3527. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3528. {
  3529. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3530. __func__, irq);
  3531. return IRQ_HANDLED;
  3532. }
  3533. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3534. {
  3535. .name = "wcd938x_cdc",
  3536. .playback = {
  3537. .stream_name = "WCD938X_AIF Playback",
  3538. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3539. .formats = WCD938X_FORMATS,
  3540. .rate_max = 192000,
  3541. .rate_min = 8000,
  3542. .channels_min = 1,
  3543. .channels_max = 4,
  3544. },
  3545. .capture = {
  3546. .stream_name = "WCD938X_AIF Capture",
  3547. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3548. .formats = WCD938X_FORMATS,
  3549. .rate_max = 192000,
  3550. .rate_min = 8000,
  3551. .channels_min = 1,
  3552. .channels_max = 4,
  3553. },
  3554. },
  3555. };
  3556. static int wcd938x_bind(struct device *dev)
  3557. {
  3558. int ret = 0, i = 0;
  3559. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3560. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3561. /*
  3562. * Add 5msec delay to provide sufficient time for
  3563. * soundwire auto enumeration of slave devices as
  3564. * as per HW requirement.
  3565. */
  3566. usleep_range(5000, 5010);
  3567. ret = component_bind_all(dev, wcd938x);
  3568. if (ret) {
  3569. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3570. __func__, ret);
  3571. return ret;
  3572. }
  3573. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3574. if (!wcd938x->rx_swr_dev) {
  3575. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3576. __func__);
  3577. ret = -ENODEV;
  3578. goto err;
  3579. }
  3580. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3581. if (!wcd938x->tx_swr_dev) {
  3582. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3583. __func__);
  3584. ret = -ENODEV;
  3585. goto err;
  3586. }
  3587. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3588. &wcd938x_regmap_config);
  3589. if (!wcd938x->regmap) {
  3590. dev_err(dev, "%s: Regmap init failed\n",
  3591. __func__);
  3592. goto err;
  3593. }
  3594. /* Set all interupts as edge triggered */
  3595. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3596. regmap_write(wcd938x->regmap,
  3597. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3598. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3599. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3600. wcd938x->irq_info.codec_name = "WCD938X";
  3601. wcd938x->irq_info.regmap = wcd938x->regmap;
  3602. wcd938x->irq_info.dev = dev;
  3603. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3604. if (ret) {
  3605. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3606. __func__, ret);
  3607. goto err;
  3608. }
  3609. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3610. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3611. if (ret < 0) {
  3612. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3613. goto err_irq;
  3614. }
  3615. /* Request for watchdog interrupt */
  3616. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3617. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3618. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3619. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3620. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3621. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3622. /* Disable watchdog interrupt for HPH and AUX */
  3623. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3624. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3625. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3626. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3627. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3628. if (ret) {
  3629. dev_err(dev, "%s: Codec registration failed\n",
  3630. __func__);
  3631. goto err_irq;
  3632. }
  3633. return ret;
  3634. err_irq:
  3635. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3636. err:
  3637. component_unbind_all(dev, wcd938x);
  3638. return ret;
  3639. }
  3640. static void wcd938x_unbind(struct device *dev)
  3641. {
  3642. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3643. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3644. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3645. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3646. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3647. snd_soc_unregister_component(dev);
  3648. component_unbind_all(dev, wcd938x);
  3649. }
  3650. static const struct of_device_id wcd938x_dt_match[] = {
  3651. { .compatible = "qcom,wcd938x-codec", .data = "wcd938x"},
  3652. {}
  3653. };
  3654. static const struct component_master_ops wcd938x_comp_ops = {
  3655. .bind = wcd938x_bind,
  3656. .unbind = wcd938x_unbind,
  3657. };
  3658. static int wcd938x_compare_of(struct device *dev, void *data)
  3659. {
  3660. return dev->of_node == data;
  3661. }
  3662. static void wcd938x_release_of(struct device *dev, void *data)
  3663. {
  3664. of_node_put(data);
  3665. }
  3666. static int wcd938x_add_slave_components(struct device *dev,
  3667. struct component_match **matchptr)
  3668. {
  3669. struct device_node *np, *rx_node, *tx_node;
  3670. np = dev->of_node;
  3671. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3672. if (!rx_node) {
  3673. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3674. return -ENODEV;
  3675. }
  3676. of_node_get(rx_node);
  3677. component_match_add_release(dev, matchptr,
  3678. wcd938x_release_of,
  3679. wcd938x_compare_of,
  3680. rx_node);
  3681. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3682. if (!tx_node) {
  3683. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3684. return -ENODEV;
  3685. }
  3686. of_node_get(tx_node);
  3687. component_match_add_release(dev, matchptr,
  3688. wcd938x_release_of,
  3689. wcd938x_compare_of,
  3690. tx_node);
  3691. return 0;
  3692. }
  3693. static int wcd938x_probe(struct platform_device *pdev)
  3694. {
  3695. struct component_match *match = NULL;
  3696. struct wcd938x_priv *wcd938x = NULL;
  3697. struct wcd938x_pdata *pdata = NULL;
  3698. struct wcd_ctrl_platform_data *plat_data = NULL;
  3699. struct device *dev = &pdev->dev;
  3700. int ret;
  3701. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3702. GFP_KERNEL);
  3703. if (!wcd938x)
  3704. return -ENOMEM;
  3705. dev_set_drvdata(dev, wcd938x);
  3706. wcd938x->dev = dev;
  3707. pdata = wcd938x_populate_dt_data(dev);
  3708. if (!pdata) {
  3709. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3710. return -EINVAL;
  3711. }
  3712. dev->platform_data = pdata;
  3713. wcd938x->rst_np = pdata->rst_np;
  3714. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3715. pdata->regulator, pdata->num_supplies);
  3716. if (!wcd938x->supplies) {
  3717. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3718. __func__);
  3719. return ret;
  3720. }
  3721. plat_data = dev_get_platdata(dev->parent);
  3722. if (!plat_data) {
  3723. dev_err(dev, "%s: platform data from parent is NULL\n",
  3724. __func__);
  3725. return -EINVAL;
  3726. }
  3727. wcd938x->handle = (void *)plat_data->handle;
  3728. if (!wcd938x->handle) {
  3729. dev_err(dev, "%s: handle is NULL\n", __func__);
  3730. return -EINVAL;
  3731. }
  3732. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3733. if (!wcd938x->update_wcd_event) {
  3734. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3735. __func__);
  3736. return -EINVAL;
  3737. }
  3738. wcd938x->register_notifier = plat_data->register_notifier;
  3739. if (!wcd938x->register_notifier) {
  3740. dev_err(dev, "%s: register_notifier api is null!\n",
  3741. __func__);
  3742. return -EINVAL;
  3743. }
  3744. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3745. pdata->regulator,
  3746. pdata->num_supplies);
  3747. if (ret) {
  3748. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3749. __func__);
  3750. return ret;
  3751. }
  3752. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3753. CODEC_RX);
  3754. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3755. CODEC_TX);
  3756. if (ret) {
  3757. dev_err(dev, "Failed to read port mapping\n");
  3758. goto err;
  3759. }
  3760. mutex_init(&wcd938x->wakeup_lock);
  3761. mutex_init(&wcd938x->micb_lock);
  3762. ret = wcd938x_add_slave_components(dev, &match);
  3763. if (ret)
  3764. goto err_lock_init;
  3765. wcd938x_reset(dev);
  3766. wcd938x->wakeup = wcd938x_wakeup;
  3767. return component_master_add_with_match(dev,
  3768. &wcd938x_comp_ops, match);
  3769. err_lock_init:
  3770. mutex_destroy(&wcd938x->micb_lock);
  3771. mutex_destroy(&wcd938x->wakeup_lock);
  3772. err:
  3773. return ret;
  3774. }
  3775. static int wcd938x_remove(struct platform_device *pdev)
  3776. {
  3777. struct wcd938x_priv *wcd938x = NULL;
  3778. wcd938x = platform_get_drvdata(pdev);
  3779. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3780. mutex_destroy(&wcd938x->micb_lock);
  3781. mutex_destroy(&wcd938x->wakeup_lock);
  3782. dev_set_drvdata(&pdev->dev, NULL);
  3783. return 0;
  3784. }
  3785. #ifdef CONFIG_PM_SLEEP
  3786. static int wcd938x_suspend(struct device *dev)
  3787. {
  3788. struct wcd938x_priv *wcd938x = NULL;
  3789. int ret = 0;
  3790. struct wcd938x_pdata *pdata = NULL;
  3791. if (!dev)
  3792. return -ENODEV;
  3793. wcd938x = dev_get_drvdata(dev);
  3794. if (!wcd938x)
  3795. return -EINVAL;
  3796. pdata = dev_get_platdata(wcd938x->dev);
  3797. if (!pdata) {
  3798. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3799. return -EINVAL;
  3800. }
  3801. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  3802. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  3803. wcd938x->supplies,
  3804. pdata->regulator,
  3805. pdata->num_supplies,
  3806. "cdc-vdd-buck");
  3807. if (ret == -EINVAL) {
  3808. dev_err(dev, "%s: vdd buck is not disabled\n",
  3809. __func__);
  3810. return 0;
  3811. }
  3812. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  3813. }
  3814. if (wcd938x->dapm_bias_off) {
  3815. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  3816. wcd938x->supplies,
  3817. pdata->regulator,
  3818. pdata->num_supplies,
  3819. true);
  3820. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  3821. }
  3822. return 0;
  3823. }
  3824. static int wcd938x_resume(struct device *dev)
  3825. {
  3826. struct wcd938x_priv *wcd938x = NULL;
  3827. struct wcd938x_pdata *pdata = NULL;
  3828. if (!dev)
  3829. return -ENODEV;
  3830. wcd938x = dev_get_drvdata(dev);
  3831. if (!wcd938x)
  3832. return -EINVAL;
  3833. pdata = dev_get_platdata(wcd938x->dev);
  3834. if (!pdata) {
  3835. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3836. return -EINVAL;
  3837. }
  3838. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask)) {
  3839. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  3840. wcd938x->supplies,
  3841. pdata->regulator,
  3842. pdata->num_supplies,
  3843. false);
  3844. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  3845. }
  3846. return 0;
  3847. }
  3848. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3849. .suspend_late = wcd938x_suspend,
  3850. .resume_early = wcd938x_resume,
  3851. };
  3852. #endif
  3853. static struct platform_driver wcd938x_codec_driver = {
  3854. .probe = wcd938x_probe,
  3855. .remove = wcd938x_remove,
  3856. .driver = {
  3857. .name = "wcd938x_codec",
  3858. .owner = THIS_MODULE,
  3859. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3860. #ifdef CONFIG_PM_SLEEP
  3861. .pm = &wcd938x_dev_pm_ops,
  3862. #endif
  3863. .suppress_bind_attrs = true,
  3864. },
  3865. };
  3866. module_platform_driver(wcd938x_codec_driver);
  3867. MODULE_DESCRIPTION("WCD938X Codec driver");
  3868. MODULE_LICENSE("GPL v2");