dp_tx.c 114 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "enet.h"
  34. #include "dp_internal.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. /* TODO Add support in TSO */
  42. #define DP_DESC_NUM_FRAG(x) 0
  43. /* disable TQM_BYPASS */
  44. #define TQM_BYPASS_WAR 0
  45. /* invalid peer id for reinject*/
  46. #define DP_INVALID_PEER 0XFFFE
  47. /*mapping between hal encrypt type and cdp_sec_type*/
  48. #define MAX_CDP_SEC_TYPE 12
  49. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  50. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  51. HAL_TX_ENCRYPT_TYPE_WEP_128,
  52. HAL_TX_ENCRYPT_TYPE_WEP_104,
  53. HAL_TX_ENCRYPT_TYPE_WEP_40,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  56. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_WAPI,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  62. #ifdef QCA_TX_LIMIT_CHECK
  63. /**
  64. * dp_tx_limit_check - Check if allocated tx descriptors reached
  65. * soc max limit and pdev max limit
  66. * @vdev: DP vdev handle
  67. *
  68. * Return: true if allocated tx descriptors reached max configured value, else
  69. * false
  70. */
  71. static inline bool
  72. dp_tx_limit_check(struct dp_vdev *vdev)
  73. {
  74. struct dp_pdev *pdev = vdev->pdev;
  75. struct dp_soc *soc = pdev->soc;
  76. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  77. soc->num_tx_allowed) {
  78. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  79. "%s: queued packets are more than max tx, drop the frame",
  80. __func__);
  81. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  82. return true;
  83. }
  84. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  85. pdev->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. return false;
  93. }
  94. /**
  95. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  96. * @vdev: DP pdev handle
  97. *
  98. * Return: void
  99. */
  100. static inline void
  101. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  102. {
  103. struct dp_soc *soc = pdev->soc;
  104. qdf_atomic_inc(&pdev->num_tx_outstanding);
  105. qdf_atomic_inc(&soc->num_tx_outstanding);
  106. }
  107. /**
  108. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  109. * @vdev: DP pdev handle
  110. *
  111. * Return: void
  112. */
  113. static inline void
  114. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  115. {
  116. struct dp_soc *soc = pdev->soc;
  117. qdf_atomic_dec(&pdev->num_tx_outstanding);
  118. qdf_atomic_dec(&soc->num_tx_outstanding);
  119. }
  120. #else //QCA_TX_LIMIT_CHECK
  121. static inline bool
  122. dp_tx_limit_check(struct dp_vdev *vdev)
  123. {
  124. return false;
  125. }
  126. static inline void
  127. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  128. {
  129. qdf_atomic_inc(&pdev->num_tx_outstanding);
  130. }
  131. static inline void
  132. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  133. {
  134. qdf_atomic_dec(&pdev->num_tx_outstanding);
  135. }
  136. #endif //QCA_TX_LIMIT_CHECK
  137. #if defined(FEATURE_TSO)
  138. /**
  139. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  140. *
  141. * @soc - core txrx main context
  142. * @seg_desc - tso segment descriptor
  143. * @num_seg_desc - tso number segment descriptor
  144. */
  145. static void dp_tx_tso_unmap_segment(
  146. struct dp_soc *soc,
  147. struct qdf_tso_seg_elem_t *seg_desc,
  148. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  149. {
  150. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  151. if (qdf_unlikely(!seg_desc)) {
  152. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  153. __func__, __LINE__);
  154. qdf_assert(0);
  155. } else if (qdf_unlikely(!num_seg_desc)) {
  156. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  157. __func__, __LINE__);
  158. qdf_assert(0);
  159. } else {
  160. bool is_last_seg;
  161. /* no tso segment left to do dma unmap */
  162. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  163. return;
  164. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  165. true : false;
  166. qdf_nbuf_unmap_tso_segment(soc->osdev,
  167. seg_desc, is_last_seg);
  168. num_seg_desc->num_seg.tso_cmn_num_seg--;
  169. }
  170. }
  171. /**
  172. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  173. * back to the freelist
  174. *
  175. * @soc - soc device handle
  176. * @tx_desc - Tx software descriptor
  177. */
  178. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  179. struct dp_tx_desc_s *tx_desc)
  180. {
  181. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  182. if (qdf_unlikely(!tx_desc->tso_desc)) {
  183. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  184. "%s %d TSO desc is NULL!",
  185. __func__, __LINE__);
  186. qdf_assert(0);
  187. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  188. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  189. "%s %d TSO num desc is NULL!",
  190. __func__, __LINE__);
  191. qdf_assert(0);
  192. } else {
  193. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  194. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  195. /* Add the tso num segment into the free list */
  196. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  197. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  198. tx_desc->tso_num_desc);
  199. tx_desc->tso_num_desc = NULL;
  200. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  201. }
  202. /* Add the tso segment into the free list*/
  203. dp_tx_tso_desc_free(soc,
  204. tx_desc->pool_id, tx_desc->tso_desc);
  205. tx_desc->tso_desc = NULL;
  206. }
  207. }
  208. #else
  209. static void dp_tx_tso_unmap_segment(
  210. struct dp_soc *soc,
  211. struct qdf_tso_seg_elem_t *seg_desc,
  212. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  213. {
  214. }
  215. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  216. struct dp_tx_desc_s *tx_desc)
  217. {
  218. }
  219. #endif
  220. /**
  221. * dp_tx_desc_release() - Release Tx Descriptor
  222. * @tx_desc : Tx Descriptor
  223. * @desc_pool_id: Descriptor Pool ID
  224. *
  225. * Deallocate all resources attached to Tx descriptor and free the Tx
  226. * descriptor.
  227. *
  228. * Return:
  229. */
  230. static void
  231. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  232. {
  233. struct dp_pdev *pdev = tx_desc->pdev;
  234. struct dp_soc *soc;
  235. uint8_t comp_status = 0;
  236. qdf_assert(pdev);
  237. soc = pdev->soc;
  238. if (tx_desc->frm_type == dp_tx_frm_tso)
  239. dp_tx_tso_desc_release(soc, tx_desc);
  240. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  241. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  242. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  243. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  244. dp_tx_outstanding_dec(pdev);
  245. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  246. qdf_atomic_dec(&pdev->num_tx_exception);
  247. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  248. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  249. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  250. soc->hal_soc);
  251. else
  252. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  253. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  254. "Tx Completion Release desc %d status %d outstanding %d",
  255. tx_desc->id, comp_status,
  256. qdf_atomic_read(&pdev->num_tx_outstanding));
  257. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  258. return;
  259. }
  260. /**
  261. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  262. * @vdev: DP vdev Handle
  263. * @nbuf: skb
  264. * @msdu_info: msdu_info required to create HTT metadata
  265. *
  266. * Prepares and fills HTT metadata in the frame pre-header for special frames
  267. * that should be transmitted using varying transmit parameters.
  268. * There are 2 VDEV modes that currently needs this special metadata -
  269. * 1) Mesh Mode
  270. * 2) DSRC Mode
  271. *
  272. * Return: HTT metadata size
  273. *
  274. */
  275. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  276. struct dp_tx_msdu_info_s *msdu_info)
  277. {
  278. uint32_t *meta_data = msdu_info->meta_data;
  279. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  280. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  281. uint8_t htt_desc_size;
  282. /* Size rounded of multiple of 8 bytes */
  283. uint8_t htt_desc_size_aligned;
  284. uint8_t *hdr = NULL;
  285. /*
  286. * Metadata - HTT MSDU Extension header
  287. */
  288. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  289. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  290. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  291. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  292. meta_data[0])) {
  293. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  294. htt_desc_size_aligned)) {
  295. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  296. htt_desc_size_aligned);
  297. if (!nbuf) {
  298. /*
  299. * qdf_nbuf_realloc_headroom won't do skb_clone
  300. * as skb_realloc_headroom does. so, no free is
  301. * needed here.
  302. */
  303. DP_STATS_INC(vdev,
  304. tx_i.dropped.headroom_insufficient,
  305. 1);
  306. qdf_print(" %s[%d] skb_realloc_headroom failed",
  307. __func__, __LINE__);
  308. return 0;
  309. }
  310. }
  311. /* Fill and add HTT metaheader */
  312. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  313. if (!hdr) {
  314. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  315. "Error in filling HTT metadata");
  316. return 0;
  317. }
  318. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  319. } else if (vdev->opmode == wlan_op_mode_ocb) {
  320. /* Todo - Add support for DSRC */
  321. }
  322. return htt_desc_size_aligned;
  323. }
  324. /**
  325. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  326. * @tso_seg: TSO segment to process
  327. * @ext_desc: Pointer to MSDU extension descriptor
  328. *
  329. * Return: void
  330. */
  331. #if defined(FEATURE_TSO)
  332. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  333. void *ext_desc)
  334. {
  335. uint8_t num_frag;
  336. uint32_t tso_flags;
  337. /*
  338. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  339. * tcp_flag_mask
  340. *
  341. * Checksum enable flags are set in TCL descriptor and not in Extension
  342. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  343. */
  344. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  345. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  346. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  347. tso_seg->tso_flags.ip_len);
  348. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  349. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  350. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  351. uint32_t lo = 0;
  352. uint32_t hi = 0;
  353. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  354. (tso_seg->tso_frags[num_frag].length));
  355. qdf_dmaaddr_to_32s(
  356. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  357. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  358. tso_seg->tso_frags[num_frag].length);
  359. }
  360. return;
  361. }
  362. #else
  363. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  364. void *ext_desc)
  365. {
  366. return;
  367. }
  368. #endif
  369. #if defined(FEATURE_TSO)
  370. /**
  371. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  372. * allocated and free them
  373. *
  374. * @soc: soc handle
  375. * @free_seg: list of tso segments
  376. * @msdu_info: msdu descriptor
  377. *
  378. * Return - void
  379. */
  380. static void dp_tx_free_tso_seg_list(
  381. struct dp_soc *soc,
  382. struct qdf_tso_seg_elem_t *free_seg,
  383. struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. struct qdf_tso_seg_elem_t *next_seg;
  386. while (free_seg) {
  387. next_seg = free_seg->next;
  388. dp_tx_tso_desc_free(soc,
  389. msdu_info->tx_queue.desc_pool_id,
  390. free_seg);
  391. free_seg = next_seg;
  392. }
  393. }
  394. /**
  395. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  396. * allocated and free them
  397. *
  398. * @soc: soc handle
  399. * @free_num_seg: list of tso number segments
  400. * @msdu_info: msdu descriptor
  401. * Return - void
  402. */
  403. static void dp_tx_free_tso_num_seg_list(
  404. struct dp_soc *soc,
  405. struct qdf_tso_num_seg_elem_t *free_num_seg,
  406. struct dp_tx_msdu_info_s *msdu_info)
  407. {
  408. struct qdf_tso_num_seg_elem_t *next_num_seg;
  409. while (free_num_seg) {
  410. next_num_seg = free_num_seg->next;
  411. dp_tso_num_seg_free(soc,
  412. msdu_info->tx_queue.desc_pool_id,
  413. free_num_seg);
  414. free_num_seg = next_num_seg;
  415. }
  416. }
  417. /**
  418. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  419. * do dma unmap for each segment
  420. *
  421. * @soc: soc handle
  422. * @free_seg: list of tso segments
  423. * @num_seg_desc: tso number segment descriptor
  424. *
  425. * Return - void
  426. */
  427. static void dp_tx_unmap_tso_seg_list(
  428. struct dp_soc *soc,
  429. struct qdf_tso_seg_elem_t *free_seg,
  430. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  431. {
  432. struct qdf_tso_seg_elem_t *next_seg;
  433. if (qdf_unlikely(!num_seg_desc)) {
  434. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  435. return;
  436. }
  437. while (free_seg) {
  438. next_seg = free_seg->next;
  439. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  440. free_seg = next_seg;
  441. }
  442. }
  443. #ifdef FEATURE_TSO_STATS
  444. /**
  445. * dp_tso_get_stats_idx: Retrieve the tso packet id
  446. * @pdev - pdev handle
  447. *
  448. * Return: id
  449. */
  450. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  451. {
  452. uint32_t stats_idx;
  453. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  454. % CDP_MAX_TSO_PACKETS);
  455. return stats_idx;
  456. }
  457. #else
  458. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  459. {
  460. return 0;
  461. }
  462. #endif /* FEATURE_TSO_STATS */
  463. /**
  464. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  465. * free the tso segments descriptor and
  466. * tso num segments descriptor
  467. *
  468. * @soc: soc handle
  469. * @msdu_info: msdu descriptor
  470. * @tso_seg_unmap: flag to show if dma unmap is necessary
  471. *
  472. * Return - void
  473. */
  474. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  475. struct dp_tx_msdu_info_s *msdu_info,
  476. bool tso_seg_unmap)
  477. {
  478. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  479. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  480. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  481. tso_info->tso_num_seg_list;
  482. /* do dma unmap for each segment */
  483. if (tso_seg_unmap)
  484. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  485. /* free all tso number segment descriptor though looks only have 1 */
  486. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  487. /* free all tso segment descriptor */
  488. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  489. }
  490. /**
  491. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  492. * @vdev: virtual device handle
  493. * @msdu: network buffer
  494. * @msdu_info: meta data associated with the msdu
  495. *
  496. * Return: QDF_STATUS_SUCCESS success
  497. */
  498. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  499. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  500. {
  501. struct qdf_tso_seg_elem_t *tso_seg;
  502. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  503. struct dp_soc *soc = vdev->pdev->soc;
  504. struct dp_pdev *pdev = vdev->pdev;
  505. struct qdf_tso_info_t *tso_info;
  506. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  507. tso_info = &msdu_info->u.tso_info;
  508. tso_info->curr_seg = NULL;
  509. tso_info->tso_seg_list = NULL;
  510. tso_info->num_segs = num_seg;
  511. msdu_info->frm_type = dp_tx_frm_tso;
  512. tso_info->tso_num_seg_list = NULL;
  513. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  514. while (num_seg) {
  515. tso_seg = dp_tx_tso_desc_alloc(
  516. soc, msdu_info->tx_queue.desc_pool_id);
  517. if (tso_seg) {
  518. tso_seg->next = tso_info->tso_seg_list;
  519. tso_info->tso_seg_list = tso_seg;
  520. num_seg--;
  521. } else {
  522. dp_err_rl("Failed to alloc tso seg desc");
  523. DP_STATS_INC_PKT(vdev->pdev,
  524. tso_stats.tso_no_mem_dropped, 1,
  525. qdf_nbuf_len(msdu));
  526. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  527. return QDF_STATUS_E_NOMEM;
  528. }
  529. }
  530. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  531. tso_num_seg = dp_tso_num_seg_alloc(soc,
  532. msdu_info->tx_queue.desc_pool_id);
  533. if (tso_num_seg) {
  534. tso_num_seg->next = tso_info->tso_num_seg_list;
  535. tso_info->tso_num_seg_list = tso_num_seg;
  536. } else {
  537. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  538. __func__);
  539. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  540. return QDF_STATUS_E_NOMEM;
  541. }
  542. msdu_info->num_seg =
  543. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  544. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  545. msdu_info->num_seg);
  546. if (!(msdu_info->num_seg)) {
  547. /*
  548. * Free allocated TSO seg desc and number seg desc,
  549. * do unmap for segments if dma map has done.
  550. */
  551. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  552. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  553. return QDF_STATUS_E_INVAL;
  554. }
  555. tso_info->curr_seg = tso_info->tso_seg_list;
  556. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  557. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  558. msdu, msdu_info->num_seg);
  559. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  560. tso_info->msdu_stats_idx);
  561. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  562. return QDF_STATUS_SUCCESS;
  563. }
  564. #else
  565. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  566. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  567. {
  568. return QDF_STATUS_E_NOMEM;
  569. }
  570. #endif
  571. /**
  572. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  573. * @vdev: DP Vdev handle
  574. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  575. * @desc_pool_id: Descriptor Pool ID
  576. *
  577. * Return:
  578. */
  579. static
  580. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  581. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  582. {
  583. uint8_t i;
  584. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  585. struct dp_tx_seg_info_s *seg_info;
  586. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  587. struct dp_soc *soc = vdev->pdev->soc;
  588. /* Allocate an extension descriptor */
  589. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  590. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  591. if (!msdu_ext_desc) {
  592. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  593. return NULL;
  594. }
  595. if (msdu_info->exception_fw &&
  596. qdf_unlikely(vdev->mesh_vdev)) {
  597. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  598. &msdu_info->meta_data[0],
  599. sizeof(struct htt_tx_msdu_desc_ext2_t));
  600. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  601. }
  602. switch (msdu_info->frm_type) {
  603. case dp_tx_frm_sg:
  604. case dp_tx_frm_me:
  605. case dp_tx_frm_raw:
  606. seg_info = msdu_info->u.sg_info.curr_seg;
  607. /* Update the buffer pointers in MSDU Extension Descriptor */
  608. for (i = 0; i < seg_info->frag_cnt; i++) {
  609. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  610. seg_info->frags[i].paddr_lo,
  611. seg_info->frags[i].paddr_hi,
  612. seg_info->frags[i].len);
  613. }
  614. break;
  615. case dp_tx_frm_tso:
  616. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  617. &cached_ext_desc[0]);
  618. break;
  619. default:
  620. break;
  621. }
  622. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  623. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  624. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  625. msdu_ext_desc->vaddr);
  626. return msdu_ext_desc;
  627. }
  628. /**
  629. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  630. *
  631. * @skb: skb to be traced
  632. * @msdu_id: msdu_id of the packet
  633. * @vdev_id: vdev_id of the packet
  634. *
  635. * Return: None
  636. */
  637. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  638. uint8_t vdev_id)
  639. {
  640. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  641. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  642. DPTRACE(qdf_dp_trace_ptr(skb,
  643. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  644. QDF_TRACE_DEFAULT_PDEV_ID,
  645. qdf_nbuf_data_addr(skb),
  646. sizeof(qdf_nbuf_data(skb)),
  647. msdu_id, vdev_id));
  648. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  649. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  650. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  651. msdu_id, QDF_TX));
  652. }
  653. /**
  654. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  655. * @vdev: DP vdev handle
  656. * @nbuf: skb
  657. * @desc_pool_id: Descriptor pool ID
  658. * @meta_data: Metadata to the fw
  659. * @tx_exc_metadata: Handle that holds exception path metadata
  660. * Allocate and prepare Tx descriptor with msdu information.
  661. *
  662. * Return: Pointer to Tx Descriptor on success,
  663. * NULL on failure
  664. */
  665. static
  666. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  667. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  668. struct dp_tx_msdu_info_s *msdu_info,
  669. struct cdp_tx_exception_metadata *tx_exc_metadata)
  670. {
  671. uint8_t align_pad;
  672. uint8_t is_exception = 0;
  673. uint8_t htt_hdr_size;
  674. qdf_ether_header_t *eh;
  675. struct dp_tx_desc_s *tx_desc;
  676. struct dp_pdev *pdev = vdev->pdev;
  677. struct dp_soc *soc = pdev->soc;
  678. if (dp_tx_limit_check(vdev))
  679. return NULL;
  680. /* Allocate software Tx descriptor */
  681. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  682. if (qdf_unlikely(!tx_desc)) {
  683. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  684. return NULL;
  685. }
  686. dp_tx_outstanding_inc(pdev);
  687. /* Initialize the SW tx descriptor */
  688. tx_desc->nbuf = nbuf;
  689. tx_desc->frm_type = dp_tx_frm_std;
  690. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  691. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  692. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  693. tx_desc->vdev = vdev;
  694. tx_desc->pdev = pdev;
  695. tx_desc->msdu_ext_desc = NULL;
  696. tx_desc->pkt_offset = 0;
  697. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  698. if (qdf_unlikely(vdev->multipass_en)) {
  699. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  700. goto failure;
  701. }
  702. /*
  703. * For special modes (vdev_type == ocb or mesh), data frames should be
  704. * transmitted using varying transmit parameters (tx spec) which include
  705. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  706. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  707. * These frames are sent as exception packets to firmware.
  708. *
  709. * HW requirement is that metadata should always point to a
  710. * 8-byte aligned address. So we add alignment pad to start of buffer.
  711. * HTT Metadata should be ensured to be multiple of 8-bytes,
  712. * to get 8-byte aligned start address along with align_pad added
  713. *
  714. * |-----------------------------|
  715. * | |
  716. * |-----------------------------| <-----Buffer Pointer Address given
  717. * | | ^ in HW descriptor (aligned)
  718. * | HTT Metadata | |
  719. * | | |
  720. * | | | Packet Offset given in descriptor
  721. * | | |
  722. * |-----------------------------| |
  723. * | Alignment Pad | v
  724. * |-----------------------------| <----- Actual buffer start address
  725. * | SKB Data | (Unaligned)
  726. * | |
  727. * | |
  728. * | |
  729. * | |
  730. * | |
  731. * |-----------------------------|
  732. */
  733. if (qdf_unlikely((msdu_info->exception_fw)) ||
  734. (vdev->opmode == wlan_op_mode_ocb) ||
  735. (tx_exc_metadata &&
  736. tx_exc_metadata->is_tx_sniffer)) {
  737. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  738. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  739. DP_STATS_INC(vdev,
  740. tx_i.dropped.headroom_insufficient, 1);
  741. goto failure;
  742. }
  743. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  744. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  745. "qdf_nbuf_push_head failed");
  746. goto failure;
  747. }
  748. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  749. msdu_info);
  750. if (htt_hdr_size == 0)
  751. goto failure;
  752. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  753. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  754. is_exception = 1;
  755. }
  756. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  757. qdf_nbuf_map(soc->osdev, nbuf,
  758. QDF_DMA_TO_DEVICE))) {
  759. /* Handle failure */
  760. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  761. "qdf_nbuf_map failed");
  762. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  763. goto failure;
  764. }
  765. if (qdf_unlikely(vdev->nawds_enabled)) {
  766. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  767. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  768. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  769. is_exception = 1;
  770. }
  771. }
  772. #if !TQM_BYPASS_WAR
  773. if (is_exception || tx_exc_metadata)
  774. #endif
  775. {
  776. /* Temporary WAR due to TQM VP issues */
  777. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  778. qdf_atomic_inc(&pdev->num_tx_exception);
  779. }
  780. return tx_desc;
  781. failure:
  782. dp_tx_desc_release(tx_desc, desc_pool_id);
  783. return NULL;
  784. }
  785. /**
  786. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  787. * @vdev: DP vdev handle
  788. * @nbuf: skb
  789. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  790. * @desc_pool_id : Descriptor Pool ID
  791. *
  792. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  793. * information. For frames wth fragments, allocate and prepare
  794. * an MSDU extension descriptor
  795. *
  796. * Return: Pointer to Tx Descriptor on success,
  797. * NULL on failure
  798. */
  799. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  800. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  801. uint8_t desc_pool_id)
  802. {
  803. struct dp_tx_desc_s *tx_desc;
  804. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  805. struct dp_pdev *pdev = vdev->pdev;
  806. struct dp_soc *soc = pdev->soc;
  807. if (dp_tx_limit_check(vdev))
  808. return NULL;
  809. /* Allocate software Tx descriptor */
  810. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  811. if (!tx_desc) {
  812. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  813. return NULL;
  814. }
  815. dp_tx_outstanding_inc(pdev);
  816. /* Initialize the SW tx descriptor */
  817. tx_desc->nbuf = nbuf;
  818. tx_desc->frm_type = msdu_info->frm_type;
  819. tx_desc->tx_encap_type = vdev->tx_encap_type;
  820. tx_desc->vdev = vdev;
  821. tx_desc->pdev = pdev;
  822. tx_desc->pkt_offset = 0;
  823. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  824. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  825. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  826. /* Handle scattered frames - TSO/SG/ME */
  827. /* Allocate and prepare an extension descriptor for scattered frames */
  828. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  829. if (!msdu_ext_desc) {
  830. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  831. "%s Tx Extension Descriptor Alloc Fail",
  832. __func__);
  833. goto failure;
  834. }
  835. #if TQM_BYPASS_WAR
  836. /* Temporary WAR due to TQM VP issues */
  837. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  838. qdf_atomic_inc(&pdev->num_tx_exception);
  839. #endif
  840. if (qdf_unlikely(msdu_info->exception_fw))
  841. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  842. tx_desc->msdu_ext_desc = msdu_ext_desc;
  843. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  844. return tx_desc;
  845. failure:
  846. dp_tx_desc_release(tx_desc, desc_pool_id);
  847. return NULL;
  848. }
  849. /**
  850. * dp_tx_prepare_raw() - Prepare RAW packet TX
  851. * @vdev: DP vdev handle
  852. * @nbuf: buffer pointer
  853. * @seg_info: Pointer to Segment info Descriptor to be prepared
  854. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  855. * descriptor
  856. *
  857. * Return:
  858. */
  859. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  860. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  861. {
  862. qdf_nbuf_t curr_nbuf = NULL;
  863. uint16_t total_len = 0;
  864. qdf_dma_addr_t paddr;
  865. int32_t i;
  866. int32_t mapped_buf_num = 0;
  867. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  868. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  869. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  870. /* Continue only if frames are of DATA type */
  871. if (!DP_FRAME_IS_DATA(qos_wh)) {
  872. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  873. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  874. "Pkt. recd is of not data type");
  875. goto error;
  876. }
  877. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  878. if (vdev->raw_mode_war &&
  879. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  880. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  881. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  882. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  883. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  884. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  885. QDF_DMA_TO_DEVICE)) {
  886. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  887. "%s dma map error ", __func__);
  888. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  889. mapped_buf_num = i;
  890. goto error;
  891. }
  892. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  893. seg_info->frags[i].paddr_lo = paddr;
  894. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  895. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  896. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  897. total_len += qdf_nbuf_len(curr_nbuf);
  898. }
  899. seg_info->frag_cnt = i;
  900. seg_info->total_len = total_len;
  901. seg_info->next = NULL;
  902. sg_info->curr_seg = seg_info;
  903. msdu_info->frm_type = dp_tx_frm_raw;
  904. msdu_info->num_seg = 1;
  905. return nbuf;
  906. error:
  907. i = 0;
  908. while (nbuf) {
  909. curr_nbuf = nbuf;
  910. if (i < mapped_buf_num) {
  911. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  912. i++;
  913. }
  914. nbuf = qdf_nbuf_next(nbuf);
  915. qdf_nbuf_free(curr_nbuf);
  916. }
  917. return NULL;
  918. }
  919. /**
  920. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  921. * @soc: DP soc handle
  922. * @nbuf: Buffer pointer
  923. *
  924. * unmap the chain of nbufs that belong to this RAW frame.
  925. *
  926. * Return: None
  927. */
  928. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  929. qdf_nbuf_t nbuf)
  930. {
  931. qdf_nbuf_t cur_nbuf = nbuf;
  932. do {
  933. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  934. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  935. } while (cur_nbuf);
  936. }
  937. /**
  938. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  939. * @soc: DP Soc Handle
  940. * @vdev: DP vdev handle
  941. * @tx_desc: Tx Descriptor Handle
  942. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  943. * @fw_metadata: Metadata to send to Target Firmware along with frame
  944. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  945. * @tx_exc_metadata: Handle that holds exception path meta data
  946. *
  947. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  948. * from software Tx descriptor
  949. *
  950. * Return:
  951. */
  952. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  953. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  954. uint16_t fw_metadata, uint8_t ring_id,
  955. struct cdp_tx_exception_metadata
  956. *tx_exc_metadata)
  957. {
  958. uint8_t type;
  959. uint16_t length;
  960. void *hal_tx_desc, *hal_tx_desc_cached;
  961. qdf_dma_addr_t dma_addr;
  962. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  963. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  964. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  965. tx_exc_metadata->sec_type : vdev->sec_type);
  966. /* Return Buffer Manager ID */
  967. uint8_t bm_id = ring_id;
  968. hal_ring_handle_t hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  969. hal_tx_desc_cached = (void *) cached_desc;
  970. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  971. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  972. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  973. type = HAL_TX_BUF_TYPE_EXT_DESC;
  974. dma_addr = tx_desc->msdu_ext_desc->paddr;
  975. } else {
  976. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  977. type = HAL_TX_BUF_TYPE_BUFFER;
  978. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  979. }
  980. qdf_assert_always(dma_addr);
  981. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  982. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  983. dma_addr, bm_id, tx_desc->id,
  984. type, soc->hal_soc);
  985. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  986. return QDF_STATUS_E_RESOURCES;
  987. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  988. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  989. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  990. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  991. vdev->pdev->lmac_id);
  992. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  993. vdev->search_type);
  994. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  995. vdev->bss_ast_idx);
  996. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  997. vdev->dscp_tid_map_id);
  998. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  999. sec_type_map[sec_type]);
  1000. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1001. (vdev->bss_ast_hash & 0xF));
  1002. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1003. length, type, (uint64_t)dma_addr,
  1004. tx_desc->pkt_offset, tx_desc->id);
  1005. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1006. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1007. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1008. vdev->hal_desc_addr_search_flags);
  1009. /* verify checksum offload configuration*/
  1010. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  1011. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1012. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1013. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1014. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1015. }
  1016. if (tid != HTT_TX_EXT_TID_INVALID)
  1017. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1018. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1019. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1020. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  1021. /* Sync cached descriptor with HW */
  1022. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1023. if (!hal_tx_desc) {
  1024. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1025. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1026. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1027. return QDF_STATUS_E_RESOURCES;
  1028. }
  1029. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1030. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1031. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  1032. return QDF_STATUS_SUCCESS;
  1033. }
  1034. /**
  1035. * dp_cce_classify() - Classify the frame based on CCE rules
  1036. * @vdev: DP vdev handle
  1037. * @nbuf: skb
  1038. *
  1039. * Classify frames based on CCE rules
  1040. * Return: bool( true if classified,
  1041. * else false)
  1042. */
  1043. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1044. {
  1045. qdf_ether_header_t *eh = NULL;
  1046. uint16_t ether_type;
  1047. qdf_llc_t *llcHdr;
  1048. qdf_nbuf_t nbuf_clone = NULL;
  1049. qdf_dot3_qosframe_t *qos_wh = NULL;
  1050. /* for mesh packets don't do any classification */
  1051. if (qdf_unlikely(vdev->mesh_vdev))
  1052. return false;
  1053. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1054. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1055. ether_type = eh->ether_type;
  1056. llcHdr = (qdf_llc_t *)(nbuf->data +
  1057. sizeof(qdf_ether_header_t));
  1058. } else {
  1059. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1060. /* For encrypted packets don't do any classification */
  1061. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1062. return false;
  1063. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1064. if (qdf_unlikely(
  1065. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1066. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1067. ether_type = *(uint16_t *)(nbuf->data
  1068. + QDF_IEEE80211_4ADDR_HDR_LEN
  1069. + sizeof(qdf_llc_t)
  1070. - sizeof(ether_type));
  1071. llcHdr = (qdf_llc_t *)(nbuf->data +
  1072. QDF_IEEE80211_4ADDR_HDR_LEN);
  1073. } else {
  1074. ether_type = *(uint16_t *)(nbuf->data
  1075. + QDF_IEEE80211_3ADDR_HDR_LEN
  1076. + sizeof(qdf_llc_t)
  1077. - sizeof(ether_type));
  1078. llcHdr = (qdf_llc_t *)(nbuf->data +
  1079. QDF_IEEE80211_3ADDR_HDR_LEN);
  1080. }
  1081. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1082. && (ether_type ==
  1083. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1084. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1085. return true;
  1086. }
  1087. }
  1088. return false;
  1089. }
  1090. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1091. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1092. sizeof(*llcHdr));
  1093. nbuf_clone = qdf_nbuf_clone(nbuf);
  1094. if (qdf_unlikely(nbuf_clone)) {
  1095. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1096. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1097. qdf_nbuf_pull_head(nbuf_clone,
  1098. sizeof(qdf_net_vlanhdr_t));
  1099. }
  1100. }
  1101. } else {
  1102. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1103. nbuf_clone = qdf_nbuf_clone(nbuf);
  1104. if (qdf_unlikely(nbuf_clone)) {
  1105. qdf_nbuf_pull_head(nbuf_clone,
  1106. sizeof(qdf_net_vlanhdr_t));
  1107. }
  1108. }
  1109. }
  1110. if (qdf_unlikely(nbuf_clone))
  1111. nbuf = nbuf_clone;
  1112. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1113. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1114. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1115. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1116. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1117. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1118. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1119. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1120. if (qdf_unlikely(nbuf_clone))
  1121. qdf_nbuf_free(nbuf_clone);
  1122. return true;
  1123. }
  1124. if (qdf_unlikely(nbuf_clone))
  1125. qdf_nbuf_free(nbuf_clone);
  1126. return false;
  1127. }
  1128. /**
  1129. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1130. * @vdev: DP vdev handle
  1131. * @nbuf: skb
  1132. *
  1133. * Extract the DSCP or PCP information from frame and map into TID value.
  1134. *
  1135. * Return: void
  1136. */
  1137. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1138. struct dp_tx_msdu_info_s *msdu_info)
  1139. {
  1140. uint8_t tos = 0, dscp_tid_override = 0;
  1141. uint8_t *hdr_ptr, *L3datap;
  1142. uint8_t is_mcast = 0;
  1143. qdf_ether_header_t *eh = NULL;
  1144. qdf_ethervlan_header_t *evh = NULL;
  1145. uint16_t ether_type;
  1146. qdf_llc_t *llcHdr;
  1147. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1148. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1149. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1150. eh = (qdf_ether_header_t *)nbuf->data;
  1151. hdr_ptr = eh->ether_dhost;
  1152. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1153. } else {
  1154. qdf_dot3_qosframe_t *qos_wh =
  1155. (qdf_dot3_qosframe_t *) nbuf->data;
  1156. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1157. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1158. return;
  1159. }
  1160. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1161. ether_type = eh->ether_type;
  1162. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1163. /*
  1164. * Check if packet is dot3 or eth2 type.
  1165. */
  1166. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1167. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1168. sizeof(*llcHdr));
  1169. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1170. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1171. sizeof(*llcHdr);
  1172. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1173. + sizeof(*llcHdr) +
  1174. sizeof(qdf_net_vlanhdr_t));
  1175. } else {
  1176. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1177. sizeof(*llcHdr);
  1178. }
  1179. } else {
  1180. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1181. evh = (qdf_ethervlan_header_t *) eh;
  1182. ether_type = evh->ether_type;
  1183. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1184. }
  1185. }
  1186. /*
  1187. * Find priority from IP TOS DSCP field
  1188. */
  1189. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1190. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1191. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1192. /* Only for unicast frames */
  1193. if (!is_mcast) {
  1194. /* send it on VO queue */
  1195. msdu_info->tid = DP_VO_TID;
  1196. }
  1197. } else {
  1198. /*
  1199. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1200. * from TOS byte.
  1201. */
  1202. tos = ip->ip_tos;
  1203. dscp_tid_override = 1;
  1204. }
  1205. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1206. /* TODO
  1207. * use flowlabel
  1208. *igmpmld cases to be handled in phase 2
  1209. */
  1210. unsigned long ver_pri_flowlabel;
  1211. unsigned long pri;
  1212. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1213. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1214. DP_IPV6_PRIORITY_SHIFT;
  1215. tos = pri;
  1216. dscp_tid_override = 1;
  1217. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1218. msdu_info->tid = DP_VO_TID;
  1219. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1220. /* Only for unicast frames */
  1221. if (!is_mcast) {
  1222. /* send ucast arp on VO queue */
  1223. msdu_info->tid = DP_VO_TID;
  1224. }
  1225. }
  1226. /*
  1227. * Assign all MCAST packets to BE
  1228. */
  1229. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1230. if (is_mcast) {
  1231. tos = 0;
  1232. dscp_tid_override = 1;
  1233. }
  1234. }
  1235. if (dscp_tid_override == 1) {
  1236. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1237. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1238. }
  1239. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1240. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1241. return;
  1242. }
  1243. /**
  1244. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1245. * @vdev: DP vdev handle
  1246. * @nbuf: skb
  1247. *
  1248. * Software based TID classification is required when more than 2 DSCP-TID
  1249. * mapping tables are needed.
  1250. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1251. *
  1252. * Return: void
  1253. */
  1254. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1255. struct dp_tx_msdu_info_s *msdu_info)
  1256. {
  1257. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1258. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1259. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1260. return;
  1261. /* for mesh packets don't do any classification */
  1262. if (qdf_unlikely(vdev->mesh_vdev))
  1263. return;
  1264. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1265. }
  1266. #ifdef FEATURE_WLAN_TDLS
  1267. /**
  1268. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1269. * @tx_desc: TX descriptor
  1270. *
  1271. * Return: None
  1272. */
  1273. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1274. {
  1275. if (tx_desc->vdev) {
  1276. if (tx_desc->vdev->is_tdls_frame) {
  1277. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1278. tx_desc->vdev->is_tdls_frame = false;
  1279. }
  1280. }
  1281. }
  1282. /**
  1283. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1284. * @tx_desc: TX descriptor
  1285. * @vdev: datapath vdev handle
  1286. *
  1287. * Return: None
  1288. */
  1289. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1290. struct dp_vdev *vdev)
  1291. {
  1292. struct hal_tx_completion_status ts = {0};
  1293. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1294. if (qdf_unlikely(!vdev)) {
  1295. dp_err("vdev is null!");
  1296. return;
  1297. }
  1298. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1299. if (vdev->tx_non_std_data_callback.func) {
  1300. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1301. vdev->tx_non_std_data_callback.func(
  1302. vdev->tx_non_std_data_callback.ctxt,
  1303. nbuf, ts.status);
  1304. return;
  1305. }
  1306. }
  1307. #else
  1308. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1309. {
  1310. }
  1311. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1312. struct dp_vdev *vdev)
  1313. {
  1314. }
  1315. #endif
  1316. /**
  1317. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1318. * @vdev: DP vdev handle
  1319. * @nbuf: skb
  1320. *
  1321. * Return: 1 if frame needs to be dropped else 0
  1322. */
  1323. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1324. {
  1325. struct dp_pdev *pdev = NULL;
  1326. struct dp_ast_entry *src_ast_entry = NULL;
  1327. struct dp_ast_entry *dst_ast_entry = NULL;
  1328. struct dp_soc *soc = NULL;
  1329. qdf_assert(vdev);
  1330. pdev = vdev->pdev;
  1331. qdf_assert(pdev);
  1332. soc = pdev->soc;
  1333. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1334. (soc, dstmac, vdev->pdev->pdev_id);
  1335. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1336. (soc, srcmac, vdev->pdev->pdev_id);
  1337. if (dst_ast_entry && src_ast_entry) {
  1338. if (dst_ast_entry->peer->peer_ids[0] ==
  1339. src_ast_entry->peer->peer_ids[0])
  1340. return 1;
  1341. }
  1342. return 0;
  1343. }
  1344. /**
  1345. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1346. * @vdev: DP vdev handle
  1347. * @nbuf: skb
  1348. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1349. * @meta_data: Metadata to the fw
  1350. * @tx_q: Tx queue to be used for this Tx frame
  1351. * @peer_id: peer_id of the peer in case of NAWDS frames
  1352. * @tx_exc_metadata: Handle that holds exception path metadata
  1353. *
  1354. * Return: NULL on success,
  1355. * nbuf when it fails to send
  1356. */
  1357. qdf_nbuf_t
  1358. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1359. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1360. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1361. {
  1362. struct dp_pdev *pdev = vdev->pdev;
  1363. struct dp_soc *soc = pdev->soc;
  1364. struct dp_tx_desc_s *tx_desc;
  1365. QDF_STATUS status;
  1366. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1367. hal_ring_handle_t hal_ring_hdl =
  1368. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1369. uint16_t htt_tcl_metadata = 0;
  1370. uint8_t tid = msdu_info->tid;
  1371. struct cdp_tid_tx_stats *tid_stats = NULL;
  1372. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1373. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1374. msdu_info, tx_exc_metadata);
  1375. if (!tx_desc) {
  1376. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1377. vdev, tx_q->desc_pool_id);
  1378. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1379. tid_stats = &pdev->stats.tid_stats.
  1380. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1381. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1382. return nbuf;
  1383. }
  1384. if (qdf_unlikely(soc->cce_disable)) {
  1385. if (dp_cce_classify(vdev, nbuf) == true) {
  1386. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1387. tid = DP_VO_TID;
  1388. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1389. }
  1390. }
  1391. dp_tx_update_tdls_flags(tx_desc);
  1392. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1393. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1394. "%s %d : HAL RING Access Failed -- %pK",
  1395. __func__, __LINE__, hal_ring_hdl);
  1396. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1397. tid_stats = &pdev->stats.tid_stats.
  1398. tid_tx_stats[tx_q->ring_id][tid];
  1399. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1400. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1401. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1402. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1403. goto fail_return;
  1404. }
  1405. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1406. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1407. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1408. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1409. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1410. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1411. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1412. peer_id);
  1413. } else
  1414. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1415. if (msdu_info->exception_fw) {
  1416. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1417. }
  1418. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1419. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1420. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1421. if (status != QDF_STATUS_SUCCESS) {
  1422. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1423. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1424. __func__, tx_desc, tx_q->ring_id);
  1425. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1426. tid_stats = &pdev->stats.tid_stats.
  1427. tid_tx_stats[tx_q->ring_id][tid];
  1428. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1429. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1430. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1431. goto fail_return;
  1432. }
  1433. nbuf = NULL;
  1434. fail_return:
  1435. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1436. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1437. hif_pm_runtime_put(soc->hif_handle);
  1438. } else {
  1439. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1440. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1441. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1442. }
  1443. return nbuf;
  1444. }
  1445. /**
  1446. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1447. * @vdev: DP vdev handle
  1448. * @nbuf: skb
  1449. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1450. *
  1451. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1452. *
  1453. * Return: NULL on success,
  1454. * nbuf when it fails to send
  1455. */
  1456. #if QDF_LOCK_STATS
  1457. noinline
  1458. #else
  1459. #endif
  1460. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1461. struct dp_tx_msdu_info_s *msdu_info)
  1462. {
  1463. uint8_t i;
  1464. struct dp_pdev *pdev = vdev->pdev;
  1465. struct dp_soc *soc = pdev->soc;
  1466. struct dp_tx_desc_s *tx_desc;
  1467. bool is_cce_classified = false;
  1468. QDF_STATUS status;
  1469. uint16_t htt_tcl_metadata = 0;
  1470. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1471. hal_ring_handle_t hal_ring_hdl =
  1472. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1473. struct cdp_tid_tx_stats *tid_stats = NULL;
  1474. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1475. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1476. "%s %d : HAL RING Access Failed -- %pK",
  1477. __func__, __LINE__, hal_ring_hdl);
  1478. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1479. tid_stats = &pdev->stats.tid_stats.
  1480. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1481. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1482. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1483. return nbuf;
  1484. }
  1485. if (qdf_unlikely(soc->cce_disable)) {
  1486. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1487. if (is_cce_classified) {
  1488. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1489. msdu_info->tid = DP_VO_TID;
  1490. }
  1491. }
  1492. if (msdu_info->frm_type == dp_tx_frm_me)
  1493. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1494. i = 0;
  1495. /* Print statement to track i and num_seg */
  1496. /*
  1497. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1498. * descriptors using information in msdu_info
  1499. */
  1500. while (i < msdu_info->num_seg) {
  1501. /*
  1502. * Setup Tx descriptor for an MSDU, and MSDU extension
  1503. * descriptor
  1504. */
  1505. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1506. tx_q->desc_pool_id);
  1507. if (!tx_desc) {
  1508. if (msdu_info->frm_type == dp_tx_frm_me) {
  1509. dp_tx_me_free_buf(pdev,
  1510. (void *)(msdu_info->u.sg_info
  1511. .curr_seg->frags[0].vaddr));
  1512. i++;
  1513. continue;
  1514. }
  1515. goto done;
  1516. }
  1517. if (msdu_info->frm_type == dp_tx_frm_me) {
  1518. tx_desc->me_buffer =
  1519. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1520. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1521. }
  1522. if (is_cce_classified)
  1523. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1524. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1525. if (msdu_info->exception_fw) {
  1526. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1527. }
  1528. /*
  1529. * Enqueue the Tx MSDU descriptor to HW for transmit
  1530. */
  1531. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1532. htt_tcl_metadata, tx_q->ring_id, NULL);
  1533. if (status != QDF_STATUS_SUCCESS) {
  1534. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1535. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1536. __func__, tx_desc, tx_q->ring_id);
  1537. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1538. tid_stats = &pdev->stats.tid_stats.
  1539. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1540. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1541. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1542. if (msdu_info->frm_type == dp_tx_frm_me) {
  1543. i++;
  1544. continue;
  1545. }
  1546. goto done;
  1547. }
  1548. /*
  1549. * TODO
  1550. * if tso_info structure can be modified to have curr_seg
  1551. * as first element, following 2 blocks of code (for TSO and SG)
  1552. * can be combined into 1
  1553. */
  1554. /*
  1555. * For frames with multiple segments (TSO, ME), jump to next
  1556. * segment.
  1557. */
  1558. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1559. if (msdu_info->u.tso_info.curr_seg->next) {
  1560. msdu_info->u.tso_info.curr_seg =
  1561. msdu_info->u.tso_info.curr_seg->next;
  1562. /*
  1563. * If this is a jumbo nbuf, then increment the number of
  1564. * nbuf users for each additional segment of the msdu.
  1565. * This will ensure that the skb is freed only after
  1566. * receiving tx completion for all segments of an nbuf
  1567. */
  1568. qdf_nbuf_inc_users(nbuf);
  1569. /* Check with MCL if this is needed */
  1570. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1571. }
  1572. }
  1573. /*
  1574. * For Multicast-Unicast converted packets,
  1575. * each converted frame (for a client) is represented as
  1576. * 1 segment
  1577. */
  1578. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1579. (msdu_info->frm_type == dp_tx_frm_me)) {
  1580. if (msdu_info->u.sg_info.curr_seg->next) {
  1581. msdu_info->u.sg_info.curr_seg =
  1582. msdu_info->u.sg_info.curr_seg->next;
  1583. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1584. }
  1585. }
  1586. i++;
  1587. }
  1588. nbuf = NULL;
  1589. done:
  1590. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1591. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1592. hif_pm_runtime_put(soc->hif_handle);
  1593. } else {
  1594. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1595. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1596. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1597. }
  1598. return nbuf;
  1599. }
  1600. /**
  1601. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1602. * for SG frames
  1603. * @vdev: DP vdev handle
  1604. * @nbuf: skb
  1605. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1606. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1607. *
  1608. * Return: NULL on success,
  1609. * nbuf when it fails to send
  1610. */
  1611. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1612. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1613. {
  1614. uint32_t cur_frag, nr_frags;
  1615. qdf_dma_addr_t paddr;
  1616. struct dp_tx_sg_info_s *sg_info;
  1617. sg_info = &msdu_info->u.sg_info;
  1618. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1619. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1620. QDF_DMA_TO_DEVICE)) {
  1621. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1622. "dma map error");
  1623. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1624. qdf_nbuf_free(nbuf);
  1625. return NULL;
  1626. }
  1627. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1628. seg_info->frags[0].paddr_lo = paddr;
  1629. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1630. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1631. seg_info->frags[0].vaddr = (void *) nbuf;
  1632. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1633. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1634. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1635. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1636. "frag dma map error");
  1637. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1638. qdf_nbuf_free(nbuf);
  1639. return NULL;
  1640. }
  1641. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1642. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1643. seg_info->frags[cur_frag + 1].paddr_hi =
  1644. ((uint64_t) paddr) >> 32;
  1645. seg_info->frags[cur_frag + 1].len =
  1646. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1647. }
  1648. seg_info->frag_cnt = (cur_frag + 1);
  1649. seg_info->total_len = qdf_nbuf_len(nbuf);
  1650. seg_info->next = NULL;
  1651. sg_info->curr_seg = seg_info;
  1652. msdu_info->frm_type = dp_tx_frm_sg;
  1653. msdu_info->num_seg = 1;
  1654. return nbuf;
  1655. }
  1656. /**
  1657. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1658. * @vdev: DP vdev handle
  1659. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1660. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1661. *
  1662. * Return: NULL on failure,
  1663. * nbuf when extracted successfully
  1664. */
  1665. static
  1666. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1667. struct dp_tx_msdu_info_s *msdu_info,
  1668. uint16_t ppdu_cookie)
  1669. {
  1670. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1671. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1672. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1673. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1674. (msdu_info->meta_data[5], 1);
  1675. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1676. (msdu_info->meta_data[5], 1);
  1677. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1678. (msdu_info->meta_data[6], ppdu_cookie);
  1679. msdu_info->exception_fw = 1;
  1680. msdu_info->is_tx_sniffer = 1;
  1681. }
  1682. #ifdef MESH_MODE_SUPPORT
  1683. /**
  1684. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1685. and prepare msdu_info for mesh frames.
  1686. * @vdev: DP vdev handle
  1687. * @nbuf: skb
  1688. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1689. *
  1690. * Return: NULL on failure,
  1691. * nbuf when extracted successfully
  1692. */
  1693. static
  1694. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1695. struct dp_tx_msdu_info_s *msdu_info)
  1696. {
  1697. struct meta_hdr_s *mhdr;
  1698. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1699. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1700. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1701. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1702. msdu_info->exception_fw = 0;
  1703. goto remove_meta_hdr;
  1704. }
  1705. msdu_info->exception_fw = 1;
  1706. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1707. meta_data->host_tx_desc_pool = 1;
  1708. meta_data->update_peer_cache = 1;
  1709. meta_data->learning_frame = 1;
  1710. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1711. meta_data->power = mhdr->power;
  1712. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1713. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1714. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1715. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1716. meta_data->dyn_bw = 1;
  1717. meta_data->valid_pwr = 1;
  1718. meta_data->valid_mcs_mask = 1;
  1719. meta_data->valid_nss_mask = 1;
  1720. meta_data->valid_preamble_type = 1;
  1721. meta_data->valid_retries = 1;
  1722. meta_data->valid_bw_info = 1;
  1723. }
  1724. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1725. meta_data->encrypt_type = 0;
  1726. meta_data->valid_encrypt_type = 1;
  1727. meta_data->learning_frame = 0;
  1728. }
  1729. meta_data->valid_key_flags = 1;
  1730. meta_data->key_flags = (mhdr->keyix & 0x3);
  1731. remove_meta_hdr:
  1732. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1733. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1734. "qdf_nbuf_pull_head failed");
  1735. qdf_nbuf_free(nbuf);
  1736. return NULL;
  1737. }
  1738. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1740. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1741. " tid %d to_fw %d",
  1742. __func__, msdu_info->meta_data[0],
  1743. msdu_info->meta_data[1],
  1744. msdu_info->meta_data[2],
  1745. msdu_info->meta_data[3],
  1746. msdu_info->meta_data[4],
  1747. msdu_info->meta_data[5],
  1748. msdu_info->tid, msdu_info->exception_fw);
  1749. return nbuf;
  1750. }
  1751. #else
  1752. static
  1753. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1754. struct dp_tx_msdu_info_s *msdu_info)
  1755. {
  1756. return nbuf;
  1757. }
  1758. #endif
  1759. /**
  1760. * dp_check_exc_metadata() - Checks if parameters are valid
  1761. * @tx_exc - holds all exception path parameters
  1762. *
  1763. * Returns true when all the parameters are valid else false
  1764. *
  1765. */
  1766. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1767. {
  1768. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1769. HTT_INVALID_TID);
  1770. bool invalid_encap_type =
  1771. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1772. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1773. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1774. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1775. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1776. tx_exc->ppdu_cookie == 0);
  1777. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1778. invalid_cookie) {
  1779. return false;
  1780. }
  1781. return true;
  1782. }
  1783. /**
  1784. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1785. * @vap_dev: DP vdev handle
  1786. * @nbuf: skb
  1787. * @tx_exc_metadata: Handle that holds exception path meta data
  1788. *
  1789. * Entry point for Core Tx layer (DP_TX) invoked from
  1790. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1791. *
  1792. * Return: NULL on success,
  1793. * nbuf when it fails to send
  1794. */
  1795. qdf_nbuf_t
  1796. dp_tx_send_exception(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf,
  1797. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1798. {
  1799. qdf_ether_header_t *eh = NULL;
  1800. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1801. struct dp_tx_msdu_info_s msdu_info;
  1802. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1803. if (!tx_exc_metadata)
  1804. goto fail;
  1805. msdu_info.tid = tx_exc_metadata->tid;
  1806. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1807. dp_verbose_debug("skb %pM", nbuf->data);
  1808. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1809. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1810. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1811. "Invalid parameters in exception path");
  1812. goto fail;
  1813. }
  1814. /* Basic sanity checks for unsupported packets */
  1815. /* MESH mode */
  1816. if (qdf_unlikely(vdev->mesh_vdev)) {
  1817. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1818. "Mesh mode is not supported in exception path");
  1819. goto fail;
  1820. }
  1821. /* TSO or SG */
  1822. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1823. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1824. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1825. "TSO and SG are not supported in exception path");
  1826. goto fail;
  1827. }
  1828. /* RAW */
  1829. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1830. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1831. "Raw frame is not supported in exception path");
  1832. goto fail;
  1833. }
  1834. /* Mcast enhancement*/
  1835. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1836. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1837. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1838. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1839. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1840. }
  1841. }
  1842. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1843. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1844. qdf_nbuf_len(nbuf));
  1845. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1846. tx_exc_metadata->ppdu_cookie);
  1847. }
  1848. /*
  1849. * Get HW Queue to use for this frame.
  1850. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1851. * dedicated for data and 1 for command.
  1852. * "queue_id" maps to one hardware ring.
  1853. * With each ring, we also associate a unique Tx descriptor pool
  1854. * to minimize lock contention for these resources.
  1855. */
  1856. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1857. /* Single linear frame */
  1858. /*
  1859. * If nbuf is a simple linear frame, use send_single function to
  1860. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1861. * SRNG. There is no need to setup a MSDU extension descriptor.
  1862. */
  1863. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1864. tx_exc_metadata->peer_id, tx_exc_metadata);
  1865. return nbuf;
  1866. fail:
  1867. dp_verbose_debug("pkt send failed");
  1868. return nbuf;
  1869. }
  1870. /**
  1871. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1872. * @vap_dev: DP vdev handle
  1873. * @nbuf: skb
  1874. *
  1875. * Entry point for Core Tx layer (DP_TX) invoked from
  1876. * hard_start_xmit in OSIF/HDD
  1877. *
  1878. * Return: NULL on success,
  1879. * nbuf when it fails to send
  1880. */
  1881. #ifdef MESH_MODE_SUPPORT
  1882. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1883. {
  1884. struct meta_hdr_s *mhdr;
  1885. qdf_nbuf_t nbuf_mesh = NULL;
  1886. qdf_nbuf_t nbuf_clone = NULL;
  1887. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1888. uint8_t no_enc_frame = 0;
  1889. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1890. if (!nbuf_mesh) {
  1891. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1892. "qdf_nbuf_unshare failed");
  1893. return nbuf;
  1894. }
  1895. nbuf = nbuf_mesh;
  1896. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1897. if ((vdev->sec_type != cdp_sec_type_none) &&
  1898. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1899. no_enc_frame = 1;
  1900. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1901. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1902. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1903. !no_enc_frame) {
  1904. nbuf_clone = qdf_nbuf_clone(nbuf);
  1905. if (!nbuf_clone) {
  1906. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1907. "qdf_nbuf_clone failed");
  1908. return nbuf;
  1909. }
  1910. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1911. }
  1912. if (nbuf_clone) {
  1913. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1914. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1915. } else {
  1916. qdf_nbuf_free(nbuf_clone);
  1917. }
  1918. }
  1919. if (no_enc_frame)
  1920. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1921. else
  1922. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1923. nbuf = dp_tx_send(vap_dev, nbuf);
  1924. if ((!nbuf) && no_enc_frame) {
  1925. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1926. }
  1927. return nbuf;
  1928. }
  1929. #else
  1930. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1931. {
  1932. return dp_tx_send(vap_dev, nbuf);
  1933. }
  1934. #endif
  1935. /**
  1936. * dp_tx_send() - Transmit a frame on a given VAP
  1937. * @vap_dev: DP vdev handle
  1938. * @nbuf: skb
  1939. *
  1940. * Entry point for Core Tx layer (DP_TX) invoked from
  1941. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1942. * cases
  1943. *
  1944. * Return: NULL on success,
  1945. * nbuf when it fails to send
  1946. */
  1947. qdf_nbuf_t dp_tx_send(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1948. {
  1949. qdf_ether_header_t *eh = NULL;
  1950. struct dp_tx_msdu_info_s msdu_info;
  1951. struct dp_tx_seg_info_s seg_info;
  1952. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1953. uint16_t peer_id = HTT_INVALID_PEER;
  1954. qdf_nbuf_t nbuf_mesh = NULL;
  1955. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1956. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1957. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1958. dp_verbose_debug("skb %pM", nbuf->data);
  1959. /*
  1960. * Set Default Host TID value to invalid TID
  1961. * (TID override disabled)
  1962. */
  1963. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1964. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1965. if (qdf_unlikely(vdev->mesh_vdev)) {
  1966. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1967. &msdu_info);
  1968. if (!nbuf_mesh) {
  1969. dp_verbose_debug("Extracting mesh metadata failed");
  1970. return nbuf;
  1971. }
  1972. nbuf = nbuf_mesh;
  1973. }
  1974. /*
  1975. * Get HW Queue to use for this frame.
  1976. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1977. * dedicated for data and 1 for command.
  1978. * "queue_id" maps to one hardware ring.
  1979. * With each ring, we also associate a unique Tx descriptor pool
  1980. * to minimize lock contention for these resources.
  1981. */
  1982. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1983. /*
  1984. * TCL H/W supports 2 DSCP-TID mapping tables.
  1985. * Table 1 - Default DSCP-TID mapping table
  1986. * Table 2 - 1 DSCP-TID override table
  1987. *
  1988. * If we need a different DSCP-TID mapping for this vap,
  1989. * call tid_classify to extract DSCP/ToS from frame and
  1990. * map to a TID and store in msdu_info. This is later used
  1991. * to fill in TCL Input descriptor (per-packet TID override).
  1992. */
  1993. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1994. /*
  1995. * Classify the frame and call corresponding
  1996. * "prepare" function which extracts the segment (TSO)
  1997. * and fragmentation information (for TSO , SG, ME, or Raw)
  1998. * into MSDU_INFO structure which is later used to fill
  1999. * SW and HW descriptors.
  2000. */
  2001. if (qdf_nbuf_is_tso(nbuf)) {
  2002. dp_verbose_debug("TSO frame %pK", vdev);
  2003. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2004. qdf_nbuf_len(nbuf));
  2005. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2006. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2007. qdf_nbuf_len(nbuf));
  2008. return nbuf;
  2009. }
  2010. goto send_multiple;
  2011. }
  2012. /* SG */
  2013. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2014. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2015. if (!nbuf)
  2016. return NULL;
  2017. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2018. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2019. qdf_nbuf_len(nbuf));
  2020. goto send_multiple;
  2021. }
  2022. #ifdef ATH_SUPPORT_IQUE
  2023. /* Mcast to Ucast Conversion*/
  2024. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2025. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2026. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2027. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2028. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2029. DP_STATS_INC_PKT(vdev,
  2030. tx_i.mcast_en.mcast_pkt, 1,
  2031. qdf_nbuf_len(nbuf));
  2032. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2033. QDF_STATUS_SUCCESS) {
  2034. return NULL;
  2035. }
  2036. }
  2037. }
  2038. #endif
  2039. /* RAW */
  2040. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2041. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2042. if (!nbuf)
  2043. return NULL;
  2044. dp_verbose_debug("Raw frame %pK", vdev);
  2045. goto send_multiple;
  2046. }
  2047. /* Single linear frame */
  2048. /*
  2049. * If nbuf is a simple linear frame, use send_single function to
  2050. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2051. * SRNG. There is no need to setup a MSDU extension descriptor.
  2052. */
  2053. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2054. return nbuf;
  2055. send_multiple:
  2056. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2057. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2058. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2059. return nbuf;
  2060. }
  2061. /**
  2062. * dp_tx_reinject_handler() - Tx Reinject Handler
  2063. * @tx_desc: software descriptor head pointer
  2064. * @status : Tx completion status from HTT descriptor
  2065. *
  2066. * This function reinjects frames back to Target.
  2067. * Todo - Host queue needs to be added
  2068. *
  2069. * Return: none
  2070. */
  2071. static
  2072. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2073. {
  2074. struct dp_vdev *vdev;
  2075. struct dp_peer *peer = NULL;
  2076. uint32_t peer_id = HTT_INVALID_PEER;
  2077. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2078. qdf_nbuf_t nbuf_copy = NULL;
  2079. struct dp_tx_msdu_info_s msdu_info;
  2080. struct dp_peer *sa_peer = NULL;
  2081. struct dp_ast_entry *ast_entry = NULL;
  2082. struct dp_soc *soc = NULL;
  2083. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2084. #ifdef WDS_VENDOR_EXTENSION
  2085. int is_mcast = 0, is_ucast = 0;
  2086. int num_peers_3addr = 0;
  2087. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2088. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2089. #endif
  2090. vdev = tx_desc->vdev;
  2091. soc = vdev->pdev->soc;
  2092. qdf_assert(vdev);
  2093. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2094. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2095. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2096. "%s Tx reinject path", __func__);
  2097. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2098. qdf_nbuf_len(tx_desc->nbuf));
  2099. qdf_spin_lock_bh(&(soc->ast_lock));
  2100. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2101. (soc,
  2102. (uint8_t *)(eh->ether_shost),
  2103. vdev->pdev->pdev_id);
  2104. if (ast_entry)
  2105. sa_peer = ast_entry->peer;
  2106. qdf_spin_unlock_bh(&(soc->ast_lock));
  2107. #ifdef WDS_VENDOR_EXTENSION
  2108. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2109. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2110. } else {
  2111. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2112. }
  2113. is_ucast = !is_mcast;
  2114. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2115. if (peer->bss_peer)
  2116. continue;
  2117. /* Detect wds peers that use 3-addr framing for mcast.
  2118. * if there are any, the bss_peer is used to send the
  2119. * the mcast frame using 3-addr format. all wds enabled
  2120. * peers that use 4-addr framing for mcast frames will
  2121. * be duplicated and sent as 4-addr frames below.
  2122. */
  2123. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2124. num_peers_3addr = 1;
  2125. break;
  2126. }
  2127. }
  2128. #endif
  2129. if (qdf_unlikely(vdev->mesh_vdev)) {
  2130. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2131. } else {
  2132. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2133. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2134. #ifdef WDS_VENDOR_EXTENSION
  2135. /*
  2136. * . if 3-addr STA, then send on BSS Peer
  2137. * . if Peer WDS enabled and accept 4-addr mcast,
  2138. * send mcast on that peer only
  2139. * . if Peer WDS enabled and accept 4-addr ucast,
  2140. * send ucast on that peer only
  2141. */
  2142. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2143. (peer->wds_enabled &&
  2144. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2145. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2146. #else
  2147. ((peer->bss_peer &&
  2148. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2149. peer->nawds_enabled)) {
  2150. #endif
  2151. peer_id = DP_INVALID_PEER;
  2152. if (peer->nawds_enabled) {
  2153. peer_id = peer->peer_ids[0];
  2154. if (sa_peer == peer) {
  2155. QDF_TRACE(
  2156. QDF_MODULE_ID_DP,
  2157. QDF_TRACE_LEVEL_DEBUG,
  2158. " %s: multicast packet",
  2159. __func__);
  2160. DP_STATS_INC(peer,
  2161. tx.nawds_mcast_drop, 1);
  2162. continue;
  2163. }
  2164. }
  2165. nbuf_copy = qdf_nbuf_copy(nbuf);
  2166. if (!nbuf_copy) {
  2167. QDF_TRACE(QDF_MODULE_ID_DP,
  2168. QDF_TRACE_LEVEL_DEBUG,
  2169. FL("nbuf copy failed"));
  2170. break;
  2171. }
  2172. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2173. nbuf_copy,
  2174. &msdu_info,
  2175. peer_id,
  2176. NULL);
  2177. if (nbuf_copy) {
  2178. QDF_TRACE(QDF_MODULE_ID_DP,
  2179. QDF_TRACE_LEVEL_DEBUG,
  2180. FL("pkt send failed"));
  2181. qdf_nbuf_free(nbuf_copy);
  2182. } else {
  2183. if (peer_id != DP_INVALID_PEER)
  2184. DP_STATS_INC_PKT(peer,
  2185. tx.nawds_mcast,
  2186. 1, qdf_nbuf_len(nbuf));
  2187. }
  2188. }
  2189. }
  2190. }
  2191. if (vdev->nawds_enabled) {
  2192. peer_id = DP_INVALID_PEER;
  2193. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2194. 1, qdf_nbuf_len(nbuf));
  2195. nbuf = dp_tx_send_msdu_single(vdev,
  2196. nbuf,
  2197. &msdu_info,
  2198. peer_id, NULL);
  2199. if (nbuf) {
  2200. QDF_TRACE(QDF_MODULE_ID_DP,
  2201. QDF_TRACE_LEVEL_DEBUG,
  2202. FL("pkt send failed"));
  2203. qdf_nbuf_free(nbuf);
  2204. }
  2205. } else
  2206. qdf_nbuf_free(nbuf);
  2207. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2208. }
  2209. /**
  2210. * dp_tx_inspect_handler() - Tx Inspect Handler
  2211. * @tx_desc: software descriptor head pointer
  2212. * @status : Tx completion status from HTT descriptor
  2213. *
  2214. * Handles Tx frames sent back to Host for inspection
  2215. * (ProxyARP)
  2216. *
  2217. * Return: none
  2218. */
  2219. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2220. {
  2221. struct dp_soc *soc;
  2222. struct dp_pdev *pdev = tx_desc->pdev;
  2223. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2224. "%s Tx inspect path",
  2225. __func__);
  2226. qdf_assert(pdev);
  2227. soc = pdev->soc;
  2228. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2229. qdf_nbuf_len(tx_desc->nbuf));
  2230. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2231. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2232. }
  2233. #ifdef FEATURE_PERPKT_INFO
  2234. /**
  2235. * dp_get_completion_indication_for_stack() - send completion to stack
  2236. * @soc : dp_soc handle
  2237. * @pdev: dp_pdev handle
  2238. * @peer: dp peer handle
  2239. * @ts: transmit completion status structure
  2240. * @netbuf: Buffer pointer for free
  2241. *
  2242. * This function is used for indication whether buffer needs to be
  2243. * sent to stack for freeing or not
  2244. */
  2245. QDF_STATUS
  2246. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2247. struct dp_pdev *pdev,
  2248. struct dp_peer *peer,
  2249. struct hal_tx_completion_status *ts,
  2250. qdf_nbuf_t netbuf,
  2251. uint64_t time_latency)
  2252. {
  2253. struct tx_capture_hdr *ppdu_hdr;
  2254. uint16_t peer_id = ts->peer_id;
  2255. uint32_t ppdu_id = ts->ppdu_id;
  2256. uint8_t first_msdu = ts->first_msdu;
  2257. uint8_t last_msdu = ts->last_msdu;
  2258. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2259. !pdev->latency_capture_enable))
  2260. return QDF_STATUS_E_NOSUPPORT;
  2261. if (!peer) {
  2262. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2263. FL("Peer Invalid"));
  2264. return QDF_STATUS_E_INVAL;
  2265. }
  2266. if (pdev->mcopy_mode) {
  2267. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2268. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2269. return QDF_STATUS_E_INVAL;
  2270. }
  2271. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2272. pdev->m_copy_id.tx_peer_id = peer_id;
  2273. }
  2274. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2275. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2276. FL("No headroom"));
  2277. return QDF_STATUS_E_NOMEM;
  2278. }
  2279. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2280. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2281. QDF_MAC_ADDR_SIZE);
  2282. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2283. QDF_MAC_ADDR_SIZE);
  2284. ppdu_hdr->ppdu_id = ppdu_id;
  2285. ppdu_hdr->peer_id = peer_id;
  2286. ppdu_hdr->first_msdu = first_msdu;
  2287. ppdu_hdr->last_msdu = last_msdu;
  2288. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2289. ppdu_hdr->tsf = ts->tsf;
  2290. ppdu_hdr->time_latency = time_latency;
  2291. }
  2292. return QDF_STATUS_SUCCESS;
  2293. }
  2294. /**
  2295. * dp_send_completion_to_stack() - send completion to stack
  2296. * @soc : dp_soc handle
  2297. * @pdev: dp_pdev handle
  2298. * @peer_id: peer_id of the peer for which completion came
  2299. * @ppdu_id: ppdu_id
  2300. * @netbuf: Buffer pointer for free
  2301. *
  2302. * This function is used to send completion to stack
  2303. * to free buffer
  2304. */
  2305. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2306. uint16_t peer_id, uint32_t ppdu_id,
  2307. qdf_nbuf_t netbuf)
  2308. {
  2309. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2310. netbuf, peer_id,
  2311. WDI_NO_VAL, pdev->pdev_id);
  2312. }
  2313. #else
  2314. static QDF_STATUS
  2315. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2316. struct dp_pdev *pdev,
  2317. struct dp_peer *peer,
  2318. struct hal_tx_completion_status *ts,
  2319. qdf_nbuf_t netbuf,
  2320. uint64_t time_latency)
  2321. {
  2322. return QDF_STATUS_E_NOSUPPORT;
  2323. }
  2324. static void
  2325. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2326. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2327. {
  2328. }
  2329. #endif
  2330. /**
  2331. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2332. * @soc: Soc handle
  2333. * @desc: software Tx descriptor to be processed
  2334. *
  2335. * Return: none
  2336. */
  2337. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2338. struct dp_tx_desc_s *desc)
  2339. {
  2340. struct dp_vdev *vdev = desc->vdev;
  2341. qdf_nbuf_t nbuf = desc->nbuf;
  2342. /* nbuf already freed in vdev detach path */
  2343. if (!nbuf)
  2344. return;
  2345. /* If it is TDLS mgmt, don't unmap or free the frame */
  2346. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2347. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2348. /* 0 : MSDU buffer, 1 : MLE */
  2349. if (desc->msdu_ext_desc) {
  2350. /* TSO free */
  2351. if (hal_tx_ext_desc_get_tso_enable(
  2352. desc->msdu_ext_desc->vaddr)) {
  2353. /* unmap eash TSO seg before free the nbuf */
  2354. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2355. desc->tso_num_desc);
  2356. qdf_nbuf_free(nbuf);
  2357. return;
  2358. }
  2359. }
  2360. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2361. if (qdf_unlikely(!vdev)) {
  2362. qdf_nbuf_free(nbuf);
  2363. return;
  2364. }
  2365. if (qdf_likely(!vdev->mesh_vdev))
  2366. qdf_nbuf_free(nbuf);
  2367. else {
  2368. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2369. qdf_nbuf_free(nbuf);
  2370. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2371. } else
  2372. vdev->osif_tx_free_ext((nbuf));
  2373. }
  2374. }
  2375. #ifdef MESH_MODE_SUPPORT
  2376. /**
  2377. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2378. * in mesh meta header
  2379. * @tx_desc: software descriptor head pointer
  2380. * @ts: pointer to tx completion stats
  2381. * Return: none
  2382. */
  2383. static
  2384. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2385. struct hal_tx_completion_status *ts)
  2386. {
  2387. struct meta_hdr_s *mhdr;
  2388. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2389. if (!tx_desc->msdu_ext_desc) {
  2390. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2391. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2392. "netbuf %pK offset %d",
  2393. netbuf, tx_desc->pkt_offset);
  2394. return;
  2395. }
  2396. }
  2397. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2398. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2399. "netbuf %pK offset %lu", netbuf,
  2400. sizeof(struct meta_hdr_s));
  2401. return;
  2402. }
  2403. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2404. mhdr->rssi = ts->ack_frame_rssi;
  2405. mhdr->channel = tx_desc->pdev->operating_channel;
  2406. }
  2407. #else
  2408. static
  2409. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2410. struct hal_tx_completion_status *ts)
  2411. {
  2412. }
  2413. #endif
  2414. /**
  2415. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2416. * to pass in correct fields
  2417. *
  2418. * @vdev: pdev handle
  2419. * @tx_desc: tx descriptor
  2420. * @tid: tid value
  2421. * @ring_id: TCL or WBM ring number for transmit path
  2422. * Return: none
  2423. */
  2424. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2425. struct dp_tx_desc_s *tx_desc,
  2426. uint8_t tid, uint8_t ring_id)
  2427. {
  2428. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2429. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2430. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2431. return;
  2432. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2433. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2434. timestamp_hw_enqueue = tx_desc->timestamp;
  2435. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2436. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2437. timestamp_hw_enqueue);
  2438. interframe_delay = (uint32_t)(timestamp_ingress -
  2439. vdev->prev_tx_enq_tstamp);
  2440. /*
  2441. * Delay in software enqueue
  2442. */
  2443. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2444. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2445. /*
  2446. * Delay between packet enqueued to HW and Tx completion
  2447. */
  2448. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2449. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2450. /*
  2451. * Update interframe delay stats calculated at hardstart receive point.
  2452. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2453. * interframe delay will not be calculate correctly for 1st frame.
  2454. * On the other side, this will help in avoiding extra per packet check
  2455. * of !vdev->prev_tx_enq_tstamp.
  2456. */
  2457. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2458. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2459. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2460. }
  2461. /**
  2462. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2463. * per wbm ring
  2464. *
  2465. * @tx_desc: software descriptor head pointer
  2466. * @ts: Tx completion status
  2467. * @peer: peer handle
  2468. * @ring_id: ring number
  2469. *
  2470. * Return: None
  2471. */
  2472. static inline void
  2473. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2474. struct hal_tx_completion_status *ts,
  2475. struct dp_peer *peer, uint8_t ring_id)
  2476. {
  2477. struct dp_pdev *pdev = peer->vdev->pdev;
  2478. struct dp_soc *soc = NULL;
  2479. uint8_t mcs, pkt_type;
  2480. uint8_t tid = ts->tid;
  2481. uint32_t length;
  2482. struct cdp_tid_tx_stats *tid_stats;
  2483. if (!pdev)
  2484. return;
  2485. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2486. tid = CDP_MAX_DATA_TIDS - 1;
  2487. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2488. soc = pdev->soc;
  2489. mcs = ts->mcs;
  2490. pkt_type = ts->pkt_type;
  2491. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2492. dp_err("Release source is not from TQM");
  2493. return;
  2494. }
  2495. length = qdf_nbuf_len(tx_desc->nbuf);
  2496. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2497. if (qdf_unlikely(pdev->delay_stats_flag))
  2498. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2499. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2500. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2501. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2502. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2503. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2504. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2505. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2506. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2507. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2508. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2509. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2510. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2511. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2512. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2513. /*
  2514. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2515. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2516. * are no completions for failed cases. Hence updating tx_failed from
  2517. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2518. * then this has to be removed
  2519. */
  2520. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2521. peer->stats.tx.dropped.fw_rem_notx +
  2522. peer->stats.tx.dropped.fw_rem_tx +
  2523. peer->stats.tx.dropped.age_out +
  2524. peer->stats.tx.dropped.fw_reason1 +
  2525. peer->stats.tx.dropped.fw_reason2 +
  2526. peer->stats.tx.dropped.fw_reason3;
  2527. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2528. tid_stats->tqm_status_cnt[ts->status]++;
  2529. }
  2530. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2531. return;
  2532. }
  2533. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2534. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2535. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2536. /*
  2537. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2538. * Return from here if HTT PPDU events are enabled.
  2539. */
  2540. if (!(soc->process_tx_status))
  2541. return;
  2542. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2543. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2544. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2545. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2546. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2547. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2548. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2549. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2550. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2551. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2552. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2553. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2554. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2555. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2556. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2557. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2558. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2559. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2560. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2561. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2562. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2563. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2564. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2565. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2566. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2567. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2568. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2569. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2570. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2571. &peer->stats, ts->peer_id,
  2572. UPDATE_PEER_STATS, pdev->pdev_id);
  2573. #endif
  2574. }
  2575. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2576. /**
  2577. * dp_tx_flow_pool_lock() - take flow pool lock
  2578. * @soc: core txrx main context
  2579. * @tx_desc: tx desc
  2580. *
  2581. * Return: None
  2582. */
  2583. static inline
  2584. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2585. struct dp_tx_desc_s *tx_desc)
  2586. {
  2587. struct dp_tx_desc_pool_s *pool;
  2588. uint8_t desc_pool_id;
  2589. desc_pool_id = tx_desc->pool_id;
  2590. pool = &soc->tx_desc[desc_pool_id];
  2591. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2592. }
  2593. /**
  2594. * dp_tx_flow_pool_unlock() - release flow pool lock
  2595. * @soc: core txrx main context
  2596. * @tx_desc: tx desc
  2597. *
  2598. * Return: None
  2599. */
  2600. static inline
  2601. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2602. struct dp_tx_desc_s *tx_desc)
  2603. {
  2604. struct dp_tx_desc_pool_s *pool;
  2605. uint8_t desc_pool_id;
  2606. desc_pool_id = tx_desc->pool_id;
  2607. pool = &soc->tx_desc[desc_pool_id];
  2608. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2609. }
  2610. #else
  2611. static inline
  2612. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2613. {
  2614. }
  2615. static inline
  2616. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2617. {
  2618. }
  2619. #endif
  2620. /**
  2621. * dp_tx_notify_completion() - Notify tx completion for this desc
  2622. * @soc: core txrx main context
  2623. * @tx_desc: tx desc
  2624. * @netbuf: buffer
  2625. *
  2626. * Return: none
  2627. */
  2628. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2629. struct dp_tx_desc_s *tx_desc,
  2630. qdf_nbuf_t netbuf)
  2631. {
  2632. void *osif_dev;
  2633. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2634. qdf_assert(tx_desc);
  2635. dp_tx_flow_pool_lock(soc, tx_desc);
  2636. if (!tx_desc->vdev ||
  2637. !tx_desc->vdev->osif_vdev) {
  2638. dp_tx_flow_pool_unlock(soc, tx_desc);
  2639. return;
  2640. }
  2641. osif_dev = tx_desc->vdev->osif_vdev;
  2642. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2643. dp_tx_flow_pool_unlock(soc, tx_desc);
  2644. if (tx_compl_cbk)
  2645. tx_compl_cbk(netbuf, osif_dev);
  2646. }
  2647. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2648. * @pdev: pdev handle
  2649. * @tid: tid value
  2650. * @txdesc_ts: timestamp from txdesc
  2651. * @ppdu_id: ppdu id
  2652. *
  2653. * Return: none
  2654. */
  2655. #ifdef FEATURE_PERPKT_INFO
  2656. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2657. struct dp_peer *peer,
  2658. uint8_t tid,
  2659. uint64_t txdesc_ts,
  2660. uint32_t ppdu_id)
  2661. {
  2662. uint64_t delta_ms;
  2663. struct cdp_tx_sojourn_stats *sojourn_stats;
  2664. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2665. return;
  2666. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2667. tid >= CDP_DATA_TID_MAX))
  2668. return;
  2669. if (qdf_unlikely(!pdev->sojourn_buf))
  2670. return;
  2671. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2672. qdf_nbuf_data(pdev->sojourn_buf);
  2673. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2674. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2675. txdesc_ts;
  2676. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2677. delta_ms);
  2678. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2679. sojourn_stats->num_msdus[tid] = 1;
  2680. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2681. peer->avg_sojourn_msdu[tid].internal;
  2682. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2683. pdev->sojourn_buf, HTT_INVALID_PEER,
  2684. WDI_NO_VAL, pdev->pdev_id);
  2685. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2686. sojourn_stats->num_msdus[tid] = 0;
  2687. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2688. }
  2689. #else
  2690. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2691. uint8_t tid,
  2692. uint64_t txdesc_ts,
  2693. uint32_t ppdu_id)
  2694. {
  2695. }
  2696. #endif
  2697. /**
  2698. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2699. * @soc: DP Soc handle
  2700. * @tx_desc: software Tx descriptor
  2701. * @ts : Tx completion status from HAL/HTT descriptor
  2702. *
  2703. * Return: none
  2704. */
  2705. static inline void
  2706. dp_tx_comp_process_desc(struct dp_soc *soc,
  2707. struct dp_tx_desc_s *desc,
  2708. struct hal_tx_completion_status *ts,
  2709. struct dp_peer *peer)
  2710. {
  2711. uint64_t time_latency = 0;
  2712. /*
  2713. * m_copy/tx_capture modes are not supported for
  2714. * scatter gather packets
  2715. */
  2716. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2717. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2718. desc->timestamp);
  2719. }
  2720. if (!(desc->msdu_ext_desc)) {
  2721. if (QDF_STATUS_SUCCESS ==
  2722. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2723. return;
  2724. }
  2725. if (QDF_STATUS_SUCCESS ==
  2726. dp_get_completion_indication_for_stack(soc,
  2727. desc->pdev,
  2728. peer, ts,
  2729. desc->nbuf,
  2730. time_latency)) {
  2731. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2732. QDF_DMA_TO_DEVICE);
  2733. dp_send_completion_to_stack(soc,
  2734. desc->pdev,
  2735. ts->peer_id,
  2736. ts->ppdu_id,
  2737. desc->nbuf);
  2738. return;
  2739. }
  2740. }
  2741. dp_tx_comp_free_buf(soc, desc);
  2742. }
  2743. /**
  2744. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2745. * @tx_desc: software descriptor head pointer
  2746. * @ts: Tx completion status
  2747. * @peer: peer handle
  2748. * @ring_id: ring number
  2749. *
  2750. * Return: none
  2751. */
  2752. static inline
  2753. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2754. struct hal_tx_completion_status *ts,
  2755. struct dp_peer *peer, uint8_t ring_id)
  2756. {
  2757. uint32_t length;
  2758. qdf_ether_header_t *eh;
  2759. struct dp_soc *soc = NULL;
  2760. struct dp_vdev *vdev = tx_desc->vdev;
  2761. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2762. if (!vdev || !nbuf) {
  2763. dp_info_rl("invalid tx descriptor. vdev or nbuf NULL");
  2764. goto out;
  2765. }
  2766. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2767. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2768. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2769. QDF_TRACE_DEFAULT_PDEV_ID,
  2770. qdf_nbuf_data_addr(nbuf),
  2771. sizeof(qdf_nbuf_data(nbuf)),
  2772. tx_desc->id,
  2773. ts->status));
  2774. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2775. "-------------------- \n"
  2776. "Tx Completion Stats: \n"
  2777. "-------------------- \n"
  2778. "ack_frame_rssi = %d \n"
  2779. "first_msdu = %d \n"
  2780. "last_msdu = %d \n"
  2781. "msdu_part_of_amsdu = %d \n"
  2782. "rate_stats valid = %d \n"
  2783. "bw = %d \n"
  2784. "pkt_type = %d \n"
  2785. "stbc = %d \n"
  2786. "ldpc = %d \n"
  2787. "sgi = %d \n"
  2788. "mcs = %d \n"
  2789. "ofdma = %d \n"
  2790. "tones_in_ru = %d \n"
  2791. "tsf = %d \n"
  2792. "ppdu_id = %d \n"
  2793. "transmit_cnt = %d \n"
  2794. "tid = %d \n"
  2795. "peer_id = %d\n",
  2796. ts->ack_frame_rssi, ts->first_msdu,
  2797. ts->last_msdu, ts->msdu_part_of_amsdu,
  2798. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2799. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2800. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2801. ts->transmit_cnt, ts->tid, ts->peer_id);
  2802. soc = vdev->pdev->soc;
  2803. /* Update SoC level stats */
  2804. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2805. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2806. /* Update per-packet stats for mesh mode */
  2807. if (qdf_unlikely(vdev->mesh_vdev) &&
  2808. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2809. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2810. length = qdf_nbuf_len(nbuf);
  2811. /* Update peer level stats */
  2812. if (!peer) {
  2813. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2814. "peer is null or deletion in progress");
  2815. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2816. goto out;
  2817. }
  2818. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2819. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2820. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2821. if ((peer->vdev->tx_encap_type ==
  2822. htt_cmn_pkt_type_ethernet) &&
  2823. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2824. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2825. }
  2826. }
  2827. } else {
  2828. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2829. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2830. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2831. }
  2832. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2833. #ifdef QCA_SUPPORT_RDK_STATS
  2834. if (soc->wlanstats_enabled)
  2835. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2836. tx_desc->timestamp,
  2837. ts->ppdu_id);
  2838. #endif
  2839. out:
  2840. return;
  2841. }
  2842. /**
  2843. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2844. * @soc: core txrx main context
  2845. * @comp_head: software descriptor head pointer
  2846. * @ring_id: ring number
  2847. *
  2848. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2849. * and release the software descriptors after processing is complete
  2850. *
  2851. * Return: none
  2852. */
  2853. static void
  2854. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2855. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2856. {
  2857. struct dp_tx_desc_s *desc;
  2858. struct dp_tx_desc_s *next;
  2859. struct hal_tx_completion_status ts = {0};
  2860. struct dp_peer *peer;
  2861. qdf_nbuf_t netbuf;
  2862. desc = comp_head;
  2863. while (desc) {
  2864. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2865. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2866. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2867. netbuf = desc->nbuf;
  2868. /* check tx complete notification */
  2869. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2870. dp_tx_notify_completion(soc, desc, netbuf);
  2871. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2872. if (peer)
  2873. dp_peer_unref_del_find_by_id(peer);
  2874. next = desc->next;
  2875. dp_tx_desc_release(desc, desc->pool_id);
  2876. desc = next;
  2877. }
  2878. }
  2879. /**
  2880. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2881. * @tx_desc: software descriptor head pointer
  2882. * @status : Tx completion status from HTT descriptor
  2883. * @ring_id: ring number
  2884. *
  2885. * This function will process HTT Tx indication messages from Target
  2886. *
  2887. * Return: none
  2888. */
  2889. static
  2890. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2891. uint8_t ring_id)
  2892. {
  2893. uint8_t tx_status;
  2894. struct dp_pdev *pdev;
  2895. struct dp_vdev *vdev;
  2896. struct dp_soc *soc;
  2897. struct hal_tx_completion_status ts = {0};
  2898. uint32_t *htt_desc = (uint32_t *)status;
  2899. struct dp_peer *peer;
  2900. struct cdp_tid_tx_stats *tid_stats = NULL;
  2901. struct htt_soc *htt_handle;
  2902. qdf_assert(tx_desc->pdev);
  2903. pdev = tx_desc->pdev;
  2904. vdev = tx_desc->vdev;
  2905. soc = pdev->soc;
  2906. if (!vdev)
  2907. return;
  2908. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2909. htt_handle = (struct htt_soc *)soc->htt_handle;
  2910. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2911. switch (tx_status) {
  2912. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2913. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2914. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2915. {
  2916. uint8_t tid;
  2917. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2918. ts.peer_id =
  2919. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2920. htt_desc[2]);
  2921. ts.tid =
  2922. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2923. htt_desc[2]);
  2924. } else {
  2925. ts.peer_id = HTT_INVALID_PEER;
  2926. ts.tid = HTT_INVALID_TID;
  2927. }
  2928. ts.ppdu_id =
  2929. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2930. htt_desc[1]);
  2931. ts.ack_frame_rssi =
  2932. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2933. htt_desc[1]);
  2934. ts.first_msdu = 1;
  2935. ts.last_msdu = 1;
  2936. tid = ts.tid;
  2937. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2938. tid = CDP_MAX_DATA_TIDS - 1;
  2939. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2940. if (qdf_unlikely(pdev->delay_stats_flag))
  2941. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2942. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  2943. tid_stats->htt_status_cnt[tx_status]++;
  2944. }
  2945. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2946. if (qdf_likely(peer))
  2947. dp_peer_unref_del_find_by_id(peer);
  2948. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2949. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2950. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2951. break;
  2952. }
  2953. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2954. {
  2955. dp_tx_reinject_handler(tx_desc, status);
  2956. break;
  2957. }
  2958. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2959. {
  2960. dp_tx_inspect_handler(tx_desc, status);
  2961. break;
  2962. }
  2963. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2964. {
  2965. dp_tx_mec_handler(vdev, status);
  2966. break;
  2967. }
  2968. default:
  2969. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2970. "%s Invalid HTT tx_status %d\n",
  2971. __func__, tx_status);
  2972. break;
  2973. }
  2974. }
  2975. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2976. static inline
  2977. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2978. {
  2979. bool limit_hit = false;
  2980. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2981. limit_hit =
  2982. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2983. if (limit_hit)
  2984. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2985. return limit_hit;
  2986. }
  2987. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2988. {
  2989. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2990. }
  2991. #else
  2992. static inline
  2993. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2994. {
  2995. return false;
  2996. }
  2997. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2998. {
  2999. return false;
  3000. }
  3001. #endif
  3002. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3003. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3004. uint32_t quota)
  3005. {
  3006. void *tx_comp_hal_desc;
  3007. uint8_t buffer_src;
  3008. uint8_t pool_id;
  3009. uint32_t tx_desc_id;
  3010. struct dp_tx_desc_s *tx_desc = NULL;
  3011. struct dp_tx_desc_s *head_desc = NULL;
  3012. struct dp_tx_desc_s *tail_desc = NULL;
  3013. uint32_t num_processed = 0;
  3014. uint32_t count = 0;
  3015. bool force_break = false;
  3016. DP_HIST_INIT();
  3017. more_data:
  3018. /* Re-initialize local variables to be re-used */
  3019. head_desc = NULL;
  3020. tail_desc = NULL;
  3021. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3022. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3023. return 0;
  3024. }
  3025. /* Find head descriptor from completion ring */
  3026. while (qdf_likely(tx_comp_hal_desc =
  3027. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  3028. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3029. /* If this buffer was not released by TQM or FW, then it is not
  3030. * Tx completion indication, assert */
  3031. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3032. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3033. uint8_t wbm_internal_error;
  3034. dp_err_rl(
  3035. "Tx comp release_src != TQM | FW but from %d",
  3036. buffer_src);
  3037. hal_dump_comp_desc(tx_comp_hal_desc);
  3038. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3039. /* When WBM sees NULL buffer_addr_info in any of
  3040. * ingress rings it sends an error indication,
  3041. * with wbm_internal_error=1, to a specific ring.
  3042. * The WBM2SW ring used to indicate these errors is
  3043. * fixed in HW, and that ring is being used as Tx
  3044. * completion ring. These errors are not related to
  3045. * Tx completions, and should just be ignored
  3046. */
  3047. wbm_internal_error =
  3048. hal_get_wbm_internal_error(tx_comp_hal_desc);
  3049. if (wbm_internal_error) {
  3050. dp_err_rl("Tx comp wbm_internal_error!!");
  3051. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3052. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3053. buffer_src)
  3054. dp_handle_wbm_internal_error(
  3055. soc,
  3056. tx_comp_hal_desc,
  3057. hal_tx_comp_get_buffer_type(
  3058. tx_comp_hal_desc));
  3059. } else {
  3060. dp_err_rl("Tx comp wbm_internal_error false");
  3061. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3062. }
  3063. continue;
  3064. }
  3065. /* Get descriptor id */
  3066. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3067. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3068. DP_TX_DESC_ID_POOL_OS;
  3069. /* Find Tx descriptor */
  3070. tx_desc = dp_tx_desc_find(soc, pool_id,
  3071. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3072. DP_TX_DESC_ID_PAGE_OS,
  3073. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3074. DP_TX_DESC_ID_OFFSET_OS);
  3075. /*
  3076. * If the descriptor is already freed in vdev_detach,
  3077. * continue to next descriptor
  3078. */
  3079. if (!tx_desc->vdev && !tx_desc->flags) {
  3080. QDF_TRACE(QDF_MODULE_ID_DP,
  3081. QDF_TRACE_LEVEL_INFO,
  3082. "Descriptor freed in vdev_detach %d",
  3083. tx_desc_id);
  3084. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3085. count++;
  3086. continue;
  3087. }
  3088. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3089. QDF_TRACE(QDF_MODULE_ID_DP,
  3090. QDF_TRACE_LEVEL_INFO,
  3091. "pdev in down state %d",
  3092. tx_desc_id);
  3093. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3094. count++;
  3095. dp_tx_comp_free_buf(soc, tx_desc);
  3096. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3097. continue;
  3098. }
  3099. /*
  3100. * If the release source is FW, process the HTT status
  3101. */
  3102. if (qdf_unlikely(buffer_src ==
  3103. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3104. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3105. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3106. htt_tx_status);
  3107. dp_tx_process_htt_completion(tx_desc,
  3108. htt_tx_status, ring_id);
  3109. } else {
  3110. /* Pool id is not matching. Error */
  3111. if (tx_desc->pool_id != pool_id) {
  3112. QDF_TRACE(QDF_MODULE_ID_DP,
  3113. QDF_TRACE_LEVEL_FATAL,
  3114. "Tx Comp pool id %d not matched %d",
  3115. pool_id, tx_desc->pool_id);
  3116. qdf_assert_always(0);
  3117. }
  3118. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3119. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3120. QDF_TRACE(QDF_MODULE_ID_DP,
  3121. QDF_TRACE_LEVEL_FATAL,
  3122. "Txdesc invalid, flgs = %x,id = %d",
  3123. tx_desc->flags, tx_desc_id);
  3124. qdf_assert_always(0);
  3125. }
  3126. /* First ring descriptor on the cycle */
  3127. if (!head_desc) {
  3128. head_desc = tx_desc;
  3129. tail_desc = tx_desc;
  3130. }
  3131. tail_desc->next = tx_desc;
  3132. tx_desc->next = NULL;
  3133. tail_desc = tx_desc;
  3134. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3135. /* Collect hw completion contents */
  3136. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3137. &tx_desc->comp, 1);
  3138. }
  3139. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3140. /*
  3141. * Processed packet count is more than given quota
  3142. * stop to processing
  3143. */
  3144. if (num_processed >= quota) {
  3145. force_break = true;
  3146. break;
  3147. }
  3148. count++;
  3149. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3150. break;
  3151. }
  3152. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3153. /* Process the reaped descriptors */
  3154. if (head_desc)
  3155. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3156. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3157. if (!force_break &&
  3158. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3159. hal_ring_hdl)) {
  3160. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3161. if (!hif_exec_should_yield(soc->hif_handle,
  3162. int_ctx->dp_intr_id))
  3163. goto more_data;
  3164. }
  3165. }
  3166. DP_TX_HIST_STATS_PER_PDEV();
  3167. return num_processed;
  3168. }
  3169. #ifdef FEATURE_WLAN_TDLS
  3170. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3171. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3172. {
  3173. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3174. struct dp_vdev *vdev = dp_get_vdev_from_soc_vdev_id_wifi3(soc, vdev_id);
  3175. if (!vdev) {
  3176. dp_err("vdev handle for id %d is NULL", vdev_id);
  3177. return NULL;
  3178. }
  3179. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3180. vdev->is_tdls_frame = true;
  3181. return dp_tx_send(dp_vdev_to_cdp_vdev(vdev), msdu_list);
  3182. }
  3183. #endif
  3184. /**
  3185. * dp_tx_vdev_attach() - attach vdev to dp tx
  3186. * @vdev: virtual device instance
  3187. *
  3188. * Return: QDF_STATUS_SUCCESS: success
  3189. * QDF_STATUS_E_RESOURCES: Error return
  3190. */
  3191. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3192. {
  3193. /*
  3194. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3195. */
  3196. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3197. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3198. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3199. vdev->vdev_id);
  3200. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3201. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3202. /*
  3203. * Set HTT Extension Valid bit to 0 by default
  3204. */
  3205. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3206. dp_tx_vdev_update_search_flags(vdev);
  3207. return QDF_STATUS_SUCCESS;
  3208. }
  3209. #ifndef FEATURE_WDS
  3210. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3211. {
  3212. return false;
  3213. }
  3214. #endif
  3215. /**
  3216. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3217. * @vdev: virtual device instance
  3218. *
  3219. * Return: void
  3220. *
  3221. */
  3222. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3223. {
  3224. struct dp_soc *soc = vdev->pdev->soc;
  3225. /*
  3226. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3227. * for TDLS link
  3228. *
  3229. * Enable AddrY (SA based search) only for non-WDS STA and
  3230. * ProxySTA VAP (in HKv1) modes.
  3231. *
  3232. * In all other VAP modes, only DA based search should be
  3233. * enabled
  3234. */
  3235. if (vdev->opmode == wlan_op_mode_sta &&
  3236. vdev->tdls_link_connected)
  3237. vdev->hal_desc_addr_search_flags =
  3238. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3239. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3240. !dp_tx_da_search_override(vdev))
  3241. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3242. else
  3243. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3244. /* Set search type only when peer map v2 messaging is enabled
  3245. * as we will have the search index (AST hash) only when v2 is
  3246. * enabled
  3247. */
  3248. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3249. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3250. else
  3251. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3252. }
  3253. static inline bool
  3254. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3255. struct dp_vdev *vdev,
  3256. struct dp_tx_desc_s *tx_desc)
  3257. {
  3258. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3259. return false;
  3260. /*
  3261. * if vdev is given, then only check whether desc
  3262. * vdev match. if vdev is NULL, then check whether
  3263. * desc pdev match.
  3264. */
  3265. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3266. }
  3267. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3268. /**
  3269. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3270. *
  3271. * @soc: Handle to DP SoC structure
  3272. * @tx_desc: pointer of one TX desc
  3273. * @desc_pool_id: TX Desc pool id
  3274. */
  3275. static inline void
  3276. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3277. uint8_t desc_pool_id)
  3278. {
  3279. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3280. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3281. tx_desc->vdev = NULL;
  3282. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3283. }
  3284. /**
  3285. * dp_tx_desc_flush() - release resources associated
  3286. * to TX Desc
  3287. *
  3288. * @dp_pdev: Handle to DP pdev structure
  3289. * @vdev: virtual device instance
  3290. * NULL: no specific Vdev is required and check all allcated TX desc
  3291. * on this pdev.
  3292. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3293. *
  3294. * @force_free:
  3295. * true: flush the TX desc.
  3296. * false: only reset the Vdev in each allocated TX desc
  3297. * that associated to current Vdev.
  3298. *
  3299. * This function will go through the TX desc pool to flush
  3300. * the outstanding TX data or reset Vdev to NULL in associated TX
  3301. * Desc.
  3302. */
  3303. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3304. struct dp_vdev *vdev,
  3305. bool force_free)
  3306. {
  3307. uint8_t i;
  3308. uint32_t j;
  3309. uint32_t num_desc, page_id, offset;
  3310. uint16_t num_desc_per_page;
  3311. struct dp_soc *soc = pdev->soc;
  3312. struct dp_tx_desc_s *tx_desc = NULL;
  3313. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3314. if (!vdev && !force_free) {
  3315. dp_err("Reset TX desc vdev, Vdev param is required!");
  3316. return;
  3317. }
  3318. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3319. tx_desc_pool = &soc->tx_desc[i];
  3320. if (!(tx_desc_pool->pool_size) ||
  3321. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3322. !(tx_desc_pool->desc_pages.cacheable_pages))
  3323. continue;
  3324. num_desc = tx_desc_pool->pool_size;
  3325. num_desc_per_page =
  3326. tx_desc_pool->desc_pages.num_element_per_page;
  3327. for (j = 0; j < num_desc; j++) {
  3328. page_id = j / num_desc_per_page;
  3329. offset = j % num_desc_per_page;
  3330. if (qdf_unlikely(!(tx_desc_pool->
  3331. desc_pages.cacheable_pages)))
  3332. break;
  3333. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3334. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3335. /*
  3336. * Free TX desc if force free is
  3337. * required, otherwise only reset vdev
  3338. * in this TX desc.
  3339. */
  3340. if (force_free) {
  3341. dp_tx_comp_free_buf(soc, tx_desc);
  3342. dp_tx_desc_release(tx_desc, i);
  3343. } else {
  3344. dp_tx_desc_reset_vdev(soc, tx_desc,
  3345. i);
  3346. }
  3347. }
  3348. }
  3349. }
  3350. }
  3351. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3352. static inline void
  3353. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3354. uint8_t desc_pool_id)
  3355. {
  3356. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3357. tx_desc->vdev = NULL;
  3358. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3359. }
  3360. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3361. struct dp_vdev *vdev,
  3362. bool force_free)
  3363. {
  3364. uint8_t i, num_pool;
  3365. uint32_t j;
  3366. uint32_t num_desc, page_id, offset;
  3367. uint16_t num_desc_per_page;
  3368. struct dp_soc *soc = pdev->soc;
  3369. struct dp_tx_desc_s *tx_desc = NULL;
  3370. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3371. if (!vdev && !force_free) {
  3372. dp_err("Reset TX desc vdev, Vdev param is required!");
  3373. return;
  3374. }
  3375. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3376. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3377. for (i = 0; i < num_pool; i++) {
  3378. tx_desc_pool = &soc->tx_desc[i];
  3379. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3380. continue;
  3381. num_desc_per_page =
  3382. tx_desc_pool->desc_pages.num_element_per_page;
  3383. for (j = 0; j < num_desc; j++) {
  3384. page_id = j / num_desc_per_page;
  3385. offset = j % num_desc_per_page;
  3386. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3387. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3388. if (force_free) {
  3389. dp_tx_comp_free_buf(soc, tx_desc);
  3390. dp_tx_desc_release(tx_desc, i);
  3391. } else {
  3392. dp_tx_desc_reset_vdev(soc, tx_desc,
  3393. i);
  3394. }
  3395. }
  3396. }
  3397. }
  3398. }
  3399. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3400. /**
  3401. * dp_tx_vdev_detach() - detach vdev from dp tx
  3402. * @vdev: virtual device instance
  3403. *
  3404. * Return: QDF_STATUS_SUCCESS: success
  3405. * QDF_STATUS_E_RESOURCES: Error return
  3406. */
  3407. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3408. {
  3409. struct dp_pdev *pdev = vdev->pdev;
  3410. /* Reset TX desc associated to this Vdev as NULL */
  3411. dp_tx_desc_flush(pdev, vdev, false);
  3412. dp_tx_vdev_multipass_deinit(vdev);
  3413. return QDF_STATUS_SUCCESS;
  3414. }
  3415. /**
  3416. * dp_tx_pdev_attach() - attach pdev to dp tx
  3417. * @pdev: physical device instance
  3418. *
  3419. * Return: QDF_STATUS_SUCCESS: success
  3420. * QDF_STATUS_E_RESOURCES: Error return
  3421. */
  3422. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3423. {
  3424. struct dp_soc *soc = pdev->soc;
  3425. /* Initialize Flow control counters */
  3426. qdf_atomic_init(&pdev->num_tx_exception);
  3427. qdf_atomic_init(&pdev->num_tx_outstanding);
  3428. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3429. /* Initialize descriptors in TCL Ring */
  3430. hal_tx_init_data_ring(soc->hal_soc,
  3431. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3432. }
  3433. return QDF_STATUS_SUCCESS;
  3434. }
  3435. /**
  3436. * dp_tx_pdev_detach() - detach pdev from dp tx
  3437. * @pdev: physical device instance
  3438. *
  3439. * Return: QDF_STATUS_SUCCESS: success
  3440. * QDF_STATUS_E_RESOURCES: Error return
  3441. */
  3442. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3443. {
  3444. /* flush TX outstanding data per pdev */
  3445. dp_tx_desc_flush(pdev, NULL, true);
  3446. dp_tx_me_exit(pdev);
  3447. return QDF_STATUS_SUCCESS;
  3448. }
  3449. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3450. /* Pools will be allocated dynamically */
  3451. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3452. int num_desc)
  3453. {
  3454. uint8_t i;
  3455. for (i = 0; i < num_pool; i++) {
  3456. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3457. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3458. }
  3459. return 0;
  3460. }
  3461. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3462. {
  3463. uint8_t i;
  3464. for (i = 0; i < num_pool; i++)
  3465. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3466. }
  3467. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3468. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3469. int num_desc)
  3470. {
  3471. uint8_t i;
  3472. /* Allocate software Tx descriptor pools */
  3473. for (i = 0; i < num_pool; i++) {
  3474. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3475. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3476. "%s Tx Desc Pool alloc %d failed %pK",
  3477. __func__, i, soc);
  3478. return ENOMEM;
  3479. }
  3480. }
  3481. return 0;
  3482. }
  3483. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3484. {
  3485. uint8_t i;
  3486. for (i = 0; i < num_pool; i++) {
  3487. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3488. if (dp_tx_desc_pool_free(soc, i)) {
  3489. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3490. "%s Tx Desc Pool Free failed", __func__);
  3491. }
  3492. }
  3493. }
  3494. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3495. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3496. /**
  3497. * dp_tso_attach_wifi3() - TSO attach handler
  3498. * @txrx_soc: Opaque Dp handle
  3499. *
  3500. * Reserve TSO descriptor buffers
  3501. *
  3502. * Return: QDF_STATUS_E_FAILURE on failure or
  3503. * QDF_STATUS_SUCCESS on success
  3504. */
  3505. static
  3506. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3507. {
  3508. return dp_tso_soc_attach(txrx_soc);
  3509. }
  3510. /**
  3511. * dp_tso_detach_wifi3() - TSO Detach handler
  3512. * @txrx_soc: Opaque Dp handle
  3513. *
  3514. * Deallocate TSO descriptor buffers
  3515. *
  3516. * Return: QDF_STATUS_E_FAILURE on failure or
  3517. * QDF_STATUS_SUCCESS on success
  3518. */
  3519. static
  3520. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3521. {
  3522. return dp_tso_soc_detach(txrx_soc);
  3523. }
  3524. #else
  3525. static
  3526. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3527. {
  3528. return QDF_STATUS_SUCCESS;
  3529. }
  3530. static
  3531. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3532. {
  3533. return QDF_STATUS_SUCCESS;
  3534. }
  3535. #endif
  3536. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3537. {
  3538. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3539. uint8_t i;
  3540. uint8_t num_pool;
  3541. uint32_t num_desc;
  3542. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3543. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3544. for (i = 0; i < num_pool; i++)
  3545. dp_tx_tso_desc_pool_free(soc, i);
  3546. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3547. __func__, num_pool, num_desc);
  3548. for (i = 0; i < num_pool; i++)
  3549. dp_tx_tso_num_seg_pool_free(soc, i);
  3550. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3551. __func__, num_pool, num_desc);
  3552. return QDF_STATUS_SUCCESS;
  3553. }
  3554. /**
  3555. * dp_tso_attach() - TSO attach handler
  3556. * @txrx_soc: Opaque Dp handle
  3557. *
  3558. * Reserve TSO descriptor buffers
  3559. *
  3560. * Return: QDF_STATUS_E_FAILURE on failure or
  3561. * QDF_STATUS_SUCCESS on success
  3562. */
  3563. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3564. {
  3565. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3566. uint8_t i;
  3567. uint8_t num_pool;
  3568. uint32_t num_desc;
  3569. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3570. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3571. for (i = 0; i < num_pool; i++) {
  3572. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3573. dp_err("TSO Desc Pool alloc %d failed %pK",
  3574. i, soc);
  3575. return QDF_STATUS_E_FAILURE;
  3576. }
  3577. }
  3578. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3579. __func__, num_pool, num_desc);
  3580. for (i = 0; i < num_pool; i++) {
  3581. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3582. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3583. i, soc);
  3584. return QDF_STATUS_E_FAILURE;
  3585. }
  3586. }
  3587. return QDF_STATUS_SUCCESS;
  3588. }
  3589. /**
  3590. * dp_tx_soc_detach() - detach soc from dp tx
  3591. * @soc: core txrx main context
  3592. *
  3593. * This function will detach dp tx into main device context
  3594. * will free dp tx resource and initialize resources
  3595. *
  3596. * Return: QDF_STATUS_SUCCESS: success
  3597. * QDF_STATUS_E_RESOURCES: Error return
  3598. */
  3599. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3600. {
  3601. uint8_t num_pool;
  3602. uint16_t num_desc;
  3603. uint16_t num_ext_desc;
  3604. uint8_t i;
  3605. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3606. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3607. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3608. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3609. dp_tx_flow_control_deinit(soc);
  3610. dp_tx_delete_static_pools(soc, num_pool);
  3611. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3612. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3613. __func__, num_pool, num_desc);
  3614. for (i = 0; i < num_pool; i++) {
  3615. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3616. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3617. "%s Tx Ext Desc Pool Free failed",
  3618. __func__);
  3619. return QDF_STATUS_E_RESOURCES;
  3620. }
  3621. }
  3622. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3623. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3624. __func__, num_pool, num_ext_desc);
  3625. status = dp_tso_detach_wifi3(soc);
  3626. if (status != QDF_STATUS_SUCCESS)
  3627. return status;
  3628. return QDF_STATUS_SUCCESS;
  3629. }
  3630. /**
  3631. * dp_tx_soc_attach() - attach soc to dp tx
  3632. * @soc: core txrx main context
  3633. *
  3634. * This function will attach dp tx into main device context
  3635. * will allocate dp tx resource and initialize resources
  3636. *
  3637. * Return: QDF_STATUS_SUCCESS: success
  3638. * QDF_STATUS_E_RESOURCES: Error return
  3639. */
  3640. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3641. {
  3642. uint8_t i;
  3643. uint8_t num_pool;
  3644. uint32_t num_desc;
  3645. uint32_t num_ext_desc;
  3646. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3647. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3648. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3649. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3650. if (num_pool > MAX_TXDESC_POOLS)
  3651. goto fail;
  3652. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3653. goto fail;
  3654. dp_tx_flow_control_init(soc);
  3655. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3656. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3657. __func__, num_pool, num_desc);
  3658. /* Allocate extension tx descriptor pools */
  3659. for (i = 0; i < num_pool; i++) {
  3660. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3661. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3662. "MSDU Ext Desc Pool alloc %d failed %pK",
  3663. i, soc);
  3664. goto fail;
  3665. }
  3666. }
  3667. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3668. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3669. __func__, num_pool, num_ext_desc);
  3670. status = dp_tso_attach_wifi3((void *)soc);
  3671. if (status != QDF_STATUS_SUCCESS)
  3672. goto fail;
  3673. /* Initialize descriptors in TCL Rings */
  3674. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3675. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3676. hal_tx_init_data_ring(soc->hal_soc,
  3677. soc->tcl_data_ring[i].hal_srng);
  3678. }
  3679. }
  3680. /*
  3681. * todo - Add a runtime config option to enable this.
  3682. */
  3683. /*
  3684. * Due to multiple issues on NPR EMU, enable it selectively
  3685. * only for NPR EMU, should be removed, once NPR platforms
  3686. * are stable.
  3687. */
  3688. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3689. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3690. "%s HAL Tx init Success", __func__);
  3691. return QDF_STATUS_SUCCESS;
  3692. fail:
  3693. /* Detach will take care of freeing only allocated resources */
  3694. dp_tx_soc_detach(soc);
  3695. return QDF_STATUS_E_RESOURCES;
  3696. }