wcd9378.c 129 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/msm-cdc-pinctrl.h>
  19. #include <asoc/msm-cdc-supply.h>
  20. #include <bindings/audio-codec-port-types.h>
  21. #include <linux/qti-regmap-debugfs.h>
  22. #include "wcd9378-reg-masks.h"
  23. #include "wcd9378.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD9378_MOBILE_MODE 0x01
  28. #define WCD9378_VERSION_1_0 1
  29. #define WCD9378_VERSION_ENTRY_SIZE 32
  30. #define SWR_BASECLK_19P2MHZ (0x01)
  31. #define SWR_BASECLK_24P576MHZ (0x03)
  32. #define SWR_BASECLK_22P5792MHZ (0x04)
  33. #define SWR_CLKSCALE_DIV2 (0x02)
  34. #define ADC_MODE_VAL_HIFI 0x01
  35. #define ADC_MODE_VAL_NORMAL 0x03
  36. #define ADC_MODE_VAL_LP 0x05
  37. #define PWR_LEVEL_LOHIFI_VAL 0x00
  38. #define PWR_LEVEL_LP_VAL 0x01
  39. #define PWR_LEVEL_HIFI_VAL 0x02
  40. #define PWR_LEVEL_ULP_VAL 0x03
  41. #define WCD9378_MBQ_ENABLE_MASK 0x2000
  42. #define MICB_USAGE_VAL_DISABLE 0x00
  43. #define MICB_USAGE_VAL_PULL_DOWN 0x01
  44. #define MICB_USAGE_VAL_1P2V 0x02
  45. #define MICB_USAGE_VAL_1P8VORPULLUP 0x03
  46. #define MICB_USAGE_VAL_2P5V 0x04
  47. #define MICB_USAGE_VAL_2P75V 0x05
  48. #define MICB_USAGE_VAL_2P2V 0xF0
  49. #define MICB_USAGE_VAL_2P7V 0xF1
  50. #define MICB_USAGE_VAL_2P8V 0xF2
  51. #define MICB_USAGE_VAL_MICB1_TABLE_VAL 0xF3
  52. #define MICB_USAGE_VAL_MICB2_TABLE_VAL 0xF4
  53. #define MICB_USAGE_VAL_MICB3_TABLE_VAL 0xF5
  54. #define MICB_NUM_MAX 3
  55. #define NUM_ATTEMPTS 20
  56. #define WCD9378_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  57. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  58. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  59. SNDRV_PCM_RATE_384000)
  60. /* Fractional Rates */
  61. #define WCD9378_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  62. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  63. #define WCD9378_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  64. SNDRV_PCM_FMTBIT_S24_LE |\
  65. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  66. #define WCD9378_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  67. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  68. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  69. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  70. .tlv.p = (tlv_array), \
  71. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  72. .put = wcd9378_ear_pa_put_gain, \
  73. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  74. #define WCD9378_AUX_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  75. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  76. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  77. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  78. .tlv.p = (tlv_array), \
  79. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  80. .put = wcd9378_aux_pa_put_gain, \
  81. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  82. enum {
  83. CODEC_TX = 0,
  84. CODEC_RX,
  85. };
  86. enum {
  87. RX2_HP_MODE,
  88. RX2_NORMAL_MODE,
  89. };
  90. enum {
  91. CLASS_AB_EN = 0,
  92. TX1_FOR_JACK,
  93. TX2_AMIC4_EN,
  94. TX2_AMIC1_EN,
  95. TX1_AMIC3_EN,
  96. TX1_AMIC2_EN,
  97. TX0_AMIC2_EN,
  98. TX0_AMIC1_EN,
  99. RX2_EAR_EN,
  100. RX2_AUX_EN,
  101. RX1_AUX_EN,
  102. RX0_EAR_EN,
  103. RX0_RX1_HPH_EN,
  104. };
  105. enum {
  106. WCD_ADC1 = 0,
  107. WCD_ADC2,
  108. WCD_ADC3,
  109. WCD_ADC4,
  110. ALLOW_BUCK_DISABLE,
  111. HPH_COMP_DELAY,
  112. HPH_PA_DELAY,
  113. AMIC2_BCS_ENABLE,
  114. WCD_SUPPLIES_LPM_MODE,
  115. WCD_ADC1_MODE,
  116. WCD_ADC2_MODE,
  117. WCD_ADC3_MODE,
  118. WCD_ADC4_MODE,
  119. WCD_AUX_EN,
  120. WCD_EAR_EN,
  121. };
  122. enum {
  123. SYS_USAGE_0,
  124. SYS_USAGE_1,
  125. SYS_USAGE_2,
  126. SYS_USAGE_3,
  127. SYS_USAGE_4,
  128. SYS_USAGE_5,
  129. SYS_USAGE_6,
  130. SYS_USAGE_7,
  131. SYS_USAGE_8,
  132. SYS_USAGE_9,
  133. SYS_USAGE_10,
  134. SYS_USAGE_11,
  135. SYS_USAGE_12,
  136. SYS_USAGE_NUM,
  137. };
  138. enum {
  139. NO_MICB_USED,
  140. MICB1,
  141. MICB2,
  142. MICB3,
  143. MICB_NUM,
  144. };
  145. enum {
  146. ADC_MODE_INVALID = 0,
  147. ADC_MODE_HIFI,
  148. ADC_MODE_NORMAL,
  149. ADC_MODE_LP,
  150. };
  151. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
  152. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(aux_pa_gain, 600, -600);
  153. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
  154. static int wcd9378_reset(struct device *dev);
  155. static int wcd9378_reset_low(struct device *dev);
  156. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable);
  157. static void wcd9378_class_load(struct snd_soc_component *component);
  158. /* sys_usage:
  159. * rx0_rx1_hph_en,
  160. * rx0_ear_en, rx1_aux_en, rx2_aux_en, rx2_ear_en,
  161. * tx0_amic1_en, tx0_amic2_en, tx1_amic2_en, tx1_amic3_en,
  162. * tx2_amic1_en, tx2_amic4_en, tx1_for_jack, class_ab_en;
  163. */
  164. static const int sys_usage[SYS_USAGE_NUM] = {
  165. [SYS_USAGE_0] = 0x0c95, /*0b0 1100 1001 0101*/
  166. [SYS_USAGE_1] = 0x12a7, /*0b1 0010 1010 0111*/
  167. [SYS_USAGE_2] = 0x0c99, /*0b0 1100 1001 1001*/
  168. [SYS_USAGE_3] = 0x1aab, /*0b1 1010 1010 1011*/
  169. [SYS_USAGE_4] = 0x0894, /*0b0 1000 1001 0100*/
  170. [SYS_USAGE_5] = 0x11a6, /*0b1 0001 1010 0110*/
  171. [SYS_USAGE_6] = 0x0898, /*0b0 1000 1001 1000*/
  172. [SYS_USAGE_7] = 0x11ab, /*0b1 0001 1010 1011*/
  173. [SYS_USAGE_8] = 0x126a, /*0b1 0010 0110 1010*/
  174. [SYS_USAGE_9] = 0x116b, /*0b1 0001 0110 1011*/
  175. [SYS_USAGE_10] = 0x1ca7, /*0b1 1100 1010 0111*/
  176. [SYS_USAGE_11] = 0x1195, /*0b1 0001 1001 0101*/
  177. [SYS_USAGE_12] = 0x1296, /*0b1 0010 1001 0101*/
  178. };
  179. static const struct regmap_irq wcd9378_regmap_irqs[WCD9378_NUM_IRQS] = {
  180. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  181. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  182. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  183. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  184. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_SW_DET, 0, 0x10),
  185. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_OCP_INT, 0, 0x20),
  186. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_CNP_INT, 0, 0x40),
  187. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_OCP_INT, 0, 0x80),
  188. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_CNP_INT, 1, 0x01),
  189. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_CNP_INT, 1, 0x02),
  190. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_SCD_INT, 1, 0x04),
  191. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_CNP_INT, 1, 0x08),
  192. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_SCD_INT, 1, 0x10),
  193. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  194. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  195. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  196. REGMAP_IRQ_REG(WCD9378_IRQ_LDORT_SCD_INT, 2, 0x01),
  197. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  198. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  199. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  200. REGMAP_IRQ_REG(WCD9378_IRQ_SAPU_PROT_MODE_CHG, 2, 0x40),
  201. };
  202. static int wcd9378_handle_post_irq(void *data)
  203. {
  204. struct wcd9378_priv *wcd9378 = data;
  205. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  206. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, &sts1);
  207. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, &sts2);
  208. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, &sts3);
  209. wcd9378->tx_swr_dev->slave_irq_pending =
  210. ((sts1 || sts2 || !sts3) ? true : false);
  211. return IRQ_HANDLED;
  212. }
  213. static struct regmap_irq_chip wcd9378_regmap_irq_chip = {
  214. .name = "wcd9378",
  215. .irqs = wcd9378_regmap_irqs,
  216. .num_irqs = ARRAY_SIZE(wcd9378_regmap_irqs),
  217. .num_regs = 3,
  218. .status_base = SWRS_SCP_SDCA_INTSTAT_1,
  219. .unmask_base = SWRS_SCP_SDCA_INTMASK_1,
  220. .type_base = SWRS_SCP_SDCA_INTRTYPE_1,
  221. .ack_base = SWRS_SCP_SDCA_INTSTAT_1,
  222. .use_ack = 1,
  223. .runtime_pm = false,
  224. .handle_post_irq = wcd9378_handle_post_irq,
  225. .irq_drv_data = NULL,
  226. };
  227. static int wcd9378_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  228. {
  229. int ret = 0;
  230. int bank = 0;
  231. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  232. if (ret)
  233. return -EINVAL;
  234. return ((bank & 0x40) ? 1 : 0);
  235. }
  236. static int wcd9378_init_reg(struct snd_soc_component *component)
  237. {
  238. struct wcd9378_priv *wcd9378 =
  239. snd_soc_component_get_drvdata(component);
  240. u32 val = 0;
  241. val = snd_soc_component_read(component, WCD9378_EFUSE_REG_16);
  242. if (!val)
  243. snd_soc_component_update_bits(component, WCD9378_MBHC_CTL_SPARE_1,
  244. WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK,
  245. 0x03);
  246. else
  247. snd_soc_component_update_bits(component, WCD9378_MBHC_CTL_SPARE_1,
  248. WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK,
  249. 0x01);
  250. /*0.9 Volts*/
  251. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  252. WCD9378_SLEEP_CTL_BG_CTL_MASK, 0x0E);
  253. /*BG_EN ENABLE*/
  254. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  255. WCD9378_SLEEP_CTL_BG_EN_MASK, 0x80);
  256. usleep_range(1000, 1010);
  257. /*LDOL_BG_SEL SLEEP_BG*/
  258. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  259. WCD9378_SLEEP_CTL_LDOL_BG_SEL_MASK, 0x40);
  260. usleep_range(1000, 1010);
  261. /*Start up analog master bias. Sequence cannot change*/
  262. /*VBG_FINE_ADJ 0.005 Volts*/
  263. snd_soc_component_update_bits(component, WCD9378_BIAS_VBG_FINE_ADJ,
  264. WCD9378_BIAS_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK, 0xB0);
  265. /*ANALOG_BIAS_EN ENABLE*/
  266. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  267. WCD9378_ANA_BIAS_ANALOG_BIAS_EN_MASK, 0x80);
  268. /*PRECHRG_EN ENABLE*/
  269. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  270. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x40);
  271. usleep_range(10000, 10010);
  272. /*PRECHRG_EN DISABLE*/
  273. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  274. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x00);
  275. /*End Analog Master Bias enable*/
  276. /*ANA_TXSCBIAS_CLK_EN ENABLE*/
  277. snd_soc_component_update_bits(component, WCD9378_CDC_ANA_TX_CLK_CTL,
  278. WCD9378_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN_MASK, 0x01);
  279. /*SEQ_BYPASS ENABLE*/
  280. snd_soc_component_update_bits(component, WCD9378_TX_COM_TXFE_DIV_CTL,
  281. WCD9378_TX_COM_TXFE_DIV_CTL_SEQ_BYPASS_MASK, 0x80);
  282. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  283. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL0,
  284. WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_PCM_MASK, 0x10);
  285. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  286. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL1,
  287. WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_PCM_MASK, 0x10);
  288. /*IBIAS_LDO_DRIVER 5e-06*/
  289. snd_soc_component_update_bits(component, WCD9378_MICB1_TEST_CTL_2,
  290. WCD9378_MICB1_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  291. /*IBIAS_LDO_DRIVER 5e-06*/
  292. snd_soc_component_update_bits(component, WCD9378_MICB2_TEST_CTL_2,
  293. WCD9378_MICB2_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  294. /*IBIAS_LDO_DRIVER 5e-06*/
  295. snd_soc_component_update_bits(component, WCD9378_MICB3_TEST_CTL_2,
  296. WCD9378_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  297. /*SHORT_PROT_EN ENABLE*/
  298. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  299. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x40);
  300. /*OCP FSM EN*/
  301. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  302. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  303. /*SCD OP EN*/
  304. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  305. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  306. /*HD2_RES_DIV_CTL_L 82.77*/
  307. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L,
  308. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK, 0x04);
  309. /*HD2_RES_DIV_CTL_R 82.77*/
  310. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R,
  311. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK, 0x04);
  312. /*OPAMP_CHOP_CLK_EN DISABLE*/
  313. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  314. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  315. /*RDAC_GAINCTL 0.55*/
  316. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL,
  317. WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_RDAC_GAINCTL_MASK, 0x50);
  318. /*HPH_UP_T0: 0.002*/
  319. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T0,
  320. WCD9378_HPH_UP_T0_HPH_UP_T0_MASK, 0x05);
  321. /*HPH_UP_T9: 0.002*/
  322. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T9,
  323. WCD9378_HPH_UP_T9_HPH_UP_T9_MASK, 0x05);
  324. /*HPH_DN_T0: 0.007*/
  325. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T0,
  326. WCD9378_HPH_DN_T0_HPH_DN_T0_MASK, 0x06);
  327. /*SM0 MB SEL:MB1*/
  328. snd_soc_component_update_bits(component, WCD9378_SM0_MB_SEL,
  329. WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK, 0x01);
  330. /*SM1 MB SEL:MB2*/
  331. snd_soc_component_update_bits(component, WCD9378_SM1_MB_SEL,
  332. WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK, 0x02);
  333. /*SM2 MB SEL:MB3*/
  334. snd_soc_component_update_bits(component, WCD9378_SM2_MB_SEL,
  335. WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK, 0x03);
  336. /*INIT SYS_USAGE*/
  337. snd_soc_component_update_bits(component,
  338. WCD9378_SYS_USAGE_CTRL,
  339. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  340. 0);
  341. wcd9378->sys_usage = 0;
  342. wcd9378_class_load(component);
  343. return 0;
  344. }
  345. static int wcd9378_set_port_params(struct snd_soc_component *component,
  346. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  347. u8 *ch_mask, u32 *ch_rate,
  348. u8 *port_type, u8 path)
  349. {
  350. int i, j;
  351. u8 num_ports = 0;
  352. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  353. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  354. switch (path) {
  355. case CODEC_RX:
  356. map = &wcd9378->rx_port_mapping;
  357. num_ports = wcd9378->num_rx_ports;
  358. break;
  359. case CODEC_TX:
  360. map = &wcd9378->tx_port_mapping;
  361. num_ports = wcd9378->num_tx_ports;
  362. break;
  363. default:
  364. dev_err(component->dev, "%s Invalid path selected %u\n",
  365. __func__, path);
  366. return -EINVAL;
  367. }
  368. for (i = 0; i <= num_ports; i++) {
  369. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  370. if ((*map)[i][j].slave_port_type == slv_prt_type)
  371. goto found;
  372. }
  373. }
  374. found:
  375. if (i > num_ports || j == MAX_CH_PER_PORT) {
  376. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  377. __func__, slv_prt_type);
  378. return -EINVAL;
  379. }
  380. *port_id = i;
  381. *num_ch = (*map)[i][j].num_ch;
  382. *ch_mask = (*map)[i][j].ch_mask;
  383. *ch_rate = (*map)[i][j].ch_rate;
  384. *port_type = (*map)[i][j].master_port_type;
  385. return 0;
  386. }
  387. static int wcd9378_parse_port_params(struct device *dev,
  388. char *prop, u8 path)
  389. {
  390. u32 *dt_array, map_size, max_uc;
  391. int ret = 0;
  392. u32 cnt = 0;
  393. u32 i, j;
  394. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  395. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  396. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  397. switch (path) {
  398. case CODEC_TX:
  399. map = &wcd9378->tx_port_params;
  400. map_uc = &wcd9378->swr_tx_port_params;
  401. break;
  402. default:
  403. ret = -EINVAL;
  404. goto err_port_map;
  405. }
  406. if (!of_find_property(dev->of_node, prop,
  407. &map_size)) {
  408. dev_err(dev, "missing port mapping prop %s\n", prop);
  409. ret = -EINVAL;
  410. goto err_port_map;
  411. }
  412. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  413. if (max_uc != SWR_UC_MAX) {
  414. dev_err(dev, "%s: port params not provided for all usecases\n",
  415. __func__);
  416. ret = -EINVAL;
  417. goto err_port_map;
  418. }
  419. dt_array = kzalloc(map_size, GFP_KERNEL);
  420. if (!dt_array) {
  421. ret = -ENOMEM;
  422. goto err_alloc;
  423. }
  424. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  425. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  426. if (ret) {
  427. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  428. __func__, prop);
  429. goto err_pdata_fail;
  430. }
  431. for (i = 0; i < max_uc; i++) {
  432. for (j = 0; j < SWR_NUM_PORTS; j++) {
  433. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  434. (*map)[i][j].offset1 = dt_array[cnt];
  435. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  436. }
  437. (*map_uc)[i].pp = &(*map)[i][0];
  438. }
  439. kfree(dt_array);
  440. return 0;
  441. err_pdata_fail:
  442. kfree(dt_array);
  443. err_alloc:
  444. err_port_map:
  445. return ret;
  446. }
  447. static int wcd9378_parse_port_mapping(struct device *dev,
  448. char *prop, u8 path)
  449. {
  450. u32 *dt_array, map_size, map_length;
  451. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  452. u32 slave_port_type, master_port_type;
  453. u32 i, ch_iter = 0;
  454. int ret = 0;
  455. u8 *num_ports = NULL;
  456. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  457. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  458. switch (path) {
  459. case CODEC_RX:
  460. map = &wcd9378->rx_port_mapping;
  461. num_ports = &wcd9378->num_rx_ports;
  462. break;
  463. case CODEC_TX:
  464. map = &wcd9378->tx_port_mapping;
  465. num_ports = &wcd9378->num_tx_ports;
  466. break;
  467. default:
  468. dev_err(dev, "%s Invalid path selected %u\n",
  469. __func__, path);
  470. return -EINVAL;
  471. }
  472. if (!of_find_property(dev->of_node, prop,
  473. &map_size)) {
  474. dev_err(dev, "missing port mapping prop %s\n", prop);
  475. ret = -EINVAL;
  476. goto err_port_map;
  477. }
  478. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  479. dt_array = kzalloc(map_size, GFP_KERNEL);
  480. if (!dt_array) {
  481. ret = -ENOMEM;
  482. goto err_alloc;
  483. }
  484. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  485. NUM_SWRS_DT_PARAMS * map_length);
  486. if (ret) {
  487. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  488. __func__, prop);
  489. goto err_pdata_fail;
  490. }
  491. for (i = 0; i < map_length; i++) {
  492. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  493. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  494. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  495. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  496. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  497. if (port_num != old_port_num)
  498. ch_iter = 0;
  499. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  500. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  501. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  502. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  503. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  504. old_port_num = port_num;
  505. }
  506. *num_ports = port_num;
  507. kfree(dt_array);
  508. return 0;
  509. err_pdata_fail:
  510. kfree(dt_array);
  511. err_alloc:
  512. err_port_map:
  513. return ret;
  514. }
  515. static int wcd9378_tx_connect_port(struct snd_soc_component *component,
  516. u8 slv_port_type, int clk_rate,
  517. u8 enable)
  518. {
  519. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  520. u8 port_id, num_ch, ch_mask;
  521. u8 ch_type = 0;
  522. u32 ch_rate;
  523. int slave_ch_idx;
  524. u8 num_port = 1;
  525. int ret = 0;
  526. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  527. &num_ch, &ch_mask, &ch_rate,
  528. &ch_type, CODEC_TX);
  529. if (ret)
  530. return ret;
  531. if (clk_rate)
  532. ch_rate = clk_rate;
  533. slave_ch_idx = wcd9378_slave_get_slave_ch_val(slv_port_type);
  534. if (slave_ch_idx != -EINVAL)
  535. ch_type = wcd9378->tx_master_ch_map[slave_ch_idx];
  536. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  537. __func__, slave_ch_idx, ch_type);
  538. if (enable)
  539. ret = swr_connect_port(wcd9378->tx_swr_dev, &port_id,
  540. num_port, &ch_mask, &ch_rate,
  541. &num_ch, &ch_type);
  542. else
  543. ret = swr_disconnect_port(wcd9378->tx_swr_dev, &port_id,
  544. num_port, &ch_mask, &ch_type);
  545. return ret;
  546. }
  547. static int wcd9378_rx_connect_port(struct snd_soc_component *component,
  548. u8 slv_port_type, u8 enable)
  549. {
  550. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  551. u8 port_id, num_ch, ch_mask, port_type;
  552. u32 ch_rate;
  553. u8 num_port = 1;
  554. int ret = 0;
  555. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  556. &num_ch, &ch_mask, &ch_rate,
  557. &port_type, CODEC_RX);
  558. if (ret)
  559. return ret;
  560. if (enable)
  561. ret = swr_connect_port(wcd9378->rx_swr_dev, &port_id,
  562. num_port, &ch_mask, &ch_rate,
  563. &num_ch, &port_type);
  564. else
  565. ret = swr_disconnect_port(wcd9378->rx_swr_dev, &port_id,
  566. num_port, &ch_mask, &port_type);
  567. return ret;
  568. }
  569. static int wcd9378_enable_clsh(struct snd_soc_dapm_widget *w,
  570. struct snd_kcontrol *kcontrol,
  571. int event)
  572. {
  573. struct snd_soc_component *component =
  574. snd_soc_dapm_to_component(w->dapm);
  575. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  576. int mode = wcd9378->hph_mode;
  577. int ret = 0;
  578. int bank = 0;
  579. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  580. w->name, event);
  581. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  582. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  583. wcd9378_rx_connect_port(component, CLSH,
  584. SND_SOC_DAPM_EVENT_ON(event));
  585. }
  586. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  587. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  588. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  589. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, false);
  590. ret = swr_slvdev_datapath_control(
  591. wcd9378->rx_swr_dev,
  592. wcd9378->rx_swr_dev->dev_num,
  593. false);
  594. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, false);
  595. }
  596. return ret;
  597. }
  598. static int wcd9378_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  599. struct snd_kcontrol *kcontrol,
  600. int event)
  601. {
  602. struct snd_soc_component *component =
  603. snd_soc_dapm_to_component(w->dapm);
  604. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  605. u32 dmic_clk_reg, dmic_clk_en_reg;
  606. s32 *dmic_clk_cnt;
  607. u8 dmic_ctl_shift = 0;
  608. u8 dmic_clk_shift = 0;
  609. u8 dmic_clk_mask = 0;
  610. u32 dmic2_left_en = 0;
  611. int ret = 0;
  612. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  613. w->name, event);
  614. switch (w->shift) {
  615. case 0:
  616. case 1:
  617. dmic_clk_cnt = &(wcd9378->dmic_0_1_clk_cnt);
  618. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  619. dmic_clk_en_reg = WCD9378_CDC_DMIC1_CTL;
  620. dmic_clk_mask = 0x0F;
  621. dmic_clk_shift = 0x00;
  622. dmic_ctl_shift = 0x00;
  623. break;
  624. case 2:
  625. dmic2_left_en = WCD9378_CDC_DMIC2_CTL;
  626. fallthrough;
  627. case 3:
  628. dmic_clk_cnt = &(wcd9378->dmic_2_3_clk_cnt);
  629. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  630. dmic_clk_en_reg = WCD9378_CDC_DMIC2_CTL;
  631. dmic_clk_mask = 0xF0;
  632. dmic_clk_shift = 0x04;
  633. dmic_ctl_shift = 0x01;
  634. break;
  635. case 4:
  636. case 5:
  637. dmic_clk_cnt = &(wcd9378->dmic_4_5_clk_cnt);
  638. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_3_4;
  639. dmic_clk_en_reg = WCD9378_CDC_DMIC3_CTL;
  640. dmic_clk_mask = 0x0F;
  641. dmic_clk_shift = 0x00;
  642. dmic_ctl_shift = 0x02;
  643. break;
  644. default:
  645. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  646. __func__);
  647. return -EINVAL;
  648. };
  649. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  650. __func__, event, (w->shift + 1), *dmic_clk_cnt);
  651. switch (event) {
  652. case SND_SOC_DAPM_PRE_PMU:
  653. snd_soc_component_update_bits(component,
  654. WCD9378_CDC_AMIC_CTL,
  655. (0x01 << dmic_ctl_shift), 0x00);
  656. /* 250us sleep as per HW requirement */
  657. usleep_range(250, 260);
  658. if (dmic2_left_en)
  659. snd_soc_component_update_bits(component,
  660. dmic2_left_en, 0x80, 0x80);
  661. /* Setting DMIC clock rate to 2.4MHz */
  662. snd_soc_component_update_bits(component,
  663. dmic_clk_reg, dmic_clk_mask,
  664. (0x03 << dmic_clk_shift));
  665. snd_soc_component_update_bits(component,
  666. dmic_clk_en_reg, 0x08, 0x08);
  667. /* enable clock scaling */
  668. snd_soc_component_update_bits(component,
  669. WCD9378_CDC_DMIC_CTL, 0x06, 0x06);
  670. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  671. wcd9378->tx_swr_dev->dev_num,
  672. true);
  673. break;
  674. case SND_SOC_DAPM_POST_PMD:
  675. wcd9378_tx_connect_port(component, DMIC0 + (w->shift), 0,
  676. false);
  677. snd_soc_component_update_bits(component,
  678. WCD9378_CDC_AMIC_CTL,
  679. (0x01 << dmic_ctl_shift),
  680. (0x01 << dmic_ctl_shift));
  681. if (dmic2_left_en)
  682. snd_soc_component_update_bits(component,
  683. dmic2_left_en, 0x80, 0x00);
  684. snd_soc_component_update_bits(component,
  685. dmic_clk_en_reg, 0x08, 0x00);
  686. break;
  687. };
  688. return ret;
  689. }
  690. /*
  691. * wcd9378_get_micb_vout_ctl_val: converts micbias from volts to register value
  692. * @micb_mv: micbias in mv
  693. *
  694. * return register value converted
  695. */
  696. int wcd9378_get_micb_vout_ctl_val(u32 micb_mv)
  697. {
  698. /* min micbias voltage is 1V and maximum is 2.85V */
  699. if (micb_mv < 1000 || micb_mv > 2850) {
  700. pr_err("%s: unsupported micbias voltage\n", __func__);
  701. return -EINVAL;
  702. }
  703. return (micb_mv - 1000) / 50;
  704. }
  705. EXPORT_SYMBOL_GPL(wcd9378_get_micb_vout_ctl_val);
  706. /*
  707. * wcd9378_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  708. * @component: handle to snd_soc_component *
  709. * @req_volt: micbias voltage to be set
  710. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  711. *
  712. * return 0 if adjustment is success or error code in case of failure
  713. */
  714. static int wcd9378_micb_table_value_set(struct snd_soc_component *component,
  715. u32 micb_mv, int micb_num)
  716. {
  717. int vcout_ctl;
  718. switch (micb_mv) {
  719. case 2200:
  720. return MICB_USAGE_VAL_2P2V;
  721. case 2700:
  722. return MICB_USAGE_VAL_2P7V;
  723. case 2800:
  724. return MICB_USAGE_VAL_2P8V;
  725. default:
  726. vcout_ctl = wcd9378_get_micb_vout_ctl_val(micb_mv);
  727. if (micb_num == MIC_BIAS_1) {
  728. snd_soc_component_update_bits(component,
  729. WCD9378_MICB_REMAP_TABLE_VAL_3,
  730. WCD9378_MICB_REMAP_TABLE_VAL_3_MICB_REMAP_TABLE_VAL_3_MASK,
  731. vcout_ctl);
  732. return MICB_USAGE_VAL_MICB1_TABLE_VAL;
  733. } else if (micb_num == MIC_BIAS_2) {
  734. snd_soc_component_update_bits(component,
  735. WCD9378_MICB_REMAP_TABLE_VAL_4,
  736. WCD9378_MICB_REMAP_TABLE_VAL_4_MICB_REMAP_TABLE_VAL_4_MASK,
  737. vcout_ctl);
  738. return MICB_USAGE_VAL_MICB2_TABLE_VAL;
  739. } else if (micb_num == MIC_BIAS_3) {
  740. snd_soc_component_update_bits(component,
  741. WCD9378_MICB_REMAP_TABLE_VAL_5,
  742. WCD9378_MICB_REMAP_TABLE_VAL_5_MICB_REMAP_TABLE_VAL_5_MASK,
  743. vcout_ctl);
  744. return MICB_USAGE_VAL_MICB3_TABLE_VAL;
  745. }
  746. }
  747. return 0;
  748. }
  749. static int wcd9378_micb_usage_value_convert(struct snd_soc_component *component,
  750. u32 micb_mv, int micb_num)
  751. {
  752. switch (micb_mv) {
  753. case 0:
  754. return MICB_USAGE_VAL_PULL_DOWN;
  755. case 1200:
  756. return MICB_USAGE_VAL_1P2V;
  757. case 1800:
  758. return MICB_USAGE_VAL_1P8VORPULLUP;
  759. case 2500:
  760. return MICB_USAGE_VAL_2P5V;
  761. case 2750:
  762. return MICB_USAGE_VAL_2P75V;
  763. default:
  764. return wcd9378_micb_table_value_set(component, micb_mv, micb_num);
  765. }
  766. return MICB_USAGE_VAL_DISABLE;
  767. }
  768. int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  769. int req_volt, int micb_num)
  770. {
  771. struct wcd9378_priv *wcd9378 =
  772. snd_soc_component_get_drvdata(component);
  773. int micb_usage = 0, micb_mask = 0, req_vout_ctl = 0;
  774. if (wcd9378 == NULL) {
  775. dev_err(component->dev,
  776. "%s: wcd9378 private data is NULL\n", __func__);
  777. return -EINVAL;
  778. }
  779. switch (micb_num) {
  780. case MIC_BIAS_1:
  781. micb_usage = WCD9378_IT11_USAGE;
  782. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  783. break;
  784. case MIC_BIAS_2:
  785. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  786. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  787. break;
  788. case MIC_BIAS_3:
  789. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  790. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  791. break;
  792. default:
  793. dev_err(component->dev,
  794. "%s: wcd9378 private data is NULL\n", __func__);
  795. break;
  796. }
  797. mutex_lock(&wcd9378->micb_lock);
  798. req_vout_ctl =
  799. wcd9378_micb_usage_value_convert(component, req_volt, micb_num);
  800. snd_soc_component_update_bits(component,
  801. micb_usage, micb_mask, req_vout_ctl);
  802. if (micb_num == MIC_BIAS_2) {
  803. dev_err(component->dev,
  804. "%s: sj micbias set\n", __func__);
  805. snd_soc_component_update_bits(component,
  806. WCD9378_IT31_MICB,
  807. WCD9378_IT31_MICB_IT31_MICB_MASK,
  808. req_vout_ctl);
  809. wcd9378->curr_micbias2 = req_volt;
  810. }
  811. mutex_unlock(&wcd9378->micb_lock);
  812. return 0;
  813. }
  814. EXPORT_SYMBOL_GPL(wcd9378_mbhc_micb_adjust_voltage);
  815. void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  816. bool bcs_disable)
  817. {
  818. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  819. if (wcd9378->update_wcd_event) {
  820. if (bcs_disable)
  821. wcd9378->update_wcd_event(wcd9378->handle,
  822. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  823. else
  824. wcd9378->update_wcd_event(wcd9378->handle,
  825. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  826. }
  827. }
  828. static int wcd9378_get_clk_rate(int mode)
  829. {
  830. int rate;
  831. switch (mode) {
  832. case ADC_MODE_LP:
  833. rate = SWR_CLK_RATE_4P8MHZ;
  834. break;
  835. case ADC_MODE_INVALID:
  836. case ADC_MODE_NORMAL:
  837. case ADC_MODE_HIFI:
  838. default:
  839. rate = SWR_CLK_RATE_9P6MHZ;
  840. break;
  841. }
  842. pr_debug("%s: mode: %d, rate: %d\n", __func__, mode, rate);
  843. return rate;
  844. }
  845. static int wcd9378_get_adc_mode_val(int mode)
  846. {
  847. int ret = 0;
  848. switch (mode) {
  849. case ADC_MODE_INVALID:
  850. case ADC_MODE_NORMAL:
  851. ret = ADC_MODE_VAL_NORMAL;
  852. break;
  853. case ADC_MODE_HIFI:
  854. ret = ADC_MODE_VAL_HIFI;
  855. break;
  856. case ADC_MODE_LP:
  857. ret = ADC_MODE_VAL_LP;
  858. break;
  859. default:
  860. ret = -EINVAL;
  861. pr_err("%s: invalid ADC mode value %d\n", __func__, mode);
  862. break;
  863. }
  864. return ret;
  865. }
  866. static int wcd9378_sys_usage_auto_udpate(struct snd_soc_component *component,
  867. int sys_usage_bit, bool set_enable)
  868. {
  869. struct wcd9378_priv *wcd9378 =
  870. snd_soc_component_get_drvdata(component);
  871. int i = 0;
  872. dev_dbg(component->dev,
  873. "%s: enter, current sys_usage: %d, sys_usage_status: 0x%x, sys_usage_bit: %d, set_enable: %d\n",
  874. __func__, wcd9378->sys_usage,
  875. wcd9378->sys_usage_status,
  876. sys_usage_bit, set_enable);
  877. mutex_lock(&wcd9378->sys_usage_lock);
  878. if (set_enable) {
  879. set_bit(sys_usage_bit, &wcd9378->sys_usage_status);
  880. if ((sys_usage[wcd9378->sys_usage] &
  881. wcd9378->sys_usage_status) == wcd9378->sys_usage_status)
  882. goto exit;
  883. for (i = 0; i < SYS_USAGE_NUM; i++) {
  884. if ((sys_usage[i] & wcd9378->sys_usage_status)
  885. == wcd9378->sys_usage_status) {
  886. snd_soc_component_update_bits(component,
  887. WCD9378_SYS_USAGE_CTRL,
  888. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  889. i);
  890. wcd9378->sys_usage = i;
  891. dev_dbg(component->dev, "%s: update sys_usage: %d\n",
  892. __func__, wcd9378->sys_usage);
  893. goto exit;
  894. }
  895. }
  896. dev_dbg(component->dev, "%s: cannot find sys_usage\n",
  897. __func__);
  898. } else {
  899. clear_bit(sys_usage_bit, &wcd9378->sys_usage_status);
  900. }
  901. exit:
  902. mutex_unlock(&wcd9378->sys_usage_lock);
  903. return 0;
  904. }
  905. static int wcd9378_sys_usage_bit_get(
  906. struct snd_soc_component *component, u32 w_shift,
  907. int *sys_usage_bit, int event)
  908. {
  909. struct wcd9378_priv *wcd9378 =
  910. snd_soc_component_get_drvdata(component);
  911. dev_dbg(component->dev, "%s: wshift: %d event: %d\n", __func__,
  912. w_shift, event);
  913. switch (event) {
  914. case SND_SOC_DAPM_PRE_PMU:
  915. switch (w_shift) {
  916. case ADC1:
  917. if ((snd_soc_component_read(component,
  918. WCD9378_TX_NEW_TX_CH12_MUX) &
  919. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_MASK) == 0x01) {
  920. *sys_usage_bit = TX0_AMIC1_EN;
  921. } else if ((snd_soc_component_read(component,
  922. WCD9378_TX_NEW_TX_CH12_MUX) &
  923. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_MASK) == 0x02) {
  924. *sys_usage_bit = TX0_AMIC2_EN;
  925. } else {
  926. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  927. __func__);
  928. return -EINVAL;
  929. }
  930. break;
  931. case ADC2:
  932. if ((snd_soc_component_read(component,
  933. WCD9378_TX_NEW_TX_CH12_MUX) &
  934. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10) {
  935. *sys_usage_bit = TX1_AMIC2_EN;
  936. } else if ((snd_soc_component_read(component,
  937. WCD9378_TX_NEW_TX_CH12_MUX) &
  938. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x18) {
  939. *sys_usage_bit = TX1_AMIC3_EN;
  940. } else {
  941. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  942. __func__);
  943. return -EINVAL;
  944. }
  945. break;
  946. case ADC3:
  947. if ((snd_soc_component_read(component,
  948. WCD9378_TX_NEW_TX_CH34_MUX) &
  949. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT) == 0x01) {
  950. *sys_usage_bit = TX2_AMIC1_EN;
  951. } else if ((snd_soc_component_read(component,
  952. WCD9378_TX_NEW_TX_CH34_MUX) &
  953. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT) == 0x03) {
  954. *sys_usage_bit = TX2_AMIC4_EN;
  955. } else {
  956. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  957. __func__);
  958. return -EINVAL;
  959. }
  960. break;
  961. default:
  962. break;
  963. }
  964. break;
  965. case SND_SOC_DAPM_POST_PMD:
  966. switch (w_shift) {
  967. case ADC1:
  968. if (test_bit(TX0_AMIC1_EN, &wcd9378->sys_usage_status))
  969. *sys_usage_bit = TX0_AMIC1_EN;
  970. if (test_bit(TX0_AMIC2_EN, &wcd9378->sys_usage_status))
  971. *sys_usage_bit = TX0_AMIC2_EN;
  972. break;
  973. case ADC2:
  974. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  975. *sys_usage_bit = TX1_AMIC2_EN;
  976. if (test_bit(TX1_AMIC3_EN, &wcd9378->sys_usage_status))
  977. *sys_usage_bit = TX1_AMIC3_EN;
  978. break;
  979. case ADC3:
  980. if (test_bit(TX2_AMIC1_EN, &wcd9378->sys_usage_status))
  981. *sys_usage_bit = TX2_AMIC1_EN;
  982. if (test_bit(TX2_AMIC4_EN, &wcd9378->sys_usage_status))
  983. *sys_usage_bit = TX2_AMIC4_EN;
  984. break;
  985. default:
  986. break;
  987. }
  988. break;
  989. default:
  990. break;
  991. }
  992. dev_dbg(component->dev, "%s: done, event: %d, sys_usage_bit: %d\n",
  993. __func__, event, *sys_usage_bit);
  994. return 0;
  995. }
  996. static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
  997. struct snd_kcontrol *kcontrol, int event)
  998. {
  999. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1000. struct wcd9378_priv *wcd9378 =
  1001. snd_soc_component_get_drvdata(component);
  1002. int mode_val = 0, bank = 0, ret = 0, rate = 0;
  1003. int act_ps = 0, sys_usage_bit = 0;
  1004. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->tx_swr_dev,
  1005. wcd9378->tx_swr_dev->dev_num) ? 0 : 1);
  1006. dev_dbg(component->dev, "%s wname: %s wshift: %d event: %d\n", __func__,
  1007. w->name, w->shift, event);
  1008. ret = wcd9378_sys_usage_bit_get(component, w->shift, &sys_usage_bit, event);
  1009. if (ret < 0)
  1010. return ret;
  1011. switch (event) {
  1012. case SND_SOC_DAPM_PRE_PMU:
  1013. /*Update sys_usage*/
  1014. wcd9378_sys_usage_auto_udpate(component, sys_usage_bit, true);
  1015. mode_val = wcd9378_get_adc_mode_val(wcd9378->tx_mode[w->shift - ADC1]);
  1016. if (mode_val < 0) {
  1017. dev_dbg(component->dev,
  1018. "%s: invalid mode, setting to normal mode\n",
  1019. __func__);
  1020. mode_val = ADC_MODE_VAL_NORMAL;
  1021. }
  1022. rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
  1023. if (w->shift == ADC2 && !((snd_soc_component_read(component,
  1024. WCD9378_TX_NEW_TX_CH12_MUX) &
  1025. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10)) {
  1026. if (!wcd9378->bcs_dis) {
  1027. wcd9378_tx_connect_port(component, MBHC,
  1028. SWR_CLK_RATE_4P8MHZ, true);
  1029. set_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  1030. }
  1031. }
  1032. set_bit(w->shift - ADC1, &wcd9378->status_mask);
  1033. wcd9378_tx_connect_port(component, w->shift, rate,
  1034. true);
  1035. switch (w->shift) {
  1036. case ADC1:
  1037. /*SMP MIC0 IT11 USAGE SET*/
  1038. snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
  1039. WCD9378_IT11_USAGE_IT11_USAGE_MASK, mode_val);
  1040. /*Hold TXFE in Initialization During Startup*/
  1041. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1042. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x40);
  1043. /*Power up TX0 sequencer*/
  1044. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1045. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  1046. break;
  1047. case ADC2:
  1048. /*Check if amic2 is connected to ADC2 MUX*/
  1049. if ((snd_soc_component_read(component,
  1050. WCD9378_TX_NEW_TX_CH12_MUX) &
  1051. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10) {
  1052. /*SMP JACK IT31 USAGE SET*/
  1053. snd_soc_component_update_bits(component,
  1054. WCD9378_IT31_USAGE,
  1055. WCD9378_IT31_USAGE_IT31_USAGE_MASK, mode_val);
  1056. /*Power up TX1 sequencer*/
  1057. snd_soc_component_update_bits(component,
  1058. WCD9378_PDE34_REQ_PS,
  1059. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x00);
  1060. } else {
  1061. snd_soc_component_update_bits(component,
  1062. WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
  1063. WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
  1064. mode_val);
  1065. /*Hold TXFE in Initialization During Startup*/
  1066. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1067. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x20);
  1068. /*Power up TX1 sequencer*/
  1069. snd_soc_component_update_bits(component,
  1070. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
  1071. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
  1072. 0x00);
  1073. }
  1074. break;
  1075. case ADC3:
  1076. /*SMP MIC2 IT11 USAGE SET*/
  1077. snd_soc_component_update_bits(component,
  1078. WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
  1079. WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
  1080. mode_val);
  1081. /*Hold TXFE in Initialization During Startup*/
  1082. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1083. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x40);
  1084. /*Power up TX2 sequencer*/
  1085. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
  1086. WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  1087. break;
  1088. default:
  1089. break;
  1090. }
  1091. /*default delay 800us*/
  1092. usleep_range(800, 810);
  1093. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, true);
  1094. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1095. wcd9378->tx_swr_dev->dev_num,
  1096. true);
  1097. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, true);
  1098. switch (w->shift) {
  1099. case ADC1:
  1100. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1101. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1102. act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
  1103. if (act_ps)
  1104. dev_dbg(component->dev, "%s: tx0 sequencer didnot power on, act_ps: 0x%0x\n",
  1105. __func__, act_ps);
  1106. else
  1107. dev_dbg(component->dev, "%s: tx0 sequencer power on successful, act_ps: 0x%0x\n",
  1108. __func__, act_ps);
  1109. break;
  1110. case ADC2:
  1111. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1112. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x00);
  1113. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  1114. act_ps = snd_soc_component_read(component,
  1115. WCD9378_PDE34_ACT_PS);
  1116. else
  1117. act_ps = snd_soc_component_read(component,
  1118. WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS);
  1119. if (act_ps)
  1120. dev_dbg(component->dev, "%s: tx1 sequencer didnot power on, act_ps: 0x%0x\n",
  1121. __func__, act_ps);
  1122. else
  1123. dev_dbg(component->dev, "%s: tx1 sequencer power on successful, act_ps: 0x%0x\n",
  1124. __func__, act_ps);
  1125. break;
  1126. case ADC3:
  1127. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1128. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  1129. act_ps = snd_soc_component_read(component,
  1130. WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS);
  1131. if (act_ps)
  1132. dev_dbg(component->dev, "%s: tx2 sequencer didnot power on, act_ps: 0x%0x\n",
  1133. __func__, act_ps);
  1134. else
  1135. dev_dbg(component->dev, "%s: tx2 sequencer power on successful, act_ps: 0x%0x\n",
  1136. __func__, act_ps);
  1137. break;
  1138. };
  1139. break;
  1140. case SND_SOC_DAPM_POST_PMD:
  1141. wcd9378_tx_connect_port(component, w->shift, 0, false);
  1142. if (w->shift == ADC2 &&
  1143. test_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask)) {
  1144. wcd9378_tx_connect_port(component, MBHC, 0,
  1145. false);
  1146. clear_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  1147. }
  1148. switch (w->shift) {
  1149. case ADC1:
  1150. /*Normal TXFE Startup*/
  1151. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1152. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1153. /*tear down TX0 sequencer*/
  1154. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1155. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1156. break;
  1157. case ADC2:
  1158. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  1159. /*tear down TX1 sequencer*/
  1160. snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
  1161. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
  1162. if (test_bit(TX1_AMIC3_EN, &wcd9378->sys_usage_status)) {
  1163. /*Normal TXFE Startup*/
  1164. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1165. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1166. /*tear down TX1 sequencer*/
  1167. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1168. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1169. }
  1170. break;
  1171. case ADC3:
  1172. /*Normal TXFE Startup*/
  1173. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1174. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  1175. /*tear down TX2 sequencer*/
  1176. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1177. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1178. break;
  1179. default:
  1180. break;
  1181. }
  1182. /*default delay 800us*/
  1183. usleep_range(800, 810);
  1184. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, false);
  1185. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1186. wcd9378->tx_swr_dev->dev_num,
  1187. false);
  1188. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, false);
  1189. /*Disable sys_usage_status*/
  1190. wcd9378_sys_usage_auto_udpate(component, sys_usage_bit, false);
  1191. break;
  1192. default:
  1193. break;
  1194. }
  1195. return ret;
  1196. }
  1197. static int wcd9378_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1198. struct snd_kcontrol *kcontrol,
  1199. int event)
  1200. {
  1201. struct snd_soc_component *component =
  1202. snd_soc_dapm_to_component(w->dapm);
  1203. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1204. int ret = 0;
  1205. switch (event) {
  1206. case SND_SOC_DAPM_PRE_PMU:
  1207. wcd9378_tx_connect_port(component, w->shift,
  1208. SWR_CLK_RATE_2P4MHZ, true);
  1209. break;
  1210. case SND_SOC_DAPM_POST_PMD:
  1211. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1212. wcd9378->tx_swr_dev->dev_num,
  1213. false);
  1214. break;
  1215. };
  1216. return ret;
  1217. }
  1218. static int wcd9378_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1219. struct snd_kcontrol *kcontrol,
  1220. int event)
  1221. {
  1222. struct snd_soc_component *component =
  1223. snd_soc_dapm_to_component(w->dapm);
  1224. int micb_num = 0;
  1225. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1226. __func__, w->name, event);
  1227. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1228. micb_num = MIC_BIAS_1;
  1229. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1230. micb_num = MIC_BIAS_2;
  1231. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1232. micb_num = MIC_BIAS_3;
  1233. else
  1234. return -EINVAL;
  1235. switch (event) {
  1236. case SND_SOC_DAPM_PRE_PMU:
  1237. wcd9378_micbias_control(component, micb_num,
  1238. MICB_ENABLE, true);
  1239. break;
  1240. case SND_SOC_DAPM_POST_PMU:
  1241. usleep_range(1000, 1100);
  1242. break;
  1243. case SND_SOC_DAPM_POST_PMD:
  1244. wcd9378_micbias_control(component, micb_num,
  1245. MICB_DISABLE, true);
  1246. break;
  1247. };
  1248. return 0;
  1249. }
  1250. static int wcd9378_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1251. struct snd_kcontrol *kcontrol,
  1252. int event)
  1253. {
  1254. struct snd_soc_component *component =
  1255. snd_soc_dapm_to_component(w->dapm);
  1256. int micb_num = 0;
  1257. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1258. __func__, w->name, event);
  1259. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1260. micb_num = MIC_BIAS_1;
  1261. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1262. micb_num = MIC_BIAS_2;
  1263. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1264. micb_num = MIC_BIAS_3;
  1265. else
  1266. return -EINVAL;
  1267. switch (event) {
  1268. case SND_SOC_DAPM_PRE_PMU:
  1269. wcd9378_micbias_control(component, micb_num,
  1270. MICB_PULLUP_ENABLE, true);
  1271. break;
  1272. case SND_SOC_DAPM_POST_PMU:
  1273. usleep_range(1000, 1100);
  1274. break;
  1275. case SND_SOC_DAPM_POST_PMD:
  1276. wcd9378_micbias_control(component, micb_num,
  1277. MICB_PULLUP_DISABLE, true);
  1278. break;
  1279. };
  1280. return 0;
  1281. }
  1282. /*
  1283. * wcd9378_soc_get_mbhc: get wcd9378_mbhc handle of corresponding component
  1284. * @component: handle to snd_soc_component *
  1285. *
  1286. * return wcd9378_mbhc handle or error code in case of failure
  1287. */
  1288. struct wcd9378_mbhc *wcd9378_soc_get_mbhc(struct snd_soc_component *component)
  1289. {
  1290. struct wcd9378_priv *wcd9378;
  1291. if (!component) {
  1292. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  1293. return NULL;
  1294. }
  1295. wcd9378 = snd_soc_component_get_drvdata(component);
  1296. if (!wcd9378) {
  1297. pr_err_ratelimited("%s: wcd9378 is NULL\n", __func__);
  1298. return NULL;
  1299. }
  1300. return wcd9378->mbhc;
  1301. }
  1302. EXPORT_SYMBOL_GPL(wcd9378_soc_get_mbhc);
  1303. static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1304. struct snd_kcontrol *kcontrol,
  1305. int event)
  1306. {
  1307. struct snd_soc_component *component =
  1308. snd_soc_dapm_to_component(w->dapm);
  1309. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1310. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1311. w->name, event);
  1312. switch (event) {
  1313. case SND_SOC_DAPM_PRE_PMU:
  1314. /*HPHL ENABLE*/
  1315. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1316. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1317. wcd9378_rx_connect_port(component, HPH_L, true);
  1318. if (wcd9378->comp1_enable) {
  1319. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1320. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x02);
  1321. wcd9378_rx_connect_port(component, COMP_L, true);
  1322. }
  1323. if (wcd9378->update_wcd_event)
  1324. wcd9378->update_wcd_event(wcd9378->handle,
  1325. SLV_BOLERO_EVT_RX_MUTE,
  1326. (WCD_RX1 << 0x10));
  1327. break;
  1328. case SND_SOC_DAPM_POST_PMD:
  1329. /*HPHL DISABLE*/
  1330. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1331. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1332. wcd9378_rx_connect_port(component, HPH_L, false);
  1333. if (wcd9378->comp1_enable) {
  1334. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1335. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x00);
  1336. wcd9378_rx_connect_port(component, COMP_R, false);
  1337. }
  1338. break;
  1339. default:
  1340. break;
  1341. };
  1342. return 0;
  1343. }
  1344. static int wcd9378_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1345. struct snd_kcontrol *kcontrol,
  1346. int event)
  1347. {
  1348. struct snd_soc_component *component =
  1349. snd_soc_dapm_to_component(w->dapm);
  1350. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1351. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1352. w->name, event);
  1353. switch (event) {
  1354. case SND_SOC_DAPM_PRE_PMU:
  1355. /*HPHR ENABLE*/
  1356. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1357. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1358. wcd9378_rx_connect_port(component, HPH_R, true);
  1359. if (wcd9378->comp2_enable) {
  1360. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1361. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x01);
  1362. wcd9378_rx_connect_port(component, COMP_R, true);
  1363. }
  1364. break;
  1365. case SND_SOC_DAPM_POST_PMD:
  1366. /*HPHR DISABLE*/
  1367. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1368. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x00);
  1369. wcd9378_rx_connect_port(component, HPH_R, false);
  1370. if (wcd9378->comp2_enable) {
  1371. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1372. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x00);
  1373. wcd9378_rx_connect_port(component, COMP_R, false);
  1374. }
  1375. break;
  1376. default:
  1377. break;
  1378. };
  1379. return 0;
  1380. }
  1381. static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1382. struct snd_kcontrol *kcontrol,
  1383. int event)
  1384. {
  1385. struct snd_soc_component *component =
  1386. snd_soc_dapm_to_component(w->dapm);
  1387. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1388. int bank = 0;
  1389. int act_ps = 0;
  1390. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1391. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1392. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1393. w->name, event);
  1394. switch (event) {
  1395. case SND_SOC_DAPM_PRE_PMU:
  1396. if (wcd9378->update_wcd_event)
  1397. wcd9378->update_wcd_event(wcd9378->handle,
  1398. SLV_BOLERO_EVT_RX_MUTE,
  1399. (WCD_RX1 << 0x10 | 0x01));
  1400. if (wcd9378->update_wcd_event)
  1401. wcd9378->update_wcd_event(wcd9378->handle,
  1402. SLV_BOLERO_EVT_RX_MUTE,
  1403. (WCD_RX1 << 0x10));
  1404. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1405. if (act_ps)
  1406. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1407. __func__, act_ps);
  1408. else
  1409. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1410. __func__, act_ps);
  1411. break;
  1412. case SND_SOC_DAPM_POST_PMD:
  1413. if (wcd9378->update_wcd_event)
  1414. wcd9378->update_wcd_event(wcd9378->handle,
  1415. SLV_BOLERO_EVT_RX_MUTE,
  1416. (WCD_RX1 << 0x10 | 0x1));
  1417. if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
  1418. wcd9378->update_wcd_event(wcd9378->handle,
  1419. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1420. (WCD_RX1 << 0x10));
  1421. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1422. WCD_EVENT_POST_HPHL_PA_OFF,
  1423. &wcd9378->mbhc->wcd_mbhc);
  1424. break;
  1425. default:
  1426. break;
  1427. };
  1428. return 0;
  1429. }
  1430. static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1431. struct snd_kcontrol *kcontrol,
  1432. int event)
  1433. {
  1434. struct snd_soc_component *component =
  1435. snd_soc_dapm_to_component(w->dapm);
  1436. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1437. int act_ps = 0;
  1438. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1439. w->name, event);
  1440. switch (event) {
  1441. case SND_SOC_DAPM_PRE_PMU:
  1442. if (wcd9378->update_wcd_event)
  1443. wcd9378->update_wcd_event(wcd9378->handle,
  1444. SLV_BOLERO_EVT_RX_MUTE,
  1445. (WCD_RX2 << 0x10 | 0x1));
  1446. if (wcd9378->update_wcd_event)
  1447. wcd9378->update_wcd_event(wcd9378->handle,
  1448. SLV_BOLERO_EVT_RX_MUTE,
  1449. (WCD_RX2 << 0x10));
  1450. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1451. if (act_ps)
  1452. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1453. __func__, act_ps);
  1454. else
  1455. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1456. __func__, act_ps);
  1457. break;
  1458. case SND_SOC_DAPM_POST_PMD:
  1459. if (wcd9378->update_wcd_event)
  1460. wcd9378->update_wcd_event(wcd9378->handle,
  1461. SLV_BOLERO_EVT_RX_MUTE,
  1462. (WCD_RX2 << 0x10 | 0x1));
  1463. if (wcd9378->update_wcd_event && wcd9378->comp2_enable)
  1464. wcd9378->update_wcd_event(wcd9378->handle,
  1465. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1466. (WCD_RX2 << 0x10));
  1467. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1468. WCD_EVENT_POST_HPHR_PA_OFF,
  1469. &wcd9378->mbhc->wcd_mbhc);
  1470. break;
  1471. default:
  1472. break;
  1473. };
  1474. return 0;
  1475. }
  1476. static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1477. struct snd_kcontrol *kcontrol,
  1478. int event)
  1479. {
  1480. struct snd_soc_component *component =
  1481. snd_soc_dapm_to_component(w->dapm);
  1482. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1483. int ret = 0;
  1484. int bank = 0;
  1485. int act_ps = 0;
  1486. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1487. w->name, event);
  1488. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1489. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1490. switch (event) {
  1491. case SND_SOC_DAPM_PRE_PMU:
  1492. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1493. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1494. wcd9378->rx_swr_dev->dev_num,
  1495. true);
  1496. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1497. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1498. if (wcd9378->update_wcd_event)
  1499. wcd9378->update_wcd_event(wcd9378->handle,
  1500. SLV_BOLERO_EVT_RX_MUTE,
  1501. (WCD_RX2 << 0x10));
  1502. } else {
  1503. if (wcd9378->update_wcd_event)
  1504. wcd9378->update_wcd_event(wcd9378->handle,
  1505. SLV_BOLERO_EVT_RX_MUTE,
  1506. (WCD_RX3 << 0x10));
  1507. }
  1508. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1509. if (act_ps)
  1510. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1511. __func__, act_ps);
  1512. else
  1513. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1514. __func__, act_ps);
  1515. break;
  1516. case SND_SOC_DAPM_POST_PMD:
  1517. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1518. if (wcd9378->update_wcd_event)
  1519. wcd9378->update_wcd_event(wcd9378->handle,
  1520. SLV_BOLERO_EVT_RX_MUTE,
  1521. (WCD_RX2 << 0x10 | 0x1));
  1522. } else {
  1523. if (wcd9378->update_wcd_event)
  1524. wcd9378->update_wcd_event(wcd9378->handle,
  1525. SLV_BOLERO_EVT_RX_MUTE,
  1526. (WCD_RX3 << 0x10 | 0x1));
  1527. }
  1528. break;
  1529. };
  1530. return ret;
  1531. }
  1532. static int wcd9378_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1533. struct snd_kcontrol *kcontrol,
  1534. int event)
  1535. {
  1536. struct snd_soc_component *component =
  1537. snd_soc_dapm_to_component(w->dapm);
  1538. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1539. int ret = 0, bank = 0;
  1540. int act_ps = 0;
  1541. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1542. w->name, event);
  1543. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1544. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1545. switch (event) {
  1546. case SND_SOC_DAPM_PRE_PMU:
  1547. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1548. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1549. wcd9378->rx_swr_dev->dev_num,
  1550. true);
  1551. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1552. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1553. if (wcd9378->update_wcd_event)
  1554. wcd9378->update_wcd_event(wcd9378->handle,
  1555. SLV_BOLERO_EVT_RX_MUTE,
  1556. (WCD_RX1 << 0x10));
  1557. } else {
  1558. if (wcd9378->update_wcd_event)
  1559. wcd9378->update_wcd_event(wcd9378->handle,
  1560. SLV_BOLERO_EVT_RX_MUTE,
  1561. (WCD_RX3 << 0x10));
  1562. }
  1563. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1564. if (act_ps)
  1565. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1566. __func__, act_ps);
  1567. else
  1568. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1569. __func__, act_ps);
  1570. break;
  1571. case SND_SOC_DAPM_POST_PMD:
  1572. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1573. if (wcd9378->update_wcd_event)
  1574. wcd9378->update_wcd_event(wcd9378->handle,
  1575. SLV_BOLERO_EVT_RX_MUTE,
  1576. (WCD_RX1 << 0x10 | 0x1));
  1577. } else {
  1578. if (wcd9378->update_wcd_event)
  1579. wcd9378->update_wcd_event(wcd9378->handle,
  1580. SLV_BOLERO_EVT_RX_MUTE,
  1581. (WCD_RX3 << 0x10 | 0x1));
  1582. }
  1583. break;
  1584. };
  1585. return ret;
  1586. }
  1587. static int wcd9378_get_hph_pwr_level(int hph_mode)
  1588. {
  1589. switch (hph_mode) {
  1590. case CLS_H_LOHIFI:
  1591. case CLS_AB_LOHIFI:
  1592. return PWR_LEVEL_LOHIFI_VAL;
  1593. case CLS_H_LP:
  1594. case CLS_AB_LP:
  1595. return PWR_LEVEL_LP_VAL;
  1596. case CLS_H_HIFI:
  1597. case CLS_AB_HIFI:
  1598. return PWR_LEVEL_HIFI_VAL;
  1599. case CLS_H_ULP:
  1600. case CLS_AB:
  1601. case CLS_H_NORMAL:
  1602. default:
  1603. return PWR_LEVEL_ULP_VAL;
  1604. }
  1605. return PWR_LEVEL_ULP_VAL;
  1606. }
  1607. static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component)
  1608. {
  1609. struct wcd9378_priv *wcd9378 =
  1610. snd_soc_component_get_drvdata(component);
  1611. if ((!wcd9378->comp1_enable) &&
  1612. (!wcd9378->comp2_enable)) {
  1613. dev_err(component->dev, "%s hph gainis 0x%0xd\n", __func__, wcd9378->hph_gain);
  1614. snd_soc_component_update_bits(component,
  1615. (WCD9378_FU42_CH_VOL_CH1 | WCD9378_MBQ_ENABLE_MASK),
  1616. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1617. wcd9378->hph_gain >> 8);
  1618. snd_soc_component_update_bits(component,
  1619. WCD9378_FU42_CH_VOL_CH1,
  1620. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1621. wcd9378->hph_gain & 0x00ff);
  1622. snd_soc_component_update_bits(component,
  1623. (WCD9378_FU42_CH_VOL_CH2 | WCD9378_MBQ_ENABLE_MASK),
  1624. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1625. wcd9378->hph_gain >> 8);
  1626. snd_soc_component_update_bits(component,
  1627. WCD9378_FU42_CH_VOL_CH2,
  1628. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1629. wcd9378->hph_gain & 0x00ff);
  1630. }
  1631. }
  1632. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable)
  1633. {
  1634. u16 clk_scale_reg = 0;
  1635. u8 clk_rst = 0x00, scale_rst = 0x00;
  1636. u8 swr_base_clk = 0, swr_clk_scale = 0;
  1637. struct wcd9378_priv *wcd9378 = NULL;
  1638. struct swr_device *swr_dev = NULL;
  1639. wcd9378 = dev_get_drvdata(dev);
  1640. if (!wcd9378)
  1641. return -EINVAL;
  1642. if (path == RX_PATH) {
  1643. swr_dev = wcd9378->rx_swr_dev;
  1644. swr_base_clk = wcd9378->swr_base_clk;
  1645. swr_clk_scale = wcd9378->swr_clk_scale;
  1646. } else {
  1647. swr_dev = wcd9378->tx_swr_dev;
  1648. swr_base_clk = SWR_BASECLK_19P2MHZ;
  1649. swr_clk_scale = SWR_CLKSCALE_DIV2;
  1650. }
  1651. clk_scale_reg = (bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
  1652. SWRS_SCP_BUSCLOCK_SCALE_BANK0);
  1653. if (enable) {
  1654. swr_write(swr_dev, swr_dev->dev_num,
  1655. SWRS_SCP_BASE_CLK_BASE, &swr_base_clk);
  1656. swr_write(swr_dev, swr_dev->dev_num,
  1657. clk_scale_reg, &swr_clk_scale);
  1658. } else {
  1659. swr_write(swr_dev, swr_dev->dev_num,
  1660. SWRS_SCP_BASE_CLK_BASE, &clk_rst);
  1661. swr_write(swr_dev, swr_dev->dev_num,
  1662. clk_scale_reg, &scale_rst);
  1663. }
  1664. return 0;
  1665. }
  1666. static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
  1667. struct snd_kcontrol *kcontrol, int event)
  1668. {
  1669. struct snd_soc_component *component =
  1670. snd_soc_dapm_to_component(w->dapm);
  1671. struct wcd9378_priv *wcd9378 =
  1672. snd_soc_component_get_drvdata(component);
  1673. int power_level, bank = 0;
  1674. int ret = 0;
  1675. struct swr_device *swr_dev = wcd9378->tx_swr_dev;
  1676. u8 scp_commit_val = 0x2;
  1677. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1678. w->name, event);
  1679. switch (event) {
  1680. case SND_SOC_DAPM_PRE_PMU:
  1681. wcd9378_sys_usage_auto_udpate(component, RX0_RX1_HPH_EN, true);
  1682. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) {
  1683. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7,
  1684. WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07);
  1685. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T1,
  1686. WCD9378_HPH_DN_T1_HPH_DN_T1_MASK, 0x07);
  1687. }
  1688. if ((wcd9378->hph_mode == CLS_AB) ||
  1689. (wcd9378->hph_mode == CLS_AB_HIFI) ||
  1690. (wcd9378->hph_mode == CLS_AB_LP) ||
  1691. (wcd9378->hph_mode == CLS_AB_LOHIFI))
  1692. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1693. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1694. /*GET HPH_MODE*/
  1695. power_level = wcd9378_get_hph_pwr_level(wcd9378->hph_mode);
  1696. /*SET HPH_MODE*/
  1697. snd_soc_component_update_bits(component, WCD9378_IT41_USAGE,
  1698. WCD9378_IT41_USAGE_IT41_USAGE_MASK, power_level);
  1699. /*TURN ON HPH SEQUENCER*/
  1700. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1701. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x00);
  1702. /*TBD: SET SDCA GAIN, NEED CHECK THE LOGIC*/
  1703. wcd9378_hph_set_channel_volume(component);
  1704. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable))
  1705. /*PA delay is 22400us*/
  1706. usleep_range(22500, 22510);
  1707. else
  1708. /*COMP delay is 9400us*/
  1709. usleep_range(9500, 9510);
  1710. /*RX0 unmute*/
  1711. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1712. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x00);
  1713. /*RX1 unmute*/
  1714. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1715. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00);
  1716. if (wcd9378->sys_usage == SYS_USAGE_10)
  1717. /*FU23 UNMUTE*/
  1718. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1719. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1720. swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val);
  1721. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1722. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1723. wcd9378->rx_swr_dev->dev_num,
  1724. true);
  1725. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1726. break;
  1727. case SND_SOC_DAPM_POST_PMD:
  1728. /*RX0 mute*/
  1729. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1730. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x01);
  1731. /*RX1 mute*/
  1732. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1733. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x01);
  1734. /*TEAR DOWN HPH SEQUENCER*/
  1735. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1736. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x03);
  1737. if (!wcd9378->comp1_enable || !wcd9378->comp2_enable)
  1738. /*PA delay is 24250us*/
  1739. usleep_range(24300, 24310);
  1740. else
  1741. /*COMP delay is 11250us*/
  1742. usleep_range(11300, 11310);
  1743. wcd9378_sys_usage_auto_udpate(component, RX0_RX1_HPH_EN, false);
  1744. break;
  1745. default:
  1746. break;
  1747. };
  1748. return ret;
  1749. }
  1750. static int wcd9378_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1751. struct snd_kcontrol *kcontrol,
  1752. int event)
  1753. {
  1754. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1755. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1756. int ear_rx2 = 0;
  1757. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1758. w->name, event);
  1759. ear_rx2 = snd_soc_component_read(component, WCD9378_CDC_AUX_GAIN_CTL) &
  1760. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK;
  1761. switch (event) {
  1762. case SND_SOC_DAPM_PRE_PMU:
  1763. if (!ear_rx2) {
  1764. /*RX0 ENABLE*/
  1765. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1766. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1767. wcd9378_sys_usage_auto_udpate(component, RX0_EAR_EN, true);
  1768. if (wcd9378->comp1_enable) {
  1769. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1770. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x04);
  1771. wcd9378_rx_connect_port(component, COMP_L, true);
  1772. }
  1773. wcd9378_rx_connect_port(component, HPH_L, true);
  1774. } else {
  1775. wcd9378_sys_usage_auto_udpate(component, RX2_EAR_EN, true);
  1776. /*FORCE CLASS_AB EN*/
  1777. snd_soc_component_update_bits(component, WCD9378_SEQ_OVRRIDE_CTL0,
  1778. WCD9378_SEQ_OVRRIDE_CTL0_CLASSAB_EN_OVR_MASK, 0x20);
  1779. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1780. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1781. if (wcd9378->rx2_clk_mode)
  1782. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1783. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1784. wcd9378_rx_connect_port(component, LO, true);
  1785. }
  1786. break;
  1787. case SND_SOC_DAPM_POST_PMD:
  1788. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1789. /*RX0 DISABLE*/
  1790. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1791. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1792. wcd9378_rx_connect_port(component, HPH_L, false);
  1793. if (wcd9378->comp1_enable) {
  1794. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1795. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x00);
  1796. wcd9378_rx_connect_port(component, COMP_L, false);
  1797. }
  1798. wcd9378_sys_usage_auto_udpate(component, RX0_EAR_EN, false);
  1799. } else {
  1800. wcd9378_rx_connect_port(component, LO, false);
  1801. wcd9378_sys_usage_auto_udpate(component, RX2_EAR_EN, false);
  1802. }
  1803. break;
  1804. };
  1805. return 0;
  1806. }
  1807. static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  1808. struct snd_kcontrol *kcontrol,
  1809. int event)
  1810. {
  1811. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1812. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1813. int aux_rx2 = 0;
  1814. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1815. w->name, event);
  1816. aux_rx2 = snd_soc_component_read(component, WCD9378_CDC_AUX_GAIN_CTL) &
  1817. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK;
  1818. switch (event) {
  1819. case SND_SOC_DAPM_PRE_PMU:
  1820. if (!aux_rx2) {
  1821. /*RX1 ENABLE*/
  1822. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1823. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1824. wcd9378_sys_usage_auto_udpate(component, RX1_AUX_EN, true);
  1825. wcd9378_rx_connect_port(component, HPH_R, true);
  1826. } else {
  1827. wcd9378_sys_usage_auto_udpate(component, RX2_AUX_EN, true);
  1828. if (wcd9378->rx2_clk_mode)
  1829. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1830. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1831. wcd9378_rx_connect_port(component, LO, true);
  1832. }
  1833. break;
  1834. case SND_SOC_DAPM_POST_PMD:
  1835. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1836. wcd9378_rx_connect_port(component, HPH_R, false);
  1837. wcd9378_sys_usage_auto_udpate(component, RX1_AUX_EN, false);
  1838. } else {
  1839. wcd9378_rx_connect_port(component, LO, true);
  1840. wcd9378_sys_usage_auto_udpate(component, RX2_AUX_EN, false);
  1841. }
  1842. break;
  1843. };
  1844. return 0;
  1845. }
  1846. static int wcd9378_sa_sequencer_enable(struct snd_soc_dapm_widget *w,
  1847. struct snd_kcontrol *kcontrol, int event)
  1848. {
  1849. struct snd_soc_component *component =
  1850. snd_soc_dapm_to_component(w->dapm);
  1851. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1852. w->name, event);
  1853. switch (event) {
  1854. case SND_SOC_DAPM_PRE_PMU:
  1855. /*TURN ON AMP SEQUENCER*/
  1856. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1857. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x00);
  1858. /*default delay 8550us*/
  1859. usleep_range(8600, 8610);
  1860. /*FU23 UNMUTE*/
  1861. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1862. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1863. break;
  1864. case SND_SOC_DAPM_POST_PMD:
  1865. /*FU23 MUTE*/
  1866. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1867. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x01);
  1868. /*TEAR DOWN AMP SEQUENCER*/
  1869. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1870. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x03);
  1871. /*default delay 1530us*/
  1872. usleep_range(15400, 15410);
  1873. break;
  1874. default:
  1875. break;
  1876. };
  1877. return 0;
  1878. }
  1879. int wcd9378_micbias_control(struct snd_soc_component *component,
  1880. int micb_num, int req, bool is_dapm)
  1881. {
  1882. struct wcd9378_priv *wcd9378 =
  1883. snd_soc_component_get_drvdata(component);
  1884. struct wcd9378_pdata *pdata =
  1885. dev_get_platdata(wcd9378->dev);
  1886. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  1887. int micb_usage = 0, micb_mask = 0, micb_usage_val = 0;
  1888. int pre_off_event = 0, post_off_event = 0;
  1889. int post_on_event = 0, post_dapm_off = 0;
  1890. int post_dapm_on = 0;
  1891. int pull_up_mask = 0, pull_up_en = 0;
  1892. int micb_index = 0, ret = 0;
  1893. switch (micb_num) {
  1894. case MIC_BIAS_1:
  1895. pull_up_mask = WCD9378_MB_PULLUP_EN_MB1_1P8V_OR_PULLUP_SEL_MASK;
  1896. pull_up_en = 0x01;
  1897. micb_usage = WCD9378_IT11_MICB;
  1898. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  1899. micb_usage_val = mb->micb1_usage_val;
  1900. break;
  1901. case MIC_BIAS_2:
  1902. pull_up_mask = WCD9378_MB_PULLUP_EN_MB2_1P8V_OR_PULLUP_SEL_MASK;
  1903. pull_up_en = 0x02;
  1904. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  1905. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  1906. micb_usage_val = mb->micb2_usage_val;
  1907. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1908. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1909. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1910. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1911. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1912. break;
  1913. case MIC_BIAS_3:
  1914. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  1915. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  1916. pull_up_mask = WCD9378_MB_PULLUP_EN_MB3_1P8V_OR_PULLUP_SEL_MASK;
  1917. pull_up_en = 0x04;
  1918. micb_usage_val = mb->micb3_usage_val;
  1919. break;
  1920. default:
  1921. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1922. __func__, micb_num);
  1923. return -EINVAL;
  1924. }
  1925. mutex_lock(&wcd9378->micb_lock);
  1926. micb_index = micb_num - 1;
  1927. switch (req) {
  1928. case MICB_PULLUP_ENABLE:
  1929. wcd9378->pullup_ref[micb_index]++;
  1930. if ((wcd9378->pullup_ref[micb_index] == 1) &&
  1931. (wcd9378->micb_ref[micb_index] == 0)) {
  1932. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1933. pull_up_mask, pull_up_en);
  1934. snd_soc_component_update_bits(component,
  1935. micb_usage, micb_mask, 0x03);
  1936. if (micb_num == MIC_BIAS_2) {
  1937. dev_dbg(component->dev, "%s: pull up sj micbias\n",
  1938. __func__);
  1939. snd_soc_component_update_bits(component,
  1940. WCD9378_IT31_MICB,
  1941. WCD9378_IT31_MICB_IT31_MICB_MASK,
  1942. 0x03);
  1943. wcd9378->curr_micbias2 = 1800;
  1944. }
  1945. }
  1946. break;
  1947. case MICB_PULLUP_DISABLE:
  1948. if (wcd9378->pullup_ref[micb_index] > 0)
  1949. wcd9378->pullup_ref[micb_index]--;
  1950. if ((wcd9378->pullup_ref[micb_index] == 0) &&
  1951. (wcd9378->micb_ref[micb_index] == 0)) {
  1952. snd_soc_component_update_bits(component, micb_usage, micb_mask, 0x01);
  1953. if (micb_num == MIC_BIAS_2) {
  1954. dev_dbg(component->dev, "%s: pull down sj micbias\n",
  1955. __func__);
  1956. snd_soc_component_update_bits(component,
  1957. WCD9378_IT31_MICB,
  1958. WCD9378_IT31_MICB_IT31_MICB_MASK,
  1959. 0x01);
  1960. wcd9378->curr_micbias2 = 0;
  1961. }
  1962. }
  1963. break;
  1964. case MICB_ENABLE:
  1965. dev_dbg(component->dev, "%s: micbias enable enter\n",
  1966. __func__);
  1967. if (!wcd9378->dev_up) {
  1968. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1969. __func__, req);
  1970. ret = -ENODEV;
  1971. goto done;
  1972. }
  1973. wcd9378->micb_ref[micb_index]++;
  1974. if (wcd9378->micb_ref[micb_index] == 1) {
  1975. dev_dbg(component->dev, "%s: enable micbias, micb_usage:0x%0x, val:0x%0x\n",
  1976. __func__, micb_usage, micb_usage_val);
  1977. snd_soc_component_update_bits(component,
  1978. micb_usage, micb_mask, micb_usage_val);
  1979. if (micb_num == MIC_BIAS_2) {
  1980. dev_dbg(component->dev, "%s: enable sj micbias\n",
  1981. __func__);
  1982. snd_soc_component_update_bits(component,
  1983. WCD9378_IT31_MICB,
  1984. WCD9378_IT31_MICB_IT31_MICB_MASK,
  1985. micb_usage_val);
  1986. wcd9378->curr_micbias2 = 1800;
  1987. }
  1988. if (post_on_event)
  1989. blocking_notifier_call_chain(
  1990. &wcd9378->mbhc->notifier,
  1991. post_on_event,
  1992. &wcd9378->mbhc->wcd_mbhc);
  1993. }
  1994. if (is_dapm && post_dapm_on && wcd9378->mbhc)
  1995. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1996. post_dapm_on,
  1997. &wcd9378->mbhc->wcd_mbhc);
  1998. break;
  1999. case MICB_DISABLE:
  2000. dev_dbg(component->dev, "%s: micbias disable enter\n",
  2001. __func__);
  2002. if (wcd9378->micb_ref[micb_index] > 0)
  2003. wcd9378->micb_ref[micb_index]--;
  2004. if ((wcd9378->micb_ref[micb_index] == 0) &&
  2005. (wcd9378->pullup_ref[micb_index] > 0)) {
  2006. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  2007. pull_up_mask, pull_up_en);
  2008. if (micb_num == MIC_BIAS_2)
  2009. wcd9378->curr_micbias2 = 1800;
  2010. } else if ((wcd9378->micb_ref[micb_index] == 0) &&
  2011. (wcd9378->pullup_ref[micb_index] == 0)) {
  2012. if (pre_off_event && wcd9378->mbhc)
  2013. blocking_notifier_call_chain(
  2014. &wcd9378->mbhc->notifier,
  2015. pre_off_event,
  2016. &wcd9378->mbhc->wcd_mbhc);
  2017. snd_soc_component_update_bits(component, micb_usage,
  2018. micb_mask, 0x00);
  2019. if (micb_num == MIC_BIAS_2) {
  2020. snd_soc_component_update_bits(component,
  2021. WCD9378_IT31_MICB,
  2022. WCD9378_IT31_MICB_IT31_MICB_MASK,
  2023. 0x00);
  2024. wcd9378->curr_micbias2 = 0;
  2025. }
  2026. if (post_off_event && wcd9378->mbhc)
  2027. blocking_notifier_call_chain(
  2028. &wcd9378->mbhc->notifier,
  2029. post_off_event,
  2030. &wcd9378->mbhc->wcd_mbhc);
  2031. }
  2032. if (is_dapm && post_dapm_off && wcd9378->mbhc)
  2033. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  2034. post_dapm_off,
  2035. &wcd9378->mbhc->wcd_mbhc);
  2036. break;
  2037. default:
  2038. dev_err(component->dev, "%s: Invalid req event: %d\n",
  2039. __func__, req);
  2040. return -EINVAL;
  2041. }
  2042. dev_dbg(component->dev,
  2043. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  2044. __func__, micb_num, wcd9378->micb_ref[micb_index],
  2045. wcd9378->pullup_ref[micb_index]);
  2046. done:
  2047. mutex_unlock(&wcd9378->micb_lock);
  2048. return ret;
  2049. }
  2050. EXPORT_SYMBOL_GPL(wcd9378_micbias_control);
  2051. static int wcd9378_get_logical_addr(struct swr_device *swr_dev)
  2052. {
  2053. int ret = 0;
  2054. uint8_t devnum = 0;
  2055. int num_retry = NUM_ATTEMPTS;
  2056. do {
  2057. /* retry after 4ms */
  2058. usleep_range(4000, 4010);
  2059. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  2060. } while (ret && --num_retry);
  2061. if (ret)
  2062. dev_err(&swr_dev->dev,
  2063. "%s get devnum %d for dev addr %llx failed\n",
  2064. __func__, devnum, swr_dev->addr);
  2065. swr_dev->dev_num = devnum;
  2066. return 0;
  2067. }
  2068. static bool get_usbc_hs_status(struct snd_soc_component *component,
  2069. struct wcd_mbhc_config *mbhc_cfg)
  2070. {
  2071. if (mbhc_cfg->enable_usbc_analog) {
  2072. if (!(snd_soc_component_read(component, WCD9378_ANA_MBHC_MECH)
  2073. & 0x20))
  2074. return true;
  2075. }
  2076. return false;
  2077. }
  2078. int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *component,
  2079. struct notifier_block *nblock,
  2080. bool enable)
  2081. {
  2082. struct wcd9378_priv *wcd9378_priv = NULL;
  2083. if (component == NULL) {
  2084. pr_err_ratelimited("%s: wcd9378 component is NULL\n", __func__);
  2085. return -EINVAL;
  2086. }
  2087. wcd9378_priv = snd_soc_component_get_drvdata(component);
  2088. wcd9378_priv->notify_swr_dmic = enable;
  2089. if (enable)
  2090. return blocking_notifier_chain_register(&wcd9378_priv->notifier,
  2091. nblock);
  2092. else
  2093. return blocking_notifier_chain_unregister(
  2094. &wcd9378_priv->notifier, nblock);
  2095. }
  2096. EXPORT_SYMBOL_GPL(wcd9378_swr_dmic_register_notifier);
  2097. static int wcd9378_event_notify(struct notifier_block *block,
  2098. unsigned long val,
  2099. void *data)
  2100. {
  2101. u16 event = (val & 0xffff);
  2102. int ret = 0;
  2103. struct wcd9378_priv *wcd9378 = dev_get_drvdata((struct device *)data);
  2104. struct snd_soc_component *component = wcd9378->component;
  2105. struct wcd_mbhc *mbhc;
  2106. int rx_clk_type;
  2107. switch (event) {
  2108. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2109. if (test_bit(WCD_ADC1, &wcd9378->status_mask)) {
  2110. snd_soc_component_update_bits(component,
  2111. WCD9378_ANA_TX_CH2, 0x40, 0x00);
  2112. set_bit(WCD_ADC1_MODE, &wcd9378->status_mask);
  2113. clear_bit(WCD_ADC1, &wcd9378->status_mask);
  2114. }
  2115. if (test_bit(WCD_ADC2, &wcd9378->status_mask)) {
  2116. snd_soc_component_update_bits(component,
  2117. WCD9378_ANA_TX_CH2, 0x20, 0x00);
  2118. set_bit(WCD_ADC2_MODE, &wcd9378->status_mask);
  2119. clear_bit(WCD_ADC2, &wcd9378->status_mask);
  2120. }
  2121. if (test_bit(WCD_ADC3, &wcd9378->status_mask)) {
  2122. snd_soc_component_update_bits(component,
  2123. WCD9378_ANA_TX_CH3_HPF, 0x40, 0x00);
  2124. set_bit(WCD_ADC3_MODE, &wcd9378->status_mask);
  2125. clear_bit(WCD_ADC3, &wcd9378->status_mask);
  2126. }
  2127. break;
  2128. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2129. snd_soc_component_update_bits(component, WCD9378_ANA_HPH,
  2130. 0xC0, 0x00);
  2131. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  2132. 0x80, 0x00);
  2133. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  2134. 0x80, 0x00);
  2135. break;
  2136. case BOLERO_SLV_EVT_SSR_DOWN:
  2137. wcd9378->dev_up = false;
  2138. if (wcd9378->notify_swr_dmic)
  2139. blocking_notifier_call_chain(&wcd9378->notifier,
  2140. WCD9378_EVT_SSR_DOWN,
  2141. NULL);
  2142. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = true;
  2143. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2144. wcd9378->usbc_hs_status = get_usbc_hs_status(component,
  2145. mbhc->mbhc_cfg);
  2146. wcd9378_mbhc_ssr_down(wcd9378->mbhc, component);
  2147. wcd9378_reset_low(wcd9378->dev);
  2148. break;
  2149. case BOLERO_SLV_EVT_SSR_UP:
  2150. wcd9378_reset(wcd9378->dev);
  2151. /* allow reset to take effect */
  2152. usleep_range(10000, 10010);
  2153. wcd9378_get_logical_addr(wcd9378->tx_swr_dev);
  2154. wcd9378_get_logical_addr(wcd9378->rx_swr_dev);
  2155. wcd9378->tx_swr_dev->scp1_val = 0;
  2156. wcd9378->tx_swr_dev->scp2_val = 0;
  2157. wcd9378->rx_swr_dev->scp1_val = 0;
  2158. wcd9378->rx_swr_dev->scp2_val = 0;
  2159. wcd9378_init_reg(component);
  2160. regcache_mark_dirty(wcd9378->regmap);
  2161. regcache_sync(wcd9378->regmap);
  2162. /* Initialize MBHC module */
  2163. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2164. ret = wcd9378_mbhc_post_ssr_init(wcd9378->mbhc, component);
  2165. if (ret) {
  2166. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2167. __func__);
  2168. } else {
  2169. wcd9378_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2170. }
  2171. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = false;
  2172. wcd9378->dev_up = true;
  2173. if (wcd9378->notify_swr_dmic)
  2174. blocking_notifier_call_chain(&wcd9378->notifier,
  2175. WCD9378_EVT_SSR_UP,
  2176. NULL);
  2177. if (wcd9378->usbc_hs_status)
  2178. mdelay(500);
  2179. break;
  2180. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2181. snd_soc_component_update_bits(component,
  2182. WCD9378_TOP_CLK_CFG, 0x06,
  2183. ((val >> 0x10) << 0x01));
  2184. rx_clk_type = (val >> 0x10);
  2185. switch (rx_clk_type) {
  2186. case RX_CLK_12P288MHZ:
  2187. wcd9378->swr_base_clk = SWR_BASECLK_24P576MHZ;
  2188. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2189. break;
  2190. case RX_CLK_11P2896MHZ:
  2191. wcd9378->swr_base_clk = SWR_BASECLK_22P5792MHZ;
  2192. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2193. break;
  2194. default:
  2195. wcd9378->swr_base_clk = SWR_BASECLK_19P2MHZ;
  2196. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2197. break;
  2198. }
  2199. dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
  2200. __func__, wcd9378->swr_base_clk, wcd9378->swr_clk_scale);
  2201. break;
  2202. default:
  2203. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2204. break;
  2205. }
  2206. return 0;
  2207. }
  2208. static int wcd9378_wakeup(void *handle, bool enable)
  2209. {
  2210. struct wcd9378_priv *priv;
  2211. int ret = 0;
  2212. if (!handle) {
  2213. pr_err("%s: NULL handle\n", __func__);
  2214. return -EINVAL;
  2215. }
  2216. priv = (struct wcd9378_priv *)handle;
  2217. if (!priv->tx_swr_dev) {
  2218. pr_err("%s: tx swr dev is NULL\n", __func__);
  2219. return -EINVAL;
  2220. }
  2221. mutex_lock(&priv->wakeup_lock);
  2222. if (enable)
  2223. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2224. else
  2225. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2226. mutex_unlock(&priv->wakeup_lock);
  2227. return ret;
  2228. }
  2229. static inline int wcd9378_tx_path_get(const char *wname,
  2230. unsigned int *path_num)
  2231. {
  2232. int ret = 0;
  2233. char *widget_name = NULL;
  2234. char *w_name = NULL;
  2235. char *path_num_char = NULL;
  2236. char *path_name = NULL;
  2237. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2238. if (!widget_name)
  2239. return -EINVAL;
  2240. w_name = widget_name;
  2241. path_name = strsep(&widget_name, " ");
  2242. if (!path_name) {
  2243. pr_err("%s: Invalid widget name = %s\n",
  2244. __func__, widget_name);
  2245. ret = -EINVAL;
  2246. goto err;
  2247. }
  2248. path_num_char = strpbrk(path_name, "0123");
  2249. if (!path_num_char) {
  2250. pr_err("%s: tx path index not found\n",
  2251. __func__);
  2252. ret = -EINVAL;
  2253. goto err;
  2254. }
  2255. ret = kstrtouint(path_num_char, 10, path_num);
  2256. if (ret < 0)
  2257. pr_err("%s: Invalid tx path = %s\n",
  2258. __func__, w_name);
  2259. err:
  2260. kfree(w_name);
  2261. return ret;
  2262. }
  2263. static int wcd9378_tx_mode_get(struct snd_kcontrol *kcontrol,
  2264. struct snd_ctl_elem_value *ucontrol)
  2265. {
  2266. struct snd_soc_component *component =
  2267. snd_soc_kcontrol_component(kcontrol);
  2268. struct wcd9378_priv *wcd9378 = NULL;
  2269. int ret = 0;
  2270. unsigned int path = 0;
  2271. if (!component)
  2272. return -EINVAL;
  2273. wcd9378 = snd_soc_component_get_drvdata(component);
  2274. if (!wcd9378)
  2275. return -EINVAL;
  2276. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2277. if (ret < 0)
  2278. return ret;
  2279. ucontrol->value.integer.value[0] = wcd9378->tx_mode[path];
  2280. return 0;
  2281. }
  2282. static int wcd9378_tx_mode_put(struct snd_kcontrol *kcontrol,
  2283. struct snd_ctl_elem_value *ucontrol)
  2284. {
  2285. struct snd_soc_component *component =
  2286. snd_soc_kcontrol_component(kcontrol);
  2287. struct wcd9378_priv *wcd9378 = NULL;
  2288. u32 mode_val;
  2289. unsigned int path = 0;
  2290. int ret = 0;
  2291. if (!component)
  2292. return -EINVAL;
  2293. wcd9378 = snd_soc_component_get_drvdata(component);
  2294. if (!wcd9378)
  2295. return -EINVAL;
  2296. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2297. if (ret)
  2298. return ret;
  2299. mode_val = ucontrol->value.enumerated.item[0];
  2300. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2301. wcd9378->tx_mode[path] = mode_val;
  2302. return 0;
  2303. }
  2304. static int wcd9378_loopback_mode_get(struct snd_kcontrol *kcontrol,
  2305. struct snd_ctl_elem_value *ucontrol)
  2306. {
  2307. struct snd_soc_component *component =
  2308. snd_soc_kcontrol_component(kcontrol);
  2309. u32 loopback_mode = 0;
  2310. if (!component)
  2311. return -EINVAL;
  2312. loopback_mode = (snd_soc_component_read(component, WCD9378_LOOP_BACK_MODE) &
  2313. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK);
  2314. ucontrol->value.integer.value[0] = loopback_mode;
  2315. return 0;
  2316. }
  2317. static int wcd9378_loopback_mode_put(struct snd_kcontrol *kcontrol,
  2318. struct snd_ctl_elem_value *ucontrol)
  2319. {
  2320. struct snd_soc_component *component =
  2321. snd_soc_kcontrol_component(kcontrol);
  2322. u32 loopback_mode = 0;
  2323. if (!component)
  2324. return -EINVAL;
  2325. loopback_mode = ucontrol->value.enumerated.item[0];
  2326. snd_soc_component_update_bits(component,
  2327. WCD9378_LOOP_BACK_MODE,
  2328. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK,
  2329. loopback_mode);
  2330. dev_dbg(component->dev, "%s: loopback_mode: %d\n",
  2331. __func__, loopback_mode);
  2332. return 0;
  2333. }
  2334. static int wcd9378_aux_dsm_get(struct snd_kcontrol *kcontrol,
  2335. struct snd_ctl_elem_value *ucontrol)
  2336. {
  2337. struct snd_soc_component *component =
  2338. snd_soc_kcontrol_component(kcontrol);
  2339. u32 aux_dsm_in = 0;
  2340. if (!component)
  2341. return -EINVAL;
  2342. aux_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2343. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK);
  2344. ucontrol->value.integer.value[0] = aux_dsm_in;
  2345. return 0;
  2346. }
  2347. static int wcd9378_aux_dsm_put(struct snd_kcontrol *kcontrol,
  2348. struct snd_ctl_elem_value *ucontrol)
  2349. {
  2350. struct snd_soc_component *component =
  2351. snd_soc_kcontrol_component(kcontrol);
  2352. u32 aux_dsm_in = 0;
  2353. if (!component)
  2354. return -EINVAL;
  2355. aux_dsm_in = ucontrol->value.enumerated.item[0];
  2356. snd_soc_component_update_bits(component,
  2357. WCD9378_LB_IN_SEL_CTL,
  2358. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK,
  2359. aux_dsm_in);
  2360. dev_dbg(component->dev, "%s: aux_dsm input: %d\n",
  2361. __func__, aux_dsm_in);
  2362. return 0;
  2363. }
  2364. static int wcd9378_hph_dsm_get(struct snd_kcontrol *kcontrol,
  2365. struct snd_ctl_elem_value *ucontrol)
  2366. {
  2367. struct snd_soc_component *component =
  2368. snd_soc_kcontrol_component(kcontrol);
  2369. u32 hph_dsm_in = 0;
  2370. if (!component)
  2371. return -EINVAL;
  2372. hph_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2373. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK);
  2374. ucontrol->value.integer.value[0] = hph_dsm_in;
  2375. return 0;
  2376. }
  2377. static int wcd9378_hph_dsm_put(struct snd_kcontrol *kcontrol,
  2378. struct snd_ctl_elem_value *ucontrol)
  2379. {
  2380. struct snd_soc_component *component =
  2381. snd_soc_kcontrol_component(kcontrol);
  2382. u32 hph_dsm_in = 0;
  2383. if (!component)
  2384. return -EINVAL;
  2385. hph_dsm_in = ucontrol->value.enumerated.item[0];
  2386. snd_soc_component_update_bits(component,
  2387. WCD9378_LB_IN_SEL_CTL,
  2388. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK,
  2389. hph_dsm_in);
  2390. dev_dbg(component->dev, "%s: hph_dsm input: %d\n",
  2391. __func__, hph_dsm_in);
  2392. return 0;
  2393. }
  2394. static int wcd9378_hph_put_gain(struct snd_kcontrol *kcontrol,
  2395. struct snd_ctl_elem_value *ucontrol)
  2396. {
  2397. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2398. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2399. u16 offset = ucontrol->value.enumerated.item[0];
  2400. u32 temp = 0;
  2401. temp = 0x00 - offset * 0x180;
  2402. wcd9378->hph_gain = (u16)(temp & 0xffff);
  2403. dev_dbg(component->dev, "%s: hph gain is 0x%0x\n", __func__, wcd9378->hph_gain);
  2404. return 0;
  2405. }
  2406. static int wcd9378_hph_get_gain(struct snd_kcontrol *kcontrol,
  2407. struct snd_ctl_elem_value *ucontrol)
  2408. {
  2409. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2410. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2411. u32 temp = 0;
  2412. u16 offset = 0;
  2413. temp = 0 - wcd9378->hph_gain;
  2414. offset = (u16)(temp & 0xffff);
  2415. offset /= 0x180;
  2416. ucontrol->value.enumerated.item[0] = offset;
  2417. dev_dbg(component->dev, "%s: offset is 0x%0x\n", __func__, offset);
  2418. return 0;
  2419. }
  2420. static int wcd9378_rx2_mode_put(struct snd_kcontrol *kcontrol,
  2421. struct snd_ctl_elem_value *ucontrol)
  2422. {
  2423. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2424. struct wcd9378_priv *wcd9378 =
  2425. snd_soc_component_get_drvdata(component);
  2426. if (ucontrol->value.enumerated.item[0])
  2427. wcd9378->rx2_clk_mode = RX2_NORMAL_MODE;
  2428. else
  2429. wcd9378->rx2_clk_mode = RX2_HP_MODE;
  2430. return 1;
  2431. }
  2432. static int wcd9378_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2433. struct snd_ctl_elem_value *ucontrol)
  2434. {
  2435. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2436. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2437. ucontrol->value.enumerated.item[0] = wcd9378->hph_mode;
  2438. return 0;
  2439. }
  2440. static int wcd9378_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2441. struct snd_ctl_elem_value *ucontrol)
  2442. {
  2443. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2444. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2445. if (wcd9378->hph_mode == ucontrol->value.enumerated.item[0])
  2446. return 0;
  2447. wcd9378->hph_mode = ucontrol->value.enumerated.item[0];
  2448. return 1;
  2449. }
  2450. /* wcd9378_codec_get_dev_num - returns swr device number
  2451. * @component: Codec instance
  2452. *
  2453. * Return: swr device number on success or negative error
  2454. * code on failure.
  2455. */
  2456. int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
  2457. {
  2458. struct wcd9378_priv *wcd9378;
  2459. if (!component)
  2460. return -EINVAL;
  2461. wcd9378 = snd_soc_component_get_drvdata(component);
  2462. if (!wcd9378 || !wcd9378->rx_swr_dev) {
  2463. pr_err("%s: wcd9378 component is NULL\n", __func__);
  2464. return -EINVAL;
  2465. }
  2466. return wcd9378->rx_swr_dev->dev_num;
  2467. }
  2468. EXPORT_SYMBOL_GPL(wcd9378_codec_get_dev_num);
  2469. static int wcd9378_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
  2470. struct snd_ctl_elem_value *ucontrol)
  2471. {
  2472. struct snd_soc_component *component =
  2473. snd_soc_kcontrol_component(kcontrol);
  2474. struct wcd9378_priv *wcd9378 =
  2475. snd_soc_component_get_drvdata(component);
  2476. if (wcd9378->comp1_enable) {
  2477. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2478. return -EINVAL;
  2479. }
  2480. snd_soc_component_update_bits(component, WCD9378_AUX_INT_MISC,
  2481. WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK,
  2482. ucontrol->value.integer.value[0]);
  2483. return 1;
  2484. }
  2485. static int wcd9378_aux_pa_put_gain(struct snd_kcontrol *kcontrol,
  2486. struct snd_ctl_elem_value *ucontrol)
  2487. {
  2488. struct snd_soc_component *component =
  2489. snd_soc_kcontrol_component(kcontrol);
  2490. struct wcd9378_priv *wcd9378 =
  2491. snd_soc_component_get_drvdata(component);
  2492. if (wcd9378->comp1_enable) {
  2493. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2494. return -EINVAL;
  2495. }
  2496. snd_soc_component_update_bits(component, WCD9378_ANA_EAR_COMPANDER_CTL,
  2497. WCD9378_AUX_INT_MISC_PA_GAIN_MASK,
  2498. ucontrol->value.integer.value[0]);
  2499. return 1;
  2500. }
  2501. static int wcd9378_get_compander(struct snd_kcontrol *kcontrol,
  2502. struct snd_ctl_elem_value *ucontrol)
  2503. {
  2504. struct snd_soc_component *component =
  2505. snd_soc_kcontrol_component(kcontrol);
  2506. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2507. bool hphr;
  2508. struct soc_multi_mixer_control *mc;
  2509. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2510. hphr = mc->shift;
  2511. ucontrol->value.integer.value[0] = hphr ? wcd9378->comp2_enable :
  2512. wcd9378->comp1_enable;
  2513. return 0;
  2514. }
  2515. static int wcd9378_set_compander(struct snd_kcontrol *kcontrol,
  2516. struct snd_ctl_elem_value *ucontrol)
  2517. {
  2518. struct snd_soc_component *component =
  2519. snd_soc_kcontrol_component(kcontrol);
  2520. struct wcd9378_priv *wcd9378 =
  2521. snd_soc_component_get_drvdata(component);
  2522. int value = ucontrol->value.integer.value[0];
  2523. bool hphr;
  2524. struct soc_multi_mixer_control *mc;
  2525. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2526. hphr = mc->shift;
  2527. if (hphr)
  2528. wcd9378->comp2_enable = value;
  2529. else
  2530. wcd9378->comp1_enable = value;
  2531. dev_dbg(component->dev, "%s: set compander: %d\n", __func__, value);
  2532. return 0;
  2533. }
  2534. static int wcd9378_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2535. struct snd_kcontrol *kcontrol,
  2536. int event)
  2537. {
  2538. struct snd_soc_component *component =
  2539. snd_soc_dapm_to_component(w->dapm);
  2540. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2541. struct wcd9378_pdata *pdata = NULL;
  2542. int ret = 0;
  2543. pdata = dev_get_platdata(wcd9378->dev);
  2544. if (!pdata) {
  2545. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2546. return -EINVAL;
  2547. }
  2548. if (!msm_cdc_is_ondemand_supply(wcd9378->dev,
  2549. wcd9378->supplies,
  2550. pdata->regulator,
  2551. pdata->num_supplies,
  2552. "cdc-vdd-buck"))
  2553. return 0;
  2554. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2555. w->name, event);
  2556. switch (event) {
  2557. case SND_SOC_DAPM_PRE_PMU:
  2558. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  2559. dev_dbg(component->dev,
  2560. "%s: buck already in enabled state\n",
  2561. __func__);
  2562. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2563. return 0;
  2564. }
  2565. ret = msm_cdc_enable_ondemand_supply(wcd9378->dev,
  2566. wcd9378->supplies,
  2567. pdata->regulator,
  2568. pdata->num_supplies,
  2569. "cdc-vdd-buck");
  2570. if (ret == -EINVAL) {
  2571. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2572. __func__);
  2573. return ret;
  2574. }
  2575. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2576. /*
  2577. * 200us sleep is required after LDO is enabled as per
  2578. * HW requirement
  2579. */
  2580. usleep_range(200, 250);
  2581. break;
  2582. case SND_SOC_DAPM_POST_PMD:
  2583. set_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2584. break;
  2585. }
  2586. return 0;
  2587. }
  2588. const char * const tx_master_ch_text[] = {
  2589. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2590. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2591. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2592. "SWRM_PCM_IN",
  2593. };
  2594. const struct soc_enum tx_master_ch_enum =
  2595. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2596. tx_master_ch_text);
  2597. static void wcd9378_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2598. {
  2599. u8 ch_type = 0;
  2600. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2601. ch_type = ADC1;
  2602. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2603. ch_type = ADC2;
  2604. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2605. ch_type = ADC3;
  2606. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2607. ch_type = ADC4;
  2608. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2609. ch_type = DMIC0;
  2610. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2611. ch_type = DMIC1;
  2612. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2613. ch_type = MBHC;
  2614. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2615. ch_type = DMIC2;
  2616. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2617. ch_type = DMIC3;
  2618. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2619. ch_type = DMIC4;
  2620. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2621. ch_type = DMIC5;
  2622. else
  2623. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2624. if (ch_type)
  2625. *ch_idx = wcd9378_slave_get_slave_ch_val(ch_type);
  2626. else
  2627. *ch_idx = -EINVAL;
  2628. }
  2629. static int wcd9378_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2630. struct snd_ctl_elem_value *ucontrol)
  2631. {
  2632. struct snd_soc_component *component =
  2633. snd_soc_kcontrol_component(kcontrol);
  2634. struct wcd9378_priv *wcd9378 = NULL;
  2635. int slave_ch_idx = -EINVAL;
  2636. if (component == NULL)
  2637. return -EINVAL;
  2638. wcd9378 = snd_soc_component_get_drvdata(component);
  2639. if (wcd9378 == NULL)
  2640. return -EINVAL;
  2641. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2642. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2643. return -EINVAL;
  2644. ucontrol->value.integer.value[0] = wcd9378_slave_get_master_ch_val(
  2645. wcd9378->tx_master_ch_map[slave_ch_idx]);
  2646. return 0;
  2647. }
  2648. static int wcd9378_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2649. struct snd_ctl_elem_value *ucontrol)
  2650. {
  2651. struct snd_soc_component *component =
  2652. snd_soc_kcontrol_component(kcontrol);
  2653. struct wcd9378_priv *wcd9378 = NULL;
  2654. int slave_ch_idx = -EINVAL, idx = 0;
  2655. if (component == NULL)
  2656. return -EINVAL;
  2657. wcd9378 = snd_soc_component_get_drvdata(component);
  2658. if (wcd9378 == NULL)
  2659. return -EINVAL;
  2660. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2661. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2662. return -EINVAL;
  2663. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2664. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2665. __func__, ucontrol->value.enumerated.item[0]);
  2666. idx = ucontrol->value.enumerated.item[0];
  2667. if (idx < 0 || idx >= ARRAY_SIZE(wcd9378_swr_master_ch_map))
  2668. return -EINVAL;
  2669. wcd9378->tx_master_ch_map[slave_ch_idx] = wcd9378_slave_get_master_ch(idx);
  2670. return 0;
  2671. }
  2672. static int wcd9378_bcs_get(struct snd_kcontrol *kcontrol,
  2673. struct snd_ctl_elem_value *ucontrol)
  2674. {
  2675. struct snd_soc_component *component =
  2676. snd_soc_kcontrol_component(kcontrol);
  2677. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2678. ucontrol->value.integer.value[0] = wcd9378->bcs_dis;
  2679. return 0;
  2680. }
  2681. static int wcd9378_bcs_put(struct snd_kcontrol *kcontrol,
  2682. struct snd_ctl_elem_value *ucontrol)
  2683. {
  2684. struct snd_soc_component *component =
  2685. snd_soc_kcontrol_component(kcontrol);
  2686. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2687. wcd9378->bcs_dis = ucontrol->value.integer.value[0];
  2688. return 0;
  2689. }
  2690. static const char * const loopback_mode_text[] = {
  2691. "NO_LP", "SWR_LP1", "SWR_LP2", "SWR_LP3",
  2692. };
  2693. static const struct soc_enum loopback_mode_enum =
  2694. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mode_text),
  2695. loopback_mode_text);
  2696. static const char * const aux_dsm_text[] = {
  2697. "TX2->AUX", "TX3->AUX", "TX0->AUX", "TX1->AUX",
  2698. };
  2699. static const struct soc_enum aux_dsm_enum =
  2700. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_dsm_text),
  2701. aux_dsm_text);
  2702. static const char * const hph_dsm_text[] = {
  2703. "HPH_DSM_IN0", "HPH_DSM_IN1", "HPH_DSM_IN2", "HPH_DSM_IN3",
  2704. };
  2705. static const struct soc_enum hph_dsm_enum =
  2706. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(hph_dsm_text),
  2707. hph_dsm_text);
  2708. static const char * const tx_mode_mux_text[] = {
  2709. "ADC_INVALID", "ADC_HIFI", "ADC_NORMAL", "ADC_LP",
  2710. };
  2711. static const struct soc_enum tx_mode_mux_enum =
  2712. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2713. tx_mode_mux_text);
  2714. static const char * const rx2_mode_text[] = {
  2715. "HP", "NORMAL",
  2716. };
  2717. static const struct soc_enum rx2_mode_enum =
  2718. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx2_mode_text),
  2719. rx2_mode_text);
  2720. static const char * const rx_hph_mode_mux_text[] = {
  2721. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2722. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2723. };
  2724. static const struct soc_enum rx_hph_mode_mux_enum =
  2725. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2726. rx_hph_mode_mux_text);
  2727. static const struct snd_kcontrol_new wcd9378_snd_controls[] = {
  2728. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2729. wcd9378_get_compander, wcd9378_set_compander),
  2730. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2731. wcd9378_get_compander, wcd9378_set_compander),
  2732. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2733. wcd9378_bcs_get, wcd9378_bcs_put),
  2734. SOC_ENUM_EXT("LOOPBACK Mode", loopback_mode_enum,
  2735. wcd9378_loopback_mode_get, wcd9378_loopback_mode_put),
  2736. SOC_ENUM_EXT("AUX_LB_IN SEL", aux_dsm_enum,
  2737. wcd9378_aux_dsm_get, wcd9378_aux_dsm_put),
  2738. SOC_ENUM_EXT("HPH_LB_IN SEL", hph_dsm_enum,
  2739. wcd9378_hph_dsm_get, wcd9378_hph_dsm_put),
  2740. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2741. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2742. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2743. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2744. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2745. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2746. SOC_ENUM_EXT("RX2 Mode", rx2_mode_enum,
  2747. NULL, wcd9378_rx2_mode_put),
  2748. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2749. wcd9378_rx_hph_mode_get, wcd9378_rx_hph_mode_put),
  2750. SOC_SINGLE_EXT("HPH Volume", SND_SOC_NOPM, 0, 0x14, 0,
  2751. wcd9378_hph_get_gain, wcd9378_hph_put_gain),
  2752. WCD9378_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD9378_ANA_EAR_COMPANDER_CTL,
  2753. 2, 0x10, 0, ear_pa_gain),
  2754. WCD9378_AUX_PA_GAIN_TLV("AUX_PA Volume", WCD9378_AUX_INT_MISC,
  2755. 0, 0x8, 0, aux_pa_gain),
  2756. SOC_SINGLE_TLV("ADC1 Volume", WCD9378_ANA_TX_CH1, 0, 20, 0,
  2757. analog_gain),
  2758. SOC_SINGLE_TLV("ADC2 Volume", WCD9378_ANA_TX_CH2, 0, 20, 0,
  2759. analog_gain),
  2760. SOC_SINGLE_TLV("ADC3 Volume", WCD9378_ANA_TX_CH3, 0, 20, 0,
  2761. analog_gain),
  2762. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2763. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2764. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2765. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2766. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2767. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2768. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2769. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2770. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2771. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2772. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2773. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2774. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2775. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2776. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2777. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2778. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2779. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2780. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2781. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2782. };
  2783. static const struct snd_kcontrol_new amic1_switch[] = {
  2784. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2785. };
  2786. static const struct snd_kcontrol_new amic2_switch[] = {
  2787. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2788. };
  2789. static const struct snd_kcontrol_new amic3_switch[] = {
  2790. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2791. };
  2792. static const struct snd_kcontrol_new amic4_switch[] = {
  2793. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2794. };
  2795. static const struct snd_kcontrol_new va_amic1_switch[] = {
  2796. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2797. };
  2798. static const struct snd_kcontrol_new va_amic2_switch[] = {
  2799. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2800. };
  2801. static const struct snd_kcontrol_new va_amic3_switch[] = {
  2802. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2803. };
  2804. static const struct snd_kcontrol_new va_amic4_switch[] = {
  2805. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2806. };
  2807. static const struct snd_kcontrol_new dmic1_switch[] = {
  2808. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2809. };
  2810. static const struct snd_kcontrol_new dmic2_switch[] = {
  2811. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2812. };
  2813. static const struct snd_kcontrol_new dmic3_switch[] = {
  2814. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2815. };
  2816. static const struct snd_kcontrol_new dmic4_switch[] = {
  2817. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2818. };
  2819. static const struct snd_kcontrol_new dmic5_switch[] = {
  2820. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2821. };
  2822. static const struct snd_kcontrol_new dmic6_switch[] = {
  2823. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2824. };
  2825. static const char * const adc1_mux_text[] = {
  2826. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4"
  2827. };
  2828. static const char * const adc2_mux_text[] = {
  2829. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4"
  2830. };
  2831. static const char * const adc3_mux_text[] = {
  2832. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4"
  2833. };
  2834. static const char * const ear_mux_text[] = {
  2835. "RX0", "RX2"
  2836. };
  2837. static const char * const aux_mux_text[] = {
  2838. "RX1", "RX2"
  2839. };
  2840. static const struct soc_enum adc1_enum =
  2841. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2842. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT,
  2843. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  2844. static const struct soc_enum adc2_enum =
  2845. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2846. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT,
  2847. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2848. static const struct soc_enum adc3_enum =
  2849. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH34_MUX,
  2850. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT,
  2851. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2852. static const struct soc_enum ear_enum =
  2853. SOC_ENUM_SINGLE(WCD9378_CDC_AUX_GAIN_CTL,
  2854. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_SHIFT,
  2855. ARRAY_SIZE(ear_mux_text), ear_mux_text);
  2856. static const struct soc_enum aux_enum =
  2857. SOC_ENUM_SINGLE(WCD9378_CDC_AUX_GAIN_CTL,
  2858. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_SHIFT,
  2859. ARRAY_SIZE(aux_mux_text), aux_mux_text);
  2860. static const struct snd_kcontrol_new tx_adc1_mux =
  2861. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  2862. static const struct snd_kcontrol_new tx_adc2_mux =
  2863. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2864. static const struct snd_kcontrol_new tx_adc3_mux =
  2865. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2866. static const struct snd_kcontrol_new ear_mux =
  2867. SOC_DAPM_ENUM("EAR Mux", ear_enum);
  2868. static const struct snd_kcontrol_new aux_mux =
  2869. SOC_DAPM_ENUM("AUX Mux", aux_enum);
  2870. static const struct snd_kcontrol_new dac1_switch[] = {
  2871. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2872. };
  2873. static const struct snd_kcontrol_new dac2_switch[] = {
  2874. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2875. };
  2876. static const struct snd_kcontrol_new ear_mixer_switch[] = {
  2877. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2878. };
  2879. static const struct snd_kcontrol_new aux_mixer_switch[] = {
  2880. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2881. };
  2882. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2883. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2884. };
  2885. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2886. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2887. };
  2888. static const struct snd_kcontrol_new rx0_switch[] = {
  2889. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2890. };
  2891. static const struct snd_kcontrol_new rx1_switch[] = {
  2892. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2893. };
  2894. static const struct snd_soc_dapm_widget wcd9378_dapm_widgets[] = {
  2895. /*input widgets*/
  2896. SND_SOC_DAPM_INPUT("AMIC1"),
  2897. SND_SOC_DAPM_INPUT("AMIC2"),
  2898. SND_SOC_DAPM_INPUT("AMIC3"),
  2899. SND_SOC_DAPM_INPUT("AMIC4"),
  2900. SND_SOC_DAPM_INPUT("VA AMIC1"),
  2901. SND_SOC_DAPM_INPUT("VA AMIC2"),
  2902. SND_SOC_DAPM_INPUT("VA AMIC3"),
  2903. SND_SOC_DAPM_INPUT("VA AMIC4"),
  2904. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2905. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2906. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2907. /*tx widgets*/
  2908. SND_SOC_DAPM_MIXER_E("TX0 SEQUENCER", SND_SOC_NOPM, ADC1, 0,
  2909. NULL, 0, wcd9378_tx_sequencer_enable,
  2910. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2911. SND_SOC_DAPM_MIXER_E("TX1 SEQUENCER", SND_SOC_NOPM, ADC2, 0,
  2912. NULL, 0, wcd9378_tx_sequencer_enable,
  2913. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2914. SND_SOC_DAPM_MIXER_E("TX2 SEQUENCER", SND_SOC_NOPM, ADC3, 0,
  2915. NULL, 0, wcd9378_tx_sequencer_enable,
  2916. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2917. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  2918. &tx_adc1_mux),
  2919. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2920. &tx_adc2_mux),
  2921. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2922. &tx_adc3_mux),
  2923. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2924. wcd9378_codec_enable_dmic,
  2925. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2926. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2927. wcd9378_codec_enable_dmic,
  2928. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2929. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2930. wcd9378_codec_enable_dmic,
  2931. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2932. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2933. wcd9378_codec_enable_dmic,
  2934. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2935. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2936. wcd9378_codec_enable_dmic,
  2937. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2938. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2939. wcd9378_codec_enable_dmic,
  2940. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2941. /*rx widgets*/
  2942. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2943. wcd9378_codec_hphl_dac_event,
  2944. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2945. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2946. wcd9378_codec_hphr_dac_event,
  2947. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2948. SND_SOC_DAPM_MIXER_E("HPH SEQUENCER", SND_SOC_NOPM, 0, 0, NULL, 0,
  2949. wcd9378_hph_sequencer_enable,
  2950. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2951. SND_SOC_DAPM_PGA_E("HPHL PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2952. wcd9378_codec_enable_hphl_pa,
  2953. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2954. SND_SOC_DAPM_PGA_E("HPHR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2955. wcd9378_codec_enable_hphr_pa,
  2956. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2957. SND_SOC_DAPM_MIXER_E("SA SEQUENCER", SND_SOC_NOPM, 0, 0,
  2958. NULL, 0, wcd9378_sa_sequencer_enable,
  2959. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2960. SND_SOC_DAPM_DAC_E("EAR_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2961. wcd9378_codec_ear_dac_event,
  2962. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2963. SND_SOC_DAPM_DAC_E("AUX_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2964. wcd9378_codec_aux_dac_event,
  2965. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2966. SND_SOC_DAPM_PGA_E("EAR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2967. wcd9378_codec_enable_ear_pa,
  2968. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2969. SND_SOC_DAPM_PGA_E("AUX PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2970. wcd9378_codec_enable_aux_pa,
  2971. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2972. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2973. wcd9378_codec_enable_vdd_buck,
  2974. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2975. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2976. wcd9378_enable_clsh,
  2977. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2978. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  2979. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  2980. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2981. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  2982. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  2983. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2984. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  2985. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  2986. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2987. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  2988. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  2989. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2990. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  2991. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  2992. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2993. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  2994. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  2995. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2996. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  2997. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  2998. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2999. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3000. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3001. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3002. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3003. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3004. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3005. SND_SOC_DAPM_POST_PMD),
  3006. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3007. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3008. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3009. SND_SOC_DAPM_POST_PMD),
  3010. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3011. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3012. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3013. SND_SOC_DAPM_POST_PMD),
  3014. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3015. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3016. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3017. SND_SOC_DAPM_POST_PMD),
  3018. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3019. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3020. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3021. SND_SOC_DAPM_POST_PMD),
  3022. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3023. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3024. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3025. SND_SOC_DAPM_POST_PMD),
  3026. /* micbias widgets*/
  3027. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3028. wcd9378_codec_enable_micbias,
  3029. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3030. SND_SOC_DAPM_POST_PMD),
  3031. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3032. wcd9378_codec_enable_micbias,
  3033. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3034. SND_SOC_DAPM_POST_PMD),
  3035. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3036. wcd9378_codec_enable_micbias,
  3037. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3038. SND_SOC_DAPM_POST_PMD),
  3039. /* micbias pull up widgets*/
  3040. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3041. wcd9378_codec_enable_micbias_pullup,
  3042. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3043. SND_SOC_DAPM_POST_PMD),
  3044. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3045. wcd9378_codec_enable_micbias_pullup,
  3046. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3047. SND_SOC_DAPM_POST_PMD),
  3048. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3049. wcd9378_codec_enable_micbias_pullup,
  3050. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3051. SND_SOC_DAPM_POST_PMD),
  3052. /* rx mixer widgets*/
  3053. SND_SOC_DAPM_MUX("EAR_MUX", SND_SOC_NOPM, 0, 0, &ear_mux),
  3054. SND_SOC_DAPM_MUX("AUX_MUX", SND_SOC_NOPM, 0, 0, &aux_mux),
  3055. SND_SOC_DAPM_MIXER("EAR_MIXER", SND_SOC_NOPM, 0, 0,
  3056. ear_mixer_switch, ARRAY_SIZE(ear_mixer_switch)),
  3057. SND_SOC_DAPM_MIXER("AUX_MIXER", SND_SOC_NOPM, 0, 0,
  3058. aux_mixer_switch, ARRAY_SIZE(aux_mixer_switch)),
  3059. SND_SOC_DAPM_MIXER("DAC1", SND_SOC_NOPM, 0, 0,
  3060. dac1_switch, ARRAY_SIZE(dac1_switch)),
  3061. SND_SOC_DAPM_MIXER("DAC2", SND_SOC_NOPM, 0, 0,
  3062. dac2_switch, ARRAY_SIZE(dac2_switch)),
  3063. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3064. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3065. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3066. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3067. /*output widgets tx*/
  3068. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  3069. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  3070. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  3071. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  3072. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  3073. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  3074. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  3075. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  3076. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  3077. /*output widgets rx*/
  3078. SND_SOC_DAPM_OUTPUT("EAR"),
  3079. SND_SOC_DAPM_OUTPUT("AUX"),
  3080. SND_SOC_DAPM_OUTPUT("HPHL"),
  3081. SND_SOC_DAPM_OUTPUT("HPHR"),
  3082. };
  3083. static const struct snd_soc_dapm_route wcd9378_audio_map[] = {
  3084. /*ADC-1 (channel-1)*/
  3085. {"ADC1_OUTPUT", NULL, "TX0 SEQUENCER"},
  3086. {"TX0 SEQUENCER", NULL, "ADC1 MUX"},
  3087. {"ADC1 MUX", "CH1_AMIC1", "AMIC1_MIXER"},
  3088. {"ADC1 MUX", "CH1_AMIC2", "AMIC2_MIXER"},
  3089. {"ADC1 MUX", "CH1_AMIC3", "AMIC3_MIXER"},
  3090. {"ADC1 MUX", "CH1_AMIC4", "AMIC4_MIXER"},
  3091. /*ADC-2 (channel-2)*/
  3092. {"ADC2_OUTPUT", NULL, "TX1 SEQUENCER"},
  3093. {"TX1 SEQUENCER", NULL, "ADC2 MUX"},
  3094. {"ADC2 MUX", "CH2_AMIC1", "AMIC1_MIXER"},
  3095. {"ADC2 MUX", "CH2_AMIC2", "AMIC2_MIXER"},
  3096. {"ADC2 MUX", "CH2_AMIC3", "AMIC3_MIXER"},
  3097. {"ADC2 MUX", "CH2_AMIC4", "AMIC4_MIXER"},
  3098. /*ADC-3 (channel-3)*/
  3099. {"ADC3_OUTPUT", NULL, "TX2 SEQUENCER"},
  3100. {"TX2 SEQUENCER", NULL, "ADC3 MUX"},
  3101. {"ADC3 MUX", "CH3_AMIC1", "AMIC1_MIXER"},
  3102. {"ADC3 MUX", "CH3_AMIC3", "AMIC3_MIXER"},
  3103. {"ADC3 MUX", "CH3_AMIC4", "AMIC4_MIXER"},
  3104. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3105. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3106. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3107. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3108. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3109. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3110. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3111. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3112. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3113. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3114. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3115. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3116. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  3117. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3118. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  3119. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3120. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  3121. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3122. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  3123. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3124. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  3125. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3126. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  3127. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3128. /*Headphone playback*/
  3129. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3130. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3131. {"HPH SEQUENCER", NULL, "IN1_HPHL"},
  3132. {"RDAC1", NULL, "HPH SEQUENCER"},
  3133. {"HPHL_RDAC", "Switch", "RDAC1"},
  3134. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3135. {"HPHL", NULL, "HPHL PGA"},
  3136. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3137. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3138. {"HPH SEQUENCER", NULL, "IN2_HPHR"},
  3139. {"RDAC2", NULL, "HPH SEQUENCER"},
  3140. {"HPHR_RDAC", "Switch", "RDAC2"},
  3141. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3142. {"HPHR", NULL, "HPHR PGA"},
  3143. /*Amplier playback*/
  3144. {"IN3_AUX", NULL, "VDD_BUCK"},
  3145. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3146. {"EAR_MUX", "RX0", "IN1_HPHL"},
  3147. {"EAR_MUX", "RX2", "IN3_AUX"},
  3148. {"DAC1", "Switch", "EAR_MUX"},
  3149. {"EAR_RDAC", NULL, "DAC1"},
  3150. {"SA SEQUENCER", NULL, "EAR_RDAC"},
  3151. {"EAR_MIXER", "Switch", "SA SEQUENCER"},
  3152. {"EAR PGA", NULL, "EAR_MIXER"},
  3153. {"EAR", NULL, "EAR PGA"},
  3154. {"AUX_MUX", "RX1", "IN2_HPHR"},
  3155. {"AUX_MUX", "RX2", "IN3_AUX"},
  3156. {"DAC2", "Switch", "AUX_MUX"},
  3157. {"AUX_RDAC", NULL, "DAC2"},
  3158. {"SA SEQUENCER", NULL, "AUX_RDAC"},
  3159. {"AUX_MIXER", "Switch", "SA SEQUENCER",},
  3160. {"AUX PGA", NULL, "AUX_MIXER"},
  3161. {"AUX", NULL, "AUX PGA"},
  3162. };
  3163. static ssize_t wcd9378_version_read(struct snd_info_entry *entry,
  3164. void *file_private_data,
  3165. struct file *file,
  3166. char __user *buf, size_t count,
  3167. loff_t pos)
  3168. {
  3169. struct wcd9378_priv *priv;
  3170. char buffer[WCD9378_VERSION_ENTRY_SIZE];
  3171. int len = 0;
  3172. priv = (struct wcd9378_priv *) entry->private_data;
  3173. if (!priv) {
  3174. pr_err("%s: wcd9378 priv is null\n", __func__);
  3175. return -EINVAL;
  3176. }
  3177. switch (priv->version) {
  3178. case WCD9378_VERSION_1_0:
  3179. len = scnprintf(buffer, sizeof(buffer), "WCD9378_1_0\n");
  3180. break;
  3181. default:
  3182. len = scnprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3183. }
  3184. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3185. }
  3186. static struct snd_info_entry_ops wcd9378_info_ops = {
  3187. .read = wcd9378_version_read,
  3188. };
  3189. /*
  3190. * wcd9378_info_create_codec_entry - creates wcd9378 module
  3191. * @codec_root: The parent directory
  3192. * @component: component instance
  3193. *
  3194. * Creates wcd9378 module, version entry under the given
  3195. * parent directory.
  3196. *
  3197. * Return: 0 on success or negative error code on failure.
  3198. */
  3199. int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
  3200. struct snd_soc_component *component)
  3201. {
  3202. struct snd_info_entry *version_entry;
  3203. struct wcd9378_priv *priv;
  3204. struct snd_soc_card *card;
  3205. if (!codec_root || !component)
  3206. return -EINVAL;
  3207. priv = snd_soc_component_get_drvdata(component);
  3208. if (priv->entry) {
  3209. dev_dbg(priv->dev,
  3210. "%s:wcd9378 module already created\n", __func__);
  3211. return 0;
  3212. }
  3213. card = component->card;
  3214. priv->entry = snd_info_create_module_entry(codec_root->module,
  3215. "wcd9378", codec_root);
  3216. if (!priv->entry) {
  3217. dev_dbg(component->dev, "%s: failed to create wcd9378 entry\n",
  3218. __func__);
  3219. return -ENOMEM;
  3220. }
  3221. priv->entry->mode = S_IFDIR | 0555;
  3222. if (snd_info_register(priv->entry) < 0) {
  3223. snd_info_free_entry(priv->entry);
  3224. return -ENOMEM;
  3225. }
  3226. version_entry = snd_info_create_card_entry(card->snd_card,
  3227. "version",
  3228. priv->entry);
  3229. if (!version_entry) {
  3230. dev_dbg(component->dev, "%s: failed to create wcd9378 version entry\n",
  3231. __func__);
  3232. snd_info_free_entry(priv->entry);
  3233. return -ENOMEM;
  3234. }
  3235. version_entry->private_data = priv;
  3236. version_entry->size = WCD9378_VERSION_ENTRY_SIZE;
  3237. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3238. version_entry->c.ops = &wcd9378_info_ops;
  3239. if (snd_info_register(version_entry) < 0) {
  3240. snd_info_free_entry(version_entry);
  3241. snd_info_free_entry(priv->entry);
  3242. return -ENOMEM;
  3243. }
  3244. priv->version_entry = version_entry;
  3245. return 0;
  3246. }
  3247. EXPORT_SYMBOL_GPL(wcd9378_info_create_codec_entry);
  3248. static void wcd9378_class_load(struct snd_soc_component *component)
  3249. {
  3250. /*SMP AMP CLASS LOADING*/
  3251. snd_soc_component_update_bits(component, WCD9378_FUNC_ACT,
  3252. WCD9378_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3253. usleep_range(20000, 20010);
  3254. snd_soc_component_update_bits(component, WCD9378_SMP_AMP_FUNC_STAT,
  3255. WCD9378_SMP_AMP_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3256. /*SMP JACK CLASS LOADING*/
  3257. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_ACT,
  3258. WCD9378_SMP_JACK_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3259. usleep_range(30000, 30010);
  3260. snd_soc_component_update_bits(component, WCD9378_CMT_GRP_MASK,
  3261. WCD9378_CMT_GRP_MASK_CMT_GRP_MASK_MASK, 0x02);
  3262. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_STAT,
  3263. WCD9378_SMP_JACK_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3264. /*SMP MIC0 CLASS LOADING*/
  3265. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_ACT,
  3266. WCD9378_SMP_MIC_CTRL0_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3267. usleep_range(5000, 5010);
  3268. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_STAT,
  3269. WCD9378_SMP_MIC_CTRL0_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3270. /*SMP MIC1 CLASS LOADING*/
  3271. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_ACT,
  3272. WCD9378_SMP_MIC_CTRL1_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3273. usleep_range(5000, 5010);
  3274. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_STAT,
  3275. WCD9378_SMP_MIC_CTRL1_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3276. /*SMP MIC2 CLASS LOADING*/
  3277. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_ACT,
  3278. WCD9378_SMP_MIC_CTRL2_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3279. usleep_range(5000, 5010);
  3280. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_STAT,
  3281. WCD9378_SMP_MIC_CTRL2_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3282. }
  3283. static void wcd9378_micb_value_convert(struct snd_soc_component *component)
  3284. {
  3285. struct wcd9378_priv *wcd9378 =
  3286. snd_soc_component_get_drvdata(component);
  3287. struct wcd9378_pdata *pdata =
  3288. dev_get_platdata(wcd9378->dev);
  3289. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  3290. mb->micb1_usage_val = wcd9378_micb_usage_value_convert(component,
  3291. mb->micb1_mv, MIC_BIAS_1);
  3292. mb->micb2_usage_val = wcd9378_micb_usage_value_convert(component,
  3293. mb->micb2_mv, MIC_BIAS_2);
  3294. mb->micb3_usage_val = wcd9378_micb_usage_value_convert(component,
  3295. mb->micb3_mv, MIC_BIAS_3);
  3296. pr_debug("%s: micb1_usage: 0x%x, micb2_usage: 0x%x, micb3_usage: 0x%x\n", __func__,
  3297. mb->micb1_usage_val, mb->micb2_usage_val, mb->micb3_usage_val);
  3298. }
  3299. static int wcd9378_wcd_mode_check(struct snd_soc_component *component)
  3300. {
  3301. struct wcd9378_priv *wcd9378 =
  3302. snd_soc_component_get_drvdata(component);
  3303. if (snd_soc_component_read(component,
  3304. WCD9378_EFUSE_REG_29)
  3305. & WCD9378_EFUSE_REG_29_PLATFORM_BLOWN_MASK) {
  3306. if (((snd_soc_component_read(component,
  3307. WCD9378_EFUSE_REG_29) &
  3308. WCD9378_EFUSE_REG_29_PLATFORM_MASK) >> 1) == wcd9378->wcd_mode)
  3309. return true;
  3310. else
  3311. return false;
  3312. } else {
  3313. if ((snd_soc_component_read(component, WCD9378_PLATFORM_CTL)
  3314. & WCD9378_PLATFORM_CTL_MODE_MASK) == wcd9378->wcd_mode)
  3315. return true;
  3316. else
  3317. return false;
  3318. }
  3319. return 0;
  3320. }
  3321. static int wcd9378_soc_codec_probe(struct snd_soc_component *component)
  3322. {
  3323. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3324. struct snd_soc_dapm_context *dapm =
  3325. snd_soc_component_get_dapm(component);
  3326. int ret = -EINVAL;
  3327. wcd9378 = snd_soc_component_get_drvdata(component);
  3328. if (!wcd9378)
  3329. return -EINVAL;
  3330. wcd9378->component = component;
  3331. snd_soc_component_init_regmap(component, wcd9378->regmap);
  3332. devm_regmap_qti_debugfs_register(&wcd9378->tx_swr_dev->dev, wcd9378->regmap);
  3333. ret = wcd9378_wcd_mode_check(component);
  3334. if (!ret) {
  3335. dev_err(component->dev, "wcd mode check failed\n");
  3336. ret = -EINVAL;
  3337. goto exit;
  3338. }
  3339. ret = wcd9378_mbhc_init(&wcd9378->mbhc, component);
  3340. if (ret) {
  3341. pr_err("%s: mbhc initialization failed\n", __func__);
  3342. ret = -EINVAL;
  3343. goto exit;
  3344. }
  3345. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3346. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3347. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3348. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3349. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3350. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3351. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3352. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3353. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3354. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3355. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3356. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  3357. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  3358. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  3359. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3360. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3361. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3362. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3363. snd_soc_dapm_sync(dapm);
  3364. wcd_cls_h_init(&wcd9378->clsh_info);
  3365. wcd9378_init_reg(component);
  3366. wcd9378_micb_value_convert(component);
  3367. wcd9378->version = WCD9378_VERSION_1_0;
  3368. /* Register event notifier */
  3369. wcd9378->nblock.notifier_call = wcd9378_event_notify;
  3370. if (wcd9378->register_notifier) {
  3371. ret = wcd9378->register_notifier(wcd9378->handle,
  3372. &wcd9378->nblock,
  3373. true);
  3374. if (ret) {
  3375. dev_err(component->dev,
  3376. "%s: Failed to register notifier %d\n",
  3377. __func__, ret);
  3378. return ret;
  3379. }
  3380. }
  3381. exit:
  3382. return ret;
  3383. }
  3384. static void wcd9378_soc_codec_remove(struct snd_soc_component *component)
  3385. {
  3386. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3387. if (!wcd9378) {
  3388. dev_err(component->dev, "%s: wcd9378 is already NULL\n",
  3389. __func__);
  3390. return;
  3391. }
  3392. if (wcd9378->register_notifier)
  3393. wcd9378->register_notifier(wcd9378->handle,
  3394. &wcd9378->nblock,
  3395. false);
  3396. }
  3397. static int wcd9378_soc_codec_suspend(struct snd_soc_component *component)
  3398. {
  3399. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3400. if (!wcd9378)
  3401. return 0;
  3402. wcd9378->dapm_bias_off = true;
  3403. return 0;
  3404. }
  3405. static int wcd9378_soc_codec_resume(struct snd_soc_component *component)
  3406. {
  3407. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3408. if (!wcd9378)
  3409. return 0;
  3410. wcd9378->dapm_bias_off = false;
  3411. return 0;
  3412. }
  3413. static const struct snd_soc_component_driver soc_codec_dev_wcd9378 = {
  3414. .name = WCD9378_DRV_NAME,
  3415. .probe = wcd9378_soc_codec_probe,
  3416. .remove = wcd9378_soc_codec_remove,
  3417. .controls = wcd9378_snd_controls,
  3418. .num_controls = ARRAY_SIZE(wcd9378_snd_controls),
  3419. .dapm_widgets = wcd9378_dapm_widgets,
  3420. .num_dapm_widgets = ARRAY_SIZE(wcd9378_dapm_widgets),
  3421. .dapm_routes = wcd9378_audio_map,
  3422. .num_dapm_routes = ARRAY_SIZE(wcd9378_audio_map),
  3423. .suspend = wcd9378_soc_codec_suspend,
  3424. .resume = wcd9378_soc_codec_resume,
  3425. };
  3426. static int wcd9378_reset(struct device *dev)
  3427. {
  3428. struct wcd9378_priv *wcd9378 = NULL;
  3429. int rc = 0;
  3430. int value = 0;
  3431. if (!dev)
  3432. return -ENODEV;
  3433. wcd9378 = dev_get_drvdata(dev);
  3434. if (!wcd9378)
  3435. return -EINVAL;
  3436. if (!wcd9378->rst_np) {
  3437. dev_err(dev, "%s: reset gpio device node not specified\n",
  3438. __func__);
  3439. return -EINVAL;
  3440. }
  3441. value = msm_cdc_pinctrl_get_state(wcd9378->rst_np);
  3442. if (value > 0)
  3443. return 0;
  3444. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3445. if (rc) {
  3446. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3447. __func__);
  3448. return -EPROBE_DEFER;
  3449. }
  3450. /* 20us sleep required after pulling the reset gpio to LOW */
  3451. usleep_range(20, 30);
  3452. rc = msm_cdc_pinctrl_select_active_state(wcd9378->rst_np);
  3453. if (rc) {
  3454. dev_err(dev, "%s: wcd active state request fail!\n",
  3455. __func__);
  3456. return -EPROBE_DEFER;
  3457. }
  3458. /* 20us sleep required after pulling the reset gpio to HIGH */
  3459. usleep_range(20, 30);
  3460. return rc;
  3461. }
  3462. static int wcd9378_read_of_property_u32(struct device *dev, const char *name,
  3463. u32 *val)
  3464. {
  3465. int rc = 0;
  3466. rc = of_property_read_u32(dev->of_node, name, val);
  3467. if (rc)
  3468. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3469. __func__, name, dev->of_node->full_name);
  3470. return rc;
  3471. }
  3472. static void wcd9378_dt_parse_micbias_info(struct device *dev,
  3473. struct wcd9378_micbias_setting *mb)
  3474. {
  3475. u32 prop_val = 0;
  3476. int rc = 0;
  3477. /* MB1 */
  3478. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3479. NULL)) {
  3480. rc = wcd9378_read_of_property_u32(dev,
  3481. "qcom,cdc-micbias1-mv",
  3482. &prop_val);
  3483. if (!rc)
  3484. mb->micb1_mv = prop_val;
  3485. } else {
  3486. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3487. __func__);
  3488. }
  3489. /* MB2 */
  3490. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3491. NULL)) {
  3492. rc = wcd9378_read_of_property_u32(dev,
  3493. "qcom,cdc-micbias2-mv",
  3494. &prop_val);
  3495. if (!rc)
  3496. mb->micb2_mv = prop_val;
  3497. } else {
  3498. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3499. __func__);
  3500. }
  3501. /* MB3 */
  3502. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3503. NULL)) {
  3504. rc = wcd9378_read_of_property_u32(dev,
  3505. "qcom,cdc-micbias3-mv",
  3506. &prop_val);
  3507. if (!rc)
  3508. mb->micb3_mv = prop_val;
  3509. } else {
  3510. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3511. __func__);
  3512. }
  3513. }
  3514. static int wcd9378_reset_low(struct device *dev)
  3515. {
  3516. struct wcd9378_priv *wcd9378 = NULL;
  3517. int rc = 0;
  3518. if (!dev)
  3519. return -ENODEV;
  3520. wcd9378 = dev_get_drvdata(dev);
  3521. if (!wcd9378)
  3522. return -EINVAL;
  3523. if (!wcd9378->rst_np) {
  3524. dev_err(dev, "%s: reset gpio device node not specified\n",
  3525. __func__);
  3526. return -EINVAL;
  3527. }
  3528. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3529. if (rc) {
  3530. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3531. __func__);
  3532. return rc;
  3533. }
  3534. /* 20us sleep required after pulling the reset gpio to LOW */
  3535. usleep_range(20, 30);
  3536. return rc;
  3537. }
  3538. struct wcd9378_pdata *wcd9378_populate_dt_data(struct device *dev)
  3539. {
  3540. struct wcd9378_pdata *pdata = NULL;
  3541. pdata = devm_kzalloc(dev, sizeof(struct wcd9378_pdata),
  3542. GFP_KERNEL);
  3543. if (!pdata)
  3544. return NULL;
  3545. pdata->rst_np = of_parse_phandle(dev->of_node,
  3546. "qcom,wcd-rst-gpio-node", 0);
  3547. if (!pdata->rst_np) {
  3548. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3549. __func__, "qcom,wcd-rst-gpio-node",
  3550. dev->of_node->full_name);
  3551. return NULL;
  3552. }
  3553. /* Parse power supplies */
  3554. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3555. &pdata->num_supplies);
  3556. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3557. dev_err(dev, "%s: no power supplies defined for codec\n",
  3558. __func__);
  3559. return NULL;
  3560. }
  3561. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3562. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3563. wcd9378_dt_parse_micbias_info(dev, &pdata->micbias);
  3564. return pdata;
  3565. }
  3566. static struct snd_soc_dai_driver wcd9378_dai[] = {
  3567. {
  3568. .name = "wcd9378_cdc",
  3569. .playback = {
  3570. .stream_name = "WCD9378_AIF Playback",
  3571. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3572. .formats = WCD9378_FORMATS,
  3573. .rate_max = 384000,
  3574. .rate_min = 8000,
  3575. .channels_min = 1,
  3576. .channels_max = 4,
  3577. },
  3578. .capture = {
  3579. .stream_name = "WCD9378_AIF Capture",
  3580. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3581. .formats = WCD9378_FORMATS,
  3582. .rate_max = 384000,
  3583. .rate_min = 8000,
  3584. .channels_min = 1,
  3585. .channels_max = 4,
  3586. },
  3587. },
  3588. };
  3589. static int wcd9378_bind(struct device *dev)
  3590. {
  3591. int ret = 0;
  3592. struct wcd9378_pdata *pdata = dev_get_platdata(dev);
  3593. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3594. /*
  3595. * Add 5msec delay to provide sufficient time for
  3596. * soundwire auto enumeration of slave devices as
  3597. * per HW requirement.
  3598. */
  3599. usleep_range(5000, 5010);
  3600. ret = component_bind_all(dev, wcd9378);
  3601. if (ret) {
  3602. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3603. __func__, ret);
  3604. return ret;
  3605. }
  3606. wcd9378->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3607. if (!wcd9378->rx_swr_dev) {
  3608. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3609. __func__);
  3610. ret = -ENODEV;
  3611. goto err;
  3612. }
  3613. wcd9378->rx_swr_dev->paging_support = true;
  3614. wcd9378->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3615. if (!wcd9378->tx_swr_dev) {
  3616. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3617. __func__);
  3618. ret = -ENODEV;
  3619. goto err;
  3620. }
  3621. wcd9378->tx_swr_dev->paging_support = true;
  3622. swr_init_port_params(wcd9378->tx_swr_dev, SWR_NUM_PORTS,
  3623. wcd9378->swr_tx_port_params);
  3624. wcd9378->regmap = devm_regmap_init_swr(wcd9378->tx_swr_dev,
  3625. &wcd9378_regmap_config);
  3626. if (!wcd9378->regmap) {
  3627. dev_err(dev, "%s: Regmap init failed\n",
  3628. __func__);
  3629. goto err;
  3630. }
  3631. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_1, 0xff);
  3632. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_2, 0x0b);
  3633. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_3, 0xff);
  3634. wcd9378_regmap_irq_chip.irq_drv_data = wcd9378;
  3635. wcd9378->irq_info.wcd_regmap_irq_chip = &wcd9378_regmap_irq_chip;
  3636. wcd9378->irq_info.codec_name = "WCD9378";
  3637. wcd9378->irq_info.regmap = wcd9378->regmap;
  3638. wcd9378->irq_info.dev = dev;
  3639. ret = wcd_irq_init(&wcd9378->irq_info, &wcd9378->virq);
  3640. if (ret) {
  3641. dev_err(wcd9378->dev, "%s: IRQ init failed: %d\n",
  3642. __func__, ret);
  3643. goto err;
  3644. }
  3645. dev_err(wcd9378->dev, "%s: wcd irq init done\n",
  3646. __func__);
  3647. wcd9378->tx_swr_dev->slave_irq = wcd9378->virq;
  3648. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd9378,
  3649. wcd9378_dai, ARRAY_SIZE(wcd9378_dai));
  3650. if (ret) {
  3651. dev_err(dev, "%s: Codec registration failed\n",
  3652. __func__);
  3653. goto err_irq;
  3654. }
  3655. wcd9378->dev_up = true;
  3656. return ret;
  3657. err_irq:
  3658. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3659. err:
  3660. component_unbind_all(dev, wcd9378);
  3661. return ret;
  3662. }
  3663. static void wcd9378_unbind(struct device *dev)
  3664. {
  3665. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3666. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3667. snd_soc_unregister_component(dev);
  3668. component_unbind_all(dev, wcd9378);
  3669. }
  3670. static const struct of_device_id wcd9378_dt_match[] = {
  3671. { .compatible = "qcom,wcd9378-codec", .data = "wcd9378"},
  3672. {}
  3673. };
  3674. static const struct component_master_ops wcd9378_comp_ops = {
  3675. .bind = wcd9378_bind,
  3676. .unbind = wcd9378_unbind,
  3677. };
  3678. static int wcd9378_compare_of(struct device *dev, void *data)
  3679. {
  3680. return dev->of_node == data;
  3681. }
  3682. static void wcd9378_release_of(struct device *dev, void *data)
  3683. {
  3684. of_node_put(data);
  3685. }
  3686. static int wcd9378_add_slave_components(struct device *dev,
  3687. struct component_match **matchptr)
  3688. {
  3689. struct device_node *np, *rx_node, *tx_node;
  3690. np = dev->of_node;
  3691. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3692. if (!rx_node) {
  3693. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3694. return -ENODEV;
  3695. }
  3696. of_node_get(rx_node);
  3697. component_match_add_release(dev, matchptr,
  3698. wcd9378_release_of,
  3699. wcd9378_compare_of,
  3700. rx_node);
  3701. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3702. if (!tx_node) {
  3703. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3704. return -ENODEV;
  3705. }
  3706. of_node_get(tx_node);
  3707. component_match_add_release(dev, matchptr,
  3708. wcd9378_release_of,
  3709. wcd9378_compare_of,
  3710. tx_node);
  3711. return 0;
  3712. }
  3713. static int wcd9378_probe(struct platform_device *pdev)
  3714. {
  3715. struct component_match *match = NULL;
  3716. struct wcd9378_priv *wcd9378 = NULL;
  3717. struct wcd9378_pdata *pdata = NULL;
  3718. struct wcd_ctrl_platform_data *plat_data = NULL;
  3719. struct device *dev = &pdev->dev;
  3720. int ret;
  3721. wcd9378 = devm_kzalloc(dev, sizeof(struct wcd9378_priv),
  3722. GFP_KERNEL);
  3723. if (!wcd9378)
  3724. return -ENOMEM;
  3725. dev_set_drvdata(dev, wcd9378);
  3726. wcd9378->dev = dev;
  3727. pdata = wcd9378_populate_dt_data(dev);
  3728. if (!pdata) {
  3729. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3730. return -EINVAL;
  3731. }
  3732. dev->platform_data = pdata;
  3733. wcd9378->rst_np = pdata->rst_np;
  3734. ret = msm_cdc_init_supplies(dev, &wcd9378->supplies,
  3735. pdata->regulator, pdata->num_supplies);
  3736. if (!wcd9378->supplies) {
  3737. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3738. __func__);
  3739. return ret;
  3740. }
  3741. plat_data = dev_get_platdata(dev->parent);
  3742. if (!plat_data) {
  3743. dev_err(dev, "%s: platform data from parent is NULL\n",
  3744. __func__);
  3745. return -EINVAL;
  3746. }
  3747. wcd9378->handle = (void *)plat_data->handle;
  3748. if (!wcd9378->handle) {
  3749. dev_err(dev, "%s: handle is NULL\n", __func__);
  3750. return -EINVAL;
  3751. }
  3752. wcd9378->update_wcd_event = plat_data->update_wcd_event;
  3753. if (!wcd9378->update_wcd_event) {
  3754. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3755. __func__);
  3756. return -EINVAL;
  3757. }
  3758. wcd9378->register_notifier = plat_data->register_notifier;
  3759. if (!wcd9378->register_notifier) {
  3760. dev_err(dev, "%s: register_notifier api is null!\n",
  3761. __func__);
  3762. return -EINVAL;
  3763. }
  3764. ret = of_property_read_u32(dev->of_node, "qcom,wcd-mode",
  3765. &wcd9378->wcd_mode);
  3766. if (ret) {
  3767. dev_dbg(dev, "%s: wcd-mode read failed, use mobile mode\n",
  3768. __func__);
  3769. wcd9378->wcd_mode = WCD9378_MOBILE_MODE;
  3770. }
  3771. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd9378->supplies,
  3772. pdata->regulator,
  3773. pdata->num_supplies);
  3774. if (ret) {
  3775. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3776. __func__);
  3777. return ret;
  3778. }
  3779. ret = wcd9378_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3780. CODEC_RX);
  3781. ret |= wcd9378_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3782. CODEC_TX);
  3783. if (ret) {
  3784. dev_err(dev, "Failed to read port mapping\n");
  3785. goto err;
  3786. }
  3787. ret = wcd9378_parse_port_params(dev, "qcom,swr-tx-port-params",
  3788. CODEC_TX);
  3789. if (ret) {
  3790. dev_err(dev, "Failed to read port params\n");
  3791. goto err;
  3792. }
  3793. mutex_init(&wcd9378->wakeup_lock);
  3794. mutex_init(&wcd9378->micb_lock);
  3795. mutex_init(&wcd9378->sys_usage_lock);
  3796. ret = wcd9378_add_slave_components(dev, &match);
  3797. if (ret)
  3798. goto err_lock_init;
  3799. ret = wcd9378_reset(dev);
  3800. if (ret == -EPROBE_DEFER) {
  3801. dev_err(dev, "%s: wcd reset failed!\n", __func__);
  3802. goto err_lock_init;
  3803. }
  3804. wcd9378->wakeup = wcd9378_wakeup;
  3805. return component_master_add_with_match(dev,
  3806. &wcd9378_comp_ops, match);
  3807. err_lock_init:
  3808. mutex_destroy(&wcd9378->micb_lock);
  3809. mutex_destroy(&wcd9378->wakeup_lock);
  3810. mutex_destroy(&wcd9378->sys_usage_lock);
  3811. err:
  3812. return ret;
  3813. }
  3814. static int wcd9378_remove(struct platform_device *pdev)
  3815. {
  3816. struct wcd9378_priv *wcd9378 = NULL;
  3817. wcd9378 = platform_get_drvdata(pdev);
  3818. component_master_del(&pdev->dev, &wcd9378_comp_ops);
  3819. mutex_destroy(&wcd9378->micb_lock);
  3820. mutex_destroy(&wcd9378->wakeup_lock);
  3821. mutex_destroy(&wcd9378->sys_usage_lock);
  3822. dev_set_drvdata(&pdev->dev, NULL);
  3823. return 0;
  3824. }
  3825. #ifdef CONFIG_PM_SLEEP
  3826. static int wcd9378_suspend(struct device *dev)
  3827. {
  3828. struct wcd9378_priv *wcd9378 = NULL;
  3829. int ret = 0;
  3830. struct wcd9378_pdata *pdata = NULL;
  3831. if (!dev)
  3832. return -ENODEV;
  3833. wcd9378 = dev_get_drvdata(dev);
  3834. if (!wcd9378)
  3835. return -EINVAL;
  3836. pdata = dev_get_platdata(wcd9378->dev);
  3837. if (!pdata) {
  3838. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3839. return -EINVAL;
  3840. }
  3841. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  3842. ret = msm_cdc_disable_ondemand_supply(wcd9378->dev,
  3843. wcd9378->supplies,
  3844. pdata->regulator,
  3845. pdata->num_supplies,
  3846. "cdc-vdd-buck");
  3847. if (ret == -EINVAL) {
  3848. dev_err(dev, "%s: vdd buck is not disabled\n",
  3849. __func__);
  3850. return 0;
  3851. }
  3852. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  3853. }
  3854. if (wcd9378->dapm_bias_off) {
  3855. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3856. wcd9378->supplies,
  3857. pdata->regulator,
  3858. pdata->num_supplies,
  3859. true);
  3860. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3861. }
  3862. return 0;
  3863. }
  3864. static int wcd9378_resume(struct device *dev)
  3865. {
  3866. struct wcd9378_priv *wcd9378 = NULL;
  3867. struct wcd9378_pdata *pdata = NULL;
  3868. if (!dev)
  3869. return -ENODEV;
  3870. wcd9378 = dev_get_drvdata(dev);
  3871. if (!wcd9378)
  3872. return -EINVAL;
  3873. pdata = dev_get_platdata(wcd9378->dev);
  3874. if (!pdata) {
  3875. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3876. return -EINVAL;
  3877. }
  3878. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask)) {
  3879. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3880. wcd9378->supplies,
  3881. pdata->regulator,
  3882. pdata->num_supplies,
  3883. false);
  3884. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3885. }
  3886. return 0;
  3887. }
  3888. static const struct dev_pm_ops wcd9378_dev_pm_ops = {
  3889. .suspend_late = wcd9378_suspend,
  3890. .resume_early = wcd9378_resume,
  3891. };
  3892. #endif
  3893. static struct platform_driver wcd9378_codec_driver = {
  3894. .probe = wcd9378_probe,
  3895. .remove = wcd9378_remove,
  3896. .driver = {
  3897. .name = "wcd9378_codec",
  3898. .of_match_table = of_match_ptr(wcd9378_dt_match),
  3899. #ifdef CONFIG_PM_SLEEP
  3900. .pm = &wcd9378_dev_pm_ops,
  3901. #endif
  3902. .suppress_bind_attrs = true,
  3903. },
  3904. };
  3905. module_platform_driver(wcd9378_codec_driver);
  3906. MODULE_DESCRIPTION("WCD9378 Codec driver");
  3907. MODULE_LICENSE("GPL");