sde_plane.c 134 KB

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  1. /*
  2. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/debugfs.h>
  20. #include <linux/dma-buf.h>
  21. #include <drm/sde_drm.h>
  22. #include <drm/msm_drm_pp.h>
  23. #include "msm_prop.h"
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include "sde_fence.h"
  27. #include "sde_formats.h"
  28. #include "sde_hw_sspp.h"
  29. #include "sde_hw_catalog_format.h"
  30. #include "sde_trace.h"
  31. #include "sde_crtc.h"
  32. #include "sde_vbif.h"
  33. #include "sde_plane.h"
  34. #include "sde_color_processing.h"
  35. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  36. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  37. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  40. #define PHASE_STEP_SHIFT 21
  41. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  42. #define PHASE_RESIDUAL 15
  43. #define SHARP_STRENGTH_DEFAULT 32
  44. #define SHARP_EDGE_THR_DEFAULT 112
  45. #define SHARP_SMOOTH_THR_DEFAULT 8
  46. #define SHARP_NOISE_THR_DEFAULT 2
  47. #define SDE_NAME_SIZE 12
  48. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  49. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  50. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  51. /* multirect rect index */
  52. enum {
  53. R0,
  54. R1,
  55. R_MAX
  56. };
  57. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  58. /**
  59. * enum sde_plane_qos - Different qos configurations for each pipe
  60. *
  61. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  62. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  63. * this configuration is mutually exclusive from VBLANK_CTRL.
  64. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  65. */
  66. enum sde_plane_qos {
  67. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  68. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  69. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  70. };
  71. /*
  72. * struct sde_plane - local sde plane structure
  73. * @aspace: address space pointer
  74. * @csc_cfg: Decoded user configuration for csc
  75. * @csc_usr_ptr: Points to csc_cfg if valid user config available
  76. * @csc_ptr: Points to sde_csc_cfg structure to use for current
  77. * @mplane_list: List of multirect planes of the same pipe
  78. * @catalog: Points to sde catalog structure
  79. * @revalidate: force revalidation of all the plane properties
  80. * @xin_halt_forced_clk: whether or not clocks were forced on for xin halt
  81. * @blob_rot_caps: Pointer to rotator capability blob
  82. */
  83. struct sde_plane {
  84. struct drm_plane base;
  85. struct mutex lock;
  86. enum sde_sspp pipe;
  87. uint64_t features; /* capabilities from catalog */
  88. uint32_t perf_features; /* perf capabilities from catalog */
  89. uint32_t nformats;
  90. uint32_t formats[64];
  91. struct sde_hw_pipe *pipe_hw;
  92. struct sde_hw_pipe_cfg pipe_cfg;
  93. struct sde_hw_sharp_cfg sharp_cfg;
  94. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  95. uint32_t color_fill;
  96. bool is_error;
  97. bool is_rt_pipe;
  98. bool is_virtual;
  99. struct list_head mplane_list;
  100. struct sde_mdss_cfg *catalog;
  101. bool revalidate;
  102. bool xin_halt_forced_clk;
  103. struct sde_csc_cfg csc_cfg;
  104. struct sde_csc_cfg *csc_usr_ptr;
  105. struct sde_csc_cfg *csc_ptr;
  106. const struct sde_sspp_sub_blks *pipe_sblk;
  107. char pipe_name[SDE_NAME_SIZE];
  108. struct msm_property_info property_info;
  109. struct msm_property_data property_data[PLANE_PROP_COUNT];
  110. struct drm_property_blob *blob_info;
  111. struct drm_property_blob *blob_rot_caps;
  112. /* debugfs related stuff */
  113. struct dentry *debugfs_root;
  114. bool debugfs_default_scale;
  115. };
  116. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  117. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  118. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  119. {
  120. struct msm_drm_private *priv;
  121. if (!plane || !plane->dev)
  122. return NULL;
  123. priv = plane->dev->dev_private;
  124. if (!priv)
  125. return NULL;
  126. return to_sde_kms(priv->kms);
  127. }
  128. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  129. {
  130. struct drm_plane_state *pstate = NULL;
  131. struct drm_crtc *drm_crtc = NULL;
  132. struct sde_crtc *sde_crtc = NULL;
  133. struct sde_crtc_mixer *mixer = NULL;
  134. struct sde_hw_ctl *ctl = NULL;
  135. if (!plane) {
  136. DRM_ERROR("Invalid plane %pK\n", plane);
  137. return NULL;
  138. }
  139. pstate = plane->state;
  140. if (!pstate) {
  141. DRM_ERROR("Invalid plane state %pK\n", pstate);
  142. return NULL;
  143. }
  144. drm_crtc = pstate->crtc;
  145. if (!drm_crtc) {
  146. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  147. return NULL;
  148. }
  149. sde_crtc = to_sde_crtc(drm_crtc);
  150. if (!sde_crtc) {
  151. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  152. return NULL;
  153. }
  154. /* it will always return the first mixer and single CTL */
  155. mixer = sde_crtc->mixers;
  156. if (!mixer) {
  157. DRM_ERROR("invalid mixer %pK\n", mixer);
  158. return NULL;
  159. }
  160. ctl = mixer->hw_ctl;
  161. if (!mixer) {
  162. DRM_ERROR("invalid ctl %pK\n", ctl);
  163. return NULL;
  164. }
  165. return ctl;
  166. }
  167. static bool sde_plane_enabled(const struct drm_plane_state *state)
  168. {
  169. return state && state->fb && state->crtc;
  170. }
  171. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  172. {
  173. struct sde_plane *psde;
  174. if (!plane)
  175. return false;
  176. psde = to_sde_plane(plane);
  177. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  178. }
  179. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  180. enum sde_sspp_multirect_index rect_mode, bool enable)
  181. {
  182. struct sde_plane *psde;
  183. if (!plane)
  184. return;
  185. psde = to_sde_plane(plane);
  186. if (psde->pipe_hw->ops.set_src_split_order)
  187. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  188. rect_mode, enable);
  189. }
  190. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  191. {
  192. struct sde_plane *psde;
  193. struct sde_kms *sde_kms;
  194. struct msm_drm_private *priv;
  195. if (!plane || !plane->dev) {
  196. SDE_ERROR("invalid plane %d\n");
  197. return;
  198. }
  199. priv = plane->dev->dev_private;
  200. if (!priv || !priv->kms) {
  201. SDE_ERROR("invalid KMS reference\n");
  202. return;
  203. }
  204. sde_kms = to_sde_kms(priv->kms);
  205. psde = to_sde_plane(plane);
  206. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm);
  207. }
  208. void _sde_plane_set_qos_lut(struct drm_plane *plane,
  209. struct drm_crtc *crtc,
  210. struct drm_framebuffer *fb)
  211. {
  212. struct sde_plane *psde;
  213. const struct sde_format *fmt = NULL;
  214. u32 frame_rate, qos_count, fps_index = 0, lut_index, index;
  215. struct sde_perf_cfg *perf;
  216. struct sde_plane_state *pstate;
  217. if (!plane || !fb) {
  218. SDE_ERROR("invalid arguments\n");
  219. return;
  220. }
  221. psde = to_sde_plane(plane);
  222. pstate = to_sde_plane_state(plane->state);
  223. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  224. SDE_ERROR("invalid arguments\n");
  225. return;
  226. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  227. return;
  228. }
  229. frame_rate = drm_mode_vrefresh(&crtc->mode);
  230. perf = &psde->catalog->perf;
  231. qos_count = perf->qos_refresh_count;
  232. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  233. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  234. (fps_index == qos_count - 1))
  235. break;
  236. fps_index++;
  237. }
  238. if (!psde->is_rt_pipe) {
  239. lut_index = SDE_QOS_LUT_USAGE_NRT;
  240. } else {
  241. fmt = sde_get_sde_format_ext(
  242. fb->format->format,
  243. fb->modifier);
  244. if (fmt && SDE_FORMAT_IS_LINEAR(fmt) &&
  245. pstate->scaler3_cfg.enable)
  246. lut_index = SDE_QOS_LUT_USAGE_LINEAR_QSEED;
  247. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  248. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  249. else if (pstate->scaler3_cfg.enable)
  250. lut_index = SDE_QOS_LUT_USAGE_MACROTILE_QSEED;
  251. else
  252. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  253. }
  254. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  255. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[index];
  256. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[index];
  257. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[index];
  258. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
  259. (fmt) ? fmt->base.pixel_format : 0,
  260. (fmt) ? fmt->fetch_mode : 0,
  261. psde->pipe_qos_cfg.danger_lut,
  262. psde->pipe_qos_cfg.safe_lut,
  263. psde->pipe_qos_cfg.creq_lut);
  264. SDE_DEBUG(
  265. "plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  266. plane->base.id,
  267. psde->pipe - SSPP_VIG0,
  268. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  269. fmt ? fmt->fetch_mode : -1,
  270. psde->pipe_qos_cfg.danger_lut,
  271. psde->pipe_qos_cfg.safe_lut,
  272. psde->pipe_qos_cfg.creq_lut);
  273. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  274. }
  275. /**
  276. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  277. * @plane: Pointer to drm plane
  278. * @enable: true to enable QoS control
  279. * @flags: QoS control mode (enum sde_plane_qos)
  280. */
  281. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  282. bool enable, u32 flags)
  283. {
  284. struct sde_plane *psde;
  285. if (!plane) {
  286. SDE_ERROR("invalid arguments\n");
  287. return;
  288. }
  289. psde = to_sde_plane(plane);
  290. if (!psde->pipe_hw || !psde->pipe_sblk) {
  291. SDE_ERROR("invalid arguments\n");
  292. return;
  293. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  294. return;
  295. }
  296. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  297. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  298. psde->pipe_qos_cfg.danger_vblank =
  299. psde->pipe_sblk->danger_vblank;
  300. psde->pipe_qos_cfg.vblank_en = enable;
  301. }
  302. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  303. /* this feature overrules previous VBLANK_CTRL */
  304. psde->pipe_qos_cfg.vblank_en = false;
  305. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  306. }
  307. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  308. psde->pipe_qos_cfg.danger_safe_en = enable;
  309. if (!psde->is_rt_pipe) {
  310. psde->pipe_qos_cfg.vblank_en = false;
  311. psde->pipe_qos_cfg.danger_safe_en = false;
  312. }
  313. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  314. plane->base.id,
  315. psde->pipe - SSPP_VIG0,
  316. psde->pipe_qos_cfg.danger_safe_en,
  317. psde->pipe_qos_cfg.vblank_en,
  318. psde->pipe_qos_cfg.creq_vblank,
  319. psde->pipe_qos_cfg.danger_vblank,
  320. psde->is_rt_pipe);
  321. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  322. &psde->pipe_qos_cfg);
  323. }
  324. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  325. {
  326. struct sde_plane *psde;
  327. if (!plane)
  328. return;
  329. psde = to_sde_plane(plane);
  330. psde->revalidate = enable;
  331. }
  332. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  333. {
  334. struct sde_plane *psde;
  335. int rc;
  336. if (!plane) {
  337. SDE_ERROR("invalid arguments\n");
  338. return -EINVAL;
  339. }
  340. psde = to_sde_plane(plane);
  341. if (!psde->is_rt_pipe)
  342. goto end;
  343. rc = pm_runtime_get_sync(plane->dev->dev);
  344. if (rc < 0) {
  345. SDE_ERROR("failed to enable power resource %d\n", rc);
  346. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  347. return rc;
  348. }
  349. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  350. pm_runtime_put_sync(plane->dev->dev);
  351. end:
  352. return 0;
  353. }
  354. /**
  355. * _sde_plane_set_ot_limit - set OT limit for the given plane
  356. * @plane: Pointer to drm plane
  357. * @crtc: Pointer to drm crtc
  358. */
  359. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  360. struct drm_crtc *crtc)
  361. {
  362. struct sde_plane *psde;
  363. struct sde_vbif_set_ot_params ot_params;
  364. struct msm_drm_private *priv;
  365. struct sde_kms *sde_kms;
  366. if (!plane || !plane->dev || !crtc) {
  367. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  368. !plane, !crtc);
  369. return;
  370. }
  371. priv = plane->dev->dev_private;
  372. if (!priv || !priv->kms) {
  373. SDE_ERROR("invalid KMS reference\n");
  374. return;
  375. }
  376. sde_kms = to_sde_kms(priv->kms);
  377. psde = to_sde_plane(plane);
  378. if (!psde->pipe_hw) {
  379. SDE_ERROR("invalid pipe reference\n");
  380. return;
  381. }
  382. memset(&ot_params, 0, sizeof(ot_params));
  383. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  384. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  385. ot_params.width = psde->pipe_cfg.src_rect.w;
  386. ot_params.height = psde->pipe_cfg.src_rect.h;
  387. ot_params.is_wfd = !psde->is_rt_pipe;
  388. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  389. ot_params.vbif_idx = VBIF_RT;
  390. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  391. ot_params.rd = true;
  392. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  393. }
  394. /**
  395. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  396. * @plane: Pointer to drm plane
  397. */
  398. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  399. {
  400. struct sde_plane *psde;
  401. struct sde_vbif_set_qos_params qos_params;
  402. struct msm_drm_private *priv;
  403. struct sde_kms *sde_kms;
  404. if (!plane || !plane->dev) {
  405. SDE_ERROR("invalid arguments\n");
  406. return;
  407. }
  408. priv = plane->dev->dev_private;
  409. if (!priv || !priv->kms) {
  410. SDE_ERROR("invalid KMS reference\n");
  411. return;
  412. }
  413. sde_kms = to_sde_kms(priv->kms);
  414. psde = to_sde_plane(plane);
  415. if (!psde->pipe_hw) {
  416. SDE_ERROR("invalid pipe reference\n");
  417. return;
  418. }
  419. memset(&qos_params, 0, sizeof(qos_params));
  420. qos_params.vbif_idx = VBIF_RT;
  421. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  422. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  423. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  424. qos_params.client_type = psde->is_rt_pipe ?
  425. VBIF_RT_CLIENT : VBIF_NRT_CLIENT;
  426. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  427. plane->base.id, qos_params.num,
  428. qos_params.vbif_idx,
  429. qos_params.xin_id, qos_params.client_type,
  430. qos_params.clk_ctrl);
  431. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  432. }
  433. /**
  434. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  435. * @plane: Pointer to drm plane
  436. * @pstate: Pointer to sde plane state
  437. */
  438. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  439. struct sde_plane_state *pstate)
  440. {
  441. struct sde_plane *psde;
  442. struct sde_hw_pipe_ts_cfg cfg;
  443. struct msm_drm_private *priv;
  444. struct sde_kms *sde_kms;
  445. if (!plane || !plane->dev) {
  446. SDE_ERROR("invalid arguments");
  447. return;
  448. }
  449. priv = plane->dev->dev_private;
  450. if (!priv || !priv->kms) {
  451. SDE_ERROR("invalid KMS reference\n");
  452. return;
  453. }
  454. sde_kms = to_sde_kms(priv->kms);
  455. psde = to_sde_plane(plane);
  456. if (!psde->pipe_hw) {
  457. SDE_ERROR("invalid pipe reference\n");
  458. return;
  459. }
  460. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  461. return;
  462. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  463. memset(&cfg, 0, sizeof(cfg));
  464. cfg.size = sde_plane_get_property(pstate,
  465. PLANE_PROP_PREFILL_SIZE);
  466. cfg.time = sde_plane_get_property(pstate,
  467. PLANE_PROP_PREFILL_TIME);
  468. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  469. plane->base.id, cfg.size, cfg.time);
  470. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  471. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  472. pstate->multirect_index);
  473. }
  474. /* helper to update a state's input fence pointer from the property */
  475. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  476. struct sde_plane_state *pstate, uint64_t fd)
  477. {
  478. if (!psde || !pstate) {
  479. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  480. !psde, !pstate);
  481. return;
  482. }
  483. /* clear previous reference */
  484. if (pstate->input_fence)
  485. sde_sync_put(pstate->input_fence);
  486. /* get fence pointer for later */
  487. if (fd == 0)
  488. pstate->input_fence = NULL;
  489. else
  490. pstate->input_fence = sde_sync_get(fd);
  491. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  492. }
  493. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  494. {
  495. struct sde_plane *psde;
  496. struct sde_plane_state *pstate;
  497. uint32_t prefix;
  498. void *input_fence;
  499. int ret = -EINVAL;
  500. signed long rc;
  501. if (!plane) {
  502. SDE_ERROR("invalid plane\n");
  503. } else if (!plane->state) {
  504. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  505. } else {
  506. psde = to_sde_plane(plane);
  507. pstate = to_sde_plane_state(plane->state);
  508. input_fence = pstate->input_fence;
  509. if (input_fence) {
  510. prefix = sde_sync_get_name_prefix(input_fence);
  511. rc = sde_sync_wait(input_fence, wait_ms);
  512. switch (rc) {
  513. case 0:
  514. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %d\n",
  515. wait_ms, prefix, sde_plane_get_property(pstate,
  516. PLANE_PROP_INPUT_FENCE));
  517. psde->is_error = true;
  518. sde_kms_timeline_status(plane->dev);
  519. ret = -ETIMEDOUT;
  520. break;
  521. case -ERESTARTSYS:
  522. SDE_ERROR_PLANE(psde,
  523. "%ums wait interrupted on %08X\n",
  524. wait_ms, prefix);
  525. psde->is_error = true;
  526. ret = -ERESTARTSYS;
  527. break;
  528. case -EINVAL:
  529. SDE_ERROR_PLANE(psde,
  530. "invalid fence param for %08X\n",
  531. prefix);
  532. psde->is_error = true;
  533. ret = -EINVAL;
  534. break;
  535. default:
  536. SDE_DEBUG_PLANE(psde, "signaled\n");
  537. ret = 0;
  538. break;
  539. }
  540. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  541. } else {
  542. ret = 0;
  543. }
  544. }
  545. return ret;
  546. }
  547. /**
  548. * _sde_plane_get_aspace: gets the address space based on the
  549. * fb_translation mode property
  550. */
  551. static int _sde_plane_get_aspace(
  552. struct sde_plane *psde,
  553. struct sde_plane_state *pstate,
  554. struct msm_gem_address_space **aspace)
  555. {
  556. struct sde_kms *kms;
  557. int mode;
  558. if (!psde || !pstate || !aspace) {
  559. SDE_ERROR("invalid parameters\n");
  560. return -EINVAL;
  561. }
  562. kms = _sde_plane_get_kms(&psde->base);
  563. if (!kms) {
  564. SDE_ERROR("invalid kms\n");
  565. return -EINVAL;
  566. }
  567. mode = sde_plane_get_property(pstate,
  568. PLANE_PROP_FB_TRANSLATION_MODE);
  569. switch (mode) {
  570. case SDE_DRM_FB_NON_SEC:
  571. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  572. if (!aspace)
  573. return -EINVAL;
  574. break;
  575. case SDE_DRM_FB_SEC:
  576. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  577. if (!aspace)
  578. return -EINVAL;
  579. break;
  580. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  581. case SDE_DRM_FB_SEC_DIR_TRANS:
  582. *aspace = NULL;
  583. break;
  584. default:
  585. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  586. return -EFAULT;
  587. }
  588. return 0;
  589. }
  590. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  591. struct sde_plane_state *pstate,
  592. struct sde_hw_pipe_cfg *pipe_cfg,
  593. struct drm_framebuffer *fb)
  594. {
  595. struct sde_plane *psde;
  596. struct msm_gem_address_space *aspace = NULL;
  597. int ret, mode;
  598. bool secure = false;
  599. if (!plane || !pstate || !pipe_cfg || !fb) {
  600. SDE_ERROR(
  601. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  602. !plane, !pstate, !pipe_cfg, !fb);
  603. return;
  604. }
  605. psde = to_sde_plane(plane);
  606. if (!psde->pipe_hw) {
  607. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  608. return;
  609. }
  610. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  611. if (ret) {
  612. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  613. return;
  614. }
  615. /*
  616. * framebuffer prepare is deferred for prepare_fb calls that
  617. * happen during the transition from secure to non-secure.
  618. * Handle the prepare at this point for such cases. This can be
  619. * expected for one or two frames during the transition.
  620. */
  621. if (aspace && pstate->defer_prepare_fb) {
  622. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  623. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  624. if (ret) {
  625. SDE_ERROR_PLANE(psde,
  626. "failed to prepare framebuffer %d\n", ret);
  627. return;
  628. }
  629. pstate->defer_prepare_fb = false;
  630. }
  631. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  632. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  633. secure = true;
  634. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  635. if (ret == -EAGAIN)
  636. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  637. else if (ret) {
  638. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  639. /*
  640. * Force solid fill color on error. This is to prevent
  641. * smmu faults during secure session transition.
  642. */
  643. psde->is_error = true;
  644. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  645. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  646. pipe_cfg->layout.width,
  647. pipe_cfg->layout.height,
  648. pipe_cfg->layout.plane_addr[0],
  649. pipe_cfg->layout.plane_size[0],
  650. pipe_cfg->layout.plane_addr[1],
  651. pipe_cfg->layout.plane_size[1],
  652. pipe_cfg->layout.plane_addr[2],
  653. pipe_cfg->layout.plane_size[2],
  654. pipe_cfg->layout.plane_addr[3],
  655. pipe_cfg->layout.plane_size[3],
  656. pstate->multirect_index,
  657. secure);
  658. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  659. pstate->multirect_index);
  660. }
  661. }
  662. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  663. struct sde_plane_state *pstate)
  664. {
  665. struct sde_hw_scaler3_cfg *cfg;
  666. int ret = 0;
  667. if (!psde || !pstate) {
  668. SDE_ERROR("invalid args\n");
  669. return -EINVAL;
  670. }
  671. cfg = &pstate->scaler3_cfg;
  672. cfg->dir_lut = msm_property_get_blob(
  673. &psde->property_info,
  674. &pstate->property_state, &cfg->dir_len,
  675. PLANE_PROP_SCALER_LUT_ED);
  676. cfg->cir_lut = msm_property_get_blob(
  677. &psde->property_info,
  678. &pstate->property_state, &cfg->cir_len,
  679. PLANE_PROP_SCALER_LUT_CIR);
  680. cfg->sep_lut = msm_property_get_blob(
  681. &psde->property_info,
  682. &pstate->property_state, &cfg->sep_len,
  683. PLANE_PROP_SCALER_LUT_SEP);
  684. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  685. ret = -ENODATA;
  686. return ret;
  687. }
  688. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  689. struct sde_plane_state *pstate)
  690. {
  691. struct sde_hw_scaler3_cfg *cfg;
  692. cfg = &pstate->scaler3_cfg;
  693. cfg->sep_lut = msm_property_get_blob(
  694. &psde->property_info,
  695. &pstate->property_state, &cfg->sep_len,
  696. PLANE_PROP_SCALER_LUT_SEP);
  697. return cfg->sep_lut ? 0 : -ENODATA;
  698. }
  699. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  700. struct sde_plane_state *pstate, const struct sde_format *fmt,
  701. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  702. {
  703. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  704. struct sde_hw_scaler3_cfg *scale_cfg;
  705. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  706. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  707. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  708. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  709. chroma_subsmpl_h, chroma_subsmpl_v);
  710. return;
  711. }
  712. scale_cfg = &pstate->scaler3_cfg;
  713. src_w = psde->pipe_cfg.src_rect.w;
  714. src_h = psde->pipe_cfg.src_rect.h;
  715. dst_w = psde->pipe_cfg.dst_rect.w;
  716. dst_h = psde->pipe_cfg.dst_rect.h;
  717. memset(scale_cfg, 0, sizeof(*scale_cfg));
  718. memset(&pstate->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  719. /*
  720. * For inline rotation cases, scaler config is post-rotation,
  721. * so swap the dimensions here. However, pixel extension will
  722. * need pre-rotation settings, this will be corrected below
  723. * when calculating pixel extension settings.
  724. */
  725. if (inline_rotation)
  726. swap(src_w, src_h);
  727. decimated = DECIMATED_DIMENSION(src_w,
  728. psde->pipe_cfg.horz_decimation);
  729. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  730. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  731. decimated = DECIMATED_DIMENSION(src_h,
  732. psde->pipe_cfg.vert_decimation);
  733. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  734. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  735. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  736. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  737. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  738. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  739. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  740. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  741. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  742. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  743. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  744. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  745. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  746. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  747. for (i = 0; i < SDE_MAX_PLANES; i++) {
  748. /*
  749. * For inline rotation cases with pre-downscaling enabled
  750. * set x pre-downscale value if required. Only x direction
  751. * is currently supported. Use src_h as values have been swapped
  752. * and x direction corresponds to height value.
  753. */
  754. src_h_pre_down = src_h;
  755. if (pre_down_supported && inline_rotation) {
  756. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  757. src_h_pre_down = src_h / 2;
  758. }
  759. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  760. psde->pipe_cfg.horz_decimation);
  761. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  762. psde->pipe_cfg.vert_decimation);
  763. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  764. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  765. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  766. }
  767. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  768. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  769. /* For pixel extension we need the pre-rotated orientation */
  770. if (inline_rotation) {
  771. pstate->pixel_ext.num_ext_pxls_top[i] =
  772. scale_cfg->src_width[i];
  773. pstate->pixel_ext.num_ext_pxls_left[i] =
  774. scale_cfg->src_height[i];
  775. } else {
  776. pstate->pixel_ext.num_ext_pxls_top[i] =
  777. scale_cfg->src_height[i];
  778. pstate->pixel_ext.num_ext_pxls_left[i] =
  779. scale_cfg->src_width[i];
  780. }
  781. }
  782. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  783. && (src_w == dst_w) && !inline_rotation) ||
  784. pstate->multirect_mode)
  785. return;
  786. SDE_DEBUG_PLANE(psde,
  787. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  788. src_w, src_h, dst_w, dst_h,
  789. chroma_subsmpl_v, chroma_subsmpl_h,
  790. fmt->base.pixel_format);
  791. scale_cfg->dst_width = dst_w;
  792. scale_cfg->dst_height = dst_h;
  793. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  794. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  795. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  796. scale_cfg->lut_flag = 0;
  797. scale_cfg->blend_cfg = 1;
  798. scale_cfg->enable = 1;
  799. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  800. }
  801. /**
  802. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  803. * @psde: Pointer to SDE plane object
  804. * @src: Source size
  805. * @dst: Destination size
  806. * @phase_steps: Pointer to output array for phase steps
  807. * @filter: Pointer to output array for filter type
  808. * @fmt: Pointer to format definition
  809. * @chroma_subsampling: Subsampling amount for chroma channel
  810. *
  811. * Returns: 0 on success
  812. */
  813. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  814. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  815. enum sde_hw_filter *filter, const struct sde_format *fmt,
  816. uint32_t chroma_subsampling)
  817. {
  818. if (!psde || !phase_steps || !filter || !fmt) {
  819. SDE_ERROR(
  820. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  821. !psde, !phase_steps, !filter, !fmt);
  822. return -EINVAL;
  823. }
  824. /* calculate phase steps, leave init phase as zero */
  825. phase_steps[SDE_SSPP_COMP_0] =
  826. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  827. phase_steps[SDE_SSPP_COMP_1_2] =
  828. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  829. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  830. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  831. /* calculate scaler config, if necessary */
  832. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  833. filter[SDE_SSPP_COMP_3] =
  834. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  835. SDE_SCALE_FILTER_PCMN;
  836. if (SDE_FORMAT_IS_YUV(fmt)) {
  837. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  838. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  839. } else {
  840. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  841. filter[SDE_SSPP_COMP_1_2] =
  842. SDE_SCALE_FILTER_NEAREST;
  843. }
  844. } else {
  845. /* disable scaler */
  846. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  847. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  848. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  849. }
  850. return 0;
  851. }
  852. /**
  853. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  854. * @psde: Pointer to SDE plane object
  855. * @src: Source size
  856. * @dst: Destination size
  857. * @decimated_src: Source size after decimation, if any
  858. * @phase_steps: Pointer to output array for phase steps
  859. * @out_src: Output array for pixel extension values
  860. * @out_edge1: Output array for pixel extension first edge
  861. * @out_edge2: Output array for pixel extension second edge
  862. * @filter: Pointer to array for filter type
  863. * @fmt: Pointer to format definition
  864. * @chroma_subsampling: Subsampling amount for chroma channel
  865. * @post_compare: Whether to chroma subsampled source size for comparisions
  866. */
  867. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  868. uint32_t src, uint32_t dst, uint32_t decimated_src,
  869. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  870. int *out_edge2, enum sde_hw_filter *filter,
  871. const struct sde_format *fmt, uint32_t chroma_subsampling,
  872. bool post_compare)
  873. {
  874. int64_t edge1, edge2, caf;
  875. uint32_t src_work;
  876. int i, tmp;
  877. if (psde && phase_steps && out_src && out_edge1 &&
  878. out_edge2 && filter && fmt) {
  879. /* handle CAF for YUV formats */
  880. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  881. caf = PHASE_STEP_UNIT_SCALE;
  882. else
  883. caf = 0;
  884. for (i = 0; i < SDE_MAX_PLANES; i++) {
  885. src_work = decimated_src;
  886. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  887. src_work /= chroma_subsampling;
  888. if (post_compare)
  889. src = src_work;
  890. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  891. /* unity */
  892. edge1 = 0;
  893. edge2 = 0;
  894. } else if (dst >= src) {
  895. /* upscale */
  896. edge1 = (1 << PHASE_RESIDUAL);
  897. edge1 -= caf;
  898. edge2 = (1 << PHASE_RESIDUAL);
  899. edge2 += (dst - 1) * *(phase_steps + i);
  900. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  901. edge2 += caf;
  902. edge2 = -(edge2);
  903. } else {
  904. /* downscale */
  905. edge1 = 0;
  906. edge2 = (dst - 1) * *(phase_steps + i);
  907. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  908. edge2 += *(phase_steps + i);
  909. edge2 = -(edge2);
  910. }
  911. /* only enable CAF for luma plane */
  912. caf = 0;
  913. /* populate output arrays */
  914. *(out_src + i) = src_work;
  915. /* edge updates taken from __pxl_extn_helper */
  916. if (edge1 >= 0) {
  917. tmp = (uint32_t)edge1;
  918. tmp >>= PHASE_STEP_SHIFT;
  919. *(out_edge1 + i) = -tmp;
  920. } else {
  921. tmp = (uint32_t)(-edge1);
  922. *(out_edge1 + i) =
  923. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  924. PHASE_STEP_SHIFT;
  925. }
  926. if (edge2 >= 0) {
  927. tmp = (uint32_t)edge2;
  928. tmp >>= PHASE_STEP_SHIFT;
  929. *(out_edge2 + i) = -tmp;
  930. } else {
  931. tmp = (uint32_t)(-edge2);
  932. *(out_edge2 + i) =
  933. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  934. PHASE_STEP_SHIFT;
  935. }
  936. }
  937. }
  938. }
  939. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  940. {
  941. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  942. {
  943. /* S15.16 format */
  944. 0x00012A00, 0x00000000, 0x00019880,
  945. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  946. 0x00012A00, 0x00020480, 0x00000000,
  947. },
  948. /* signed bias */
  949. { 0xfff0, 0xff80, 0xff80,},
  950. { 0x0, 0x0, 0x0,},
  951. /* unsigned clamp */
  952. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  953. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  954. };
  955. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  956. {
  957. /* S15.16 format */
  958. 0x00012A00, 0x00000000, 0x00019880,
  959. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  960. 0x00012A00, 0x00020480, 0x00000000,
  961. },
  962. /* signed bias */
  963. { 0xffc0, 0xfe00, 0xfe00,},
  964. { 0x0, 0x0, 0x0,},
  965. /* unsigned clamp */
  966. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  967. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  968. };
  969. if (!psde) {
  970. SDE_ERROR("invalid plane\n");
  971. return;
  972. }
  973. /* revert to kernel default if override not available */
  974. if (psde->csc_usr_ptr)
  975. psde->csc_ptr = psde->csc_usr_ptr;
  976. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  977. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  978. else
  979. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  980. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  981. psde->csc_ptr->csc_mv[0],
  982. psde->csc_ptr->csc_mv[1],
  983. psde->csc_ptr->csc_mv[2]);
  984. }
  985. static void sde_color_process_plane_setup(struct drm_plane *plane)
  986. {
  987. struct sde_plane *psde;
  988. struct sde_plane_state *pstate;
  989. uint32_t hue, saturation, value, contrast;
  990. struct drm_msm_memcol *memcol = NULL;
  991. struct drm_msm_3d_gamut *vig_gamut = NULL;
  992. struct drm_msm_igc_lut *igc = NULL;
  993. struct drm_msm_pgc_lut *gc = NULL;
  994. size_t memcol_sz = 0, size = 0;
  995. struct sde_hw_cp_cfg hw_cfg = {};
  996. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  997. bool fp16_igc, fp16_unmult;
  998. struct drm_msm_fp16_gc *fp16_gc = NULL;
  999. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1000. psde = to_sde_plane(plane);
  1001. pstate = to_sde_plane_state(plane->state);
  1002. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1003. if (psde->pipe_hw->ops.setup_pa_hue)
  1004. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1005. saturation = (uint32_t) sde_plane_get_property(pstate,
  1006. PLANE_PROP_SATURATION_ADJUST);
  1007. if (psde->pipe_hw->ops.setup_pa_sat)
  1008. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1009. value = (uint32_t) sde_plane_get_property(pstate,
  1010. PLANE_PROP_VALUE_ADJUST);
  1011. if (psde->pipe_hw->ops.setup_pa_val)
  1012. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1013. contrast = (uint32_t) sde_plane_get_property(pstate,
  1014. PLANE_PROP_CONTRAST_ADJUST);
  1015. if (psde->pipe_hw->ops.setup_pa_cont)
  1016. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1017. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1018. /* Skin memory color setup */
  1019. memcol = msm_property_get_blob(&psde->property_info,
  1020. &pstate->property_state,
  1021. &memcol_sz,
  1022. PLANE_PROP_SKIN_COLOR);
  1023. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1024. MEMCOLOR_SKIN, memcol);
  1025. /* Sky memory color setup */
  1026. memcol = msm_property_get_blob(&psde->property_info,
  1027. &pstate->property_state,
  1028. &memcol_sz,
  1029. PLANE_PROP_SKY_COLOR);
  1030. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1031. MEMCOLOR_SKY, memcol);
  1032. /* Foliage memory color setup */
  1033. memcol = msm_property_get_blob(&psde->property_info,
  1034. &pstate->property_state,
  1035. &memcol_sz,
  1036. PLANE_PROP_FOLIAGE_COLOR);
  1037. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1038. MEMCOLOR_FOLIAGE, memcol);
  1039. }
  1040. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1041. psde->pipe_hw->ops.setup_vig_gamut) {
  1042. vig_gamut = msm_property_get_blob(&psde->property_info,
  1043. &pstate->property_state,
  1044. &size,
  1045. PLANE_PROP_VIG_GAMUT);
  1046. hw_cfg.last_feature = 0;
  1047. hw_cfg.ctl = ctl;
  1048. hw_cfg.len = sizeof(struct drm_msm_3d_gamut);
  1049. hw_cfg.payload = vig_gamut;
  1050. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1051. }
  1052. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1053. psde->pipe_hw->ops.setup_vig_igc) {
  1054. igc = msm_property_get_blob(&psde->property_info,
  1055. &pstate->property_state,
  1056. &size,
  1057. PLANE_PROP_VIG_IGC);
  1058. hw_cfg.last_feature = 0;
  1059. hw_cfg.ctl = ctl;
  1060. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1061. hw_cfg.payload = igc;
  1062. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1063. }
  1064. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1065. psde->pipe_hw->ops.setup_dma_igc) {
  1066. igc = msm_property_get_blob(&psde->property_info,
  1067. &pstate->property_state,
  1068. &size,
  1069. PLANE_PROP_DMA_IGC);
  1070. hw_cfg.last_feature = 0;
  1071. hw_cfg.ctl = ctl;
  1072. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1073. hw_cfg.payload = igc;
  1074. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1075. pstate->multirect_index);
  1076. }
  1077. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1078. psde->pipe_hw->ops.setup_dma_gc) {
  1079. gc = msm_property_get_blob(&psde->property_info,
  1080. &pstate->property_state,
  1081. &size,
  1082. PLANE_PROP_DMA_GC);
  1083. hw_cfg.last_feature = 0;
  1084. hw_cfg.ctl = ctl;
  1085. hw_cfg.len = sizeof(struct drm_msm_pgc_lut);
  1086. hw_cfg.payload = gc;
  1087. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1088. pstate->multirect_index);
  1089. }
  1090. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1091. psde->pipe_hw->ops.setup_fp16_igc) {
  1092. fp16_igc = !!sde_plane_get_property(pstate,
  1093. PLANE_PROP_FP16_IGC);
  1094. hw_cfg.last_feature = 0;
  1095. hw_cfg.ctl = ctl;
  1096. hw_cfg.len = sizeof(bool);
  1097. hw_cfg.payload = &fp16_igc;
  1098. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1099. pstate->multirect_index, &hw_cfg);
  1100. }
  1101. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1102. psde->pipe_hw->ops.setup_fp16_gc) {
  1103. fp16_gc = msm_property_get_blob(&psde->property_info,
  1104. &pstate->property_state,
  1105. &size,
  1106. PLANE_PROP_FP16_GC);
  1107. hw_cfg.last_feature = 0;
  1108. hw_cfg.ctl = ctl;
  1109. hw_cfg.len = size;
  1110. hw_cfg.payload = fp16_gc;
  1111. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1112. pstate->multirect_index, &hw_cfg);
  1113. }
  1114. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1115. psde->pipe_hw->ops.setup_fp16_csc) {
  1116. fp16_csc = msm_property_get_blob(&psde->property_info,
  1117. &pstate->property_state,
  1118. &size,
  1119. PLANE_PROP_FP16_CSC);
  1120. hw_cfg.last_feature = 0;
  1121. hw_cfg.ctl = ctl;
  1122. hw_cfg.len = size;
  1123. hw_cfg.payload = fp16_csc;
  1124. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1125. pstate->multirect_index, &hw_cfg);
  1126. }
  1127. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1128. psde->pipe_hw->ops.setup_fp16_unmult) {
  1129. fp16_unmult = !!sde_plane_get_property(pstate,
  1130. PLANE_PROP_FP16_UNMULT);
  1131. hw_cfg.last_feature = 0;
  1132. hw_cfg.ctl = ctl;
  1133. hw_cfg.len = sizeof(bool);
  1134. hw_cfg.payload = &fp16_unmult;
  1135. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1136. pstate->multirect_index, &hw_cfg);
  1137. }
  1138. }
  1139. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1140. struct sde_plane_state *pstate,
  1141. const struct sde_format *fmt, bool color_fill)
  1142. {
  1143. struct sde_hw_pixel_ext *pe;
  1144. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1145. const struct drm_format_info *info = NULL;
  1146. if (!psde || !fmt || !pstate) {
  1147. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1148. !psde, !fmt, !pstate);
  1149. return;
  1150. }
  1151. info = drm_format_info(fmt->base.pixel_format);
  1152. pe = &pstate->pixel_ext;
  1153. psde->pipe_cfg.horz_decimation =
  1154. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1155. psde->pipe_cfg.vert_decimation =
  1156. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1157. /* don't chroma subsample if decimating */
  1158. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1159. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1160. /* update scaler */
  1161. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1162. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1163. int rc = -EINVAL;
  1164. if (!color_fill && !psde->debugfs_default_scale)
  1165. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1166. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1167. _sde_plane_setup_scaler3_lut(psde, pstate);
  1168. if (rc || pstate->scaler_check_state !=
  1169. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1170. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1171. pstate->scaler_check_state,
  1172. psde->debugfs_default_scale, rc,
  1173. psde->pipe_cfg.src_rect.w,
  1174. psde->pipe_cfg.src_rect.h,
  1175. psde->pipe_cfg.dst_rect.w,
  1176. psde->pipe_cfg.dst_rect.h,
  1177. pstate->multirect_mode);
  1178. /* calculate default config for QSEED3 */
  1179. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1180. chroma_subsmpl_h, chroma_subsmpl_v);
  1181. }
  1182. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1183. color_fill || psde->debugfs_default_scale) {
  1184. uint32_t deci_dim, i;
  1185. /* calculate default configuration for QSEED2 */
  1186. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1187. SDE_DEBUG_PLANE(psde, "default config\n");
  1188. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1189. psde->pipe_cfg.horz_decimation);
  1190. _sde_plane_setup_scaler2(psde,
  1191. deci_dim,
  1192. psde->pipe_cfg.dst_rect.w,
  1193. pe->phase_step_x,
  1194. pe->horz_filter, fmt, chroma_subsmpl_h);
  1195. if (SDE_FORMAT_IS_YUV(fmt))
  1196. deci_dim &= ~0x1;
  1197. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1198. psde->pipe_cfg.dst_rect.w, deci_dim,
  1199. pe->phase_step_x,
  1200. pe->roi_w,
  1201. pe->num_ext_pxls_left,
  1202. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1203. chroma_subsmpl_h, 0);
  1204. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1205. psde->pipe_cfg.vert_decimation);
  1206. _sde_plane_setup_scaler2(psde,
  1207. deci_dim,
  1208. psde->pipe_cfg.dst_rect.h,
  1209. pe->phase_step_y,
  1210. pe->vert_filter, fmt, chroma_subsmpl_v);
  1211. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1212. psde->pipe_cfg.dst_rect.h, deci_dim,
  1213. pe->phase_step_y,
  1214. pe->roi_h,
  1215. pe->num_ext_pxls_top,
  1216. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1217. chroma_subsmpl_v, 1);
  1218. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1219. if (pe->num_ext_pxls_left[i] >= 0)
  1220. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1221. else
  1222. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1223. if (pe->num_ext_pxls_right[i] >= 0)
  1224. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1225. else
  1226. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1227. if (pe->num_ext_pxls_top[i] >= 0)
  1228. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1229. else
  1230. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1231. if (pe->num_ext_pxls_btm[i] >= 0)
  1232. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1233. else
  1234. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1235. }
  1236. }
  1237. if (psde->pipe_hw->ops.setup_pre_downscale)
  1238. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1239. &pstate->pre_down);
  1240. }
  1241. /**
  1242. * _sde_plane_color_fill - enables color fill on plane
  1243. * @psde: Pointer to SDE plane object
  1244. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1245. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1246. * Returns: 0 on success
  1247. */
  1248. static int _sde_plane_color_fill(struct sde_plane *psde,
  1249. uint32_t color, uint32_t alpha)
  1250. {
  1251. const struct sde_format *fmt;
  1252. const struct drm_plane *plane;
  1253. struct sde_plane_state *pstate;
  1254. bool blend_enable = true;
  1255. if (!psde || !psde->base.state) {
  1256. SDE_ERROR("invalid plane\n");
  1257. return -EINVAL;
  1258. }
  1259. if (!psde->pipe_hw) {
  1260. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1261. return -EINVAL;
  1262. }
  1263. plane = &psde->base;
  1264. pstate = to_sde_plane_state(plane->state);
  1265. SDE_DEBUG_PLANE(psde, "\n");
  1266. /*
  1267. * select fill format to match user property expectation,
  1268. * h/w only supports RGB variants
  1269. */
  1270. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1271. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1272. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1273. /* update sspp */
  1274. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1275. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1276. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1277. pstate->multirect_index);
  1278. /* override scaler/decimation if solid fill */
  1279. psde->pipe_cfg.src_rect.x = 0;
  1280. psde->pipe_cfg.src_rect.y = 0;
  1281. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1282. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1283. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1284. if (psde->pipe_hw->ops.setup_format)
  1285. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1286. fmt, blend_enable,
  1287. SDE_SSPP_SOLID_FILL,
  1288. pstate->multirect_index);
  1289. if (psde->pipe_hw->ops.setup_rects)
  1290. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1291. &psde->pipe_cfg,
  1292. pstate->multirect_index);
  1293. if (psde->pipe_hw->ops.setup_pe)
  1294. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1295. &pstate->pixel_ext);
  1296. if (psde->pipe_hw->ops.setup_scaler &&
  1297. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1298. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1299. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1300. &psde->pipe_cfg, &pstate->pixel_ext,
  1301. &pstate->scaler3_cfg);
  1302. }
  1303. }
  1304. return 0;
  1305. }
  1306. /**
  1307. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1308. * @plane: Pointer to drm plane
  1309. * @state: Pointer to drm plane state to be validated
  1310. * return: 0 if success; error code otherwise
  1311. */
  1312. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1313. struct drm_plane_state *state)
  1314. {
  1315. struct sde_plane *psde;
  1316. struct sde_plane_state *pstate, *old_pstate;
  1317. int ret = 0;
  1318. u32 rotation;
  1319. if (!plane || !state) {
  1320. SDE_ERROR("invalid plane/state\n");
  1321. return -EINVAL;
  1322. }
  1323. psde = to_sde_plane(plane);
  1324. pstate = to_sde_plane_state(state);
  1325. old_pstate = to_sde_plane_state(plane->state);
  1326. /* check inline rotation and simplify the transform */
  1327. rotation = drm_rotation_simplify(
  1328. state->rotation,
  1329. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1330. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1331. if ((rotation & DRM_MODE_ROTATE_180) ||
  1332. (rotation & DRM_MODE_ROTATE_270)) {
  1333. SDE_ERROR_PLANE(psde,
  1334. "invalid rotation transform must be simplified 0x%x\n",
  1335. rotation);
  1336. ret = -EINVAL;
  1337. goto exit;
  1338. }
  1339. if (rotation & DRM_MODE_ROTATE_90) {
  1340. struct msm_drm_private *priv = plane->dev->dev_private;
  1341. struct sde_kms *sde_kms;
  1342. const struct msm_format *msm_fmt;
  1343. const struct sde_format *fmt;
  1344. struct sde_rect src;
  1345. bool q16_data = true;
  1346. POPULATE_RECT(&src, state->src_x, state->src_y,
  1347. state->src_w, state->src_h, q16_data);
  1348. /*
  1349. * DRM framework expects rotation flag in counter-clockwise
  1350. * direction and the HW expects in clockwise direction.
  1351. * Flip the flags to match with HW.
  1352. */
  1353. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1354. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1355. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1356. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1357. !psde->pipe_sblk->in_rot_maxheight ||
  1358. !psde->pipe_sblk->in_rot_format_list ||
  1359. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1360. SDE_ERROR_PLANE(psde,
  1361. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1362. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1363. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1364. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1365. !psde->pipe_sblk->in_rot_format_list,
  1366. !psde->pipe_sblk->in_rot_maxheight,
  1367. psde->features);
  1368. ret = -EINVAL;
  1369. goto exit;
  1370. }
  1371. /* check for valid height */
  1372. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1373. SDE_ERROR_PLANE(psde,
  1374. "invalid height for inline rot:%d max:%d\n",
  1375. src.h, psde->pipe_sblk->in_rot_maxheight);
  1376. ret = -EINVAL;
  1377. goto exit;
  1378. }
  1379. if (!sde_plane_enabled(state))
  1380. goto exit;
  1381. /* check for valid formats supported by inline rot */
  1382. sde_kms = to_sde_kms(priv->kms);
  1383. msm_fmt = msm_framebuffer_format(state->fb);
  1384. fmt = to_sde_format(msm_fmt);
  1385. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1386. psde->pipe_sblk->in_rot_format_list);
  1387. }
  1388. exit:
  1389. pstate->rotation = rotation;
  1390. return ret;
  1391. }
  1392. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1393. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1394. {
  1395. struct sde_plane *psde;
  1396. struct msm_drm_private *priv;
  1397. struct sde_vbif_set_xin_halt_params halt_params;
  1398. if (!plane || !plane->dev) {
  1399. SDE_ERROR("invalid arguments\n");
  1400. return false;
  1401. }
  1402. psde = to_sde_plane(plane);
  1403. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1404. SDE_ERROR("invalid pipe reference\n");
  1405. return false;
  1406. }
  1407. priv = plane->dev->dev_private;
  1408. if (!priv || !priv->kms) {
  1409. SDE_ERROR("invalid KMS reference\n");
  1410. return false;
  1411. }
  1412. memset(&halt_params, 0, sizeof(halt_params));
  1413. halt_params.vbif_idx = VBIF_RT;
  1414. halt_params.xin_id = xin_id;
  1415. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1416. halt_params.forced_on = halt_forced_clk;
  1417. halt_params.enable = enable;
  1418. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1419. }
  1420. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1421. {
  1422. struct sde_plane *psde;
  1423. if (!plane) {
  1424. SDE_ERROR("invalid plane\n");
  1425. return;
  1426. }
  1427. psde = to_sde_plane(plane);
  1428. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1429. SDE_ERROR("invalid pipe reference\n");
  1430. return;
  1431. }
  1432. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1433. psde->xin_halt_forced_clk =
  1434. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1435. psde->xin_halt_forced_clk, enable);
  1436. }
  1437. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1438. struct drm_crtc *crtc)
  1439. {
  1440. struct sde_plane *psde;
  1441. if (!plane || !crtc) {
  1442. SDE_ERROR("invalid plane/crtc\n");
  1443. return;
  1444. }
  1445. psde = to_sde_plane(plane);
  1446. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1447. return;
  1448. /* do all VBIF programming for the sec-ui allowed SSPP */
  1449. _sde_plane_set_qos_remap(plane);
  1450. _sde_plane_set_ot_limit(plane, crtc);
  1451. }
  1452. /**
  1453. * sde_plane_rot_install_properties - install plane rotator properties
  1454. * @plane: Pointer to drm plane
  1455. * @catalog: Pointer to mdss configuration
  1456. * return: none
  1457. */
  1458. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1459. struct sde_mdss_cfg *catalog)
  1460. {
  1461. struct sde_plane *psde = to_sde_plane(plane);
  1462. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1463. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1464. int ret = 0;
  1465. if (!plane || !psde) {
  1466. SDE_ERROR("invalid plane\n");
  1467. return;
  1468. } else if (!catalog) {
  1469. SDE_ERROR("invalid catalog\n");
  1470. return;
  1471. }
  1472. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1473. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1474. ret = drm_plane_create_rotation_property(plane,
  1475. DRM_MODE_ROTATE_0, supported_rotations);
  1476. if (ret) {
  1477. DRM_ERROR("create rotation property failed: %d\n", ret);
  1478. return;
  1479. }
  1480. }
  1481. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1482. {
  1483. struct sde_plane_state *pstate;
  1484. if (!drm_state)
  1485. return;
  1486. pstate = to_sde_plane_state(drm_state);
  1487. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1488. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1489. }
  1490. /**
  1491. * multi_rect validate API allows to validate only R0 and R1 RECT
  1492. * passing for each plane. Client of this API must not pass multiple
  1493. * plane which are not sharing same XIN client. Such calls will fail
  1494. * even though kernel client is passing valid multirect configuration.
  1495. */
  1496. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1497. {
  1498. struct sde_plane_state *pstate[R_MAX];
  1499. const struct drm_plane_state *drm_state[R_MAX];
  1500. struct sde_rect src[R_MAX], dst[R_MAX];
  1501. struct sde_plane *sde_plane[R_MAX];
  1502. const struct sde_format *fmt[R_MAX];
  1503. int xin_id[R_MAX];
  1504. bool q16_data = true;
  1505. int i, j, buffer_lines, width_threshold[R_MAX];
  1506. unsigned int max_tile_height = 1;
  1507. bool parallel_fetch_qualified = true;
  1508. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1509. const struct msm_format *msm_fmt;
  1510. bool const_alpha_enable = true;
  1511. for (i = 0; i < R_MAX; i++) {
  1512. drm_state[i] = i ? plane->r1 : plane->r0;
  1513. if (!drm_state[i]) {
  1514. SDE_ERROR("drm plane state is NULL\n");
  1515. return -EINVAL;
  1516. }
  1517. pstate[i] = to_sde_plane_state(drm_state[i]);
  1518. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1519. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1520. for (j = 0; j < i; j++) {
  1521. if (xin_id[i] != xin_id[j]) {
  1522. SDE_ERROR_PLANE(sde_plane[i],
  1523. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1524. j, xin_id[j], i, xin_id[i]);
  1525. return -EINVAL;
  1526. }
  1527. }
  1528. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1529. if (!msm_fmt) {
  1530. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1531. return -EINVAL;
  1532. }
  1533. fmt[i] = to_sde_format(msm_fmt);
  1534. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1535. (fmt[i]->tile_height > max_tile_height))
  1536. max_tile_height = fmt[i]->tile_height;
  1537. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1538. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1539. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1540. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1541. drm_state[i]->crtc_h, !q16_data);
  1542. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1543. SDE_ERROR_PLANE(sde_plane[i],
  1544. "scaling is not supported in multirect mode\n");
  1545. return -EINVAL;
  1546. }
  1547. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1548. SDE_ERROR_PLANE(sde_plane[i],
  1549. "inline rotation is not supported in mulirect mode\n");
  1550. return -EINVAL;
  1551. }
  1552. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1553. SDE_ERROR_PLANE(sde_plane[i],
  1554. "Unsupported format for multirect mode\n");
  1555. return -EINVAL;
  1556. }
  1557. /**
  1558. * SSPP PD_MEM is split half - one for each RECT.
  1559. * Tiled formats need 5 lines of buffering while fetching
  1560. * whereas linear formats need only 2 lines.
  1561. * So we cannot support more than half of the supported SSPP
  1562. * width for tiled formats.
  1563. */
  1564. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1565. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1566. width_threshold[i] /= 2;
  1567. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1568. parallel_fetch_qualified = false;
  1569. if (sde_plane[i]->is_virtual)
  1570. mode = sde_plane_get_property(pstate[i],
  1571. PLANE_PROP_MULTIRECT_MODE);
  1572. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1573. const_alpha_enable = false;
  1574. }
  1575. buffer_lines = 2 * max_tile_height;
  1576. /**
  1577. * fallback to driver mode selection logic if client is using
  1578. * multirect plane without setting property.
  1579. *
  1580. * validate multirect mode configuration based on rectangle
  1581. */
  1582. switch (mode) {
  1583. case SDE_SSPP_MULTIRECT_NONE:
  1584. if (parallel_fetch_qualified)
  1585. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1586. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1587. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1588. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1589. else
  1590. SDE_ERROR(
  1591. "planes(%d - %d) multirect mode selection fail\n",
  1592. drm_state[R0]->plane->base.id,
  1593. drm_state[R1]->plane->base.id);
  1594. break;
  1595. case SDE_SSPP_MULTIRECT_PARALLEL:
  1596. if (!parallel_fetch_qualified) {
  1597. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1598. drm_state[R0]->plane->base.id,
  1599. width_threshold[R0], src[R0].w);
  1600. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1601. drm_state[R1]->plane->base.id,
  1602. width_threshold[R1], src[R1].w);
  1603. SDE_ERROR("parallel fetch not qualified\n");
  1604. mode = SDE_SSPP_MULTIRECT_NONE;
  1605. }
  1606. break;
  1607. case SDE_SSPP_MULTIRECT_TIME_MX:
  1608. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1609. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1610. SDE_ERROR(
  1611. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1612. buffer_lines, drm_state[R0]->plane->base.id,
  1613. dst[R0].y, dst[R0].h);
  1614. SDE_ERROR(
  1615. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1616. buffer_lines, drm_state[R1]->plane->base.id,
  1617. dst[R1].y, dst[R1].h);
  1618. SDE_ERROR("time multiplexed fetch not qualified\n");
  1619. mode = SDE_SSPP_MULTIRECT_NONE;
  1620. }
  1621. break;
  1622. default:
  1623. SDE_ERROR("bad mode:%d selection\n", mode);
  1624. mode = SDE_SSPP_MULTIRECT_NONE;
  1625. break;
  1626. }
  1627. for (i = 0; i < R_MAX; i++) {
  1628. pstate[i]->multirect_mode = mode;
  1629. pstate[i]->const_alpha_en = const_alpha_enable;
  1630. }
  1631. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1632. return -EINVAL;
  1633. if (sde_plane[R0]->is_virtual) {
  1634. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1635. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1636. } else {
  1637. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1638. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1639. }
  1640. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1641. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1642. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1643. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1644. return 0;
  1645. }
  1646. /**
  1647. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1648. * @plane: Pointer to drm plane structure
  1649. * @ctl: Pointer to hardware control driver
  1650. * @set: set if true else clear
  1651. */
  1652. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1653. bool set)
  1654. {
  1655. if (!plane || !ctl) {
  1656. SDE_ERROR("invalid parameters\n");
  1657. return;
  1658. }
  1659. if (!ctl->ops.update_bitmask_sspp) {
  1660. SDE_ERROR("invalid ops\n");
  1661. return;
  1662. }
  1663. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1664. }
  1665. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1666. struct drm_plane_state *new_state)
  1667. {
  1668. struct drm_framebuffer *fb = new_state->fb;
  1669. struct sde_plane *psde = to_sde_plane(plane);
  1670. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1671. struct sde_hw_fmt_layout layout;
  1672. struct msm_gem_address_space *aspace;
  1673. int ret;
  1674. if (!fb)
  1675. return 0;
  1676. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1677. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1678. if (ret) {
  1679. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1680. return ret;
  1681. }
  1682. /* cache aspace */
  1683. pstate->aspace = aspace;
  1684. /*
  1685. * when transitioning from secure to non-secure,
  1686. * plane->prepare_fb happens before the commit. In such case,
  1687. * defer the prepare_fb and handled it late, during the commit
  1688. * after attaching the domains as part of the transition
  1689. */
  1690. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1691. true : false;
  1692. if (pstate->defer_prepare_fb) {
  1693. SDE_EVT32(DRMID(plane), psde->pipe);
  1694. SDE_DEBUG_PLANE(psde,
  1695. "domain not attached, prepare_fb handled later\n");
  1696. return 0;
  1697. }
  1698. if (pstate->aspace && fb) {
  1699. ret = msm_framebuffer_prepare(fb,
  1700. pstate->aspace);
  1701. if (ret) {
  1702. SDE_ERROR("failed to prepare framebuffer\n");
  1703. return ret;
  1704. }
  1705. }
  1706. /* validate framebuffer layout before commit */
  1707. ret = sde_format_populate_layout(pstate->aspace,
  1708. fb, &layout);
  1709. if (ret) {
  1710. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1711. return ret;
  1712. }
  1713. return 0;
  1714. }
  1715. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1716. struct drm_plane_state *old_state)
  1717. {
  1718. struct sde_plane *psde = to_sde_plane(plane);
  1719. struct sde_plane_state *old_pstate;
  1720. if (!old_state || !old_state->fb || !plane)
  1721. return;
  1722. old_pstate = to_sde_plane_state(old_state);
  1723. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1724. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1725. }
  1726. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1727. struct drm_plane_state *state,
  1728. struct drm_plane_state *old_state)
  1729. {
  1730. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1731. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1732. struct drm_framebuffer *fb, *old_fb;
  1733. /* no need to check it again */
  1734. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1735. return;
  1736. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1737. || psde->is_error) {
  1738. SDE_DEBUG_PLANE(psde,
  1739. "enabling/disabling full modeset required\n");
  1740. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1741. } else if (to_sde_plane_state(old_state)->pending) {
  1742. SDE_DEBUG_PLANE(psde, "still pending\n");
  1743. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1744. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1745. pstate->multirect_mode != old_pstate->multirect_mode) {
  1746. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1747. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1748. } else if (state->src_w != old_state->src_w ||
  1749. state->src_h != old_state->src_h ||
  1750. state->src_x != old_state->src_x ||
  1751. state->src_y != old_state->src_y) {
  1752. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1753. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1754. } else if (state->crtc_w != old_state->crtc_w ||
  1755. state->crtc_h != old_state->crtc_h ||
  1756. state->crtc_x != old_state->crtc_x ||
  1757. state->crtc_y != old_state->crtc_y) {
  1758. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1759. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1760. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1761. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1762. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1763. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1764. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1765. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1766. } else if (pstate->rotation != old_pstate->rotation) {
  1767. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1768. pstate->rotation, old_pstate->rotation);
  1769. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1770. }
  1771. fb = state->fb;
  1772. old_fb = old_state->fb;
  1773. if (!fb || !old_fb) {
  1774. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1775. } else if ((fb->format->format != old_fb->format->format) ||
  1776. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1777. SDE_DEBUG_PLANE(psde, "format change\n");
  1778. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1779. } else {
  1780. uint64_t new_mod = fb->modifier;
  1781. uint64_t old_mod = old_fb->modifier;
  1782. uint32_t *new_pitches = fb->pitches;
  1783. uint32_t *old_pitches = old_fb->pitches;
  1784. uint32_t *new_offset = fb->offsets;
  1785. uint32_t *old_offset = old_fb->offsets;
  1786. int i;
  1787. if (new_mod != old_mod) {
  1788. SDE_DEBUG_PLANE(psde,
  1789. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1790. new_mod, old_mod);
  1791. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1792. SDE_PLANE_DIRTY_RECTS;
  1793. }
  1794. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1795. if (new_pitches[i] != old_pitches[i]) {
  1796. SDE_DEBUG_PLANE(psde,
  1797. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1798. i, old_pitches[i], new_pitches[i]);
  1799. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1800. break;
  1801. }
  1802. }
  1803. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1804. if (new_offset[i] != old_offset[i]) {
  1805. SDE_DEBUG_PLANE(psde,
  1806. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1807. i, old_offset[i], new_offset[i]);
  1808. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1809. SDE_PLANE_DIRTY_RECTS;
  1810. break;
  1811. }
  1812. }
  1813. }
  1814. }
  1815. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1816. unsigned long base_addr, u32 size)
  1817. {
  1818. int ret = -EINVAL;
  1819. u32 addr;
  1820. struct sde_plane *psde = to_sde_plane(plane);
  1821. if (!psde || !base_addr || !size) {
  1822. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1823. return ret;
  1824. }
  1825. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1826. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1827. is_sde_plane_virtual(plane));
  1828. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1829. ret = 0;
  1830. }
  1831. return ret;
  1832. }
  1833. static inline bool _sde_plane_is_pre_downscale_enabled(
  1834. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1835. {
  1836. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1837. }
  1838. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1839. struct sde_plane_state *pstate,
  1840. const struct sde_format *fmt,
  1841. uint32_t img_w, uint32_t img_h,
  1842. uint32_t src_w, uint32_t src_h,
  1843. uint32_t deci_w, uint32_t deci_h)
  1844. {
  1845. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1846. bool pre_down_en;
  1847. int i;
  1848. if (!psde || !pstate || !fmt) {
  1849. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1850. return -EINVAL;
  1851. }
  1852. if (psde->debugfs_default_scale ||
  1853. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1854. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1855. return 0;
  1856. pd_cfg = &pstate->pre_down;
  1857. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1858. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1859. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1860. uint32_t hor_req_pixels, hor_fetch_pixels;
  1861. uint32_t vert_req_pixels, vert_fetch_pixels;
  1862. uint32_t src_w_tmp, src_h_tmp;
  1863. uint32_t scaler_w, scaler_h;
  1864. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1865. bool rot;
  1866. /* re-use color plane 1's config for plane 2 */
  1867. if (i == 2)
  1868. continue;
  1869. if (pre_down_en) {
  1870. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1871. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1872. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1873. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1874. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1875. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1876. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1877. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1878. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1879. i, pre_down_ratio_x, pre_down_ratio_y);
  1880. }
  1881. src_w_tmp = src_w;
  1882. src_h_tmp = src_h;
  1883. /*
  1884. * For chroma plane, width is half for the following sub sampled
  1885. * formats. Except in case of decimation, where hardware avoids
  1886. * 1 line of decimation instead of downsampling.
  1887. */
  1888. if (i == 1) {
  1889. if (!deci_w &&
  1890. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1891. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1892. src_w_tmp >>= 1;
  1893. if (!deci_h &&
  1894. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1895. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1896. src_h_tmp >>= 1;
  1897. }
  1898. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1899. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1900. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1901. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1902. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1903. deci_w);
  1904. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1905. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1906. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1907. deci_h);
  1908. if ((hor_req_pixels != hor_fetch_pixels) ||
  1909. (hor_fetch_pixels > img_w) ||
  1910. (vert_req_pixels != vert_fetch_pixels) ||
  1911. (vert_fetch_pixels > img_h)) {
  1912. SDE_ERROR_PLANE(psde,
  1913. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1914. hor_req_pixels, vert_req_pixels,
  1915. hor_fetch_pixels, vert_fetch_pixels,
  1916. img_w, img_h);
  1917. return -EINVAL;
  1918. }
  1919. /*
  1920. * swap the scaler src width & height for inline-rotation 90
  1921. * comparison with Pixel-Extension, as PE is based on
  1922. * pre-rotation and QSEED is based on post-rotation
  1923. */
  1924. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1925. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1926. : pstate->scaler3_cfg.src_width[i];
  1927. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1928. : pstate->scaler3_cfg.src_height[i];
  1929. /*
  1930. * Alpha plane can only be scaled using bilinear or pixel
  1931. * repeat/drop, src_width and src_height are only specified
  1932. * for Y and UV plane
  1933. */
  1934. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1935. vert_req_pixels / pre_down_ratio_y !=
  1936. scaler_h)) {
  1937. SDE_ERROR_PLANE(psde,
  1938. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1939. i, pstate->pixel_ext.roi_w[i],
  1940. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1941. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1942. return -EINVAL;
  1943. }
  1944. /*
  1945. * SSPP fetch , unpack output and QSEED3 input lines need
  1946. * to match for Y plane
  1947. */
  1948. if (i == 0 &&
  1949. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1950. BIT(SDE_DRM_DEINTERLACE)) &&
  1951. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1952. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1953. SDE_ERROR_PLANE(psde,
  1954. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1955. i, pstate->pixel_ext.roi_w[i],
  1956. pstate->pixel_ext.roi_h[i],
  1957. pstate->scaler3_cfg.src_width[i],
  1958. pstate->scaler3_cfg.src_height[i],
  1959. src_w, src_h);
  1960. return -EINVAL;
  1961. }
  1962. }
  1963. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1964. return 0;
  1965. }
  1966. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1967. {
  1968. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1969. }
  1970. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1971. struct sde_plane_state *pstate, struct sde_rect *dst,
  1972. u32 src_w, u32 src_h)
  1973. {
  1974. int ret = 0;
  1975. u32 min_ratio_numer, min_ratio_denom;
  1976. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1977. bool pd_x;
  1978. bool pd_y;
  1979. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1980. return ret;
  1981. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1982. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1983. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  1984. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  1985. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  1986. SDE_ERROR_PLANE(psde,
  1987. "hw does not support pre-downscale X: 0x%x\n",
  1988. psde->features);
  1989. ret = -EINVAL;
  1990. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  1991. SDE_ERROR_PLANE(psde,
  1992. "hw does not support pre-downscale Y: 0x%x\n",
  1993. psde->features);
  1994. ret = -EINVAL;
  1995. } else if (!min_ratio_numer || !min_ratio_denom) {
  1996. SDE_ERROR_PLANE(psde,
  1997. "min downscale ratio not set! %u / %u\n",
  1998. min_ratio_numer, min_ratio_denom);
  1999. ret = -EINVAL;
  2000. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2001. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2002. min_ratio_denom))) {
  2003. SDE_ERROR_PLANE(psde,
  2004. "failed min downscale-x check %u->%u, %u/%u\n",
  2005. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2006. ret = -EINVAL;
  2007. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2008. min_ratio_denom))) {
  2009. SDE_ERROR_PLANE(psde,
  2010. "failed min downscale-y check %u->%u, %u/%u\n",
  2011. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2012. ret = -EINVAL;
  2013. }
  2014. return ret;
  2015. }
  2016. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2017. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2018. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2019. u32 *max_numer_h, u32 *max_denom_h)
  2020. {
  2021. bool rotated, has_predown, default_scale;
  2022. const struct sde_sspp_sub_blks *sblk;
  2023. struct sde_hw_inline_pre_downscale_cfg *pd;
  2024. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2025. sblk = psde->pipe_sblk;
  2026. *max_numer_w = sblk->maxdwnscale;
  2027. *max_denom_w = 1;
  2028. *max_numer_h = sblk->maxdwnscale;
  2029. *max_denom_h = 1;
  2030. has_predown = _sde_plane_has_pre_downscale(psde);
  2031. if (has_predown)
  2032. pd = &pstate->pre_down;
  2033. default_scale = psde->debugfs_default_scale ||
  2034. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2035. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2036. /**
  2037. * Inline rotation has different max vertical downscaling limits since
  2038. * the source-width becomes the scaler's pre-downscaled source-height.
  2039. **/
  2040. if (rotated) {
  2041. if (rt_client && has_predown) {
  2042. if (default_scale)
  2043. pd->pre_downscale_x_0 = (src_h >
  2044. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2045. *max_numer_h = pd->pre_downscale_x_0 ?
  2046. sblk->in_rot_maxdwnscale_rt_num :
  2047. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2048. *max_denom_h = pd->pre_downscale_x_0 ?
  2049. sblk->in_rot_maxdwnscale_rt_denom :
  2050. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2051. } else if (rt_client) {
  2052. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2053. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2054. } else {
  2055. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2056. }
  2057. }
  2058. }
  2059. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2060. struct sde_plane *psde, const struct sde_format *fmt,
  2061. struct sde_plane_state *pstate, struct sde_rect *src,
  2062. struct sde_rect *dst, u32 width, u32 height)
  2063. {
  2064. int ret = 0;
  2065. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2066. uint32_t scaler_src_w, scaler_src_h;
  2067. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2068. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2069. uint32_t max_upscale, max_linewidth;
  2070. bool inline_rotation, rt_client;
  2071. struct drm_crtc *crtc;
  2072. struct drm_crtc_state *new_cstate;
  2073. const struct sde_sspp_sub_blks *sblk;
  2074. if (!state || !state->state || !state->crtc) {
  2075. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2076. return -EINVAL;
  2077. }
  2078. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2079. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2080. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2081. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2082. /* with inline rotator, the source of the scaler is post-rotated */
  2083. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2084. if (inline_rotation) {
  2085. scaler_src_w = src_deci_h;
  2086. scaler_src_h = src_deci_w;
  2087. } else {
  2088. scaler_src_w = src_deci_w;
  2089. scaler_src_h = src_deci_h;
  2090. }
  2091. sblk = psde->pipe_sblk;
  2092. max_upscale = sblk->maxupscale;
  2093. if (inline_rotation)
  2094. max_linewidth = sblk->in_rot_maxheight;
  2095. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2096. max_linewidth = sblk->scaling_linewidth;
  2097. else
  2098. max_linewidth = sblk->maxlinewidth;
  2099. crtc = state->crtc;
  2100. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2101. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2102. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2103. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2104. &max_downscale_num_h, &max_downscale_denom_h);
  2105. /* decimation validation */
  2106. if ((deci_w || deci_h)
  2107. && ((deci_w > sblk->maxhdeciexp)
  2108. || (deci_h > sblk->maxvdeciexp))) {
  2109. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2110. ret = -EINVAL;
  2111. } else if ((deci_w || deci_h)
  2112. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2113. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2114. ret = -EINVAL;
  2115. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2116. ((src->w != dst->w) || (src->h != dst->h))) {
  2117. SDE_ERROR_PLANE(psde,
  2118. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2119. src->w, src->h, dst->w, dst->h);
  2120. ret = -EINVAL;
  2121. /* check scaler source width */
  2122. } else if (scaler_src_w > max_linewidth) {
  2123. SDE_ERROR_PLANE(psde,
  2124. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2125. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2126. ret = -E2BIG;
  2127. /* check max scaler capability */
  2128. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2129. ((scaler_src_h * max_upscale) < dst->h) ||
  2130. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2131. < scaler_src_w) ||
  2132. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2133. < scaler_src_h)) {
  2134. SDE_ERROR_PLANE(psde,
  2135. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2136. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2137. inline_rotation, max_downscale_num_w,
  2138. max_downscale_denom_w, max_downscale_num_h,
  2139. max_downscale_denom_h);
  2140. ret = -E2BIG;
  2141. /* check inline pre-downscale support */
  2142. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2143. pstate, dst, src_deci_w, src_deci_h)) {
  2144. ret = -EINVAL;
  2145. /* QSEED validation */
  2146. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2147. width, height, src->w, src->h,
  2148. deci_w, deci_h)) {
  2149. ret = -EINVAL;
  2150. }
  2151. return ret;
  2152. }
  2153. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2154. struct sde_plane_state *pstate, struct sde_rect *src,
  2155. const struct sde_format *fmt, int ret)
  2156. {
  2157. /* check excl rect configs */
  2158. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2159. struct sde_rect intersect;
  2160. /*
  2161. * Check exclusion rect against src rect.
  2162. * it must intersect with source rect.
  2163. */
  2164. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2165. if (intersect.w != pstate->excl_rect.w ||
  2166. intersect.h != pstate->excl_rect.h ||
  2167. SDE_FORMAT_IS_YUV(fmt)) {
  2168. SDE_ERROR_PLANE(psde,
  2169. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2170. pstate->excl_rect.x, pstate->excl_rect.y,
  2171. pstate->excl_rect.w, pstate->excl_rect.h,
  2172. src->x, src->y, src->w, src->h,
  2173. (char *)&fmt->base.pixel_format);
  2174. ret = -EINVAL;
  2175. }
  2176. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2177. pstate->excl_rect.x, pstate->excl_rect.y,
  2178. pstate->excl_rect.w, pstate->excl_rect.h);
  2179. }
  2180. return ret;
  2181. }
  2182. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2183. struct drm_plane_state *state)
  2184. {
  2185. struct sde_kms *sde_kms;
  2186. struct sde_splash_display *splash_display;
  2187. int i, j;
  2188. sde_kms = _sde_plane_get_kms(&psde->base);
  2189. if (!sde_kms || !state->crtc)
  2190. return 0;
  2191. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2192. splash_display = &sde_kms->splash_data.splash_display[i];
  2193. if (splash_display && splash_display->cont_splash_enabled &&
  2194. splash_display->encoder &&
  2195. state->crtc != splash_display->encoder->crtc) {
  2196. for (j = 0; j < MAX_DATA_PATH_PER_DSIPLAY; j++) {
  2197. if (splash_display->pipes[j].sspp ==
  2198. psde->pipe) {
  2199. SDE_ERROR_PLANE(psde,
  2200. "pipe:%d used in cont-splash on crtc:%d\n",
  2201. psde->pipe,
  2202. splash_display->encoder->crtc->base.id);
  2203. return -EINVAL;
  2204. }
  2205. }
  2206. }
  2207. }
  2208. return 0;
  2209. }
  2210. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2211. const struct sde_format *fmt,
  2212. struct sde_rect src, struct sde_rect dst,
  2213. u32 width, u32 height)
  2214. {
  2215. int ret = 0;
  2216. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2217. if (SDE_FORMAT_IS_YUV(fmt) &&
  2218. (!(psde->features & SDE_SSPP_SCALER) ||
  2219. !(psde->features & (BIT(SDE_SSPP_CSC)
  2220. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2221. SDE_ERROR_PLANE(psde,
  2222. "plane doesn't have scaler/csc for yuv\n");
  2223. ret = -EINVAL;
  2224. /* check src bounds */
  2225. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2226. src.w < min_src_size || src.h < min_src_size ||
  2227. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2228. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2229. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2230. src.x, src.y, src.w, src.h);
  2231. ret = -E2BIG;
  2232. /* valid yuv image */
  2233. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2234. (src.w & 0x1) || (src.h & 0x1))) {
  2235. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2236. src.x, src.y, src.w, src.h);
  2237. ret = -EINVAL;
  2238. /* min dst support */
  2239. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2240. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2241. dst.x, dst.y, dst.w, dst.h);
  2242. ret = -EINVAL;
  2243. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2244. !psde->catalog->ubwc_version) {
  2245. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2246. ret = -EINVAL;
  2247. }
  2248. return ret;
  2249. }
  2250. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2251. struct drm_plane_state *state)
  2252. {
  2253. int ret = 0;
  2254. struct sde_plane *psde;
  2255. struct sde_plane_state *pstate;
  2256. const struct msm_format *msm_fmt;
  2257. const struct sde_format *fmt;
  2258. struct sde_rect src, dst;
  2259. bool q16_data = true;
  2260. struct drm_framebuffer *fb;
  2261. u32 width;
  2262. u32 height;
  2263. psde = to_sde_plane(plane);
  2264. pstate = to_sde_plane_state(state);
  2265. if (!psde->pipe_sblk) {
  2266. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2267. return -EINVAL;
  2268. }
  2269. /* src values are in Q16 fixed point, convert to integer */
  2270. POPULATE_RECT(&src, state->src_x, state->src_y,
  2271. state->src_w, state->src_h, q16_data);
  2272. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2273. state->crtc_h, !q16_data);
  2274. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2275. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2276. if (!sde_plane_enabled(state))
  2277. goto modeset_update;
  2278. fb = state->fb;
  2279. width = fb ? state->fb->width : 0x0;
  2280. height = fb ? state->fb->height : 0x0;
  2281. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2282. plane->base.id,
  2283. pstate->rotation,
  2284. width, height,
  2285. fb ? (char *) &state->fb->format->format : 0x0,
  2286. fb ? state->fb->modifier : 0x0);
  2287. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2288. state->src_w >> 16, state->src_h >> 16,
  2289. state->src_x >> 16, state->src_y >> 16,
  2290. state->crtc_w, state->crtc_h,
  2291. state->crtc_x, state->crtc_y);
  2292. msm_fmt = msm_framebuffer_format(fb);
  2293. fmt = to_sde_format(msm_fmt);
  2294. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2295. height);
  2296. if (ret)
  2297. return ret;
  2298. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2299. &src, &dst, width, height);
  2300. if (ret)
  2301. return ret;
  2302. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2303. &src, fmt, ret);
  2304. if (ret)
  2305. return ret;
  2306. ret = _sde_plane_validate_shared_crtc(psde, state);
  2307. if (ret)
  2308. return ret;
  2309. pstate->const_alpha_en = fmt->alpha_enable &&
  2310. (SDE_DRM_BLEND_OP_OPAQUE !=
  2311. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2312. (pstate->stage != SDE_STAGE_0);
  2313. modeset_update:
  2314. if (!ret)
  2315. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2316. state, plane->state);
  2317. return ret;
  2318. }
  2319. static int sde_plane_atomic_check(struct drm_plane *plane,
  2320. struct drm_plane_state *state)
  2321. {
  2322. int ret = 0;
  2323. struct sde_plane *psde;
  2324. struct sde_plane_state *pstate;
  2325. if (!plane || !state) {
  2326. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2327. !plane, !state);
  2328. ret = -EINVAL;
  2329. goto exit;
  2330. }
  2331. psde = to_sde_plane(plane);
  2332. pstate = to_sde_plane_state(state);
  2333. SDE_DEBUG_PLANE(psde, "\n");
  2334. ret = sde_plane_rot_atomic_check(plane, state);
  2335. if (ret)
  2336. goto exit;
  2337. ret = sde_plane_sspp_atomic_check(plane, state);
  2338. exit:
  2339. return ret;
  2340. }
  2341. void sde_plane_flush(struct drm_plane *plane)
  2342. {
  2343. struct sde_plane *psde;
  2344. struct sde_plane_state *pstate;
  2345. if (!plane || !plane->state) {
  2346. SDE_ERROR("invalid plane\n");
  2347. return;
  2348. }
  2349. psde = to_sde_plane(plane);
  2350. pstate = to_sde_plane_state(plane->state);
  2351. /*
  2352. * These updates have to be done immediately before the plane flush
  2353. * timing, and may not be moved to the atomic_update/mode_set functions.
  2354. */
  2355. if (psde->is_error)
  2356. /* force white frame with 100% alpha pipe output on error */
  2357. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2358. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2359. /* force 100% alpha */
  2360. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2361. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2362. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2363. /* flag h/w flush complete */
  2364. if (plane->state)
  2365. pstate->pending = false;
  2366. }
  2367. /**
  2368. * sde_plane_set_error: enable/disable error condition
  2369. * @plane: pointer to drm_plane structure
  2370. */
  2371. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2372. {
  2373. struct sde_plane *psde;
  2374. if (!plane)
  2375. return;
  2376. psde = to_sde_plane(plane);
  2377. psde->is_error = error;
  2378. }
  2379. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2380. struct sde_plane_state *pstate, bool is_tp10)
  2381. {
  2382. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2383. bool prev_rd_en;
  2384. if (!psde->pipe_hw->ops.setup_sys_cache ||
  2385. !(psde->perf_features & BIT(SDE_PERF_SSPP_SYS_CACHE)))
  2386. return;
  2387. prev_rd_en = pstate->sc_cfg.rd_en;
  2388. SDE_DEBUG("features:0x%x rotation:0x%x\n",
  2389. psde->features, pstate->rotation);
  2390. pstate->sc_cfg.rd_en = false;
  2391. pstate->sc_cfg.rd_scid = 0x0;
  2392. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2393. SSPP_SYS_CACHE_SCID;
  2394. pstate->sc_cfg.type = SDE_SYS_CACHE_NONE;
  2395. if (pstate->rotation & DRM_MODE_ROTATE_90) {
  2396. if (is_tp10 && sc_cfg[SDE_SYS_CACHE_ROT].has_sys_cache) {
  2397. pstate->sc_cfg.rd_en = true;
  2398. pstate->sc_cfg.rd_scid =
  2399. sc_cfg[SDE_SYS_CACHE_ROT].llcc_scid;
  2400. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2401. SSPP_SYS_CACHE_SCID;
  2402. pstate->sc_cfg.type = SDE_SYS_CACHE_ROT;
  2403. }
  2404. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_WRITE &&
  2405. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2406. pstate->sc_cfg.rd_en = true;
  2407. pstate->sc_cfg.rd_scid =
  2408. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2409. pstate->sc_cfg.rd_noallocate = false;
  2410. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2411. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2412. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2413. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_READ &&
  2414. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2415. pstate->sc_cfg.rd_en = true;
  2416. pstate->sc_cfg.rd_scid =
  2417. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2418. pstate->sc_cfg.rd_noallocate = true;
  2419. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2420. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2421. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2422. }
  2423. if (!pstate->sc_cfg.rd_en && !prev_rd_en)
  2424. return;
  2425. SDE_EVT32(DRMID(&psde->base), pstate->sc_cfg.rd_scid,
  2426. pstate->sc_cfg.rd_en, pstate->sc_cfg.rd_noallocate);
  2427. psde->pipe_hw->ops.setup_sys_cache(
  2428. psde->pipe_hw, &pstate->sc_cfg);
  2429. }
  2430. void sde_plane_static_img_control(struct drm_plane *plane,
  2431. enum sde_crtc_cache_state state)
  2432. {
  2433. struct sde_plane *psde;
  2434. struct sde_plane_state *pstate;
  2435. if (!plane || !plane->state) {
  2436. SDE_ERROR("invalid plane\n");
  2437. return;
  2438. }
  2439. psde = to_sde_plane(plane);
  2440. pstate = to_sde_plane_state(plane->state);
  2441. pstate->static_cache_state = state;
  2442. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2443. _sde_plane_sspp_setup_sys_cache(psde, pstate, false);
  2444. }
  2445. static void _sde_plane_map_prop_to_dirty_bits(void)
  2446. {
  2447. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2448. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2449. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2450. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2451. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2452. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2453. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2454. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2455. plane_prop_array[PLANE_PROP_ZPOS] =
  2456. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2457. SDE_PLANE_DIRTY_RECTS;
  2458. plane_prop_array[PLANE_PROP_CSC_V1] =
  2459. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2460. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2461. SDE_PLANE_DIRTY_FORMAT;
  2462. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2463. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2464. SDE_PLANE_DIRTY_ALL;
  2465. /* no special action required */
  2466. plane_prop_array[PLANE_PROP_INFO] =
  2467. plane_prop_array[PLANE_PROP_ALPHA] =
  2468. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2469. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2470. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2471. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2472. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2473. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2474. SDE_PLANE_DIRTY_PERF;
  2475. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2476. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2477. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2478. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2479. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2480. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2481. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2482. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2483. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2484. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2485. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2486. SDE_PLANE_DIRTY_ALL;
  2487. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2488. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2489. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2490. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2491. }
  2492. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2493. struct sde_rect *src, struct sde_rect *dst)
  2494. {
  2495. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2496. u32 downscale = (src->h * 1000)/dst->h;
  2497. return (downscale > max_downscale) ? false : true;
  2498. }
  2499. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2500. struct sde_plane *psde, struct sde_plane_state *pstate,
  2501. struct sde_rect *src, struct sde_rect *dst)
  2502. {
  2503. struct sde_hw_pipe_uidle_cfg cfg;
  2504. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2505. u32 fal1_threshold_max = 15;
  2506. u32 line_time = sde_get_linetime(&crtc->mode,
  2507. sde_crtc->src_bpp, sde_crtc->target_bpp); /* nS */
  2508. u32 fal1_target_idle_time_ns =
  2509. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2510. u32 fal10_target_idle_time_ns =
  2511. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2512. u32 fal10_threshold =
  2513. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2514. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2515. fal1_target_idle_time_ns) {
  2516. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2517. cfg.fal10_threshold = fal10_threshold;
  2518. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2519. cfg.fal1_threshold = min(1 +
  2520. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2521. fal1_threshold_max);
  2522. cfg.fal_allowed_threshold = fal10_threshold +
  2523. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2524. } else {
  2525. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2526. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2527. fal1_target_idle_time_ns);
  2528. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2529. }
  2530. SDE_DEBUG_PLANE(psde,
  2531. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",
  2532. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2533. cfg.fal1_threshold, cfg.fal_allowed_threshold);
  2534. SDE_DEBUG_PLANE(psde,
  2535. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2536. line_time, fal1_target_idle_time_ns,
  2537. fal10_target_idle_time_ns,
  2538. psde->catalog->uidle_cfg.max_dwnscale);
  2539. SDE_EVT32_VERBOSE(cfg.enable,
  2540. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2541. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2542. psde->catalog->uidle_cfg.max_dwnscale);
  2543. psde->pipe_hw->ops.setup_uidle(
  2544. psde->pipe_hw, &cfg,
  2545. pstate->multirect_index);
  2546. }
  2547. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2548. struct sde_plane_state *pstate)
  2549. {
  2550. bool enable = false;
  2551. int mode = sde_plane_get_property(pstate,
  2552. PLANE_PROP_FB_TRANSLATION_MODE);
  2553. if ((mode == SDE_DRM_FB_SEC) ||
  2554. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2555. enable = true;
  2556. /* update secure session flag */
  2557. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2558. pstate->multirect_index,
  2559. enable);
  2560. }
  2561. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2562. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2563. {
  2564. const struct sde_format *fmt;
  2565. const struct msm_format *msm_fmt;
  2566. struct sde_plane *psde;
  2567. struct drm_plane_state *state;
  2568. struct sde_plane_state *pstate;
  2569. struct sde_rect src, dst;
  2570. const struct sde_rect *crtc_roi;
  2571. bool q16_data = true;
  2572. int idx;
  2573. psde = to_sde_plane(plane);
  2574. state = plane->state;
  2575. pstate = to_sde_plane_state(state);
  2576. msm_fmt = msm_framebuffer_format(fb);
  2577. if (!msm_fmt) {
  2578. SDE_ERROR("crtc%d plane%d: null format\n",
  2579. DRMID(crtc), DRMID(plane));
  2580. return;
  2581. }
  2582. fmt = to_sde_format(msm_fmt);
  2583. POPULATE_RECT(&src, state->src_x, state->src_y,
  2584. state->src_w, state->src_h, q16_data);
  2585. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2586. state->crtc_w, state->crtc_h, !q16_data);
  2587. SDE_DEBUG_PLANE(psde,
  2588. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2589. fb->base.id, src.x, src.y, src.w, src.h,
  2590. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2591. (char *)&fmt->base.pixel_format,
  2592. SDE_FORMAT_IS_UBWC(fmt));
  2593. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2594. BIT(SDE_DRM_DEINTERLACE)) {
  2595. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2596. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2597. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2598. src.h /= 2;
  2599. src.y = DIV_ROUND_UP(src.y, 2);
  2600. src.y &= ~0x1;
  2601. }
  2602. /*
  2603. * adjust layer mixer position of the sspp in the presence
  2604. * of a partial update to the active lm origin
  2605. */
  2606. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2607. dst.x -= crtc_roi->x;
  2608. dst.y -= crtc_roi->y;
  2609. /* check for UIDLE */
  2610. if (psde->pipe_hw->ops.setup_uidle)
  2611. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2612. psde->pipe_cfg.src_rect = src;
  2613. psde->pipe_cfg.dst_rect = dst;
  2614. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2615. /* check for color fill */
  2616. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2617. PLANE_PROP_COLOR_FILL);
  2618. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2619. /* skip remaining processing on color fill */
  2620. pstate->dirty = 0x0;
  2621. } else if (psde->pipe_hw->ops.setup_rects) {
  2622. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2623. &psde->pipe_cfg,
  2624. pstate->multirect_index);
  2625. }
  2626. if (psde->pipe_hw->ops.setup_pe &&
  2627. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2628. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2629. &pstate->pixel_ext);
  2630. /**
  2631. * when programmed in multirect mode, scalar block will be
  2632. * bypassed. Still we need to update alpha and bitwidth
  2633. * ONLY for RECT0
  2634. */
  2635. if (psde->pipe_hw->ops.setup_scaler &&
  2636. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2637. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2638. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2639. &psde->pipe_cfg, &pstate->pixel_ext,
  2640. &pstate->scaler3_cfg);
  2641. }
  2642. /* update excl rect */
  2643. if (psde->pipe_hw->ops.setup_excl_rect)
  2644. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2645. &pstate->excl_rect,
  2646. pstate->multirect_index);
  2647. /* enable multirect config of corresponding rect */
  2648. if (psde->pipe_hw->ops.update_multirect)
  2649. psde->pipe_hw->ops.update_multirect(
  2650. psde->pipe_hw,
  2651. true,
  2652. pstate->multirect_index,
  2653. pstate->multirect_mode);
  2654. }
  2655. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2656. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2657. {
  2658. uint32_t src_flags = 0;
  2659. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2660. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2661. src_flags |= SDE_SSPP_FLIP_LR;
  2662. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2663. src_flags |= SDE_SSPP_FLIP_UD;
  2664. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2665. src_flags |= SDE_SSPP_ROT_90;
  2666. /* update format */
  2667. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2668. pstate->const_alpha_en, src_flags,
  2669. pstate->multirect_index);
  2670. if (psde->pipe_hw->ops.setup_cdp) {
  2671. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2672. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2673. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2674. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2675. cdp_cfg->ubwc_meta_enable =
  2676. SDE_FORMAT_IS_UBWC(fmt);
  2677. cdp_cfg->tile_amortize_enable =
  2678. SDE_FORMAT_IS_UBWC(fmt) ||
  2679. SDE_FORMAT_IS_TILE(fmt);
  2680. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2681. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2682. pstate->multirect_index);
  2683. }
  2684. _sde_plane_sspp_setup_sys_cache(psde, pstate,
  2685. sde_format_is_tp10_ubwc(fmt));
  2686. /* update csc */
  2687. if (SDE_FORMAT_IS_YUV(fmt))
  2688. _sde_plane_setup_csc(psde);
  2689. else
  2690. psde->csc_ptr = 0;
  2691. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2692. uint32_t pma_mode = 0;
  2693. if (fmt->alpha_enable)
  2694. pma_mode = (uint32_t) sde_plane_get_property(
  2695. pstate, PLANE_PROP_INVERSE_PMA);
  2696. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2697. pstate->multirect_index, pma_mode);
  2698. }
  2699. if (psde->pipe_hw->ops.setup_dgm_csc)
  2700. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2701. pstate->multirect_index, psde->csc_usr_ptr);
  2702. }
  2703. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2704. {
  2705. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2706. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2707. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2708. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2709. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2710. &psde->sharp_cfg);
  2711. }
  2712. static void _sde_plane_update_properties(struct drm_plane *plane,
  2713. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2714. {
  2715. uint32_t nplanes;
  2716. const struct msm_format *msm_fmt;
  2717. const struct sde_format *fmt;
  2718. struct sde_plane *psde;
  2719. struct drm_plane_state *state;
  2720. struct sde_plane_state *pstate;
  2721. psde = to_sde_plane(plane);
  2722. state = plane->state;
  2723. pstate = to_sde_plane_state(state);
  2724. if (!pstate) {
  2725. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2726. return;
  2727. }
  2728. msm_fmt = msm_framebuffer_format(fb);
  2729. if (!msm_fmt) {
  2730. SDE_ERROR("crtc%d plane%d: null format\n",
  2731. DRMID(crtc), DRMID(plane));
  2732. return;
  2733. }
  2734. fmt = to_sde_format(msm_fmt);
  2735. nplanes = fmt->num_planes;
  2736. /* update secure session flag */
  2737. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2738. _sde_plane_update_secure_session(psde, pstate);
  2739. /* update roi config */
  2740. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2741. _sde_plane_update_roi_config(plane, crtc, fb);
  2742. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2743. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2744. psde->pipe_hw->ops.setup_format)
  2745. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2746. sde_color_process_plane_setup(plane);
  2747. /* update sharpening */
  2748. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2749. psde->pipe_hw->ops.setup_sharpening)
  2750. _sde_plane_update_sharpening(psde);
  2751. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2752. SDE_PLANE_DIRTY_FORMAT))
  2753. _sde_plane_set_qos_lut(plane, crtc, fb);
  2754. if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  2755. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2756. _sde_plane_set_ot_limit(plane, crtc);
  2757. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2758. _sde_plane_set_ts_prefill(plane, pstate);
  2759. }
  2760. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2761. _sde_plane_set_qos_remap(plane);
  2762. /* clear dirty */
  2763. pstate->dirty = 0x0;
  2764. }
  2765. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2766. struct drm_plane_state *old_state)
  2767. {
  2768. struct sde_plane *psde;
  2769. struct drm_plane_state *state;
  2770. struct sde_plane_state *pstate;
  2771. struct sde_plane_state *old_pstate;
  2772. struct drm_crtc *crtc;
  2773. struct drm_framebuffer *fb;
  2774. int idx;
  2775. int dirty_prop_flag;
  2776. bool is_rt;
  2777. if (!plane) {
  2778. SDE_ERROR("invalid plane\n");
  2779. return -EINVAL;
  2780. } else if (!plane->state) {
  2781. SDE_ERROR("invalid plane state\n");
  2782. return -EINVAL;
  2783. } else if (!old_state) {
  2784. SDE_ERROR("invalid old state\n");
  2785. return -EINVAL;
  2786. }
  2787. psde = to_sde_plane(plane);
  2788. state = plane->state;
  2789. pstate = to_sde_plane_state(state);
  2790. old_pstate = to_sde_plane_state(old_state);
  2791. crtc = state->crtc;
  2792. fb = state->fb;
  2793. if (!crtc || !fb) {
  2794. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2795. !crtc, !fb);
  2796. return -EINVAL;
  2797. }
  2798. SDE_DEBUG(
  2799. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2800. plane->base.id,
  2801. state->fb->width, state->fb->height,
  2802. (char *) &state->fb->format->format,
  2803. state->fb->modifier,
  2804. state->src_w >> 16, state->src_h >> 16,
  2805. state->src_x >> 16, state->src_y >> 16,
  2806. pstate->rotation,
  2807. state->crtc_w, state->crtc_h,
  2808. state->crtc_x, state->crtc_y);
  2809. /* force reprogramming of all the parameters, if the flag is set */
  2810. if (psde->revalidate) {
  2811. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2812. plane->base.id);
  2813. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2814. psde->revalidate = false;
  2815. }
  2816. /* determine what needs to be refreshed */
  2817. mutex_lock(&psde->property_info.property_lock);
  2818. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2819. &pstate->property_state)) >= 0) {
  2820. dirty_prop_flag = plane_prop_array[idx];
  2821. pstate->dirty |= dirty_prop_flag;
  2822. }
  2823. mutex_unlock(&psde->property_info.property_lock);
  2824. /**
  2825. * since plane_atomic_check is invoked before crtc_atomic_check
  2826. * in the commit sequence, all the parameters for updating the
  2827. * plane dirty flag will not be available during
  2828. * plane_atomic_check as some features params are updated
  2829. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2830. * before sspp update.
  2831. */
  2832. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2833. old_state);
  2834. /* re-program the output rects always if partial update roi changed */
  2835. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2836. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2837. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2838. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2839. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2840. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2841. if (is_rt != psde->is_rt_pipe) {
  2842. psde->is_rt_pipe = is_rt;
  2843. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2844. }
  2845. /* early out if nothing dirty */
  2846. if (!pstate->dirty)
  2847. return 0;
  2848. pstate->pending = true;
  2849. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2850. _sde_plane_update_properties(plane, crtc, fb);
  2851. return 0;
  2852. }
  2853. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2854. struct drm_plane_state *old_state)
  2855. {
  2856. struct sde_plane *psde;
  2857. struct drm_plane_state *state;
  2858. struct sde_plane_state *pstate;
  2859. u32 multirect_index = SDE_SSPP_RECT_0;
  2860. if (!plane) {
  2861. SDE_ERROR("invalid plane\n");
  2862. return;
  2863. } else if (!plane->state) {
  2864. SDE_ERROR("invalid plane state\n");
  2865. return;
  2866. } else if (!old_state) {
  2867. SDE_ERROR("invalid old state\n");
  2868. return;
  2869. }
  2870. psde = to_sde_plane(plane);
  2871. state = plane->state;
  2872. pstate = to_sde_plane_state(state);
  2873. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2874. pstate->multirect_mode);
  2875. pstate->pending = true;
  2876. if (is_sde_plane_virtual(plane))
  2877. multirect_index = SDE_SSPP_RECT_1;
  2878. /* disable multirect config of corresponding rect */
  2879. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  2880. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  2881. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  2882. }
  2883. static void sde_plane_atomic_update(struct drm_plane *plane,
  2884. struct drm_plane_state *old_state)
  2885. {
  2886. struct sde_plane *psde;
  2887. struct drm_plane_state *state;
  2888. if (!plane) {
  2889. SDE_ERROR("invalid plane\n");
  2890. return;
  2891. } else if (!plane->state) {
  2892. SDE_ERROR("invalid plane state\n");
  2893. return;
  2894. }
  2895. psde = to_sde_plane(plane);
  2896. psde->is_error = false;
  2897. state = plane->state;
  2898. SDE_DEBUG_PLANE(psde, "\n");
  2899. if (!sde_plane_enabled(state)) {
  2900. _sde_plane_atomic_disable(plane, old_state);
  2901. } else {
  2902. int ret;
  2903. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2904. /* atomic_check should have ensured that this doesn't fail */
  2905. WARN_ON(ret < 0);
  2906. }
  2907. }
  2908. void sde_plane_restore(struct drm_plane *plane)
  2909. {
  2910. struct sde_plane *psde;
  2911. if (!plane || !plane->state) {
  2912. SDE_ERROR("invalid plane\n");
  2913. return;
  2914. }
  2915. psde = to_sde_plane(plane);
  2916. /*
  2917. * Revalidate is only true here if idle PC occurred and
  2918. * there is no plane state update in current commit cycle.
  2919. */
  2920. if (!psde->revalidate)
  2921. return;
  2922. SDE_DEBUG_PLANE(psde, "\n");
  2923. /* last plane state is same as current state */
  2924. sde_plane_atomic_update(plane, plane->state);
  2925. }
  2926. bool sde_plane_is_cache_required(struct drm_plane *plane,
  2927. enum sde_sys_cache_type type)
  2928. {
  2929. struct sde_plane_state *pstate;
  2930. if (!plane || !plane->state) {
  2931. SDE_ERROR("invalid plane\n");
  2932. return false;
  2933. }
  2934. pstate = to_sde_plane_state(plane->state);
  2935. /* check if llcc is required for the plane */
  2936. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  2937. return true;
  2938. else
  2939. return false;
  2940. }
  2941. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  2942. {
  2943. char feature_name[256];
  2944. if (psde->pipe_sblk->maxhdeciexp) {
  2945. msm_property_install_range(&psde->property_info,
  2946. "h_decimate", 0x0, 0,
  2947. psde->pipe_sblk->maxhdeciexp, 0,
  2948. PLANE_PROP_H_DECIMATE);
  2949. }
  2950. if (psde->pipe_sblk->maxvdeciexp) {
  2951. msm_property_install_range(&psde->property_info,
  2952. "v_decimate", 0x0, 0,
  2953. psde->pipe_sblk->maxvdeciexp, 0,
  2954. PLANE_PROP_V_DECIMATE);
  2955. }
  2956. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  2957. msm_property_install_range(
  2958. &psde->property_info, "scaler_v2",
  2959. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2960. msm_property_install_blob(&psde->property_info,
  2961. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  2962. msm_property_install_blob(&psde->property_info,
  2963. "lut_cir", 0,
  2964. PLANE_PROP_SCALER_LUT_CIR);
  2965. msm_property_install_blob(&psde->property_info,
  2966. "lut_sep", 0,
  2967. PLANE_PROP_SCALER_LUT_SEP);
  2968. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  2969. msm_property_install_range(
  2970. &psde->property_info, "scaler_v2",
  2971. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2972. msm_property_install_blob(&psde->property_info,
  2973. "lut_sep", 0,
  2974. PLANE_PROP_SCALER_LUT_SEP);
  2975. } else if (psde->features & SDE_SSPP_SCALER) {
  2976. msm_property_install_range(
  2977. &psde->property_info, "scaler_v1", 0x0,
  2978. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  2979. }
  2980. if (psde->features & BIT(SDE_SSPP_CSC) ||
  2981. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  2982. msm_property_install_volatile_range(
  2983. &psde->property_info, "csc_v1", 0x0,
  2984. 0, ~0, 0, PLANE_PROP_CSC_V1);
  2985. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  2986. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2987. "SDE_SSPP_HUE_V",
  2988. psde->pipe_sblk->hsic_blk.version >> 16);
  2989. msm_property_install_range(&psde->property_info,
  2990. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2991. PLANE_PROP_HUE_ADJUST);
  2992. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2993. "SDE_SSPP_SATURATION_V",
  2994. psde->pipe_sblk->hsic_blk.version >> 16);
  2995. msm_property_install_range(&psde->property_info,
  2996. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2997. PLANE_PROP_SATURATION_ADJUST);
  2998. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2999. "SDE_SSPP_VALUE_V",
  3000. psde->pipe_sblk->hsic_blk.version >> 16);
  3001. msm_property_install_range(&psde->property_info,
  3002. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3003. PLANE_PROP_VALUE_ADJUST);
  3004. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3005. "SDE_SSPP_CONTRAST_V",
  3006. psde->pipe_sblk->hsic_blk.version >> 16);
  3007. msm_property_install_range(&psde->property_info,
  3008. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3009. PLANE_PROP_CONTRAST_ADJUST);
  3010. }
  3011. }
  3012. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3013. struct sde_kms_info *info)
  3014. {
  3015. char feature_name[256];
  3016. bool is_master = !psde->is_virtual;
  3017. if ((is_master &&
  3018. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3019. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3020. msm_property_install_range(&psde->property_info,
  3021. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3022. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3023. }
  3024. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3025. msm_property_install_volatile_range(
  3026. &psde->property_info, "csc_dma_v1", 0x0,
  3027. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3028. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3029. }
  3030. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3031. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3032. "SDE_SSPP_SKIN_COLOR_V",
  3033. psde->pipe_sblk->memcolor_blk.version >> 16);
  3034. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3035. PLANE_PROP_SKIN_COLOR);
  3036. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3037. "SDE_SSPP_SKY_COLOR_V",
  3038. psde->pipe_sblk->memcolor_blk.version >> 16);
  3039. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3040. PLANE_PROP_SKY_COLOR);
  3041. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3042. "SDE_SSPP_FOLIAGE_COLOR_V",
  3043. psde->pipe_sblk->memcolor_blk.version >> 16);
  3044. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3045. PLANE_PROP_FOLIAGE_COLOR);
  3046. }
  3047. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3048. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3049. "SDE_VIG_3D_LUT_GAMUT_V",
  3050. psde->pipe_sblk->gamut_blk.version >> 16);
  3051. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3052. PLANE_PROP_VIG_GAMUT);
  3053. }
  3054. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3055. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3056. "SDE_VIG_1D_LUT_IGC_V",
  3057. psde->pipe_sblk->igc_blk[0].version >> 16);
  3058. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3059. PLANE_PROP_VIG_IGC);
  3060. }
  3061. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3062. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3063. "SDE_DGM_1D_LUT_IGC_V",
  3064. psde->pipe_sblk->igc_blk[0].version >> 16);
  3065. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3066. PLANE_PROP_DMA_IGC);
  3067. }
  3068. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3069. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3070. "SDE_DGM_1D_LUT_GC_V",
  3071. psde->pipe_sblk->gc_blk[0].version >> 16);
  3072. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3073. PLANE_PROP_DMA_GC);
  3074. }
  3075. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3076. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3077. "SDE_SSPP_FP16_IGC_V",
  3078. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3079. msm_property_install_range(&psde->property_info, feature_name,
  3080. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3081. }
  3082. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3083. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3084. "SDE_SSPP_FP16_GC_V",
  3085. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3086. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3087. PLANE_PROP_FP16_GC);
  3088. }
  3089. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3090. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3091. "SDE_SSPP_FP16_CSC_V",
  3092. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3093. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3094. PLANE_PROP_FP16_CSC);
  3095. }
  3096. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3097. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3098. "SDE_SSPP_FP16_UNMULT_V",
  3099. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3100. msm_property_install_range(&psde->property_info, feature_name,
  3101. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3102. }
  3103. }
  3104. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3105. u32 master_plane_id, struct sde_kms_info *info,
  3106. struct sde_mdss_cfg *catalog)
  3107. {
  3108. bool is_master = !psde->is_virtual;
  3109. const struct sde_format_extended *format_list;
  3110. u32 index;
  3111. int pipe_id;
  3112. if (is_master) {
  3113. format_list = psde->pipe_sblk->format_list;
  3114. } else {
  3115. format_list = psde->pipe_sblk->virt_format_list;
  3116. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3117. master_plane_id);
  3118. }
  3119. if (format_list) {
  3120. sde_kms_info_start(info, "pixel_formats");
  3121. while (format_list->fourcc_format) {
  3122. sde_kms_info_append_format(info,
  3123. format_list->fourcc_format,
  3124. format_list->modifier);
  3125. ++format_list;
  3126. }
  3127. sde_kms_info_stop(info);
  3128. }
  3129. if (psde->pipe_hw && catalog->qseed_hw_version)
  3130. sde_kms_info_add_keyint(info, "scaler_step_ver",
  3131. catalog->qseed_hw_version);
  3132. sde_kms_info_add_keyint(info, "max_linewidth",
  3133. psde->pipe_sblk->maxlinewidth);
  3134. sde_kms_info_add_keyint(info, "max_upscale",
  3135. psde->pipe_sblk->maxupscale);
  3136. sde_kms_info_add_keyint(info, "max_downscale",
  3137. psde->pipe_sblk->maxdwnscale);
  3138. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3139. psde->pipe_sblk->maxhdeciexp);
  3140. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3141. psde->pipe_sblk->maxvdeciexp);
  3142. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3143. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3144. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3145. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3146. if (psde->pipe <= SSPP_VIG3 && psde->pipe >= SSPP_VIG0)
  3147. pipe_id = psde->pipe - SSPP_VIG0;
  3148. else if (psde->pipe <= SSPP_RGB3 && psde->pipe >= SSPP_RGB0)
  3149. pipe_id = psde->pipe - SSPP_RGB0;
  3150. else if (psde->pipe <= SSPP_DMA3 && psde->pipe >= SSPP_DMA0)
  3151. pipe_id = psde->pipe - SSPP_DMA0;
  3152. else
  3153. pipe_id = -1;
  3154. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3155. index = (master_plane_id == 0) ? 0 : 1;
  3156. if (catalog->has_demura &&
  3157. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3158. sde_kms_info_add_keyint(info, "demura_block", index);
  3159. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3160. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3161. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3162. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3163. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3164. const struct sde_format_extended *inline_rot_fmt_list;
  3165. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3166. catalog->true_inline_rot_rev);
  3167. sde_kms_info_add_keyint(info,
  3168. "true_inline_dwnscale_rt",
  3169. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3170. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3171. sde_kms_info_add_keyint(info,
  3172. "true_inline_dwnscale_rt_numerator",
  3173. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3174. sde_kms_info_add_keyint(info,
  3175. "true_inline_dwnscale_rt_denominator",
  3176. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3177. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3178. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3179. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3180. psde->pipe_sblk->in_rot_maxheight);
  3181. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3182. if (inline_rot_fmt_list) {
  3183. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3184. while (inline_rot_fmt_list->fourcc_format) {
  3185. sde_kms_info_append_format(info,
  3186. inline_rot_fmt_list->fourcc_format,
  3187. inline_rot_fmt_list->modifier);
  3188. ++inline_rot_fmt_list;
  3189. }
  3190. sde_kms_info_stop(info);
  3191. }
  3192. }
  3193. }
  3194. /* helper to install properties which are common to planes and crtcs */
  3195. static void _sde_plane_install_properties(struct drm_plane *plane,
  3196. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3197. {
  3198. static const struct drm_prop_enum_list e_blend_op[] = {
  3199. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3200. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3201. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3202. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3203. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3204. };
  3205. static const struct drm_prop_enum_list e_src_config[] = {
  3206. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3207. };
  3208. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3209. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3210. {SDE_DRM_FB_SEC, "sec"},
  3211. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3212. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3213. };
  3214. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3215. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3216. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3217. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3218. };
  3219. struct sde_kms_info *info;
  3220. struct sde_plane *psde = to_sde_plane(plane);
  3221. bool is_master;
  3222. int zpos_max = 255;
  3223. int zpos_def = 0;
  3224. if (!plane || !psde) {
  3225. SDE_ERROR("invalid plane\n");
  3226. return;
  3227. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3228. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3229. !psde->pipe_hw, !psde->pipe_sblk);
  3230. return;
  3231. } else if (!catalog) {
  3232. SDE_ERROR("invalid catalog\n");
  3233. return;
  3234. }
  3235. psde->catalog = catalog;
  3236. is_master = !psde->is_virtual;
  3237. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3238. if (!info) {
  3239. SDE_ERROR("failed to allocate info memory\n");
  3240. return;
  3241. }
  3242. if (sde_is_custom_client()) {
  3243. if (catalog->mixer_count &&
  3244. catalog->mixer[0].sblk->maxblendstages) {
  3245. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3246. if (catalog->has_base_layer &&
  3247. (zpos_max > SDE_STAGE_MAX - 1))
  3248. zpos_max = SDE_STAGE_MAX - 1;
  3249. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3250. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3251. }
  3252. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3253. /* reserve zpos == 0 for primary planes */
  3254. zpos_def = drm_plane_index(plane) + 1;
  3255. }
  3256. msm_property_install_range(&psde->property_info, "zpos",
  3257. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3258. msm_property_install_range(&psde->property_info, "alpha",
  3259. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3260. /* linux default file descriptor range on each process */
  3261. msm_property_install_range(&psde->property_info, "input_fence",
  3262. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3263. if (is_master)
  3264. _sde_plane_install_master_only_properties(psde);
  3265. else
  3266. msm_property_install_enum(&psde->property_info,
  3267. "multirect_mode", 0x0, 0, e_multirect_mode,
  3268. ARRAY_SIZE(e_multirect_mode), 0,
  3269. PLANE_PROP_MULTIRECT_MODE);
  3270. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3271. msm_property_install_volatile_range(&psde->property_info,
  3272. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3273. sde_plane_rot_install_properties(plane, catalog);
  3274. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3275. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3276. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3277. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3278. PLANE_PROP_SRC_CONFIG);
  3279. if (psde->pipe_hw->ops.setup_solidfill)
  3280. msm_property_install_range(&psde->property_info, "color_fill",
  3281. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3282. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3283. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3284. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3285. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3286. msm_property_install_blob(&psde->property_info, "capabilities",
  3287. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3288. sde_kms_info_reset(info);
  3289. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3290. catalog);
  3291. _sde_plane_install_colorproc_properties(psde, info);
  3292. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3293. info->data, SDE_KMS_INFO_DATALEN(info),
  3294. PLANE_PROP_INFO);
  3295. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3296. 0x0, 0, e_fb_translation_mode,
  3297. ARRAY_SIZE(e_fb_translation_mode), 0,
  3298. PLANE_PROP_FB_TRANSLATION_MODE);
  3299. kfree(info);
  3300. }
  3301. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3302. void __user *usr_ptr)
  3303. {
  3304. struct sde_drm_csc_v1 csc_v1;
  3305. int i;
  3306. if (!psde) {
  3307. SDE_ERROR("invalid plane\n");
  3308. return;
  3309. }
  3310. psde->csc_usr_ptr = NULL;
  3311. if (!usr_ptr) {
  3312. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3313. return;
  3314. }
  3315. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3316. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3317. return;
  3318. }
  3319. /* populate from user space */
  3320. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3321. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3322. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3323. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3324. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3325. }
  3326. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3327. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3328. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3329. }
  3330. psde->csc_usr_ptr = &psde->csc_cfg;
  3331. }
  3332. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3333. struct sde_plane_state *pstate, void __user *usr)
  3334. {
  3335. struct sde_drm_scaler_v1 scale_v1;
  3336. struct sde_hw_pixel_ext *pe;
  3337. int i;
  3338. if (!psde || !pstate) {
  3339. SDE_ERROR("invalid argument(s)\n");
  3340. return;
  3341. }
  3342. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3343. if (!usr) {
  3344. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3345. return;
  3346. }
  3347. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3348. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3349. return;
  3350. }
  3351. /* force property to be dirty, even if the pointer didn't change */
  3352. msm_property_set_dirty(&psde->property_info,
  3353. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3354. /* populate from user space */
  3355. pe = &pstate->pixel_ext;
  3356. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3357. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3358. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3359. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3360. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3361. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3362. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3363. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3364. }
  3365. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3366. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3367. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3368. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3369. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3370. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3371. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3372. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3373. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3374. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3375. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3376. }
  3377. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3378. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3379. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3380. }
  3381. static void _sde_plane_clear_predownscale_settings(
  3382. struct sde_plane_state *pstate)
  3383. {
  3384. pstate->pre_down.pre_downscale_x_0 = 0;
  3385. pstate->pre_down.pre_downscale_x_1 = 0;
  3386. pstate->pre_down.pre_downscale_y_0 = 0;
  3387. pstate->pre_down.pre_downscale_y_1 = 0;
  3388. }
  3389. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3390. struct sde_plane_state *pstate, void __user *usr)
  3391. {
  3392. struct sde_drm_scaler_v2 scale_v2;
  3393. struct sde_hw_pixel_ext *pe;
  3394. int i;
  3395. struct sde_hw_scaler3_cfg *cfg;
  3396. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3397. if (!psde || !pstate) {
  3398. SDE_ERROR("invalid argument(s)\n");
  3399. return;
  3400. }
  3401. cfg = &pstate->scaler3_cfg;
  3402. pd_cfg = &pstate->pre_down;
  3403. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3404. if (!usr) {
  3405. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3406. cfg->enable = 0;
  3407. _sde_plane_clear_predownscale_settings(pstate);
  3408. goto end;
  3409. }
  3410. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3411. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3412. return;
  3413. }
  3414. /* detach/ignore user data if 'disabled' */
  3415. if (!scale_v2.enable) {
  3416. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3417. cfg->enable = 0;
  3418. _sde_plane_clear_predownscale_settings(pstate);
  3419. goto end;
  3420. }
  3421. /* populate from user space */
  3422. sde_set_scaler_v2(cfg, &scale_v2);
  3423. if (_sde_plane_has_pre_downscale(psde)) {
  3424. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3425. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3426. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3427. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3428. }
  3429. pe = &pstate->pixel_ext;
  3430. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3431. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3432. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3433. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3434. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3435. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3436. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3437. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3438. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3439. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3440. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3441. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3442. }
  3443. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3444. end:
  3445. /* force property to be dirty, even if the pointer didn't change */
  3446. msm_property_set_dirty(&psde->property_info,
  3447. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3448. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3449. cfg->src_width[0], cfg->src_height[0],
  3450. cfg->dst_width, cfg->dst_height);
  3451. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3452. }
  3453. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3454. struct sde_plane_state *pstate, void __user *usr_ptr)
  3455. {
  3456. struct drm_clip_rect excl_rect_v1;
  3457. if (!psde || !pstate) {
  3458. SDE_ERROR("invalid argument(s)\n");
  3459. return;
  3460. }
  3461. if (!usr_ptr) {
  3462. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3463. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3464. return;
  3465. }
  3466. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3467. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3468. return;
  3469. }
  3470. /* populate from user space */
  3471. pstate->excl_rect.x = excl_rect_v1.x1;
  3472. pstate->excl_rect.y = excl_rect_v1.y1;
  3473. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3474. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3475. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3476. pstate->excl_rect.x, pstate->excl_rect.y,
  3477. pstate->excl_rect.w, pstate->excl_rect.h);
  3478. }
  3479. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3480. struct drm_plane_state *state, struct drm_property *property,
  3481. uint64_t val)
  3482. {
  3483. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3484. struct sde_plane_state *pstate;
  3485. int idx, ret = -EINVAL;
  3486. SDE_DEBUG_PLANE(psde, "\n");
  3487. if (!plane) {
  3488. SDE_ERROR("invalid plane\n");
  3489. } else if (!state) {
  3490. SDE_ERROR_PLANE(psde, "invalid state\n");
  3491. } else {
  3492. pstate = to_sde_plane_state(state);
  3493. ret = msm_property_atomic_set(&psde->property_info,
  3494. &pstate->property_state, property, val);
  3495. if (!ret) {
  3496. idx = msm_property_index(&psde->property_info,
  3497. property);
  3498. switch (idx) {
  3499. case PLANE_PROP_INPUT_FENCE:
  3500. _sde_plane_set_input_fence(psde, pstate, val);
  3501. break;
  3502. case PLANE_PROP_CSC_V1:
  3503. case PLANE_PROP_CSC_DMA_V1:
  3504. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3505. break;
  3506. case PLANE_PROP_SCALER_V1:
  3507. _sde_plane_set_scaler_v1(psde, pstate,
  3508. (void *)(uintptr_t)val);
  3509. break;
  3510. case PLANE_PROP_SCALER_V2:
  3511. _sde_plane_set_scaler_v2(psde, pstate,
  3512. (void *)(uintptr_t)val);
  3513. break;
  3514. case PLANE_PROP_EXCL_RECT_V1:
  3515. _sde_plane_set_excl_rect_v1(psde, pstate,
  3516. (void *)(uintptr_t)val);
  3517. break;
  3518. default:
  3519. /* nothing to do */
  3520. break;
  3521. }
  3522. }
  3523. }
  3524. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3525. property->name, property->base.id, val, ret);
  3526. return ret;
  3527. }
  3528. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3529. const struct drm_plane_state *state,
  3530. struct drm_property *property, uint64_t *val)
  3531. {
  3532. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3533. struct sde_plane_state *pstate;
  3534. int ret = -EINVAL;
  3535. if (!plane) {
  3536. SDE_ERROR("invalid plane\n");
  3537. } else if (!state) {
  3538. SDE_ERROR("invalid state\n");
  3539. } else {
  3540. SDE_DEBUG_PLANE(psde, "\n");
  3541. pstate = to_sde_plane_state(state);
  3542. ret = msm_property_atomic_get(&psde->property_info,
  3543. &pstate->property_state, property, val);
  3544. }
  3545. return ret;
  3546. }
  3547. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3548. struct drm_plane_state *plane_state)
  3549. {
  3550. struct sde_plane *psde;
  3551. struct sde_plane_state *pstate;
  3552. struct drm_property *drm_prop;
  3553. enum msm_mdp_plane_property prop_idx;
  3554. if (!plane || !plane_state) {
  3555. SDE_ERROR("invalid params\n");
  3556. return -EINVAL;
  3557. }
  3558. psde = to_sde_plane(plane);
  3559. pstate = to_sde_plane_state(plane_state);
  3560. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3561. uint64_t val = pstate->property_values[prop_idx].value;
  3562. uint64_t def;
  3563. int ret;
  3564. drm_prop = msm_property_index_to_drm_property(
  3565. &psde->property_info, prop_idx);
  3566. if (!drm_prop) {
  3567. /* not all props will be installed, based on caps */
  3568. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3569. prop_idx);
  3570. continue;
  3571. }
  3572. def = msm_property_get_default(&psde->property_info, prop_idx);
  3573. if (val == def)
  3574. continue;
  3575. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3576. drm_prop->name, prop_idx, val, def);
  3577. ret = sde_plane_atomic_set_property(plane, plane_state,
  3578. drm_prop, def);
  3579. if (ret) {
  3580. SDE_ERROR_PLANE(psde,
  3581. "set property failed, idx %d ret %d\n",
  3582. prop_idx, ret);
  3583. continue;
  3584. }
  3585. }
  3586. return 0;
  3587. }
  3588. static void sde_plane_destroy(struct drm_plane *plane)
  3589. {
  3590. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3591. SDE_DEBUG_PLANE(psde, "\n");
  3592. if (psde) {
  3593. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3594. if (psde->blob_info)
  3595. drm_property_blob_put(psde->blob_info);
  3596. msm_property_destroy(&psde->property_info);
  3597. mutex_destroy(&psde->lock);
  3598. /* this will destroy the states as well */
  3599. drm_plane_cleanup(plane);
  3600. if (psde->pipe_hw)
  3601. sde_hw_sspp_destroy(psde->pipe_hw);
  3602. kfree(psde);
  3603. }
  3604. }
  3605. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3606. {
  3607. struct sde_plane_state *pstate;
  3608. if (!state) {
  3609. SDE_ERROR("invalid arg state %d\n", !state);
  3610. return;
  3611. }
  3612. pstate = to_sde_plane_state(state);
  3613. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3614. SDE_DRM_FB_SEC) {
  3615. /* remove ref count for frame buffers */
  3616. if (state->fb) {
  3617. drm_framebuffer_put(state->fb);
  3618. state->fb = NULL;
  3619. }
  3620. }
  3621. }
  3622. static void sde_plane_destroy_state(struct drm_plane *plane,
  3623. struct drm_plane_state *state)
  3624. {
  3625. struct sde_plane *psde;
  3626. struct sde_plane_state *pstate;
  3627. if (!plane || !state) {
  3628. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3629. !plane, !state);
  3630. return;
  3631. }
  3632. psde = to_sde_plane(plane);
  3633. pstate = to_sde_plane_state(state);
  3634. SDE_DEBUG_PLANE(psde, "\n");
  3635. /* remove ref count for frame buffers */
  3636. if (state->fb)
  3637. drm_framebuffer_put(state->fb);
  3638. /* remove ref count for fence */
  3639. if (pstate->input_fence)
  3640. sde_sync_put(pstate->input_fence);
  3641. pstate->input_fence = 0;
  3642. /* destroy value helper */
  3643. msm_property_destroy_state(&psde->property_info, pstate,
  3644. &pstate->property_state);
  3645. }
  3646. static struct drm_plane_state *
  3647. sde_plane_duplicate_state(struct drm_plane *plane)
  3648. {
  3649. struct sde_plane *psde;
  3650. struct sde_plane_state *pstate;
  3651. struct sde_plane_state *old_state;
  3652. struct drm_property *drm_prop;
  3653. uint64_t input_fence_default;
  3654. if (!plane) {
  3655. SDE_ERROR("invalid plane\n");
  3656. return NULL;
  3657. } else if (!plane->state) {
  3658. SDE_ERROR("invalid plane state\n");
  3659. return NULL;
  3660. }
  3661. old_state = to_sde_plane_state(plane->state);
  3662. psde = to_sde_plane(plane);
  3663. if (old_state->cont_splash_populated) {
  3664. plane->state->crtc = NULL;
  3665. old_state->cont_splash_populated = false;
  3666. }
  3667. pstate = msm_property_alloc_state(&psde->property_info);
  3668. if (!pstate) {
  3669. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3670. return NULL;
  3671. }
  3672. SDE_DEBUG_PLANE(psde, "\n");
  3673. /* duplicate value helper */
  3674. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3675. &pstate->property_state, pstate->property_values);
  3676. /* clear out any input fence */
  3677. pstate->input_fence = 0;
  3678. input_fence_default = msm_property_get_default(
  3679. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3680. drm_prop = msm_property_index_to_drm_property(
  3681. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3682. if (msm_property_atomic_set(&psde->property_info,
  3683. &pstate->property_state, drm_prop,
  3684. input_fence_default))
  3685. SDE_DEBUG_PLANE(psde,
  3686. "error clearing duplicated input fence\n");
  3687. pstate->dirty = 0x0;
  3688. pstate->pending = false;
  3689. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3690. /* reset layout offset */
  3691. if (pstate->layout_offset) {
  3692. if (pstate->layout_offset > 0)
  3693. pstate->base.crtc_x += pstate->layout_offset;
  3694. pstate->layout = SDE_LAYOUT_NONE;
  3695. pstate->layout_offset = 0;
  3696. }
  3697. return &pstate->base;
  3698. }
  3699. static void sde_plane_reset(struct drm_plane *plane)
  3700. {
  3701. struct sde_plane *psde;
  3702. struct sde_plane_state *pstate;
  3703. if (!plane) {
  3704. SDE_ERROR("invalid plane\n");
  3705. return;
  3706. }
  3707. psde = to_sde_plane(plane);
  3708. SDE_DEBUG_PLANE(psde, "\n");
  3709. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3710. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3711. return;
  3712. }
  3713. /* remove previous state, if present */
  3714. if (plane->state) {
  3715. sde_plane_destroy_state(plane, plane->state);
  3716. plane->state = 0;
  3717. }
  3718. pstate = msm_property_alloc_state(&psde->property_info);
  3719. if (!pstate) {
  3720. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3721. return;
  3722. }
  3723. /* reset value helper */
  3724. msm_property_reset_state(&psde->property_info, pstate,
  3725. &pstate->property_state,
  3726. pstate->property_values);
  3727. pstate->base.plane = plane;
  3728. plane->state = &pstate->base;
  3729. }
  3730. u32 sde_plane_get_ubwc_error(struct drm_plane *plane)
  3731. {
  3732. u32 ubwc_error = 0;
  3733. struct sde_plane *psde;
  3734. struct sde_plane_state *pstate;
  3735. if (!plane) {
  3736. SDE_ERROR("invalid plane\n");
  3737. return 0;
  3738. }
  3739. psde = to_sde_plane(plane);
  3740. pstate = to_sde_plane_state(plane->state);
  3741. if (!psde->is_virtual && psde->pipe_hw->ops.get_ubwc_error)
  3742. ubwc_error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  3743. pstate->multirect_index);
  3744. return ubwc_error;
  3745. }
  3746. void sde_plane_clear_ubwc_error(struct drm_plane *plane)
  3747. {
  3748. struct sde_plane *psde;
  3749. struct sde_plane_state *pstate;
  3750. if (!plane) {
  3751. SDE_ERROR("invalid plane\n");
  3752. return;
  3753. }
  3754. psde = to_sde_plane(plane);
  3755. pstate = to_sde_plane_state(plane->state);
  3756. if (psde->pipe_hw->ops.clear_ubwc_error)
  3757. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  3758. }
  3759. u32 sde_plane_get_meta_error(struct drm_plane *plane)
  3760. {
  3761. u32 meta_error = 0;
  3762. struct sde_plane *psde;
  3763. struct sde_plane_state *pstate;
  3764. if (!plane) {
  3765. SDE_ERROR("invalid plane\n");
  3766. return 0;
  3767. }
  3768. psde = to_sde_plane(plane);
  3769. pstate = to_sde_plane_state(plane->state);
  3770. if (psde->pipe_hw->ops.get_meta_error)
  3771. meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  3772. pstate->multirect_index);
  3773. return meta_error;
  3774. }
  3775. void sde_plane_clear_meta_error(struct drm_plane *plane)
  3776. {
  3777. struct sde_plane *psde;
  3778. struct sde_plane_state *pstate;
  3779. if (!plane) {
  3780. SDE_ERROR("invalid plane\n");
  3781. return;
  3782. }
  3783. psde = to_sde_plane(plane);
  3784. pstate = to_sde_plane_state(plane->state);
  3785. if (psde->pipe_hw->ops.clear_meta_error)
  3786. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  3787. }
  3788. #ifdef CONFIG_DEBUG_FS
  3789. static ssize_t _sde_plane_danger_read(struct file *file,
  3790. char __user *buff, size_t count, loff_t *ppos)
  3791. {
  3792. struct sde_kms *kms = file->private_data;
  3793. struct sde_mdss_cfg *cfg = kms->catalog;
  3794. int len = 0;
  3795. char buf[40] = {'\0'};
  3796. if (!cfg)
  3797. return -ENODEV;
  3798. if (*ppos)
  3799. return 0; /* the end */
  3800. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3801. if (len < 0 || len >= sizeof(buf))
  3802. return 0;
  3803. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3804. return -EFAULT;
  3805. *ppos += len; /* increase offset */
  3806. return len;
  3807. }
  3808. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3809. {
  3810. struct drm_plane *plane;
  3811. drm_for_each_plane(plane, kms->dev) {
  3812. if (plane->fb && plane->state) {
  3813. sde_plane_danger_signal_ctrl(plane, enable);
  3814. SDE_DEBUG("plane:%d img:%dx%d ",
  3815. plane->base.id, plane->fb->width,
  3816. plane->fb->height);
  3817. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3818. plane->state->src_x >> 16,
  3819. plane->state->src_y >> 16,
  3820. plane->state->src_w >> 16,
  3821. plane->state->src_h >> 16,
  3822. plane->state->crtc_x, plane->state->crtc_y,
  3823. plane->state->crtc_w, plane->state->crtc_h);
  3824. } else {
  3825. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3826. }
  3827. }
  3828. }
  3829. static ssize_t _sde_plane_danger_write(struct file *file,
  3830. const char __user *user_buf, size_t count, loff_t *ppos)
  3831. {
  3832. struct sde_kms *kms = file->private_data;
  3833. struct sde_mdss_cfg *cfg = kms->catalog;
  3834. int disable_panic;
  3835. char buf[10];
  3836. if (!cfg)
  3837. return -EFAULT;
  3838. if (count >= sizeof(buf))
  3839. return -EFAULT;
  3840. if (copy_from_user(buf, user_buf, count))
  3841. return -EFAULT;
  3842. buf[count] = 0; /* end of string */
  3843. if (kstrtoint(buf, 0, &disable_panic))
  3844. return -EFAULT;
  3845. if (disable_panic) {
  3846. /* Disable panic signal for all active pipes */
  3847. SDE_DEBUG("Disabling danger:\n");
  3848. _sde_plane_set_danger_state(kms, false);
  3849. kms->has_danger_ctrl = false;
  3850. } else {
  3851. /* Enable panic signal for all active pipes */
  3852. SDE_DEBUG("Enabling danger:\n");
  3853. kms->has_danger_ctrl = true;
  3854. _sde_plane_set_danger_state(kms, true);
  3855. }
  3856. return count;
  3857. }
  3858. static const struct file_operations sde_plane_danger_enable = {
  3859. .open = simple_open,
  3860. .read = _sde_plane_danger_read,
  3861. .write = _sde_plane_danger_write,
  3862. };
  3863. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3864. {
  3865. struct sde_plane *psde;
  3866. struct sde_kms *kms;
  3867. struct msm_drm_private *priv;
  3868. const struct sde_sspp_sub_blks *sblk = 0;
  3869. const struct sde_sspp_cfg *cfg = 0;
  3870. if (!plane || !plane->dev) {
  3871. SDE_ERROR("invalid arguments\n");
  3872. return -EINVAL;
  3873. }
  3874. priv = plane->dev->dev_private;
  3875. if (!priv || !priv->kms) {
  3876. SDE_ERROR("invalid KMS reference\n");
  3877. return -EINVAL;
  3878. }
  3879. kms = to_sde_kms(priv->kms);
  3880. psde = to_sde_plane(plane);
  3881. if (psde && psde->pipe_hw)
  3882. cfg = psde->pipe_hw->cap;
  3883. if (cfg)
  3884. sblk = cfg->sblk;
  3885. if (!sblk)
  3886. return 0;
  3887. /* create overall sub-directory for the pipe */
  3888. psde->debugfs_root =
  3889. debugfs_create_dir(psde->pipe_name,
  3890. plane->dev->primary->debugfs_root);
  3891. if (!psde->debugfs_root)
  3892. return -ENOMEM;
  3893. /* don't error check these */
  3894. debugfs_create_x64("features", 0400,
  3895. psde->debugfs_root, &psde->features);
  3896. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3897. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3898. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3899. debugfs_create_bool("default_scaling",
  3900. 0600,
  3901. psde->debugfs_root,
  3902. &psde->debugfs_default_scale);
  3903. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3904. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3905. 0600,
  3906. psde->debugfs_root,
  3907. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3908. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3909. 0600,
  3910. psde->debugfs_root,
  3911. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3912. debugfs_create_u32("in_rot_max_downscale_nrt",
  3913. 0600,
  3914. psde->debugfs_root,
  3915. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3916. debugfs_create_u32("in_rot_max_height",
  3917. 0600,
  3918. psde->debugfs_root,
  3919. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3920. }
  3921. debugfs_create_u32("xin_id",
  3922. 0400,
  3923. psde->debugfs_root,
  3924. (u32 *) &cfg->xin_id);
  3925. debugfs_create_x32("creq_vblank",
  3926. 0600,
  3927. psde->debugfs_root,
  3928. (u32 *) &sblk->creq_vblank);
  3929. debugfs_create_x32("danger_vblank",
  3930. 0600,
  3931. psde->debugfs_root,
  3932. (u32 *) &sblk->danger_vblank);
  3933. debugfs_create_file("disable_danger",
  3934. 0600,
  3935. psde->debugfs_root,
  3936. kms, &sde_plane_danger_enable);
  3937. return 0;
  3938. }
  3939. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3940. {
  3941. struct sde_plane *psde;
  3942. if (!plane)
  3943. return;
  3944. psde = to_sde_plane(plane);
  3945. debugfs_remove_recursive(psde->debugfs_root);
  3946. }
  3947. #else
  3948. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3949. {
  3950. return 0;
  3951. }
  3952. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3953. {
  3954. }
  3955. #endif
  3956. static int sde_plane_late_register(struct drm_plane *plane)
  3957. {
  3958. return _sde_plane_init_debugfs(plane);
  3959. }
  3960. static void sde_plane_early_unregister(struct drm_plane *plane)
  3961. {
  3962. _sde_plane_destroy_debugfs(plane);
  3963. }
  3964. static const struct drm_plane_funcs sde_plane_funcs = {
  3965. .update_plane = drm_atomic_helper_update_plane,
  3966. .disable_plane = drm_atomic_helper_disable_plane,
  3967. .destroy = sde_plane_destroy,
  3968. .atomic_set_property = sde_plane_atomic_set_property,
  3969. .atomic_get_property = sde_plane_atomic_get_property,
  3970. .reset = sde_plane_reset,
  3971. .atomic_duplicate_state = sde_plane_duplicate_state,
  3972. .atomic_destroy_state = sde_plane_destroy_state,
  3973. .late_register = sde_plane_late_register,
  3974. .early_unregister = sde_plane_early_unregister,
  3975. };
  3976. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  3977. .prepare_fb = sde_plane_prepare_fb,
  3978. .cleanup_fb = sde_plane_cleanup_fb,
  3979. .atomic_check = sde_plane_atomic_check,
  3980. .atomic_update = sde_plane_atomic_update,
  3981. };
  3982. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  3983. {
  3984. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  3985. }
  3986. bool is_sde_plane_virtual(struct drm_plane *plane)
  3987. {
  3988. return plane ? to_sde_plane(plane)->is_virtual : false;
  3989. }
  3990. /* initialize plane */
  3991. struct drm_plane *sde_plane_init(struct drm_device *dev,
  3992. uint32_t pipe, bool primary_plane,
  3993. unsigned long possible_crtcs, u32 master_plane_id)
  3994. {
  3995. struct drm_plane *plane = NULL, *master_plane = NULL;
  3996. const struct sde_format_extended *format_list;
  3997. struct sde_plane *psde;
  3998. struct msm_drm_private *priv;
  3999. struct sde_kms *kms;
  4000. enum drm_plane_type type;
  4001. int ret = -EINVAL;
  4002. if (!dev) {
  4003. SDE_ERROR("[%u]device is NULL\n", pipe);
  4004. goto exit;
  4005. }
  4006. priv = dev->dev_private;
  4007. if (!priv) {
  4008. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4009. goto exit;
  4010. }
  4011. if (!priv->kms) {
  4012. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4013. goto exit;
  4014. }
  4015. kms = to_sde_kms(priv->kms);
  4016. if (!kms->catalog) {
  4017. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4018. goto exit;
  4019. }
  4020. /* create and zero local structure */
  4021. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4022. if (!psde) {
  4023. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4024. ret = -ENOMEM;
  4025. goto exit;
  4026. }
  4027. /* cache local stuff for later */
  4028. plane = &psde->base;
  4029. psde->pipe = pipe;
  4030. psde->is_virtual = (master_plane_id != 0);
  4031. INIT_LIST_HEAD(&psde->mplane_list);
  4032. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4033. if (master_plane) {
  4034. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4035. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4036. }
  4037. /* initialize underlying h/w driver */
  4038. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog,
  4039. psde->is_virtual);
  4040. if (IS_ERR(psde->pipe_hw)) {
  4041. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4042. ret = PTR_ERR(psde->pipe_hw);
  4043. goto clean_plane;
  4044. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4045. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4046. goto clean_sspp;
  4047. }
  4048. /* cache features mask for later */
  4049. psde->features = psde->pipe_hw->cap->features_ext;
  4050. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4051. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4052. if (!psde->pipe_sblk) {
  4053. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4054. goto clean_sspp;
  4055. }
  4056. if (psde->is_virtual)
  4057. format_list = psde->pipe_sblk->virt_format_list;
  4058. else
  4059. format_list = psde->pipe_sblk->format_list;
  4060. psde->nformats = sde_populate_formats(format_list,
  4061. psde->formats,
  4062. 0,
  4063. ARRAY_SIZE(psde->formats));
  4064. if (!psde->nformats) {
  4065. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4066. goto clean_sspp;
  4067. }
  4068. if (psde->features & BIT(SDE_SSPP_CURSOR))
  4069. type = DRM_PLANE_TYPE_CURSOR;
  4070. else if (primary_plane)
  4071. type = DRM_PLANE_TYPE_PRIMARY;
  4072. else
  4073. type = DRM_PLANE_TYPE_OVERLAY;
  4074. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4075. psde->formats, psde->nformats,
  4076. NULL, type, NULL);
  4077. if (ret)
  4078. goto clean_sspp;
  4079. /* Populate static array of plane property flags */
  4080. _sde_plane_map_prop_to_dirty_bits();
  4081. /* success! finalize initialization */
  4082. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4083. msm_property_init(&psde->property_info, &plane->base, dev,
  4084. priv->plane_property, psde->property_data,
  4085. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4086. sizeof(struct sde_plane_state));
  4087. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4088. /* save user friendly pipe name for later */
  4089. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4090. mutex_init(&psde->lock);
  4091. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4092. pipe, plane->base.id, master_plane_id);
  4093. return plane;
  4094. clean_sspp:
  4095. if (psde && psde->pipe_hw)
  4096. sde_hw_sspp_destroy(psde->pipe_hw);
  4097. clean_plane:
  4098. kfree(psde);
  4099. exit:
  4100. return ERR_PTR(ret);
  4101. }