sde_hw_catalog.h 55 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _SDE_HW_CATALOG_H
  6. #define _SDE_HW_CATALOG_H
  7. #include <linux/kernel.h>
  8. #include <linux/bug.h>
  9. #include <linux/bitmap.h>
  10. #include <linux/err.h>
  11. #include <linux/of_fdt.h>
  12. #include "sde_hw_mdss.h"
  13. /**
  14. * Max hardware block count: For ex: max 12 SSPP pipes or
  15. * 5 ctl paths. In all cases, it can have max 12 hardware blocks
  16. * based on current design
  17. */
  18. #define MAX_BLOCKS 12
  19. #define SDE_HW_VER(MAJOR, MINOR, STEP) ((u32)((MAJOR & 0xF) << 28) |\
  20. ((MINOR & 0xFFF) << 16) |\
  21. (STEP & 0xFFFF))
  22. #define SDE_HW_MAJOR(rev) ((rev) >> 28)
  23. #define SDE_HW_MINOR(rev) (((rev) >> 16) & 0xFFF)
  24. #define SDE_HW_STEP(rev) ((rev) & 0xFFFF)
  25. #define SDE_HW_MAJOR_MINOR(rev) ((rev) >> 16)
  26. #define SDE_HW_VER_170 SDE_HW_VER(1, 7, 0) /* 8996 */
  27. #define SDE_HW_VER_300 SDE_HW_VER(3, 0, 0) /* 8998 */
  28. #define SDE_HW_VER_400 SDE_HW_VER(4, 0, 0) /* sdm845 */
  29. #define SDE_HW_VER_410 SDE_HW_VER(4, 1, 0) /* sdm670 */
  30. #define SDE_HW_VER_500 SDE_HW_VER(5, 0, 0) /* sm8150 */
  31. #define SDE_HW_VER_510 SDE_HW_VER(5, 1, 0) /* sdmshrike */
  32. #define SDE_HW_VER_520 SDE_HW_VER(5, 2, 0) /* sdmmagpie */
  33. #define SDE_HW_VER_530 SDE_HW_VER(5, 3, 0) /* sm6150 */
  34. #define SDE_HW_VER_540 SDE_HW_VER(5, 4, 0) /* sdmtrinket */
  35. #define SDE_HW_VER_600 SDE_HW_VER(6, 0, 0) /* kona */
  36. #define SDE_HW_VER_610 SDE_HW_VER(6, 1, 0) /* sm7250 */
  37. #define SDE_HW_VER_630 SDE_HW_VER(6, 3, 0) /* bengal */
  38. #define SDE_HW_VER_640 SDE_HW_VER(6, 4, 0) /* lagoon */
  39. #define SDE_HW_VER_650 SDE_HW_VER(6, 5, 0) /* scuba */
  40. #define SDE_HW_VER_660 SDE_HW_VER(6, 6, 0) /* holi */
  41. #define SDE_HW_VER_670 SDE_HW_VER(6, 7, 0) /* shima */
  42. #define SDE_HW_VER_700 SDE_HW_VER(7, 0, 0) /* lahaina */
  43. #define SDE_HW_VER_810 SDE_HW_VER(8, 1, 0) /* waipio */
  44. /* Avoid using below IS_XXX macros outside catalog, use feature bit instead */
  45. #define IS_SDE_MAJOR_SAME(rev1, rev2) \
  46. (SDE_HW_MAJOR((rev1)) == SDE_HW_MAJOR((rev2)))
  47. #define IS_SDE_MAJOR_MINOR_SAME(rev1, rev2) \
  48. (SDE_HW_MAJOR_MINOR((rev1)) == SDE_HW_MAJOR_MINOR((rev2)))
  49. #define IS_MSM8996_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_170)
  50. #define IS_MSM8998_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_300)
  51. #define IS_SDM845_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_400)
  52. #define IS_SDM670_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_410)
  53. #define IS_SM8150_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_500)
  54. #define IS_SDMSHRIKE_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_510)
  55. #define IS_SDMMAGPIE_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_520)
  56. #define IS_SM6150_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_530)
  57. #define IS_SDMTRINKET_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_540)
  58. #define IS_KONA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_600)
  59. #define IS_SAIPAN_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_610)
  60. #define IS_BENGAL_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_630)
  61. #define IS_LAGOON_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_640)
  62. #define IS_SCUBA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_650)
  63. #define IS_HOLI_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_660)
  64. #define IS_SHIMA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_670)
  65. #define IS_LAHAINA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_700)
  66. #define IS_WAIPIO_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_810)
  67. #define SDE_HW_BLK_NAME_LEN 16
  68. /* default size of valid register space for MDSS_HW block (offset 0) */
  69. #define DEFAULT_MDSS_HW_BLOCK_SIZE 0x5C
  70. #define MAX_IMG_WIDTH 0x3fff
  71. #define MAX_IMG_HEIGHT 0x3fff
  72. #define CRTC_DUAL_MIXERS_ONLY 2
  73. #define MAX_MIXERS_PER_CRTC 4
  74. #define MAX_MIXERS_PER_LAYOUT 2
  75. #define MAX_LAYOUTS_PER_CRTC (MAX_MIXERS_PER_CRTC / MAX_MIXERS_PER_LAYOUT)
  76. #define SDE_COLOR_PROCESS_VER(MAJOR, MINOR) \
  77. ((((MAJOR) & 0xFFFF) << 16) | (((MINOR) & 0xFFFF)))
  78. #define SDE_COLOR_PROCESS_MAJOR(version) (((version) & 0xFFFF0000) >> 16)
  79. #define SDE_COLOR_PROCESS_MINOR(version) ((version) & 0xFFFF)
  80. #define IS_SDE_CP_VER_1_0(version) \
  81. (version == SDE_COLOR_PROCESS_VER(0x1, 0x0))
  82. #define MAX_XIN_COUNT 16
  83. #define SSPP_SUBBLK_COUNT_MAX 2
  84. #define SDE_CTL_CFG_VERSION_1_0_0 0x100
  85. #define MAX_INTF_PER_CTL_V1 2
  86. #define MAX_DSC_PER_CTL_V1 4
  87. #define MAX_CWB_PER_CTL_V1 2
  88. #define MAX_MERGE_3D_PER_CTL_V1 2
  89. #define MAX_WB_PER_CTL_V1 1
  90. #define MAX_CDM_PER_CTL_V1 1
  91. #define MAX_VDC_PER_CTL_V1 1
  92. #define IS_SDE_CTL_REV_100(rev) \
  93. ((rev) == SDE_CTL_CFG_VERSION_1_0_0)
  94. /**
  95. * True inline rotation supported versions
  96. */
  97. #define SDE_INLINE_ROT_VERSION_1_0_0 0x100
  98. #define SDE_INLINE_ROT_VERSION_2_0_0 0x200
  99. #define IS_SDE_INLINE_ROT_REV_100(rev) \
  100. ((rev) == SDE_INLINE_ROT_VERSION_1_0_0)
  101. #define IS_SDE_INLINE_ROT_REV_200(rev) \
  102. ((rev) == SDE_INLINE_ROT_VERSION_2_0_0)
  103. /*
  104. * UIDLE supported versions
  105. */
  106. #define SDE_UIDLE_VERSION_1_0_0 0x100
  107. #define SDE_UIDLE_VERSION_1_0_1 0x101
  108. #define IS_SDE_UIDLE_REV_100(rev) \
  109. ((rev) == SDE_UIDLE_VERSION_1_0_0)
  110. #define IS_SDE_UIDLE_REV_101(rev) \
  111. ((rev) == SDE_UIDLE_VERSION_1_0_1)
  112. #define SDE_UIDLE_MAJOR(rev) ((rev) >> 8)
  113. #define SDE_HW_UBWC_VER(rev) \
  114. SDE_HW_VER((((rev) >> 8) & 0xF), (((rev) >> 4) & 0xF), ((rev) & 0xF))
  115. /**
  116. * Supported UBWC feature versions
  117. */
  118. enum {
  119. SDE_HW_UBWC_VER_10 = SDE_HW_UBWC_VER(0x100),
  120. SDE_HW_UBWC_VER_20 = SDE_HW_UBWC_VER(0x200),
  121. SDE_HW_UBWC_VER_30 = SDE_HW_UBWC_VER(0x300),
  122. SDE_HW_UBWC_VER_40 = SDE_HW_UBWC_VER(0x400),
  123. };
  124. #define IS_UBWC_10_SUPPORTED(rev) \
  125. IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_10)
  126. #define IS_UBWC_20_SUPPORTED(rev) \
  127. IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_20)
  128. #define IS_UBWC_30_SUPPORTED(rev) \
  129. IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_30)
  130. #define IS_UBWC_40_SUPPORTED(rev) \
  131. IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_40)
  132. /**
  133. * Supported SSPP system cache settings
  134. */
  135. #define SSPP_SYS_CACHE_EN_FLAG BIT(0)
  136. #define SSPP_SYS_CACHE_SCID BIT(1)
  137. #define SSPP_SYS_CACHE_OP_MODE BIT(2)
  138. #define SSPP_SYS_CACHE_OP_TYPE BIT(3)
  139. #define SSPP_SYS_CACHE_NO_ALLOC BIT(4)
  140. /**
  141. * sde_sys_cache_type: Types of system cache supported
  142. * SDE_SYS_CACHE_ROT: Rotator system cache
  143. * SDE_SYS_CACHE_DISP: Static img system cache
  144. */
  145. enum sde_sys_cache_type {
  146. SDE_SYS_CACHE_ROT,
  147. SDE_SYS_CACHE_DISP,
  148. SDE_SYS_CACHE_MAX,
  149. SDE_SYS_CACHE_NONE
  150. };
  151. /**
  152. * All INTRs relevant for a specific target should be enabled via
  153. * _add_to_irq_offset_list()
  154. */
  155. enum sde_intr_hwblk_type {
  156. SDE_INTR_HWBLK_TOP,
  157. SDE_INTR_HWBLK_INTF,
  158. SDE_INTR_HWBLK_AD4,
  159. SDE_INTR_HWBLK_INTF_TEAR,
  160. SDE_INTR_HWBLK_LTM,
  161. SDE_INTR_HWBLK_MAX
  162. };
  163. enum sde_intr_top_intr {
  164. SDE_INTR_TOP_INTR = 1,
  165. SDE_INTR_TOP_INTR2,
  166. SDE_INTR_TOP_HIST_INTR,
  167. SDE_INTR_TOP_MAX
  168. };
  169. struct sde_intr_irq_offsets {
  170. struct list_head list;
  171. enum sde_intr_hwblk_type type;
  172. u32 instance_idx;
  173. u32 base_offset;
  174. };
  175. /**
  176. * MDP TOP BLOCK features
  177. * @SDE_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
  178. * @SDE_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
  179. * @SDE_MDP_BWC, MDSS HW supports Bandwidth compression.
  180. * @SDE_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth
  181. * compression initial revision
  182. * @SDE_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5
  183. * @SDE_MDP_VSYNC_SEL Vsync selection for command mode panels
  184. * @SDE_MDP_WD_TIMER WD timer support
  185. * @SDE_MDP_DHDR_MEMPOOL Dynamic HDR Metadata mempool present
  186. * @SDE_MDP_DHDR_MEMPOOL_4K Dynamic HDR mempool is 4k aligned
  187. * @SDE_MDP_PERIPH_TOP_REMOVED Indicates if periph top0 block is removed
  188. * @SDE_MDP_MAX Maximum value
  189. */
  190. enum {
  191. SDE_MDP_PANIC_PER_PIPE = 0x1,
  192. SDE_MDP_10BIT_SUPPORT,
  193. SDE_MDP_BWC,
  194. SDE_MDP_UBWC_1_0,
  195. SDE_MDP_UBWC_1_5,
  196. SDE_MDP_VSYNC_SEL,
  197. SDE_MDP_WD_TIMER,
  198. SDE_MDP_DHDR_MEMPOOL,
  199. SDE_MDP_DHDR_MEMPOOL_4K,
  200. SDE_MDP_PERIPH_TOP_0_REMOVED,
  201. SDE_MDP_MAX
  202. };
  203. /**
  204. * SSPP sub-blocks/features
  205. * @SDE_SSPP_SRC Src and fetch part of the pipes,
  206. * @SDE_SSPP_SCALER_QSEED2, QSEED2 algorithm support
  207. * @SDE_SSPP_SCALER_QSEED3, QSEED3 alogorithm support
  208. * @SDE_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes
  209. * @SDE_SSPP_CSC, Support of Color space converion
  210. * @SDE_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
  211. * @SDE_SSPP_HSIC, Global HSIC control
  212. * @SDE_SSPP_MEMCOLOR Memory Color Support
  213. * @SDE_SSPP_PCC, Color correction support
  214. * @SDE_SSPP_CURSOR, SSPP can be used as a cursor layer
  215. * @SDE_SSPP_EXCL_RECT, SSPP supports exclusion rect
  216. * @SDE_SSPP_SMART_DMA_V1, SmartDMA 1.0 support
  217. * @SDE_SSPP_SMART_DMA_V2, SmartDMA 2.0 support
  218. * @SDE_SSPP_SMART_DMA_V2p5, SmartDMA 2.5 support
  219. * @SDE_SSPP_VIG_IGC, VIG 1D LUT IGC
  220. * @SDE_SSPP_VIG_GAMUT, VIG 3D LUT Gamut
  221. * @SDE_SSPP_DMA_IGC, DMA 1D LUT IGC
  222. * @SDE_SSPP_DMA_GC, DMA 1D LUT GC
  223. * @SDE_SSPP_INVERSE_PMA Alpha unmultiply (PMA) support
  224. * @SDE_SSPP_DGM_INVERSE_PMA Alpha unmultiply (PMA) support in DGM block
  225. * @SDE_SSPP_DGM_CSC Support of color space conversion in DGM block
  226. * @SDE_SSPP_SEC_UI_ALLOWED Allows secure-ui layers
  227. * @SDE_SSPP_BLOCK_SEC_UI Blocks secure-ui layers
  228. * @SDE_SSPP_SCALER_QSEED3LITE Qseed3lite algorithm support
  229. * @SDE_SSPP_TRUE_INLINE_ROT Support of SSPP true inline rotation v1
  230. * @SDE_SSPP_MULTIRECT_ERROR SSPP has error based on RECT0 or RECT1
  231. * @SDE_SSPP_PREDOWNSCALE Support pre-downscale X-direction by 2 for inline
  232. * @SDE_SSPP_PREDOWNSCALE_Y Support pre-downscale Y-direction for inline
  233. * @SDE_SSPP_INLINE_CONST_CLR Inline rotation requires const clr disabled
  234. * @SDE_SSPP_FP16_IGC FP16 IGC color processing block support
  235. * @SDE_SSPP_FP16_GC FP16 GC color processing block support
  236. * @SDE_SSPP_FP16_CSC FP16 CSC color processing block support
  237. * @SDE_SSPP_FP16_UNMULT FP16 alpha unmult color processing block support
  238. * @SDE_SSPP_MAX maximum value
  239. */
  240. enum {
  241. SDE_SSPP_SRC = 0x1,
  242. SDE_SSPP_SCALER_QSEED2,
  243. SDE_SSPP_SCALER_QSEED3,
  244. SDE_SSPP_SCALER_RGB,
  245. SDE_SSPP_CSC,
  246. SDE_SSPP_CSC_10BIT,
  247. SDE_SSPP_HSIC,
  248. SDE_SSPP_MEMCOLOR,
  249. SDE_SSPP_PCC,
  250. SDE_SSPP_CURSOR,
  251. SDE_SSPP_EXCL_RECT,
  252. SDE_SSPP_SMART_DMA_V1,
  253. SDE_SSPP_SMART_DMA_V2,
  254. SDE_SSPP_SMART_DMA_V2p5,
  255. SDE_SSPP_VIG_IGC,
  256. SDE_SSPP_VIG_GAMUT,
  257. SDE_SSPP_DMA_IGC,
  258. SDE_SSPP_DMA_GC,
  259. SDE_SSPP_INVERSE_PMA,
  260. SDE_SSPP_DGM_INVERSE_PMA,
  261. SDE_SSPP_DGM_CSC,
  262. SDE_SSPP_SEC_UI_ALLOWED,
  263. SDE_SSPP_BLOCK_SEC_UI,
  264. SDE_SSPP_SCALER_QSEED3LITE,
  265. SDE_SSPP_TRUE_INLINE_ROT,
  266. SDE_SSPP_MULTIRECT_ERROR,
  267. SDE_SSPP_PREDOWNSCALE,
  268. SDE_SSPP_PREDOWNSCALE_Y,
  269. SDE_SSPP_INLINE_CONST_CLR,
  270. SDE_SSPP_FP16_IGC,
  271. SDE_SSPP_FP16_GC,
  272. SDE_SSPP_FP16_CSC,
  273. SDE_SSPP_FP16_UNMULT,
  274. SDE_SSPP_MAX
  275. };
  276. /**
  277. * SDE performance features
  278. * @SDE_PERF_SSPP_QOS, SSPP support QoS control, danger/safe/creq
  279. * @SDE_PERF_SSPP_QOS_8LVL, SSPP support 8-level QoS control
  280. * @SDE_PERF_SSPP_TS_PREFILL Supports prefill with traffic shaper
  281. * @SDE_PERF_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
  282. * @SDE_PERF_SSPP_CDP Supports client driven prefetch
  283. * @SDE_PERF_SSPP_SYS_CACHE, SSPP supports system cache
  284. * @SDE_PERF_SSPP_UIDLE, sspp supports uidle
  285. * @SDE_PERF_SSPP_MAX Maximum value
  286. */
  287. enum {
  288. SDE_PERF_SSPP_QOS = 0x1,
  289. SDE_PERF_SSPP_QOS_8LVL,
  290. SDE_PERF_SSPP_TS_PREFILL,
  291. SDE_PERF_SSPP_TS_PREFILL_REC1,
  292. SDE_PERF_SSPP_CDP,
  293. SDE_PERF_SSPP_SYS_CACHE,
  294. SDE_PERF_SSPP_UIDLE,
  295. SDE_PERF_SSPP_MAX
  296. };
  297. /*
  298. * MIXER sub-blocks/features
  299. * @SDE_MIXER_LAYER Layer mixer layer blend configuration,
  300. * @SDE_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
  301. * @SDE_MIXER_GC Gamma correction block
  302. * @SDE_DIM_LAYER Layer mixer supports dim layer
  303. * @SDE_DISP_CWB_PREF Layer mixer preferred for CWB
  304. * @SDE_DISP_DCWB_PREF Layer mixer preferred for Dedicated CWB
  305. * @SDE_DISP_PRIMARY_PREF Layer mixer preferred for primary display
  306. * @SDE_DISP_SECONDARY_PREF Layer mixer preferred for secondary display
  307. * @SDE_MIXER_COMBINED_ALPHA Layer mixer bg and fg alpha in single register
  308. * @SDE_MIXER_NOISE_LAYER Layer mixer supports noise layer
  309. * @SDE_MIXER_MAX maximum value
  310. */
  311. enum {
  312. SDE_MIXER_LAYER = 0x1,
  313. SDE_MIXER_SOURCESPLIT,
  314. SDE_MIXER_GC,
  315. SDE_DIM_LAYER,
  316. SDE_DISP_PRIMARY_PREF,
  317. SDE_DISP_SECONDARY_PREF,
  318. SDE_DISP_CWB_PREF,
  319. SDE_DISP_DCWB_PREF,
  320. SDE_MIXER_COMBINED_ALPHA,
  321. SDE_MIXER_NOISE_LAYER,
  322. SDE_MIXER_MAX
  323. };
  324. /**
  325. * DSPP sub-blocks
  326. * @SDE_DSPP_IGC DSPP Inverse gamma correction block
  327. * @SDE_DSPP_PCC Panel color correction block
  328. * @SDE_DSPP_GC Gamma correction block
  329. * @SDE_DSPP_HSIC Global HSIC block
  330. * @SDE_DSPP_MEMCOLOR Memory Color block
  331. * @SDE_DSPP_SIXZONE Six zone block
  332. * @SDE_DSPP_GAMUT Gamut block
  333. * @SDE_DSPP_DITHER Dither block
  334. * @SDE_DSPP_HIST Histogram block
  335. * @SDE_DSPP_VLUT PA VLUT block
  336. * @SDE_DSPP_AD AD block
  337. * @SDE_DSPP_LTM LTM block
  338. * @SDE_DSPP_SPR SPR block
  339. * @SDE_DSPP_DEMURA Demura block
  340. * @SDE_DSPP_RC RC block
  341. * @SDE_DSPP_SB SB LUT DMA
  342. * @SDE_DSPP_MAX maximum value
  343. */
  344. enum {
  345. SDE_DSPP_IGC = 0x1,
  346. SDE_DSPP_PCC,
  347. SDE_DSPP_GC,
  348. SDE_DSPP_HSIC,
  349. SDE_DSPP_MEMCOLOR,
  350. SDE_DSPP_SIXZONE,
  351. SDE_DSPP_GAMUT,
  352. SDE_DSPP_DITHER,
  353. SDE_DSPP_HIST,
  354. SDE_DSPP_VLUT,
  355. SDE_DSPP_AD,
  356. SDE_DSPP_LTM,
  357. SDE_DSPP_SPR,
  358. SDE_DSPP_DEMURA,
  359. SDE_DSPP_RC,
  360. SDE_DSPP_SB,
  361. SDE_DSPP_MAX
  362. };
  363. /**
  364. * LTM sub-features
  365. * @SDE_LTM_INIT LTM INIT feature
  366. * @SDE_LTM_ROI LTM ROI feature
  367. * @SDE_LTM_VLUT LTM VLUT feature
  368. * @SDE_LTM_MAX maximum value
  369. */
  370. enum {
  371. SDE_LTM_INIT = 0x1,
  372. SDE_LTM_ROI,
  373. SDE_LTM_VLUT,
  374. SDE_LTM_MAX
  375. };
  376. /**
  377. * PINGPONG sub-blocks
  378. * @SDE_PINGPONG_TE Tear check block
  379. * @SDE_PINGPONG_TE2 Additional tear check block for split pipes
  380. * @SDE_PINGPONG_SPLIT PP block supports split fifo
  381. * @SDE_PINGPONG_SLAVE PP block is a suitable slave for split fifo
  382. * @SDE_PINGPONG_DSC, Display stream compression blocks
  383. * @SDE_PINGPONG_DITHER, Dither blocks
  384. * @SDE_PINGPONG_DITHER_LUMA, Dither sub-blocks and features
  385. * @SDE_PINGPONG_MERGE_3D, Separate MERGE_3D block exists
  386. * @SDE_PINGPONG_CWB, PP block supports CWB
  387. * @SDE_PINGPONG_MAX
  388. */
  389. enum {
  390. SDE_PINGPONG_TE = 0x1,
  391. SDE_PINGPONG_TE2,
  392. SDE_PINGPONG_SPLIT,
  393. SDE_PINGPONG_SLAVE,
  394. SDE_PINGPONG_DSC,
  395. SDE_PINGPONG_DITHER,
  396. SDE_PINGPONG_DITHER_LUMA,
  397. SDE_PINGPONG_MERGE_3D,
  398. SDE_PINGPONG_CWB,
  399. SDE_PINGPONG_MAX
  400. };
  401. /** DSC sub-blocks/features
  402. * @SDE_DSC_OUTPUT_CTRL Supports the control of the pp id which gets
  403. * the pixel output from this DSC.
  404. * @SDE_DSC_HW_REV_1_1 dsc block supports dsc 1.1 only
  405. * @SDE_DSC_HW_REV_1_2 dsc block supports dsc 1.1 and 1.2
  406. * @SDE_DSC_NATIVE_422_EN, Supports native422 and native420 encoding
  407. * @SDE_DSC_ENC, DSC encoder sub block
  408. * @SDE_DSC_CTL, DSC ctl sub block
  409. * @SDE_DSC_MAX
  410. */
  411. enum {
  412. SDE_DSC_OUTPUT_CTRL = 0x1,
  413. SDE_DSC_HW_REV_1_1,
  414. SDE_DSC_HW_REV_1_2,
  415. SDE_DSC_NATIVE_422_EN,
  416. SDE_DSC_ENC,
  417. SDE_DSC_CTL,
  418. SDE_DSC_MAX
  419. };
  420. /** VDC sub-blocks/features
  421. * @SDE_VDC_HW_REV_1_2 vdc block supports vdc 1.2 only
  422. * @SDE_VDC_ENC vdc encoder sub block
  423. * @SDE_VDC_CTL vdc ctl sub block
  424. * @SDE_VDC_MAX
  425. */
  426. enum {
  427. SDE_VDC_HW_REV_1_2,
  428. SDE_VDC_ENC,
  429. SDE_VDC_CTL,
  430. SDE_VDC_MAX
  431. };
  432. /**
  433. * CTL sub-blocks
  434. * @SDE_CTL_SPLIT_DISPLAY CTL supports video mode split display
  435. * @SDE_CTL_PINGPONG_SPLIT CTL supports pingpong split
  436. * @SDE_CTL_PRIMARY_PREF CTL preferred for primary display
  437. * @SDE_CTL_ACTIVE_CFG CTL configuration is specified using active
  438. * blocks
  439. * @SDE_CTL_UIDLE CTL supports uidle
  440. * @SDE_CTL_UNIFIED_DSPP_FLUSH CTL supports only one flush bit for DSPP
  441. * @SDE_CTL_MAX
  442. */
  443. enum {
  444. SDE_CTL_SPLIT_DISPLAY = 0x1,
  445. SDE_CTL_PINGPONG_SPLIT,
  446. SDE_CTL_PRIMARY_PREF,
  447. SDE_CTL_ACTIVE_CFG,
  448. SDE_CTL_UIDLE,
  449. SDE_CTL_UNIFIED_DSPP_FLUSH,
  450. SDE_CTL_MAX
  451. };
  452. /**
  453. * INTF sub-blocks
  454. * @SDE_INTF_INPUT_CTRL Supports the setting of pp block from which
  455. * pixel data arrives to this INTF
  456. * @SDE_INTF_TE INTF block has TE configuration support
  457. * @SDE_INTF_TE_ALIGN_VSYNC INTF block has POMS Align vsync support
  458. * @SDE_INTF_WD_TIMER INTF block has WD Timer support
  459. * @SDE_INTF_STATUS INTF block has INTF_STATUS register
  460. * @SDE_INTF_RESET_COUNTER INTF block has frame/line counter reset support
  461. * @SDE_INTF_VSYNC_TIMESTAMP INTF block has vsync timestamp logged
  462. * @SDE_INTF_MAX
  463. */
  464. enum {
  465. SDE_INTF_INPUT_CTRL = 0x1,
  466. SDE_INTF_TE,
  467. SDE_INTF_TE_ALIGN_VSYNC,
  468. SDE_INTF_WD_TIMER,
  469. SDE_INTF_STATUS,
  470. SDE_INTF_RESET_COUNTER,
  471. SDE_INTF_VSYNC_TIMESTAMP,
  472. SDE_INTF_MAX
  473. };
  474. /**
  475. * WB sub-blocks and features
  476. * @SDE_WB_LINE_MODE Writeback module supports line/linear mode
  477. * @SDE_WB_BLOCK_MODE Writeback module supports block mode read
  478. * @SDE_WB_ROTATE rotation support,this is available if writeback
  479. * supports block mode read
  480. * @SDE_WB_CSC Writeback color conversion block support
  481. * @SDE_WB_CHROMA_DOWN, Writeback chroma down block,
  482. * @SDE_WB_DOWNSCALE, Writeback integer downscaler,
  483. * @SDE_WB_DITHER, Dither block
  484. * @SDE_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc
  485. * @SDE_WB_UBWC, Writeback Universal bandwidth compression
  486. * @SDE_WB_YUV_CONFIG Writeback supports output of YUV colorspace
  487. * @SDE_WB_PIPE_ALPHA Writeback supports pipe alpha
  488. * @SDE_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in
  489. * the destination image
  490. * @SDE_WB_QOS, Writeback supports QoS control, danger/safe/creq
  491. * @SDE_WB_QOS_8LVL, Writeback supports 8-level QoS control
  492. * @SDE_WB_CDP Writeback supports client driven prefetch
  493. * @SDE_WB_INPUT_CTRL Writeback supports from which pp block input pixel
  494. * data arrives.
  495. * @SDE_WB_HAS_CWB Writeback block supports concurrent writeback
  496. * @SDE_WB_HAS_DCWB Writeback block supports dedicated CWB
  497. * @SDE_WB_CROP CWB supports cropping
  498. * @SDE_WB_CWB_CTRL Separate CWB control is available for configuring
  499. * @SDE_WB_DCWB_CTRL Separate DCWB control is available for configuring
  500. * @SDE_WB_MAX maximum value
  501. */
  502. enum {
  503. SDE_WB_LINE_MODE = 0x1,
  504. SDE_WB_BLOCK_MODE,
  505. SDE_WB_ROTATE = SDE_WB_BLOCK_MODE,
  506. SDE_WB_CSC,
  507. SDE_WB_CHROMA_DOWN,
  508. SDE_WB_DOWNSCALE,
  509. SDE_WB_DITHER,
  510. SDE_WB_TRAFFIC_SHAPER,
  511. SDE_WB_UBWC,
  512. SDE_WB_YUV_CONFIG,
  513. SDE_WB_PIPE_ALPHA,
  514. SDE_WB_XY_ROI_OFFSET,
  515. SDE_WB_QOS,
  516. SDE_WB_QOS_8LVL,
  517. SDE_WB_CDP,
  518. SDE_WB_INPUT_CTRL,
  519. SDE_WB_HAS_CWB,
  520. SDE_WB_HAS_DCWB,
  521. SDE_WB_CROP,
  522. SDE_WB_CWB_CTRL,
  523. SDE_WB_DCWB_CTRL,
  524. SDE_WB_MAX
  525. };
  526. /* CDM features
  527. * @SDE_CDM_INPUT_CTRL CDM supports from which pp block intput pixel data
  528. * arrives
  529. * @SDE_CDM_MAX maximum value
  530. */
  531. enum {
  532. SDE_CDM_INPUT_CTRL = 0x1,
  533. SDE_CDM_MAX
  534. };
  535. /**
  536. * VBIF sub-blocks and features
  537. * @SDE_VBIF_QOS_OTLIM VBIF supports OT Limit
  538. * @SDE_VBIF_QOS_REMAP VBIF supports QoS priority remap
  539. * @SDE_VBIF_DISABLE_SHAREABLE: VBIF requires inner/outer shareables disabled
  540. * @SDE_VBIF_MAX maximum value
  541. */
  542. enum {
  543. SDE_VBIF_QOS_OTLIM = 0x1,
  544. SDE_VBIF_QOS_REMAP,
  545. SDE_VBIF_DISABLE_SHAREABLE,
  546. SDE_VBIF_MAX
  547. };
  548. /**
  549. * uidle features
  550. * @SDE_UIDLE_QACTIVE_OVERRIDE uidle sends qactive signal
  551. * @SDE_UIDLE_MAX maximum value
  552. */
  553. enum {
  554. SDE_UIDLE_QACTIVE_OVERRIDE = 0x1,
  555. SDE_UIDLE_MAX
  556. };
  557. /**
  558. * MACRO SDE_HW_BLK_INFO - information of HW blocks inside SDE
  559. * @name: string name for debug purposes
  560. * @id: enum identifying this block
  561. * @base: register base offset to mdss
  562. * @len: length of hardware block
  563. * @features bit mask identifying sub-blocks/features
  564. * @perf_features bit mask identifying performance sub-blocks/features
  565. */
  566. #define SDE_HW_BLK_INFO \
  567. char name[SDE_HW_BLK_NAME_LEN]; \
  568. u32 id; \
  569. u32 base; \
  570. u32 len; \
  571. union { \
  572. unsigned long features; \
  573. u64 features_ext; \
  574. }; \
  575. unsigned long perf_features
  576. /**
  577. * MACRO SDE_HW_SUBBLK_INFO - information of HW sub-block inside SDE
  578. * @name: string name for debug purposes
  579. * @id: enum identifying this sub-block
  580. * @base: offset of this sub-block relative to the block
  581. * offset
  582. * @len register block length of this sub-block
  583. */
  584. #define SDE_HW_SUBBLK_INFO \
  585. char name[SDE_HW_BLK_NAME_LEN]; \
  586. u32 id; \
  587. u32 base; \
  588. u32 len
  589. /**
  590. * struct sde_src_blk: SSPP part of the source pipes
  591. * @info: HW register and features supported by this sub-blk
  592. */
  593. struct sde_src_blk {
  594. SDE_HW_SUBBLK_INFO;
  595. };
  596. /**
  597. * struct sde_scaler_blk: Scaler information
  598. * @info: HW register and features supported by this sub-blk
  599. * @regdma_base: offset of this sub-block relative regdma top
  600. * @version: qseed block revision
  601. * @h_preload: horizontal preload
  602. * @v_preload: vertical preload
  603. */
  604. struct sde_scaler_blk {
  605. SDE_HW_SUBBLK_INFO;
  606. u32 regdma_base;
  607. u32 version;
  608. u32 h_preload;
  609. u32 v_preload;
  610. };
  611. struct sde_csc_blk {
  612. SDE_HW_SUBBLK_INFO;
  613. };
  614. /**
  615. * struct sde_pp_blk : Pixel processing sub-blk information
  616. * @regdma_base: offset of this sub-block relative regdma top
  617. * @info: HW register and features supported by this sub-blk
  618. * @version: HW Algorithm version
  619. */
  620. struct sde_pp_blk {
  621. SDE_HW_SUBBLK_INFO;
  622. u32 regdma_base;
  623. u32 version;
  624. };
  625. /**
  626. * struct sde_dsc_blk : DSC Encoder sub-blk information
  627. * @info: HW register and features supported by this sub-blk
  628. */
  629. struct sde_dsc_blk {
  630. SDE_HW_SUBBLK_INFO;
  631. };
  632. /**
  633. * struct sde_vdc_blk : VDC Encoder sub-blk information
  634. * @info: HW register and features supported by this sub-blk
  635. */
  636. struct sde_vdc_blk {
  637. SDE_HW_SUBBLK_INFO;
  638. };
  639. /**
  640. * struct sde_format_extended - define sde specific pixel format+modifier
  641. * @fourcc_format: Base FOURCC pixel format code
  642. * @modifier: 64-bit drm format modifier, same modifier must be applied to all
  643. * framebuffer planes
  644. */
  645. struct sde_format_extended {
  646. uint32_t fourcc_format;
  647. uint64_t modifier;
  648. };
  649. /**
  650. * enum sde_qos_lut_usage - define QoS LUT use cases
  651. */
  652. enum sde_qos_lut_usage {
  653. SDE_QOS_LUT_USAGE_LINEAR,
  654. SDE_QOS_LUT_USAGE_MACROTILE,
  655. SDE_QOS_LUT_USAGE_NRT,
  656. SDE_QOS_LUT_USAGE_CWB,
  657. SDE_QOS_LUT_USAGE_MACROTILE_QSEED,
  658. SDE_QOS_LUT_USAGE_LINEAR_QSEED,
  659. SDE_QOS_LUT_USAGE_MAX,
  660. };
  661. /**
  662. * struct sde_sspp_sub_blks : SSPP sub-blocks
  663. * @maxlinewidth: max source pipe line width support
  664. * @scaling_linewidth: max vig source pipe linewidth for scaling usecases
  665. * @maxdwnscale: max downscale ratio supported(without DECIMATION)
  666. * @maxupscale: maxupscale ratio supported
  667. * @maxwidth: max pixelwidth supported by this pipe
  668. * @creq_vblank: creq priority during vertical blanking
  669. * @danger_vblank: danger priority during vertical blanking
  670. * @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes
  671. * @smart_dma_priority: hw priority of rect1 of multirect pipe
  672. * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
  673. * @max_per_pipe_bw_high: maximum allowable bandwidth of this pipe in kBps
  674. * in case of no VFE
  675. * @top_off: offset of the sub-block top register relative to sspp top
  676. * @src_blk:
  677. * @scaler_blk:
  678. * @csc_blk:
  679. * @hsic:
  680. * @memcolor:
  681. * @pcc_blk:
  682. * @gamut_blk: 3D LUT gamut block
  683. * @num_igc_blk: number of IGC block
  684. * @igc_blk: 1D LUT IGC block
  685. * @num_gc_blk: number of GC block
  686. * @gc_blk: 1D LUT GC block
  687. * @num_dgm_csc_blk: number of DGM CSC blocks
  688. * @dgm_csc_blk: DGM CSC blocks
  689. * @num_fp16_igc_blk: number of FP16 IGC blocks
  690. * @fp16_igc_blk: FP16 IGC block array
  691. * @num_fp16_gc_blk: number of FP16 GC blocks
  692. * @fp16_gc_blk: FP16 GC block array
  693. * @num_fp16_csc_blk: number of FP16 CSC blocks
  694. * @fp16_csc_blk: FP16 CSC block array
  695. * @num_fp16_unmult_blk: number of FP16 UNMULT blocks
  696. * @fp16_unmult_blk: FP16 UNMULT block array
  697. * @format_list: Pointer to list of supported formats
  698. * @virt_format_list: Pointer to list of supported formats for virtual planes
  699. * @in_rot_format_list: Pointer to list of supported formats for inline rotation
  700. * @in_rot_maxdwnscale_rt_num: max downscale ratio for inline rotation
  701. * rt clients - numerator
  702. * @in_rot_maxdwnscale_rt_denom: max downscale ratio for inline rotation
  703. * rt clients - denominator
  704. * @in_rot_maxdwnscale_nrt: max downscale ratio for inline rotation nrt clients
  705. * @in_rot_maxdwnscale_rt_nopd_num: downscale threshold for when pre-downscale
  706. * must be enabled on HW with this support.
  707. * @in_rot_maxdwnscale_rt_nopd_denom: downscale threshold for when pre-downscale
  708. * must be enabled on HW with this support.
  709. * @in_rot_maxheight: max pre rotated height for inline rotation
  710. * @llcc_scid: scid for the system cache
  711. * @llcc_slice size: slice size of the system cache
  712. */
  713. struct sde_sspp_sub_blks {
  714. u32 maxlinewidth;
  715. u32 scaling_linewidth;
  716. u32 creq_vblank;
  717. u32 danger_vblank;
  718. u32 pixel_ram_size;
  719. u32 maxdwnscale;
  720. u32 maxupscale;
  721. u32 maxhdeciexp; /* max decimation is 2^value */
  722. u32 maxvdeciexp; /* max decimation is 2^value */
  723. u32 smart_dma_priority;
  724. u32 max_per_pipe_bw;
  725. u32 max_per_pipe_bw_high;
  726. u32 top_off;
  727. struct sde_src_blk src_blk;
  728. struct sde_scaler_blk scaler_blk;
  729. struct sde_pp_blk csc_blk;
  730. struct sde_pp_blk hsic_blk;
  731. struct sde_pp_blk memcolor_blk;
  732. struct sde_pp_blk pcc_blk;
  733. struct sde_pp_blk gamut_blk;
  734. u32 num_igc_blk;
  735. struct sde_pp_blk igc_blk[SSPP_SUBBLK_COUNT_MAX];
  736. u32 num_gc_blk;
  737. struct sde_pp_blk gc_blk[SSPP_SUBBLK_COUNT_MAX];
  738. u32 num_dgm_csc_blk;
  739. struct sde_pp_blk dgm_csc_blk[SSPP_SUBBLK_COUNT_MAX];
  740. u32 num_fp16_igc_blk;
  741. struct sde_pp_blk fp16_igc_blk[SSPP_SUBBLK_COUNT_MAX];
  742. u32 num_fp16_gc_blk;
  743. struct sde_pp_blk fp16_gc_blk[SSPP_SUBBLK_COUNT_MAX];
  744. u32 num_fp16_csc_blk;
  745. struct sde_pp_blk fp16_csc_blk[SSPP_SUBBLK_COUNT_MAX];
  746. u32 num_fp16_unmult_blk;
  747. struct sde_pp_blk fp16_unmult_blk[SSPP_SUBBLK_COUNT_MAX];
  748. const struct sde_format_extended *format_list;
  749. const struct sde_format_extended *virt_format_list;
  750. const struct sde_format_extended *in_rot_format_list;
  751. u32 in_rot_maxdwnscale_rt_num;
  752. u32 in_rot_maxdwnscale_rt_denom;
  753. u32 in_rot_maxdwnscale_nrt;
  754. u32 in_rot_maxdwnscale_rt_nopd_num;
  755. u32 in_rot_maxdwnscale_rt_nopd_denom;
  756. u32 in_rot_maxheight;
  757. int llcc_scid;
  758. size_t llcc_slice_size;
  759. };
  760. /**
  761. * struct sde_lm_sub_blks: information of mixer block
  762. * @maxwidth: Max pixel width supported by this mixer
  763. * @maxblendstages: Max number of blend-stages supported
  764. * @blendstage_base: Blend-stage register base offset
  765. * @gc: gamma correction block
  766. * @nlayer: noise layer block
  767. */
  768. struct sde_lm_sub_blks {
  769. u32 maxwidth;
  770. u32 maxblendstages;
  771. u32 blendstage_base[MAX_BLOCKS];
  772. struct sde_pp_blk gc;
  773. struct sde_pp_blk nlayer;
  774. };
  775. /**
  776. * struct sde_dspp_rc: Pixel processing rounded corner sub-blk information
  777. * @info: HW register and features supported by this sub-blk.
  778. * @version: HW Algorithm version.
  779. * @idx: HW block instance id.
  780. * @mem_total_size: data memory size.
  781. */
  782. struct sde_dspp_rc {
  783. SDE_HW_SUBBLK_INFO;
  784. u32 version;
  785. u32 idx;
  786. u32 mem_total_size;
  787. };
  788. struct sde_dspp_sub_blks {
  789. struct sde_pp_blk igc;
  790. struct sde_pp_blk pcc;
  791. struct sde_pp_blk gc;
  792. struct sde_pp_blk hsic;
  793. struct sde_pp_blk memcolor;
  794. struct sde_pp_blk sixzone;
  795. struct sde_pp_blk gamut;
  796. struct sde_pp_blk dither;
  797. struct sde_pp_blk hist;
  798. struct sde_pp_blk ad;
  799. struct sde_pp_blk ltm;
  800. struct sde_pp_blk spr;
  801. struct sde_pp_blk vlut;
  802. struct sde_dspp_rc rc;
  803. struct sde_pp_blk demura;
  804. };
  805. struct sde_pingpong_sub_blks {
  806. struct sde_pp_blk te;
  807. struct sde_pp_blk te2;
  808. struct sde_pp_blk dsc;
  809. struct sde_pp_blk dither;
  810. };
  811. /**
  812. * struct sde_dsc_sub_blks : DSC sub-blks
  813. *
  814. */
  815. struct sde_dsc_sub_blks {
  816. struct sde_dsc_blk enc;
  817. struct sde_dsc_blk ctl;
  818. };
  819. /**
  820. * struct sde_vdc_sub_blks : VDC sub-blks
  821. *
  822. */
  823. struct sde_vdc_sub_blks {
  824. struct sde_vdc_blk enc;
  825. struct sde_vdc_blk ctl;
  826. };
  827. struct sde_wb_sub_blocks {
  828. u32 maxlinewidth;
  829. u32 maxlinewidth_linear;
  830. };
  831. struct sde_mdss_base_cfg {
  832. SDE_HW_BLK_INFO;
  833. };
  834. /**
  835. * sde_clk_ctrl_type - Defines top level clock control signals
  836. */
  837. enum sde_clk_ctrl_type {
  838. SDE_CLK_CTRL_NONE,
  839. SDE_CLK_CTRL_VIG0,
  840. SDE_CLK_CTRL_VIG1,
  841. SDE_CLK_CTRL_VIG2,
  842. SDE_CLK_CTRL_VIG3,
  843. SDE_CLK_CTRL_VIG4,
  844. SDE_CLK_CTRL_RGB0,
  845. SDE_CLK_CTRL_RGB1,
  846. SDE_CLK_CTRL_RGB2,
  847. SDE_CLK_CTRL_RGB3,
  848. SDE_CLK_CTRL_DMA0,
  849. SDE_CLK_CTRL_DMA1,
  850. SDE_CLK_CTRL_CURSOR0,
  851. SDE_CLK_CTRL_CURSOR1,
  852. SDE_CLK_CTRL_WB0,
  853. SDE_CLK_CTRL_WB1,
  854. SDE_CLK_CTRL_WB2,
  855. SDE_CLK_CTRL_LUTDMA,
  856. SDE_CLK_CTRL_MAX,
  857. };
  858. /* struct sde_clk_ctrl_reg : Clock control register
  859. * @reg_off: register offset
  860. * @bit_off: bit offset
  861. */
  862. struct sde_clk_ctrl_reg {
  863. u32 reg_off;
  864. u32 bit_off;
  865. };
  866. /* struct sde_mdp_cfg : MDP TOP-BLK instance info
  867. * @id: index identifying this block
  868. * @base: register base offset to mdss
  869. * @features bit mask identifying sub-blocks/features
  870. * @highest_bank_bit: UBWC parameter
  871. * @ubwc_static: ubwc static configuration
  872. * @ubwc_swizzle: ubwc default swizzle setting
  873. * @has_dest_scaler: indicates support of destination scaler
  874. * @smart_panel_align_mode: split display smart panel align modes
  875. * @clk_ctrls clock control register definition
  876. * @clk_status clock status register definition
  877. */
  878. struct sde_mdp_cfg {
  879. SDE_HW_BLK_INFO;
  880. u32 highest_bank_bit;
  881. u32 ubwc_static;
  882. u32 ubwc_swizzle;
  883. bool has_dest_scaler;
  884. u32 smart_panel_align_mode;
  885. struct sde_clk_ctrl_reg clk_ctrls[SDE_CLK_CTRL_MAX];
  886. struct sde_clk_ctrl_reg clk_status[SDE_CLK_CTRL_MAX];
  887. };
  888. /* struct sde_uidle_cfg : MDP TOP-BLK instance info
  889. * @id: index identifying this block
  890. * @base: register base offset to mdss
  891. * @features: bit mask identifying sub-blocks/features
  892. * @fal10_exit_cnt: fal10 exit counter
  893. * @fal10_exit_danger: fal10 exit danger level
  894. * @fal10_danger: fal10 danger level
  895. * @fal10_target_idle_time: fal10 targeted time in uS
  896. * @fal1_target_idle_time: fal1 targeted time in uS
  897. * @fal10_threshold: fal10 threshold value
  898. * @max_downscale: maximum downscaling ratio x1000.
  899. * This ratio is multiplied x1000 to allow
  900. * 3 decimal precision digits.
  901. * @max_fps: maximum fps to allow micro idle
  902. * @uidle_rev: uidle revision supported by the target,
  903. * zero if no support
  904. * @debugfs_perf: enable/disable performance counters and status
  905. * logging
  906. * @debugfs_ctrl: uidle is enabled/disabled through debugfs
  907. * @perf_cntr_en: performance counters are enabled/disabled
  908. */
  909. struct sde_uidle_cfg {
  910. SDE_HW_BLK_INFO;
  911. /* global settings */
  912. u32 fal10_exit_cnt;
  913. u32 fal10_exit_danger;
  914. u32 fal10_danger;
  915. /* per-pipe settings */
  916. u32 fal10_target_idle_time;
  917. u32 fal1_target_idle_time;
  918. u32 fal10_threshold;
  919. u32 max_dwnscale;
  920. u32 max_fps;
  921. u32 uidle_rev;
  922. u32 debugfs_perf;
  923. bool debugfs_ctrl;
  924. bool perf_cntr_en;
  925. };
  926. /* struct sde_mdp_cfg : MDP TOP-BLK instance info
  927. * @id: index identifying this block
  928. * @base: register base offset to mdss
  929. * @features bit mask identifying sub-blocks/features
  930. */
  931. struct sde_ctl_cfg {
  932. SDE_HW_BLK_INFO;
  933. };
  934. /**
  935. * struct sde_sspp_cfg - information of source pipes
  936. * @id: index identifying this block
  937. * @base register offset of this block
  938. * @features bit mask identifying sub-blocks/features
  939. * @sblk: SSPP sub-blocks information
  940. * @xin_id: bus client identifier
  941. * @clk_ctrl clock control identifier
  942. * @type sspp type identifier
  943. */
  944. struct sde_sspp_cfg {
  945. SDE_HW_BLK_INFO;
  946. struct sde_sspp_sub_blks *sblk;
  947. u32 xin_id;
  948. enum sde_clk_ctrl_type clk_ctrl;
  949. u32 type;
  950. };
  951. /**
  952. * struct sde_lm_cfg - information of layer mixer blocks
  953. * @id: index identifying this block
  954. * @base register offset of this block
  955. * @features bit mask identifying sub-blocks/features
  956. * @sblk: LM Sub-blocks information
  957. * @dspp: ID of connected DSPP, DSPP_MAX if unsupported
  958. * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported
  959. * @ds: ID of connected DS, DS_MAX if unsupported
  960. * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
  961. */
  962. struct sde_lm_cfg {
  963. SDE_HW_BLK_INFO;
  964. struct sde_lm_sub_blks *sblk;
  965. u32 dspp;
  966. u32 pingpong;
  967. u32 ds;
  968. unsigned long lm_pair_mask;
  969. };
  970. /**
  971. * struct sde_dspp_cfg - information of DSPP top block
  972. * @id enum identifying this block
  973. * @base register offset of this block
  974. * @features bit mask identifying sub-blocks/features
  975. * supported by this block
  976. */
  977. struct sde_dspp_top_cfg {
  978. SDE_HW_BLK_INFO;
  979. };
  980. /**
  981. * struct sde_dspp_cfg - information of DSPP blocks
  982. * @id enum identifying this block
  983. * @base register offset of this block
  984. * @features bit mask identifying sub-blocks/features
  985. * supported by this block
  986. * @sblk sub-blocks information
  987. */
  988. struct sde_dspp_cfg {
  989. SDE_HW_BLK_INFO;
  990. struct sde_dspp_sub_blks *sblk;
  991. };
  992. /**
  993. * struct sde_ds_top_cfg - information of dest scaler top
  994. * @id enum identifying this block
  995. * @base register offset of this block
  996. * @features bit mask identifying features
  997. * @version hw version of dest scaler
  998. * @maxinputwidth maximum input line width
  999. * @maxoutputwidth maximum output line width
  1000. * @maxupscale maximum upscale ratio
  1001. */
  1002. struct sde_ds_top_cfg {
  1003. SDE_HW_BLK_INFO;
  1004. u32 version;
  1005. u32 maxinputwidth;
  1006. u32 maxoutputwidth;
  1007. u32 maxupscale;
  1008. };
  1009. /**
  1010. * struct sde_ds_cfg - information of dest scaler blocks
  1011. * @id enum identifying this block
  1012. * @base register offset wrt DS top offset
  1013. * @features bit mask identifying features
  1014. * @version hw version of the qseed block
  1015. * @top DS top information
  1016. */
  1017. struct sde_ds_cfg {
  1018. SDE_HW_BLK_INFO;
  1019. u32 version;
  1020. const struct sde_ds_top_cfg *top;
  1021. };
  1022. /**
  1023. * struct sde_pingpong_cfg - information of PING-PONG blocks
  1024. * @id enum identifying this block
  1025. * @base register offset of this block
  1026. * @features bit mask identifying sub-blocks/features
  1027. * @sblk sub-blocks information
  1028. * @merge_3d_id merge_3d block id
  1029. */
  1030. struct sde_pingpong_cfg {
  1031. SDE_HW_BLK_INFO;
  1032. const struct sde_pingpong_sub_blks *sblk;
  1033. int merge_3d_id;
  1034. };
  1035. /**
  1036. * struct sde_dsc_cfg - information of DSC blocks
  1037. * @id enum identifying this block
  1038. * @base register offset of this block
  1039. * @len: length of hardware block
  1040. * @features bit mask identifying sub-blocks/features
  1041. * @dsc_pair_mask: Bitmask of DSCs that can be controlled by same CTL
  1042. */
  1043. struct sde_dsc_cfg {
  1044. SDE_HW_BLK_INFO;
  1045. DECLARE_BITMAP(dsc_pair_mask, DSC_MAX);
  1046. struct sde_dsc_sub_blks *sblk;
  1047. };
  1048. /**
  1049. * struct sde_vdc_cfg - information of VDC blocks
  1050. * @id enum identifying this block
  1051. * @base register offset of this block
  1052. * @len: length of hardware block
  1053. * @features bit mask identifying sub-blocks/features
  1054. * @enc VDC encoder register offset(relative to VDC base)
  1055. * @ctl VDC Control register offset(relative to VDC base)
  1056. */
  1057. struct sde_vdc_cfg {
  1058. SDE_HW_BLK_INFO;
  1059. struct sde_vdc_sub_blks *sblk;
  1060. };
  1061. /**
  1062. * struct sde_cdm_cfg - information of chroma down blocks
  1063. * @id enum identifying this block
  1064. * @base register offset of this block
  1065. * @features bit mask identifying sub-blocks/features
  1066. * @intf_connect Bitmask of INTF IDs this CDM can connect to
  1067. * @wb_connect: Bitmask of Writeback IDs this CDM can connect to
  1068. */
  1069. struct sde_cdm_cfg {
  1070. SDE_HW_BLK_INFO;
  1071. unsigned long intf_connect;
  1072. unsigned long wb_connect;
  1073. };
  1074. /**
  1075. * struct sde_intf_cfg - information of timing engine blocks
  1076. * @id enum identifying this block
  1077. * @base register offset of this block
  1078. * @features bit mask identifying sub-blocks/features
  1079. * @type: Interface type(DSI, DP, HDMI)
  1080. * @controller_id: Controller Instance ID in case of multiple of intf type
  1081. * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
  1082. * @te_irq_offset: Register offset for INTF TE IRQ block
  1083. */
  1084. struct sde_intf_cfg {
  1085. SDE_HW_BLK_INFO;
  1086. u32 type; /* interface type*/
  1087. u32 controller_id;
  1088. u32 prog_fetch_lines_worst_case;
  1089. u32 te_irq_offset;
  1090. };
  1091. /**
  1092. * struct sde_wb_cfg - information of writeback blocks
  1093. * @id enum identifying this block
  1094. * @base register offset of this block
  1095. * @features bit mask identifying sub-blocks/features
  1096. * @sblk sub-block information
  1097. * @format_list: Pointer to list of supported formats
  1098. * @vbif_idx vbif identifier
  1099. * @xin_id client interface identifier
  1100. * @clk_ctrl clock control identifier
  1101. */
  1102. struct sde_wb_cfg {
  1103. SDE_HW_BLK_INFO;
  1104. const struct sde_wb_sub_blocks *sblk;
  1105. const struct sde_format_extended *format_list;
  1106. u32 vbif_idx;
  1107. u32 xin_id;
  1108. enum sde_clk_ctrl_type clk_ctrl;
  1109. };
  1110. /**
  1111. * struct sde_merge_3d_cfg - information of merge_3d blocks
  1112. * @id enum identifying this block
  1113. * @base register offset of this block
  1114. * @len: length of hardware block
  1115. * @features bit mask identifying sub-blocks/features
  1116. */
  1117. struct sde_merge_3d_cfg {
  1118. SDE_HW_BLK_INFO;
  1119. };
  1120. /**
  1121. * struct sde_qdss_cfg - information of qdss blocks
  1122. * @id enum identifying this block
  1123. * @base register offset of this block
  1124. * @len: length of hardware block
  1125. * @features bit mask identifying sub-blocks/features
  1126. */
  1127. struct sde_qdss_cfg {
  1128. SDE_HW_BLK_INFO;
  1129. };
  1130. /*
  1131. * struct sde_vbif_dynamic_ot_cfg - dynamic OT setting
  1132. * @pps pixel per seconds
  1133. * @ot_limit OT limit to use up to specified pixel per second
  1134. */
  1135. struct sde_vbif_dynamic_ot_cfg {
  1136. u64 pps;
  1137. u32 ot_limit;
  1138. };
  1139. /**
  1140. * struct sde_vbif_dynamic_ot_tbl - dynamic OT setting table
  1141. * @count length of cfg
  1142. * @cfg pointer to array of configuration settings with
  1143. * ascending requirements
  1144. */
  1145. struct sde_vbif_dynamic_ot_tbl {
  1146. u32 count;
  1147. struct sde_vbif_dynamic_ot_cfg *cfg;
  1148. };
  1149. /**
  1150. * struct sde_vbif_qos_tbl - QoS priority table
  1151. * @npriority_lvl num of priority level
  1152. * @priority_lvl pointer to array of priority level in ascending order
  1153. */
  1154. struct sde_vbif_qos_tbl {
  1155. u32 npriority_lvl;
  1156. u32 *priority_lvl;
  1157. };
  1158. /**
  1159. * enum sde_vbif_client_type
  1160. * @VBIF_RT_CLIENT: real time client
  1161. * @VBIF_NRT_CLIENT: non-realtime clients like writeback
  1162. * @VBIF_CWB_CLIENT: concurrent writeback client
  1163. * @VBIF_LUTDMA_CLIENT: LUTDMA client
  1164. * @VBIF_MAX_CLIENT: max number of clients
  1165. */
  1166. enum sde_vbif_client_type {
  1167. VBIF_RT_CLIENT,
  1168. VBIF_NRT_CLIENT,
  1169. VBIF_CWB_CLIENT,
  1170. VBIF_LUTDMA_CLIENT,
  1171. VBIF_MAX_CLIENT
  1172. };
  1173. /**
  1174. * struct sde_vbif_cfg - information of VBIF blocks
  1175. * @id enum identifying this block
  1176. * @base register offset of this block
  1177. * @features bit mask identifying sub-blocks/features
  1178. * @ot_rd_limit default OT read limit
  1179. * @ot_wr_limit default OT write limit
  1180. * @xin_halt_timeout maximum time (in usec) for xin to halt
  1181. * @dynamic_ot_rd_tbl dynamic OT read configuration table
  1182. * @dynamic_ot_wr_tbl dynamic OT write configuration table
  1183. * @qos_tbl Array of QoS priority table
  1184. * @memtype_count number of defined memtypes
  1185. * @memtype array of xin memtype definitions
  1186. */
  1187. struct sde_vbif_cfg {
  1188. SDE_HW_BLK_INFO;
  1189. u32 default_ot_rd_limit;
  1190. u32 default_ot_wr_limit;
  1191. u32 xin_halt_timeout;
  1192. struct sde_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
  1193. struct sde_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
  1194. struct sde_vbif_qos_tbl qos_tbl[VBIF_MAX_CLIENT];
  1195. u32 memtype_count;
  1196. u32 memtype[MAX_XIN_COUNT];
  1197. };
  1198. /**
  1199. * enum sde_reg_dma_type - defines reg dma block type
  1200. * @REG_DMA_TYPE_DB: DB LUT DMA block
  1201. * @REG_DMA_TYPE_SB: SB LUT DMA block
  1202. * @REG_DMA_TYPE_MAX: invalid selection
  1203. */
  1204. enum sde_reg_dma_type {
  1205. REG_DMA_TYPE_DB,
  1206. REG_DMA_TYPE_SB,
  1207. REG_DMA_TYPE_MAX,
  1208. };
  1209. /**
  1210. * struct sde_reg_dma_blk_info - definition of lut dma block.
  1211. * @valid bool indicating if the definiton is valid.
  1212. * @base register offset of this block.
  1213. * @features bit mask identifying sub-blocks/features.
  1214. */
  1215. struct sde_reg_dma_blk_info {
  1216. bool valid;
  1217. u32 base;
  1218. u32 features;
  1219. };
  1220. /**
  1221. * struct sde_reg_dma_cfg - overall config struct of lut dma blocks.
  1222. * @reg_dma_blks Reg DMA blk info for each possible block type
  1223. * @version version of lutdma hw blocks
  1224. * @trigger_sel_off offset to trigger select registers of lutdma
  1225. * @broadcast_disabled flag indicating if broadcast usage should be avoided
  1226. * @xin_id VBIF xin client-id for LUTDMA
  1227. * @vbif_idx VBIF id (RT/NRT)
  1228. * @clk_ctrl VBIF xin client clk-ctrl
  1229. */
  1230. struct sde_reg_dma_cfg {
  1231. struct sde_reg_dma_blk_info reg_dma_blks[REG_DMA_TYPE_MAX];
  1232. u32 version;
  1233. u32 trigger_sel_off;
  1234. u32 broadcast_disabled;
  1235. u32 xin_id;
  1236. u32 vbif_idx;
  1237. enum sde_clk_ctrl_type clk_ctrl;
  1238. };
  1239. /**
  1240. * Define CDP use cases
  1241. * @SDE_PERF_CDP_UDAGE_RT: real-time use cases
  1242. * @SDE_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD
  1243. */
  1244. enum {
  1245. SDE_PERF_CDP_USAGE_RT,
  1246. SDE_PERF_CDP_USAGE_NRT,
  1247. SDE_PERF_CDP_USAGE_MAX
  1248. };
  1249. /**
  1250. * struct sde_perf_cdp_cfg - define CDP use case configuration
  1251. * @rd_enable: true if read pipe CDP is enabled
  1252. * @wr_enable: true if write pipe CDP is enabled
  1253. */
  1254. struct sde_perf_cdp_cfg {
  1255. bool rd_enable;
  1256. bool wr_enable;
  1257. };
  1258. /**
  1259. * struct sde_sc_cfg - define system cache configuration
  1260. * @has_sys_cache: true if system cache is enabled
  1261. * @llcc_scid: scid for the system cache
  1262. * @llcc_slice_size: slice size of the system cache
  1263. */
  1264. struct sde_sc_cfg {
  1265. bool has_sys_cache;
  1266. int llcc_scid;
  1267. size_t llcc_slice_size;
  1268. };
  1269. /**
  1270. * struct sde_perf_cfg - performance control settings
  1271. * @max_bw_low low threshold of maximum bandwidth (kbps)
  1272. * @max_bw_high high threshold of maximum bandwidth (kbps)
  1273. * @min_core_ib minimum bandwidth for core (kbps)
  1274. * @min_core_ib minimum mnoc ib vote in kbps
  1275. * @min_llcc_ib minimum llcc ib vote in kbps
  1276. * @min_dram_ib minimum dram ib vote in kbps
  1277. * @core_ib_ff core instantaneous bandwidth fudge factor
  1278. * @core_clk_ff core clock fudge factor
  1279. * @comp_ratio_rt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
  1280. * @comp_ratio_nrt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
  1281. * @undersized_prefill_lines undersized prefill in lines
  1282. * @xtra_prefill_lines extra prefill latency in lines
  1283. * @dest_scale_prefill_lines destination scaler latency in lines
  1284. * @macrotile_perfill_lines macrotile latency in lines
  1285. * @yuv_nv12_prefill_lines yuv_nv12 latency in lines
  1286. * @linear_prefill_lines linear latency in lines
  1287. * @downscaling_prefill_lines downscaling latency in lines
  1288. * @amortizable_theshold minimum y position for traffic shaping prefill
  1289. * @min_prefill_lines minimum pipeline latency in lines
  1290. * @danger_lut: liner, linear_qseed, macrotile, etc. danger luts
  1291. * @sfe_lut: linear, macrotile, macrotile_qseed, etc. safe luts
  1292. * @creq_lut: linear, macrotile, non_realtime, cwb, etc. creq luts
  1293. * @qos_refresh_count: total refresh count for possible different luts
  1294. * @qos_refresh_rate: different refresh rates for luts
  1295. * @cdp_cfg cdp use case configurations
  1296. * @cpu_mask: pm_qos cpu mask value
  1297. * @cpu_mask_perf: pm_qos cpu silver core mask value
  1298. * @cpu_dma_latency: pm_qos cpu dma latency value
  1299. * @cpu_irq_latency: pm_qos cpu irq latency value
  1300. * @axi_bus_width: axi bus width value in bytes
  1301. * @num_mnoc_ports: number of mnoc ports
  1302. */
  1303. struct sde_perf_cfg {
  1304. u32 max_bw_low;
  1305. u32 max_bw_high;
  1306. u32 min_core_ib;
  1307. u32 min_llcc_ib;
  1308. u32 min_dram_ib;
  1309. const char *core_ib_ff;
  1310. const char *core_clk_ff;
  1311. const char *comp_ratio_rt;
  1312. const char *comp_ratio_nrt;
  1313. u32 undersized_prefill_lines;
  1314. u32 xtra_prefill_lines;
  1315. u32 dest_scale_prefill_lines;
  1316. u32 macrotile_prefill_lines;
  1317. u32 yuv_nv12_prefill_lines;
  1318. u32 linear_prefill_lines;
  1319. u32 downscaling_prefill_lines;
  1320. u32 amortizable_threshold;
  1321. u32 min_prefill_lines;
  1322. u64 *danger_lut;
  1323. u64 *safe_lut;
  1324. u64 *creq_lut;
  1325. u32 qos_refresh_count;
  1326. u32 *qos_refresh_rate;
  1327. struct sde_perf_cdp_cfg cdp_cfg[SDE_PERF_CDP_USAGE_MAX];
  1328. unsigned long cpu_mask;
  1329. unsigned long cpu_mask_perf;
  1330. u32 cpu_dma_latency;
  1331. u32 cpu_irq_latency;
  1332. u32 axi_bus_width;
  1333. u32 num_mnoc_ports;
  1334. };
  1335. /**
  1336. * struct sde_mdss_cfg - information of MDSS HW
  1337. * This is the main catalog data structure representing
  1338. * this HW version. Contains number of instances,
  1339. * register offsets, capabilities of the all MDSS HW sub-blocks.
  1340. *
  1341. * @trusted_vm_env set to true, if the driver is executing in
  1342. * the trusted VM. false, otherwise.
  1343. * @max_trusted_vm_displays maximum number of concurrent trusted
  1344. * vm displays supported.
  1345. * @max_sspp_linewidth max source pipe line width support.
  1346. * @vig_sspp_linewidth max vig source pipe line width support.
  1347. * @scaling_linewidth max vig source pipe linewidth for scaling usecases
  1348. * @max_mixer_width max layer mixer line width support.
  1349. * @max_dsc_width max dsc line width support.
  1350. * @max_mixer_blendstages max layer mixer blend stages or
  1351. * supported z order
  1352. * @max_wb_linewidth max writeback line width support.
  1353. * @max_wb_linewidth_linear max writeback line width for linear formats.
  1354. * @max_display_width maximum display width support.
  1355. * @max_display_height maximum display height support.
  1356. * @min_display_width minimum display width support.
  1357. * @min_display_height minimum display height support.
  1358. * @csc_type csc or csc_10bit support.
  1359. * @smart_dma_rev Supported version of SmartDMA feature.
  1360. * @ctl_rev supported version of control path.
  1361. * @has_src_split source split feature status
  1362. * @has_cdp Client driven prefetch feature status
  1363. * @has_wb_ubwc UBWC feature supported on WB
  1364. * @has_cwb_crop CWB cropping is supported
  1365. * @has_cwb_support indicates if device supports primary capture through CWB
  1366. * @has_dedicated_cwb_support indicates if device supports dedicated path for CWB capture
  1367. * @cwb_blk_off CWB offset address
  1368. * @cwb_blk_stride offset between each CWB blk
  1369. * @ubwc_version UBWC feature version (0x0 for not supported)
  1370. * @ubwc_bw_calc_version indicate how UBWC BW has to be calculated
  1371. * @has_idle_pc indicate if idle power collapse feature is supported
  1372. * @wakeup_with_touch indicate early wake up display with input touch event
  1373. * @has_hdr HDR feature support
  1374. * @has_hdr_plus HDR10+ feature support
  1375. * @dma_formats Supported formats for dma pipe
  1376. * @cursor_formats Supported formats for cursor pipe
  1377. * @vig_formats Supported formats for vig pipe
  1378. * @wb_formats Supported formats for wb
  1379. * @virt_vig_formats Supported formats for virtual vig pipe
  1380. * @vbif_qos_nlvl number of vbif QoS priority level
  1381. * @ts_prefill_rev prefill traffic shaper feature revision
  1382. * @true_inline_rot_rev inline rotator feature revision
  1383. * @macrotile_mode UBWC parameter for macro tile channel distribution
  1384. * @pipe_order_type indicate if it is required to specify pipe order
  1385. * @sspp_multirect_error flag to indicate whether ubwc and meta error by rect is supported
  1386. * @delay_prg_fetch_start indicates if throttling the fetch start is required
  1387. * @has_qsync Supports qsync feature
  1388. * @has_3d_merge_reset Supports 3D merge reset
  1389. * @has_decimation Supports decimation
  1390. * @has_trusted_vm_support Supported HW sharing with trusted VM
  1391. * @rc_lm_flush_override Support Rounded Corner using layer mixer flush
  1392. * @has_mixer_combined_alpha Mixer has single register for FG & BG alpha
  1393. * @vbif_disable_inner_outer_shareable VBIF requires disabling shareables
  1394. * @inline_disable_const_clr Disable constant color during inline rotate
  1395. * @dither_luma_mode_support Enables dither luma mode
  1396. * @has_base_layer Supports staging layer as base layer
  1397. * @demura_supported Demura pipe support flag(~0x00 - Not supported)
  1398. * @qseed_sw_lib_rev qseed sw library type supporting the qseed hw
  1399. * @qseed_hw_version qseed hw version of the target
  1400. * @sc_cfg: system cache configuration
  1401. * @syscache_supported Flag to indicate if sys cache support is enabled
  1402. * @uidle_cfg Settings for uidle feature
  1403. * @sui_misr_supported indicate if secure-ui-misr is supported
  1404. * @sui_block_xin_mask mask of all the xin-clients to be blocked during
  1405. * secure-ui when secure-ui-misr feature is supported
  1406. * @sec_sid_mask_count number of SID masks
  1407. * @sec_sid_mask SID masks used during the scm_call for transition
  1408. * between secure/non-secure sessions
  1409. * @sui_ns_allowed flag to indicate non-secure context banks are allowed
  1410. * during secure-ui session
  1411. * @sui_supported_blendstage secure-ui supported blendstage
  1412. * @has_sui_blendstage flag to indicate secure-ui has a blendstage restriction
  1413. * @has_cursor indicates if hardware cursor is supported
  1414. * @has_vig_p010 indicates if vig pipe supports p010 format
  1415. * @has_fp16 indicates if FP16 format is supported on SSPP pipes
  1416. * @has_precise_vsync_ts indicates if HW has vsyc timestamp logging capability
  1417. * @mdss_hw_block_size Max offset of MDSS_HW block (0 offset), used for debug
  1418. * @inline_rot_formats formats supported by the inline rotator feature
  1419. * @irq_offset_list list of sde_intr_irq_offsets to initialize irq table
  1420. * @rc_count number of rounded corner hardware instances
  1421. * @demura_count number of demura hardware instances
  1422. * @dcwb_count number of dcwb hardware instances
  1423. */
  1424. struct sde_mdss_cfg {
  1425. u32 hwversion;
  1426. bool trusted_vm_env;
  1427. u32 max_trusted_vm_displays;
  1428. u32 max_sspp_linewidth;
  1429. u32 vig_sspp_linewidth;
  1430. u32 scaling_linewidth;
  1431. u32 max_mixer_width;
  1432. u32 max_dsc_width;
  1433. u32 max_mixer_blendstages;
  1434. u32 max_wb_linewidth;
  1435. u32 max_wb_linewidth_linear;
  1436. u32 max_display_width;
  1437. u32 max_display_height;
  1438. u32 min_display_width;
  1439. u32 min_display_height;
  1440. u32 csc_type;
  1441. u32 smart_dma_rev;
  1442. u32 ctl_rev;
  1443. bool has_src_split;
  1444. bool has_cdp;
  1445. bool has_dim_layer;
  1446. bool has_wb_ubwc;
  1447. bool has_cwb_crop;
  1448. bool has_cwb_support;
  1449. bool has_dedicated_cwb_support;
  1450. u32 cwb_blk_off;
  1451. u32 cwb_blk_stride;
  1452. u32 ubwc_version;
  1453. u32 ubwc_bw_calc_version;
  1454. bool has_idle_pc;
  1455. bool wakeup_with_touch;
  1456. u32 vbif_qos_nlvl;
  1457. u32 ts_prefill_rev;
  1458. u32 true_inline_rot_rev;
  1459. u32 macrotile_mode;
  1460. u32 pipe_order_type;
  1461. bool sspp_multirect_error;
  1462. bool delay_prg_fetch_start;
  1463. bool has_qsync;
  1464. bool has_3d_merge_reset;
  1465. bool has_decimation;
  1466. bool has_mixer_combined_alpha;
  1467. bool vbif_disable_inner_outer_shareable;
  1468. bool inline_disable_const_clr;
  1469. bool dither_luma_mode_support;
  1470. bool has_base_layer;
  1471. bool has_demura;
  1472. bool has_trusted_vm_support;
  1473. bool rc_lm_flush_override;
  1474. u32 demura_supported[SSPP_MAX][2];
  1475. u32 qseed_sw_lib_rev;
  1476. u32 qseed_hw_version;
  1477. struct sde_sc_cfg sc_cfg[SDE_SYS_CACHE_MAX];
  1478. bool syscache_supported;
  1479. bool sui_misr_supported;
  1480. u32 sui_block_xin_mask;
  1481. u32 sec_sid_mask_count;
  1482. u32 sec_sid_mask[MAX_BLOCKS];
  1483. u32 sui_ns_allowed;
  1484. u32 sui_supported_blendstage;
  1485. bool has_sui_blendstage;
  1486. bool has_hdr;
  1487. bool has_hdr_plus;
  1488. bool has_cursor;
  1489. bool has_vig_p010;
  1490. bool has_fp16;
  1491. bool has_precise_vsync_ts;
  1492. u32 mdss_hw_block_size;
  1493. u32 mdss_count;
  1494. struct sde_mdss_base_cfg mdss[MAX_BLOCKS];
  1495. u32 mdp_count;
  1496. struct sde_mdp_cfg mdp[MAX_BLOCKS];
  1497. /* uidle is a singleton */
  1498. struct sde_uidle_cfg uidle_cfg;
  1499. u32 ctl_count;
  1500. struct sde_ctl_cfg ctl[MAX_BLOCKS];
  1501. u32 sspp_count;
  1502. struct sde_sspp_cfg sspp[MAX_BLOCKS];
  1503. u32 mixer_count;
  1504. struct sde_lm_cfg mixer[MAX_BLOCKS];
  1505. struct sde_dspp_top_cfg dspp_top;
  1506. u32 dspp_count;
  1507. struct sde_dspp_cfg dspp[MAX_BLOCKS];
  1508. u32 ds_count;
  1509. struct sde_ds_cfg ds[MAX_BLOCKS];
  1510. u32 pingpong_count;
  1511. struct sde_pingpong_cfg pingpong[MAX_BLOCKS];
  1512. u32 dsc_count;
  1513. struct sde_dsc_cfg dsc[MAX_BLOCKS];
  1514. u32 vdc_count;
  1515. struct sde_vdc_cfg vdc[MAX_BLOCKS];
  1516. u32 cdm_count;
  1517. struct sde_cdm_cfg cdm[MAX_BLOCKS];
  1518. u32 intf_count;
  1519. struct sde_intf_cfg intf[MAX_BLOCKS];
  1520. u32 wb_count;
  1521. struct sde_wb_cfg wb[MAX_BLOCKS];
  1522. u32 vbif_count;
  1523. struct sde_vbif_cfg vbif[MAX_BLOCKS];
  1524. u32 reg_dma_count;
  1525. struct sde_reg_dma_cfg dma_cfg;
  1526. u32 ad_count;
  1527. u32 ltm_count;
  1528. u32 rc_count;
  1529. u32 spr_count;
  1530. u32 demura_count;
  1531. u32 merge_3d_count;
  1532. struct sde_merge_3d_cfg merge_3d[MAX_BLOCKS];
  1533. u32 qdss_count;
  1534. struct sde_qdss_cfg qdss[MAX_BLOCKS];
  1535. u32 dcwb_count;
  1536. /* Add additional block data structures here */
  1537. struct sde_perf_cfg perf;
  1538. struct sde_format_extended *dma_formats;
  1539. struct sde_format_extended *cursor_formats;
  1540. struct sde_format_extended *vig_formats;
  1541. struct sde_format_extended *wb_formats;
  1542. struct sde_format_extended *virt_vig_formats;
  1543. struct sde_format_extended *inline_rot_formats;
  1544. struct list_head irq_offset_list;
  1545. };
  1546. struct sde_mdss_hw_cfg_handler {
  1547. u32 major;
  1548. u32 minor;
  1549. struct sde_mdss_cfg* (*cfg_init)(u32 data);
  1550. };
  1551. /*
  1552. * Access Macros
  1553. */
  1554. #define BLK_MDP(s) ((s)->mdp)
  1555. #define BLK_CTL(s) ((s)->ctl)
  1556. #define BLK_VIG(s) ((s)->vig)
  1557. #define BLK_RGB(s) ((s)->rgb)
  1558. #define BLK_DMA(s) ((s)->dma)
  1559. #define BLK_CURSOR(s) ((s)->cursor)
  1560. #define BLK_MIXER(s) ((s)->mixer)
  1561. #define BLK_DSPP(s) ((s)->dspp)
  1562. #define BLK_DS(s) ((s)->ds)
  1563. #define BLK_PINGPONG(s) ((s)->pingpong)
  1564. #define BLK_CDM(s) ((s)->cdm)
  1565. #define BLK_INTF(s) ((s)->intf)
  1566. #define BLK_WB(s) ((s)->wb)
  1567. #define BLK_AD(s) ((s)->ad)
  1568. #define BLK_LTM(s) ((s)->ltm)
  1569. #define BLK_RC(s) ((s)->rc)
  1570. /**
  1571. * sde_hw_set_preference: populate the individual hw lm preferences,
  1572. * overwrite if exists
  1573. * @sde_cfg: pointer to sspp cfg
  1574. * @num_lm: num lms to set preference
  1575. * @disp_type: is the given display primary/secondary
  1576. */
  1577. void sde_hw_mixer_set_preference(struct sde_mdss_cfg *sde_cfg, u32 num_lm,
  1578. uint32_t disp_type);
  1579. /**
  1580. * sde_hw_catalog_init - sde hardware catalog init API parses dtsi property
  1581. * and stores all parsed offset, hardware capabilities in config structure.
  1582. * @dev: drm device node.
  1583. *
  1584. * Return: parsed sde config structure
  1585. */
  1586. struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev);
  1587. /**
  1588. * sde_hw_catalog_deinit - sde hardware catalog cleanup
  1589. * @sde_cfg: pointer returned from init function
  1590. */
  1591. void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg);
  1592. /**
  1593. * sde_hw_catalog_irq_offset_list_delete - delete the irq_offset_list
  1594. * maintained by the catalog
  1595. * @head: pointer to the catalog's irq_offset_list
  1596. */
  1597. static inline void sde_hw_catalog_irq_offset_list_delete(
  1598. struct list_head *head)
  1599. {
  1600. struct sde_intr_irq_offsets *item, *tmp;
  1601. list_for_each_entry_safe(item, tmp, head, list) {
  1602. list_del(&item->list);
  1603. kfree(item);
  1604. }
  1605. }
  1606. /**
  1607. * sde_hw_sspp_multirect_enabled - check multirect enabled for the sspp
  1608. * @cfg: pointer to sspp cfg
  1609. */
  1610. static inline bool sde_hw_sspp_multirect_enabled(const struct sde_sspp_cfg *cfg)
  1611. {
  1612. return test_bit(SDE_SSPP_SMART_DMA_V1, &cfg->features) ||
  1613. test_bit(SDE_SSPP_SMART_DMA_V2, &cfg->features) ||
  1614. test_bit(SDE_SSPP_SMART_DMA_V2p5, &cfg->features);
  1615. }
  1616. #endif /* _SDE_HW_CATALOG_H */