dsi_phy_timing_v3_0.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include "dsi_phy_timing_calc.h"
  6. void dsi_phy_hw_v3_0_get_default_phy_params(
  7. struct phy_clk_params *params, u32 phy_type)
  8. {
  9. params->clk_prep_buf = 0;
  10. params->clk_zero_buf = 0;
  11. params->clk_trail_buf = 0;
  12. params->hs_prep_buf = 0;
  13. params->hs_zero_buf = 0;
  14. params->hs_trail_buf = 0;
  15. params->hs_rqst_buf = 0;
  16. params->hs_exit_buf = 0;
  17. }
  18. int32_t dsi_phy_hw_v3_0_calc_clk_zero(s64 rec_temp1, s64 mult)
  19. {
  20. s64 rec_temp2, rec_temp3;
  21. rec_temp2 = (rec_temp1 - mult);
  22. rec_temp3 = roundup64(div_s64(rec_temp2, 8), mult);
  23. return (div_s64(rec_temp3, mult) - 1);
  24. }
  25. int32_t dsi_phy_hw_v3_0_calc_clk_trail_rec_min(s64 temp_mul,
  26. s64 frac, s64 mult)
  27. {
  28. s64 rec_temp1, rec_temp2, rec_temp3;
  29. rec_temp1 = temp_mul + frac;
  30. rec_temp2 = div_s64(rec_temp1, 8);
  31. rec_temp3 = roundup64(rec_temp2, mult);
  32. return (div_s64(rec_temp3, mult) - 1);
  33. }
  34. int32_t dsi_phy_hw_v3_0_calc_clk_trail_rec_max(s64 temp1, s64 mult)
  35. {
  36. s64 rec_temp2;
  37. rec_temp2 = temp1 / 8;
  38. return (div_s64(rec_temp2, mult) - 1);
  39. }
  40. int32_t dsi_phy_hw_v3_0_calc_hs_zero(s64 temp1, s64 mult)
  41. {
  42. s64 rec_temp2, rec_min;
  43. rec_temp2 = roundup64((temp1 / 8), mult);
  44. rec_min = rec_temp2 - (1 * mult);
  45. return div_s64(rec_min, mult);
  46. }
  47. void dsi_phy_hw_v3_0_calc_hs_trail(struct phy_clk_params *clk_params,
  48. struct phy_timing_desc *desc)
  49. {
  50. s64 rec_temp1;
  51. struct timing_entry *t = &desc->hs_trail;
  52. t->rec_min = DIV_ROUND_UP(
  53. (t->mipi_min * clk_params->bitclk_mbps),
  54. (8 * clk_params->tlpx_numer_ns)) - 1;
  55. rec_temp1 = (t->mipi_max * clk_params->bitclk_mbps);
  56. t->rec_max =
  57. (div_s64(rec_temp1, (8 * clk_params->tlpx_numer_ns))) - 1;
  58. }
  59. void dsi_phy_hw_v3_0_update_timing_params(
  60. struct dsi_phy_per_lane_cfgs *timing,
  61. struct phy_timing_desc *desc, u32 phy_type)
  62. {
  63. timing->lane_v3[0] = 0x00;
  64. timing->lane_v3[1] = desc->clk_zero.reg_value;
  65. timing->lane_v3[2] = desc->clk_prepare.reg_value;
  66. timing->lane_v3[3] = desc->clk_trail.reg_value;
  67. timing->lane_v3[4] = desc->hs_exit.reg_value;
  68. timing->lane_v3[5] = desc->hs_zero.reg_value;
  69. timing->lane_v3[6] = desc->hs_prepare.reg_value;
  70. timing->lane_v3[7] = desc->hs_trail.reg_value;
  71. timing->lane_v3[8] = desc->hs_rqst.reg_value;
  72. timing->lane_v3[9] = 0x02;
  73. timing->lane_v3[10] = 0x04;
  74. timing->lane_v3[11] = 0x00;
  75. DSI_DEBUG("[%d %d %d %d]\n", timing->lane_v3[0],
  76. timing->lane_v3[1], timing->lane_v3[2], timing->lane_v3[3]);
  77. DSI_DEBUG("[%d %d %d %d]\n", timing->lane_v3[4],
  78. timing->lane_v3[5], timing->lane_v3[6], timing->lane_v3[7]);
  79. DSI_DEBUG("[%d %d %d %d]\n", timing->lane_v3[8],
  80. timing->lane_v3[9], timing->lane_v3[10], timing->lane_v3[11]);
  81. timing->count_per_lane = 12;
  82. }