cam_cpas_hw.c 114 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/device.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/of.h>
  9. #include <linux/pm_opp.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include "cam_cpas_hw.h"
  13. #include "cam_cpas_hw_intf.h"
  14. #include "cam_cpas_soc.h"
  15. #include "cam_req_mgr_dev.h"
  16. #include "cam_smmu_api.h"
  17. #include "cam_compat.h"
  18. #include "cam_cpastop_hw.h"
  19. #define CAM_CPAS_LOG_BUF_LEN 512
  20. #define CAM_CPAS_APPLY_TYPE_START 1
  21. #define CAM_CPAS_APPLY_TYPE_STOP 2
  22. #define CAM_CPAS_APPLY_TYPE_UPDATE 3
  23. static uint cam_min_camnoc_ib_bw;
  24. module_param(cam_min_camnoc_ib_bw, uint, 0644);
  25. static void cam_cpas_update_monitor_array(struct cam_hw_info *cpas_hw,
  26. const char *identifier_string, int32_t identifier_value);
  27. static void cam_cpas_dump_monitor_array(
  28. struct cam_hw_info *cpas_hw);
  29. static void cam_cpas_process_drv_bw_overrides(
  30. struct cam_cpas_bus_client *bus_client, uint64_t *high_ab, uint64_t *high_ib,
  31. uint64_t *low_ab, uint64_t *low_ib, const struct cam_cpas_debug_settings *cpas_settings)
  32. {
  33. uint64_t curr_ab_high = *high_ab;
  34. uint64_t curr_ib_high = *high_ib;
  35. uint64_t curr_ab_low = *low_ab;
  36. uint64_t curr_ib_low = *low_ib;
  37. size_t name_len = strlen(bus_client->common_data.name);
  38. if (!cpas_settings) {
  39. CAM_ERR(CAM_CPAS, "Invalid cpas debug settings");
  40. return;
  41. }
  42. if (strnstr(bus_client->common_data.name, "cam_ife_0_drv",
  43. name_len)) {
  44. if (cpas_settings->cam_ife_0_drv_ab_high_bw)
  45. *high_ab = cpas_settings->cam_ife_0_drv_ab_high_bw;
  46. if (cpas_settings->cam_ife_0_drv_ib_high_bw)
  47. *high_ib = cpas_settings->cam_ife_0_drv_ib_high_bw;
  48. if (cpas_settings->cam_ife_0_drv_ab_low_bw)
  49. *low_ab = cpas_settings->cam_ife_0_drv_ab_low_bw;
  50. if (cpas_settings->cam_ife_0_drv_ib_low_bw)
  51. *low_ib = cpas_settings->cam_ife_0_drv_ib_low_bw;
  52. if (cpas_settings->cam_ife_0_drv_low_set_zero) {
  53. *low_ab = 0;
  54. *low_ib = 0;
  55. }
  56. } else if (strnstr(bus_client->common_data.name, "cam_ife_1_drv",
  57. name_len)) {
  58. if (cpas_settings->cam_ife_1_drv_ab_high_bw)
  59. *high_ab = cpas_settings->cam_ife_1_drv_ab_high_bw;
  60. if (cpas_settings->cam_ife_1_drv_ib_high_bw)
  61. *high_ib = cpas_settings->cam_ife_1_drv_ib_high_bw;
  62. if (cpas_settings->cam_ife_1_drv_ab_low_bw)
  63. *low_ab = cpas_settings->cam_ife_1_drv_ab_low_bw;
  64. if (cpas_settings->cam_ife_1_drv_ib_low_bw)
  65. *low_ib = cpas_settings->cam_ife_1_drv_ib_low_bw;
  66. if (cpas_settings->cam_ife_1_drv_low_set_zero) {
  67. *low_ab = 0;
  68. *low_ib = 0;
  69. }
  70. } else if (strnstr(bus_client->common_data.name, "cam_ife_2_drv",
  71. name_len)) {
  72. if (cpas_settings->cam_ife_2_drv_ab_high_bw)
  73. *high_ab = cpas_settings->cam_ife_2_drv_ab_high_bw;
  74. if (cpas_settings->cam_ife_2_drv_ib_high_bw)
  75. *high_ib = cpas_settings->cam_ife_2_drv_ib_high_bw;
  76. if (cpas_settings->cam_ife_2_drv_ab_low_bw)
  77. *low_ab = cpas_settings->cam_ife_2_drv_ab_low_bw;
  78. if (cpas_settings->cam_ife_2_drv_ib_low_bw)
  79. *low_ib = cpas_settings->cam_ife_2_drv_ib_low_bw;
  80. if (cpas_settings->cam_ife_2_drv_low_set_zero) {
  81. *low_ab = 0;
  82. *low_ib = 0;
  83. }
  84. } else {
  85. CAM_ERR(CAM_CPAS, "unknown mnoc port: %s, bw override failed",
  86. bus_client->common_data.name);
  87. return;
  88. }
  89. CAM_INFO(CAM_CPAS,
  90. "Overriding mnoc bw for: %s with [AB IB] high: [%llu %llu], low: [%llu %llu], curr high: [%llu %llu], curr low: [%llu %llu]",
  91. bus_client->common_data.name, *high_ab, *high_ib, *low_ab, *low_ib,
  92. curr_ab_high, curr_ib_high, curr_ab_low, curr_ib_low);
  93. }
  94. static void cam_cpas_process_bw_overrides(
  95. struct cam_cpas_bus_client *bus_client, uint64_t *ab, uint64_t *ib,
  96. const struct cam_cpas_debug_settings *cpas_settings)
  97. {
  98. uint64_t curr_ab = *ab;
  99. uint64_t curr_ib = *ib;
  100. size_t name_len = strlen(bus_client->common_data.name);
  101. if (!cpas_settings) {
  102. CAM_ERR(CAM_CPAS, "Invalid cpas debug settings");
  103. return;
  104. }
  105. if (strnstr(bus_client->common_data.name, "cam_hf_0", name_len)) {
  106. if (cpas_settings->mnoc_hf_0_ab_bw)
  107. *ab = cpas_settings->mnoc_hf_0_ab_bw;
  108. if (cpas_settings->mnoc_hf_0_ib_bw)
  109. *ib = cpas_settings->mnoc_hf_0_ib_bw;
  110. } else if (strnstr(bus_client->common_data.name, "cam_hf_1",
  111. name_len)) {
  112. if (cpas_settings->mnoc_hf_1_ab_bw)
  113. *ab = cpas_settings->mnoc_hf_1_ab_bw;
  114. if (cpas_settings->mnoc_hf_1_ib_bw)
  115. *ib = cpas_settings->mnoc_hf_1_ib_bw;
  116. } else if (strnstr(bus_client->common_data.name, "cam_sf_0",
  117. name_len)) {
  118. if (cpas_settings->mnoc_sf_0_ab_bw)
  119. *ab = cpas_settings->mnoc_sf_0_ab_bw;
  120. if (cpas_settings->mnoc_sf_0_ib_bw)
  121. *ib = cpas_settings->mnoc_sf_0_ib_bw;
  122. } else if (strnstr(bus_client->common_data.name, "cam_sf_1",
  123. name_len)) {
  124. if (cpas_settings->mnoc_sf_1_ab_bw)
  125. *ab = cpas_settings->mnoc_sf_1_ab_bw;
  126. if (cpas_settings->mnoc_sf_1_ib_bw)
  127. *ib = cpas_settings->mnoc_sf_1_ib_bw;
  128. } else if (strnstr(bus_client->common_data.name, "cam_sf_icp",
  129. name_len)) {
  130. if (cpas_settings->mnoc_sf_icp_ab_bw)
  131. *ab = cpas_settings->mnoc_sf_icp_ab_bw;
  132. if (cpas_settings->mnoc_sf_icp_ib_bw)
  133. *ib = cpas_settings->mnoc_sf_icp_ib_bw;
  134. } else {
  135. CAM_ERR(CAM_CPAS, "unknown mnoc port: %s, bw override failed",
  136. bus_client->common_data.name);
  137. return;
  138. }
  139. CAM_INFO(CAM_CPAS,
  140. "Overriding mnoc bw for: %s with ab: %llu, ib: %llu, curr_ab: %llu, curr_ib: %llu",
  141. bus_client->common_data.name, *ab, *ib, curr_ab, curr_ib);
  142. }
  143. int cam_cpas_util_reg_read(struct cam_hw_info *cpas_hw,
  144. enum cam_cpas_reg_base reg_base, struct cam_cpas_reg *reg_info)
  145. {
  146. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  147. struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
  148. uint32_t value;
  149. int reg_base_index;
  150. if (!reg_info->enable)
  151. return 0;
  152. reg_base_index = cpas_core->regbase_index[reg_base];
  153. if (reg_base_index == -1)
  154. return -EINVAL;
  155. value = cam_io_r_mb(
  156. soc_info->reg_map[reg_base_index].mem_base + reg_info->offset);
  157. CAM_INFO(CAM_CPAS, "Base[%d] Offset[0x%08x] Value[0x%08x]",
  158. reg_base, reg_info->offset, value);
  159. return 0;
  160. }
  161. int cam_cpas_util_reg_update(struct cam_hw_info *cpas_hw,
  162. enum cam_cpas_reg_base reg_base, struct cam_cpas_reg *reg_info)
  163. {
  164. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  165. struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
  166. uint32_t value;
  167. int reg_base_index;
  168. if (reg_info->enable == false)
  169. return 0;
  170. reg_base_index = cpas_core->regbase_index[reg_base];
  171. if (reg_base_index == -1)
  172. return -EINVAL;
  173. if (reg_info->masked_value) {
  174. value = cam_io_r_mb(
  175. soc_info->reg_map[reg_base_index].mem_base +
  176. reg_info->offset);
  177. value = value & (~reg_info->mask);
  178. value = value | (reg_info->value << reg_info->shift);
  179. } else {
  180. value = reg_info->value;
  181. }
  182. CAM_DBG(CAM_CPAS, "Base[%d]:[0x%08x] Offset[0x%08x] Value[0x%08x]",
  183. reg_base, soc_info->reg_map[reg_base_index].mem_base, reg_info->offset, value);
  184. cam_io_w_mb(value, soc_info->reg_map[reg_base_index].mem_base +
  185. reg_info->offset);
  186. return 0;
  187. }
  188. static int cam_cpas_util_vote_bus_client_level(
  189. struct cam_cpas_bus_client *bus_client, unsigned int level)
  190. {
  191. int rc = 0;
  192. if (!bus_client->valid) {
  193. CAM_ERR(CAM_CPAS, "bus client not valid");
  194. rc = -EINVAL;
  195. goto end;
  196. }
  197. if (level >= CAM_MAX_VOTE) {
  198. CAM_ERR(CAM_CPAS,
  199. "Invalid votelevel=%d,usecases=%d,Bus client=[%s]",
  200. level, bus_client->common_data.num_usecases,
  201. bus_client->common_data.name);
  202. return -EINVAL;
  203. }
  204. if (level == bus_client->curr_vote_level)
  205. goto end;
  206. rc = cam_soc_bus_client_update_request(bus_client->soc_bus_client,
  207. level);
  208. if (rc) {
  209. CAM_ERR(CAM_CPAS, "Client: %s update request failed rc: %d",
  210. bus_client->common_data.name, rc);
  211. goto end;
  212. }
  213. bus_client->curr_vote_level = level;
  214. end:
  215. return rc;
  216. }
  217. static int cam_cpas_util_vote_drv_bus_client_bw(struct cam_cpas_bus_client *bus_client,
  218. struct cam_cpas_axi_bw_info *curr_vote, struct cam_cpas_axi_bw_info *applied_vote)
  219. {
  220. int rc = 0;
  221. const struct camera_debug_settings *cam_debug = NULL;
  222. if (!bus_client->valid) {
  223. CAM_ERR(CAM_CPAS, "bus client: %s not valid",
  224. bus_client->common_data.name);
  225. rc = -EINVAL;
  226. goto end;
  227. }
  228. mutex_lock(&bus_client->lock);
  229. if ((curr_vote->drv_vote.high.ab > 0) &&
  230. (curr_vote->drv_vote.high.ab < CAM_CPAS_AXI_MIN_MNOC_AB_BW))
  231. curr_vote->drv_vote.high.ab = CAM_CPAS_AXI_MIN_MNOC_AB_BW;
  232. if ((curr_vote->drv_vote.high.ib > 0) &&
  233. (curr_vote->drv_vote.high.ib < CAM_CPAS_AXI_MIN_MNOC_IB_BW))
  234. curr_vote->drv_vote.high.ib = CAM_CPAS_AXI_MIN_MNOC_IB_BW;
  235. if ((curr_vote->drv_vote.low.ab > 0) &&
  236. (curr_vote->drv_vote.low.ab < CAM_CPAS_AXI_MIN_MNOC_AB_BW))
  237. curr_vote->drv_vote.low.ab = CAM_CPAS_AXI_MIN_MNOC_AB_BW;
  238. if ((curr_vote->drv_vote.low.ib > 0) &&
  239. (curr_vote->drv_vote.low.ib < CAM_CPAS_AXI_MIN_MNOC_IB_BW))
  240. curr_vote->drv_vote.low.ib = CAM_CPAS_AXI_MIN_MNOC_IB_BW;
  241. cam_debug = cam_debug_get_settings();
  242. if ((curr_vote->drv_vote.high.ab || curr_vote->drv_vote.high.ib ||
  243. curr_vote->drv_vote.low.ab || curr_vote->drv_vote.low.ib) &&
  244. cam_debug && cam_debug->cpas_settings.is_updated)
  245. cam_cpas_process_drv_bw_overrides(bus_client, &curr_vote->drv_vote.high.ab,
  246. &curr_vote->drv_vote.high.ib, &curr_vote->drv_vote.low.ab,
  247. &curr_vote->drv_vote.low.ib, &cam_debug->cpas_settings);
  248. if (debug_drv)
  249. CAM_INFO(CAM_CPAS, "Bus_client: %s, DRV vote high=[%llu %llu] low=[%llu %llu]",
  250. bus_client->common_data.name, curr_vote->drv_vote.high.ab,
  251. curr_vote->drv_vote.high.ib, curr_vote->drv_vote.low.ab,
  252. curr_vote->drv_vote.low.ib);
  253. CAM_DBG(CAM_CPAS, "Bus_client: %s, DRV vote high=[%llu %llu] low=[%llu %llu]",
  254. bus_client->common_data.name, curr_vote->drv_vote.high.ab,
  255. curr_vote->drv_vote.high.ib, curr_vote->drv_vote.low.ab,
  256. curr_vote->drv_vote.low.ib);
  257. rc = cam_soc_bus_client_update_bw(bus_client->soc_bus_client, curr_vote->drv_vote.high.ab,
  258. curr_vote->drv_vote.high.ib, CAM_SOC_BUS_PATH_DATA_DRV_HIGH);
  259. if (rc) {
  260. CAM_ERR(CAM_CPAS, "Update bw failed, Bus path: %s ab[%llu] ib[%llu]",
  261. cam_soc_bus_path_data_to_str(CAM_SOC_BUS_PATH_DATA_DRV_HIGH),
  262. curr_vote->drv_vote.high.ab, curr_vote->drv_vote.high.ib);
  263. goto unlock_client;
  264. }
  265. rc = cam_soc_bus_client_update_bw(bus_client->soc_bus_client, curr_vote->drv_vote.low.ab,
  266. curr_vote->drv_vote.low.ib, CAM_SOC_BUS_PATH_DATA_DRV_LOW);
  267. if (rc) {
  268. CAM_ERR(CAM_CPAS, "Update bw failed, Bus path: %s ab[%llu] ib[%llu]",
  269. cam_soc_bus_path_data_to_str(CAM_SOC_BUS_PATH_DATA_DRV_LOW),
  270. curr_vote->drv_vote.low.ab, curr_vote->drv_vote.low.ib);
  271. goto unlock_client;
  272. }
  273. if (applied_vote)
  274. memcpy(applied_vote, curr_vote, sizeof(struct cam_cpas_axi_bw_info));
  275. unlock_client:
  276. mutex_unlock(&bus_client->lock);
  277. end:
  278. return rc;
  279. }
  280. static int cam_cpas_util_vote_hlos_bus_client_bw(
  281. struct cam_cpas_bus_client *bus_client, uint64_t ab, uint64_t ib,
  282. bool is_camnoc_bw, uint64_t *applied_ab, uint64_t *applied_ib)
  283. {
  284. int rc = 0;
  285. uint64_t min_camnoc_ib_bw = CAM_CPAS_AXI_MIN_CAMNOC_IB_BW;
  286. const struct camera_debug_settings *cam_debug = NULL;
  287. if (!bus_client->valid) {
  288. CAM_ERR(CAM_CPAS, "bus client: %s not valid",
  289. bus_client->common_data.name);
  290. rc = -EINVAL;
  291. goto end;
  292. }
  293. if (cam_min_camnoc_ib_bw > 0)
  294. min_camnoc_ib_bw = (uint64_t)cam_min_camnoc_ib_bw * 1000000L;
  295. CAM_DBG(CAM_CPAS,
  296. "Bus_client: %s, cam_min_camnoc_ib_bw = %d, min_camnoc_ib_bw=%llu",
  297. bus_client->common_data.name, cam_min_camnoc_ib_bw,
  298. min_camnoc_ib_bw);
  299. mutex_lock(&bus_client->lock);
  300. if (is_camnoc_bw) {
  301. if ((ab > 0) && (ab < CAM_CPAS_AXI_MIN_CAMNOC_AB_BW))
  302. ab = CAM_CPAS_AXI_MIN_CAMNOC_AB_BW;
  303. if ((ib > 0) && (ib < min_camnoc_ib_bw))
  304. ib = min_camnoc_ib_bw;
  305. } else {
  306. if ((ab > 0) && (ab < CAM_CPAS_AXI_MIN_MNOC_AB_BW))
  307. ab = CAM_CPAS_AXI_MIN_MNOC_AB_BW;
  308. if ((ib > 0) && (ib < CAM_CPAS_AXI_MIN_MNOC_IB_BW))
  309. ib = CAM_CPAS_AXI_MIN_MNOC_IB_BW;
  310. }
  311. cam_debug = cam_debug_get_settings();
  312. if ((ab || ib) && cam_debug && cam_debug->cpas_settings.is_updated)
  313. cam_cpas_process_bw_overrides(bus_client, &ab, &ib,
  314. &cam_debug->cpas_settings);
  315. rc = cam_soc_bus_client_update_bw(bus_client->soc_bus_client, ab, ib,
  316. CAM_SOC_BUS_PATH_DATA_HLOS);
  317. if (rc) {
  318. CAM_ERR(CAM_CPAS,
  319. "Update bw failed, Bus path %s ab[%llu] ib[%llu]",
  320. cam_soc_bus_path_data_to_str(CAM_SOC_BUS_PATH_DATA_HLOS), ab, ib);
  321. goto unlock_client;
  322. }
  323. if (applied_ab)
  324. *applied_ab = ab;
  325. if (applied_ib)
  326. *applied_ib = ib;
  327. unlock_client:
  328. mutex_unlock(&bus_client->lock);
  329. end:
  330. return rc;
  331. }
  332. static int cam_cpas_util_register_bus_client(
  333. struct cam_hw_soc_info *soc_info, struct device_node *dev_node,
  334. struct cam_cpas_bus_client *bus_client)
  335. {
  336. int rc = 0;
  337. rc = cam_soc_bus_client_register(soc_info->pdev, dev_node,
  338. &bus_client->soc_bus_client, &bus_client->common_data);
  339. if (rc) {
  340. CAM_ERR(CAM_CPAS, "Bus client: %s registertion failed ,rc: %d",
  341. bus_client->common_data.name, rc);
  342. return rc;
  343. }
  344. bus_client->curr_vote_level = 0;
  345. bus_client->valid = true;
  346. mutex_init(&bus_client->lock);
  347. return 0;
  348. }
  349. static int cam_cpas_util_unregister_bus_client(
  350. struct cam_cpas_bus_client *bus_client)
  351. {
  352. if (!bus_client->valid) {
  353. CAM_ERR(CAM_CPAS, "bus client not valid");
  354. return -EINVAL;
  355. }
  356. cam_soc_bus_client_unregister(&bus_client->soc_bus_client);
  357. bus_client->curr_vote_level = 0;
  358. bus_client->valid = false;
  359. mutex_destroy(&bus_client->lock);
  360. return 0;
  361. }
  362. static int cam_cpas_util_axi_cleanup(struct cam_cpas *cpas_core,
  363. struct cam_hw_soc_info *soc_info)
  364. {
  365. int i = 0;
  366. if (cpas_core->num_axi_ports > CAM_CPAS_MAX_AXI_PORTS) {
  367. CAM_ERR(CAM_CPAS, "Invalid num_axi_ports: %d",
  368. cpas_core->num_axi_ports);
  369. return -EINVAL;
  370. }
  371. if (cpas_core->num_camnoc_axi_ports > CAM_CPAS_MAX_AXI_PORTS) {
  372. CAM_ERR(CAM_CPAS, "Invalid num_camnoc_axi_ports: %d",
  373. cpas_core->num_camnoc_axi_ports);
  374. return -EINVAL;
  375. }
  376. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  377. cam_cpas_util_unregister_bus_client(
  378. &cpas_core->axi_port[i].bus_client);
  379. of_node_put(cpas_core->axi_port[i].axi_port_node);
  380. cpas_core->axi_port[i].axi_port_node = NULL;
  381. }
  382. for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) {
  383. cam_cpas_util_unregister_bus_client(
  384. &cpas_core->camnoc_axi_port[i].bus_client);
  385. of_node_put(cpas_core->camnoc_axi_port[i].axi_port_node);
  386. cpas_core->camnoc_axi_port[i].axi_port_node = NULL;
  387. }
  388. return 0;
  389. }
  390. static int cam_cpas_util_axi_setup(struct cam_cpas *cpas_core,
  391. struct cam_hw_soc_info *soc_info)
  392. {
  393. int i = 0, rc = 0;
  394. struct device_node *axi_port_mnoc_node = NULL;
  395. struct device_node *axi_port_camnoc_node = NULL;
  396. if (cpas_core->num_axi_ports > CAM_CPAS_MAX_AXI_PORTS) {
  397. CAM_ERR(CAM_CPAS, "Invalid num_axi_ports: %d",
  398. cpas_core->num_axi_ports);
  399. return -EINVAL;
  400. }
  401. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  402. axi_port_mnoc_node = cpas_core->axi_port[i].axi_port_node;
  403. rc = cam_cpas_util_register_bus_client(soc_info,
  404. axi_port_mnoc_node, &cpas_core->axi_port[i].bus_client);
  405. if (rc)
  406. goto bus_register_fail;
  407. }
  408. for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) {
  409. axi_port_camnoc_node =
  410. cpas_core->camnoc_axi_port[i].axi_port_node;
  411. rc = cam_cpas_util_register_bus_client(soc_info,
  412. axi_port_camnoc_node,
  413. &cpas_core->camnoc_axi_port[i].bus_client);
  414. if (rc)
  415. goto bus_register_fail;
  416. }
  417. return 0;
  418. bus_register_fail:
  419. of_node_put(cpas_core->axi_port[i].axi_port_node);
  420. return rc;
  421. }
  422. static int cam_cpas_util_vote_default_ahb_axi(struct cam_hw_info *cpas_hw,
  423. int enable)
  424. {
  425. int rc, i = 0;
  426. struct cam_cpas *cpas_core = (struct cam_cpas *)cpas_hw->core_info;
  427. uint64_t ab_bw, ib_bw;
  428. uint64_t applied_ab_bw = 0, applied_ib_bw = 0;
  429. rc = cam_cpas_util_vote_bus_client_level(&cpas_core->ahb_bus_client,
  430. (enable == true) ? CAM_SVS_VOTE : CAM_SUSPEND_VOTE);
  431. if (rc) {
  432. CAM_ERR(CAM_CPAS, "Failed in AHB vote, enable=%d, rc=%d",
  433. enable, rc);
  434. return rc;
  435. }
  436. if (enable) {
  437. ab_bw = CAM_CPAS_DEFAULT_AXI_BW;
  438. ib_bw = CAM_CPAS_DEFAULT_AXI_BW;
  439. } else {
  440. ab_bw = 0;
  441. ib_bw = 0;
  442. }
  443. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  444. if (cpas_core->axi_port[i].bus_client.common_data.is_drv_port)
  445. continue;
  446. rc = cam_cpas_util_vote_hlos_bus_client_bw(
  447. &cpas_core->axi_port[i].bus_client,
  448. ab_bw, ib_bw, false, &applied_ab_bw, &applied_ib_bw);
  449. if (rc) {
  450. CAM_ERR(CAM_CPAS,
  451. "Failed in mnoc vote, enable=%d, rc=%d",
  452. enable, rc);
  453. goto remove_ahb_vote;
  454. }
  455. cpas_core->axi_port[i].applied_bw.hlos_vote.ab = applied_ab_bw;
  456. cpas_core->axi_port[i].applied_bw.hlos_vote.ib = applied_ib_bw;
  457. }
  458. return 0;
  459. remove_ahb_vote:
  460. cam_cpas_util_vote_bus_client_level(&cpas_core->ahb_bus_client,
  461. CAM_SUSPEND_VOTE);
  462. return rc;
  463. }
  464. static int cam_cpas_hw_reg_write(struct cam_hw_info *cpas_hw,
  465. uint32_t client_handle, enum cam_cpas_reg_base reg_base,
  466. uint32_t offset, bool mb, uint32_t value)
  467. {
  468. struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
  469. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  470. struct cam_cpas_client *cpas_client = NULL;
  471. int reg_base_index = cpas_core->regbase_index[reg_base];
  472. uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle);
  473. int rc = 0;
  474. if (reg_base_index < 0 || reg_base_index >= soc_info->num_reg_map) {
  475. CAM_ERR(CAM_CPAS,
  476. "Invalid reg_base=%d, reg_base_index=%d, num_map=%d",
  477. reg_base, reg_base_index, soc_info->num_reg_map);
  478. return -EINVAL;
  479. }
  480. if (!CAM_CPAS_CLIENT_VALID(client_indx))
  481. return -EINVAL;
  482. mutex_lock(&cpas_core->client_mutex[client_indx]);
  483. cpas_client = cpas_core->cpas_client[client_indx];
  484. if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) {
  485. CAM_ERR(CAM_CPAS, "client=[%d][%s][%d] has not started",
  486. client_indx, cpas_client->data.identifier,
  487. cpas_client->data.cell_index);
  488. rc = -EPERM;
  489. goto unlock_client;
  490. }
  491. if (mb)
  492. cam_io_w_mb(value,
  493. soc_info->reg_map[reg_base_index].mem_base + offset);
  494. else
  495. cam_io_w(value,
  496. soc_info->reg_map[reg_base_index].mem_base + offset);
  497. unlock_client:
  498. mutex_unlock(&cpas_core->client_mutex[client_indx]);
  499. return rc;
  500. }
  501. static int cam_cpas_hw_reg_read(struct cam_hw_info *cpas_hw,
  502. uint32_t client_handle, enum cam_cpas_reg_base reg_base,
  503. uint32_t offset, bool mb, uint32_t *value)
  504. {
  505. struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
  506. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  507. struct cam_cpas_client *cpas_client = NULL;
  508. int reg_base_index = cpas_core->regbase_index[reg_base];
  509. uint32_t reg_value;
  510. uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle);
  511. int rc = 0;
  512. if (!value)
  513. return -EINVAL;
  514. if (reg_base_index < 0 || reg_base_index >= soc_info->num_reg_map) {
  515. CAM_ERR(CAM_CPAS,
  516. "Invalid reg_base=%d, reg_base_index=%d, num_map=%d",
  517. reg_base, reg_base_index, soc_info->num_reg_map);
  518. return -EINVAL;
  519. }
  520. if (!CAM_CPAS_CLIENT_VALID(client_indx))
  521. return -EINVAL;
  522. cpas_client = cpas_core->cpas_client[client_indx];
  523. if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) {
  524. CAM_ERR(CAM_CPAS, "client=[%d][%s][%d] has not started",
  525. client_indx, cpas_client->data.identifier,
  526. cpas_client->data.cell_index);
  527. return -EPERM;
  528. }
  529. if (mb)
  530. reg_value = cam_io_r_mb(
  531. soc_info->reg_map[reg_base_index].mem_base + offset);
  532. else
  533. reg_value = cam_io_r(
  534. soc_info->reg_map[reg_base_index].mem_base + offset);
  535. *value = reg_value;
  536. return rc;
  537. }
  538. static int cam_cpas_hw_dump_camnoc_buff_fill_info(
  539. struct cam_hw_info *cpas_hw,
  540. uint32_t client_handle)
  541. {
  542. int rc = 0, i;
  543. uint32_t val = 0;
  544. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  545. struct cam_camnoc_info *camnoc_info =
  546. (struct cam_camnoc_info *) cpas_core->camnoc_info;
  547. char log_buf[CAM_CPAS_LOG_BUF_LEN] = {0};
  548. size_t len = 0;
  549. if (!camnoc_info) {
  550. CAM_ERR(CAM_CPAS, "Invalid camnoc info for hw_version: 0x%x",
  551. cpas_hw->soc_info.hw_version);
  552. return -EINVAL;
  553. }
  554. for (i = 0; i < camnoc_info->specific_size; i++) {
  555. if ((!camnoc_info->specific[i].enable) ||
  556. (!camnoc_info->specific[i].maxwr_low.enable))
  557. continue;
  558. rc = cam_cpas_hw_reg_read(cpas_hw, client_handle,
  559. CAM_CPAS_REG_CAMNOC,
  560. camnoc_info->specific[i].maxwr_low.offset, true, &val);
  561. if (rc)
  562. break;
  563. len += scnprintf((log_buf + len), (CAM_CPAS_LOG_BUF_LEN - len),
  564. " %s:[%d %d]", camnoc_info->specific[i].port_name,
  565. (val & 0x7FF), (val & 0x7F0000) >> 16);
  566. }
  567. CAM_INFO(CAM_CPAS, "CAMNOC Fill level [Queued Pending] %s", log_buf);
  568. return rc;
  569. }
  570. static void cam_cpas_print_smart_qos_priority(
  571. struct cam_hw_info *cpas_hw)
  572. {
  573. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  574. struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
  575. struct cam_cpas_private_soc *soc_private =
  576. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  577. struct cam_cpas_tree_node *niu_node;
  578. uint8_t i;
  579. int32_t reg_indx = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC];
  580. char log_buf[CAM_CPAS_LOG_BUF_LEN] = {0};
  581. size_t len = 0;
  582. uint32_t val_low = 0, val_high = 0;
  583. for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) {
  584. niu_node = soc_private->smart_qos_info->rt_wr_niu_node[i];
  585. val_high = cam_io_r_mb(soc_info->reg_map[reg_indx].mem_base +
  586. niu_node->pri_lut_high_offset);
  587. val_low = cam_io_r_mb(soc_info->reg_map[reg_indx].mem_base +
  588. niu_node->pri_lut_low_offset);
  589. len += scnprintf((log_buf + len), (CAM_CPAS_LOG_BUF_LEN - len),
  590. " [%s:high 0x%x low 0x%x]", niu_node->node_name,
  591. val_high, val_low);
  592. }
  593. CAM_INFO(CAM_CPAS, "SmartQoS [Node Pri_lut] %s", log_buf);
  594. }
  595. static bool cam_cpas_is_new_rt_bw_lower(
  596. const struct cam_hw_info *cpas_hw)
  597. {
  598. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  599. int i;
  600. struct cam_cpas_axi_port *temp_axi_port = NULL;
  601. uint64_t applied_total = 0, new_total = 0;
  602. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  603. temp_axi_port = &cpas_core->axi_port[i];
  604. if (!temp_axi_port->is_rt)
  605. continue;
  606. if (temp_axi_port->bus_client.common_data.is_drv_port) {
  607. CAM_DBG(CAM_PERF, "Port %s DRV ab applied [%llu %llu] new [%llu %llu]",
  608. temp_axi_port->axi_port_name,
  609. temp_axi_port->applied_bw.drv_vote.high.ab,
  610. temp_axi_port->applied_bw.drv_vote.low.ab,
  611. temp_axi_port->curr_bw.drv_vote.high.ab,
  612. temp_axi_port->curr_bw.drv_vote.low.ab);
  613. applied_total += temp_axi_port->applied_bw.drv_vote.high.ab;
  614. new_total += temp_axi_port->curr_bw.drv_vote.high.ab;
  615. } else {
  616. CAM_DBG(CAM_PERF, "Port %s HLOS ab applied %llu new %llu",
  617. temp_axi_port->axi_port_name,
  618. temp_axi_port->applied_bw.hlos_vote.ab,
  619. temp_axi_port->curr_bw.hlos_vote.ab);
  620. applied_total += temp_axi_port->applied_bw.hlos_vote.ab;
  621. new_total += temp_axi_port->curr_bw.hlos_vote.ab;
  622. }
  623. }
  624. return (new_total < applied_total) ? true : false;
  625. }
  626. static void cam_cpas_reset_niu_priorities(
  627. struct cam_hw_info *cpas_hw)
  628. {
  629. struct cam_cpas_private_soc *soc_private =
  630. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  631. uint8_t i;
  632. for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) {
  633. soc_private->smart_qos_info->rt_wr_niu_node[i]->applied_priority_low = 0x0;
  634. soc_private->smart_qos_info->rt_wr_niu_node[i]->applied_priority_high = 0x0;
  635. }
  636. }
  637. static bool cam_cpas_calculate_smart_qos(
  638. struct cam_hw_info *cpas_hw)
  639. {
  640. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  641. struct cam_cpas_private_soc *soc_private =
  642. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  643. struct cam_cpas_tree_node *niu_node;
  644. uint8_t i;
  645. bool needs_update = false;
  646. uint64_t bw_per_kb, max_bw_per_kb = 0, remainder, ramp_val;
  647. uint64_t total_bw_per_kb = 0, total_bw_ramp_val = 0;
  648. int8_t pos;
  649. uint64_t priority;
  650. uint8_t val, clamp_threshold;
  651. for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) {
  652. niu_node = soc_private->smart_qos_info->rt_wr_niu_node[i];
  653. bw_per_kb = niu_node->camnoc_bw;
  654. remainder = do_div(bw_per_kb, niu_node->niu_size);
  655. total_bw_per_kb += bw_per_kb;
  656. if (max_bw_per_kb < bw_per_kb)
  657. max_bw_per_kb = bw_per_kb;
  658. CAM_DBG(CAM_PERF,
  659. "NIU[%d][%s]camnoc_bw %llu, niu_size %u, bw_per_kb %lld, remainder %lld, max_bw_per_kb %lld, total_bw_per_kb %lld",
  660. i, niu_node->node_name, niu_node->camnoc_bw, niu_node->niu_size,
  661. bw_per_kb, remainder, max_bw_per_kb, total_bw_per_kb);
  662. }
  663. if (!max_bw_per_kb) {
  664. CAM_DBG(CAM_PERF, "No valid bw on NIU nodes");
  665. return false;
  666. }
  667. for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) {
  668. niu_node = soc_private->smart_qos_info->rt_wr_niu_node[i];
  669. bw_per_kb = niu_node->camnoc_bw;
  670. remainder = do_div(bw_per_kb, niu_node->niu_size); // --> dropping remainder
  671. if ((bw_per_kb * CAM_CPAS_MAX_STRESS_INDICATOR) >
  672. (total_bw_per_kb *
  673. soc_private->smart_qos_info->highstress_indicator_th)) {
  674. clamp_threshold = soc_private->smart_qos_info->moststressed_clamp_th;
  675. CAM_DBG(CAM_PERF, "Current niu clamp_threshold=%d",
  676. clamp_threshold);
  677. } else {
  678. ramp_val = soc_private->smart_qos_info->bw_ratio_scale_factor *
  679. bw_per_kb;
  680. ramp_val = ramp_val *
  681. (soc_private->smart_qos_info->leaststressed_clamp_th -
  682. soc_private->smart_qos_info->moststressed_clamp_th);
  683. /*
  684. * Stress indicator threshold may have a float type value
  685. * such as 0.5 according max stress indicator value 1,
  686. * we take in percentages to avoid float type calcaulate.
  687. */
  688. total_bw_ramp_val = total_bw_per_kb *
  689. (soc_private->smart_qos_info->highstress_indicator_th -
  690. soc_private->smart_qos_info->lowstress_indicator_th) /
  691. CAM_CPAS_MAX_STRESS_INDICATOR;
  692. CAM_DBG(CAM_PERF, "ramp_val=%lld, total_bw_ramp_val=%lld",
  693. ramp_val, total_bw_ramp_val);
  694. remainder = do_div(ramp_val, total_bw_ramp_val);
  695. /* round the value */
  696. if ((remainder * 2) >= total_bw_ramp_val)
  697. ramp_val += 1;
  698. val = (uint8_t)(ramp_val);
  699. clamp_threshold =
  700. soc_private->smart_qos_info->leaststressed_clamp_th - val;
  701. CAM_DBG(CAM_PERF, "Current niu clamp_threshold=%d, val=%d",
  702. clamp_threshold, val);
  703. }
  704. priority = 0;
  705. for (pos = 15; pos >= clamp_threshold; pos--) {
  706. val = soc_private->smart_qos_info->rt_wr_priority_clamp;
  707. priority = priority << 4;
  708. priority |= val;
  709. CAM_DBG(CAM_PERF, "pos=%d, val=0x%x, priority=0x%llx", pos, val, priority);
  710. }
  711. for (pos = clamp_threshold - 1; pos >= 0; pos--) {
  712. if (pos == 0) {
  713. val = soc_private->smart_qos_info->rt_wr_priority_min;
  714. } else {
  715. ramp_val = pos * bw_per_kb;
  716. /*
  717. * Slope factor may have a float type value such as 0.7
  718. * according max slope factor value 1,
  719. * we take in percentages to avoid float type calcaulate.
  720. */
  721. ramp_val = ramp_val *
  722. soc_private->smart_qos_info->rt_wr_slope_factor /
  723. CAM_CPAS_MAX_SLOPE_FACTOR;
  724. remainder = do_div(ramp_val, max_bw_per_kb);
  725. CAM_DBG(CAM_PERF,
  726. "pos=%d, bw_per_kb=%lld, pos*bw_per_kb=%lld, ramp_val=%lld, remainder=%lld, max_bw_per_kb=%lld",
  727. pos, bw_per_kb, pos * bw_per_kb, ramp_val, remainder,
  728. max_bw_per_kb);
  729. /* round the value */
  730. if ((remainder * 2) >= max_bw_per_kb)
  731. ramp_val += 1;
  732. val = (uint8_t)(ramp_val);
  733. val += soc_private->smart_qos_info->rt_wr_priority_min;
  734. val = min(val, soc_private->smart_qos_info->rt_wr_priority_max);
  735. }
  736. priority = priority << 4;
  737. priority |= val;
  738. CAM_DBG(CAM_PERF, "pos=%d, val=0x%x, priority=0x%llx", pos, val, priority);
  739. }
  740. niu_node->curr_priority_low = (uint32_t)(priority & 0xFFFFFFFF);
  741. niu_node->curr_priority_high = (uint32_t)((priority >> 32) & 0xFFFFFFFF);
  742. if ((niu_node->curr_priority_low != niu_node->applied_priority_low) ||
  743. (niu_node->curr_priority_high != niu_node->applied_priority_high))
  744. needs_update = true;
  745. CAM_DBG(CAM_PERF,
  746. "Node[%d][%s]Priority applied high 0x%x low 0x%x, new high 0x%x low 0x%x, needs_update %d",
  747. i, niu_node->node_name,
  748. niu_node->applied_priority_high, niu_node->applied_priority_low,
  749. niu_node->curr_priority_high, niu_node->curr_priority_low,
  750. needs_update);
  751. }
  752. if (cpas_core->smart_qos_dump && needs_update) {
  753. for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) {
  754. niu_node = soc_private->smart_qos_info->rt_wr_niu_node[i];
  755. CAM_INFO(CAM_PERF,
  756. "Node[%d][%s]camnoc_bw=%lld, niu_size=%d, offset high 0x%x, low 0x%x, Priority new high 0x%x low 0x%x, applied high 0x%x low 0x%x",
  757. i, niu_node->node_name, niu_node->camnoc_bw, niu_node->niu_size,
  758. niu_node->pri_lut_high_offset, niu_node->pri_lut_low_offset,
  759. niu_node->curr_priority_high, niu_node->curr_priority_low,
  760. niu_node->applied_priority_high, niu_node->applied_priority_low);
  761. }
  762. }
  763. return needs_update;
  764. }
  765. static int cam_cpas_apply_smart_qos(
  766. struct cam_hw_info *cpas_hw)
  767. {
  768. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  769. struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
  770. struct cam_cpas_private_soc *soc_private =
  771. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  772. struct cam_cpas_tree_node *niu_node;
  773. uint8_t i;
  774. int32_t reg_indx = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC];
  775. if (cpas_core->smart_qos_dump) {
  776. CAM_INFO(CAM_PERF, "Printing SmartQos values before update");
  777. cam_cpas_print_smart_qos_priority(cpas_hw);
  778. }
  779. for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) {
  780. niu_node = soc_private->smart_qos_info->rt_wr_niu_node[i];
  781. if (niu_node->curr_priority_high != niu_node->applied_priority_high) {
  782. cam_io_w_mb(niu_node->curr_priority_high,
  783. soc_info->reg_map[reg_indx].mem_base +
  784. niu_node->pri_lut_high_offset);
  785. niu_node->applied_priority_high = niu_node->curr_priority_high;
  786. }
  787. if (niu_node->curr_priority_low != niu_node->applied_priority_low) {
  788. cam_io_w_mb(niu_node->curr_priority_low,
  789. soc_info->reg_map[reg_indx].mem_base +
  790. niu_node->pri_lut_low_offset);
  791. niu_node->applied_priority_low = niu_node->curr_priority_low;
  792. }
  793. }
  794. if (cpas_core->smart_qos_dump) {
  795. CAM_INFO(CAM_PERF, "Printing SmartQos values after update");
  796. cam_cpas_print_smart_qos_priority(cpas_hw);
  797. }
  798. return 0;
  799. }
  800. static int cam_cpas_util_set_camnoc_axi_clk_rate(
  801. struct cam_hw_info *cpas_hw)
  802. {
  803. struct cam_cpas_private_soc *soc_private =
  804. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  805. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  806. struct cam_cpas_tree_node *tree_node = NULL;
  807. int rc = 0, i = 0;
  808. const struct camera_debug_settings *cam_debug = NULL;
  809. CAM_DBG(CAM_CPAS, "control_camnoc_axi_clk=%d",
  810. soc_private->control_camnoc_axi_clk);
  811. if (soc_private->control_camnoc_axi_clk) {
  812. struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
  813. uint64_t required_camnoc_bw = 0, intermediate_result = 0;
  814. int64_t clk_rate = 0;
  815. for (i = 0; i < CAM_CPAS_MAX_TREE_NODES; i++) {
  816. tree_node = soc_private->tree_node[i];
  817. if (!tree_node ||
  818. !tree_node->camnoc_max_needed)
  819. continue;
  820. if (required_camnoc_bw < (tree_node->camnoc_bw *
  821. tree_node->bus_width_factor)) {
  822. required_camnoc_bw = tree_node->camnoc_bw *
  823. tree_node->bus_width_factor;
  824. }
  825. }
  826. intermediate_result = required_camnoc_bw *
  827. soc_private->camnoc_axi_clk_bw_margin;
  828. do_div(intermediate_result, 100);
  829. required_camnoc_bw += intermediate_result;
  830. if (cpas_core->streamon_clients && (required_camnoc_bw == 0)) {
  831. CAM_DBG(CAM_CPAS,
  832. "Set min vote if streamon_clients is non-zero : streamon_clients=%d",
  833. cpas_core->streamon_clients);
  834. required_camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW;
  835. }
  836. if ((required_camnoc_bw > 0) &&
  837. (required_camnoc_bw <
  838. soc_private->camnoc_axi_min_ib_bw))
  839. required_camnoc_bw = soc_private->camnoc_axi_min_ib_bw;
  840. cam_debug = cam_debug_get_settings();
  841. if (cam_debug && cam_debug->cpas_settings.camnoc_bw) {
  842. if (cam_debug->cpas_settings.camnoc_bw <
  843. soc_private->camnoc_bus_width)
  844. required_camnoc_bw =
  845. soc_private->camnoc_bus_width;
  846. else
  847. required_camnoc_bw =
  848. cam_debug->cpas_settings.camnoc_bw;
  849. CAM_INFO(CAM_CPAS, "Overriding camnoc bw: %llu",
  850. required_camnoc_bw);
  851. }
  852. intermediate_result = required_camnoc_bw;
  853. do_div(intermediate_result, soc_private->camnoc_bus_width);
  854. clk_rate = intermediate_result;
  855. CAM_DBG(CAM_CPAS,
  856. "Setting camnoc axi clk rate[BW Clk] : [%llu %lld]",
  857. required_camnoc_bw, clk_rate);
  858. /*
  859. * CPAS hw is not powered on for the first client.
  860. * Also, clk_rate will be overwritten with default
  861. * value while power on. So, skipping this for first
  862. * client.
  863. */
  864. if (cpas_core->streamon_clients) {
  865. rc = cam_soc_util_set_src_clk_rate(soc_info, clk_rate);
  866. if (rc)
  867. CAM_ERR(CAM_CPAS,
  868. "Failed in setting camnoc axi clk %llu %lld %d",
  869. required_camnoc_bw, clk_rate, rc);
  870. cpas_core->applied_camnoc_axi_rate = clk_rate;
  871. }
  872. }
  873. return rc;
  874. }
  875. static int cam_cpas_util_translate_client_paths(
  876. struct cam_axi_vote *axi_vote)
  877. {
  878. int i;
  879. uint32_t *path_data_type = NULL;
  880. if (!axi_vote)
  881. return -EINVAL;
  882. for (i = 0; i < axi_vote->num_paths; i++) {
  883. path_data_type = &axi_vote->axi_path[i].path_data_type;
  884. /* Update path_data_type from UAPI value to internal value */
  885. if (*path_data_type >= CAM_CPAS_PATH_DATA_CONSO_OFFSET)
  886. *path_data_type = CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT +
  887. (*path_data_type %
  888. CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT);
  889. else
  890. *path_data_type %= CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT;
  891. if (*path_data_type >= CAM_CPAS_PATH_DATA_MAX) {
  892. CAM_ERR(CAM_CPAS, "index Invalid: %d", path_data_type);
  893. return -EINVAL;
  894. }
  895. }
  896. return 0;
  897. }
  898. static int cam_cpas_axi_consolidate_path_votes(
  899. struct cam_cpas_client *cpas_client,
  900. struct cam_axi_vote *axi_vote)
  901. {
  902. int rc = 0, i, k, l;
  903. struct cam_axi_vote *con_axi_vote = &cpas_client->axi_vote;
  904. bool path_found = false, cons_entry_found;
  905. struct cam_cpas_tree_node *curr_tree_node = NULL;
  906. struct cam_cpas_tree_node *sum_tree_node = NULL;
  907. uint32_t transac_type;
  908. uint32_t path_data_type;
  909. struct cam_cpas_axi_per_path_bw_vote *axi_path;
  910. con_axi_vote->num_paths = 0;
  911. for (i = 0; i < axi_vote->num_paths; i++) {
  912. path_found = false;
  913. path_data_type = axi_vote->axi_path[i].path_data_type;
  914. transac_type = axi_vote->axi_path[i].transac_type;
  915. if ((path_data_type >= CAM_CPAS_PATH_DATA_MAX) ||
  916. (transac_type >= CAM_CPAS_TRANSACTION_MAX)) {
  917. CAM_ERR(CAM_CPAS, "Invalid path or transac type: %d %d",
  918. path_data_type, transac_type);
  919. return -EINVAL;
  920. }
  921. axi_path = &con_axi_vote->axi_path[con_axi_vote->num_paths];
  922. curr_tree_node =
  923. cpas_client->tree_node[path_data_type][transac_type];
  924. if (curr_tree_node) {
  925. memcpy(axi_path, &axi_vote->axi_path[i],
  926. sizeof(struct cam_cpas_axi_per_path_bw_vote));
  927. con_axi_vote->num_paths++;
  928. continue;
  929. }
  930. for (k = 0; k < CAM_CPAS_PATH_DATA_MAX; k++) {
  931. sum_tree_node = cpas_client->tree_node[k][transac_type];
  932. if (!sum_tree_node)
  933. continue;
  934. if (sum_tree_node->constituent_paths[path_data_type]) {
  935. path_found = true;
  936. /*
  937. * Check if corresponding consolidated path
  938. * entry is already added into consolidated list
  939. */
  940. cons_entry_found = false;
  941. for (l = 0; l < con_axi_vote->num_paths; l++) {
  942. if ((con_axi_vote->axi_path[l].path_data_type == k) &&
  943. (con_axi_vote->axi_path[l].transac_type == transac_type)) {
  944. cons_entry_found = true;
  945. con_axi_vote->axi_path[l].camnoc_bw +=
  946. axi_vote->axi_path[i].camnoc_bw;
  947. con_axi_vote->axi_path[l].mnoc_ab_bw +=
  948. axi_vote->axi_path[i].mnoc_ab_bw;
  949. con_axi_vote->axi_path[l].mnoc_ib_bw +=
  950. axi_vote->axi_path[i].mnoc_ib_bw;
  951. break;
  952. }
  953. }
  954. /* If not found, add a new entry */
  955. if (!cons_entry_found) {
  956. axi_path->path_data_type = k;
  957. axi_path->transac_type = transac_type;
  958. axi_path->camnoc_bw = axi_vote->axi_path[i].camnoc_bw;
  959. axi_path->mnoc_ab_bw = axi_vote->axi_path[i].mnoc_ab_bw;
  960. axi_path->mnoc_ib_bw = axi_vote->axi_path[i].mnoc_ib_bw;
  961. axi_path->vote_level = axi_vote->axi_path[i].vote_level;
  962. con_axi_vote->num_paths++;
  963. }
  964. break;
  965. }
  966. }
  967. if (!path_found) {
  968. CAM_ERR(CAM_CPAS,
  969. "Client [%s][%d] i=%d num_paths=%d Consolidated path not found for path=%d, transac=%d",
  970. cpas_client->data.identifier, cpas_client->data.cell_index, i,
  971. axi_vote->num_paths, path_data_type, transac_type);
  972. return -EINVAL;
  973. }
  974. }
  975. return rc;
  976. }
  977. static int cam_cpas_update_axi_vote_bw(
  978. struct cam_hw_info *cpas_hw,
  979. struct cam_cpas_tree_node *cpas_tree_node,
  980. int drv_voting_idx,
  981. bool *mnoc_axi_port_updated,
  982. bool *camnoc_axi_port_updated)
  983. {
  984. int i, axi_port_idx = -1;
  985. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  986. struct cam_cpas_private_soc *soc_private =
  987. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  988. bool is_mnoc_updated = false;
  989. for (i = 0; i < CAM_CPAS_MAX_DRV_PORTS; i++) {
  990. axi_port_idx = cpas_tree_node->axi_port_idx_arr[i];
  991. if ((axi_port_idx < 0) || (i != drv_voting_idx))
  992. continue;
  993. if (axi_port_idx >= CAM_CPAS_MAX_AXI_PORTS) {
  994. CAM_ERR(CAM_CPAS, "Invalid axi_port_idx: %d drv_idx: %d", axi_port_idx, i);
  995. return -EINVAL;
  996. }
  997. memcpy(&cpas_core->axi_port[axi_port_idx].curr_bw, &cpas_tree_node->bw_info[i],
  998. sizeof(struct cam_cpas_axi_bw_info));
  999. /* Add low value to high for drv */
  1000. if (i > CAM_CPAS_PORT_HLOS_DRV) {
  1001. cpas_core->axi_port[axi_port_idx].curr_bw.drv_vote.high.ab +=
  1002. cpas_core->axi_port[axi_port_idx].curr_bw.drv_vote.low.ab;
  1003. cpas_core->axi_port[axi_port_idx].curr_bw.drv_vote.high.ib +=
  1004. cpas_core->axi_port[axi_port_idx].curr_bw.drv_vote.low.ib;
  1005. }
  1006. mnoc_axi_port_updated[axi_port_idx] = true;
  1007. is_mnoc_updated = true;
  1008. }
  1009. if (!is_mnoc_updated) {
  1010. CAM_ERR(CAM_CPAS, "No mnoc port was updated");
  1011. return -EINVAL;
  1012. }
  1013. if (soc_private->control_camnoc_axi_clk)
  1014. return 0;
  1015. cpas_core->camnoc_axi_port[cpas_tree_node->axi_port_idx_arr[CAM_CPAS_PORT_HLOS_DRV]]
  1016. .camnoc_bw = cpas_tree_node->camnoc_bw;
  1017. camnoc_axi_port_updated[cpas_tree_node->camnoc_axi_port_idx] = true;
  1018. return 0;
  1019. }
  1020. static int cam_cpas_camnoc_set_vote_axi_clk_rate(
  1021. struct cam_hw_info *cpas_hw,
  1022. bool *camnoc_axi_port_updated)
  1023. {
  1024. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  1025. struct cam_cpas_private_soc *soc_private =
  1026. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  1027. int i;
  1028. int rc = 0;
  1029. struct cam_cpas_axi_port *camnoc_axi_port = NULL;
  1030. uint64_t camnoc_bw;
  1031. uint64_t applied_ab = 0, applied_ib = 0;
  1032. if (soc_private->control_camnoc_axi_clk) {
  1033. rc = cam_cpas_util_set_camnoc_axi_clk_rate(cpas_hw);
  1034. if (rc)
  1035. CAM_ERR(CAM_CPAS,
  1036. "Failed in setting axi clk rate rc=%d", rc);
  1037. return rc;
  1038. }
  1039. /* Below code is executed if we just vote and do not set the clk rate
  1040. * for camnoc
  1041. */
  1042. if (cpas_core->num_camnoc_axi_ports > CAM_CPAS_MAX_AXI_PORTS) {
  1043. CAM_ERR(CAM_CPAS, "Invalid num_camnoc_axi_ports: %d",
  1044. cpas_core->num_camnoc_axi_ports);
  1045. return -EINVAL;
  1046. }
  1047. for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) {
  1048. if (camnoc_axi_port_updated[i])
  1049. camnoc_axi_port = &cpas_core->camnoc_axi_port[i];
  1050. else
  1051. continue;
  1052. CAM_DBG(CAM_PERF, "Port[%s] : camnoc_bw=%lld",
  1053. camnoc_axi_port->axi_port_name,
  1054. camnoc_axi_port->camnoc_bw);
  1055. if (camnoc_axi_port->camnoc_bw)
  1056. camnoc_bw = camnoc_axi_port->camnoc_bw;
  1057. else if (camnoc_axi_port->additional_bw)
  1058. camnoc_bw = camnoc_axi_port->additional_bw;
  1059. else if (cpas_core->streamon_clients)
  1060. camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW;
  1061. else
  1062. camnoc_bw = 0;
  1063. rc = cam_cpas_util_vote_hlos_bus_client_bw(
  1064. &camnoc_axi_port->bus_client,
  1065. 0, camnoc_bw, true, &applied_ab, &applied_ib);
  1066. CAM_DBG(CAM_CPAS,
  1067. "camnoc vote camnoc_bw[%llu] rc=%d %s",
  1068. camnoc_bw, rc, camnoc_axi_port->axi_port_name);
  1069. if (rc) {
  1070. CAM_ERR(CAM_CPAS,
  1071. "Failed in camnoc vote camnoc_bw[%llu] rc=%d",
  1072. camnoc_bw, rc);
  1073. break;
  1074. }
  1075. camnoc_axi_port->applied_bw.hlos_vote.ab = applied_ab;
  1076. camnoc_axi_port->applied_bw.hlos_vote.ib = applied_ib;
  1077. }
  1078. return rc;
  1079. }
  1080. static int cam_cpas_util_apply_client_axi_vote(
  1081. struct cam_hw_info *cpas_hw,
  1082. struct cam_cpas_client *cpas_client,
  1083. struct cam_axi_vote *axi_vote, uint32_t apply_type)
  1084. {
  1085. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  1086. struct cam_cpas_private_soc *soc_private =
  1087. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  1088. struct cam_axi_vote *con_axi_vote = NULL;
  1089. struct cam_cpas_axi_port *mnoc_axi_port = NULL;
  1090. struct cam_cpas_tree_node *curr_tree_node = NULL;
  1091. struct cam_cpas_tree_node *par_tree_node = NULL;
  1092. uint32_t transac_type;
  1093. uint32_t path_data_type;
  1094. bool mnoc_axi_port_updated[CAM_CPAS_MAX_AXI_PORTS] = {false};
  1095. bool camnoc_axi_port_updated[CAM_CPAS_MAX_AXI_PORTS] = {false};
  1096. uint64_t curr_camnoc_old = 0, par_camnoc_old = 0;
  1097. struct cam_cpas_axi_bw_info curr_mnoc_old = {0}, par_mnoc_old = {0}, curr_port_bw = {0},
  1098. applied_port_bw = {0};
  1099. int rc = 0, i = 0, drv_voting_idx;
  1100. bool apply_smart_qos = false;
  1101. bool rt_bw_updated = false;
  1102. bool camnoc_unchanged;
  1103. mutex_lock(&cpas_core->tree_lock);
  1104. if (!cpas_client->tree_node_valid) {
  1105. /*
  1106. * This is by assuming apply_client_axi_vote is called
  1107. * for these clients from only cpas_start, cpas_stop.
  1108. * not called from hw_update_axi_vote
  1109. */
  1110. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  1111. if (cpas_core->axi_port[i].bus_client.common_data.is_drv_port)
  1112. continue;
  1113. if (axi_vote->axi_path[0].mnoc_ab_bw) {
  1114. /* start case */
  1115. cpas_core->axi_port[i].additional_bw +=
  1116. CAM_CPAS_DEFAULT_AXI_BW;
  1117. } else {
  1118. /* stop case */
  1119. cpas_core->axi_port[i].additional_bw -=
  1120. CAM_CPAS_DEFAULT_AXI_BW;
  1121. }
  1122. mnoc_axi_port_updated[i] = true;
  1123. }
  1124. for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) {
  1125. if (axi_vote->axi_path[0].camnoc_bw) {
  1126. /* start case */
  1127. cpas_core->camnoc_axi_port[i].additional_bw +=
  1128. CAM_CPAS_DEFAULT_AXI_BW;
  1129. } else {
  1130. /* stop case */
  1131. cpas_core->camnoc_axi_port[i].additional_bw -=
  1132. CAM_CPAS_DEFAULT_AXI_BW;
  1133. }
  1134. camnoc_axi_port_updated[i] = true;
  1135. }
  1136. goto vote_start_clients;
  1137. }
  1138. rc = cam_cpas_axi_consolidate_path_votes(cpas_client, axi_vote);
  1139. if (rc) {
  1140. CAM_ERR(CAM_PERF, "Failed in bw consolidation, Client [%s][%d]",
  1141. cpas_client->data.identifier,
  1142. cpas_client->data.cell_index);
  1143. goto unlock_tree;
  1144. }
  1145. con_axi_vote = &cpas_client->axi_vote;
  1146. cam_cpas_dump_axi_vote_info(cpas_client, "Consolidated Vote", con_axi_vote);
  1147. /* Traverse through node tree and update bw vote values */
  1148. for (i = 0; i < con_axi_vote->num_paths; i++) {
  1149. camnoc_unchanged = false;
  1150. path_data_type = con_axi_vote->axi_path[i].path_data_type;
  1151. transac_type = con_axi_vote->axi_path[i].transac_type;
  1152. curr_tree_node = cpas_client->tree_node[path_data_type][transac_type];
  1153. drv_voting_idx = curr_tree_node->drv_voting_idx;
  1154. if (cpas_core->force_hlos_drv)
  1155. drv_voting_idx = CAM_CPAS_PORT_HLOS_DRV;
  1156. if (curr_tree_node->camnoc_bw == con_axi_vote->axi_path[i].camnoc_bw)
  1157. camnoc_unchanged = true;
  1158. curr_camnoc_old = curr_tree_node->camnoc_bw;
  1159. memcpy(&curr_mnoc_old, &curr_tree_node->bw_info[drv_voting_idx],
  1160. sizeof(struct cam_cpas_axi_bw_info));
  1161. cam_cpas_dump_tree_vote_info(curr_tree_node, "Level0 before update",
  1162. drv_voting_idx);
  1163. if (soc_private->enable_cam_ddr_drv && (con_axi_vote->axi_path[i].vote_level ==
  1164. CAM_CPAS_VOTE_LEVEL_HIGH)) {
  1165. if ((apply_type != CAM_CPAS_APPLY_TYPE_STOP) && camnoc_unchanged &&
  1166. (curr_tree_node->bw_info[drv_voting_idx].drv_vote.high.ab ==
  1167. con_axi_vote->axi_path[i].mnoc_ab_bw) &&
  1168. (curr_tree_node->bw_info[drv_voting_idx].drv_vote.high.ib ==
  1169. con_axi_vote->axi_path[i].mnoc_ib_bw))
  1170. continue;
  1171. curr_tree_node->bw_info[drv_voting_idx].drv_vote.high.ab =
  1172. con_axi_vote->axi_path[i].mnoc_ab_bw;
  1173. curr_tree_node->bw_info[drv_voting_idx].drv_vote.high.ib =
  1174. con_axi_vote->axi_path[i].mnoc_ib_bw;
  1175. curr_tree_node->bw_info[drv_voting_idx].drv_vote.low.ab = 0;
  1176. curr_tree_node->bw_info[drv_voting_idx].drv_vote.low.ib = 0;
  1177. } else {
  1178. if ((drv_voting_idx > CAM_CPAS_PORT_HLOS_DRV) &&
  1179. !cpas_core->force_hlos_drv) {
  1180. if ((apply_type != CAM_CPAS_APPLY_TYPE_STOP) && camnoc_unchanged &&
  1181. (curr_tree_node->bw_info[drv_voting_idx].drv_vote.low.ab ==
  1182. con_axi_vote->axi_path[i].mnoc_ab_bw) &&
  1183. (curr_tree_node->bw_info[drv_voting_idx].drv_vote.low.ib ==
  1184. con_axi_vote->axi_path[i].mnoc_ib_bw))
  1185. continue;
  1186. curr_tree_node->bw_info[drv_voting_idx].drv_vote.low.ab =
  1187. con_axi_vote->axi_path[i].mnoc_ab_bw;
  1188. curr_tree_node->bw_info[drv_voting_idx].drv_vote.low.ib =
  1189. con_axi_vote->axi_path[i].mnoc_ib_bw;
  1190. curr_tree_node->bw_info[drv_voting_idx].drv_vote.high.ab = 0;
  1191. curr_tree_node->bw_info[drv_voting_idx].drv_vote.high.ib = 0;
  1192. } else {
  1193. if (camnoc_unchanged &&
  1194. (curr_tree_node->bw_info[drv_voting_idx].hlos_vote.ab ==
  1195. con_axi_vote->axi_path[i].mnoc_ab_bw) &&
  1196. (curr_tree_node->bw_info[drv_voting_idx].hlos_vote.ib ==
  1197. con_axi_vote->axi_path[i].mnoc_ib_bw))
  1198. continue;
  1199. curr_tree_node->bw_info[drv_voting_idx].hlos_vote.ab =
  1200. con_axi_vote->axi_path[i].mnoc_ab_bw;
  1201. curr_tree_node->bw_info[drv_voting_idx].hlos_vote.ib =
  1202. con_axi_vote->axi_path[i].mnoc_ib_bw;
  1203. }
  1204. }
  1205. curr_tree_node->camnoc_bw = con_axi_vote->axi_path[i].camnoc_bw;
  1206. cam_cpas_dump_tree_vote_info(curr_tree_node, "Level0 after update", drv_voting_idx);
  1207. while (curr_tree_node->parent_node) {
  1208. par_tree_node = curr_tree_node->parent_node;
  1209. par_camnoc_old = par_tree_node->camnoc_bw;
  1210. memcpy(&par_mnoc_old, &par_tree_node->bw_info[drv_voting_idx],
  1211. sizeof(struct cam_cpas_axi_bw_info));
  1212. cam_cpas_dump_tree_vote_info(par_tree_node, "Parent before update",
  1213. drv_voting_idx);
  1214. /*
  1215. * Remove contribution of current node old bw from parent,
  1216. * then add new bw of current level to the parent
  1217. */
  1218. if (drv_voting_idx > CAM_CPAS_PORT_HLOS_DRV) {
  1219. par_tree_node->bw_info[drv_voting_idx].drv_vote.high.ab -=
  1220. curr_mnoc_old.drv_vote.high.ab;
  1221. par_tree_node->bw_info[drv_voting_idx].drv_vote.high.ib -=
  1222. curr_mnoc_old.drv_vote.high.ib;
  1223. par_tree_node->bw_info[drv_voting_idx].drv_vote.low.ab -=
  1224. curr_mnoc_old.drv_vote.low.ab;
  1225. par_tree_node->bw_info[drv_voting_idx].drv_vote.low.ib -=
  1226. curr_mnoc_old.drv_vote.low.ib;
  1227. par_tree_node->bw_info[drv_voting_idx].drv_vote.high.ab +=
  1228. curr_tree_node->bw_info[drv_voting_idx].drv_vote.high.ab;
  1229. par_tree_node->bw_info[drv_voting_idx].drv_vote.high.ib +=
  1230. curr_tree_node->bw_info[drv_voting_idx].drv_vote.high.ib;
  1231. par_tree_node->bw_info[drv_voting_idx].drv_vote.low.ab +=
  1232. curr_tree_node->bw_info[drv_voting_idx].drv_vote.low.ab;
  1233. par_tree_node->bw_info[drv_voting_idx].drv_vote.low.ib +=
  1234. curr_tree_node->bw_info[drv_voting_idx].drv_vote.low.ib;
  1235. } else {
  1236. par_tree_node->bw_info[drv_voting_idx].hlos_vote.ab -=
  1237. curr_mnoc_old.hlos_vote.ab;
  1238. par_tree_node->bw_info[drv_voting_idx].hlos_vote.ib -=
  1239. curr_mnoc_old.hlos_vote.ib;
  1240. par_tree_node->bw_info[drv_voting_idx].hlos_vote.ab +=
  1241. curr_tree_node->bw_info[drv_voting_idx].hlos_vote.ab;
  1242. par_tree_node->bw_info[drv_voting_idx].hlos_vote.ib +=
  1243. curr_tree_node->bw_info[drv_voting_idx].hlos_vote.ib;
  1244. }
  1245. if (par_tree_node->merge_type == CAM_CPAS_TRAFFIC_MERGE_SUM) {
  1246. par_tree_node->camnoc_bw -= curr_camnoc_old;
  1247. par_tree_node->camnoc_bw += curr_tree_node->camnoc_bw;
  1248. } else if (par_tree_node->merge_type ==
  1249. CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE) {
  1250. par_tree_node->camnoc_bw -= (curr_camnoc_old / 2);
  1251. par_tree_node->camnoc_bw += (curr_tree_node->camnoc_bw / 2);
  1252. } else {
  1253. CAM_ERR(CAM_CPAS, "Invalid Merge type");
  1254. rc = -EINVAL;
  1255. goto unlock_tree;
  1256. }
  1257. cam_cpas_dump_tree_vote_info(par_tree_node, "Parent after update",
  1258. drv_voting_idx);
  1259. if (!par_tree_node->parent_node) {
  1260. rc = cam_cpas_update_axi_vote_bw(cpas_hw, par_tree_node,
  1261. drv_voting_idx, mnoc_axi_port_updated,
  1262. camnoc_axi_port_updated);
  1263. if (rc) {
  1264. CAM_ERR(CAM_CPAS, "Update Vote failed");
  1265. goto unlock_tree;
  1266. }
  1267. }
  1268. curr_tree_node = par_tree_node;
  1269. curr_camnoc_old = par_camnoc_old;
  1270. memcpy(&curr_mnoc_old, &par_mnoc_old, sizeof(struct cam_cpas_axi_bw_info));
  1271. }
  1272. }
  1273. if (!par_tree_node) {
  1274. CAM_DBG(CAM_CPAS, "No change in BW for all paths");
  1275. rc = 0;
  1276. goto unlock_tree;
  1277. }
  1278. if (soc_private->enable_smart_qos) {
  1279. CAM_DBG(CAM_PERF, "Start QoS update for client[%s][%d]",
  1280. cpas_client->data.identifier, cpas_client->data.cell_index);
  1281. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  1282. if (mnoc_axi_port_updated[i] && cpas_core->axi_port[i].is_rt) {
  1283. rt_bw_updated = true;
  1284. break;
  1285. }
  1286. }
  1287. if (rt_bw_updated) {
  1288. apply_smart_qos = cam_cpas_calculate_smart_qos(cpas_hw);
  1289. if (apply_smart_qos && cam_cpas_is_new_rt_bw_lower(cpas_hw)) {
  1290. /*
  1291. * If new BW is low, apply QoS first and then vote,
  1292. * otherwise vote first and then apply QoS
  1293. */
  1294. CAM_DBG(CAM_PERF, "Apply Smart QoS first");
  1295. rc = cam_cpas_apply_smart_qos(cpas_hw);
  1296. if (rc) {
  1297. CAM_ERR(CAM_CPAS,
  1298. "Failed in Smart QoS rc=%d", rc);
  1299. goto unlock_tree;
  1300. }
  1301. apply_smart_qos = false;
  1302. }
  1303. }
  1304. }
  1305. vote_start_clients:
  1306. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  1307. if (mnoc_axi_port_updated[i])
  1308. mnoc_axi_port = &cpas_core->axi_port[i];
  1309. else
  1310. continue;
  1311. memcpy(&curr_port_bw, &mnoc_axi_port->curr_bw, sizeof(struct cam_cpas_axi_bw_info));
  1312. if (mnoc_axi_port->bus_client.common_data.is_drv_port) {
  1313. CAM_DBG(CAM_PERF,
  1314. "Port[%s] :DRV high [%lld %lld] low [%lld %lld] streamon_clients=%d",
  1315. mnoc_axi_port->axi_port_name,
  1316. mnoc_axi_port->curr_bw.drv_vote.high.ab,
  1317. mnoc_axi_port->curr_bw.drv_vote.high.ib,
  1318. mnoc_axi_port->curr_bw.drv_vote.low.ab,
  1319. mnoc_axi_port->curr_bw.drv_vote.low.ib,
  1320. cpas_core->streamon_clients);
  1321. if (!mnoc_axi_port->ib_bw_voting_needed) {
  1322. curr_port_bw.drv_vote.high.ib = 0;
  1323. curr_port_bw.drv_vote.low.ib = 0;
  1324. }
  1325. /* Vote bw on appropriate bus id */
  1326. rc = cam_cpas_util_vote_drv_bus_client_bw(&mnoc_axi_port->bus_client,
  1327. &curr_port_bw, &applied_port_bw);
  1328. if (rc) {
  1329. CAM_ERR(CAM_CPAS, "Failed in mnoc vote for %s rc=%d",
  1330. mnoc_axi_port->axi_port_name, rc);
  1331. goto unlock_tree;
  1332. }
  1333. /* Do start/stop/channel switch based on apply type */
  1334. if ((apply_type == CAM_CPAS_APPLY_TYPE_START) &&
  1335. !mnoc_axi_port->is_drv_started) {
  1336. rc = cam_cpas_start_drv_for_dev(mnoc_axi_port->cam_rsc_dev);
  1337. if (rc) {
  1338. CAM_ERR(CAM_CPAS, "Port[%s] failed in DRV start rc:%d",
  1339. mnoc_axi_port->axi_port_name, rc);
  1340. goto unlock_tree;
  1341. }
  1342. if (debug_drv)
  1343. CAM_INFO(CAM_CPAS, "Started rsc dev %s mnoc port:%s",
  1344. dev_name(mnoc_axi_port->cam_rsc_dev),
  1345. mnoc_axi_port->axi_port_name);
  1346. CAM_DBG(CAM_CPAS, "Started rsc dev %s mnoc port:%s",
  1347. dev_name(mnoc_axi_port->cam_rsc_dev),
  1348. mnoc_axi_port->axi_port_name);
  1349. mnoc_axi_port->is_drv_started = true;
  1350. } else if ((apply_type == CAM_CPAS_APPLY_TYPE_STOP) &&
  1351. mnoc_axi_port->is_drv_started &&
  1352. (applied_port_bw.drv_vote.high.ab == 0) &&
  1353. (applied_port_bw.drv_vote.high.ib == 0) &&
  1354. (applied_port_bw.drv_vote.low.ab == 0) &&
  1355. (applied_port_bw.drv_vote.low.ib == 0)) {
  1356. rc = cam_cpas_stop_drv_for_dev(mnoc_axi_port->cam_rsc_dev);
  1357. if (rc) {
  1358. CAM_ERR(CAM_CPAS, "Port[%s] failed in DRV stop rc:%d",
  1359. mnoc_axi_port->axi_port_name, rc);
  1360. goto unlock_tree;
  1361. }
  1362. if (debug_drv)
  1363. CAM_INFO(CAM_CPAS, "Stopped rsc dev %s mnoc port:%s",
  1364. dev_name(mnoc_axi_port->cam_rsc_dev),
  1365. mnoc_axi_port->axi_port_name);
  1366. CAM_DBG(CAM_CPAS, "Stopped rsc dev %s mnoc port:%s",
  1367. dev_name(mnoc_axi_port->cam_rsc_dev),
  1368. mnoc_axi_port->axi_port_name);
  1369. mnoc_axi_port->is_drv_started = false;
  1370. } else {
  1371. if (mnoc_axi_port->is_drv_started) {
  1372. rc = cam_cpas_drv_channel_switch_for_dev(
  1373. mnoc_axi_port->cam_rsc_dev);
  1374. if (rc) {
  1375. CAM_ERR(CAM_CPAS,
  1376. "Port[%s] failed in channel switch rc:%d",
  1377. mnoc_axi_port->axi_port_name, rc);
  1378. goto unlock_tree;
  1379. }
  1380. if (debug_drv)
  1381. CAM_INFO(CAM_CPAS,
  1382. "Channel switch for rsc dev %s mnoc port:%s",
  1383. dev_name(mnoc_axi_port->cam_rsc_dev),
  1384. mnoc_axi_port->axi_port_name);
  1385. CAM_DBG(CAM_CPAS,
  1386. "Channel switch for rsc dev %s mnoc port:%s",
  1387. dev_name(mnoc_axi_port->cam_rsc_dev),
  1388. mnoc_axi_port->axi_port_name);
  1389. }
  1390. }
  1391. } else {
  1392. CAM_DBG(CAM_PERF,
  1393. "Port[%s] :HLOS ab=%lld ib=%lld additional=%lld, streamon_clients=%d",
  1394. mnoc_axi_port->axi_port_name, mnoc_axi_port->curr_bw.hlos_vote.ab,
  1395. mnoc_axi_port->curr_bw.hlos_vote.ib, mnoc_axi_port->additional_bw,
  1396. cpas_core->streamon_clients);
  1397. if (!mnoc_axi_port->curr_bw.hlos_vote.ab) {
  1398. if (mnoc_axi_port->additional_bw)
  1399. curr_port_bw.hlos_vote.ab = mnoc_axi_port->additional_bw;
  1400. else if (cpas_core->streamon_clients)
  1401. curr_port_bw.hlos_vote.ab = CAM_CPAS_DEFAULT_AXI_BW;
  1402. else
  1403. curr_port_bw.hlos_vote.ab = 0;
  1404. }
  1405. if (!mnoc_axi_port->ib_bw_voting_needed)
  1406. curr_port_bw.hlos_vote.ib = 0;
  1407. rc = cam_cpas_util_vote_hlos_bus_client_bw(&mnoc_axi_port->bus_client,
  1408. curr_port_bw.hlos_vote.ab, curr_port_bw.hlos_vote.ib, false,
  1409. &applied_port_bw.hlos_vote.ab, &applied_port_bw.hlos_vote.ib);
  1410. if (rc) {
  1411. CAM_ERR(CAM_CPAS, "Failed in mnoc vote for %s rc=%d",
  1412. mnoc_axi_port->axi_port_name, rc);
  1413. goto unlock_tree;
  1414. }
  1415. }
  1416. memcpy(&mnoc_axi_port->applied_bw, &applied_port_bw,
  1417. sizeof(struct cam_cpas_axi_bw_info));
  1418. }
  1419. rc = cam_cpas_camnoc_set_vote_axi_clk_rate(cpas_hw, camnoc_axi_port_updated);
  1420. if (rc) {
  1421. CAM_ERR(CAM_CPAS, "Failed in setting axi clk rate rc=%d", rc);
  1422. goto unlock_tree;
  1423. }
  1424. if (soc_private->enable_smart_qos && apply_smart_qos) {
  1425. CAM_DBG(CAM_PERF, "Apply Smart QoS after bw votes");
  1426. rc = cam_cpas_apply_smart_qos(cpas_hw);
  1427. if (rc) {
  1428. CAM_ERR(CAM_CPAS, "Failed in Smart QoS rc=%d", rc);
  1429. goto unlock_tree;
  1430. }
  1431. }
  1432. unlock_tree:
  1433. mutex_unlock(&cpas_core->tree_lock);
  1434. return rc;
  1435. }
  1436. static int cam_cpas_util_apply_default_axi_vote(
  1437. struct cam_hw_info *cpas_hw, bool enable)
  1438. {
  1439. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  1440. struct cam_cpas_axi_port *axi_port = NULL;
  1441. uint64_t mnoc_ab_bw = 0, mnoc_ib_bw = 0;
  1442. int rc = 0, i = 0;
  1443. mutex_lock(&cpas_core->tree_lock);
  1444. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  1445. if ((!cpas_core->axi_port[i].bus_client.common_data.is_drv_port) &&
  1446. (!cpas_core->axi_port[i].curr_bw.hlos_vote.ab ||
  1447. !cpas_core->axi_port[i].curr_bw.hlos_vote.ib))
  1448. axi_port = &cpas_core->axi_port[i];
  1449. else
  1450. continue;
  1451. if (enable)
  1452. mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW;
  1453. else
  1454. mnoc_ib_bw = 0;
  1455. CAM_DBG(CAM_CPAS, "Port=[%s] :ab[%llu] ib[%llu]",
  1456. axi_port->axi_port_name, mnoc_ab_bw, mnoc_ib_bw);
  1457. rc = cam_cpas_util_vote_hlos_bus_client_bw(&axi_port->bus_client,
  1458. mnoc_ab_bw, mnoc_ib_bw, false, &axi_port->applied_bw.hlos_vote.ab,
  1459. &axi_port->applied_bw.hlos_vote.ib);
  1460. if (rc) {
  1461. CAM_ERR(CAM_CPAS,
  1462. "Failed in mnoc vote ab[%llu] ib[%llu] rc=%d",
  1463. mnoc_ab_bw, mnoc_ib_bw, rc);
  1464. goto unlock_tree;
  1465. }
  1466. }
  1467. unlock_tree:
  1468. mutex_unlock(&cpas_core->tree_lock);
  1469. return rc;
  1470. }
  1471. static int cam_cpas_hw_update_axi_vote(struct cam_hw_info *cpas_hw,
  1472. uint32_t client_handle, struct cam_axi_vote *client_axi_vote)
  1473. {
  1474. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  1475. struct cam_cpas_client *cpas_client = NULL;
  1476. struct cam_axi_vote *axi_vote = NULL;
  1477. uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle);
  1478. int rc = 0;
  1479. if (!client_axi_vote) {
  1480. CAM_ERR(CAM_CPAS, "Invalid arg, client_handle=%d",
  1481. client_handle);
  1482. return -EINVAL;
  1483. }
  1484. if (!CAM_CPAS_CLIENT_VALID(client_indx))
  1485. return -EINVAL;
  1486. mutex_lock(&cpas_hw->hw_mutex);
  1487. mutex_lock(&cpas_core->client_mutex[client_indx]);
  1488. axi_vote = kmemdup(client_axi_vote, sizeof(struct cam_axi_vote),
  1489. GFP_KERNEL);
  1490. if (!axi_vote) {
  1491. CAM_ERR(CAM_CPAS, "Out of memory");
  1492. mutex_unlock(&cpas_core->client_mutex[client_indx]);
  1493. mutex_unlock(&cpas_hw->hw_mutex);
  1494. return -ENOMEM;
  1495. }
  1496. cam_cpas_dump_axi_vote_info(cpas_core->cpas_client[client_indx],
  1497. "Incoming Vote", axi_vote);
  1498. cpas_client = cpas_core->cpas_client[client_indx];
  1499. if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) {
  1500. CAM_ERR(CAM_CPAS, "client=[%d][%s][%d] has not started",
  1501. client_indx, cpas_client->data.identifier,
  1502. cpas_client->data.cell_index);
  1503. rc = -EPERM;
  1504. goto unlock_client;
  1505. }
  1506. rc = cam_cpas_util_translate_client_paths(axi_vote);
  1507. if (rc) {
  1508. CAM_ERR(CAM_CPAS,
  1509. "Unable to translate per path votes rc: %d", rc);
  1510. goto unlock_client;
  1511. }
  1512. cam_cpas_dump_axi_vote_info(cpas_core->cpas_client[client_indx],
  1513. "Translated Vote", axi_vote);
  1514. rc = cam_cpas_util_apply_client_axi_vote(cpas_hw,
  1515. cpas_core->cpas_client[client_indx], axi_vote, CAM_CPAS_APPLY_TYPE_UPDATE);
  1516. /* Log an entry whenever there is an AXI update - after updating */
  1517. cam_cpas_update_monitor_array(cpas_hw, "CPAS AXI post-update",
  1518. client_indx);
  1519. unlock_client:
  1520. cam_free_clear((void *)axi_vote);
  1521. axi_vote = NULL;
  1522. mutex_unlock(&cpas_core->client_mutex[client_indx]);
  1523. mutex_unlock(&cpas_hw->hw_mutex);
  1524. return rc;
  1525. }
  1526. static int cam_cpas_util_get_ahb_level(struct cam_hw_info *cpas_hw,
  1527. struct device *dev, unsigned long freq, enum cam_vote_level *req_level)
  1528. {
  1529. struct cam_cpas_private_soc *soc_private =
  1530. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  1531. struct dev_pm_opp *opp;
  1532. unsigned int corner;
  1533. enum cam_vote_level level = CAM_SVS_VOTE;
  1534. unsigned long corner_freq = freq;
  1535. int i;
  1536. if (!dev || !req_level) {
  1537. CAM_ERR(CAM_CPAS, "Invalid params %pK, %pK", dev, req_level);
  1538. return -EINVAL;
  1539. }
  1540. opp = dev_pm_opp_find_freq_ceil(dev, &corner_freq);
  1541. if (IS_ERR(opp)) {
  1542. CAM_DBG(CAM_CPAS, "OPP Ceil not available for freq :%ld, %pK",
  1543. corner_freq, opp);
  1544. *req_level = CAM_TURBO_VOTE;
  1545. return 0;
  1546. }
  1547. corner = dev_pm_opp_get_voltage(opp);
  1548. for (i = 0; i < soc_private->num_vdd_ahb_mapping; i++)
  1549. if (corner == soc_private->vdd_ahb[i].vdd_corner)
  1550. level = soc_private->vdd_ahb[i].ahb_level;
  1551. CAM_DBG(CAM_CPAS,
  1552. "From OPP table : freq=[%ld][%ld], corner=%d, level=%d",
  1553. freq, corner_freq, corner, level);
  1554. *req_level = level;
  1555. return 0;
  1556. }
  1557. static int cam_cpas_util_apply_client_ahb_vote(struct cam_hw_info *cpas_hw,
  1558. struct cam_cpas_client *cpas_client, struct cam_ahb_vote *ahb_vote,
  1559. enum cam_vote_level *applied_level)
  1560. {
  1561. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  1562. struct cam_cpas_bus_client *ahb_bus_client = &cpas_core->ahb_bus_client;
  1563. enum cam_vote_level required_level;
  1564. enum cam_vote_level highest_level;
  1565. int i, rc = 0;
  1566. if (!ahb_bus_client->valid) {
  1567. CAM_ERR(CAM_CPAS, "AHB Bus client not valid");
  1568. return -EINVAL;
  1569. }
  1570. if (ahb_vote->type == CAM_VOTE_DYNAMIC) {
  1571. rc = cam_cpas_util_get_ahb_level(cpas_hw, cpas_client->data.dev,
  1572. ahb_vote->vote.freq, &required_level);
  1573. if (rc)
  1574. return rc;
  1575. } else {
  1576. required_level = ahb_vote->vote.level;
  1577. }
  1578. if (cpas_client->ahb_level == required_level)
  1579. return 0;
  1580. mutex_lock(&ahb_bus_client->lock);
  1581. cpas_client->ahb_level = required_level;
  1582. CAM_DBG(CAM_CPAS, "Client[%s] required level[%d], curr_level[%d]",
  1583. ahb_bus_client->common_data.name, required_level,
  1584. ahb_bus_client->curr_vote_level);
  1585. if (required_level == ahb_bus_client->curr_vote_level)
  1586. goto unlock_bus_client;
  1587. highest_level = required_level;
  1588. for (i = 0; i < cpas_core->num_clients; i++) {
  1589. if (cpas_core->cpas_client[i] && (highest_level <
  1590. cpas_core->cpas_client[i]->ahb_level))
  1591. highest_level = cpas_core->cpas_client[i]->ahb_level;
  1592. }
  1593. CAM_DBG(CAM_CPAS, "Required highest_level[%d]", highest_level);
  1594. if (!cpas_core->ahb_bus_scaling_disable) {
  1595. rc = cam_cpas_util_vote_bus_client_level(ahb_bus_client,
  1596. highest_level);
  1597. if (rc) {
  1598. CAM_ERR(CAM_CPAS, "Failed in ahb vote, level=%d, rc=%d",
  1599. highest_level, rc);
  1600. goto unlock_bus_client;
  1601. }
  1602. }
  1603. if (cpas_core->streamon_clients) {
  1604. rc = cam_soc_util_set_clk_rate_level(&cpas_hw->soc_info,
  1605. highest_level, true);
  1606. if (rc) {
  1607. CAM_ERR(CAM_CPAS,
  1608. "Failed in scaling clock rate level %d for AHB",
  1609. highest_level);
  1610. goto unlock_bus_client;
  1611. }
  1612. }
  1613. if (applied_level)
  1614. *applied_level = highest_level;
  1615. unlock_bus_client:
  1616. mutex_unlock(&ahb_bus_client->lock);
  1617. return rc;
  1618. }
  1619. static int cam_cpas_hw_update_ahb_vote(struct cam_hw_info *cpas_hw,
  1620. uint32_t client_handle, struct cam_ahb_vote *client_ahb_vote)
  1621. {
  1622. struct cam_ahb_vote ahb_vote;
  1623. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  1624. struct cam_cpas_client *cpas_client = NULL;
  1625. uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle);
  1626. int rc = 0;
  1627. if (!client_ahb_vote) {
  1628. CAM_ERR(CAM_CPAS, "Invalid input arg");
  1629. return -EINVAL;
  1630. }
  1631. ahb_vote = *client_ahb_vote;
  1632. if (ahb_vote.vote.level == 0) {
  1633. CAM_DBG(CAM_CPAS, "0 ahb vote from client %d",
  1634. client_handle);
  1635. ahb_vote.type = CAM_VOTE_ABSOLUTE;
  1636. ahb_vote.vote.level = CAM_SVS_VOTE;
  1637. }
  1638. if (!CAM_CPAS_CLIENT_VALID(client_indx))
  1639. return -EINVAL;
  1640. mutex_lock(&cpas_hw->hw_mutex);
  1641. mutex_lock(&cpas_core->client_mutex[client_indx]);
  1642. cpas_client = cpas_core->cpas_client[client_indx];
  1643. if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) {
  1644. CAM_ERR(CAM_CPAS, "client=[%d][%s][%d] has not started",
  1645. client_indx, cpas_client->data.identifier,
  1646. cpas_client->data.cell_index);
  1647. rc = -EPERM;
  1648. goto unlock_client;
  1649. }
  1650. CAM_DBG(CAM_PERF,
  1651. "client=[%d][%s][%d] : type[%d], level[%d], freq[%ld], applied[%d]",
  1652. client_indx, cpas_client->data.identifier,
  1653. cpas_client->data.cell_index, ahb_vote.type,
  1654. ahb_vote.vote.level, ahb_vote.vote.freq,
  1655. cpas_core->cpas_client[client_indx]->ahb_level);
  1656. rc = cam_cpas_util_apply_client_ahb_vote(cpas_hw,
  1657. cpas_core->cpas_client[client_indx], &ahb_vote, NULL);
  1658. unlock_client:
  1659. mutex_unlock(&cpas_core->client_mutex[client_indx]);
  1660. mutex_unlock(&cpas_hw->hw_mutex);
  1661. return rc;
  1662. }
  1663. static int cam_cpas_util_create_vote_all_paths(
  1664. struct cam_cpas_client *cpas_client,
  1665. struct cam_axi_vote *axi_vote)
  1666. {
  1667. int i, j;
  1668. uint64_t camnoc_bw, mnoc_ab_bw, mnoc_ib_bw;
  1669. struct cam_cpas_axi_per_path_bw_vote *axi_path;
  1670. if (!cpas_client || !axi_vote)
  1671. return -EINVAL;
  1672. camnoc_bw = axi_vote->axi_path[0].camnoc_bw;
  1673. mnoc_ab_bw = axi_vote->axi_path[0].mnoc_ab_bw;
  1674. mnoc_ib_bw = axi_vote->axi_path[0].mnoc_ib_bw;
  1675. axi_vote->num_paths = 0;
  1676. for (i = 0; i < CAM_CPAS_TRANSACTION_MAX; i++) {
  1677. for (j = 0; j < CAM_CPAS_PATH_DATA_MAX; j++) {
  1678. if (cpas_client->tree_node[j][i]) {
  1679. axi_path = &axi_vote->axi_path[axi_vote->num_paths];
  1680. axi_path->path_data_type = j;
  1681. axi_path->transac_type = i;
  1682. axi_path->camnoc_bw = camnoc_bw;
  1683. axi_path->mnoc_ab_bw = mnoc_ab_bw;
  1684. axi_path->mnoc_ib_bw = mnoc_ib_bw;
  1685. if (cpas_client->tree_node[j][i]->drv_voting_idx >
  1686. CAM_CPAS_PORT_HLOS_DRV)
  1687. axi_path->vote_level = CAM_CPAS_VOTE_LEVEL_LOW;
  1688. axi_vote->num_paths++;
  1689. }
  1690. }
  1691. }
  1692. return 0;
  1693. }
  1694. static int cam_cpas_hw_start(void *hw_priv, void *start_args,
  1695. uint32_t arg_size)
  1696. {
  1697. struct cam_hw_info *cpas_hw;
  1698. struct cam_cpas *cpas_core;
  1699. uint32_t client_indx;
  1700. struct cam_cpas_hw_cmd_start *cmd_hw_start;
  1701. struct cam_cpas_client *cpas_client;
  1702. struct cam_ahb_vote *ahb_vote;
  1703. struct cam_ahb_vote remove_ahb;
  1704. struct cam_axi_vote axi_vote = {0};
  1705. enum cam_vote_level applied_level = CAM_SVS_VOTE;
  1706. int rc, i = 0;
  1707. struct cam_cpas_private_soc *soc_private = NULL;
  1708. bool invalid_start = true;
  1709. int count;
  1710. if (!hw_priv || !start_args) {
  1711. CAM_ERR(CAM_CPAS, "Invalid arguments %pK %pK",
  1712. hw_priv, start_args);
  1713. return -EINVAL;
  1714. }
  1715. if (sizeof(struct cam_cpas_hw_cmd_start) != arg_size) {
  1716. CAM_ERR(CAM_CPAS, "HW_CAPS size mismatch %zd %d",
  1717. sizeof(struct cam_cpas_hw_cmd_start), arg_size);
  1718. return -EINVAL;
  1719. }
  1720. cpas_hw = (struct cam_hw_info *)hw_priv;
  1721. cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  1722. soc_private = (struct cam_cpas_private_soc *)
  1723. cpas_hw->soc_info.soc_private;
  1724. cmd_hw_start = (struct cam_cpas_hw_cmd_start *)start_args;
  1725. client_indx = CAM_CPAS_GET_CLIENT_IDX(cmd_hw_start->client_handle);
  1726. ahb_vote = cmd_hw_start->ahb_vote;
  1727. if (!ahb_vote || !cmd_hw_start->axi_vote)
  1728. return -EINVAL;
  1729. if (!ahb_vote->vote.level) {
  1730. CAM_ERR(CAM_CPAS, "Invalid vote ahb[%d]",
  1731. ahb_vote->vote.level);
  1732. return -EINVAL;
  1733. }
  1734. memcpy(&axi_vote, cmd_hw_start->axi_vote, sizeof(struct cam_axi_vote));
  1735. for (i = 0; i < axi_vote.num_paths; i++) {
  1736. if ((axi_vote.axi_path[i].camnoc_bw != 0) ||
  1737. (axi_vote.axi_path[i].mnoc_ab_bw != 0) ||
  1738. (axi_vote.axi_path[i].mnoc_ib_bw != 0)) {
  1739. invalid_start = false;
  1740. break;
  1741. }
  1742. }
  1743. if (invalid_start) {
  1744. CAM_ERR(CAM_CPAS, "Zero start vote");
  1745. return -EINVAL;
  1746. }
  1747. if (!CAM_CPAS_CLIENT_VALID(client_indx))
  1748. return -EINVAL;
  1749. mutex_lock(&cpas_hw->hw_mutex);
  1750. mutex_lock(&cpas_core->client_mutex[client_indx]);
  1751. cpas_client = cpas_core->cpas_client[client_indx];
  1752. if (!CAM_CPAS_CLIENT_REGISTERED(cpas_core, client_indx)) {
  1753. CAM_ERR(CAM_CPAS, "client=[%d] is not registered",
  1754. client_indx);
  1755. rc = -EPERM;
  1756. goto error;
  1757. }
  1758. if (CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) {
  1759. CAM_ERR(CAM_CPAS, "client=[%d][%s][%d] is in start state",
  1760. client_indx, cpas_client->data.identifier,
  1761. cpas_client->data.cell_index);
  1762. rc = -EPERM;
  1763. goto error;
  1764. }
  1765. CAM_DBG(CAM_CPAS,
  1766. "AHB :client=[%d][%s][%d] type[%d], level[%d], applied[%d]",
  1767. client_indx, cpas_client->data.identifier,
  1768. cpas_client->data.cell_index,
  1769. ahb_vote->type, ahb_vote->vote.level, cpas_client->ahb_level);
  1770. rc = cam_cpas_util_apply_client_ahb_vote(cpas_hw, cpas_client,
  1771. ahb_vote, &applied_level);
  1772. if (rc)
  1773. goto error;
  1774. cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Start Vote",
  1775. &axi_vote);
  1776. /*
  1777. * If client has indicated start bw to be applied on all paths
  1778. * of client, apply that otherwise apply whatever the client supplies
  1779. * for specific paths
  1780. */
  1781. if (axi_vote.axi_path[0].path_data_type ==
  1782. CAM_CPAS_API_PATH_DATA_STD_START) {
  1783. rc = cam_cpas_util_create_vote_all_paths(cpas_client,
  1784. &axi_vote);
  1785. } else {
  1786. rc = cam_cpas_util_translate_client_paths(&axi_vote);
  1787. }
  1788. if (rc) {
  1789. CAM_ERR(CAM_CPAS, "Unable to create or translate paths rc: %d",
  1790. rc);
  1791. goto remove_ahb_vote;
  1792. }
  1793. cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Start Translated Vote", &axi_vote);
  1794. if (cpas_core->streamon_clients == 0) {
  1795. if (cpas_core->force_hlos_drv)
  1796. soc_private->enable_cam_ddr_drv = false;
  1797. if (debug_drv)
  1798. CAM_INFO(CAM_CPAS, "DDR DRV enable:%s",
  1799. CAM_BOOL_TO_YESNO(soc_private->enable_cam_ddr_drv));
  1800. rc = cam_cpas_util_apply_default_axi_vote(cpas_hw, true);
  1801. if (rc)
  1802. goto remove_ahb_vote;
  1803. atomic_set(&cpas_core->irq_count, 1);
  1804. count = cam_soc_util_regulators_enabled(&cpas_hw->soc_info);
  1805. if (count > 0)
  1806. CAM_DBG(CAM_CPAS, "Regulators already enabled %d", count);
  1807. rc = cam_cpas_soc_enable_resources(&cpas_hw->soc_info,
  1808. applied_level);
  1809. if (rc) {
  1810. atomic_set(&cpas_core->irq_count, 0);
  1811. CAM_ERR(CAM_CPAS, "enable_resorce failed, rc=%d", rc);
  1812. goto remove_ahb_vote;
  1813. }
  1814. if (cpas_core->internal_ops.qchannel_handshake) {
  1815. rc = cpas_core->internal_ops.qchannel_handshake(cpas_hw, true, false);
  1816. if (rc) {
  1817. CAM_WARN(CAM_CPAS, "failed in qchannel_handshake rc=%d", rc);
  1818. /* Do not return error, passthrough */
  1819. rc = cpas_core->internal_ops.qchannel_handshake(cpas_hw,
  1820. true, true);
  1821. if (rc) {
  1822. CAM_ERR(CAM_CPAS,
  1823. "failed in qchannel_handshake, hw blocks may not work rc=%d",
  1824. rc);
  1825. /* Do not return error, passthrough */
  1826. }
  1827. rc = 0;
  1828. }
  1829. }
  1830. if (cpas_core->internal_ops.power_on) {
  1831. rc = cpas_core->internal_ops.power_on(cpas_hw);
  1832. if (rc) {
  1833. atomic_set(&cpas_core->irq_count, 0);
  1834. cam_cpas_soc_disable_resources(
  1835. &cpas_hw->soc_info, true, true);
  1836. CAM_ERR(CAM_CPAS,
  1837. "failed in power_on settings rc=%d",
  1838. rc);
  1839. goto remove_ahb_vote;
  1840. }
  1841. }
  1842. CAM_DBG(CAM_CPAS, "irq_count=%d\n",
  1843. atomic_read(&cpas_core->irq_count));
  1844. if (soc_private->enable_smart_qos)
  1845. cam_cpas_reset_niu_priorities(cpas_hw);
  1846. cam_smmu_reset_cb_page_fault_cnt();
  1847. cpas_hw->hw_state = CAM_HW_STATE_POWER_UP;
  1848. }
  1849. /*
  1850. * Need to apply axi vote after we enable clocks, since we need certain clocks enabled for
  1851. * drv channel switch
  1852. */
  1853. rc = cam_cpas_util_apply_client_axi_vote(cpas_hw, cpas_client, &axi_vote,
  1854. CAM_CPAS_APPLY_TYPE_START);
  1855. if (rc)
  1856. goto remove_ahb_vote;
  1857. cpas_client->started = true;
  1858. cpas_core->streamon_clients++;
  1859. CAM_DBG(CAM_CPAS, "client=[%d][%s][%d] streamon_clients=%d",
  1860. client_indx, cpas_client->data.identifier,
  1861. cpas_client->data.cell_index, cpas_core->streamon_clients);
  1862. mutex_unlock(&cpas_core->client_mutex[client_indx]);
  1863. mutex_unlock(&cpas_hw->hw_mutex);
  1864. return rc;
  1865. remove_ahb_vote:
  1866. remove_ahb.type = CAM_VOTE_ABSOLUTE;
  1867. remove_ahb.vote.level = CAM_SUSPEND_VOTE;
  1868. rc = cam_cpas_util_apply_client_ahb_vote(cpas_hw, cpas_client,
  1869. &remove_ahb, NULL);
  1870. if (rc)
  1871. CAM_ERR(CAM_CPAS, "Removing AHB vote failed, rc=%d", rc);
  1872. error:
  1873. mutex_unlock(&cpas_core->client_mutex[client_indx]);
  1874. mutex_unlock(&cpas_hw->hw_mutex);
  1875. return rc;
  1876. }
  1877. static int _check_irq_count(struct cam_cpas *cpas_core)
  1878. {
  1879. return (atomic_read(&cpas_core->irq_count) > 0) ? 0 : 1;
  1880. }
  1881. static int cam_cpas_util_validate_stop_bw(struct cam_cpas_private_soc *soc_private,
  1882. struct cam_cpas *cpas_core)
  1883. {
  1884. int i;
  1885. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  1886. if (soc_private->enable_cam_ddr_drv &&
  1887. (cpas_core->axi_port[i].bus_client.common_data.is_drv_port)) {
  1888. if ((cpas_core->axi_port[i].applied_bw.drv_vote.high.ab) ||
  1889. (cpas_core->axi_port[i].applied_bw.drv_vote.high.ib) ||
  1890. (cpas_core->axi_port[i].applied_bw.drv_vote.low.ab) ||
  1891. (cpas_core->axi_port[i].applied_bw.drv_vote.low.ib)) {
  1892. CAM_ERR(CAM_CPAS,
  1893. "port:%s Non zero DRV applied BW high[%llu %llu] low[%llu %llu]",
  1894. cpas_core->axi_port[i].axi_port_name,
  1895. cpas_core->axi_port[i].applied_bw.drv_vote.high.ab,
  1896. cpas_core->axi_port[i].applied_bw.drv_vote.high.ib,
  1897. cpas_core->axi_port[i].applied_bw.drv_vote.low.ab,
  1898. cpas_core->axi_port[i].applied_bw.drv_vote.low.ib);
  1899. return -EINVAL;
  1900. }
  1901. } else {
  1902. if (cpas_core->axi_port[i].bus_client.common_data.is_drv_port)
  1903. continue;
  1904. if ((cpas_core->axi_port[i].applied_bw.hlos_vote.ab) ||
  1905. (cpas_core->axi_port[i].applied_bw.hlos_vote.ib)) {
  1906. CAM_ERR(CAM_CPAS,
  1907. "port:%s Non zero HLOS applied BW [%llu %llu]",
  1908. cpas_core->axi_port[i].axi_port_name,
  1909. cpas_core->axi_port[i].applied_bw.hlos_vote.ab,
  1910. cpas_core->axi_port[i].applied_bw.hlos_vote.ib);
  1911. return -EINVAL;
  1912. }
  1913. }
  1914. }
  1915. return 0;
  1916. }
  1917. static int cam_cpas_hw_stop(void *hw_priv, void *stop_args,
  1918. uint32_t arg_size)
  1919. {
  1920. struct cam_hw_info *cpas_hw;
  1921. struct cam_cpas *cpas_core;
  1922. uint32_t client_indx;
  1923. struct cam_cpas_hw_cmd_stop *cmd_hw_stop;
  1924. struct cam_cpas_client *cpas_client;
  1925. struct cam_ahb_vote ahb_vote;
  1926. struct cam_axi_vote axi_vote = {0};
  1927. struct cam_cpas_private_soc *soc_private = NULL;
  1928. int rc = 0, count;
  1929. long result;
  1930. int retry_camnoc_idle = 0;
  1931. if (!hw_priv || !stop_args) {
  1932. CAM_ERR(CAM_CPAS, "Invalid arguments %pK %pK",
  1933. hw_priv, stop_args);
  1934. return -EINVAL;
  1935. }
  1936. if (sizeof(struct cam_cpas_hw_cmd_stop) != arg_size) {
  1937. CAM_ERR(CAM_CPAS, "HW_CAPS size mismatch %zd %d",
  1938. sizeof(struct cam_cpas_hw_cmd_stop), arg_size);
  1939. return -EINVAL;
  1940. }
  1941. cpas_hw = (struct cam_hw_info *)hw_priv;
  1942. cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  1943. soc_private = (struct cam_cpas_private_soc *)
  1944. cpas_hw->soc_info.soc_private;
  1945. cmd_hw_stop = (struct cam_cpas_hw_cmd_stop *)stop_args;
  1946. client_indx = CAM_CPAS_GET_CLIENT_IDX(cmd_hw_stop->client_handle);
  1947. if (!CAM_CPAS_CLIENT_VALID(client_indx))
  1948. return -EINVAL;
  1949. mutex_lock(&cpas_hw->hw_mutex);
  1950. mutex_lock(&cpas_core->client_mutex[client_indx]);
  1951. cpas_client = cpas_core->cpas_client[client_indx];
  1952. CAM_DBG(CAM_CPAS, "Client=[%d][%s][%d] streamon_clients=%d",
  1953. client_indx, cpas_client->data.identifier,
  1954. cpas_client->data.cell_index, cpas_core->streamon_clients);
  1955. if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) {
  1956. CAM_ERR(CAM_CPAS, "Client=[%d][%s][%d] is not started",
  1957. client_indx, cpas_client->data.identifier,
  1958. cpas_client->data.cell_index);
  1959. rc = -EPERM;
  1960. goto done;
  1961. }
  1962. rc = cam_cpas_util_create_vote_all_paths(cpas_client, &axi_vote);
  1963. if (rc) {
  1964. CAM_ERR(CAM_CPAS, "Unable to create per path votes rc: %d", rc);
  1965. goto done;
  1966. }
  1967. cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Stop Vote", &axi_vote);
  1968. rc = cam_cpas_util_apply_client_axi_vote(cpas_hw, cpas_client, &axi_vote,
  1969. CAM_CPAS_APPLY_TYPE_STOP);
  1970. if (rc)
  1971. goto done;
  1972. cpas_client->started = false;
  1973. cpas_core->streamon_clients--;
  1974. if (cpas_core->streamon_clients == 0) {
  1975. if (cpas_core->internal_ops.power_off) {
  1976. rc = cpas_core->internal_ops.power_off(cpas_hw);
  1977. if (rc) {
  1978. CAM_ERR(CAM_CPAS,
  1979. "failed in power_off settings rc=%d",
  1980. rc);
  1981. /* Do not return error, passthrough */
  1982. }
  1983. }
  1984. if (cpas_core->internal_ops.qchannel_handshake) {
  1985. rc = cpas_core->internal_ops.qchannel_handshake(cpas_hw, false, false);
  1986. if (rc) {
  1987. CAM_ERR(CAM_CPAS, "failed in qchannel_handshake rc=%d", rc);
  1988. retry_camnoc_idle = 1;
  1989. /* Do not return error, passthrough */
  1990. }
  1991. }
  1992. rc = cam_cpas_soc_disable_irq(&cpas_hw->soc_info);
  1993. if (rc) {
  1994. CAM_ERR(CAM_CPAS, "disable_irq failed, rc=%d", rc);
  1995. goto done;
  1996. }
  1997. /* Wait for any IRQs still being handled */
  1998. atomic_dec(&cpas_core->irq_count);
  1999. result = wait_event_timeout(cpas_core->irq_count_wq,
  2000. _check_irq_count(cpas_core), HZ);
  2001. if (result == 0) {
  2002. CAM_ERR(CAM_CPAS, "Wait failed: irq_count=%d",
  2003. atomic_read(&cpas_core->irq_count));
  2004. }
  2005. /* try again incase camnoc is still not idle */
  2006. if (cpas_core->internal_ops.qchannel_handshake &&
  2007. retry_camnoc_idle) {
  2008. rc = cpas_core->internal_ops.qchannel_handshake(cpas_hw, false, false);
  2009. if (rc) {
  2010. CAM_ERR(CAM_CPAS, "failed in qchannel_handshake rc=%d", rc);
  2011. /* Do not return error, passthrough */
  2012. }
  2013. }
  2014. rc = cam_cpas_soc_disable_resources(&cpas_hw->soc_info,
  2015. true, false);
  2016. if (rc) {
  2017. CAM_ERR(CAM_CPAS, "disable_resorce failed, rc=%d", rc);
  2018. goto done;
  2019. }
  2020. CAM_DBG(CAM_CPAS, "Disabled all the resources: irq_count=%d",
  2021. atomic_read(&cpas_core->irq_count));
  2022. count = cam_soc_util_regulators_enabled(&cpas_hw->soc_info);
  2023. if (count > 0)
  2024. CAM_WARN(CAM_CPAS,
  2025. "Client=[%d][%s][%d] qchannel shut down while top gdsc is still on %d",
  2026. client_indx, cpas_client->data.identifier,
  2027. cpas_client->data.cell_index, count);
  2028. rc = cam_cpas_util_apply_default_axi_vote(cpas_hw, false);
  2029. if (rc)
  2030. CAM_ERR(CAM_CPAS, "Failed in power off default vote rc: %d", rc);
  2031. rc = cam_cpas_util_validate_stop_bw(soc_private, cpas_core);
  2032. if (rc)
  2033. CAM_ERR(CAM_CPAS, "Invalid applied bw at stop rc: %d", rc);
  2034. cpas_hw->hw_state = CAM_HW_STATE_POWER_DOWN;
  2035. }
  2036. ahb_vote.type = CAM_VOTE_ABSOLUTE;
  2037. ahb_vote.vote.level = CAM_SUSPEND_VOTE;
  2038. rc = cam_cpas_util_apply_client_ahb_vote(cpas_hw, cpas_client,
  2039. &ahb_vote, NULL);
  2040. if (rc)
  2041. goto done;
  2042. done:
  2043. mutex_unlock(&cpas_core->client_mutex[client_indx]);
  2044. mutex_unlock(&cpas_hw->hw_mutex);
  2045. return rc;
  2046. }
  2047. static int cam_cpas_hw_init(void *hw_priv, void *init_hw_args,
  2048. uint32_t arg_size)
  2049. {
  2050. struct cam_hw_info *cpas_hw;
  2051. struct cam_cpas *cpas_core;
  2052. int rc = 0;
  2053. if (!hw_priv || !init_hw_args) {
  2054. CAM_ERR(CAM_CPAS, "Invalid arguments %pK %pK",
  2055. hw_priv, init_hw_args);
  2056. return -EINVAL;
  2057. }
  2058. if (sizeof(struct cam_cpas_hw_caps) != arg_size) {
  2059. CAM_ERR(CAM_CPAS, "INIT HW size mismatch %zd %d",
  2060. sizeof(struct cam_cpas_hw_caps), arg_size);
  2061. return -EINVAL;
  2062. }
  2063. cpas_hw = (struct cam_hw_info *)hw_priv;
  2064. cpas_core = (struct cam_cpas *)cpas_hw->core_info;
  2065. if (cpas_core->internal_ops.init_hw_version) {
  2066. rc = cpas_core->internal_ops.init_hw_version(cpas_hw,
  2067. (struct cam_cpas_hw_caps *)init_hw_args);
  2068. }
  2069. return rc;
  2070. }
  2071. static int cam_cpas_hw_register_client(struct cam_hw_info *cpas_hw,
  2072. struct cam_cpas_register_params *register_params)
  2073. {
  2074. int rc;
  2075. char client_name[CAM_HW_IDENTIFIER_LENGTH + 3];
  2076. int32_t client_indx = -1;
  2077. struct cam_cpas *cpas_core = (struct cam_cpas *)cpas_hw->core_info;
  2078. struct cam_cpas_private_soc *soc_private =
  2079. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  2080. if ((!register_params) ||
  2081. (strlen(register_params->identifier) < 1)) {
  2082. CAM_ERR(CAM_CPAS, "Invalid cpas client identifier");
  2083. return -EINVAL;
  2084. }
  2085. CAM_DBG(CAM_CPAS, "Register params : identifier=%s, cell_index=%d",
  2086. register_params->identifier, register_params->cell_index);
  2087. if (soc_private->client_id_based)
  2088. snprintf(client_name, sizeof(client_name), "%s%d",
  2089. register_params->identifier,
  2090. register_params->cell_index);
  2091. else
  2092. snprintf(client_name, sizeof(client_name), "%s",
  2093. register_params->identifier);
  2094. mutex_lock(&cpas_hw->hw_mutex);
  2095. rc = cam_common_util_get_string_index(soc_private->client_name,
  2096. soc_private->num_clients, client_name, &client_indx);
  2097. mutex_lock(&cpas_core->client_mutex[client_indx]);
  2098. if (rc || !CAM_CPAS_CLIENT_VALID(client_indx) ||
  2099. CAM_CPAS_CLIENT_REGISTERED(cpas_core, client_indx)) {
  2100. CAM_ERR(CAM_CPAS,
  2101. "Inval client %s %d : %d %d %pK %d",
  2102. register_params->identifier,
  2103. register_params->cell_index,
  2104. CAM_CPAS_CLIENT_VALID(client_indx),
  2105. CAM_CPAS_CLIENT_REGISTERED(cpas_core, client_indx),
  2106. cpas_core->cpas_client[client_indx], rc);
  2107. mutex_unlock(&cpas_core->client_mutex[client_indx]);
  2108. mutex_unlock(&cpas_hw->hw_mutex);
  2109. return -EPERM;
  2110. }
  2111. register_params->client_handle =
  2112. CAM_CPAS_GET_CLIENT_HANDLE(client_indx);
  2113. memcpy(&cpas_core->cpas_client[client_indx]->data, register_params,
  2114. sizeof(struct cam_cpas_register_params));
  2115. cpas_core->registered_clients++;
  2116. cpas_core->cpas_client[client_indx]->registered = true;
  2117. CAM_DBG(CAM_CPAS, "client=[%d][%s][%d], registered_clients=%d",
  2118. client_indx,
  2119. cpas_core->cpas_client[client_indx]->data.identifier,
  2120. cpas_core->cpas_client[client_indx]->data.cell_index,
  2121. cpas_core->registered_clients);
  2122. mutex_unlock(&cpas_core->client_mutex[client_indx]);
  2123. mutex_unlock(&cpas_hw->hw_mutex);
  2124. return 0;
  2125. }
  2126. static int cam_cpas_hw_unregister_client(struct cam_hw_info *cpas_hw,
  2127. uint32_t client_handle)
  2128. {
  2129. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  2130. uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle);
  2131. int rc = 0;
  2132. if (!CAM_CPAS_CLIENT_VALID(client_indx))
  2133. return -EINVAL;
  2134. mutex_lock(&cpas_hw->hw_mutex);
  2135. mutex_lock(&cpas_core->client_mutex[client_indx]);
  2136. if (!CAM_CPAS_CLIENT_REGISTERED(cpas_core, client_indx)) {
  2137. CAM_ERR(CAM_CPAS, "Client=[%d][%s][%d] not registered",
  2138. client_indx,
  2139. cpas_core->cpas_client[client_indx]->data.identifier,
  2140. cpas_core->cpas_client[client_indx]->data.cell_index);
  2141. rc = -EPERM;
  2142. goto done;
  2143. }
  2144. if (CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) {
  2145. CAM_ERR(CAM_CPAS, "Client=[%d][%s][%d] is not stopped",
  2146. client_indx,
  2147. cpas_core->cpas_client[client_indx]->data.identifier,
  2148. cpas_core->cpas_client[client_indx]->data.cell_index);
  2149. rc = -EPERM;
  2150. goto done;
  2151. }
  2152. CAM_DBG(CAM_CPAS, "client=[%d][%s][%d], registered_clients=%d",
  2153. client_indx,
  2154. cpas_core->cpas_client[client_indx]->data.identifier,
  2155. cpas_core->cpas_client[client_indx]->data.cell_index,
  2156. cpas_core->registered_clients);
  2157. cpas_core->cpas_client[client_indx]->registered = false;
  2158. cpas_core->registered_clients--;
  2159. done:
  2160. mutex_unlock(&cpas_core->client_mutex[client_indx]);
  2161. mutex_unlock(&cpas_hw->hw_mutex);
  2162. return rc;
  2163. }
  2164. static int cam_cpas_hw_get_hw_info(void *hw_priv,
  2165. void *get_hw_cap_args, uint32_t arg_size)
  2166. {
  2167. struct cam_hw_info *cpas_hw;
  2168. struct cam_cpas *cpas_core;
  2169. struct cam_cpas_hw_caps *hw_caps;
  2170. struct cam_cpas_private_soc *soc_private;
  2171. if (!hw_priv || !get_hw_cap_args) {
  2172. CAM_ERR(CAM_CPAS, "Invalid arguments %pK %pK",
  2173. hw_priv, get_hw_cap_args);
  2174. return -EINVAL;
  2175. }
  2176. if (sizeof(struct cam_cpas_hw_caps) != arg_size) {
  2177. CAM_ERR(CAM_CPAS, "HW_CAPS size mismatch %zd %d",
  2178. sizeof(struct cam_cpas_hw_caps), arg_size);
  2179. return -EINVAL;
  2180. }
  2181. cpas_hw = (struct cam_hw_info *)hw_priv;
  2182. cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  2183. hw_caps = (struct cam_cpas_hw_caps *)get_hw_cap_args;
  2184. *hw_caps = cpas_core->hw_caps;
  2185. /*Extract Fuse Info*/
  2186. soc_private = (struct cam_cpas_private_soc *)
  2187. cpas_hw->soc_info.soc_private;
  2188. hw_caps->fuse_info = soc_private->fuse_info;
  2189. CAM_INFO(CAM_CPAS, "fuse info->num_fuses %d",
  2190. hw_caps->fuse_info.num_fuses);
  2191. return 0;
  2192. }
  2193. static int cam_cpas_log_vote(struct cam_hw_info *cpas_hw, bool ddr_only)
  2194. {
  2195. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  2196. struct cam_cpas_private_soc *soc_private =
  2197. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  2198. uint32_t i;
  2199. struct cam_cpas_tree_node *curr_node;
  2200. struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
  2201. if ((cpas_core->streamon_clients > 0) && soc_private->enable_smart_qos && !ddr_only)
  2202. cam_cpas_print_smart_qos_priority(cpas_hw);
  2203. /*
  2204. * First print rpmh registers as early as possible to catch nearest
  2205. * state of rpmh after an issue (overflow) occurs.
  2206. */
  2207. if ((cpas_core->streamon_clients > 0) &&
  2208. (cpas_core->regbase_index[CAM_CPAS_REG_RPMH] != -1)) {
  2209. int reg_base_index =
  2210. cpas_core->regbase_index[CAM_CPAS_REG_RPMH];
  2211. void __iomem *rpmh_base =
  2212. soc_info->reg_map[reg_base_index].mem_base;
  2213. uint32_t offset_fe, offset_be;
  2214. uint32_t fe_val, be_val;
  2215. uint32_t *rpmh_info = &soc_private->rpmh_info[0];
  2216. uint32_t ddr_bcm_index =
  2217. soc_private->rpmh_info[CAM_RPMH_BCM_DDR_INDEX];
  2218. uint32_t mnoc_bcm_index =
  2219. soc_private->rpmh_info[CAM_RPMH_BCM_MNOC_INDEX];
  2220. /*
  2221. * print 12 registers from 0x4, 0x800 offsets -
  2222. * this will give ddr, mmnoc and other BCM info.
  2223. * i=0 for DDR, i=4 for mnoc, but double check for each chipset.
  2224. */
  2225. for (i = 0; i < rpmh_info[CAM_RPMH_NUMBER_OF_BCMS]; i++) {
  2226. if ((!cpas_core->full_state_dump) &&
  2227. (i != ddr_bcm_index) &&
  2228. (i != mnoc_bcm_index))
  2229. continue;
  2230. offset_fe = rpmh_info[CAM_RPMH_BCM_FE_OFFSET] +
  2231. (i * 0x4);
  2232. offset_be = rpmh_info[CAM_RPMH_BCM_BE_OFFSET] +
  2233. (i * 0x4);
  2234. fe_val = cam_io_r_mb(rpmh_base + offset_fe);
  2235. be_val = cam_io_r_mb(rpmh_base + offset_be);
  2236. CAM_INFO(CAM_CPAS,
  2237. "i=%d, FE[offset=0x%x, value=0x%x] BE[offset=0x%x, value=0x%x]",
  2238. i, offset_fe, fe_val, offset_be, be_val);
  2239. }
  2240. }
  2241. if (ddr_only)
  2242. return 0;
  2243. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  2244. if (cpas_core->axi_port[i].bus_client.common_data.is_drv_port) {
  2245. CAM_INFO(CAM_PERF,
  2246. "[%s] DRV applied: high [%llu %llu] low[%llu %llu] new: high [%llu %llu] low [%llu %llu]",
  2247. cpas_core->axi_port[i].axi_port_name,
  2248. cpas_core->axi_port[i].applied_bw.drv_vote.high.ab,
  2249. cpas_core->axi_port[i].applied_bw.drv_vote.high.ib,
  2250. cpas_core->axi_port[i].applied_bw.drv_vote.low.ab,
  2251. cpas_core->axi_port[i].applied_bw.drv_vote.low.ib,
  2252. cpas_core->axi_port[i].curr_bw.drv_vote.high.ab,
  2253. cpas_core->axi_port[i].curr_bw.drv_vote.high.ib,
  2254. cpas_core->axi_port[i].curr_bw.drv_vote.low.ab,
  2255. cpas_core->axi_port[i].curr_bw.drv_vote.low.ib);
  2256. } else {
  2257. CAM_INFO(CAM_PERF, "Port %s HLOS applied [%llu %llu] new [%llu %llu]",
  2258. cpas_core->axi_port[i].axi_port_name,
  2259. cpas_core->axi_port[i].applied_bw.hlos_vote.ab,
  2260. cpas_core->axi_port[i].applied_bw.hlos_vote.ib,
  2261. cpas_core->axi_port[i].curr_bw.hlos_vote.ab,
  2262. cpas_core->axi_port[i].curr_bw.hlos_vote.ib);
  2263. }
  2264. }
  2265. if (soc_private->control_camnoc_axi_clk) {
  2266. CAM_INFO(CAM_CPAS, "applied camnoc axi clk[%lld]",
  2267. cpas_core->applied_camnoc_axi_rate);
  2268. } else {
  2269. for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) {
  2270. CAM_INFO(CAM_CPAS,
  2271. "[%s] ab_bw[%lld] ib_bw[%lld] additional_bw[%lld] applied_ab[%lld] applied_ib[%lld]",
  2272. cpas_core->camnoc_axi_port[i].axi_port_name,
  2273. cpas_core->camnoc_axi_port[i].curr_bw.hlos_vote.ab,
  2274. cpas_core->camnoc_axi_port[i].curr_bw.hlos_vote.ib,
  2275. cpas_core->camnoc_axi_port[i].additional_bw,
  2276. cpas_core->camnoc_axi_port[i].applied_bw.hlos_vote.ab,
  2277. cpas_core->camnoc_axi_port[i].applied_bw.hlos_vote.ib);
  2278. }
  2279. }
  2280. CAM_INFO(CAM_CPAS, "ahb client curr vote level[%d]",
  2281. cpas_core->ahb_bus_client.curr_vote_level);
  2282. if (!cpas_core->full_state_dump) {
  2283. CAM_DBG(CAM_CPAS, "CPAS full state dump not enabled");
  2284. return 0;
  2285. }
  2286. /* This will traverse through all nodes in the tree and print stats*/
  2287. for (i = 0; i < CAM_CPAS_MAX_TREE_NODES; i++) {
  2288. if (!soc_private->tree_node[i])
  2289. continue;
  2290. curr_node = soc_private->tree_node[i];
  2291. CAM_INFO(CAM_CPAS,
  2292. "[%s] Cell[%d] level[%d] PortIdx[%d][%d] camnoc_bw[%d %d %lld %lld] mnoc_bw[%lld %lld]",
  2293. curr_node->node_name, curr_node->cell_idx,
  2294. curr_node->level_idx,
  2295. curr_node->axi_port_idx_arr[CAM_CPAS_PORT_HLOS_DRV],
  2296. curr_node->camnoc_axi_port_idx,
  2297. curr_node->camnoc_max_needed,
  2298. curr_node->bus_width_factor,
  2299. curr_node->camnoc_bw,
  2300. curr_node->camnoc_bw * curr_node->bus_width_factor,
  2301. curr_node->bw_info[CAM_CPAS_PORT_HLOS_DRV].hlos_vote.ab,
  2302. curr_node->bw_info[CAM_CPAS_PORT_HLOS_DRV].hlos_vote.ib);
  2303. if (!soc_private->enable_cam_ddr_drv)
  2304. continue;
  2305. CAM_INFO(CAM_CPAS,
  2306. "DRV PortIdx[%d][%d][%d] mnoc_bw DRV_0: [high[%lld %lld] low[%lld %lld]] DRV_1: [high[%lld %lld] low[%lld %lld]] DRV_2: [high[%lld %lld] low[%lld %lld]]",
  2307. curr_node->axi_port_idx_arr[CAM_CPAS_PORT_DRV_0],
  2308. curr_node->axi_port_idx_arr[CAM_CPAS_PORT_DRV_1],
  2309. curr_node->axi_port_idx_arr[CAM_CPAS_PORT_DRV_2],
  2310. curr_node->bw_info[CAM_CPAS_PORT_DRV_0].drv_vote.high.ab,
  2311. curr_node->bw_info[CAM_CPAS_PORT_DRV_0].drv_vote.high.ib,
  2312. curr_node->bw_info[CAM_CPAS_PORT_DRV_0].drv_vote.low.ab,
  2313. curr_node->bw_info[CAM_CPAS_PORT_DRV_0].drv_vote.low.ib,
  2314. curr_node->bw_info[CAM_CPAS_PORT_DRV_1].drv_vote.high.ab,
  2315. curr_node->bw_info[CAM_CPAS_PORT_DRV_1].drv_vote.high.ib,
  2316. curr_node->bw_info[CAM_CPAS_PORT_DRV_1].drv_vote.low.ab,
  2317. curr_node->bw_info[CAM_CPAS_PORT_DRV_1].drv_vote.low.ib,
  2318. curr_node->bw_info[CAM_CPAS_PORT_DRV_2].drv_vote.high.ab,
  2319. curr_node->bw_info[CAM_CPAS_PORT_DRV_2].drv_vote.high.ib,
  2320. curr_node->bw_info[CAM_CPAS_PORT_DRV_2].drv_vote.low.ab,
  2321. curr_node->bw_info[CAM_CPAS_PORT_DRV_2].drv_vote.low.ib);
  2322. }
  2323. cam_cpas_dump_monitor_array(cpas_hw);
  2324. if (cpas_core->internal_ops.print_poweron_settings)
  2325. cpas_core->internal_ops.print_poweron_settings(cpas_hw);
  2326. else
  2327. CAM_DBG(CAM_CPAS, "No ops for print_poweron_settings");
  2328. return 0;
  2329. }
  2330. static void cam_cpas_update_monitor_array(struct cam_hw_info *cpas_hw,
  2331. const char *identifier_string, int32_t identifier_value)
  2332. {
  2333. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  2334. struct cam_camnoc_info *camnoc_info =
  2335. (struct cam_camnoc_info *) cpas_core->camnoc_info;
  2336. struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
  2337. struct cam_cpas_private_soc *soc_private =
  2338. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  2339. struct cam_cpas_monitor *entry;
  2340. int iterator;
  2341. int i, j = 0;
  2342. int reg_camnoc = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC];
  2343. uint32_t val = 0;
  2344. if (!camnoc_info) {
  2345. CAM_ERR(CAM_CPAS, "Invalid camnoc info for hw_version: 0x%x",
  2346. cpas_hw->soc_info.hw_version);
  2347. return;
  2348. }
  2349. CAM_CPAS_INC_MONITOR_HEAD(&cpas_core->monitor_head, &iterator);
  2350. entry = &cpas_core->monitor_entries[iterator];
  2351. CAM_GET_TIMESTAMP(entry->timestamp);
  2352. strlcpy(entry->identifier_string, identifier_string,
  2353. sizeof(entry->identifier_string));
  2354. entry->identifier_value = identifier_value;
  2355. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  2356. entry->axi_info[i].axi_port_name = cpas_core->axi_port[i].axi_port_name;
  2357. memcpy(&entry->axi_info[i].curr_bw, &cpas_core->axi_port[i].curr_bw,
  2358. sizeof(struct cam_cpas_axi_bw_info));
  2359. entry->axi_info[i].camnoc_bw = cpas_core->axi_port[i].camnoc_bw;
  2360. memcpy(&entry->axi_info[i].applied_bw, &cpas_core->axi_port[i].applied_bw,
  2361. sizeof(struct cam_cpas_axi_bw_info));
  2362. entry->axi_info[i].is_drv_started = cpas_core->axi_port[i].is_drv_started;
  2363. }
  2364. entry->applied_camnoc_clk = cpas_core->applied_camnoc_axi_rate;
  2365. entry->applied_ahb_level = cpas_core->ahb_bus_client.curr_vote_level;
  2366. if ((cpas_core->streamon_clients > 0) &&
  2367. (cpas_core->regbase_index[CAM_CPAS_REG_RPMH] != -1) &&
  2368. soc_private->rpmh_info[CAM_RPMH_NUMBER_OF_BCMS]) {
  2369. int reg_base_index =
  2370. cpas_core->regbase_index[CAM_CPAS_REG_RPMH];
  2371. void __iomem *rpmh_base =
  2372. soc_info->reg_map[reg_base_index].mem_base;
  2373. uint32_t fe_ddr_offset =
  2374. soc_private->rpmh_info[CAM_RPMH_BCM_FE_OFFSET] +
  2375. (0x4 * soc_private->rpmh_info[CAM_RPMH_BCM_DDR_INDEX]);
  2376. uint32_t fe_mnoc_offset =
  2377. soc_private->rpmh_info[CAM_RPMH_BCM_FE_OFFSET] +
  2378. (0x4 * soc_private->rpmh_info[CAM_RPMH_BCM_MNOC_INDEX]);
  2379. uint32_t be_ddr_offset =
  2380. soc_private->rpmh_info[CAM_RPMH_BCM_BE_OFFSET] +
  2381. (0x4 * soc_private->rpmh_info[CAM_RPMH_BCM_DDR_INDEX]);
  2382. uint32_t be_mnoc_offset =
  2383. soc_private->rpmh_info[CAM_RPMH_BCM_BE_OFFSET] +
  2384. (0x4 * soc_private->rpmh_info[CAM_RPMH_BCM_MNOC_INDEX]);
  2385. uint32_t be_shub_offset =
  2386. soc_private->rpmh_info[CAM_RPMH_BCM_BE_OFFSET] +
  2387. (0x4 * 1); /* i=1 for SHUB, hardcode for now */
  2388. /*
  2389. * 0x4, 0x800 - DDR
  2390. * 0x800, 0x810 - mmnoc
  2391. */
  2392. entry->fe_ddr = cam_io_r_mb(rpmh_base + fe_ddr_offset);
  2393. entry->fe_mnoc = cam_io_r_mb(rpmh_base + fe_mnoc_offset);
  2394. entry->be_ddr = cam_io_r_mb(rpmh_base + be_ddr_offset);
  2395. entry->be_mnoc = cam_io_r_mb(rpmh_base + be_mnoc_offset);
  2396. entry->be_shub = cam_io_r_mb(rpmh_base + be_shub_offset);
  2397. CAM_DBG(CAM_CPAS,
  2398. "fe_ddr=0x%x, fe_mnoc=0x%x, be_ddr=0x%x, be_mnoc=0x%x",
  2399. entry->fe_ddr, entry->fe_mnoc, entry->be_ddr,
  2400. entry->be_mnoc);
  2401. }
  2402. for (i = 0; i < camnoc_info->specific_size; i++) {
  2403. if ((!camnoc_info->specific[i].enable) ||
  2404. (!camnoc_info->specific[i].maxwr_low.enable))
  2405. continue;
  2406. if (j >= CAM_CAMNOC_FILL_LVL_REG_INFO_MAX) {
  2407. CAM_WARN(CAM_CPAS,
  2408. "CPAS monitor reg info buffer full, max : %d",
  2409. j);
  2410. break;
  2411. }
  2412. entry->camnoc_port_name[j] = camnoc_info->specific[i].port_name;
  2413. val = cam_io_r_mb(soc_info->reg_map[reg_camnoc].mem_base +
  2414. camnoc_info->specific[i].maxwr_low.offset);
  2415. entry->camnoc_fill_level[j] = val;
  2416. j++;
  2417. }
  2418. entry->num_camnoc_lvl_regs = j;
  2419. if (soc_private->enable_smart_qos) {
  2420. for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) {
  2421. struct cam_cpas_tree_node *niu_node =
  2422. soc_private->smart_qos_info->rt_wr_niu_node[i];
  2423. entry->rt_wr_niu_pri_lut_high[i] =
  2424. cam_io_r_mb(soc_info->reg_map[reg_camnoc].mem_base +
  2425. niu_node->pri_lut_high_offset);
  2426. entry->rt_wr_niu_pri_lut_low[i] =
  2427. cam_io_r_mb(soc_info->reg_map[reg_camnoc].mem_base +
  2428. niu_node->pri_lut_low_offset);
  2429. }
  2430. }
  2431. }
  2432. static void cam_cpas_dump_monitor_array(
  2433. struct cam_hw_info *cpas_hw)
  2434. {
  2435. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  2436. struct cam_cpas_private_soc *soc_private =
  2437. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  2438. int i = 0, j = 0;
  2439. int64_t state_head = 0;
  2440. uint32_t index, num_entries, oldest_entry;
  2441. uint64_t ms, hrs, min, sec;
  2442. struct cam_cpas_monitor *entry;
  2443. struct timespec64 curr_timestamp;
  2444. char log_buf[CAM_CPAS_LOG_BUF_LEN];
  2445. size_t len;
  2446. if (!cpas_core->full_state_dump)
  2447. return;
  2448. state_head = atomic64_read(&cpas_core->monitor_head);
  2449. if (state_head == -1) {
  2450. CAM_WARN(CAM_CPAS, "No valid entries in cpas monitor array");
  2451. return;
  2452. } else if (state_head < CAM_CPAS_MONITOR_MAX_ENTRIES) {
  2453. num_entries = state_head;
  2454. oldest_entry = 0;
  2455. } else {
  2456. num_entries = CAM_CPAS_MONITOR_MAX_ENTRIES;
  2457. div_u64_rem(state_head + 1,
  2458. CAM_CPAS_MONITOR_MAX_ENTRIES, &oldest_entry);
  2459. }
  2460. CAM_GET_TIMESTAMP(curr_timestamp);
  2461. CAM_CONVERT_TIMESTAMP_FORMAT(curr_timestamp, hrs, min, sec, ms);
  2462. CAM_INFO(CAM_CPAS,
  2463. "**** %llu:%llu:%llu.%llu : ======== Dumping monitor information ===========",
  2464. hrs, min, sec, ms);
  2465. index = oldest_entry;
  2466. for (i = 0; i < num_entries; i++) {
  2467. entry = &cpas_core->monitor_entries[index];
  2468. CAM_CONVERT_TIMESTAMP_FORMAT(entry->timestamp, hrs, min, sec, ms);
  2469. log_buf[0] = '\0';
  2470. len = 0;
  2471. CAM_INFO(CAM_CPAS,
  2472. "**** %llu:%llu:%llu.%llu : Index[%d] Identifier[%s][%d] camnoc=%lld, ahb=%d",
  2473. hrs, min, sec, ms,
  2474. index,
  2475. entry->identifier_string, entry->identifier_value,
  2476. entry->applied_camnoc_clk, entry->applied_ahb_level);
  2477. for (j = 0; j < cpas_core->num_axi_ports; j++) {
  2478. if ((entry->axi_info[j].applied_bw.vote_type == CAM_CPAS_VOTE_TYPE_DRV) &&
  2479. !cpas_core->force_hlos_drv)
  2480. CAM_INFO(CAM_CPAS,
  2481. "BW [%s] : DRV started:%s high=[%lld %lld], low=[%lld %lld], camnoc=%lld",
  2482. entry->axi_info[j].axi_port_name,
  2483. CAM_BOOL_TO_YESNO(entry->axi_info[j].is_drv_started),
  2484. entry->axi_info[j].applied_bw.drv_vote.high.ab,
  2485. entry->axi_info[j].applied_bw.drv_vote.high.ib,
  2486. entry->axi_info[j].applied_bw.drv_vote.low.ab,
  2487. entry->axi_info[j].applied_bw.drv_vote.low.ib,
  2488. entry->axi_info[j].camnoc_bw);
  2489. else
  2490. CAM_INFO(CAM_CPAS,
  2491. "BW [%s] : HLOS ab=%lld, ib=%lld, DRV high_ab=%lld, high_ib=%lld, low_ab=%lld, low_ib=%lld, camnoc=%lld",
  2492. entry->axi_info[j].axi_port_name,
  2493. entry->axi_info[j].applied_bw.hlos_vote.ab,
  2494. entry->axi_info[j].applied_bw.hlos_vote.ib,
  2495. entry->axi_info[j].camnoc_bw);
  2496. }
  2497. if (cpas_core->regbase_index[CAM_CPAS_REG_RPMH] != -1) {
  2498. CAM_INFO(CAM_CPAS,
  2499. "fe_ddr=0x%x, fe_mnoc=0x%x, be_ddr=0x%x, be_mnoc=0x%x, be_shub=0x%x",
  2500. entry->fe_ddr, entry->fe_mnoc,
  2501. entry->be_ddr, entry->be_mnoc, entry->be_shub);
  2502. }
  2503. for (j = 0; j < entry->num_camnoc_lvl_regs; j++) {
  2504. len += scnprintf((log_buf + len),
  2505. (CAM_CPAS_LOG_BUF_LEN - len), " %s:[%d %d]",
  2506. entry->camnoc_port_name[j],
  2507. (entry->camnoc_fill_level[j] & 0x7FF),
  2508. (entry->camnoc_fill_level[j] & 0x7F0000) >> 16);
  2509. }
  2510. CAM_INFO(CAM_CPAS, "CAMNOC REG[Queued Pending] %s", log_buf);
  2511. if (soc_private->enable_smart_qos) {
  2512. len = 0;
  2513. for (j = 0; j < soc_private->smart_qos_info->num_rt_wr_nius; j++) {
  2514. struct cam_cpas_tree_node *niu_node =
  2515. soc_private->smart_qos_info->rt_wr_niu_node[j];
  2516. len += scnprintf((log_buf + len),
  2517. (CAM_CPAS_LOG_BUF_LEN - len), " [%s: high 0x%x low 0x%x]",
  2518. niu_node->node_name,
  2519. entry->rt_wr_niu_pri_lut_high[j],
  2520. entry->rt_wr_niu_pri_lut_low[j]);
  2521. }
  2522. CAM_INFO(CAM_CPAS, "SmartQoS [Node: Pri_lut] %s", log_buf);
  2523. }
  2524. index = (index + 1) % CAM_CPAS_MONITOR_MAX_ENTRIES;
  2525. }
  2526. }
  2527. static int cam_cpas_log_event(struct cam_hw_info *cpas_hw,
  2528. const char *identifier_string, int32_t identifier_value)
  2529. {
  2530. cam_cpas_update_monitor_array(cpas_hw, identifier_string,
  2531. identifier_value);
  2532. return 0;
  2533. }
  2534. static int cam_cpas_select_qos(struct cam_hw_info *cpas_hw,
  2535. uint32_t selection_mask)
  2536. {
  2537. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  2538. int rc = 0;
  2539. mutex_lock(&cpas_hw->hw_mutex);
  2540. if (cpas_hw->hw_state == CAM_HW_STATE_POWER_UP) {
  2541. CAM_ERR(CAM_CPAS,
  2542. "Hw already in power up state, can't change QoS settings");
  2543. rc = -EINVAL;
  2544. goto done;
  2545. }
  2546. if (cpas_core->internal_ops.setup_qos_settings) {
  2547. rc = cpas_core->internal_ops.setup_qos_settings(cpas_hw,
  2548. selection_mask);
  2549. if (rc)
  2550. CAM_ERR(CAM_CPAS, "Failed in changing QoS %d", rc);
  2551. } else {
  2552. CAM_WARN(CAM_CPAS, "No ops for qos_settings");
  2553. }
  2554. done:
  2555. mutex_unlock(&cpas_hw->hw_mutex);
  2556. return rc;
  2557. }
  2558. static int cam_cpas_activate_cache(
  2559. struct cam_hw_info *cpas_hw,
  2560. struct cam_sys_cache_info *cache_info)
  2561. {
  2562. int rc = 0;
  2563. mutex_lock(&cpas_hw->hw_mutex);
  2564. cache_info->ref_cnt++;
  2565. if (cache_info->ref_cnt > 1) {
  2566. mutex_unlock(&cpas_hw->hw_mutex);
  2567. CAM_DBG(CAM_CPAS, "Cache: %s has already been activated cnt: %d",
  2568. cache_info->name, cache_info->ref_cnt);
  2569. return rc;
  2570. }
  2571. rc = llcc_slice_activate(cache_info->slic_desc);
  2572. if (rc) {
  2573. CAM_ERR(CAM_CPAS, "Failed to activate cache:%s",
  2574. cache_info->name);
  2575. goto end;
  2576. }
  2577. mutex_unlock(&cpas_hw->hw_mutex);
  2578. CAM_DBG(CAM_CPAS, "Activated cache:%s", cache_info->name);
  2579. return rc;
  2580. end:
  2581. cache_info->ref_cnt--;
  2582. mutex_unlock(&cpas_hw->hw_mutex);
  2583. return rc;
  2584. }
  2585. static int cam_cpas_deactivate_cache(
  2586. struct cam_hw_info *cpas_hw,
  2587. struct cam_sys_cache_info *cache_info)
  2588. {
  2589. int rc = 0;
  2590. mutex_lock(&cpas_hw->hw_mutex);
  2591. if (!cache_info->ref_cnt) {
  2592. mutex_unlock(&cpas_hw->hw_mutex);
  2593. CAM_ERR(CAM_CPAS, "Unbalanced deactivate");
  2594. return -EFAULT;
  2595. }
  2596. cache_info->ref_cnt--;
  2597. if (cache_info->ref_cnt) {
  2598. mutex_unlock(&cpas_hw->hw_mutex);
  2599. CAM_DBG(CAM_CPAS, "activate cnt for: %s non-zero: %d",
  2600. cache_info->name, cache_info->ref_cnt);
  2601. return rc;
  2602. }
  2603. rc = llcc_slice_deactivate(cache_info->slic_desc);
  2604. if (rc)
  2605. CAM_ERR(CAM_CPAS, "Failed to deactivate cache:%s",
  2606. cache_info->name);
  2607. mutex_unlock(&cpas_hw->hw_mutex);
  2608. CAM_DBG(CAM_CPAS, "De-activated cache:%s", cache_info->name);
  2609. return rc;
  2610. }
  2611. static inline int cam_cpas_validate_cache_type(
  2612. uint32_t num_caches, enum cam_sys_cache_config_types type)
  2613. {
  2614. if ((!num_caches) || (type < 0) || (type >= CAM_LLCC_MAX))
  2615. return -EINVAL;
  2616. else
  2617. return 0;
  2618. }
  2619. static int cam_cpas_get_slice_id(
  2620. struct cam_hw_info *cpas_hw,
  2621. enum cam_sys_cache_config_types type)
  2622. {
  2623. struct cam_cpas_private_soc *soc_private =
  2624. (struct cam_cpas_private_soc *)cpas_hw->soc_info.soc_private;
  2625. uint32_t num_caches = soc_private->num_caches;
  2626. int scid = -1, i;
  2627. if (cam_cpas_validate_cache_type(num_caches, type))
  2628. goto end;
  2629. for (i = 0; i < num_caches; i++) {
  2630. if (type == soc_private->llcc_info[i].type) {
  2631. scid = soc_private->llcc_info[i].scid;
  2632. CAM_DBG(CAM_CPAS, "Cache:%s type:%d scid:%d",
  2633. soc_private->llcc_info[i].name, type, scid);
  2634. break;
  2635. }
  2636. }
  2637. end:
  2638. return scid;
  2639. }
  2640. static int cam_cpas_activate_cache_slice(
  2641. struct cam_hw_info *cpas_hw,
  2642. enum cam_sys_cache_config_types type)
  2643. {
  2644. struct cam_cpas_private_soc *soc_private =
  2645. (struct cam_cpas_private_soc *)cpas_hw->soc_info.soc_private;
  2646. uint32_t num_caches = soc_private->num_caches;
  2647. int rc = 0, i;
  2648. CAM_DBG(CAM_CPAS, "Activate type: %d", type);
  2649. if (cam_cpas_validate_cache_type(num_caches, type))
  2650. goto end;
  2651. for (i = 0; i < num_caches; i++) {
  2652. if (type == soc_private->llcc_info[i].type)
  2653. rc = cam_cpas_activate_cache(cpas_hw,
  2654. &soc_private->llcc_info[i]);
  2655. }
  2656. end:
  2657. return rc;
  2658. }
  2659. static int cam_cpas_deactivate_cache_slice(
  2660. struct cam_hw_info *cpas_hw,
  2661. enum cam_sys_cache_config_types type)
  2662. {
  2663. struct cam_cpas_private_soc *soc_private =
  2664. (struct cam_cpas_private_soc *)cpas_hw->soc_info.soc_private;
  2665. uint32_t num_caches = soc_private->num_caches;
  2666. int rc = 0, i;
  2667. CAM_DBG(CAM_CPAS, "De-activate type: %d", type);
  2668. if (cam_cpas_validate_cache_type(num_caches, type))
  2669. goto end;
  2670. for (i = 0; i < num_caches; i++) {
  2671. if (type == soc_private->llcc_info[i].type)
  2672. rc = cam_cpas_deactivate_cache(cpas_hw,
  2673. &soc_private->llcc_info[i]);
  2674. }
  2675. end:
  2676. return rc;
  2677. }
  2678. static int cam_cpas_hw_csid_input_core_info_update(struct cam_hw_info *cpas_hw,
  2679. int csid_idx, int sfe_idx, bool set_port)
  2680. {
  2681. int i, j, rc = 0;
  2682. char client_name[CAM_HW_IDENTIFIER_LENGTH + 3];
  2683. int32_t client_indx = -1;
  2684. struct cam_cpas_private_soc *soc_private =
  2685. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  2686. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  2687. struct cam_cpas_tree_node *tree_node = NULL;
  2688. if (!soc_private->enable_cam_ddr_drv || cpas_core->force_hlos_drv)
  2689. return 0;
  2690. if ((csid_idx < 0) || (sfe_idx < 0)) {
  2691. CAM_ERR(CAM_CPAS, "Invalid core info csid:%d sfe:%d", csid_idx, sfe_idx);
  2692. return -EINVAL;
  2693. }
  2694. snprintf(client_name, sizeof(client_name), "%s%d", "sfe", sfe_idx);
  2695. rc = cam_common_util_get_string_index(soc_private->client_name,
  2696. soc_private->num_clients, client_name, &client_indx);
  2697. if (!cpas_core->cpas_client[client_indx]->is_drv_dyn)
  2698. return 0;
  2699. for (i = 0; i < CAM_CPAS_PATH_DATA_MAX; i++) {
  2700. for (j = 0; j < CAM_CPAS_TRANSACTION_MAX; j++) {
  2701. tree_node = cpas_core->cpas_client[client_indx]->tree_node[i][j];
  2702. if (!tree_node)
  2703. continue;
  2704. if (set_port)
  2705. tree_node->drv_voting_idx = CAM_CPAS_PORT_DRV_0 + csid_idx;
  2706. else
  2707. tree_node->drv_voting_idx = CAM_CPAS_PORT_DRV_DYN;
  2708. }
  2709. }
  2710. return rc;
  2711. }
  2712. static int cam_cpas_hw_enable_domain_id_clks(struct cam_hw_info *cpas_hw,
  2713. bool enable)
  2714. {
  2715. int rc = 0, i;
  2716. struct cam_cpas_private_soc *soc_private =
  2717. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  2718. struct cam_cpas_domain_id_support_clks *domain_id_clks =
  2719. soc_private->domain_id_clks;
  2720. if (!soc_private->domain_id_info.domain_id_supported) {
  2721. CAM_DBG(CAM_CPAS, "Domain-id not supported on target");
  2722. return -EINVAL;
  2723. }
  2724. if (enable) {
  2725. for (i = 0; i < domain_id_clks->number_clks; i++) {
  2726. rc = cam_soc_util_clk_enable(&cpas_hw->soc_info, true,
  2727. domain_id_clks->clk_idx[i], 0, NULL);
  2728. if (rc) {
  2729. CAM_ERR(CAM_CPAS, "Domain-id clk %s enable failed, rc: %d",
  2730. domain_id_clks->clk_names[i], i);
  2731. goto clean_up;
  2732. }
  2733. }
  2734. CAM_DBG(CAM_CPAS, "Domain-id clks enable success");
  2735. } else {
  2736. for (i = 0; i < domain_id_clks->number_clks; i++) {
  2737. rc = cam_soc_util_clk_disable(&cpas_hw->soc_info, true,
  2738. domain_id_clks->clk_idx[i]);
  2739. if (rc)
  2740. CAM_WARN(CAM_CPAS, "Domain-id clk %s disable failed, rc: %d",
  2741. domain_id_clks->clk_names[i], rc);
  2742. }
  2743. if (!rc)
  2744. CAM_DBG(CAM_CPAS, "Domain-id clks disable success");
  2745. }
  2746. return rc;
  2747. clean_up:
  2748. for (--i; i >= 0; i--)
  2749. cam_soc_util_clk_disable(&cpas_hw->soc_info, true,
  2750. domain_id_clks->clk_idx[i]);
  2751. return rc;
  2752. }
  2753. static int cam_cpas_hw_csid_process_resume(struct cam_hw_info *cpas_hw, uint32_t csid_idx)
  2754. {
  2755. int i, rc = 0;
  2756. struct cam_cpas_private_soc *soc_private =
  2757. (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
  2758. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  2759. if (!soc_private->enable_cam_ddr_drv)
  2760. return 0;
  2761. for (i = 0; i < cpas_core->num_axi_ports; i++) {
  2762. if (!cpas_core->axi_port[i].bus_client.common_data.is_drv_port ||
  2763. !cpas_core->axi_port[i].is_drv_started ||
  2764. (cpas_core->axi_port[i].drv_idx != (CAM_CPAS_PORT_DRV_0 + csid_idx)))
  2765. continue;
  2766. /* Apply last applied bw again to applicable DRV port */
  2767. rc = cam_cpas_util_vote_drv_bus_client_bw(&cpas_core->axi_port[i].bus_client,
  2768. &cpas_core->axi_port[i].applied_bw, &cpas_core->axi_port[i].applied_bw);
  2769. if (rc) {
  2770. CAM_ERR(CAM_CPAS, "Failed in BW update on resume rc:%d", rc);
  2771. goto end;
  2772. }
  2773. /* Trigger channel switch for RSC dev */
  2774. rc = cam_cpas_drv_channel_switch_for_dev(cpas_core->axi_port[i].cam_rsc_dev);
  2775. if (rc) {
  2776. CAM_ERR(CAM_CPAS,
  2777. "Port[%s] failed in channel switch during resume rc:%d",
  2778. cpas_core->axi_port[i].axi_port_name, rc);
  2779. goto end;
  2780. }
  2781. }
  2782. end:
  2783. return rc;
  2784. }
  2785. static int cam_cpas_hw_process_cmd(void *hw_priv,
  2786. uint32_t cmd_type, void *cmd_args, uint32_t arg_size)
  2787. {
  2788. int rc = -EINVAL;
  2789. if (!hw_priv || !cmd_args ||
  2790. (cmd_type >= CAM_CPAS_HW_CMD_INVALID)) {
  2791. CAM_ERR(CAM_CPAS, "Invalid arguments %pK %pK %d",
  2792. hw_priv, cmd_args, cmd_type);
  2793. return -EINVAL;
  2794. }
  2795. switch (cmd_type) {
  2796. case CAM_CPAS_HW_CMD_REGISTER_CLIENT: {
  2797. struct cam_cpas_register_params *register_params;
  2798. if (sizeof(struct cam_cpas_register_params) != arg_size) {
  2799. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2800. cmd_type, arg_size);
  2801. break;
  2802. }
  2803. register_params = (struct cam_cpas_register_params *)cmd_args;
  2804. rc = cam_cpas_hw_register_client(hw_priv, register_params);
  2805. break;
  2806. }
  2807. case CAM_CPAS_HW_CMD_UNREGISTER_CLIENT: {
  2808. uint32_t *client_handle;
  2809. if (sizeof(uint32_t) != arg_size) {
  2810. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2811. cmd_type, arg_size);
  2812. break;
  2813. }
  2814. client_handle = (uint32_t *)cmd_args;
  2815. rc = cam_cpas_hw_unregister_client(hw_priv, *client_handle);
  2816. break;
  2817. }
  2818. case CAM_CPAS_HW_CMD_REG_WRITE: {
  2819. struct cam_cpas_hw_cmd_reg_read_write *reg_write;
  2820. if (sizeof(struct cam_cpas_hw_cmd_reg_read_write) !=
  2821. arg_size) {
  2822. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2823. cmd_type, arg_size);
  2824. break;
  2825. }
  2826. reg_write =
  2827. (struct cam_cpas_hw_cmd_reg_read_write *)cmd_args;
  2828. rc = cam_cpas_hw_reg_write(hw_priv, reg_write->client_handle,
  2829. reg_write->reg_base, reg_write->offset, reg_write->mb,
  2830. reg_write->value);
  2831. break;
  2832. }
  2833. case CAM_CPAS_HW_CMD_REG_READ: {
  2834. struct cam_cpas_hw_cmd_reg_read_write *reg_read;
  2835. if (sizeof(struct cam_cpas_hw_cmd_reg_read_write) !=
  2836. arg_size) {
  2837. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2838. cmd_type, arg_size);
  2839. break;
  2840. }
  2841. reg_read =
  2842. (struct cam_cpas_hw_cmd_reg_read_write *)cmd_args;
  2843. rc = cam_cpas_hw_reg_read(hw_priv,
  2844. reg_read->client_handle, reg_read->reg_base,
  2845. reg_read->offset, reg_read->mb, &reg_read->value);
  2846. break;
  2847. }
  2848. case CAM_CPAS_HW_CMD_AHB_VOTE: {
  2849. struct cam_cpas_hw_cmd_ahb_vote *cmd_ahb_vote;
  2850. if (sizeof(struct cam_cpas_hw_cmd_ahb_vote) != arg_size) {
  2851. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2852. cmd_type, arg_size);
  2853. break;
  2854. }
  2855. cmd_ahb_vote = (struct cam_cpas_hw_cmd_ahb_vote *)cmd_args;
  2856. rc = cam_cpas_hw_update_ahb_vote(hw_priv,
  2857. cmd_ahb_vote->client_handle, cmd_ahb_vote->ahb_vote);
  2858. break;
  2859. }
  2860. case CAM_CPAS_HW_CMD_AXI_VOTE: {
  2861. struct cam_cpas_hw_cmd_axi_vote *cmd_axi_vote;
  2862. if (sizeof(struct cam_cpas_hw_cmd_axi_vote) != arg_size) {
  2863. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2864. cmd_type, arg_size);
  2865. break;
  2866. }
  2867. cmd_axi_vote = (struct cam_cpas_hw_cmd_axi_vote *)cmd_args;
  2868. rc = cam_cpas_hw_update_axi_vote(hw_priv,
  2869. cmd_axi_vote->client_handle, cmd_axi_vote->axi_vote);
  2870. break;
  2871. }
  2872. case CAM_CPAS_HW_CMD_LOG_VOTE: {
  2873. bool *ddr_only;
  2874. if (sizeof(bool) != arg_size) {
  2875. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2876. cmd_type, arg_size);
  2877. break;
  2878. }
  2879. ddr_only = (bool *) cmd_args;
  2880. rc = cam_cpas_log_vote(hw_priv, *ddr_only);
  2881. break;
  2882. }
  2883. case CAM_CPAS_HW_CMD_LOG_EVENT: {
  2884. struct cam_cpas_hw_cmd_notify_event *event;
  2885. if (sizeof(struct cam_cpas_hw_cmd_notify_event) != arg_size) {
  2886. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2887. cmd_type, arg_size);
  2888. break;
  2889. }
  2890. event = (struct cam_cpas_hw_cmd_notify_event *)cmd_args;
  2891. rc = cam_cpas_log_event(hw_priv, event->identifier_string,
  2892. event->identifier_value);
  2893. break;
  2894. }
  2895. case CAM_CPAS_HW_CMD_SELECT_QOS: {
  2896. uint32_t *selection_mask;
  2897. if (sizeof(uint32_t) != arg_size) {
  2898. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2899. cmd_type, arg_size);
  2900. break;
  2901. }
  2902. selection_mask = (uint32_t *)cmd_args;
  2903. rc = cam_cpas_select_qos(hw_priv, *selection_mask);
  2904. break;
  2905. }
  2906. case CAM_CPAS_HW_CMD_GET_SCID: {
  2907. enum cam_sys_cache_config_types type;
  2908. if (sizeof(enum cam_sys_cache_config_types) != arg_size) {
  2909. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2910. cmd_type, arg_size);
  2911. break;
  2912. }
  2913. type = *((enum cam_sys_cache_config_types *) cmd_args);
  2914. rc = cam_cpas_get_slice_id(hw_priv, type);
  2915. }
  2916. break;
  2917. case CAM_CPAS_HW_CMD_ACTIVATE_LLC: {
  2918. enum cam_sys_cache_config_types type;
  2919. if (sizeof(enum cam_sys_cache_config_types) != arg_size) {
  2920. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2921. cmd_type, arg_size);
  2922. break;
  2923. }
  2924. type = *((enum cam_sys_cache_config_types *) cmd_args);
  2925. rc = cam_cpas_activate_cache_slice(hw_priv, type);
  2926. }
  2927. break;
  2928. case CAM_CPAS_HW_CMD_DEACTIVATE_LLC: {
  2929. enum cam_sys_cache_config_types type;
  2930. if (sizeof(enum cam_sys_cache_config_types) != arg_size) {
  2931. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2932. cmd_type, arg_size);
  2933. break;
  2934. }
  2935. type = *((enum cam_sys_cache_config_types *) cmd_args);
  2936. rc = cam_cpas_deactivate_cache_slice(hw_priv, type);
  2937. }
  2938. break;
  2939. case CAM_CPAS_HW_CMD_DUMP_BUFF_FILL_INFO: {
  2940. uint32_t *client_handle;
  2941. if (sizeof(uint32_t) != arg_size) {
  2942. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2943. cmd_type, arg_size);
  2944. break;
  2945. }
  2946. client_handle = (uint32_t *)cmd_args;
  2947. rc = cam_cpas_hw_dump_camnoc_buff_fill_info(hw_priv,
  2948. *client_handle);
  2949. break;
  2950. }
  2951. case CAM_CPAS_HW_CMD_CSID_INPUT_CORE_INFO_UPDATE: {
  2952. struct cam_cpas_hw_cmd_csid_input_core_info_update *core_info_update;
  2953. if (sizeof(struct cam_cpas_hw_cmd_csid_input_core_info_update) != arg_size) {
  2954. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d", cmd_type, arg_size);
  2955. break;
  2956. }
  2957. core_info_update = (struct cam_cpas_hw_cmd_csid_input_core_info_update *)cmd_args;
  2958. rc = cam_cpas_hw_csid_input_core_info_update(hw_priv, core_info_update->csid_idx,
  2959. core_info_update->sfe_idx, core_info_update->set_port);
  2960. break;
  2961. }
  2962. case CAM_CPAS_HW_CMD_CSID_PROCESS_RESUME: {
  2963. uint32_t *csid_idx;
  2964. if (sizeof(uint32_t) != arg_size) {
  2965. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2966. cmd_type, arg_size);
  2967. break;
  2968. }
  2969. csid_idx = (uint32_t *)cmd_args;
  2970. rc = cam_cpas_hw_csid_process_resume(hw_priv, *csid_idx);
  2971. break;
  2972. }
  2973. case CAM_CPAS_HW_CMD_ENABLE_DISABLE_DOMAIN_ID_CLK: {
  2974. bool *enable;
  2975. if (sizeof(bool) != arg_size) {
  2976. CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
  2977. cmd_type, arg_size);
  2978. break;
  2979. }
  2980. enable = (bool *)cmd_args;
  2981. rc = cam_cpas_hw_enable_domain_id_clks(hw_priv, *enable);
  2982. break;
  2983. }
  2984. default:
  2985. CAM_ERR(CAM_CPAS, "CPAS HW command not valid =%d", cmd_type);
  2986. break;
  2987. }
  2988. return rc;
  2989. }
  2990. static int cam_cpas_util_client_setup(struct cam_hw_info *cpas_hw)
  2991. {
  2992. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  2993. int i;
  2994. for (i = 0; i < CAM_CPAS_MAX_CLIENTS; i++) {
  2995. mutex_init(&cpas_core->client_mutex[i]);
  2996. }
  2997. return 0;
  2998. }
  2999. int cam_cpas_util_client_cleanup(struct cam_hw_info *cpas_hw)
  3000. {
  3001. struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
  3002. int i;
  3003. for (i = 0; i < CAM_CPAS_MAX_CLIENTS; i++) {
  3004. if (cpas_core->cpas_client[i] &&
  3005. cpas_core->cpas_client[i]->registered) {
  3006. cam_cpas_hw_unregister_client(cpas_hw, i);
  3007. }
  3008. kfree(cpas_core->cpas_client[i]);
  3009. cpas_core->cpas_client[i] = NULL;
  3010. mutex_destroy(&cpas_core->client_mutex[i]);
  3011. }
  3012. return 0;
  3013. }
  3014. static int cam_cpas_util_get_internal_ops(struct platform_device *pdev,
  3015. struct cam_hw_intf *hw_intf, struct cam_cpas_internal_ops *internal_ops)
  3016. {
  3017. struct device_node *of_node = pdev->dev.of_node;
  3018. int rc;
  3019. const char *compat_str = NULL;
  3020. rc = of_property_read_string_index(of_node, "arch-compat", 0,
  3021. (const char **)&compat_str);
  3022. if (rc) {
  3023. CAM_ERR(CAM_CPAS, "failed to get arch-compat rc=%d", rc);
  3024. return -EINVAL;
  3025. }
  3026. if (strnstr(compat_str, "camss_top", strlen(compat_str))) {
  3027. hw_intf->hw_type = CAM_HW_CAMSSTOP;
  3028. rc = cam_camsstop_get_internal_ops(internal_ops);
  3029. } else if (strnstr(compat_str, "cpas_top", strlen(compat_str))) {
  3030. hw_intf->hw_type = CAM_HW_CPASTOP;
  3031. rc = cam_cpastop_get_internal_ops(internal_ops);
  3032. } else {
  3033. CAM_ERR(CAM_CPAS, "arch-compat %s not supported", compat_str);
  3034. rc = -EINVAL;
  3035. }
  3036. return rc;
  3037. }
  3038. static int cam_cpas_util_create_debugfs(struct cam_cpas *cpas_core)
  3039. {
  3040. int rc = 0;
  3041. struct dentry *dbgfileptr = NULL;
  3042. if (!cam_debugfs_available())
  3043. return 0;
  3044. rc = cam_debugfs_create_subdir("cpas", &dbgfileptr);
  3045. if (rc) {
  3046. CAM_ERR(CAM_CPAS,"DebugFS could not create directory!");
  3047. rc = -ENOENT;
  3048. goto end;
  3049. }
  3050. /* Store parent inode for cleanup in caller */
  3051. cpas_core->dentry = dbgfileptr;
  3052. debugfs_create_bool("ahb_bus_scaling_disable", 0644,
  3053. cpas_core->dentry, &cpas_core->ahb_bus_scaling_disable);
  3054. debugfs_create_bool("full_state_dump", 0644,
  3055. cpas_core->dentry, &cpas_core->full_state_dump);
  3056. debugfs_create_bool("smart_qos_dump", 0644,
  3057. cpas_core->dentry, &cpas_core->smart_qos_dump);
  3058. debugfs_create_bool("force_hlos_drv", 0644,
  3059. cpas_core->dentry, &cpas_core->force_hlos_drv);
  3060. end:
  3061. return rc;
  3062. }
  3063. int cam_cpas_hw_probe(struct platform_device *pdev,
  3064. struct cam_hw_intf **hw_intf)
  3065. {
  3066. int rc = 0;
  3067. int i;
  3068. struct cam_hw_info *cpas_hw = NULL;
  3069. struct cam_hw_intf *cpas_hw_intf = NULL;
  3070. struct cam_cpas *cpas_core = NULL;
  3071. struct cam_cpas_private_soc *soc_private;
  3072. struct cam_cpas_internal_ops *internal_ops;
  3073. cpas_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL);
  3074. if (!cpas_hw_intf)
  3075. return -ENOMEM;
  3076. cpas_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL);
  3077. if (!cpas_hw) {
  3078. kfree(cpas_hw_intf);
  3079. return -ENOMEM;
  3080. }
  3081. cpas_core = kzalloc(sizeof(struct cam_cpas), GFP_KERNEL);
  3082. if (!cpas_core) {
  3083. kfree(cpas_hw);
  3084. kfree(cpas_hw_intf);
  3085. return -ENOMEM;
  3086. }
  3087. for (i = 0; i < CAM_CPAS_REG_MAX; i++)
  3088. cpas_core->regbase_index[i] = -1;
  3089. cpas_hw_intf->hw_priv = cpas_hw;
  3090. cpas_hw->core_info = cpas_core;
  3091. cpas_hw->hw_state = CAM_HW_STATE_POWER_DOWN;
  3092. cpas_hw->soc_info.pdev = pdev;
  3093. cpas_hw->soc_info.dev = &pdev->dev;
  3094. cpas_hw->soc_info.dev_name = pdev->name;
  3095. cpas_hw->open_count = 0;
  3096. cpas_core->ahb_bus_scaling_disable = false;
  3097. cpas_core->full_state_dump = false;
  3098. cpas_core->smart_qos_dump = false;
  3099. atomic64_set(&cpas_core->monitor_head, -1);
  3100. mutex_init(&cpas_hw->hw_mutex);
  3101. spin_lock_init(&cpas_hw->hw_lock);
  3102. init_completion(&cpas_hw->hw_complete);
  3103. cpas_hw_intf->hw_ops.get_hw_caps = cam_cpas_hw_get_hw_info;
  3104. cpas_hw_intf->hw_ops.init = cam_cpas_hw_init;
  3105. cpas_hw_intf->hw_ops.deinit = NULL;
  3106. cpas_hw_intf->hw_ops.reset = NULL;
  3107. cpas_hw_intf->hw_ops.reserve = NULL;
  3108. cpas_hw_intf->hw_ops.release = NULL;
  3109. cpas_hw_intf->hw_ops.start = cam_cpas_hw_start;
  3110. cpas_hw_intf->hw_ops.stop = cam_cpas_hw_stop;
  3111. cpas_hw_intf->hw_ops.read = NULL;
  3112. cpas_hw_intf->hw_ops.write = NULL;
  3113. cpas_hw_intf->hw_ops.process_cmd = cam_cpas_hw_process_cmd;
  3114. cpas_core->work_queue = alloc_workqueue(CAM_CPAS_WORKQUEUE_NAME,
  3115. WQ_UNBOUND | WQ_MEM_RECLAIM, CAM_CPAS_INFLIGHT_WORKS);
  3116. if (!cpas_core->work_queue) {
  3117. rc = -ENOMEM;
  3118. goto release_mem;
  3119. }
  3120. internal_ops = &cpas_core->internal_ops;
  3121. rc = cam_cpas_util_get_internal_ops(pdev, cpas_hw_intf, internal_ops);
  3122. if (rc)
  3123. goto release_workq;
  3124. rc = cam_cpas_soc_init_resources(&cpas_hw->soc_info,
  3125. internal_ops->handle_irq, cpas_hw);
  3126. if (rc)
  3127. goto release_workq;
  3128. soc_private = (struct cam_cpas_private_soc *)
  3129. cpas_hw->soc_info.soc_private;
  3130. cpas_core->num_clients = soc_private->num_clients;
  3131. atomic_set(&cpas_core->irq_count, 0);
  3132. init_waitqueue_head(&cpas_core->irq_count_wq);
  3133. if (internal_ops->setup_regbase) {
  3134. rc = internal_ops->setup_regbase(&cpas_hw->soc_info,
  3135. cpas_core->regbase_index, CAM_CPAS_REG_MAX);
  3136. if (rc)
  3137. goto deinit_platform_res;
  3138. }
  3139. rc = cam_cpas_util_client_setup(cpas_hw);
  3140. if (rc) {
  3141. CAM_ERR(CAM_CPAS, "failed in client setup, rc=%d", rc);
  3142. goto deinit_platform_res;
  3143. }
  3144. rc = cam_cpas_util_register_bus_client(&cpas_hw->soc_info,
  3145. cpas_hw->soc_info.pdev->dev.of_node,
  3146. &cpas_core->ahb_bus_client);
  3147. if (rc) {
  3148. CAM_ERR(CAM_CPAS, "failed in ahb setup, rc=%d", rc);
  3149. goto client_cleanup;
  3150. }
  3151. rc = cam_cpas_util_axi_setup(cpas_core, &cpas_hw->soc_info);
  3152. if (rc) {
  3153. CAM_ERR(CAM_CPAS, "failed in axi setup, rc=%d", rc);
  3154. goto ahb_cleanup;
  3155. }
  3156. /* Need to vote first before enabling clocks */
  3157. rc = cam_cpas_util_vote_default_ahb_axi(cpas_hw, true);
  3158. if (rc)
  3159. goto axi_cleanup;
  3160. rc = cam_cpas_soc_enable_resources(&cpas_hw->soc_info, CAM_SVS_VOTE);
  3161. if (rc) {
  3162. CAM_ERR(CAM_CPAS, "failed in soc_enable_resources, rc=%d", rc);
  3163. goto remove_default_vote;
  3164. }
  3165. if (internal_ops->get_hw_info) {
  3166. rc = internal_ops->get_hw_info(cpas_hw, &cpas_core->hw_caps);
  3167. if (rc) {
  3168. CAM_ERR(CAM_CPAS, "failed in get_hw_info, rc=%d", rc);
  3169. goto disable_soc_res;
  3170. }
  3171. } else {
  3172. CAM_ERR(CAM_CPAS, "Invalid get_hw_info");
  3173. goto disable_soc_res;
  3174. }
  3175. rc = cam_cpas_hw_init(cpas_hw_intf->hw_priv,
  3176. &cpas_core->hw_caps, sizeof(struct cam_cpas_hw_caps));
  3177. if (rc)
  3178. goto disable_soc_res;
  3179. rc = cam_cpas_soc_disable_resources(&cpas_hw->soc_info, true, true);
  3180. if (rc) {
  3181. CAM_ERR(CAM_CPAS, "failed in soc_disable_resources, rc=%d", rc);
  3182. goto remove_default_vote;
  3183. }
  3184. rc = cam_cpas_util_vote_default_ahb_axi(cpas_hw, false);
  3185. if (rc)
  3186. goto axi_cleanup;
  3187. rc = cam_cpas_util_create_debugfs(cpas_core);
  3188. *hw_intf = cpas_hw_intf;
  3189. return 0;
  3190. disable_soc_res:
  3191. cam_cpas_soc_disable_resources(&cpas_hw->soc_info, true, true);
  3192. remove_default_vote:
  3193. cam_cpas_util_vote_default_ahb_axi(cpas_hw, false);
  3194. axi_cleanup:
  3195. cam_cpas_util_axi_cleanup(cpas_core, &cpas_hw->soc_info);
  3196. ahb_cleanup:
  3197. cam_cpas_util_unregister_bus_client(&cpas_core->ahb_bus_client);
  3198. client_cleanup:
  3199. cam_cpas_util_client_cleanup(cpas_hw);
  3200. cam_cpas_node_tree_cleanup(cpas_core, cpas_hw->soc_info.soc_private);
  3201. deinit_platform_res:
  3202. cam_cpas_soc_deinit_resources(&cpas_hw->soc_info);
  3203. release_workq:
  3204. flush_workqueue(cpas_core->work_queue);
  3205. destroy_workqueue(cpas_core->work_queue);
  3206. release_mem:
  3207. mutex_destroy(&cpas_hw->hw_mutex);
  3208. kfree(cpas_core);
  3209. kfree(cpas_hw);
  3210. kfree(cpas_hw_intf);
  3211. CAM_ERR(CAM_CPAS, "failed in hw probe");
  3212. return rc;
  3213. }
  3214. int cam_cpas_hw_remove(struct cam_hw_intf *cpas_hw_intf)
  3215. {
  3216. struct cam_hw_info *cpas_hw;
  3217. struct cam_cpas *cpas_core;
  3218. if (!cpas_hw_intf) {
  3219. CAM_ERR(CAM_CPAS, "cpas interface not initialized");
  3220. return -EINVAL;
  3221. }
  3222. cpas_hw = (struct cam_hw_info *)cpas_hw_intf->hw_priv;
  3223. cpas_core = (struct cam_cpas *)cpas_hw->core_info;
  3224. if (cpas_hw->hw_state == CAM_HW_STATE_POWER_UP) {
  3225. CAM_ERR(CAM_CPAS, "cpas hw is in power up state");
  3226. return -EINVAL;
  3227. }
  3228. cam_cpas_util_axi_cleanup(cpas_core, &cpas_hw->soc_info);
  3229. cam_cpas_node_tree_cleanup(cpas_core, cpas_hw->soc_info.soc_private);
  3230. cam_cpas_util_unregister_bus_client(&cpas_core->ahb_bus_client);
  3231. cam_cpas_util_client_cleanup(cpas_hw);
  3232. cam_cpas_soc_deinit_resources(&cpas_hw->soc_info);
  3233. cpas_core->dentry = NULL;
  3234. flush_workqueue(cpas_core->work_queue);
  3235. destroy_workqueue(cpas_core->work_queue);
  3236. mutex_destroy(&cpas_hw->hw_mutex);
  3237. kfree(cpas_core);
  3238. kfree(cpas_hw);
  3239. kfree(cpas_hw_intf);
  3240. return 0;
  3241. }