sde_encoder.c 153 KB

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  1. /*
  2. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/kthread.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/input.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sde_rsc.h>
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "sde_hwio.h"
  29. #include "sde_hw_catalog.h"
  30. #include "sde_hw_intf.h"
  31. #include "sde_hw_ctl.h"
  32. #include "sde_formats.h"
  33. #include "sde_encoder.h"
  34. #include "sde_encoder_phys.h"
  35. #include "sde_hw_dsc.h"
  36. #include "sde_crtc.h"
  37. #include "sde_trace.h"
  38. #include "sde_core_irq.h"
  39. #include "sde_hw_top.h"
  40. #include "sde_hw_qdss.h"
  41. #include "sde_encoder_dce.h"
  42. #include "sde_vm.h"
  43. #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
  44. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  45. #define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
  46. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  47. #define SDE_DEBUG_PHYS(p, fmt, ...) SDE_DEBUG("enc%d intf%d pp%d " fmt,\
  48. (p) ? (p)->parent->base.id : -1, \
  49. (p) ? (p)->intf_idx - INTF_0 : -1, \
  50. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  51. ##__VA_ARGS__)
  52. #define SDE_ERROR_PHYS(p, fmt, ...) SDE_ERROR("enc%d intf%d pp%d " fmt,\
  53. (p) ? (p)->parent->base.id : -1, \
  54. (p) ? (p)->intf_idx - INTF_0 : -1, \
  55. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  56. ##__VA_ARGS__)
  57. #define MISR_BUFF_SIZE 256
  58. #define IDLE_SHORT_TIMEOUT 1
  59. #define EVT_TIME_OUT_SPLIT 2
  60. /* worst case poll time for delay_kickoff to be cleared */
  61. #define DELAY_KICKOFF_POLL_TIMEOUT_US 100000
  62. /* Maximum number of VSYNC wait attempts for RSC state transition */
  63. #define MAX_RSC_WAIT 5
  64. /**
  65. * enum sde_enc_rc_events - events for resource control state machine
  66. * @SDE_ENC_RC_EVENT_KICKOFF:
  67. * This event happens at NORMAL priority.
  68. * Event that signals the start of the transfer. When this event is
  69. * received, enable MDP/DSI core clocks and request RSC with CMD state.
  70. * Regardless of the previous state, the resource should be in ON state
  71. * at the end of this event. At the end of this event, a delayed work is
  72. * scheduled to go to IDLE_PC state after IDLE_POWERCOLLAPSE_DURATION
  73. * ktime.
  74. * @SDE_ENC_RC_EVENT_PRE_STOP:
  75. * This event happens at NORMAL priority.
  76. * This event, when received during the ON state, set RSC to IDLE, and
  77. * and leave the RC STATE in the PRE_OFF state.
  78. * It should be followed by the STOP event as part of encoder disable.
  79. * If received during IDLE or OFF states, it will do nothing.
  80. * @SDE_ENC_RC_EVENT_STOP:
  81. * This event happens at NORMAL priority.
  82. * When this event is received, disable all the MDP/DSI core clocks, and
  83. * disable IRQs. It should be called from the PRE_OFF or IDLE states.
  84. * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  85. * PRE_OFF is expected when PRE_STOP was executed during the ON state.
  86. * Resource state should be in OFF at the end of the event.
  87. * @SDE_ENC_RC_EVENT_PRE_MODESET:
  88. * This event happens at NORMAL priority from a work item.
  89. * Event signals that there is a seamless mode switch is in prgoress. A
  90. * client needs to leave clocks ON to reduce the mode switch latency.
  91. * @SDE_ENC_RC_EVENT_POST_MODESET:
  92. * This event happens at NORMAL priority from a work item.
  93. * Event signals that seamless mode switch is complete and resources are
  94. * acquired. Clients wants to update the rsc with new vtotal and update
  95. * pm_qos vote.
  96. * @SDE_ENC_RC_EVENT_ENTER_IDLE:
  97. * This event happens at NORMAL priority from a work item.
  98. * Event signals that there were no frame updates for
  99. * IDLE_POWERCOLLAPSE_DURATION time. This would disable MDP/DSI core clocks
  100. * and request RSC with IDLE state and change the resource state to IDLE.
  101. * @SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  102. * This event is triggered from the input event thread when touch event is
  103. * received from the input device. On receiving this event,
  104. * - If the device is in SDE_ENC_RC_STATE_IDLE state, it turns ON the
  105. clocks and enable RSC.
  106. * - If the device is in SDE_ENC_RC_STATE_ON state, it resets the delayed
  107. * off work since a new commit is imminent.
  108. */
  109. enum sde_enc_rc_events {
  110. SDE_ENC_RC_EVENT_KICKOFF = 1,
  111. SDE_ENC_RC_EVENT_PRE_STOP,
  112. SDE_ENC_RC_EVENT_STOP,
  113. SDE_ENC_RC_EVENT_PRE_MODESET,
  114. SDE_ENC_RC_EVENT_POST_MODESET,
  115. SDE_ENC_RC_EVENT_ENTER_IDLE,
  116. SDE_ENC_RC_EVENT_EARLY_WAKEUP,
  117. };
  118. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable)
  119. {
  120. struct sde_encoder_virt *sde_enc;
  121. int i;
  122. sde_enc = to_sde_encoder_virt(drm_enc);
  123. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  124. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  125. if (phys && phys->hw_ctl && phys->hw_ctl->ops.uidle_enable) {
  126. SDE_EVT32(DRMID(drm_enc), enable);
  127. phys->hw_ctl->ops.uidle_enable(phys->hw_ctl, enable);
  128. }
  129. }
  130. }
  131. ktime_t sde_encoder_calc_last_vsync_timestamp(struct drm_encoder *drm_enc)
  132. {
  133. struct sde_encoder_virt *sde_enc;
  134. struct sde_encoder_phys *cur_master;
  135. u64 vsync_counter, qtmr_counter, hw_diff, hw_diff_ns, frametime_ns;
  136. ktime_t tvblank, cur_time;
  137. struct intf_status intf_status = {0};
  138. u32 fps;
  139. sde_enc = to_sde_encoder_virt(drm_enc);
  140. cur_master = sde_enc->cur_master;
  141. fps = sde_encoder_get_fps(drm_enc);
  142. if (!cur_master || !cur_master->hw_intf || !fps
  143. || !cur_master->hw_intf->ops.get_vsync_timestamp
  144. || (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE)
  145. && !sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  146. return 0;
  147. /*
  148. * avoid calculation and rely on ktime_get, if programmable fetch is enabled
  149. * as the HW VSYNC timestamp will be updated at panel vsync and not at MDP VSYNC
  150. */
  151. if (cur_master->hw_intf->ops.get_status) {
  152. cur_master->hw_intf->ops.get_status(cur_master->hw_intf, &intf_status);
  153. if (intf_status.is_prog_fetch_en)
  154. return 0;
  155. }
  156. vsync_counter = cur_master->hw_intf->ops.get_vsync_timestamp(cur_master->hw_intf);
  157. qtmr_counter = arch_timer_read_counter();
  158. cur_time = ktime_get_ns();
  159. /* check for counter rollover between the two timestamps [56 bits] */
  160. if (qtmr_counter < vsync_counter) {
  161. hw_diff = (0xffffffffffffff - vsync_counter) + qtmr_counter;
  162. SDE_EVT32(DRMID(drm_enc), vsync_counter >> 32, vsync_counter,
  163. qtmr_counter >> 32, qtmr_counter, hw_diff,
  164. fps, SDE_EVTLOG_FUNC_CASE1);
  165. } else {
  166. hw_diff = qtmr_counter - vsync_counter;
  167. }
  168. hw_diff_ns = DIV_ROUND_UP(hw_diff * 1000 * 10, 192); /* 19.2 MHz clock */
  169. frametime_ns = DIV_ROUND_UP(1000000000, fps);
  170. /* avoid setting timestamp, if diff is more than one vsync */
  171. if (ktime_compare(hw_diff_ns, frametime_ns) > 0) {
  172. tvblank = 0;
  173. SDE_EVT32(DRMID(drm_enc), vsync_counter >> 32, vsync_counter,
  174. qtmr_counter >> 32, qtmr_counter, ktime_to_us(hw_diff_ns),
  175. fps, SDE_EVTLOG_ERROR);
  176. } else {
  177. tvblank = ktime_sub_ns(cur_time, hw_diff_ns);
  178. }
  179. SDE_DEBUG_ENC(sde_enc,
  180. "vsync:%llu, qtmr:%llu, diff_ns:%llu, ts:%llu, cur_ts:%llu, fps:%d\n",
  181. vsync_counter, qtmr_counter, ktime_to_us(hw_diff_ns),
  182. ktime_to_us(tvblank), ktime_to_us(cur_time), fps);
  183. SDE_EVT32_VERBOSE(DRMID(drm_enc), hw_diff >> 32, hw_diff, ktime_to_us(hw_diff_ns),
  184. ktime_to_us(tvblank), ktime_to_us(cur_time), fps, SDE_EVTLOG_FUNC_CASE2);
  185. return tvblank;
  186. }
  187. static void _sde_encoder_pm_qos_add_request(struct drm_encoder *drm_enc)
  188. {
  189. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  190. struct msm_drm_private *priv;
  191. struct sde_kms *sde_kms;
  192. struct device *cpu_dev;
  193. struct cpumask *cpu_mask = NULL;
  194. int cpu = 0;
  195. u32 cpu_dma_latency;
  196. priv = drm_enc->dev->dev_private;
  197. sde_kms = to_sde_kms(priv->kms);
  198. if (!sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)
  199. return;
  200. cpu_dma_latency = sde_kms->catalog->perf.cpu_dma_latency;
  201. cpumask_clear(&sde_enc->valid_cpu_mask);
  202. if (sde_enc->mode_info.frame_rate > DEFAULT_FPS)
  203. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask_perf);
  204. if (!cpu_mask &&
  205. sde_encoder_check_curr_mode(drm_enc,
  206. MSM_DISPLAY_CMD_MODE))
  207. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask);
  208. if (!cpu_mask)
  209. return;
  210. for_each_cpu(cpu, cpu_mask) {
  211. cpu_dev = get_cpu_device(cpu);
  212. if (!cpu_dev) {
  213. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  214. cpu);
  215. return;
  216. }
  217. cpumask_set_cpu(cpu, &sde_enc->valid_cpu_mask);
  218. dev_pm_qos_add_request(cpu_dev,
  219. &sde_enc->pm_qos_cpu_req[cpu],
  220. DEV_PM_QOS_RESUME_LATENCY, cpu_dma_latency);
  221. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu_dma_latency, cpu);
  222. }
  223. }
  224. static void _sde_encoder_pm_qos_remove_request(struct drm_encoder *drm_enc)
  225. {
  226. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  227. struct device *cpu_dev;
  228. int cpu = 0;
  229. for_each_cpu(cpu, &sde_enc->valid_cpu_mask) {
  230. cpu_dev = get_cpu_device(cpu);
  231. if (!cpu_dev) {
  232. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  233. cpu);
  234. continue;
  235. }
  236. dev_pm_qos_remove_request(&sde_enc->pm_qos_cpu_req[cpu]);
  237. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu);
  238. }
  239. cpumask_clear(&sde_enc->valid_cpu_mask);
  240. }
  241. static bool _sde_encoder_is_autorefresh_enabled(
  242. struct sde_encoder_virt *sde_enc)
  243. {
  244. struct drm_connector *drm_conn;
  245. if (!sde_enc->cur_master ||
  246. !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE))
  247. return false;
  248. drm_conn = sde_enc->cur_master->connector;
  249. if (!drm_conn || !drm_conn->state)
  250. return false;
  251. return sde_connector_get_property(drm_conn->state,
  252. CONNECTOR_PROP_AUTOREFRESH) ? true : false;
  253. }
  254. static void sde_configure_qdss(struct sde_encoder_virt *sde_enc,
  255. struct sde_hw_qdss *hw_qdss,
  256. struct sde_encoder_phys *phys, bool enable)
  257. {
  258. if (sde_enc->qdss_status == enable)
  259. return;
  260. sde_enc->qdss_status = enable;
  261. phys->hw_mdptop->ops.set_mdp_hw_events(phys->hw_mdptop,
  262. sde_enc->qdss_status);
  263. hw_qdss->ops.enable_qdss_events(hw_qdss, sde_enc->qdss_status);
  264. }
  265. static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,
  266. s64 timeout_ms, struct sde_encoder_wait_info *info)
  267. {
  268. int rc = 0;
  269. s64 wait_time_jiffies = msecs_to_jiffies(timeout_ms);
  270. ktime_t cur_ktime;
  271. ktime_t exp_ktime = ktime_add_ms(ktime_get(), timeout_ms);
  272. do {
  273. rc = wait_event_timeout(*(info->wq),
  274. atomic_read(info->atomic_cnt) == info->count_check,
  275. wait_time_jiffies);
  276. cur_ktime = ktime_get();
  277. SDE_EVT32(drm_id, hw_id, rc, ktime_to_ms(cur_ktime),
  278. timeout_ms, atomic_read(info->atomic_cnt),
  279. info->count_check);
  280. /* If we timed out, counter is valid and time is less, wait again */
  281. } while ((atomic_read(info->atomic_cnt) != info->count_check) &&
  282. (rc == 0) &&
  283. (ktime_compare_safe(exp_ktime, cur_ktime) > 0));
  284. return rc;
  285. }
  286. bool sde_encoder_is_primary_display(struct drm_encoder *drm_enc)
  287. {
  288. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  289. return sde_enc &&
  290. (sde_enc->disp_info.display_type ==
  291. SDE_CONNECTOR_PRIMARY);
  292. }
  293. bool sde_encoder_is_dsi_display(struct drm_encoder *drm_enc)
  294. {
  295. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  296. return sde_enc &&
  297. (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI);
  298. }
  299. int sde_encoder_in_cont_splash(struct drm_encoder *drm_enc)
  300. {
  301. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  302. return sde_enc && sde_enc->cur_master &&
  303. sde_enc->cur_master->cont_splash_enabled;
  304. }
  305. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  306. enum sde_intr_idx intr_idx)
  307. {
  308. SDE_EVT32(DRMID(phys_enc->parent),
  309. phys_enc->intf_idx - INTF_0,
  310. phys_enc->hw_pp->idx - PINGPONG_0,
  311. intr_idx);
  312. SDE_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
  313. if (phys_enc->parent_ops.handle_frame_done)
  314. phys_enc->parent_ops.handle_frame_done(
  315. phys_enc->parent, phys_enc,
  316. SDE_ENCODER_FRAME_EVENT_ERROR);
  317. }
  318. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  319. enum sde_intr_idx intr_idx,
  320. struct sde_encoder_wait_info *wait_info)
  321. {
  322. struct sde_encoder_irq *irq;
  323. u32 irq_status;
  324. int ret, i;
  325. if (!phys_enc || !phys_enc->hw_pp || !wait_info || intr_idx >= INTR_IDX_MAX) {
  326. SDE_ERROR("invalid params\n");
  327. return -EINVAL;
  328. }
  329. irq = &phys_enc->irq[intr_idx];
  330. /* note: do master / slave checking outside */
  331. /* return EWOULDBLOCK since we know the wait isn't necessary */
  332. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  333. SDE_ERROR_PHYS(phys_enc, "encoder is disabled\n");
  334. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  335. irq->irq_idx, intr_idx, SDE_EVTLOG_ERROR);
  336. return -EWOULDBLOCK;
  337. }
  338. if (irq->irq_idx < 0) {
  339. SDE_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
  340. irq->name, irq->hw_idx);
  341. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  342. irq->irq_idx);
  343. return 0;
  344. }
  345. SDE_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
  346. atomic_read(wait_info->atomic_cnt));
  347. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  348. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  349. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_ENTRY);
  350. /*
  351. * Some module X may disable interrupt for longer duration
  352. * and it may trigger all interrupts including timer interrupt
  353. * when module X again enable the interrupt.
  354. * That may cause interrupt wait timeout API in this API.
  355. * It is handled by split the wait timer in two halves.
  356. */
  357. for (i = 0; i < EVT_TIME_OUT_SPLIT; i++) {
  358. ret = _sde_encoder_wait_timeout(DRMID(phys_enc->parent),
  359. irq->hw_idx,
  360. (wait_info->timeout_ms/EVT_TIME_OUT_SPLIT),
  361. wait_info);
  362. if (ret)
  363. break;
  364. }
  365. if (ret <= 0) {
  366. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  367. irq->irq_idx, true);
  368. if (irq_status) {
  369. unsigned long flags;
  370. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  371. irq->hw_idx, irq->irq_idx,
  372. phys_enc->hw_pp->idx - PINGPONG_0,
  373. atomic_read(wait_info->atomic_cnt));
  374. SDE_DEBUG_PHYS(phys_enc,
  375. "done but irq %d not triggered\n",
  376. irq->irq_idx);
  377. local_irq_save(flags);
  378. irq->cb.func(phys_enc, irq->irq_idx);
  379. local_irq_restore(flags);
  380. ret = 0;
  381. } else {
  382. ret = -ETIMEDOUT;
  383. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  384. irq->hw_idx, irq->irq_idx,
  385. phys_enc->hw_pp->idx - PINGPONG_0,
  386. atomic_read(wait_info->atomic_cnt), irq_status,
  387. SDE_EVTLOG_ERROR);
  388. }
  389. } else {
  390. ret = 0;
  391. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  392. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  393. atomic_read(wait_info->atomic_cnt));
  394. }
  395. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  396. irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
  397. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_EXIT);
  398. return ret;
  399. }
  400. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  401. enum sde_intr_idx intr_idx)
  402. {
  403. struct sde_encoder_irq *irq;
  404. int ret = 0;
  405. if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
  406. SDE_ERROR("invalid params\n");
  407. return -EINVAL;
  408. }
  409. irq = &phys_enc->irq[intr_idx];
  410. if (irq->irq_idx >= 0) {
  411. SDE_DEBUG_PHYS(phys_enc,
  412. "skipping already registered irq %s type %d\n",
  413. irq->name, irq->intr_type);
  414. return 0;
  415. }
  416. irq->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
  417. irq->intr_type, irq->hw_idx);
  418. if (irq->irq_idx < 0) {
  419. SDE_ERROR_PHYS(phys_enc,
  420. "failed to lookup IRQ index for %s type:%d\n",
  421. irq->name, irq->intr_type);
  422. return -EINVAL;
  423. }
  424. ret = sde_core_irq_register_callback(phys_enc->sde_kms, irq->irq_idx,
  425. &irq->cb);
  426. if (ret) {
  427. SDE_ERROR_PHYS(phys_enc,
  428. "failed to register IRQ callback for %s\n",
  429. irq->name);
  430. irq->irq_idx = -EINVAL;
  431. return ret;
  432. }
  433. ret = sde_core_irq_enable(phys_enc->sde_kms, &irq->irq_idx, 1);
  434. if (ret) {
  435. SDE_ERROR_PHYS(phys_enc,
  436. "enable IRQ for intr:%s failed, irq_idx %d\n",
  437. irq->name, irq->irq_idx);
  438. sde_core_irq_unregister_callback(phys_enc->sde_kms,
  439. irq->irq_idx, &irq->cb);
  440. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  441. irq->irq_idx, SDE_EVTLOG_ERROR);
  442. irq->irq_idx = -EINVAL;
  443. return ret;
  444. }
  445. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  446. SDE_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
  447. irq->name, irq->irq_idx);
  448. return ret;
  449. }
  450. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  451. enum sde_intr_idx intr_idx)
  452. {
  453. struct sde_encoder_irq *irq;
  454. int ret;
  455. if (!phys_enc) {
  456. SDE_ERROR("invalid encoder\n");
  457. return -EINVAL;
  458. }
  459. irq = &phys_enc->irq[intr_idx];
  460. /* silently skip irqs that weren't registered */
  461. if (irq->irq_idx < 0) {
  462. SDE_ERROR(
  463. "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
  464. DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  465. irq->irq_idx);
  466. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  467. irq->irq_idx, SDE_EVTLOG_ERROR);
  468. return 0;
  469. }
  470. ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
  471. if (ret)
  472. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  473. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  474. ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
  475. &irq->cb);
  476. if (ret)
  477. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  478. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  479. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  480. SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
  481. irq->irq_idx = -EINVAL;
  482. return 0;
  483. }
  484. void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  485. struct sde_encoder_hw_resources *hw_res,
  486. struct drm_connector_state *conn_state)
  487. {
  488. struct sde_encoder_virt *sde_enc = NULL;
  489. int ret, i = 0;
  490. if (!hw_res || !drm_enc || !conn_state || !hw_res->comp_info) {
  491. SDE_ERROR("rc %d, drm_enc %d, res %d, state %d, comp-info %d\n",
  492. -EINVAL, !drm_enc, !hw_res, !conn_state,
  493. hw_res ? !hw_res->comp_info : 0);
  494. return;
  495. }
  496. sde_enc = to_sde_encoder_virt(drm_enc);
  497. SDE_DEBUG_ENC(sde_enc, "\n");
  498. hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
  499. hw_res->display_type = sde_enc->disp_info.display_type;
  500. /* Query resources used by phys encs, expected to be without overlap */
  501. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  502. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  503. if (phys && phys->ops.get_hw_resources)
  504. phys->ops.get_hw_resources(phys, hw_res, conn_state);
  505. }
  506. /*
  507. * NOTE: Do not use sde_encoder_get_mode_info here as this function is
  508. * called from atomic_check phase. Use the below API to get mode
  509. * information of the temporary conn_state passed
  510. */
  511. ret = sde_connector_state_get_topology(conn_state, &hw_res->topology);
  512. if (ret)
  513. SDE_ERROR("failed to get topology ret %d\n", ret);
  514. ret = sde_connector_state_get_compression_info(conn_state,
  515. hw_res->comp_info);
  516. if (ret)
  517. SDE_ERROR("failed to get compression info ret %d\n", ret);
  518. }
  519. void sde_encoder_destroy(struct drm_encoder *drm_enc)
  520. {
  521. struct sde_encoder_virt *sde_enc = NULL;
  522. int i = 0;
  523. unsigned int num_encs;
  524. if (!drm_enc) {
  525. SDE_ERROR("invalid encoder\n");
  526. return;
  527. }
  528. sde_enc = to_sde_encoder_virt(drm_enc);
  529. SDE_DEBUG_ENC(sde_enc, "\n");
  530. num_encs = sde_enc->num_phys_encs;
  531. mutex_lock(&sde_enc->enc_lock);
  532. sde_rsc_client_destroy(sde_enc->rsc_client);
  533. for (i = 0; i < num_encs; i++) {
  534. struct sde_encoder_phys *phys;
  535. phys = sde_enc->phys_vid_encs[i];
  536. if (phys && phys->ops.destroy) {
  537. phys->ops.destroy(phys);
  538. --sde_enc->num_phys_encs;
  539. sde_enc->phys_vid_encs[i] = NULL;
  540. }
  541. phys = sde_enc->phys_cmd_encs[i];
  542. if (phys && phys->ops.destroy) {
  543. phys->ops.destroy(phys);
  544. --sde_enc->num_phys_encs;
  545. sde_enc->phys_cmd_encs[i] = NULL;
  546. }
  547. phys = sde_enc->phys_encs[i];
  548. if (phys && phys->ops.destroy) {
  549. phys->ops.destroy(phys);
  550. --sde_enc->num_phys_encs;
  551. sde_enc->phys_encs[i] = NULL;
  552. }
  553. }
  554. if (sde_enc->num_phys_encs)
  555. SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
  556. sde_enc->num_phys_encs);
  557. sde_enc->num_phys_encs = 0;
  558. mutex_unlock(&sde_enc->enc_lock);
  559. drm_encoder_cleanup(drm_enc);
  560. mutex_destroy(&sde_enc->enc_lock);
  561. kfree(sde_enc->input_handler);
  562. sde_enc->input_handler = NULL;
  563. kfree(sde_enc);
  564. }
  565. void sde_encoder_helper_update_intf_cfg(
  566. struct sde_encoder_phys *phys_enc)
  567. {
  568. struct sde_encoder_virt *sde_enc;
  569. struct sde_hw_intf_cfg_v1 *intf_cfg;
  570. enum sde_3d_blend_mode mode_3d;
  571. if (!phys_enc || !phys_enc->hw_pp) {
  572. SDE_ERROR("invalid args, encoder %d\n", !phys_enc);
  573. return;
  574. }
  575. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  576. intf_cfg = &sde_enc->cur_master->intf_cfg_v1;
  577. SDE_DEBUG_ENC(sde_enc,
  578. "intf_cfg updated for %d at idx %d\n",
  579. phys_enc->intf_idx,
  580. intf_cfg->intf_count);
  581. /* setup interface configuration */
  582. if (intf_cfg->intf_count >= MAX_INTF_PER_CTL_V1) {
  583. pr_err("invalid inf_count %d\n", intf_cfg->intf_count);
  584. return;
  585. }
  586. intf_cfg->intf[intf_cfg->intf_count++] = phys_enc->intf_idx;
  587. if (phys_enc == sde_enc->cur_master) {
  588. if (sde_enc->cur_master->intf_mode == INTF_MODE_CMD)
  589. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
  590. else
  591. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  592. }
  593. /* configure this interface as master for split display */
  594. if (phys_enc->split_role == ENC_ROLE_MASTER)
  595. intf_cfg->intf_master = phys_enc->hw_intf->idx;
  596. /* setup which pp blk will connect to this intf */
  597. if (phys_enc->hw_intf->ops.bind_pingpong_blk)
  598. phys_enc->hw_intf->ops.bind_pingpong_blk(
  599. phys_enc->hw_intf,
  600. true,
  601. phys_enc->hw_pp->idx);
  602. /*setup merge_3d configuration */
  603. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  604. if (mode_3d && phys_enc->hw_pp->merge_3d &&
  605. intf_cfg->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  606. intf_cfg->merge_3d[intf_cfg->merge_3d_count++] =
  607. phys_enc->hw_pp->merge_3d->idx;
  608. if (phys_enc->hw_pp->ops.setup_3d_mode)
  609. phys_enc->hw_pp->ops.setup_3d_mode(phys_enc->hw_pp,
  610. mode_3d);
  611. }
  612. void sde_encoder_helper_split_config(
  613. struct sde_encoder_phys *phys_enc,
  614. enum sde_intf interface)
  615. {
  616. struct sde_encoder_virt *sde_enc;
  617. struct split_pipe_cfg *cfg;
  618. struct sde_hw_mdp *hw_mdptop;
  619. enum sde_rm_topology_name topology;
  620. struct msm_display_info *disp_info;
  621. if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
  622. SDE_ERROR("invalid arg(s), encoder %d\n", !phys_enc);
  623. return;
  624. }
  625. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  626. hw_mdptop = phys_enc->hw_mdptop;
  627. disp_info = &sde_enc->disp_info;
  628. cfg = &phys_enc->hw_intf->cfg;
  629. memset(cfg, 0, sizeof(*cfg));
  630. if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
  631. return;
  632. if (disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK)
  633. cfg->split_link_en = true;
  634. /**
  635. * disable split modes since encoder will be operating in as the only
  636. * encoder, either for the entire use case in the case of, for example,
  637. * single DSI, or for this frame in the case of left/right only partial
  638. * update.
  639. */
  640. if (phys_enc->split_role == ENC_ROLE_SOLO) {
  641. if (hw_mdptop->ops.setup_split_pipe)
  642. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  643. if (hw_mdptop->ops.setup_pp_split)
  644. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  645. return;
  646. }
  647. cfg->en = true;
  648. cfg->mode = phys_enc->intf_mode;
  649. cfg->intf = interface;
  650. if (cfg->en && phys_enc->ops.needs_single_flush &&
  651. phys_enc->ops.needs_single_flush(phys_enc))
  652. cfg->split_flush_en = true;
  653. topology = sde_connector_get_topology_name(phys_enc->connector);
  654. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  655. cfg->pp_split_slave = cfg->intf;
  656. else
  657. cfg->pp_split_slave = INTF_MAX;
  658. if (phys_enc->split_role == ENC_ROLE_MASTER) {
  659. SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg->en);
  660. if (hw_mdptop->ops.setup_split_pipe)
  661. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  662. } else if (sde_enc->hw_pp[0]) {
  663. /*
  664. * slave encoder
  665. * - determine split index from master index,
  666. * assume master is first pp
  667. */
  668. cfg->pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
  669. SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
  670. cfg->pp_split_index);
  671. if (hw_mdptop->ops.setup_pp_split)
  672. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  673. }
  674. }
  675. bool sde_encoder_in_clone_mode(struct drm_encoder *drm_enc)
  676. {
  677. struct sde_encoder_virt *sde_enc;
  678. int i = 0;
  679. if (!drm_enc)
  680. return false;
  681. sde_enc = to_sde_encoder_virt(drm_enc);
  682. if (!sde_enc)
  683. return false;
  684. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  685. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  686. if (phys && phys->in_clone_mode)
  687. return true;
  688. }
  689. return false;
  690. }
  691. bool sde_encoder_is_cwb_disabling(struct drm_encoder *drm_enc,
  692. struct drm_crtc *crtc)
  693. {
  694. struct sde_encoder_virt *sde_enc;
  695. int i;
  696. if (!drm_enc)
  697. return false;
  698. sde_enc = to_sde_encoder_virt(drm_enc);
  699. if (sde_enc->disp_info.intf_type != DRM_MODE_CONNECTOR_VIRTUAL)
  700. return false;
  701. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  702. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  703. if (sde_encoder_phys_is_cwb_disabling(phys, crtc))
  704. return true;
  705. }
  706. return false;
  707. }
  708. static int _sde_encoder_atomic_check_phys_enc(struct sde_encoder_virt *sde_enc,
  709. struct drm_crtc_state *crtc_state,
  710. struct drm_connector_state *conn_state)
  711. {
  712. const struct drm_display_mode *mode;
  713. struct drm_display_mode *adj_mode;
  714. int i = 0;
  715. int ret = 0;
  716. mode = &crtc_state->mode;
  717. adj_mode = &crtc_state->adjusted_mode;
  718. /* perform atomic check on the first physical encoder (master) */
  719. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  720. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  721. if (phys && phys->ops.atomic_check)
  722. ret = phys->ops.atomic_check(phys, crtc_state,
  723. conn_state);
  724. else if (phys && phys->ops.mode_fixup)
  725. if (!phys->ops.mode_fixup(phys, mode, adj_mode))
  726. ret = -EINVAL;
  727. if (ret) {
  728. SDE_ERROR_ENC(sde_enc,
  729. "mode unsupported, phys idx %d\n", i);
  730. break;
  731. }
  732. }
  733. return ret;
  734. }
  735. static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc,
  736. struct drm_crtc_state *crtc_state,
  737. struct drm_connector_state *conn_state,
  738. struct sde_connector_state *sde_conn_state,
  739. struct sde_crtc_state *sde_crtc_state)
  740. {
  741. int ret = 0;
  742. if (crtc_state->mode_changed || crtc_state->active_changed) {
  743. struct sde_rect mode_roi, roi;
  744. mode_roi.x = 0;
  745. mode_roi.y = 0;
  746. mode_roi.w = crtc_state->adjusted_mode.hdisplay;
  747. mode_roi.h = crtc_state->adjusted_mode.vdisplay;
  748. if (sde_conn_state->rois.num_rects) {
  749. sde_kms_rect_merge_rectangles(
  750. &sde_conn_state->rois, &roi);
  751. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  752. SDE_ERROR_ENC(sde_enc,
  753. "roi (%d,%d,%d,%d) on connector invalid during modeset\n",
  754. roi.x, roi.y, roi.w, roi.h);
  755. ret = -EINVAL;
  756. }
  757. }
  758. if (sde_crtc_state->user_roi_list.num_rects) {
  759. sde_kms_rect_merge_rectangles(
  760. &sde_crtc_state->user_roi_list, &roi);
  761. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  762. SDE_ERROR_ENC(sde_enc,
  763. "roi (%d,%d,%d,%d) on crtc invalid during modeset\n",
  764. roi.x, roi.y, roi.w, roi.h);
  765. ret = -EINVAL;
  766. }
  767. }
  768. }
  769. return ret;
  770. }
  771. static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,
  772. struct drm_crtc_state *crtc_state,
  773. struct drm_connector_state *conn_state,
  774. struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,
  775. struct sde_connector *sde_conn,
  776. struct sde_connector_state *sde_conn_state)
  777. {
  778. int ret = 0;
  779. struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
  780. if (sde_conn && msm_atomic_needs_modeset(crtc_state)) {
  781. struct msm_display_topology *topology = NULL;
  782. ret = sde_connector_get_mode_info(&sde_conn->base,
  783. adj_mode, &sde_conn_state->mode_info);
  784. if (ret) {
  785. SDE_ERROR_ENC(sde_enc,
  786. "failed to get mode info, rc = %d\n", ret);
  787. return ret;
  788. }
  789. if (sde_conn_state->mode_info.comp_info.comp_type &&
  790. sde_conn_state->mode_info.comp_info.comp_ratio >=
  791. MSM_DISPLAY_COMPRESSION_RATIO_MAX) {
  792. SDE_ERROR_ENC(sde_enc,
  793. "invalid compression ratio: %d\n",
  794. sde_conn_state->mode_info.comp_info.comp_ratio);
  795. ret = -EINVAL;
  796. return ret;
  797. }
  798. /* Reserve dynamic resources, indicating atomic_check phase */
  799. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
  800. conn_state, true);
  801. if (ret) {
  802. if (ret != -EAGAIN)
  803. SDE_ERROR_ENC(sde_enc,
  804. "RM failed to reserve resources, rc = %d\n", ret);
  805. return ret;
  806. }
  807. /**
  808. * Update connector state with the topology selected for the
  809. * resource set validated. Reset the topology if we are
  810. * de-activating crtc.
  811. */
  812. if (crtc_state->active) {
  813. topology = &sde_conn_state->mode_info.topology;
  814. ret = sde_rm_update_topology(&sde_kms->rm,
  815. conn_state, topology);
  816. if (ret) {
  817. SDE_ERROR_ENC(sde_enc,
  818. "RM failed to update topology, rc: %d\n", ret);
  819. return ret;
  820. }
  821. }
  822. ret = sde_connector_set_blob_data(conn_state->connector,
  823. conn_state,
  824. CONNECTOR_PROP_SDE_INFO);
  825. if (ret) {
  826. SDE_ERROR_ENC(sde_enc,
  827. "connector failed to update info, rc: %d\n",
  828. ret);
  829. return ret;
  830. }
  831. }
  832. return ret;
  833. }
  834. static void _sde_encoder_get_qsync_fps_callback(
  835. struct drm_encoder *drm_enc, u32 *qsync_fps, u32 vrr_fps)
  836. {
  837. struct msm_display_info *disp_info;
  838. struct sde_encoder_virt *sde_enc;
  839. int rc = 0;
  840. struct sde_connector *sde_conn;
  841. if (!qsync_fps)
  842. return;
  843. *qsync_fps = 0;
  844. if (!drm_enc) {
  845. SDE_ERROR("invalid drm encoder\n");
  846. return;
  847. }
  848. sde_enc = to_sde_encoder_virt(drm_enc);
  849. disp_info = &sde_enc->disp_info;
  850. *qsync_fps = disp_info->qsync_min_fps;
  851. if (!disp_info->has_qsync_min_fps_list) {
  852. return;
  853. } else if (!sde_enc->cur_master || !(disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE)) {
  854. SDE_ERROR("invalid qsync settings %d\n", !sde_enc->cur_master);
  855. return;
  856. }
  857. /*
  858. * If "dsi-supported-qsync-min-fps-list" is defined, get
  859. * the qsync min fps corresponding to the fps in dfps list
  860. */
  861. sde_conn = to_sde_connector(sde_enc->cur_master->connector);
  862. if (sde_conn->ops.get_qsync_min_fps)
  863. rc = sde_conn->ops.get_qsync_min_fps(sde_conn->display, vrr_fps);
  864. if (rc <= 0) {
  865. SDE_ERROR("invalid qsync min fps %d\n", rc);
  866. return;
  867. }
  868. *qsync_fps = rc;
  869. }
  870. static int _sde_encoder_avr_step_check(struct sde_connector *sde_conn,
  871. struct sde_connector_state *sde_conn_state, u32 step)
  872. {
  873. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(sde_conn_state->base.best_encoder);
  874. u32 nom_fps = drm_mode_vrefresh(sde_conn_state->msm_mode.base);
  875. u32 min_fps, req_fps = 0;
  876. u32 vtotal = sde_conn_state->msm_mode.base->vtotal;
  877. bool has_panel_req = sde_enc->disp_info.has_avr_step_req;
  878. u32 qsync_mode = sde_connector_get_property(&sde_conn_state->base,
  879. CONNECTOR_PROP_QSYNC_MODE);
  880. if (has_panel_req) {
  881. if (!sde_conn->ops.get_avr_step_req) {
  882. SDE_ERROR("unable to retrieve required step rate\n");
  883. return -EINVAL;
  884. }
  885. req_fps = sde_conn->ops.get_avr_step_req(sde_conn->display, nom_fps);
  886. /* when qsync is enabled, the step fps *must* be set to the panel requirement */
  887. if (qsync_mode && req_fps != step) {
  888. SDE_ERROR("invalid avr_step %u, panel requires %u at nominal %u fps\n",
  889. step, req_fps, nom_fps);
  890. return -EINVAL;
  891. }
  892. }
  893. if (!step)
  894. return 0;
  895. _sde_encoder_get_qsync_fps_callback(sde_conn_state->base.best_encoder, &min_fps, nom_fps);
  896. if (!min_fps || !nom_fps || step % nom_fps || step % min_fps || step < nom_fps ||
  897. (vtotal * nom_fps) % step) {
  898. SDE_ERROR("invalid avr_step rate! nom:%u min:%u step:%u vtotal:%u\n", nom_fps,
  899. min_fps, step, vtotal);
  900. return -EINVAL;
  901. }
  902. return 0;
  903. }
  904. static int _sde_encoder_atomic_check_qsync(struct sde_connector *sde_conn,
  905. struct sde_connector_state *sde_conn_state)
  906. {
  907. int rc = 0;
  908. u32 avr_step;
  909. bool qsync_dirty, has_modeset;
  910. struct drm_connector_state *conn_state = &sde_conn_state->base;
  911. u32 qsync_mode = sde_connector_get_property(&sde_conn_state->base,
  912. CONNECTOR_PROP_QSYNC_MODE);
  913. has_modeset = sde_crtc_atomic_check_has_modeset(conn_state->state, conn_state->crtc);
  914. qsync_dirty = msm_property_is_dirty(&sde_conn->property_info,
  915. &sde_conn_state->property_state, CONNECTOR_PROP_QSYNC_MODE);
  916. if (has_modeset && qsync_dirty &&
  917. (msm_is_mode_seamless_poms(&sde_conn_state->msm_mode) ||
  918. msm_is_mode_seamless_dms(&sde_conn_state->msm_mode) ||
  919. msm_is_mode_seamless_dyn_clk(&sde_conn_state->msm_mode))) {
  920. SDE_ERROR("invalid qsync update during modeset priv flag:%x\n",
  921. sde_conn_state->msm_mode.private_flags);
  922. return -EINVAL;
  923. }
  924. avr_step = sde_connector_get_property(conn_state, CONNECTOR_PROP_AVR_STEP);
  925. if (qsync_dirty || (avr_step != sde_conn->avr_step) || (qsync_mode && has_modeset))
  926. rc = _sde_encoder_avr_step_check(sde_conn, sde_conn_state, avr_step);
  927. return rc;
  928. }
  929. static int sde_encoder_virt_atomic_check(
  930. struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,
  931. struct drm_connector_state *conn_state)
  932. {
  933. struct sde_encoder_virt *sde_enc;
  934. struct sde_kms *sde_kms;
  935. const struct drm_display_mode *mode;
  936. struct drm_display_mode *adj_mode;
  937. struct sde_connector *sde_conn = NULL;
  938. struct sde_connector_state *sde_conn_state = NULL;
  939. struct sde_crtc_state *sde_crtc_state = NULL;
  940. enum sde_rm_topology_name old_top;
  941. enum sde_rm_topology_name top_name;
  942. struct msm_display_info *disp_info;
  943. int ret = 0;
  944. if (!drm_enc || !crtc_state || !conn_state) {
  945. SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
  946. !drm_enc, !crtc_state, !conn_state);
  947. return -EINVAL;
  948. }
  949. sde_enc = to_sde_encoder_virt(drm_enc);
  950. disp_info = &sde_enc->disp_info;
  951. SDE_DEBUG_ENC(sde_enc, "\n");
  952. sde_kms = sde_encoder_get_kms(drm_enc);
  953. if (!sde_kms)
  954. return -EINVAL;
  955. mode = &crtc_state->mode;
  956. adj_mode = &crtc_state->adjusted_mode;
  957. sde_conn = to_sde_connector(conn_state->connector);
  958. sde_conn_state = to_sde_connector_state(conn_state);
  959. sde_crtc_state = to_sde_crtc_state(crtc_state);
  960. ret = sde_connector_set_msm_mode(conn_state, adj_mode);
  961. if (ret)
  962. return ret;
  963. SDE_EVT32(DRMID(drm_enc), crtc_state->mode_changed,
  964. crtc_state->active_changed, crtc_state->connectors_changed);
  965. ret = _sde_encoder_atomic_check_phys_enc(sde_enc, crtc_state,
  966. conn_state);
  967. if (ret)
  968. return ret;
  969. ret = _sde_encoder_atomic_check_pu_roi(sde_enc, crtc_state,
  970. conn_state, sde_conn_state, sde_crtc_state);
  971. if (ret)
  972. return ret;
  973. /**
  974. * record topology in previous atomic state to be able to handle
  975. * topology transitions correctly.
  976. */
  977. old_top = sde_connector_get_property(conn_state,
  978. CONNECTOR_PROP_TOPOLOGY_NAME);
  979. ret = sde_connector_set_old_topology_name(conn_state, old_top);
  980. if (ret)
  981. return ret;
  982. ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,
  983. conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);
  984. if (ret)
  985. return ret;
  986. top_name = sde_connector_get_property(conn_state,
  987. CONNECTOR_PROP_TOPOLOGY_NAME);
  988. if ((disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK) && crtc_state->active) {
  989. if ((top_name != SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE) &&
  990. (top_name != SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE)) {
  991. SDE_ERROR_ENC(sde_enc, "Splitlink check failed, top_name:%d",
  992. top_name);
  993. return -EINVAL;
  994. }
  995. }
  996. ret = sde_connector_roi_v1_check_roi(conn_state);
  997. if (ret) {
  998. SDE_ERROR_ENC(sde_enc, "connector roi check failed, rc: %d",
  999. ret);
  1000. return ret;
  1001. }
  1002. drm_mode_set_crtcinfo(adj_mode, 0);
  1003. ret = _sde_encoder_atomic_check_qsync(sde_conn, sde_conn_state);
  1004. SDE_EVT32(DRMID(drm_enc), adj_mode->flags,
  1005. sde_conn_state->msm_mode.private_flags,
  1006. old_top, drm_mode_vrefresh(adj_mode), adj_mode->hdisplay,
  1007. adj_mode->vdisplay, adj_mode->htotal, adj_mode->vtotal, ret);
  1008. return ret;
  1009. }
  1010. static void _sde_encoder_get_connector_roi(
  1011. struct sde_encoder_virt *sde_enc,
  1012. struct sde_rect *merged_conn_roi)
  1013. {
  1014. struct drm_connector *drm_conn;
  1015. struct sde_connector_state *c_state;
  1016. if (!sde_enc || !merged_conn_roi)
  1017. return;
  1018. drm_conn = sde_enc->phys_encs[0]->connector;
  1019. if (!drm_conn || !drm_conn->state)
  1020. return;
  1021. c_state = to_sde_connector_state(drm_conn->state);
  1022. sde_kms_rect_merge_rectangles(&c_state->rois, merged_conn_roi);
  1023. }
  1024. static int _sde_encoder_update_roi(struct drm_encoder *drm_enc)
  1025. {
  1026. struct sde_encoder_virt *sde_enc;
  1027. struct drm_connector *drm_conn;
  1028. struct drm_display_mode *adj_mode;
  1029. struct sde_rect roi;
  1030. if (!drm_enc) {
  1031. SDE_ERROR("invalid encoder parameter\n");
  1032. return -EINVAL;
  1033. }
  1034. sde_enc = to_sde_encoder_virt(drm_enc);
  1035. if (!sde_enc->crtc || !sde_enc->crtc->state) {
  1036. SDE_ERROR("invalid crtc parameter\n");
  1037. return -EINVAL;
  1038. }
  1039. if (!sde_enc->cur_master) {
  1040. SDE_ERROR("invalid cur_master parameter\n");
  1041. return -EINVAL;
  1042. }
  1043. adj_mode = &sde_enc->cur_master->cached_mode;
  1044. drm_conn = sde_enc->cur_master->connector;
  1045. _sde_encoder_get_connector_roi(sde_enc, &roi);
  1046. if (sde_kms_rect_is_null(&roi)) {
  1047. roi.w = adj_mode->hdisplay;
  1048. roi.h = adj_mode->vdisplay;
  1049. }
  1050. memcpy(&sde_enc->prv_conn_roi, &sde_enc->cur_conn_roi,
  1051. sizeof(sde_enc->prv_conn_roi));
  1052. memcpy(&sde_enc->cur_conn_roi, &roi, sizeof(sde_enc->cur_conn_roi));
  1053. return 0;
  1054. }
  1055. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc, u32 vsync_source)
  1056. {
  1057. struct sde_vsync_source_cfg vsync_cfg = { 0 };
  1058. struct sde_kms *sde_kms;
  1059. struct sde_hw_mdp *hw_mdptop;
  1060. struct sde_encoder_virt *sde_enc;
  1061. int i;
  1062. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  1063. if (!sde_enc) {
  1064. SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL);
  1065. return;
  1066. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  1067. SDE_ERROR("invalid num phys enc %d/%d\n",
  1068. sde_enc->num_phys_encs,
  1069. (int) ARRAY_SIZE(sde_enc->hw_pp));
  1070. return;
  1071. }
  1072. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  1073. if (!sde_kms) {
  1074. SDE_ERROR("invalid sde_kms\n");
  1075. return;
  1076. }
  1077. hw_mdptop = sde_kms->hw_mdp;
  1078. if (!hw_mdptop) {
  1079. SDE_ERROR("invalid mdptop\n");
  1080. return;
  1081. }
  1082. if (hw_mdptop->ops.setup_vsync_source) {
  1083. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1084. vsync_cfg.ppnumber[i] = sde_enc->hw_pp[i]->idx;
  1085. vsync_cfg.pp_count = sde_enc->num_phys_encs;
  1086. vsync_cfg.frame_rate = sde_enc->mode_info.frame_rate;
  1087. vsync_cfg.vsync_source = vsync_source;
  1088. hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
  1089. }
  1090. }
  1091. static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc,
  1092. struct msm_display_info *disp_info)
  1093. {
  1094. struct sde_encoder_phys *phys;
  1095. int i;
  1096. u32 vsync_source;
  1097. if (!sde_enc || !disp_info) {
  1098. SDE_ERROR("invalid param sde_enc:%d or disp_info:%d\n",
  1099. sde_enc != NULL, disp_info != NULL);
  1100. return;
  1101. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  1102. SDE_ERROR("invalid num phys enc %d/%d\n",
  1103. sde_enc->num_phys_encs,
  1104. (int) ARRAY_SIZE(sde_enc->hw_pp));
  1105. return;
  1106. }
  1107. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)) {
  1108. if (disp_info->is_te_using_watchdog_timer)
  1109. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_4 + sde_enc->te_source;
  1110. else
  1111. vsync_source = sde_enc->te_source;
  1112. SDE_EVT32(DRMID(&sde_enc->base), vsync_source,
  1113. disp_info->is_te_using_watchdog_timer);
  1114. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1115. phys = sde_enc->phys_encs[i];
  1116. if (phys && phys->ops.setup_vsync_source)
  1117. phys->ops.setup_vsync_source(phys, vsync_source);
  1118. }
  1119. }
  1120. }
  1121. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  1122. bool watchdog_te)
  1123. {
  1124. struct sde_encoder_virt *sde_enc;
  1125. struct msm_display_info disp_info;
  1126. if (!drm_enc) {
  1127. pr_err("invalid drm encoder\n");
  1128. return -EINVAL;
  1129. }
  1130. sde_enc = to_sde_encoder_virt(drm_enc);
  1131. sde_encoder_control_te(drm_enc, false);
  1132. memcpy(&disp_info, &sde_enc->disp_info, sizeof(disp_info));
  1133. disp_info.is_te_using_watchdog_timer = watchdog_te;
  1134. _sde_encoder_update_vsync_source(sde_enc, &disp_info);
  1135. sde_encoder_control_te(drm_enc, true);
  1136. return 0;
  1137. }
  1138. static int _sde_encoder_rsc_client_update_vsync_wait(
  1139. struct drm_encoder *drm_enc, struct sde_encoder_virt *sde_enc,
  1140. int wait_vblank_crtc_id)
  1141. {
  1142. int wait_refcount = 0, ret = 0;
  1143. int pipe = -1;
  1144. int wait_count = 0;
  1145. struct drm_crtc *primary_crtc;
  1146. struct drm_crtc *crtc;
  1147. crtc = sde_enc->crtc;
  1148. if (wait_vblank_crtc_id)
  1149. wait_refcount =
  1150. sde_rsc_client_get_vsync_refcount(sde_enc->rsc_client);
  1151. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1152. SDE_EVTLOG_FUNC_ENTRY);
  1153. if (crtc->base.id != wait_vblank_crtc_id) {
  1154. primary_crtc = drm_crtc_find(drm_enc->dev,
  1155. NULL, wait_vblank_crtc_id);
  1156. if (!primary_crtc) {
  1157. SDE_ERROR_ENC(sde_enc,
  1158. "failed to find primary crtc id %d\n",
  1159. wait_vblank_crtc_id);
  1160. return -EINVAL;
  1161. }
  1162. pipe = drm_crtc_index(primary_crtc);
  1163. }
  1164. /**
  1165. * note: VBLANK is expected to be enabled at this point in
  1166. * resource control state machine if on primary CRTC
  1167. */
  1168. for (wait_count = 0; wait_count < MAX_RSC_WAIT; wait_count++) {
  1169. if (sde_rsc_client_is_state_update_complete(
  1170. sde_enc->rsc_client))
  1171. break;
  1172. if (crtc->base.id == wait_vblank_crtc_id)
  1173. ret = sde_encoder_wait_for_event(drm_enc,
  1174. MSM_ENC_VBLANK);
  1175. else
  1176. drm_wait_one_vblank(drm_enc->dev, pipe);
  1177. if (ret) {
  1178. SDE_ERROR_ENC(sde_enc,
  1179. "wait for vblank failed ret:%d\n", ret);
  1180. /**
  1181. * rsc hardware may hang without vsync. avoid rsc hang
  1182. * by generating the vsync from watchdog timer.
  1183. */
  1184. if (crtc->base.id == wait_vblank_crtc_id)
  1185. sde_encoder_helper_switch_vsync(drm_enc, true);
  1186. }
  1187. }
  1188. if (wait_count >= MAX_RSC_WAIT)
  1189. SDE_EVT32(DRMID(drm_enc), wait_vblank_crtc_id, wait_count,
  1190. SDE_EVTLOG_ERROR);
  1191. if (wait_refcount)
  1192. sde_rsc_client_reset_vsync_refcount(sde_enc->rsc_client);
  1193. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1194. SDE_EVTLOG_FUNC_EXIT);
  1195. return ret;
  1196. }
  1197. static int _sde_encoder_update_rsc_client(
  1198. struct drm_encoder *drm_enc, bool enable)
  1199. {
  1200. struct sde_encoder_virt *sde_enc;
  1201. struct drm_crtc *crtc;
  1202. enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;
  1203. struct sde_rsc_cmd_config *rsc_config;
  1204. int ret;
  1205. struct msm_display_info *disp_info;
  1206. struct msm_mode_info *mode_info;
  1207. int wait_vblank_crtc_id = SDE_RSC_INVALID_CRTC_ID;
  1208. u32 qsync_mode = 0, v_front_porch;
  1209. struct drm_display_mode *mode;
  1210. bool is_vid_mode;
  1211. struct drm_encoder *enc;
  1212. if (!drm_enc || !drm_enc->dev) {
  1213. SDE_ERROR("invalid encoder arguments\n");
  1214. return -EINVAL;
  1215. }
  1216. sde_enc = to_sde_encoder_virt(drm_enc);
  1217. mode_info = &sde_enc->mode_info;
  1218. crtc = sde_enc->crtc;
  1219. if (!sde_enc->crtc) {
  1220. SDE_ERROR("invalid crtc parameter\n");
  1221. return -EINVAL;
  1222. }
  1223. disp_info = &sde_enc->disp_info;
  1224. rsc_config = &sde_enc->rsc_config;
  1225. if (!sde_enc->rsc_client) {
  1226. SDE_DEBUG_ENC(sde_enc, "rsc client not created\n");
  1227. return 0;
  1228. }
  1229. /**
  1230. * only primary command mode panel without Qsync can request CMD state.
  1231. * all other panels/displays can request for VID state including
  1232. * secondary command mode panel.
  1233. * Clone mode encoder can request CLK STATE only.
  1234. */
  1235. if (sde_enc->cur_master) {
  1236. qsync_mode = sde_connector_get_qsync_mode(
  1237. sde_enc->cur_master->connector);
  1238. sde_enc->autorefresh_solver_disable =
  1239. _sde_encoder_is_autorefresh_enabled(sde_enc) ? true : false;
  1240. }
  1241. /* left primary encoder keep vote */
  1242. if (sde_encoder_in_clone_mode(drm_enc)) {
  1243. SDE_EVT32(rsc_state, SDE_EVTLOG_FUNC_CASE1);
  1244. return 0;
  1245. }
  1246. if ((disp_info->display_type != SDE_CONNECTOR_PRIMARY) ||
  1247. (disp_info->display_type && qsync_mode) ||
  1248. sde_enc->autorefresh_solver_disable || mode_info->disable_rsc_solver)
  1249. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  1250. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1251. rsc_state = enable ? SDE_RSC_CMD_STATE : SDE_RSC_IDLE_STATE;
  1252. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE))
  1253. rsc_state = enable ? SDE_RSC_VID_STATE : SDE_RSC_IDLE_STATE;
  1254. drm_for_each_encoder(enc, drm_enc->dev) {
  1255. if (enc->base.id != drm_enc->base.id &&
  1256. sde_encoder_in_cont_splash(enc))
  1257. rsc_state = SDE_RSC_CLK_STATE;
  1258. }
  1259. is_vid_mode = sde_encoder_check_curr_mode(&sde_enc->base,
  1260. MSM_DISPLAY_VIDEO_MODE);
  1261. mode = &sde_enc->crtc->state->mode;
  1262. v_front_porch = mode->vsync_start - mode->vdisplay;
  1263. /* compare specific items and reconfigure the rsc */
  1264. if ((rsc_config->fps != mode_info->frame_rate) ||
  1265. (rsc_config->vtotal != mode_info->vtotal) ||
  1266. (rsc_config->prefill_lines != mode_info->prefill_lines) ||
  1267. (rsc_config->jitter_numer != mode_info->jitter_numer) ||
  1268. (rsc_config->jitter_denom != mode_info->jitter_denom)) {
  1269. rsc_config->fps = mode_info->frame_rate;
  1270. rsc_config->vtotal = mode_info->vtotal;
  1271. /*
  1272. * for video mode, prefill lines should not go beyond vertical
  1273. * front porch for RSCC configuration. This will ensure bw
  1274. * downvotes are not sent within the active region. Additional
  1275. * -1 is to give one line time for rscc mode min_threshold.
  1276. */
  1277. if (is_vid_mode && (mode_info->prefill_lines >= v_front_porch))
  1278. rsc_config->prefill_lines = v_front_porch - 1;
  1279. else
  1280. rsc_config->prefill_lines = mode_info->prefill_lines;
  1281. rsc_config->jitter_numer = mode_info->jitter_numer;
  1282. rsc_config->jitter_denom = mode_info->jitter_denom;
  1283. sde_enc->rsc_state_init = false;
  1284. }
  1285. SDE_EVT32(DRMID(drm_enc), rsc_state, qsync_mode,
  1286. rsc_config->fps, sde_enc->rsc_state_init);
  1287. if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
  1288. && (disp_info->display_type == SDE_CONNECTOR_PRIMARY)) {
  1289. /* update it only once */
  1290. sde_enc->rsc_state_init = true;
  1291. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1292. rsc_state, rsc_config, crtc->base.id,
  1293. &wait_vblank_crtc_id);
  1294. } else {
  1295. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1296. rsc_state, NULL, crtc->base.id,
  1297. &wait_vblank_crtc_id);
  1298. }
  1299. /**
  1300. * if RSC performed a state change that requires a VBLANK wait, it will
  1301. * set wait_vblank_crtc_id to the CRTC whose VBLANK we must wait on.
  1302. *
  1303. * if we are the primary display, we will need to enable and wait
  1304. * locally since we hold the commit thread
  1305. *
  1306. * if we are an external display, we must send a signal to the primary
  1307. * to enable its VBLANK and wait one, since the RSC hardware is driven
  1308. * by the primary panel's VBLANK signals
  1309. */
  1310. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id);
  1311. if (ret) {
  1312. SDE_ERROR_ENC(sde_enc,
  1313. "sde rsc client update failed ret:%d\n", ret);
  1314. return ret;
  1315. } else if (wait_vblank_crtc_id == SDE_RSC_INVALID_CRTC_ID) {
  1316. return ret;
  1317. }
  1318. ret = _sde_encoder_rsc_client_update_vsync_wait(drm_enc,
  1319. sde_enc, wait_vblank_crtc_id);
  1320. return ret;
  1321. }
  1322. void sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
  1323. {
  1324. struct sde_encoder_virt *sde_enc;
  1325. int i;
  1326. if (!drm_enc) {
  1327. SDE_ERROR("invalid encoder\n");
  1328. return;
  1329. }
  1330. sde_enc = to_sde_encoder_virt(drm_enc);
  1331. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1332. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1333. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1334. if (phys && phys->ops.irq_control)
  1335. phys->ops.irq_control(phys, enable);
  1336. }
  1337. sde_kms_cpu_vote_for_irq(sde_encoder_get_kms(drm_enc), enable);
  1338. }
  1339. /* keep track of the userspace vblank during modeset */
  1340. static void _sde_encoder_modeset_helper_locked(struct drm_encoder *drm_enc,
  1341. u32 sw_event)
  1342. {
  1343. struct sde_encoder_virt *sde_enc;
  1344. bool enable;
  1345. int i;
  1346. if (!drm_enc) {
  1347. SDE_ERROR("invalid encoder\n");
  1348. return;
  1349. }
  1350. sde_enc = to_sde_encoder_virt(drm_enc);
  1351. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, vblank_enabled:%d\n",
  1352. sw_event, sde_enc->vblank_enabled);
  1353. /* nothing to do if vblank not enabled by userspace */
  1354. if (!sde_enc->vblank_enabled)
  1355. return;
  1356. /* disable vblank on pre_modeset */
  1357. if (sw_event == SDE_ENC_RC_EVENT_PRE_MODESET)
  1358. enable = false;
  1359. /* enable vblank on post_modeset */
  1360. else if (sw_event == SDE_ENC_RC_EVENT_POST_MODESET)
  1361. enable = true;
  1362. else
  1363. return;
  1364. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1365. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1366. if (phys && phys->ops.control_vblank_irq)
  1367. phys->ops.control_vblank_irq(phys, enable);
  1368. }
  1369. }
  1370. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
  1371. {
  1372. struct sde_encoder_virt *sde_enc;
  1373. if (!drm_enc)
  1374. return NULL;
  1375. sde_enc = to_sde_encoder_virt(drm_enc);
  1376. return sde_enc->rsc_client;
  1377. }
  1378. static int _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
  1379. bool enable)
  1380. {
  1381. struct sde_kms *sde_kms;
  1382. struct sde_encoder_virt *sde_enc;
  1383. int rc;
  1384. sde_enc = to_sde_encoder_virt(drm_enc);
  1385. sde_kms = sde_encoder_get_kms(drm_enc);
  1386. if (!sde_kms)
  1387. return -EINVAL;
  1388. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1389. SDE_EVT32(DRMID(drm_enc), enable);
  1390. if (!sde_enc->cur_master) {
  1391. SDE_ERROR("encoder master not set\n");
  1392. return -EINVAL;
  1393. }
  1394. if (enable) {
  1395. /* enable SDE core clks */
  1396. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  1397. if (rc < 0) {
  1398. SDE_ERROR("failed to enable power resource %d\n", rc);
  1399. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1400. return rc;
  1401. }
  1402. sde_enc->elevated_ahb_vote = true;
  1403. /* enable DSI clks */
  1404. rc = sde_connector_clk_ctrl(sde_enc->cur_master->connector,
  1405. true);
  1406. if (rc) {
  1407. SDE_ERROR("failed to enable clk control %d\n", rc);
  1408. pm_runtime_put_sync(drm_enc->dev->dev);
  1409. return rc;
  1410. }
  1411. /* enable all the irq */
  1412. sde_encoder_irq_control(drm_enc, true);
  1413. _sde_encoder_pm_qos_add_request(drm_enc);
  1414. } else {
  1415. _sde_encoder_pm_qos_remove_request(drm_enc);
  1416. /* disable all the irq */
  1417. sde_encoder_irq_control(drm_enc, false);
  1418. /* disable DSI clks */
  1419. sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
  1420. /* disable SDE core clks */
  1421. pm_runtime_put_sync(drm_enc->dev->dev);
  1422. }
  1423. return 0;
  1424. }
  1425. static void sde_encoder_misr_configure(struct drm_encoder *drm_enc,
  1426. bool enable, u32 frame_count)
  1427. {
  1428. struct sde_encoder_virt *sde_enc;
  1429. int i;
  1430. if (!drm_enc) {
  1431. SDE_ERROR("invalid encoder\n");
  1432. return;
  1433. }
  1434. sde_enc = to_sde_encoder_virt(drm_enc);
  1435. if (!sde_enc->misr_reconfigure)
  1436. return;
  1437. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1438. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1439. if (!phys || !phys->ops.setup_misr)
  1440. continue;
  1441. phys->ops.setup_misr(phys, enable, frame_count);
  1442. }
  1443. sde_enc->misr_reconfigure = false;
  1444. }
  1445. static void sde_encoder_input_event_handler(struct input_handle *handle,
  1446. unsigned int type, unsigned int code, int value)
  1447. {
  1448. struct drm_encoder *drm_enc = NULL;
  1449. struct sde_encoder_virt *sde_enc = NULL;
  1450. struct msm_drm_thread *disp_thread = NULL;
  1451. struct msm_drm_private *priv = NULL;
  1452. if (!handle || !handle->handler || !handle->handler->private) {
  1453. SDE_ERROR("invalid encoder for the input event\n");
  1454. return;
  1455. }
  1456. drm_enc = (struct drm_encoder *)handle->handler->private;
  1457. if (!drm_enc->dev || !drm_enc->dev->dev_private) {
  1458. SDE_ERROR("invalid parameters\n");
  1459. return;
  1460. }
  1461. priv = drm_enc->dev->dev_private;
  1462. sde_enc = to_sde_encoder_virt(drm_enc);
  1463. if (!sde_enc->crtc || (sde_enc->crtc->index
  1464. >= ARRAY_SIZE(priv->disp_thread))) {
  1465. SDE_DEBUG_ENC(sde_enc,
  1466. "invalid cached CRTC: %d or crtc index: %d\n",
  1467. sde_enc->crtc == NULL,
  1468. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  1469. return;
  1470. }
  1471. SDE_EVT32_VERBOSE(DRMID(drm_enc));
  1472. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1473. kthread_queue_work(&disp_thread->worker,
  1474. &sde_enc->input_event_work);
  1475. }
  1476. void sde_encoder_control_idle_pc(struct drm_encoder *drm_enc, bool enable)
  1477. {
  1478. struct sde_encoder_virt *sde_enc;
  1479. if (!drm_enc) {
  1480. SDE_ERROR("invalid encoder\n");
  1481. return;
  1482. }
  1483. sde_enc = to_sde_encoder_virt(drm_enc);
  1484. /* return early if there is no state change */
  1485. if (sde_enc->idle_pc_enabled == enable)
  1486. return;
  1487. sde_enc->idle_pc_enabled = enable;
  1488. SDE_DEBUG("idle-pc state:%d\n", sde_enc->idle_pc_enabled);
  1489. SDE_EVT32(sde_enc->idle_pc_enabled);
  1490. }
  1491. static void _sde_encoder_rc_restart_delayed(struct sde_encoder_virt *sde_enc,
  1492. u32 sw_event)
  1493. {
  1494. struct drm_encoder *drm_enc = &sde_enc->base;
  1495. struct msm_drm_private *priv;
  1496. unsigned int lp, idle_pc_duration;
  1497. struct msm_drm_thread *disp_thread;
  1498. /* return early if called from esd thread */
  1499. if (sde_enc->delay_kickoff)
  1500. return;
  1501. /* set idle timeout based on master connector's lp value */
  1502. if (sde_enc->cur_master)
  1503. lp = sde_connector_get_lp(
  1504. sde_enc->cur_master->connector);
  1505. else
  1506. lp = SDE_MODE_DPMS_ON;
  1507. if (lp == SDE_MODE_DPMS_LP2)
  1508. idle_pc_duration = IDLE_SHORT_TIMEOUT;
  1509. else
  1510. idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
  1511. priv = drm_enc->dev->dev_private;
  1512. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1513. kthread_mod_delayed_work(
  1514. &disp_thread->worker,
  1515. &sde_enc->delayed_off_work,
  1516. msecs_to_jiffies(idle_pc_duration));
  1517. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1518. idle_pc_duration, SDE_EVTLOG_FUNC_CASE2);
  1519. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
  1520. sw_event);
  1521. }
  1522. static void _sde_encoder_rc_cancel_delayed(struct sde_encoder_virt *sde_enc,
  1523. u32 sw_event)
  1524. {
  1525. if (kthread_cancel_delayed_work_sync(&sde_enc->delayed_off_work))
  1526. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
  1527. sw_event);
  1528. }
  1529. static void _sde_encoder_rc_kickoff_delayed(struct sde_encoder_virt *sde_enc,
  1530. u32 sw_event)
  1531. {
  1532. if (_sde_encoder_is_autorefresh_enabled(sde_enc))
  1533. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1534. else
  1535. _sde_encoder_rc_restart_delayed(sde_enc, sw_event);
  1536. }
  1537. static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc,
  1538. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1539. {
  1540. int ret = 0;
  1541. mutex_lock(&sde_enc->rc_lock);
  1542. /* return if the resource control is already in ON state */
  1543. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1544. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
  1545. sw_event);
  1546. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1547. SDE_EVTLOG_FUNC_CASE1);
  1548. goto end;
  1549. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_OFF &&
  1550. sde_enc->rc_state != SDE_ENC_RC_STATE_IDLE) {
  1551. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1552. sw_event, sde_enc->rc_state);
  1553. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1554. SDE_EVTLOG_ERROR);
  1555. goto end;
  1556. }
  1557. if (is_vid_mode && sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1558. sde_encoder_irq_control(drm_enc, true);
  1559. } else {
  1560. /* enable all the clks and resources */
  1561. ret = _sde_encoder_resource_control_helper(drm_enc,
  1562. true);
  1563. if (ret) {
  1564. SDE_ERROR_ENC(sde_enc,
  1565. "sw_event:%d, rc in state %d\n",
  1566. sw_event, sde_enc->rc_state);
  1567. SDE_EVT32(DRMID(drm_enc), sw_event,
  1568. sde_enc->rc_state,
  1569. SDE_EVTLOG_ERROR);
  1570. goto end;
  1571. }
  1572. _sde_encoder_update_rsc_client(drm_enc, true);
  1573. }
  1574. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1575. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
  1576. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1577. end:
  1578. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1579. mutex_unlock(&sde_enc->rc_lock);
  1580. return ret;
  1581. }
  1582. static int _sde_encoder_rc_pre_stop(struct drm_encoder *drm_enc,
  1583. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1584. {
  1585. /* cancel delayed off work, if any */
  1586. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1587. mutex_lock(&sde_enc->rc_lock);
  1588. if (is_vid_mode &&
  1589. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1590. sde_encoder_irq_control(drm_enc, true);
  1591. }
  1592. /* skip if is already OFF or IDLE, resources are off already */
  1593. else if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF ||
  1594. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1595. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in %d state\n",
  1596. sw_event, sde_enc->rc_state);
  1597. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1598. SDE_EVTLOG_FUNC_CASE3);
  1599. goto end;
  1600. }
  1601. /**
  1602. * IRQs are still enabled currently, which allows wait for
  1603. * VBLANK which RSC may require to correctly transition to OFF
  1604. */
  1605. _sde_encoder_update_rsc_client(drm_enc, false);
  1606. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1607. SDE_ENC_RC_STATE_PRE_OFF,
  1608. SDE_EVTLOG_FUNC_CASE3);
  1609. sde_enc->rc_state = SDE_ENC_RC_STATE_PRE_OFF;
  1610. end:
  1611. mutex_unlock(&sde_enc->rc_lock);
  1612. return 0;
  1613. }
  1614. static int _sde_encoder_rc_stop(struct drm_encoder *drm_enc,
  1615. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1616. {
  1617. int ret = 0;
  1618. mutex_lock(&sde_enc->rc_lock);
  1619. /* return if the resource control is already in OFF state */
  1620. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1621. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1622. sw_event);
  1623. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1624. SDE_EVTLOG_FUNC_CASE4);
  1625. goto end;
  1626. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON ||
  1627. sde_enc->rc_state == SDE_ENC_RC_STATE_MODESET) {
  1628. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1629. sw_event, sde_enc->rc_state);
  1630. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1631. SDE_EVTLOG_ERROR);
  1632. ret = -EINVAL;
  1633. goto end;
  1634. }
  1635. /**
  1636. * expect to arrive here only if in either idle state or pre-off
  1637. * and in IDLE state the resources are already disabled
  1638. */
  1639. if (sde_enc->rc_state == SDE_ENC_RC_STATE_PRE_OFF)
  1640. _sde_encoder_resource_control_helper(drm_enc, false);
  1641. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1642. SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE4);
  1643. sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
  1644. end:
  1645. mutex_unlock(&sde_enc->rc_lock);
  1646. return ret;
  1647. }
  1648. static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
  1649. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1650. {
  1651. int ret = 0;
  1652. /* cancel delayed off work, if any */
  1653. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1654. mutex_lock(&sde_enc->rc_lock);
  1655. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1656. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1657. sw_event);
  1658. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1659. SDE_EVTLOG_FUNC_CASE5);
  1660. goto end;
  1661. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1662. /* enable all the clks and resources */
  1663. ret = _sde_encoder_resource_control_helper(drm_enc,
  1664. true);
  1665. if (ret) {
  1666. SDE_ERROR_ENC(sde_enc,
  1667. "sw_event:%d, rc in state %d\n",
  1668. sw_event, sde_enc->rc_state);
  1669. SDE_EVT32(DRMID(drm_enc), sw_event,
  1670. sde_enc->rc_state,
  1671. SDE_EVTLOG_ERROR);
  1672. goto end;
  1673. }
  1674. _sde_encoder_update_rsc_client(drm_enc, true);
  1675. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1676. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE5);
  1677. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1678. }
  1679. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1680. SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
  1681. sde_enc->rc_state = SDE_ENC_RC_STATE_MODESET;
  1682. _sde_encoder_pm_qos_remove_request(drm_enc);
  1683. end:
  1684. mutex_unlock(&sde_enc->rc_lock);
  1685. return ret;
  1686. }
  1687. static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
  1688. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1689. {
  1690. int ret = 0;
  1691. mutex_lock(&sde_enc->rc_lock);
  1692. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1693. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1694. sw_event);
  1695. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1696. SDE_EVTLOG_FUNC_CASE5);
  1697. goto end;
  1698. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_MODESET) {
  1699. SDE_ERROR_ENC(sde_enc,
  1700. "sw_event:%d, rc:%d !MODESET state\n",
  1701. sw_event, sde_enc->rc_state);
  1702. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1703. SDE_EVTLOG_ERROR);
  1704. ret = -EINVAL;
  1705. goto end;
  1706. }
  1707. _sde_encoder_update_rsc_client(drm_enc, true);
  1708. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1709. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE6);
  1710. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1711. _sde_encoder_pm_qos_add_request(drm_enc);
  1712. end:
  1713. mutex_unlock(&sde_enc->rc_lock);
  1714. return ret;
  1715. }
  1716. static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
  1717. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1718. {
  1719. struct msm_drm_private *priv;
  1720. struct sde_kms *sde_kms;
  1721. struct drm_crtc *crtc = drm_enc->crtc;
  1722. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1723. struct sde_connector *sde_conn;
  1724. priv = drm_enc->dev->dev_private;
  1725. sde_kms = to_sde_kms(priv->kms);
  1726. sde_conn = to_sde_connector(sde_enc->cur_master->connector);
  1727. mutex_lock(&sde_enc->rc_lock);
  1728. if (sde_conn->panel_dead) {
  1729. SDE_DEBUG_ENC(sde_enc, "skip idle. Panel in dead state\n");
  1730. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state, SDE_EVTLOG_ERROR);
  1731. goto end;
  1732. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1733. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
  1734. sw_event, sde_enc->rc_state);
  1735. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state, SDE_EVTLOG_ERROR);
  1736. goto end;
  1737. } else if (sde_crtc_frame_pending(sde_enc->crtc)) {
  1738. SDE_DEBUG_ENC(sde_enc, "skip idle entry");
  1739. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1740. sde_crtc_frame_pending(sde_enc->crtc), SDE_EVTLOG_ERROR);
  1741. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1742. goto end;
  1743. }
  1744. if (is_vid_mode) {
  1745. sde_encoder_irq_control(drm_enc, false);
  1746. } else {
  1747. /* disable all the clks and resources */
  1748. _sde_encoder_update_rsc_client(drm_enc, false);
  1749. _sde_encoder_resource_control_helper(drm_enc, false);
  1750. if (!sde_kms->perf.bw_vote_mode)
  1751. memset(&sde_crtc->cur_perf, 0,
  1752. sizeof(struct sde_core_perf_params));
  1753. }
  1754. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1755. SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE7);
  1756. sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
  1757. end:
  1758. mutex_unlock(&sde_enc->rc_lock);
  1759. return 0;
  1760. }
  1761. static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
  1762. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1763. struct msm_drm_private *priv, bool is_vid_mode)
  1764. {
  1765. bool autorefresh_enabled = false;
  1766. struct msm_drm_thread *disp_thread;
  1767. int ret = 0;
  1768. if (!sde_enc->crtc ||
  1769. sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1770. SDE_DEBUG_ENC(sde_enc,
  1771. "invalid crtc:%d or crtc index:%d , sw_event:%u\n",
  1772. sde_enc->crtc == NULL,
  1773. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL,
  1774. sw_event);
  1775. return -EINVAL;
  1776. }
  1777. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1778. mutex_lock(&sde_enc->rc_lock);
  1779. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1780. if (sde_enc->cur_master &&
  1781. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1782. autorefresh_enabled =
  1783. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1784. sde_enc->cur_master);
  1785. if (autorefresh_enabled) {
  1786. SDE_DEBUG_ENC(sde_enc,
  1787. "not handling early wakeup since auto refresh is enabled\n");
  1788. goto end;
  1789. }
  1790. if (!sde_crtc_frame_pending(sde_enc->crtc))
  1791. kthread_mod_delayed_work(&disp_thread->worker,
  1792. &sde_enc->delayed_off_work,
  1793. msecs_to_jiffies(
  1794. IDLE_POWERCOLLAPSE_DURATION));
  1795. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1796. /* enable all the clks and resources */
  1797. ret = _sde_encoder_resource_control_helper(drm_enc,
  1798. true);
  1799. if (ret) {
  1800. SDE_ERROR_ENC(sde_enc,
  1801. "sw_event:%d, rc in state %d\n",
  1802. sw_event, sde_enc->rc_state);
  1803. SDE_EVT32(DRMID(drm_enc), sw_event,
  1804. sde_enc->rc_state,
  1805. SDE_EVTLOG_ERROR);
  1806. goto end;
  1807. }
  1808. _sde_encoder_update_rsc_client(drm_enc, true);
  1809. /*
  1810. * In some cases, commit comes with slight delay
  1811. * (> 80 ms)after early wake up, prevent clock switch
  1812. * off to avoid jank in next update. So, increase the
  1813. * command mode idle timeout sufficiently to prevent
  1814. * such case.
  1815. */
  1816. kthread_mod_delayed_work(&disp_thread->worker,
  1817. &sde_enc->delayed_off_work,
  1818. msecs_to_jiffies(
  1819. IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
  1820. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1821. }
  1822. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1823. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
  1824. end:
  1825. mutex_unlock(&sde_enc->rc_lock);
  1826. return ret;
  1827. }
  1828. static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
  1829. u32 sw_event)
  1830. {
  1831. struct sde_encoder_virt *sde_enc;
  1832. struct msm_drm_private *priv;
  1833. int ret = 0;
  1834. bool is_vid_mode = false;
  1835. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  1836. SDE_ERROR("invalid encoder parameters, sw_event:%u\n",
  1837. sw_event);
  1838. return -EINVAL;
  1839. }
  1840. sde_enc = to_sde_encoder_virt(drm_enc);
  1841. priv = drm_enc->dev->dev_private;
  1842. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  1843. is_vid_mode = true;
  1844. /*
  1845. * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
  1846. * events and return early for other events (ie wb display).
  1847. */
  1848. if (!sde_enc->idle_pc_enabled &&
  1849. (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
  1850. sw_event != SDE_ENC_RC_EVENT_PRE_MODESET &&
  1851. sw_event != SDE_ENC_RC_EVENT_POST_MODESET &&
  1852. sw_event != SDE_ENC_RC_EVENT_STOP &&
  1853. sw_event != SDE_ENC_RC_EVENT_PRE_STOP))
  1854. return 0;
  1855. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc:%d\n",
  1856. sw_event, sde_enc->idle_pc_enabled);
  1857. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1858. sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
  1859. switch (sw_event) {
  1860. case SDE_ENC_RC_EVENT_KICKOFF:
  1861. ret = _sde_encoder_rc_kickoff(drm_enc, sw_event, sde_enc,
  1862. is_vid_mode);
  1863. break;
  1864. case SDE_ENC_RC_EVENT_PRE_STOP:
  1865. ret = _sde_encoder_rc_pre_stop(drm_enc, sw_event, sde_enc,
  1866. is_vid_mode);
  1867. break;
  1868. case SDE_ENC_RC_EVENT_STOP:
  1869. ret = _sde_encoder_rc_stop(drm_enc, sw_event, sde_enc);
  1870. break;
  1871. case SDE_ENC_RC_EVENT_PRE_MODESET:
  1872. ret = _sde_encoder_rc_pre_modeset(drm_enc, sw_event, sde_enc);
  1873. break;
  1874. case SDE_ENC_RC_EVENT_POST_MODESET:
  1875. ret = _sde_encoder_rc_post_modeset(drm_enc, sw_event, sde_enc);
  1876. break;
  1877. case SDE_ENC_RC_EVENT_ENTER_IDLE:
  1878. ret = _sde_encoder_rc_idle(drm_enc, sw_event, sde_enc,
  1879. is_vid_mode);
  1880. break;
  1881. case SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  1882. ret = _sde_encoder_rc_early_wakeup(drm_enc, sw_event, sde_enc,
  1883. priv, is_vid_mode);
  1884. break;
  1885. default:
  1886. SDE_EVT32(DRMID(drm_enc), sw_event, SDE_EVTLOG_ERROR);
  1887. SDE_ERROR("unexpected sw_event: %d\n", sw_event);
  1888. break;
  1889. }
  1890. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1891. sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
  1892. return ret;
  1893. }
  1894. static void sde_encoder_virt_mode_switch(struct drm_encoder *drm_enc,
  1895. enum sde_intf_mode intf_mode, struct msm_display_mode *adj_mode)
  1896. {
  1897. int i = 0;
  1898. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1899. bool poms_to_vid = msm_is_mode_seamless_poms_to_vid(adj_mode);
  1900. bool poms_to_cmd = msm_is_mode_seamless_poms_to_cmd(adj_mode);
  1901. if (poms_to_vid)
  1902. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  1903. else if (poms_to_cmd)
  1904. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  1905. _sde_encoder_update_rsc_client(drm_enc, true);
  1906. if (intf_mode == INTF_MODE_CMD && poms_to_vid) {
  1907. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1908. sde_enc->phys_encs[i] = sde_enc->phys_vid_encs[i];
  1909. SDE_DEBUG_ENC(sde_enc, "switch to video physical encoder\n");
  1910. SDE_EVT32(DRMID(&sde_enc->base), intf_mode, poms_to_cmd, poms_to_vid,
  1911. SDE_EVTLOG_FUNC_CASE1);
  1912. } else if (intf_mode == INTF_MODE_VIDEO && poms_to_cmd) {
  1913. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1914. sde_enc->phys_encs[i] = sde_enc->phys_cmd_encs[i];
  1915. SDE_DEBUG_ENC(sde_enc, "switch to command physical encoder\n");
  1916. SDE_EVT32(DRMID(&sde_enc->base), intf_mode, poms_to_cmd, poms_to_vid,
  1917. SDE_EVTLOG_FUNC_CASE2);
  1918. }
  1919. }
  1920. struct drm_connector *sde_encoder_get_connector(
  1921. struct drm_device *dev, struct drm_encoder *drm_enc)
  1922. {
  1923. struct drm_connector_list_iter conn_iter;
  1924. struct drm_connector *conn = NULL, *conn_search;
  1925. drm_connector_list_iter_begin(dev, &conn_iter);
  1926. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1927. if (conn_search->encoder == drm_enc) {
  1928. conn = conn_search;
  1929. break;
  1930. }
  1931. }
  1932. drm_connector_list_iter_end(&conn_iter);
  1933. return conn;
  1934. }
  1935. static void _sde_encoder_virt_populate_hw_res(struct drm_encoder *drm_enc)
  1936. {
  1937. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1938. struct sde_kms *sde_kms = sde_encoder_get_kms(drm_enc);
  1939. struct sde_rm_hw_iter pp_iter, qdss_iter;
  1940. struct sde_rm_hw_iter dsc_iter, vdc_iter;
  1941. struct sde_rm_hw_request request_hw;
  1942. int i, j;
  1943. sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
  1944. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1945. sde_enc->hw_pp[i] = NULL;
  1946. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  1947. break;
  1948. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  1949. }
  1950. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1951. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1952. if (phys) {
  1953. sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
  1954. SDE_HW_BLK_QDSS);
  1955. for (j = 0; j < QDSS_MAX; j++) {
  1956. if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
  1957. phys->hw_qdss =
  1958. (struct sde_hw_qdss *)qdss_iter.hw;
  1959. break;
  1960. }
  1961. }
  1962. }
  1963. }
  1964. sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);
  1965. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1966. sde_enc->hw_dsc[i] = NULL;
  1967. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  1968. break;
  1969. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  1970. }
  1971. sde_rm_init_hw_iter(&vdc_iter, drm_enc->base.id, SDE_HW_BLK_VDC);
  1972. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1973. sde_enc->hw_vdc[i] = NULL;
  1974. if (!sde_rm_get_hw(&sde_kms->rm, &vdc_iter))
  1975. break;
  1976. sde_enc->hw_vdc[i] = (struct sde_hw_vdc *) vdc_iter.hw;
  1977. }
  1978. /* Get PP for DSC configuration */
  1979. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1980. struct sde_hw_pingpong *pp = NULL;
  1981. unsigned long features = 0;
  1982. if (!sde_enc->hw_dsc[i])
  1983. continue;
  1984. request_hw.id = sde_enc->hw_dsc[i]->base.id;
  1985. request_hw.type = SDE_HW_BLK_PINGPONG;
  1986. if (!sde_rm_request_hw_blk(&sde_kms->rm, &request_hw))
  1987. break;
  1988. pp = (struct sde_hw_pingpong *) request_hw.hw;
  1989. features = pp->ops.get_hw_caps(pp);
  1990. if (test_bit(SDE_PINGPONG_DSC, &features))
  1991. sde_enc->hw_dsc_pp[i] = pp;
  1992. else
  1993. sde_enc->hw_dsc_pp[i] = NULL;
  1994. }
  1995. }
  1996. static int sde_encoder_virt_modeset_rc(struct drm_encoder *drm_enc,
  1997. struct msm_display_mode *msm_mode, bool pre_modeset)
  1998. {
  1999. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2000. enum sde_intf_mode intf_mode;
  2001. int ret;
  2002. bool is_cmd_mode = false;
  2003. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2004. is_cmd_mode = true;
  2005. if (pre_modeset) {
  2006. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2007. if (msm_is_mode_seamless_dms(msm_mode) ||
  2008. (msm_is_mode_seamless_dyn_clk(msm_mode) &&
  2009. is_cmd_mode)) {
  2010. /* restore resource state before releasing them */
  2011. ret = sde_encoder_resource_control(drm_enc,
  2012. SDE_ENC_RC_EVENT_PRE_MODESET);
  2013. if (ret) {
  2014. SDE_ERROR_ENC(sde_enc,
  2015. "sde resource control failed: %d\n",
  2016. ret);
  2017. return ret;
  2018. }
  2019. /*
  2020. * Disable dce before switching the mode and after pre-
  2021. * modeset to guarantee previous kickoff has finished.
  2022. */
  2023. sde_encoder_dce_disable(sde_enc);
  2024. } else if (msm_is_mode_seamless_poms(msm_mode)) {
  2025. _sde_encoder_modeset_helper_locked(drm_enc,
  2026. SDE_ENC_RC_EVENT_PRE_MODESET);
  2027. sde_encoder_virt_mode_switch(drm_enc, intf_mode,
  2028. msm_mode);
  2029. }
  2030. } else {
  2031. if (msm_is_mode_seamless_dms(msm_mode) ||
  2032. (msm_is_mode_seamless_dyn_clk(msm_mode) &&
  2033. is_cmd_mode))
  2034. sde_encoder_resource_control(&sde_enc->base,
  2035. SDE_ENC_RC_EVENT_POST_MODESET);
  2036. else if (msm_is_mode_seamless_poms(msm_mode))
  2037. _sde_encoder_modeset_helper_locked(drm_enc,
  2038. SDE_ENC_RC_EVENT_POST_MODESET);
  2039. }
  2040. return 0;
  2041. }
  2042. static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
  2043. struct drm_display_mode *mode,
  2044. struct drm_display_mode *adj_mode)
  2045. {
  2046. struct sde_encoder_virt *sde_enc;
  2047. struct sde_kms *sde_kms;
  2048. struct drm_connector *conn;
  2049. struct sde_connector_state *c_state;
  2050. struct msm_display_mode *msm_mode;
  2051. int i = 0, ret;
  2052. int num_lm, num_intf, num_pp_per_intf;
  2053. if (!drm_enc) {
  2054. SDE_ERROR("invalid encoder\n");
  2055. return;
  2056. }
  2057. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2058. SDE_ERROR("power resource is not enabled\n");
  2059. return;
  2060. }
  2061. sde_kms = sde_encoder_get_kms(drm_enc);
  2062. if (!sde_kms)
  2063. return;
  2064. sde_enc = to_sde_encoder_virt(drm_enc);
  2065. SDE_DEBUG_ENC(sde_enc, "\n");
  2066. SDE_EVT32(DRMID(drm_enc));
  2067. /*
  2068. * cache the crtc in sde_enc on enable for duration of use case
  2069. * for correctly servicing asynchronous irq events and timers
  2070. */
  2071. if (!drm_enc->crtc) {
  2072. SDE_ERROR("invalid crtc\n");
  2073. return;
  2074. }
  2075. sde_enc->crtc = drm_enc->crtc;
  2076. sde_crtc_set_qos_dirty(drm_enc->crtc);
  2077. /* get and store the mode_info */
  2078. conn = sde_encoder_get_connector(sde_kms->dev, drm_enc);
  2079. if (!conn) {
  2080. SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
  2081. return;
  2082. } else if (!conn->state) {
  2083. SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
  2084. return;
  2085. }
  2086. sde_connector_state_get_mode_info(conn->state, &sde_enc->mode_info);
  2087. sde_encoder_dce_set_bpp(sde_enc->mode_info, sde_enc->crtc);
  2088. c_state = to_sde_connector_state(conn->state);
  2089. if (!c_state) {
  2090. SDE_ERROR_ENC(sde_enc, "could not get connector state");
  2091. return;
  2092. }
  2093. /* release resources before seamless mode change */
  2094. msm_mode = &c_state->msm_mode;
  2095. ret = sde_encoder_virt_modeset_rc(drm_enc, msm_mode, true);
  2096. if (ret)
  2097. return;
  2098. /* reserve dynamic resources now, indicating non test-only */
  2099. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state, conn->state, false);
  2100. if (ret) {
  2101. SDE_ERROR_ENC(sde_enc, "failed to reserve hw resources, %d\n", ret);
  2102. return;
  2103. }
  2104. /* assign the reserved HW blocks to this encoder */
  2105. _sde_encoder_virt_populate_hw_res(drm_enc);
  2106. /* determine left HW PP block to map to INTF */
  2107. num_lm = sde_enc->mode_info.topology.num_lm;
  2108. num_intf = sde_enc->mode_info.topology.num_intf;
  2109. num_pp_per_intf = num_lm / num_intf;
  2110. if (!num_pp_per_intf)
  2111. num_pp_per_intf = 1;
  2112. /* perform mode_set on phys_encs */
  2113. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2114. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2115. if (phys) {
  2116. if (!sde_enc->hw_pp[i * num_pp_per_intf] ||
  2117. sde_enc->topology.num_intf) {
  2118. SDE_ERROR_ENC(sde_enc, "invalid phys %d pp_per_intf %d num_intf %d",
  2119. i, num_pp_per_intf, sde_enc->topology.num_intf);
  2120. return;
  2121. }
  2122. phys->hw_pp = sde_enc->hw_pp[i * num_pp_per_intf];
  2123. phys->connector = conn->state->connector;
  2124. if (phys->ops.mode_set)
  2125. phys->ops.mode_set(phys, mode, adj_mode);
  2126. }
  2127. }
  2128. /* update resources after seamless mode change */
  2129. sde_encoder_virt_modeset_rc(drm_enc, msm_mode, false);
  2130. }
  2131. void sde_encoder_control_te(struct drm_encoder *drm_enc, bool enable)
  2132. {
  2133. struct sde_encoder_virt *sde_enc;
  2134. struct sde_encoder_phys *phys;
  2135. int i;
  2136. if (!drm_enc) {
  2137. SDE_ERROR("invalid parameters\n");
  2138. return;
  2139. }
  2140. sde_enc = to_sde_encoder_virt(drm_enc);
  2141. if (!sde_enc) {
  2142. SDE_ERROR("invalid sde encoder\n");
  2143. return;
  2144. }
  2145. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2146. phys = sde_enc->phys_encs[i];
  2147. if (phys && phys->ops.control_te)
  2148. phys->ops.control_te(phys, enable);
  2149. }
  2150. }
  2151. static int _sde_encoder_input_connect(struct input_handler *handler,
  2152. struct input_dev *dev, const struct input_device_id *id)
  2153. {
  2154. struct input_handle *handle;
  2155. int rc = 0;
  2156. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  2157. if (!handle)
  2158. return -ENOMEM;
  2159. handle->dev = dev;
  2160. handle->handler = handler;
  2161. handle->name = handler->name;
  2162. rc = input_register_handle(handle);
  2163. if (rc) {
  2164. pr_err("failed to register input handle\n");
  2165. goto error;
  2166. }
  2167. rc = input_open_device(handle);
  2168. if (rc) {
  2169. pr_err("failed to open input device\n");
  2170. goto error_unregister;
  2171. }
  2172. return 0;
  2173. error_unregister:
  2174. input_unregister_handle(handle);
  2175. error:
  2176. kfree(handle);
  2177. return rc;
  2178. }
  2179. static void _sde_encoder_input_disconnect(struct input_handle *handle)
  2180. {
  2181. input_close_device(handle);
  2182. input_unregister_handle(handle);
  2183. kfree(handle);
  2184. }
  2185. /**
  2186. * Structure for specifying event parameters on which to receive callbacks.
  2187. * This structure will trigger a callback in case of a touch event (specified by
  2188. * EV_ABS) where there is a change in X and Y coordinates,
  2189. */
  2190. static const struct input_device_id sde_input_ids[] = {
  2191. {
  2192. .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
  2193. .evbit = { BIT_MASK(EV_ABS) },
  2194. .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
  2195. BIT_MASK(ABS_MT_POSITION_X) |
  2196. BIT_MASK(ABS_MT_POSITION_Y) },
  2197. },
  2198. { },
  2199. };
  2200. static void _sde_encoder_input_handler_register(
  2201. struct drm_encoder *drm_enc)
  2202. {
  2203. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2204. int rc;
  2205. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE) ||
  2206. !sde_enc->input_event_enabled)
  2207. return;
  2208. if (sde_enc->input_handler && !sde_enc->input_handler->private) {
  2209. sde_enc->input_handler->private = sde_enc;
  2210. /* register input handler if not already registered */
  2211. rc = input_register_handler(sde_enc->input_handler);
  2212. if (rc) {
  2213. SDE_ERROR("input_handler_register failed, rc= %d\n",
  2214. rc);
  2215. kfree(sde_enc->input_handler);
  2216. }
  2217. }
  2218. }
  2219. static void _sde_encoder_input_handler_unregister(
  2220. struct drm_encoder *drm_enc)
  2221. {
  2222. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2223. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE) ||
  2224. !sde_enc->input_event_enabled)
  2225. return;
  2226. if (sde_enc->input_handler && sde_enc->input_handler->private) {
  2227. input_unregister_handler(sde_enc->input_handler);
  2228. sde_enc->input_handler->private = NULL;
  2229. }
  2230. }
  2231. static int _sde_encoder_input_handler(
  2232. struct sde_encoder_virt *sde_enc)
  2233. {
  2234. struct input_handler *input_handler = NULL;
  2235. int rc = 0;
  2236. if (sde_enc->input_handler) {
  2237. SDE_ERROR_ENC(sde_enc,
  2238. "input_handle is active. unexpected\n");
  2239. return -EINVAL;
  2240. }
  2241. input_handler = kzalloc(sizeof(*sde_enc->input_handler), GFP_KERNEL);
  2242. if (!input_handler)
  2243. return -ENOMEM;
  2244. input_handler->event = sde_encoder_input_event_handler;
  2245. input_handler->connect = _sde_encoder_input_connect;
  2246. input_handler->disconnect = _sde_encoder_input_disconnect;
  2247. input_handler->name = "sde";
  2248. input_handler->id_table = sde_input_ids;
  2249. sde_enc->input_handler = input_handler;
  2250. return rc;
  2251. }
  2252. static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
  2253. {
  2254. struct sde_encoder_virt *sde_enc = NULL;
  2255. struct sde_kms *sde_kms;
  2256. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  2257. SDE_ERROR("invalid parameters\n");
  2258. return;
  2259. }
  2260. sde_kms = sde_encoder_get_kms(drm_enc);
  2261. if (!sde_kms)
  2262. return;
  2263. sde_enc = to_sde_encoder_virt(drm_enc);
  2264. if (!sde_enc || !sde_enc->cur_master) {
  2265. SDE_DEBUG("invalid sde encoder/master\n");
  2266. return;
  2267. }
  2268. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
  2269. sde_enc->cur_master->hw_mdptop &&
  2270. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select)
  2271. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select(
  2272. sde_enc->cur_master->hw_mdptop);
  2273. if (sde_enc->cur_master->hw_mdptop &&
  2274. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc &&
  2275. !sde_in_trusted_vm(sde_kms))
  2276. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
  2277. sde_enc->cur_master->hw_mdptop,
  2278. sde_kms->catalog);
  2279. if (sde_enc->cur_master->hw_ctl &&
  2280. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1 &&
  2281. !sde_enc->cur_master->cont_splash_enabled)
  2282. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1(
  2283. sde_enc->cur_master->hw_ctl,
  2284. &sde_enc->cur_master->intf_cfg_v1);
  2285. _sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info);
  2286. sde_encoder_control_te(drm_enc, true);
  2287. memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));
  2288. memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
  2289. }
  2290. static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
  2291. {
  2292. struct sde_kms *sde_kms;
  2293. void *dither_cfg = NULL;
  2294. int ret = 0, i = 0;
  2295. size_t len = 0;
  2296. enum sde_rm_topology_name topology;
  2297. struct drm_encoder *drm_enc;
  2298. struct msm_display_dsc_info *dsc = NULL;
  2299. struct sde_encoder_virt *sde_enc;
  2300. struct sde_hw_pingpong *hw_pp;
  2301. u32 bpp, bpc;
  2302. int num_lm;
  2303. if (!phys || !phys->connector || !phys->hw_pp ||
  2304. !phys->hw_pp->ops.setup_dither || !phys->parent)
  2305. return;
  2306. sde_kms = sde_encoder_get_kms(phys->parent);
  2307. if (!sde_kms)
  2308. return;
  2309. topology = sde_connector_get_topology_name(phys->connector);
  2310. if ((topology == SDE_RM_TOPOLOGY_NONE) ||
  2311. ((topology == SDE_RM_TOPOLOGY_PPSPLIT) &&
  2312. (phys->split_role == ENC_ROLE_SLAVE)))
  2313. return;
  2314. drm_enc = phys->parent;
  2315. sde_enc = to_sde_encoder_virt(drm_enc);
  2316. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  2317. bpc = dsc->config.bits_per_component;
  2318. bpp = dsc->config.bits_per_pixel;
  2319. /* disable dither for 10 bpp or 10bpc dsc config */
  2320. if (bpp == 10 || bpc == 10) {
  2321. phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
  2322. return;
  2323. }
  2324. ret = sde_connector_get_dither_cfg(phys->connector,
  2325. phys->connector->state, &dither_cfg,
  2326. &len, sde_enc->idle_pc_restore);
  2327. /* skip reg writes when return values are invalid or no data */
  2328. if (ret && ret == -ENODATA)
  2329. return;
  2330. num_lm = sde_rm_topology_get_num_lm(&sde_kms->rm, topology);
  2331. for (i = 0; i < num_lm; i++) {
  2332. hw_pp = sde_enc->hw_pp[i];
  2333. phys->hw_pp->ops.setup_dither(hw_pp,
  2334. dither_cfg, len);
  2335. }
  2336. }
  2337. void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
  2338. {
  2339. struct sde_encoder_virt *sde_enc = NULL;
  2340. int i;
  2341. if (!drm_enc) {
  2342. SDE_ERROR("invalid encoder\n");
  2343. return;
  2344. }
  2345. sde_enc = to_sde_encoder_virt(drm_enc);
  2346. if (!sde_enc->cur_master) {
  2347. SDE_DEBUG("virt encoder has no master\n");
  2348. return;
  2349. }
  2350. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2351. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2352. sde_enc->idle_pc_restore = true;
  2353. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2354. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2355. if (!phys)
  2356. continue;
  2357. if (phys->hw_ctl && phys->hw_ctl->ops.clear_pending_flush)
  2358. phys->hw_ctl->ops.clear_pending_flush(phys->hw_ctl);
  2359. if ((phys != sde_enc->cur_master) && phys->ops.restore)
  2360. phys->ops.restore(phys);
  2361. _sde_encoder_setup_dither(phys);
  2362. }
  2363. if (sde_enc->cur_master->ops.restore)
  2364. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2365. _sde_encoder_virt_enable_helper(drm_enc);
  2366. }
  2367. static void sde_encoder_populate_encoder_phys(struct drm_encoder *drm_enc,
  2368. struct sde_encoder_virt *sde_enc, struct msm_display_mode *msm_mode)
  2369. {
  2370. struct msm_compression_info *comp_info = &sde_enc->mode_info.comp_info;
  2371. struct msm_display_info *disp_info = &sde_enc->disp_info;
  2372. int i;
  2373. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2374. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2375. if (!phys)
  2376. continue;
  2377. phys->comp_type = comp_info->comp_type;
  2378. phys->comp_ratio = comp_info->comp_ratio;
  2379. phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
  2380. phys->poms_align_vsync = disp_info->poms_align_vsync;
  2381. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
  2382. phys->dsc_extra_pclk_cycle_cnt =
  2383. comp_info->dsc_info.pclk_per_line;
  2384. phys->dsc_extra_disp_width =
  2385. comp_info->dsc_info.extra_width;
  2386. phys->dce_bytes_per_line =
  2387. comp_info->dsc_info.bytes_per_pkt *
  2388. comp_info->dsc_info.pkt_per_line;
  2389. } else if (phys->comp_type == MSM_DISPLAY_COMPRESSION_VDC) {
  2390. phys->dce_bytes_per_line =
  2391. comp_info->vdc_info.bytes_per_pkt *
  2392. comp_info->vdc_info.pkt_per_line;
  2393. }
  2394. if (phys != sde_enc->cur_master) {
  2395. /**
  2396. * on DMS request, the encoder will be enabled
  2397. * already. Invoke restore to reconfigure the
  2398. * new mode.
  2399. */
  2400. if ((msm_is_mode_seamless_dms(msm_mode) ||
  2401. msm_is_mode_seamless_dyn_clk(msm_mode)) &&
  2402. phys->ops.restore)
  2403. phys->ops.restore(phys);
  2404. else if (phys->ops.enable)
  2405. phys->ops.enable(phys);
  2406. }
  2407. if (sde_enc->misr_enable && phys->ops.setup_misr &&
  2408. (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  2409. phys->ops.setup_misr(phys, true,
  2410. sde_enc->misr_frame_count);
  2411. }
  2412. if ((msm_is_mode_seamless_dms(msm_mode) ||
  2413. msm_is_mode_seamless_dyn_clk(msm_mode)) &&
  2414. sde_enc->cur_master->ops.restore)
  2415. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2416. else if (sde_enc->cur_master->ops.enable)
  2417. sde_enc->cur_master->ops.enable(sde_enc->cur_master);
  2418. }
  2419. static void sde_encoder_off_work(struct kthread_work *work)
  2420. {
  2421. struct sde_encoder_virt *sde_enc = container_of(work,
  2422. struct sde_encoder_virt, delayed_off_work.work);
  2423. struct drm_encoder *drm_enc;
  2424. if (!sde_enc) {
  2425. SDE_ERROR("invalid sde encoder\n");
  2426. return;
  2427. }
  2428. drm_enc = &sde_enc->base;
  2429. SDE_ATRACE_BEGIN("sde_encoder_off_work");
  2430. sde_encoder_idle_request(drm_enc);
  2431. SDE_ATRACE_END("sde_encoder_off_work");
  2432. }
  2433. static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
  2434. {
  2435. struct sde_encoder_virt *sde_enc = NULL;
  2436. int i, ret = 0;
  2437. struct sde_connector_state *c_state;
  2438. struct drm_display_mode *cur_mode = NULL;
  2439. struct msm_display_mode *msm_mode;
  2440. if (!drm_enc || !drm_enc->crtc) {
  2441. SDE_ERROR("invalid encoder\n");
  2442. return;
  2443. }
  2444. sde_enc = to_sde_encoder_virt(drm_enc);
  2445. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2446. SDE_ERROR("power resource is not enabled\n");
  2447. return;
  2448. }
  2449. if (!sde_enc->crtc)
  2450. sde_enc->crtc = drm_enc->crtc;
  2451. cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
  2452. SDE_DEBUG_ENC(sde_enc, "\n");
  2453. SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
  2454. sde_enc->cur_master = NULL;
  2455. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2456. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2457. if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
  2458. SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
  2459. sde_enc->cur_master = phys;
  2460. break;
  2461. }
  2462. }
  2463. if (!sde_enc->cur_master) {
  2464. SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
  2465. return;
  2466. }
  2467. _sde_encoder_input_handler_register(drm_enc);
  2468. c_state = to_sde_connector_state(sde_enc->cur_master->connector->state);
  2469. if (!c_state) {
  2470. SDE_ERROR("invalid connector state\n");
  2471. return;
  2472. }
  2473. msm_mode = &c_state->msm_mode;
  2474. if ((drm_enc->crtc->state->connectors_changed &&
  2475. sde_encoder_in_clone_mode(drm_enc)) ||
  2476. !(msm_is_mode_seamless_vrr(msm_mode)
  2477. || msm_is_mode_seamless_dms(msm_mode)
  2478. || msm_is_mode_seamless_dyn_clk(msm_mode)))
  2479. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  2480. sde_encoder_off_work);
  2481. ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  2482. if (ret) {
  2483. SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
  2484. ret);
  2485. return;
  2486. }
  2487. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2488. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2489. sde_encoder_populate_encoder_phys(drm_enc, sde_enc, msm_mode);
  2490. _sde_encoder_virt_enable_helper(drm_enc);
  2491. }
  2492. void sde_encoder_virt_reset(struct drm_encoder *drm_enc)
  2493. {
  2494. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2495. struct sde_kms *sde_kms = sde_encoder_get_kms(drm_enc);
  2496. int i = 0;
  2497. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2498. if (sde_enc->phys_encs[i]) {
  2499. sde_enc->phys_encs[i]->cont_splash_enabled = false;
  2500. sde_enc->phys_encs[i]->connector = NULL;
  2501. }
  2502. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2503. }
  2504. sde_enc->cur_master = NULL;
  2505. /*
  2506. * clear the cached crtc in sde_enc on use case finish, after all the
  2507. * outstanding events and timers have been completed
  2508. */
  2509. sde_enc->crtc = NULL;
  2510. memset(&sde_enc->mode_info, 0, sizeof(sde_enc->mode_info));
  2511. SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
  2512. sde_rm_release(&sde_kms->rm, drm_enc, false);
  2513. }
  2514. static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
  2515. {
  2516. struct sde_encoder_virt *sde_enc = NULL;
  2517. struct sde_kms *sde_kms;
  2518. enum sde_intf_mode intf_mode;
  2519. int ret, i = 0;
  2520. if (!drm_enc) {
  2521. SDE_ERROR("invalid encoder\n");
  2522. return;
  2523. } else if (!drm_enc->dev) {
  2524. SDE_ERROR("invalid dev\n");
  2525. return;
  2526. } else if (!drm_enc->dev->dev_private) {
  2527. SDE_ERROR("invalid dev_private\n");
  2528. return;
  2529. }
  2530. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2531. SDE_ERROR("power resource is not enabled\n");
  2532. return;
  2533. }
  2534. sde_enc = to_sde_encoder_virt(drm_enc);
  2535. SDE_DEBUG_ENC(sde_enc, "\n");
  2536. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2537. if (!sde_kms)
  2538. return;
  2539. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2540. SDE_EVT32(DRMID(drm_enc));
  2541. /* wait for idle */
  2542. if (!sde_encoder_in_clone_mode(drm_enc))
  2543. sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2544. _sde_encoder_input_handler_unregister(drm_enc);
  2545. /*
  2546. * For primary command mode and video mode encoders, execute the
  2547. * resource control pre-stop operations before the physical encoders
  2548. * are disabled, to allow the rsc to transition its states properly.
  2549. *
  2550. * For other encoder types, rsc should not be enabled until after
  2551. * they have been fully disabled, so delay the pre-stop operations
  2552. * until after the physical disable calls have returned.
  2553. */
  2554. if (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY &&
  2555. (intf_mode == INTF_MODE_CMD || intf_mode == INTF_MODE_VIDEO)) {
  2556. sde_encoder_resource_control(drm_enc,
  2557. SDE_ENC_RC_EVENT_PRE_STOP);
  2558. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2559. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2560. if (phys && phys->ops.disable)
  2561. phys->ops.disable(phys);
  2562. }
  2563. } else {
  2564. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2565. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2566. if (phys && phys->ops.disable)
  2567. phys->ops.disable(phys);
  2568. }
  2569. sde_encoder_resource_control(drm_enc,
  2570. SDE_ENC_RC_EVENT_PRE_STOP);
  2571. }
  2572. /*
  2573. * disable dce after the transfer is complete (for command mode)
  2574. * and after physical encoder is disabled, to make sure timing
  2575. * engine is already disabled (for video mode).
  2576. */
  2577. if (!sde_in_trusted_vm(sde_kms))
  2578. sde_encoder_dce_disable(sde_enc);
  2579. sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
  2580. /* reset connector topology name property */
  2581. if (sde_enc->cur_master && sde_enc->cur_master->connector &&
  2582. sde_enc->crtc->state->active_changed) {
  2583. ret = sde_rm_update_topology(&sde_kms->rm,
  2584. sde_enc->cur_master->connector->state, NULL);
  2585. if (ret) {
  2586. SDE_ERROR_ENC(sde_enc, "RM failed to update topology, rc: %d\n", ret);
  2587. return;
  2588. }
  2589. }
  2590. if (!sde_encoder_in_clone_mode(drm_enc))
  2591. sde_encoder_virt_reset(drm_enc);
  2592. }
  2593. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  2594. struct sde_encoder_phys_wb *wb_enc)
  2595. {
  2596. struct sde_encoder_virt *sde_enc;
  2597. struct sde_hw_ctl *ctl = phys_enc->hw_ctl;
  2598. struct sde_ctl_flush_cfg cfg;
  2599. ctl->ops.reset(ctl);
  2600. sde_encoder_helper_reset_mixers(phys_enc, NULL);
  2601. if (wb_enc) {
  2602. if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
  2603. wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
  2604. false, phys_enc->hw_pp->idx);
  2605. if (ctl->ops.update_bitmask)
  2606. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_WB,
  2607. wb_enc->hw_wb->idx, true);
  2608. }
  2609. } else {
  2610. if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
  2611. phys_enc->hw_intf->ops.bind_pingpong_blk(
  2612. phys_enc->hw_intf, false,
  2613. phys_enc->hw_pp->idx);
  2614. if (ctl->ops.update_bitmask)
  2615. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_INTF,
  2616. phys_enc->hw_intf->idx, true);
  2617. }
  2618. }
  2619. if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
  2620. phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
  2621. if (ctl->ops.update_bitmask && phys_enc->hw_pp->merge_3d)
  2622. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_MERGE_3D,
  2623. phys_enc->hw_pp->merge_3d->idx, true);
  2624. }
  2625. if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&
  2626. phys_enc->hw_pp) {
  2627. phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
  2628. false, phys_enc->hw_pp->idx);
  2629. if (ctl->ops.update_bitmask)
  2630. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_CDM,
  2631. phys_enc->hw_cdm->idx, true);
  2632. }
  2633. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2634. if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&
  2635. ctl->ops.reset_post_disable)
  2636. ctl->ops.reset_post_disable(ctl, &phys_enc->intf_cfg_v1,
  2637. phys_enc->hw_pp->merge_3d ?
  2638. phys_enc->hw_pp->merge_3d->idx : 0);
  2639. sde_crtc_disable_cp_features(sde_enc->base.crtc);
  2640. ctl->ops.get_pending_flush(ctl, &cfg);
  2641. SDE_EVT32(DRMID(phys_enc->parent), cfg.pending_flush_mask);
  2642. ctl->ops.trigger_flush(ctl);
  2643. ctl->ops.trigger_start(ctl);
  2644. ctl->ops.clear_pending_flush(ctl);
  2645. }
  2646. static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
  2647. enum sde_intf_type type, u32 controller_id)
  2648. {
  2649. int i = 0;
  2650. for (i = 0; i < catalog->intf_count; i++) {
  2651. if (catalog->intf[i].type == type
  2652. && catalog->intf[i].controller_id == controller_id) {
  2653. return catalog->intf[i].id;
  2654. }
  2655. }
  2656. return INTF_MAX;
  2657. }
  2658. static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
  2659. enum sde_intf_type type, u32 controller_id)
  2660. {
  2661. if (controller_id < catalog->wb_count)
  2662. return catalog->wb[controller_id].id;
  2663. return WB_MAX;
  2664. }
  2665. void sde_encoder_perf_uidle_status(struct sde_kms *sde_kms,
  2666. struct drm_crtc *crtc)
  2667. {
  2668. struct sde_hw_uidle *uidle;
  2669. struct sde_uidle_cntr cntr;
  2670. struct sde_uidle_status status;
  2671. if (!sde_kms || !crtc || !sde_kms->hw_uidle) {
  2672. pr_err("invalid params %d %d\n",
  2673. !sde_kms, !crtc);
  2674. return;
  2675. }
  2676. /* check if perf counters are enabled and setup */
  2677. if (!sde_kms->catalog->uidle_cfg.perf_cntr_en)
  2678. return;
  2679. uidle = sde_kms->hw_uidle;
  2680. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_STATUS)
  2681. && uidle->ops.uidle_get_status) {
  2682. uidle->ops.uidle_get_status(uidle, &status);
  2683. trace_sde_perf_uidle_status(
  2684. crtc->base.id,
  2685. status.uidle_danger_status_0,
  2686. status.uidle_danger_status_1,
  2687. status.uidle_safe_status_0,
  2688. status.uidle_safe_status_1,
  2689. status.uidle_idle_status_0,
  2690. status.uidle_idle_status_1,
  2691. status.uidle_fal_status_0,
  2692. status.uidle_fal_status_1,
  2693. status.uidle_status,
  2694. status.uidle_en_fal10);
  2695. }
  2696. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_CNT)
  2697. && uidle->ops.uidle_get_cntr) {
  2698. uidle->ops.uidle_get_cntr(uidle, &cntr);
  2699. trace_sde_perf_uidle_cntr(
  2700. crtc->base.id,
  2701. cntr.fal1_gate_cntr,
  2702. cntr.fal10_gate_cntr,
  2703. cntr.fal_wait_gate_cntr,
  2704. cntr.fal1_num_transitions_cntr,
  2705. cntr.fal10_num_transitions_cntr,
  2706. cntr.min_gate_cntr,
  2707. cntr.max_gate_cntr);
  2708. }
  2709. }
  2710. static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
  2711. struct sde_encoder_phys *phy_enc)
  2712. {
  2713. struct sde_encoder_virt *sde_enc = NULL;
  2714. unsigned long lock_flags;
  2715. ktime_t ts = 0;
  2716. if (!drm_enc || !phy_enc)
  2717. return;
  2718. SDE_ATRACE_BEGIN("encoder_vblank_callback");
  2719. sde_enc = to_sde_encoder_virt(drm_enc);
  2720. /*
  2721. * calculate accurate vsync timestamp when available
  2722. * set current time otherwise
  2723. */
  2724. if (phy_enc->sde_kms && phy_enc->sde_kms->catalog->has_precise_vsync_ts)
  2725. ts = sde_encoder_calc_last_vsync_timestamp(drm_enc);
  2726. if (!ts)
  2727. ts = ktime_get();
  2728. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2729. phy_enc->last_vsync_timestamp = ts;
  2730. atomic_inc(&phy_enc->vsync_cnt);
  2731. if (sde_enc->crtc_vblank_cb)
  2732. sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data, ts);
  2733. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2734. if (phy_enc->sde_kms &&
  2735. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2736. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2737. SDE_ATRACE_END("encoder_vblank_callback");
  2738. }
  2739. static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
  2740. struct sde_encoder_phys *phy_enc)
  2741. {
  2742. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2743. if (!phy_enc)
  2744. return;
  2745. SDE_ATRACE_BEGIN("encoder_underrun_callback");
  2746. atomic_inc(&phy_enc->underrun_cnt);
  2747. SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
  2748. if (sde_enc->cur_master &&
  2749. sde_enc->cur_master->ops.get_underrun_line_count)
  2750. sde_enc->cur_master->ops.get_underrun_line_count(
  2751. sde_enc->cur_master);
  2752. trace_sde_encoder_underrun(DRMID(drm_enc),
  2753. atomic_read(&phy_enc->underrun_cnt));
  2754. SDE_DBG_CTRL("stop_ftrace");
  2755. SDE_DBG_CTRL("panic_underrun");
  2756. SDE_ATRACE_END("encoder_underrun_callback");
  2757. }
  2758. void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
  2759. void (*vbl_cb)(void *, ktime_t), void *vbl_data)
  2760. {
  2761. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2762. unsigned long lock_flags;
  2763. bool enable;
  2764. int i;
  2765. enable = vbl_cb ? true : false;
  2766. if (!drm_enc) {
  2767. SDE_ERROR("invalid encoder\n");
  2768. return;
  2769. }
  2770. SDE_DEBUG_ENC(sde_enc, "\n");
  2771. SDE_EVT32(DRMID(drm_enc), enable);
  2772. if (sde_encoder_in_clone_mode(drm_enc)) {
  2773. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  2774. return;
  2775. }
  2776. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2777. sde_enc->crtc_vblank_cb = vbl_cb;
  2778. sde_enc->crtc_vblank_cb_data = vbl_data;
  2779. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2780. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2781. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2782. if (phys && phys->ops.control_vblank_irq)
  2783. phys->ops.control_vblank_irq(phys, enable);
  2784. }
  2785. sde_enc->vblank_enabled = enable;
  2786. }
  2787. void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
  2788. void (*frame_event_cb)(void *, u32 event, ktime_t ts),
  2789. struct drm_crtc *crtc)
  2790. {
  2791. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2792. unsigned long lock_flags;
  2793. bool enable;
  2794. enable = frame_event_cb ? true : false;
  2795. if (!drm_enc) {
  2796. SDE_ERROR("invalid encoder\n");
  2797. return;
  2798. }
  2799. SDE_DEBUG_ENC(sde_enc, "\n");
  2800. SDE_EVT32(DRMID(drm_enc), enable, 0);
  2801. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2802. sde_enc->crtc_frame_event_cb = frame_event_cb;
  2803. sde_enc->crtc_frame_event_cb_data.crtc = crtc;
  2804. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2805. }
  2806. static void sde_encoder_frame_done_callback(
  2807. struct drm_encoder *drm_enc,
  2808. struct sde_encoder_phys *ready_phys, u32 event)
  2809. {
  2810. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2811. struct sde_kms *sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2812. unsigned int i;
  2813. bool trigger = true;
  2814. bool is_cmd_mode = false;
  2815. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2816. ktime_t ts = 0;
  2817. if (!sde_kms || !sde_enc->cur_master) {
  2818. SDE_ERROR("invalid param: sde_kms %pK, cur_master %pK\n",
  2819. sde_kms, sde_enc->cur_master);
  2820. return;
  2821. }
  2822. sde_enc->crtc_frame_event_cb_data.connector =
  2823. sde_enc->cur_master->connector;
  2824. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2825. is_cmd_mode = true;
  2826. /* get precise vsync timestamp for retire fence, if precise vsync timestamp is enabled */
  2827. if (sde_kms->catalog->has_precise_vsync_ts
  2828. && (event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
  2829. && (!(event & (SDE_ENCODER_FRAME_EVENT_ERROR | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD))))
  2830. ts = sde_encoder_calc_last_vsync_timestamp(drm_enc);
  2831. /*
  2832. * get current ktime for other events and when precise timestamp is not
  2833. * available for retire-fence
  2834. */
  2835. if (!ts)
  2836. ts = ktime_get();
  2837. if (event & (SDE_ENCODER_FRAME_EVENT_DONE
  2838. | SDE_ENCODER_FRAME_EVENT_ERROR
  2839. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) && is_cmd_mode) {
  2840. if (ready_phys->connector)
  2841. topology = sde_connector_get_topology_name(
  2842. ready_phys->connector);
  2843. /* One of the physical encoders has become idle */
  2844. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2845. if (sde_enc->phys_encs[i] == ready_phys) {
  2846. SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
  2847. atomic_read(&sde_enc->frame_done_cnt[i]));
  2848. if (!atomic_add_unless(
  2849. &sde_enc->frame_done_cnt[i], 1, 2)) {
  2850. SDE_EVT32(DRMID(drm_enc), event,
  2851. ready_phys->intf_idx,
  2852. SDE_EVTLOG_ERROR);
  2853. SDE_ERROR_ENC(sde_enc,
  2854. "intf idx:%d, event:%d\n",
  2855. ready_phys->intf_idx, event);
  2856. return;
  2857. }
  2858. }
  2859. if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
  2860. atomic_read(&sde_enc->frame_done_cnt[i]) == 0)
  2861. trigger = false;
  2862. }
  2863. if (trigger) {
  2864. if (sde_enc->crtc_frame_event_cb)
  2865. sde_enc->crtc_frame_event_cb(
  2866. &sde_enc->crtc_frame_event_cb_data, event, ts);
  2867. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2868. atomic_add_unless(&sde_enc->frame_done_cnt[i],
  2869. -1, 0);
  2870. }
  2871. } else if (sde_enc->crtc_frame_event_cb) {
  2872. sde_enc->crtc_frame_event_cb(&sde_enc->crtc_frame_event_cb_data, event, ts);
  2873. }
  2874. }
  2875. int sde_encoder_idle_request(struct drm_encoder *drm_enc)
  2876. {
  2877. struct sde_encoder_virt *sde_enc;
  2878. if (!drm_enc) {
  2879. SDE_ERROR("invalid drm encoder\n");
  2880. return -EINVAL;
  2881. }
  2882. sde_enc = to_sde_encoder_virt(drm_enc);
  2883. sde_encoder_resource_control(&sde_enc->base,
  2884. SDE_ENC_RC_EVENT_ENTER_IDLE);
  2885. return 0;
  2886. }
  2887. /**
  2888. * _sde_encoder_trigger_flush - trigger flush for a physical encoder
  2889. * drm_enc: Pointer to drm encoder structure
  2890. * phys: Pointer to physical encoder structure
  2891. * extra_flush: Additional bit mask to include in flush trigger
  2892. * config_changed: if true new config is applied, avoid increment of retire
  2893. * count if false
  2894. */
  2895. static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
  2896. struct sde_encoder_phys *phys,
  2897. struct sde_ctl_flush_cfg *extra_flush,
  2898. bool config_changed)
  2899. {
  2900. struct sde_hw_ctl *ctl;
  2901. unsigned long lock_flags;
  2902. struct sde_encoder_virt *sde_enc;
  2903. int pend_ret_fence_cnt;
  2904. struct sde_connector *c_conn;
  2905. if (!drm_enc || !phys) {
  2906. SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
  2907. !drm_enc, !phys);
  2908. return;
  2909. }
  2910. sde_enc = to_sde_encoder_virt(drm_enc);
  2911. c_conn = to_sde_connector(phys->connector);
  2912. if (!phys->hw_pp) {
  2913. SDE_ERROR("invalid pingpong hw\n");
  2914. return;
  2915. }
  2916. ctl = phys->hw_ctl;
  2917. if (!ctl || !phys->ops.trigger_flush) {
  2918. SDE_ERROR("missing ctl/trigger cb\n");
  2919. return;
  2920. }
  2921. if (phys->split_role == ENC_ROLE_SKIP) {
  2922. SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
  2923. "skip flush pp%d ctl%d\n",
  2924. phys->hw_pp->idx - PINGPONG_0,
  2925. ctl->idx - CTL_0);
  2926. return;
  2927. }
  2928. /* update pending counts and trigger kickoff ctl flush atomically */
  2929. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2930. if (phys->ops.is_master && phys->ops.is_master(phys) && config_changed)
  2931. atomic_inc(&phys->pending_retire_fence_cnt);
  2932. pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
  2933. if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
  2934. ctl->ops.update_bitmask) {
  2935. /* perform peripheral flush on every frame update for dp dsc */
  2936. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  2937. phys->comp_ratio && c_conn->ops.update_pps) {
  2938. c_conn->ops.update_pps(phys->connector, NULL,
  2939. c_conn->display);
  2940. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2941. phys->hw_intf->idx, 1);
  2942. }
  2943. if (sde_enc->dynamic_hdr_updated)
  2944. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2945. phys->hw_intf->idx, 1);
  2946. }
  2947. if ((extra_flush && extra_flush->pending_flush_mask)
  2948. && ctl->ops.update_pending_flush)
  2949. ctl->ops.update_pending_flush(ctl, extra_flush);
  2950. phys->ops.trigger_flush(phys);
  2951. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2952. if (ctl->ops.get_pending_flush) {
  2953. struct sde_ctl_flush_cfg pending_flush = {0,};
  2954. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2955. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2956. ctl->idx - CTL_0,
  2957. pending_flush.pending_flush_mask,
  2958. pend_ret_fence_cnt);
  2959. } else {
  2960. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2961. ctl->idx - CTL_0,
  2962. pend_ret_fence_cnt);
  2963. }
  2964. }
  2965. /**
  2966. * _sde_encoder_trigger_start - trigger start for a physical encoder
  2967. * phys: Pointer to physical encoder structure
  2968. */
  2969. static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
  2970. {
  2971. struct sde_hw_ctl *ctl;
  2972. struct sde_encoder_virt *sde_enc;
  2973. if (!phys) {
  2974. SDE_ERROR("invalid argument(s)\n");
  2975. return;
  2976. }
  2977. if (!phys->hw_pp) {
  2978. SDE_ERROR("invalid pingpong hw\n");
  2979. return;
  2980. }
  2981. if (!phys->parent) {
  2982. SDE_ERROR("invalid parent\n");
  2983. return;
  2984. }
  2985. /* avoid ctrl start for encoder in clone mode */
  2986. if (phys->in_clone_mode)
  2987. return;
  2988. ctl = phys->hw_ctl;
  2989. sde_enc = to_sde_encoder_virt(phys->parent);
  2990. if (phys->split_role == ENC_ROLE_SKIP) {
  2991. SDE_DEBUG_ENC(sde_enc,
  2992. "skip start pp%d ctl%d\n",
  2993. phys->hw_pp->idx - PINGPONG_0,
  2994. ctl->idx - CTL_0);
  2995. return;
  2996. }
  2997. if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
  2998. phys->ops.trigger_start(phys);
  2999. }
  3000. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc)
  3001. {
  3002. struct sde_hw_ctl *ctl;
  3003. if (!phys_enc) {
  3004. SDE_ERROR("invalid encoder\n");
  3005. return;
  3006. }
  3007. ctl = phys_enc->hw_ctl;
  3008. if (ctl && ctl->ops.trigger_flush)
  3009. ctl->ops.trigger_flush(ctl);
  3010. }
  3011. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
  3012. {
  3013. struct sde_hw_ctl *ctl;
  3014. if (!phys_enc) {
  3015. SDE_ERROR("invalid encoder\n");
  3016. return;
  3017. }
  3018. ctl = phys_enc->hw_ctl;
  3019. if (ctl && ctl->ops.trigger_start) {
  3020. ctl->ops.trigger_start(ctl);
  3021. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
  3022. }
  3023. }
  3024. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc)
  3025. {
  3026. struct sde_encoder_virt *sde_enc;
  3027. struct sde_connector *sde_con;
  3028. void *sde_con_disp;
  3029. struct sde_hw_ctl *ctl;
  3030. int rc;
  3031. if (!phys_enc) {
  3032. SDE_ERROR("invalid encoder\n");
  3033. return;
  3034. }
  3035. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  3036. ctl = phys_enc->hw_ctl;
  3037. if (!ctl || !ctl->ops.reset)
  3038. return;
  3039. SDE_DEBUG_ENC(sde_enc, "ctl %d reset\n", ctl->idx);
  3040. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx);
  3041. if (phys_enc->ops.is_master && phys_enc->ops.is_master(phys_enc) &&
  3042. phys_enc->connector) {
  3043. sde_con = to_sde_connector(phys_enc->connector);
  3044. sde_con_disp = sde_connector_get_display(phys_enc->connector);
  3045. if (sde_con->ops.soft_reset) {
  3046. rc = sde_con->ops.soft_reset(sde_con_disp);
  3047. if (rc) {
  3048. SDE_ERROR_ENC(sde_enc,
  3049. "connector soft reset failure\n");
  3050. SDE_DBG_DUMP(SDE_DBG_BUILT_IN_ALL, "panic");
  3051. }
  3052. }
  3053. }
  3054. phys_enc->enable_state = SDE_ENC_ENABLED;
  3055. }
  3056. /**
  3057. * _sde_encoder_kickoff_phys - handle physical encoder kickoff
  3058. * Iterate through the physical encoders and perform consolidated flush
  3059. * and/or control start triggering as needed. This is done in the virtual
  3060. * encoder rather than the individual physical ones in order to handle
  3061. * use cases that require visibility into multiple physical encoders at
  3062. * a time.
  3063. * sde_enc: Pointer to virtual encoder structure
  3064. * config_changed: if true new config is applied. Avoid regdma_flush and
  3065. * incrementing the retire count if false.
  3066. */
  3067. static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc,
  3068. bool config_changed)
  3069. {
  3070. struct sde_hw_ctl *ctl;
  3071. uint32_t i;
  3072. struct sde_ctl_flush_cfg pending_flush = {0,};
  3073. u32 pending_kickoff_cnt;
  3074. struct msm_drm_private *priv = NULL;
  3075. struct sde_kms *sde_kms = NULL;
  3076. struct sde_crtc_misr_info crtc_misr_info = {false, 0};
  3077. bool is_regdma_blocking = false, is_vid_mode = false;
  3078. struct sde_crtc *sde_crtc;
  3079. if (!sde_enc) {
  3080. SDE_ERROR("invalid encoder\n");
  3081. return;
  3082. }
  3083. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3084. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  3085. is_vid_mode = true;
  3086. is_regdma_blocking = (is_vid_mode ||
  3087. _sde_encoder_is_autorefresh_enabled(sde_enc));
  3088. /* don't perform flush/start operations for slave encoders */
  3089. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3090. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3091. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  3092. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  3093. continue;
  3094. ctl = phys->hw_ctl;
  3095. if (!ctl)
  3096. continue;
  3097. if (phys->connector)
  3098. topology = sde_connector_get_topology_name(
  3099. phys->connector);
  3100. if (!phys->ops.needs_single_flush ||
  3101. !phys->ops.needs_single_flush(phys)) {
  3102. if (config_changed && ctl->ops.reg_dma_flush)
  3103. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  3104. _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0,
  3105. config_changed);
  3106. } else if (ctl->ops.get_pending_flush) {
  3107. ctl->ops.get_pending_flush(ctl, &pending_flush);
  3108. }
  3109. }
  3110. /* for split flush, combine pending flush masks and send to master */
  3111. if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
  3112. ctl = sde_enc->cur_master->hw_ctl;
  3113. if (config_changed && ctl->ops.reg_dma_flush)
  3114. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  3115. _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
  3116. &pending_flush,
  3117. config_changed);
  3118. }
  3119. /* update pending_kickoff_cnt AFTER flush but before trigger start */
  3120. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3121. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3122. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  3123. continue;
  3124. if (!phys->ops.needs_single_flush ||
  3125. !phys->ops.needs_single_flush(phys)) {
  3126. pending_kickoff_cnt =
  3127. sde_encoder_phys_inc_pending(phys);
  3128. SDE_EVT32(pending_kickoff_cnt, SDE_EVTLOG_FUNC_CASE1);
  3129. } else {
  3130. pending_kickoff_cnt =
  3131. sde_encoder_phys_inc_pending(phys);
  3132. SDE_EVT32(pending_kickoff_cnt,
  3133. pending_flush.pending_flush_mask,
  3134. SDE_EVTLOG_FUNC_CASE2);
  3135. }
  3136. }
  3137. if (sde_enc->misr_enable)
  3138. sde_encoder_misr_configure(&sde_enc->base, true,
  3139. sde_enc->misr_frame_count);
  3140. sde_crtc_get_misr_info(sde_enc->crtc, &crtc_misr_info);
  3141. if (crtc_misr_info.misr_enable && sde_crtc &&
  3142. sde_crtc->misr_reconfigure) {
  3143. sde_crtc_misr_setup(sde_enc->crtc, true,
  3144. crtc_misr_info.misr_frame_count);
  3145. sde_crtc->misr_reconfigure = false;
  3146. }
  3147. _sde_encoder_trigger_start(sde_enc->cur_master);
  3148. if (sde_enc->elevated_ahb_vote) {
  3149. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3150. priv = sde_enc->base.dev->dev_private;
  3151. if (sde_kms != NULL) {
  3152. sde_power_scale_reg_bus(&priv->phandle,
  3153. VOTE_INDEX_LOW,
  3154. false);
  3155. }
  3156. sde_enc->elevated_ahb_vote = false;
  3157. }
  3158. }
  3159. static void _sde_encoder_ppsplit_swap_intf_for_right_only_update(
  3160. struct drm_encoder *drm_enc,
  3161. unsigned long *affected_displays,
  3162. int num_active_phys)
  3163. {
  3164. struct sde_encoder_virt *sde_enc;
  3165. struct sde_encoder_phys *master;
  3166. enum sde_rm_topology_name topology;
  3167. bool is_right_only;
  3168. if (!drm_enc || !affected_displays)
  3169. return;
  3170. sde_enc = to_sde_encoder_virt(drm_enc);
  3171. master = sde_enc->cur_master;
  3172. if (!master || !master->connector)
  3173. return;
  3174. topology = sde_connector_get_topology_name(master->connector);
  3175. if (topology != SDE_RM_TOPOLOGY_PPSPLIT)
  3176. return;
  3177. /*
  3178. * For pingpong split, the slave pingpong won't generate IRQs. For
  3179. * right-only updates, we can't swap pingpongs, or simply swap the
  3180. * master/slave assignment, we actually have to swap the interfaces
  3181. * so that the master physical encoder will use a pingpong/interface
  3182. * that generates irqs on which to wait.
  3183. */
  3184. is_right_only = !test_bit(0, affected_displays) &&
  3185. test_bit(1, affected_displays);
  3186. if (is_right_only && !sde_enc->intfs_swapped) {
  3187. /* right-only update swap interfaces */
  3188. swap(sde_enc->phys_encs[0]->intf_idx,
  3189. sde_enc->phys_encs[1]->intf_idx);
  3190. sde_enc->intfs_swapped = true;
  3191. } else if (!is_right_only && sde_enc->intfs_swapped) {
  3192. /* left-only or full update, swap back */
  3193. swap(sde_enc->phys_encs[0]->intf_idx,
  3194. sde_enc->phys_encs[1]->intf_idx);
  3195. sde_enc->intfs_swapped = false;
  3196. }
  3197. SDE_DEBUG_ENC(sde_enc,
  3198. "right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
  3199. is_right_only, sde_enc->intfs_swapped,
  3200. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  3201. sde_enc->phys_encs[1]->intf_idx - INTF_0);
  3202. SDE_EVT32(DRMID(drm_enc), is_right_only, sde_enc->intfs_swapped,
  3203. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  3204. sde_enc->phys_encs[1]->intf_idx - INTF_0,
  3205. *affected_displays);
  3206. /* ppsplit always uses master since ppslave invalid for irqs*/
  3207. if (num_active_phys == 1)
  3208. *affected_displays = BIT(0);
  3209. }
  3210. static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
  3211. struct sde_encoder_kickoff_params *params)
  3212. {
  3213. struct sde_encoder_virt *sde_enc;
  3214. struct sde_encoder_phys *phys;
  3215. int i, num_active_phys;
  3216. bool master_assigned = false;
  3217. if (!drm_enc || !params)
  3218. return;
  3219. sde_enc = to_sde_encoder_virt(drm_enc);
  3220. if (sde_enc->num_phys_encs <= 1)
  3221. return;
  3222. /* count bits set */
  3223. num_active_phys = hweight_long(params->affected_displays);
  3224. SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
  3225. params->affected_displays, num_active_phys);
  3226. SDE_EVT32_VERBOSE(DRMID(drm_enc), params->affected_displays,
  3227. num_active_phys);
  3228. /* for left/right only update, ppsplit master switches interface */
  3229. _sde_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
  3230. &params->affected_displays, num_active_phys);
  3231. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3232. enum sde_enc_split_role prv_role, new_role;
  3233. bool active = false;
  3234. phys = sde_enc->phys_encs[i];
  3235. if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
  3236. continue;
  3237. active = test_bit(i, &params->affected_displays);
  3238. prv_role = phys->split_role;
  3239. if (active && num_active_phys == 1)
  3240. new_role = ENC_ROLE_SOLO;
  3241. else if (active && !master_assigned)
  3242. new_role = ENC_ROLE_MASTER;
  3243. else if (active)
  3244. new_role = ENC_ROLE_SLAVE;
  3245. else
  3246. new_role = ENC_ROLE_SKIP;
  3247. phys->ops.update_split_role(phys, new_role);
  3248. if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
  3249. sde_enc->cur_master = phys;
  3250. master_assigned = true;
  3251. }
  3252. SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
  3253. phys->hw_pp->idx - PINGPONG_0, prv_role,
  3254. phys->split_role, active);
  3255. SDE_EVT32(DRMID(drm_enc), params->affected_displays,
  3256. phys->hw_pp->idx - PINGPONG_0, prv_role,
  3257. phys->split_role, active, num_active_phys);
  3258. }
  3259. }
  3260. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode)
  3261. {
  3262. struct sde_encoder_virt *sde_enc;
  3263. struct msm_display_info *disp_info;
  3264. if (!drm_enc) {
  3265. SDE_ERROR("invalid encoder\n");
  3266. return false;
  3267. }
  3268. sde_enc = to_sde_encoder_virt(drm_enc);
  3269. disp_info = &sde_enc->disp_info;
  3270. return (disp_info->curr_panel_mode == mode);
  3271. }
  3272. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
  3273. {
  3274. struct sde_encoder_virt *sde_enc;
  3275. struct sde_encoder_phys *phys;
  3276. unsigned int i;
  3277. struct sde_hw_ctl *ctl;
  3278. if (!drm_enc) {
  3279. SDE_ERROR("invalid encoder\n");
  3280. return;
  3281. }
  3282. sde_enc = to_sde_encoder_virt(drm_enc);
  3283. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3284. phys = sde_enc->phys_encs[i];
  3285. if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
  3286. sde_encoder_check_curr_mode(drm_enc,
  3287. MSM_DISPLAY_CMD_MODE)) {
  3288. ctl = phys->hw_ctl;
  3289. if (ctl->ops.trigger_pending)
  3290. /* update only for command mode primary ctl */
  3291. ctl->ops.trigger_pending(ctl);
  3292. }
  3293. }
  3294. sde_enc->idle_pc_restore = false;
  3295. }
  3296. static void sde_encoder_esd_trigger_work_handler(struct kthread_work *work)
  3297. {
  3298. struct sde_encoder_virt *sde_enc = container_of(work,
  3299. struct sde_encoder_virt, esd_trigger_work);
  3300. if (!sde_enc) {
  3301. SDE_ERROR("invalid sde encoder\n");
  3302. return;
  3303. }
  3304. sde_encoder_resource_control(&sde_enc->base,
  3305. SDE_ENC_RC_EVENT_KICKOFF);
  3306. }
  3307. static void sde_encoder_input_event_work_handler(struct kthread_work *work)
  3308. {
  3309. struct sde_encoder_virt *sde_enc = container_of(work,
  3310. struct sde_encoder_virt, input_event_work);
  3311. if (!sde_enc) {
  3312. SDE_ERROR("invalid sde encoder\n");
  3313. return;
  3314. }
  3315. sde_encoder_resource_control(&sde_enc->base,
  3316. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3317. }
  3318. static void sde_encoder_early_wakeup_work_handler(struct kthread_work *work)
  3319. {
  3320. struct sde_encoder_virt *sde_enc = container_of(work,
  3321. struct sde_encoder_virt, early_wakeup_work);
  3322. if (!sde_enc) {
  3323. SDE_ERROR("invalid sde encoder\n");
  3324. return;
  3325. }
  3326. SDE_ATRACE_BEGIN("encoder_early_wakeup");
  3327. sde_encoder_resource_control(&sde_enc->base,
  3328. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3329. SDE_ATRACE_END("encoder_early_wakeup");
  3330. }
  3331. void sde_encoder_early_wakeup(struct drm_encoder *drm_enc)
  3332. {
  3333. struct sde_encoder_virt *sde_enc = NULL;
  3334. struct msm_drm_thread *disp_thread = NULL;
  3335. struct msm_drm_private *priv = NULL;
  3336. priv = drm_enc->dev->dev_private;
  3337. sde_enc = to_sde_encoder_virt(drm_enc);
  3338. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE)) {
  3339. SDE_DEBUG_ENC(sde_enc,
  3340. "should only early wake up command mode display\n");
  3341. return;
  3342. }
  3343. if (!sde_enc->crtc || (sde_enc->crtc->index
  3344. >= ARRAY_SIZE(priv->event_thread))) {
  3345. SDE_DEBUG_ENC(sde_enc, "invalid CRTC: %d or crtc index: %d\n",
  3346. sde_enc->crtc == NULL,
  3347. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  3348. return;
  3349. }
  3350. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  3351. SDE_ATRACE_BEGIN("queue_early_wakeup_work");
  3352. kthread_queue_work(&disp_thread->worker,
  3353. &sde_enc->early_wakeup_work);
  3354. SDE_ATRACE_END("queue_early_wakeup_work");
  3355. }
  3356. int sde_encoder_poll_line_counts(struct drm_encoder *drm_enc)
  3357. {
  3358. static const uint64_t timeout_us = 50000;
  3359. static const uint64_t sleep_us = 20;
  3360. struct sde_encoder_virt *sde_enc;
  3361. ktime_t cur_ktime, exp_ktime;
  3362. uint32_t line_count, tmp, i;
  3363. if (!drm_enc) {
  3364. SDE_ERROR("invalid encoder\n");
  3365. return -EINVAL;
  3366. }
  3367. sde_enc = to_sde_encoder_virt(drm_enc);
  3368. if (!sde_enc->cur_master ||
  3369. !sde_enc->cur_master->ops.get_line_count) {
  3370. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3371. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  3372. return -EINVAL;
  3373. }
  3374. exp_ktime = ktime_add_ms(ktime_get(), timeout_us / 1000);
  3375. line_count = sde_enc->cur_master->ops.get_line_count(
  3376. sde_enc->cur_master);
  3377. for (i = 0; i < (timeout_us * 2 / sleep_us); ++i) {
  3378. tmp = line_count;
  3379. line_count = sde_enc->cur_master->ops.get_line_count(
  3380. sde_enc->cur_master);
  3381. if (line_count < tmp) {
  3382. SDE_EVT32(DRMID(drm_enc), line_count);
  3383. return 0;
  3384. }
  3385. cur_ktime = ktime_get();
  3386. if (ktime_compare_safe(exp_ktime, cur_ktime) <= 0)
  3387. break;
  3388. usleep_range(sleep_us / 2, sleep_us);
  3389. }
  3390. SDE_EVT32(DRMID(drm_enc), line_count, SDE_EVTLOG_ERROR);
  3391. return -ETIMEDOUT;
  3392. }
  3393. static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
  3394. {
  3395. struct drm_encoder *drm_enc;
  3396. struct sde_rm_hw_iter rm_iter;
  3397. bool lm_valid = false;
  3398. bool intf_valid = false;
  3399. if (!phys_enc || !phys_enc->parent) {
  3400. SDE_ERROR("invalid encoder\n");
  3401. return -EINVAL;
  3402. }
  3403. drm_enc = phys_enc->parent;
  3404. /* Flush the interfaces for AVR update or Qsync with INTF TE */
  3405. if (phys_enc->intf_mode == INTF_MODE_VIDEO ||
  3406. (phys_enc->intf_mode == INTF_MODE_CMD &&
  3407. phys_enc->has_intf_te)) {
  3408. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id,
  3409. SDE_HW_BLK_INTF);
  3410. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3411. struct sde_hw_intf *hw_intf =
  3412. (struct sde_hw_intf *)rm_iter.hw;
  3413. if (!hw_intf)
  3414. continue;
  3415. if (phys_enc->hw_ctl->ops.update_bitmask)
  3416. phys_enc->hw_ctl->ops.update_bitmask(
  3417. phys_enc->hw_ctl,
  3418. SDE_HW_FLUSH_INTF,
  3419. hw_intf->idx, 1);
  3420. intf_valid = true;
  3421. }
  3422. if (!intf_valid) {
  3423. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3424. "intf not found to flush\n");
  3425. return -EFAULT;
  3426. }
  3427. } else {
  3428. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3429. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3430. struct sde_hw_mixer *hw_lm =
  3431. (struct sde_hw_mixer *)rm_iter.hw;
  3432. if (!hw_lm)
  3433. continue;
  3434. /* update LM flush for HW without INTF TE */
  3435. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3436. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3437. phys_enc->hw_ctl,
  3438. hw_lm->idx, 1);
  3439. lm_valid = true;
  3440. }
  3441. if (!lm_valid) {
  3442. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3443. "lm not found to flush\n");
  3444. return -EFAULT;
  3445. }
  3446. }
  3447. return 0;
  3448. }
  3449. static void _sde_encoder_helper_hdr_plus_mempool_update(
  3450. struct sde_encoder_virt *sde_enc)
  3451. {
  3452. struct sde_connector_dyn_hdr_metadata *dhdr_meta = NULL;
  3453. struct sde_hw_mdp *mdptop = NULL;
  3454. sde_enc->dynamic_hdr_updated = false;
  3455. if (sde_enc->cur_master) {
  3456. mdptop = sde_enc->cur_master->hw_mdptop;
  3457. dhdr_meta = sde_connector_get_dyn_hdr_meta(
  3458. sde_enc->cur_master->connector);
  3459. }
  3460. if (!mdptop || !dhdr_meta || !dhdr_meta->dynamic_hdr_update)
  3461. return;
  3462. if (mdptop->ops.set_hdr_plus_metadata) {
  3463. sde_enc->dynamic_hdr_updated = true;
  3464. mdptop->ops.set_hdr_plus_metadata(
  3465. mdptop, dhdr_meta->dynamic_hdr_payload,
  3466. dhdr_meta->dynamic_hdr_payload_size,
  3467. sde_enc->cur_master->intf_idx == INTF_0 ?
  3468. 0 : 1);
  3469. }
  3470. }
  3471. void sde_encoder_needs_hw_reset(struct drm_encoder *drm_enc)
  3472. {
  3473. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  3474. struct sde_encoder_phys *phys;
  3475. int i;
  3476. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3477. phys = sde_enc->phys_encs[i];
  3478. if (phys && phys->ops.hw_reset)
  3479. phys->ops.hw_reset(phys);
  3480. }
  3481. }
  3482. int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
  3483. struct sde_encoder_kickoff_params *params)
  3484. {
  3485. struct sde_encoder_virt *sde_enc;
  3486. struct sde_encoder_phys *phys;
  3487. struct sde_kms *sde_kms = NULL;
  3488. struct sde_crtc *sde_crtc;
  3489. bool needs_hw_reset = false, is_cmd_mode;
  3490. int i, rc, ret = 0;
  3491. struct msm_display_info *disp_info;
  3492. if (!drm_enc || !params || !drm_enc->dev ||
  3493. !drm_enc->dev->dev_private) {
  3494. SDE_ERROR("invalid args\n");
  3495. return -EINVAL;
  3496. }
  3497. sde_enc = to_sde_encoder_virt(drm_enc);
  3498. sde_kms = sde_encoder_get_kms(drm_enc);
  3499. if (!sde_kms)
  3500. return -EINVAL;
  3501. disp_info = &sde_enc->disp_info;
  3502. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3503. SDE_DEBUG_ENC(sde_enc, "\n");
  3504. SDE_EVT32(DRMID(drm_enc));
  3505. is_cmd_mode = sde_encoder_check_curr_mode(drm_enc,
  3506. MSM_DISPLAY_CMD_MODE);
  3507. if (sde_enc->cur_master && sde_enc->cur_master->connector
  3508. && is_cmd_mode)
  3509. sde_enc->frame_trigger_mode = sde_connector_get_property(
  3510. sde_enc->cur_master->connector->state,
  3511. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE);
  3512. _sde_encoder_helper_hdr_plus_mempool_update(sde_enc);
  3513. /* prepare for next kickoff, may include waiting on previous kickoff */
  3514. SDE_ATRACE_BEGIN("sde_encoder_prepare_for_kickoff");
  3515. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3516. phys = sde_enc->phys_encs[i];
  3517. params->frame_trigger_mode = sde_enc->frame_trigger_mode;
  3518. params->recovery_events_enabled =
  3519. sde_enc->recovery_events_enabled;
  3520. if (phys) {
  3521. if (phys->ops.prepare_for_kickoff) {
  3522. rc = phys->ops.prepare_for_kickoff(
  3523. phys, params);
  3524. if (rc)
  3525. ret = rc;
  3526. }
  3527. if (phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3528. needs_hw_reset = true;
  3529. _sde_encoder_setup_dither(phys);
  3530. if (sde_enc->cur_master &&
  3531. sde_connector_is_qsync_updated(
  3532. sde_enc->cur_master->connector))
  3533. _helper_flush_qsync(phys);
  3534. }
  3535. }
  3536. if (is_cmd_mode && sde_enc->cur_master &&
  3537. (sde_connector_is_qsync_updated(sde_enc->cur_master->connector) ||
  3538. _sde_encoder_is_autorefresh_enabled(sde_enc)))
  3539. _sde_encoder_update_rsc_client(drm_enc, true);
  3540. rc = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  3541. if (rc) {
  3542. SDE_ERROR_ENC(sde_enc, "resource kickoff failed rc %d\n", rc);
  3543. ret = rc;
  3544. goto end;
  3545. }
  3546. /* if any phys needs reset, reset all phys, in-order */
  3547. if (needs_hw_reset)
  3548. sde_encoder_needs_hw_reset(drm_enc);
  3549. _sde_encoder_update_master(drm_enc, params);
  3550. _sde_encoder_update_roi(drm_enc);
  3551. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3552. rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
  3553. if (rc) {
  3554. SDE_ERROR_ENC(sde_enc, "kickoff conn%d failed rc %d\n",
  3555. sde_enc->cur_master->connector->base.id,
  3556. rc);
  3557. ret = rc;
  3558. }
  3559. }
  3560. if (sde_enc->cur_master &&
  3561. ((is_cmd_mode && sde_enc->cur_master->cont_splash_enabled) ||
  3562. !sde_enc->cur_master->cont_splash_enabled)) {
  3563. rc = sde_encoder_dce_setup(sde_enc, params);
  3564. if (rc) {
  3565. SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
  3566. ret = rc;
  3567. }
  3568. }
  3569. sde_encoder_dce_flush(sde_enc);
  3570. if (sde_enc->cur_master && !sde_enc->cur_master->cont_splash_enabled)
  3571. sde_configure_qdss(sde_enc, sde_enc->cur_master->hw_qdss,
  3572. sde_enc->cur_master, sde_kms->qdss_enabled);
  3573. end:
  3574. SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");
  3575. return ret;
  3576. }
  3577. /**
  3578. * _sde_encoder_reset_ctl_hw - reset h/w configuration for all ctl's associated
  3579. * with the specified encoder, and unstage all pipes from it
  3580. * @encoder: encoder pointer
  3581. * Returns: 0 on success
  3582. */
  3583. static int _sde_encoder_reset_ctl_hw(struct drm_encoder *drm_enc)
  3584. {
  3585. struct sde_encoder_virt *sde_enc;
  3586. struct sde_encoder_phys *phys;
  3587. unsigned int i;
  3588. int rc = 0;
  3589. if (!drm_enc) {
  3590. SDE_ERROR("invalid encoder\n");
  3591. return -EINVAL;
  3592. }
  3593. sde_enc = to_sde_encoder_virt(drm_enc);
  3594. SDE_ATRACE_BEGIN("encoder_release_lm");
  3595. SDE_DEBUG_ENC(sde_enc, "\n");
  3596. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3597. phys = sde_enc->phys_encs[i];
  3598. if (!phys)
  3599. continue;
  3600. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0);
  3601. rc = sde_encoder_helper_reset_mixers(phys, NULL);
  3602. if (rc)
  3603. SDE_EVT32(DRMID(drm_enc), rc, SDE_EVTLOG_ERROR);
  3604. }
  3605. SDE_ATRACE_END("encoder_release_lm");
  3606. return rc;
  3607. }
  3608. void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error,
  3609. bool config_changed)
  3610. {
  3611. struct sde_encoder_virt *sde_enc;
  3612. struct sde_encoder_phys *phys;
  3613. unsigned int i;
  3614. if (!drm_enc) {
  3615. SDE_ERROR("invalid encoder\n");
  3616. return;
  3617. }
  3618. SDE_ATRACE_BEGIN("encoder_kickoff");
  3619. sde_enc = to_sde_encoder_virt(drm_enc);
  3620. SDE_DEBUG_ENC(sde_enc, "\n");
  3621. /* create a 'no pipes' commit to release buffers on errors */
  3622. if (is_error)
  3623. _sde_encoder_reset_ctl_hw(drm_enc);
  3624. if (sde_enc->delay_kickoff) {
  3625. u32 loop_count = 20;
  3626. u32 sleep = DELAY_KICKOFF_POLL_TIMEOUT_US / loop_count;
  3627. for (i = 0; i < loop_count; i++) {
  3628. usleep_range(sleep, sleep * 2);
  3629. if (!sde_enc->delay_kickoff)
  3630. break;
  3631. }
  3632. SDE_EVT32(DRMID(drm_enc), i, SDE_EVTLOG_FUNC_CASE1);
  3633. }
  3634. /* All phys encs are ready to go, trigger the kickoff */
  3635. _sde_encoder_kickoff_phys(sde_enc, config_changed);
  3636. /* allow phys encs to handle any post-kickoff business */
  3637. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3638. phys = sde_enc->phys_encs[i];
  3639. if (phys && phys->ops.handle_post_kickoff)
  3640. phys->ops.handle_post_kickoff(phys);
  3641. }
  3642. if (sde_enc->autorefresh_solver_disable &&
  3643. !_sde_encoder_is_autorefresh_enabled(sde_enc))
  3644. _sde_encoder_update_rsc_client(drm_enc, true);
  3645. SDE_ATRACE_END("encoder_kickoff");
  3646. }
  3647. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  3648. struct sde_hw_pp_vsync_info *info)
  3649. {
  3650. struct sde_encoder_virt *sde_enc;
  3651. struct sde_encoder_phys *phys;
  3652. int i, ret;
  3653. if (!drm_enc || !info)
  3654. return;
  3655. sde_enc = to_sde_encoder_virt(drm_enc);
  3656. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3657. phys = sde_enc->phys_encs[i];
  3658. if (phys && phys->hw_intf && phys->hw_pp
  3659. && phys->hw_intf->ops.get_vsync_info) {
  3660. ret = phys->hw_intf->ops.get_vsync_info(
  3661. phys->hw_intf, &info[i]);
  3662. if (!ret) {
  3663. info[i].pp_idx = phys->hw_pp->idx - PINGPONG_0;
  3664. info[i].intf_idx = phys->hw_intf->idx - INTF_0;
  3665. }
  3666. }
  3667. }
  3668. }
  3669. void sde_encoder_get_transfer_time(struct drm_encoder *drm_enc,
  3670. u32 *transfer_time_us)
  3671. {
  3672. struct sde_encoder_virt *sde_enc;
  3673. struct msm_mode_info *info;
  3674. if (!drm_enc || !transfer_time_us) {
  3675. SDE_ERROR("bad arg: encoder:%d transfer_time:%d\n", !drm_enc,
  3676. !transfer_time_us);
  3677. return;
  3678. }
  3679. sde_enc = to_sde_encoder_virt(drm_enc);
  3680. info = &sde_enc->mode_info;
  3681. *transfer_time_us = info->mdp_transfer_time_us;
  3682. }
  3683. int sde_encoder_get_avr_status(struct drm_encoder *drm_enc)
  3684. {
  3685. struct sde_encoder_virt *sde_enc;
  3686. struct sde_encoder_phys *master;
  3687. bool is_vid_mode;
  3688. if (!drm_enc)
  3689. return -EINVAL;
  3690. sde_enc = to_sde_encoder_virt(drm_enc);
  3691. master = sde_enc->cur_master;
  3692. is_vid_mode = sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CAP_VID_MODE);
  3693. if (!master || !is_vid_mode || !sde_connector_get_qsync_mode(master->connector))
  3694. return -ENODATA;
  3695. if (!master->hw_intf->ops.get_avr_status)
  3696. return -EOPNOTSUPP;
  3697. return master->hw_intf->ops.get_avr_status(master->hw_intf);
  3698. }
  3699. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  3700. struct drm_framebuffer *fb)
  3701. {
  3702. struct drm_encoder *drm_enc;
  3703. struct sde_hw_mixer_cfg mixer;
  3704. struct sde_rm_hw_iter lm_iter;
  3705. bool lm_valid = false;
  3706. if (!phys_enc || !phys_enc->parent) {
  3707. SDE_ERROR("invalid encoder\n");
  3708. return -EINVAL;
  3709. }
  3710. drm_enc = phys_enc->parent;
  3711. memset(&mixer, 0, sizeof(mixer));
  3712. /* reset associated CTL/LMs */
  3713. if (phys_enc->hw_ctl->ops.clear_all_blendstages)
  3714. phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
  3715. sde_rm_init_hw_iter(&lm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3716. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &lm_iter)) {
  3717. struct sde_hw_mixer *hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  3718. if (!hw_lm)
  3719. continue;
  3720. /* need to flush LM to remove it */
  3721. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3722. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3723. phys_enc->hw_ctl,
  3724. hw_lm->idx, 1);
  3725. if (fb) {
  3726. /* assume a single LM if targeting a frame buffer */
  3727. if (lm_valid)
  3728. continue;
  3729. mixer.out_height = fb->height;
  3730. mixer.out_width = fb->width;
  3731. if (hw_lm->ops.setup_mixer_out)
  3732. hw_lm->ops.setup_mixer_out(hw_lm, &mixer);
  3733. }
  3734. lm_valid = true;
  3735. /* only enable border color on LM */
  3736. if (phys_enc->hw_ctl->ops.setup_blendstage)
  3737. phys_enc->hw_ctl->ops.setup_blendstage(
  3738. phys_enc->hw_ctl, hw_lm->idx, NULL, false);
  3739. }
  3740. if (!lm_valid) {
  3741. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc), "lm not found\n");
  3742. return -EFAULT;
  3743. }
  3744. return 0;
  3745. }
  3746. int sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
  3747. {
  3748. struct sde_encoder_virt *sde_enc;
  3749. struct sde_encoder_phys *phys;
  3750. int i, rc = 0, ret = 0;
  3751. struct sde_hw_ctl *ctl;
  3752. if (!drm_enc) {
  3753. SDE_ERROR("invalid encoder\n");
  3754. return -EINVAL;
  3755. }
  3756. sde_enc = to_sde_encoder_virt(drm_enc);
  3757. /* update the qsync parameters for the current frame */
  3758. if (sde_enc->cur_master)
  3759. sde_connector_set_qsync_params(
  3760. sde_enc->cur_master->connector);
  3761. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3762. phys = sde_enc->phys_encs[i];
  3763. if (phys && phys->ops.prepare_commit)
  3764. phys->ops.prepare_commit(phys);
  3765. if (phys && phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3766. ret = -ETIMEDOUT;
  3767. if (phys && phys->hw_ctl) {
  3768. ctl = phys->hw_ctl;
  3769. /*
  3770. * avoid clearing the pending flush during the first
  3771. * frame update after idle power collpase as the
  3772. * restore path would have updated the pending flush
  3773. */
  3774. if (!sde_enc->idle_pc_restore &&
  3775. ctl->ops.clear_pending_flush)
  3776. ctl->ops.clear_pending_flush(ctl);
  3777. }
  3778. }
  3779. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3780. rc = sde_connector_prepare_commit(
  3781. sde_enc->cur_master->connector);
  3782. if (rc)
  3783. SDE_ERROR_ENC(sde_enc,
  3784. "prepare commit failed conn %d rc %d\n",
  3785. sde_enc->cur_master->connector->base.id,
  3786. rc);
  3787. }
  3788. return ret;
  3789. }
  3790. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  3791. bool enable, u32 frame_count)
  3792. {
  3793. if (!phys_enc)
  3794. return;
  3795. if (phys_enc->hw_intf && phys_enc->hw_intf->ops.setup_misr)
  3796. phys_enc->hw_intf->ops.setup_misr(phys_enc->hw_intf,
  3797. enable, frame_count);
  3798. }
  3799. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  3800. bool nonblock, u32 *misr_value)
  3801. {
  3802. if (!phys_enc)
  3803. return -EINVAL;
  3804. return phys_enc->hw_intf && phys_enc->hw_intf->ops.collect_misr ?
  3805. phys_enc->hw_intf->ops.collect_misr(phys_enc->hw_intf,
  3806. nonblock, misr_value) : -ENOTSUPP;
  3807. }
  3808. #ifdef CONFIG_DEBUG_FS
  3809. static int _sde_encoder_status_show(struct seq_file *s, void *data)
  3810. {
  3811. struct sde_encoder_virt *sde_enc;
  3812. int i;
  3813. if (!s || !s->private)
  3814. return -EINVAL;
  3815. sde_enc = s->private;
  3816. mutex_lock(&sde_enc->enc_lock);
  3817. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3818. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3819. if (!phys)
  3820. continue;
  3821. seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
  3822. phys->intf_idx - INTF_0,
  3823. atomic_read(&phys->vsync_cnt),
  3824. atomic_read(&phys->underrun_cnt));
  3825. switch (phys->intf_mode) {
  3826. case INTF_MODE_VIDEO:
  3827. seq_puts(s, "mode: video\n");
  3828. break;
  3829. case INTF_MODE_CMD:
  3830. seq_puts(s, "mode: command\n");
  3831. break;
  3832. case INTF_MODE_WB_BLOCK:
  3833. seq_puts(s, "mode: wb block\n");
  3834. break;
  3835. case INTF_MODE_WB_LINE:
  3836. seq_puts(s, "mode: wb line\n");
  3837. break;
  3838. default:
  3839. seq_puts(s, "mode: ???\n");
  3840. break;
  3841. }
  3842. }
  3843. mutex_unlock(&sde_enc->enc_lock);
  3844. return 0;
  3845. }
  3846. static int _sde_encoder_debugfs_status_open(struct inode *inode,
  3847. struct file *file)
  3848. {
  3849. return single_open(file, _sde_encoder_status_show, inode->i_private);
  3850. }
  3851. static ssize_t _sde_encoder_misr_setup(struct file *file,
  3852. const char __user *user_buf, size_t count, loff_t *ppos)
  3853. {
  3854. struct sde_encoder_virt *sde_enc;
  3855. char buf[MISR_BUFF_SIZE + 1];
  3856. size_t buff_copy;
  3857. u32 frame_count, enable;
  3858. struct sde_kms *sde_kms = NULL;
  3859. struct drm_encoder *drm_enc;
  3860. if (!file || !file->private_data)
  3861. return -EINVAL;
  3862. sde_enc = file->private_data;
  3863. if (!sde_enc)
  3864. return -EINVAL;
  3865. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3866. if (!sde_kms)
  3867. return -EINVAL;
  3868. drm_enc = &sde_enc->base;
  3869. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3870. SDE_DEBUG_ENC(sde_enc, "misr enable/disable not allowed\n");
  3871. return -ENOTSUPP;
  3872. }
  3873. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  3874. if (copy_from_user(buf, user_buf, buff_copy))
  3875. return -EINVAL;
  3876. buf[buff_copy] = 0; /* end of string */
  3877. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  3878. return -EINVAL;
  3879. sde_enc->misr_enable = enable;
  3880. sde_enc->misr_reconfigure = true;
  3881. sde_enc->misr_frame_count = frame_count;
  3882. return count;
  3883. }
  3884. static ssize_t _sde_encoder_misr_read(struct file *file,
  3885. char __user *user_buff, size_t count, loff_t *ppos)
  3886. {
  3887. struct sde_encoder_virt *sde_enc;
  3888. struct sde_kms *sde_kms = NULL;
  3889. struct drm_encoder *drm_enc;
  3890. struct sde_vm_ops *vm_ops;
  3891. int i = 0, len = 0;
  3892. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  3893. int rc;
  3894. if (*ppos)
  3895. return 0;
  3896. if (!file || !file->private_data)
  3897. return -EINVAL;
  3898. sde_enc = file->private_data;
  3899. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3900. if (!sde_kms)
  3901. return -EINVAL;
  3902. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3903. SDE_DEBUG_ENC(sde_enc, "misr read not allowed\n");
  3904. return -ENOTSUPP;
  3905. }
  3906. drm_enc = &sde_enc->base;
  3907. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3908. if (rc < 0)
  3909. return rc;
  3910. vm_ops = sde_vm_get_ops(sde_kms);
  3911. sde_vm_lock(sde_kms);
  3912. if (vm_ops && vm_ops->vm_owns_hw && !vm_ops->vm_owns_hw(sde_kms)) {
  3913. SDE_DEBUG("op not supported due to HW unavailablity\n");
  3914. rc = -EOPNOTSUPP;
  3915. goto end;
  3916. }
  3917. if (!sde_enc->misr_enable) {
  3918. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3919. "disabled\n");
  3920. goto buff_check;
  3921. }
  3922. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3923. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3924. u32 misr_value = 0;
  3925. if (!phys || !phys->ops.collect_misr) {
  3926. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3927. "invalid\n");
  3928. SDE_ERROR_ENC(sde_enc, "invalid misr ops\n");
  3929. continue;
  3930. }
  3931. rc = phys->ops.collect_misr(phys, false, &misr_value);
  3932. if (rc) {
  3933. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3934. "invalid\n");
  3935. SDE_ERROR_ENC(sde_enc, "failed to collect misr %d\n",
  3936. rc);
  3937. continue;
  3938. } else {
  3939. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3940. "Intf idx:%d\n",
  3941. phys->intf_idx - INTF_0);
  3942. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3943. "0x%x\n", misr_value);
  3944. }
  3945. }
  3946. buff_check:
  3947. if (count <= len) {
  3948. len = 0;
  3949. goto end;
  3950. }
  3951. if (copy_to_user(user_buff, buf, len)) {
  3952. len = -EFAULT;
  3953. goto end;
  3954. }
  3955. *ppos += len; /* increase offset */
  3956. end:
  3957. sde_vm_unlock(sde_kms);
  3958. pm_runtime_put_sync(drm_enc->dev->dev);
  3959. return len;
  3960. }
  3961. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3962. {
  3963. struct sde_encoder_virt *sde_enc;
  3964. struct sde_kms *sde_kms;
  3965. int i;
  3966. static const struct file_operations debugfs_status_fops = {
  3967. .open = _sde_encoder_debugfs_status_open,
  3968. .read = seq_read,
  3969. .llseek = seq_lseek,
  3970. .release = single_release,
  3971. };
  3972. static const struct file_operations debugfs_misr_fops = {
  3973. .open = simple_open,
  3974. .read = _sde_encoder_misr_read,
  3975. .write = _sde_encoder_misr_setup,
  3976. };
  3977. char name[SDE_NAME_SIZE];
  3978. if (!drm_enc) {
  3979. SDE_ERROR("invalid encoder\n");
  3980. return -EINVAL;
  3981. }
  3982. sde_enc = to_sde_encoder_virt(drm_enc);
  3983. sde_kms = sde_encoder_get_kms(drm_enc);
  3984. if (!sde_kms) {
  3985. SDE_ERROR("invalid sde_kms\n");
  3986. return -EINVAL;
  3987. }
  3988. snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
  3989. /* create overall sub-directory for the encoder */
  3990. sde_enc->debugfs_root = debugfs_create_dir(name,
  3991. drm_enc->dev->primary->debugfs_root);
  3992. if (!sde_enc->debugfs_root)
  3993. return -ENOMEM;
  3994. /* don't error check these */
  3995. debugfs_create_file("status", 0400,
  3996. sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
  3997. debugfs_create_file("misr_data", 0600,
  3998. sde_enc->debugfs_root, sde_enc, &debugfs_misr_fops);
  3999. debugfs_create_bool("idle_power_collapse", 0600, sde_enc->debugfs_root,
  4000. &sde_enc->idle_pc_enabled);
  4001. debugfs_create_u32("frame_trigger_mode", 0400, sde_enc->debugfs_root,
  4002. &sde_enc->frame_trigger_mode);
  4003. for (i = 0; i < sde_enc->num_phys_encs; i++)
  4004. if (sde_enc->phys_encs[i] &&
  4005. sde_enc->phys_encs[i]->ops.late_register)
  4006. sde_enc->phys_encs[i]->ops.late_register(
  4007. sde_enc->phys_encs[i],
  4008. sde_enc->debugfs_root);
  4009. return 0;
  4010. }
  4011. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  4012. {
  4013. struct sde_encoder_virt *sde_enc;
  4014. if (!drm_enc)
  4015. return;
  4016. sde_enc = to_sde_encoder_virt(drm_enc);
  4017. debugfs_remove_recursive(sde_enc->debugfs_root);
  4018. }
  4019. #else
  4020. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  4021. {
  4022. return 0;
  4023. }
  4024. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  4025. {
  4026. }
  4027. #endif
  4028. static int sde_encoder_late_register(struct drm_encoder *encoder)
  4029. {
  4030. return _sde_encoder_init_debugfs(encoder);
  4031. }
  4032. static void sde_encoder_early_unregister(struct drm_encoder *encoder)
  4033. {
  4034. _sde_encoder_destroy_debugfs(encoder);
  4035. }
  4036. static int sde_encoder_virt_add_phys_encs(
  4037. struct msm_display_info *disp_info,
  4038. struct sde_encoder_virt *sde_enc,
  4039. struct sde_enc_phys_init_params *params)
  4040. {
  4041. struct sde_encoder_phys *enc = NULL;
  4042. u32 display_caps = disp_info->capabilities;
  4043. SDE_DEBUG_ENC(sde_enc, "\n");
  4044. /*
  4045. * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
  4046. * in this function, check up-front.
  4047. */
  4048. if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
  4049. ARRAY_SIZE(sde_enc->phys_encs)) {
  4050. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  4051. sde_enc->num_phys_encs);
  4052. return -EINVAL;
  4053. }
  4054. if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
  4055. enc = sde_encoder_phys_vid_init(params);
  4056. if (IS_ERR_OR_NULL(enc)) {
  4057. SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
  4058. PTR_ERR(enc));
  4059. return !enc ? -EINVAL : PTR_ERR(enc);
  4060. }
  4061. sde_enc->phys_vid_encs[sde_enc->num_phys_encs] = enc;
  4062. }
  4063. if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
  4064. enc = sde_encoder_phys_cmd_init(params);
  4065. if (IS_ERR_OR_NULL(enc)) {
  4066. SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
  4067. PTR_ERR(enc));
  4068. return !enc ? -EINVAL : PTR_ERR(enc);
  4069. }
  4070. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs] = enc;
  4071. }
  4072. if (disp_info->curr_panel_mode == MSM_DISPLAY_VIDEO_MODE)
  4073. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  4074. sde_enc->phys_vid_encs[sde_enc->num_phys_encs];
  4075. else
  4076. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  4077. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs];
  4078. ++sde_enc->num_phys_encs;
  4079. return 0;
  4080. }
  4081. static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
  4082. struct sde_enc_phys_init_params *params)
  4083. {
  4084. struct sde_encoder_phys *enc = NULL;
  4085. if (!sde_enc) {
  4086. SDE_ERROR("invalid encoder\n");
  4087. return -EINVAL;
  4088. }
  4089. SDE_DEBUG_ENC(sde_enc, "\n");
  4090. if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
  4091. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  4092. sde_enc->num_phys_encs);
  4093. return -EINVAL;
  4094. }
  4095. enc = sde_encoder_phys_wb_init(params);
  4096. if (IS_ERR_OR_NULL(enc)) {
  4097. SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
  4098. PTR_ERR(enc));
  4099. return !enc ? -EINVAL : PTR_ERR(enc);
  4100. }
  4101. sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
  4102. ++sde_enc->num_phys_encs;
  4103. return 0;
  4104. }
  4105. static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
  4106. struct sde_kms *sde_kms,
  4107. struct msm_display_info *disp_info,
  4108. int *drm_enc_mode)
  4109. {
  4110. int ret = 0;
  4111. int i = 0;
  4112. enum sde_intf_type intf_type;
  4113. struct sde_encoder_virt_ops parent_ops = {
  4114. sde_encoder_vblank_callback,
  4115. sde_encoder_underrun_callback,
  4116. sde_encoder_frame_done_callback,
  4117. _sde_encoder_get_qsync_fps_callback,
  4118. };
  4119. struct sde_enc_phys_init_params phys_params;
  4120. if (!sde_enc || !sde_kms) {
  4121. SDE_ERROR("invalid arg(s), enc %d kms %d\n",
  4122. !sde_enc, !sde_kms);
  4123. return -EINVAL;
  4124. }
  4125. memset(&phys_params, 0, sizeof(phys_params));
  4126. phys_params.sde_kms = sde_kms;
  4127. phys_params.parent = &sde_enc->base;
  4128. phys_params.parent_ops = parent_ops;
  4129. phys_params.enc_spinlock = &sde_enc->enc_spinlock;
  4130. phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
  4131. SDE_DEBUG("\n");
  4132. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
  4133. *drm_enc_mode = DRM_MODE_ENCODER_DSI;
  4134. intf_type = INTF_DSI;
  4135. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
  4136. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  4137. intf_type = INTF_HDMI;
  4138. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
  4139. if (disp_info->capabilities & MSM_DISPLAY_CAP_MST_MODE)
  4140. *drm_enc_mode = DRM_MODE_ENCODER_DPMST;
  4141. else
  4142. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  4143. intf_type = INTF_DP;
  4144. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
  4145. *drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
  4146. intf_type = INTF_WB;
  4147. } else {
  4148. SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
  4149. return -EINVAL;
  4150. }
  4151. WARN_ON(disp_info->num_of_h_tiles < 1);
  4152. sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
  4153. sde_enc->te_source = disp_info->te_source;
  4154. SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
  4155. if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
  4156. (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
  4157. sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
  4158. sde_enc->input_event_enabled = sde_kms->catalog->wakeup_with_touch;
  4159. mutex_lock(&sde_enc->enc_lock);
  4160. for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
  4161. /*
  4162. * Left-most tile is at index 0, content is controller id
  4163. * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
  4164. * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
  4165. */
  4166. u32 controller_id = disp_info->h_tile_instance[i];
  4167. if (disp_info->num_of_h_tiles > 1) {
  4168. if (i == 0)
  4169. phys_params.split_role = ENC_ROLE_MASTER;
  4170. else
  4171. phys_params.split_role = ENC_ROLE_SLAVE;
  4172. } else {
  4173. phys_params.split_role = ENC_ROLE_SOLO;
  4174. }
  4175. SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
  4176. i, controller_id, phys_params.split_role);
  4177. if (intf_type == INTF_WB) {
  4178. phys_params.intf_idx = INTF_MAX;
  4179. phys_params.wb_idx = sde_encoder_get_wb(
  4180. sde_kms->catalog,
  4181. intf_type, controller_id);
  4182. if (phys_params.wb_idx == WB_MAX) {
  4183. SDE_ERROR_ENC(sde_enc,
  4184. "could not get wb: type %d, id %d\n",
  4185. intf_type, controller_id);
  4186. ret = -EINVAL;
  4187. }
  4188. } else {
  4189. phys_params.wb_idx = WB_MAX;
  4190. phys_params.intf_idx = sde_encoder_get_intf(
  4191. sde_kms->catalog, intf_type,
  4192. controller_id);
  4193. if (phys_params.intf_idx == INTF_MAX) {
  4194. SDE_ERROR_ENC(sde_enc,
  4195. "could not get wb: type %d, id %d\n",
  4196. intf_type, controller_id);
  4197. ret = -EINVAL;
  4198. }
  4199. }
  4200. if (!ret) {
  4201. if (intf_type == INTF_WB)
  4202. ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
  4203. &phys_params);
  4204. else
  4205. ret = sde_encoder_virt_add_phys_encs(
  4206. disp_info,
  4207. sde_enc,
  4208. &phys_params);
  4209. if (ret)
  4210. SDE_ERROR_ENC(sde_enc,
  4211. "failed to add phys encs\n");
  4212. }
  4213. }
  4214. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4215. struct sde_encoder_phys *vid_phys = sde_enc->phys_vid_encs[i];
  4216. struct sde_encoder_phys *cmd_phys = sde_enc->phys_cmd_encs[i];
  4217. if (vid_phys) {
  4218. atomic_set(&vid_phys->vsync_cnt, 0);
  4219. atomic_set(&vid_phys->underrun_cnt, 0);
  4220. }
  4221. if (cmd_phys) {
  4222. atomic_set(&cmd_phys->vsync_cnt, 0);
  4223. atomic_set(&cmd_phys->underrun_cnt, 0);
  4224. }
  4225. }
  4226. mutex_unlock(&sde_enc->enc_lock);
  4227. return ret;
  4228. }
  4229. static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
  4230. .mode_set = sde_encoder_virt_mode_set,
  4231. .disable = sde_encoder_virt_disable,
  4232. .enable = sde_encoder_virt_enable,
  4233. .atomic_check = sde_encoder_virt_atomic_check,
  4234. };
  4235. static const struct drm_encoder_funcs sde_encoder_funcs = {
  4236. .destroy = sde_encoder_destroy,
  4237. .late_register = sde_encoder_late_register,
  4238. .early_unregister = sde_encoder_early_unregister,
  4239. };
  4240. struct drm_encoder *sde_encoder_init(struct drm_device *dev, struct msm_display_info *disp_info)
  4241. {
  4242. struct msm_drm_private *priv = dev->dev_private;
  4243. struct sde_kms *sde_kms = to_sde_kms(priv->kms);
  4244. struct drm_encoder *drm_enc = NULL;
  4245. struct sde_encoder_virt *sde_enc = NULL;
  4246. int drm_enc_mode = DRM_MODE_ENCODER_NONE;
  4247. char name[SDE_NAME_SIZE];
  4248. int ret = 0, i, intf_index = INTF_MAX;
  4249. struct sde_encoder_phys *phys = NULL;
  4250. sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
  4251. if (!sde_enc) {
  4252. ret = -ENOMEM;
  4253. goto fail;
  4254. }
  4255. mutex_init(&sde_enc->enc_lock);
  4256. ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
  4257. &drm_enc_mode);
  4258. if (ret)
  4259. goto fail;
  4260. sde_enc->cur_master = NULL;
  4261. spin_lock_init(&sde_enc->enc_spinlock);
  4262. mutex_init(&sde_enc->vblank_ctl_lock);
  4263. for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  4264. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  4265. drm_enc = &sde_enc->base;
  4266. drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode, NULL);
  4267. drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
  4268. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4269. phys = sde_enc->phys_encs[i];
  4270. if (!phys)
  4271. continue;
  4272. if (phys->ops.is_master && phys->ops.is_master(phys))
  4273. intf_index = phys->intf_idx - INTF_0;
  4274. }
  4275. snprintf(name, SDE_NAME_SIZE, "rsc_enc%u", drm_enc->base.id);
  4276. sde_enc->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX, name,
  4277. (disp_info->display_type == SDE_CONNECTOR_PRIMARY) ?
  4278. SDE_RSC_PRIMARY_DISP_CLIENT :
  4279. SDE_RSC_EXTERNAL_DISP_CLIENT, intf_index + 1);
  4280. if (IS_ERR_OR_NULL(sde_enc->rsc_client)) {
  4281. SDE_DEBUG("sde rsc client create failed :%ld\n",
  4282. PTR_ERR(sde_enc->rsc_client));
  4283. sde_enc->rsc_client = NULL;
  4284. }
  4285. if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE &&
  4286. sde_enc->input_event_enabled) {
  4287. ret = _sde_encoder_input_handler(sde_enc);
  4288. if (ret)
  4289. SDE_ERROR(
  4290. "input handler registration failed, rc = %d\n", ret);
  4291. }
  4292. mutex_init(&sde_enc->rc_lock);
  4293. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  4294. sde_encoder_off_work);
  4295. sde_enc->vblank_enabled = false;
  4296. sde_enc->qdss_status = false;
  4297. kthread_init_work(&sde_enc->input_event_work,
  4298. sde_encoder_input_event_work_handler);
  4299. kthread_init_work(&sde_enc->early_wakeup_work,
  4300. sde_encoder_early_wakeup_work_handler);
  4301. kthread_init_work(&sde_enc->esd_trigger_work,
  4302. sde_encoder_esd_trigger_work_handler);
  4303. memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
  4304. SDE_DEBUG_ENC(sde_enc, "created\n");
  4305. return drm_enc;
  4306. fail:
  4307. SDE_ERROR("failed to create encoder\n");
  4308. if (drm_enc)
  4309. sde_encoder_destroy(drm_enc);
  4310. return ERR_PTR(ret);
  4311. }
  4312. int sde_encoder_wait_for_event(struct drm_encoder *drm_enc,
  4313. enum msm_event_wait event)
  4314. {
  4315. int (*fn_wait)(struct sde_encoder_phys *phys_enc) = NULL;
  4316. struct sde_encoder_virt *sde_enc = NULL;
  4317. int i, ret = 0;
  4318. char atrace_buf[32];
  4319. if (!drm_enc) {
  4320. SDE_ERROR("invalid encoder\n");
  4321. return -EINVAL;
  4322. }
  4323. sde_enc = to_sde_encoder_virt(drm_enc);
  4324. SDE_DEBUG_ENC(sde_enc, "\n");
  4325. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4326. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4327. switch (event) {
  4328. case MSM_ENC_COMMIT_DONE:
  4329. fn_wait = phys->ops.wait_for_commit_done;
  4330. break;
  4331. case MSM_ENC_TX_COMPLETE:
  4332. fn_wait = phys->ops.wait_for_tx_complete;
  4333. break;
  4334. case MSM_ENC_VBLANK:
  4335. fn_wait = phys->ops.wait_for_vblank;
  4336. break;
  4337. case MSM_ENC_ACTIVE_REGION:
  4338. fn_wait = phys->ops.wait_for_active;
  4339. break;
  4340. default:
  4341. SDE_ERROR_ENC(sde_enc, "unknown wait event %d\n",
  4342. event);
  4343. return -EINVAL;
  4344. }
  4345. if (phys && fn_wait) {
  4346. snprintf(atrace_buf, sizeof(atrace_buf),
  4347. "wait_completion_event_%d", event);
  4348. SDE_ATRACE_BEGIN(atrace_buf);
  4349. ret = fn_wait(phys);
  4350. SDE_ATRACE_END(atrace_buf);
  4351. if (ret)
  4352. return ret;
  4353. }
  4354. }
  4355. return ret;
  4356. }
  4357. void sde_encoder_helper_get_jitter_bounds_ns(struct drm_encoder *drm_enc,
  4358. u64 *l_bound, u64 *u_bound)
  4359. {
  4360. struct sde_encoder_virt *sde_enc;
  4361. u64 jitter_ns, frametime_ns;
  4362. struct msm_mode_info *info;
  4363. if (!drm_enc) {
  4364. SDE_ERROR("invalid encoder\n");
  4365. return;
  4366. }
  4367. sde_enc = to_sde_encoder_virt(drm_enc);
  4368. info = &sde_enc->mode_info;
  4369. frametime_ns = (1 * 1000000000) / info->frame_rate;
  4370. jitter_ns = info->jitter_numer * frametime_ns;
  4371. do_div(jitter_ns, info->jitter_denom * 100);
  4372. *l_bound = frametime_ns - jitter_ns;
  4373. *u_bound = frametime_ns + jitter_ns;
  4374. }
  4375. u32 sde_encoder_get_fps(struct drm_encoder *drm_enc)
  4376. {
  4377. struct sde_encoder_virt *sde_enc;
  4378. if (!drm_enc) {
  4379. SDE_ERROR("invalid encoder\n");
  4380. return 0;
  4381. }
  4382. sde_enc = to_sde_encoder_virt(drm_enc);
  4383. return sde_enc->mode_info.frame_rate;
  4384. }
  4385. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
  4386. {
  4387. struct sde_encoder_virt *sde_enc = NULL;
  4388. int i;
  4389. if (!encoder) {
  4390. SDE_ERROR("invalid encoder\n");
  4391. return INTF_MODE_NONE;
  4392. }
  4393. sde_enc = to_sde_encoder_virt(encoder);
  4394. if (sde_enc->cur_master)
  4395. return sde_enc->cur_master->intf_mode;
  4396. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4397. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4398. if (phys)
  4399. return phys->intf_mode;
  4400. }
  4401. return INTF_MODE_NONE;
  4402. }
  4403. u32 sde_encoder_get_frame_count(struct drm_encoder *encoder)
  4404. {
  4405. struct sde_encoder_virt *sde_enc = NULL;
  4406. struct sde_encoder_phys *phys;
  4407. if (!encoder) {
  4408. SDE_ERROR("invalid encoder\n");
  4409. return 0;
  4410. }
  4411. sde_enc = to_sde_encoder_virt(encoder);
  4412. phys = sde_enc->cur_master;
  4413. return phys ? atomic_read(&phys->vsync_cnt) : 0;
  4414. }
  4415. bool sde_encoder_get_vblank_timestamp(struct drm_encoder *encoder,
  4416. ktime_t *tvblank)
  4417. {
  4418. struct sde_encoder_virt *sde_enc = NULL;
  4419. struct sde_encoder_phys *phys;
  4420. if (!encoder) {
  4421. SDE_ERROR("invalid encoder\n");
  4422. return false;
  4423. }
  4424. sde_enc = to_sde_encoder_virt(encoder);
  4425. phys = sde_enc->cur_master;
  4426. if (!phys)
  4427. return false;
  4428. *tvblank = phys->last_vsync_timestamp;
  4429. return *tvblank ? true : false;
  4430. }
  4431. static void _sde_encoder_cache_hw_res_cont_splash(
  4432. struct drm_encoder *encoder,
  4433. struct sde_kms *sde_kms)
  4434. {
  4435. int i, idx;
  4436. struct sde_encoder_virt *sde_enc;
  4437. struct sde_encoder_phys *phys_enc;
  4438. struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;
  4439. sde_enc = to_sde_encoder_virt(encoder);
  4440. sde_rm_init_hw_iter(&pp_iter, encoder->base.id, SDE_HW_BLK_PINGPONG);
  4441. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4442. sde_enc->hw_pp[i] = NULL;
  4443. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  4444. break;
  4445. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  4446. }
  4447. sde_rm_init_hw_iter(&dsc_iter, encoder->base.id, SDE_HW_BLK_DSC);
  4448. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4449. sde_enc->hw_dsc[i] = NULL;
  4450. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  4451. break;
  4452. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  4453. }
  4454. /*
  4455. * If we have multiple phys encoders with one controller, make
  4456. * sure to populate the controller pointer in both phys encoders.
  4457. */
  4458. for (idx = 0; idx < sde_enc->num_phys_encs; idx++) {
  4459. phys_enc = sde_enc->phys_encs[idx];
  4460. phys_enc->hw_ctl = NULL;
  4461. sde_rm_init_hw_iter(&ctl_iter, encoder->base.id,
  4462. SDE_HW_BLK_CTL);
  4463. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4464. if (sde_rm_get_hw(&sde_kms->rm, &ctl_iter)) {
  4465. phys_enc->hw_ctl =
  4466. (struct sde_hw_ctl *) ctl_iter.hw;
  4467. pr_debug("HW CTL intf_idx:%d hw_ctl:[0x%pK]\n",
  4468. phys_enc->intf_idx, phys_enc->hw_ctl);
  4469. }
  4470. }
  4471. }
  4472. sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);
  4473. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4474. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4475. phys->hw_intf = NULL;
  4476. if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))
  4477. break;
  4478. phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;
  4479. }
  4480. }
  4481. /**
  4482. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  4483. * device bootup when cont_splash is enabled
  4484. * @drm_enc: Pointer to drm encoder structure
  4485. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  4486. * @enable: boolean indicates enable or displae state of splash
  4487. * @Return: true if successful in updating the encoder structure
  4488. */
  4489. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  4490. struct sde_splash_display *splash_display, bool enable)
  4491. {
  4492. struct sde_encoder_virt *sde_enc;
  4493. struct msm_drm_private *priv;
  4494. struct sde_kms *sde_kms;
  4495. struct drm_connector *conn = NULL;
  4496. struct sde_connector *sde_conn = NULL;
  4497. struct sde_connector_state *sde_conn_state = NULL;
  4498. struct drm_display_mode *drm_mode = NULL;
  4499. struct sde_encoder_phys *phys_enc;
  4500. struct drm_bridge *bridge;
  4501. int ret = 0, i;
  4502. if (!encoder) {
  4503. SDE_ERROR("invalid drm enc\n");
  4504. return -EINVAL;
  4505. }
  4506. sde_enc = to_sde_encoder_virt(encoder);
  4507. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  4508. if (!sde_kms) {
  4509. SDE_ERROR("invalid sde_kms\n");
  4510. return -EINVAL;
  4511. }
  4512. priv = encoder->dev->dev_private;
  4513. if (!priv->num_connectors) {
  4514. SDE_ERROR_ENC(sde_enc, "No connectors registered\n");
  4515. return -EINVAL;
  4516. }
  4517. SDE_DEBUG_ENC(sde_enc,
  4518. "num of connectors: %d\n", priv->num_connectors);
  4519. SDE_DEBUG_ENC(sde_enc, "enable: %d\n", enable);
  4520. if (!enable) {
  4521. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4522. phys_enc = sde_enc->phys_encs[i];
  4523. if (phys_enc)
  4524. phys_enc->cont_splash_enabled = false;
  4525. }
  4526. return ret;
  4527. }
  4528. if (!splash_display) {
  4529. SDE_ERROR_ENC(sde_enc, "invalid splash data\n");
  4530. return -EINVAL;
  4531. }
  4532. for (i = 0; i < priv->num_connectors; i++) {
  4533. SDE_DEBUG_ENC(sde_enc, "connector id: %d\n",
  4534. priv->connectors[i]->base.id);
  4535. sde_conn = to_sde_connector(priv->connectors[i]);
  4536. if (!sde_conn->encoder) {
  4537. SDE_DEBUG_ENC(sde_enc,
  4538. "encoder not attached to connector\n");
  4539. continue;
  4540. }
  4541. if (sde_conn->encoder->base.id
  4542. == encoder->base.id) {
  4543. conn = (priv->connectors[i]);
  4544. break;
  4545. }
  4546. }
  4547. if (!conn || !conn->state) {
  4548. SDE_ERROR_ENC(sde_enc, "connector not found\n");
  4549. return -EINVAL;
  4550. }
  4551. sde_conn_state = to_sde_connector_state(conn->state);
  4552. if (!sde_conn->ops.get_mode_info) {
  4553. SDE_ERROR_ENC(sde_enc, "conn: get_mode_info ops not found\n");
  4554. return -EINVAL;
  4555. }
  4556. drm_mode = &encoder->crtc->state->adjusted_mode;
  4557. ret = sde_connector_get_mode_info(&sde_conn->base,
  4558. drm_mode, &sde_conn_state->mode_info);
  4559. if (ret) {
  4560. SDE_ERROR_ENC(sde_enc,
  4561. "conn: ->get_mode_info failed. ret=%d\n", ret);
  4562. return ret;
  4563. }
  4564. if (sde_conn->encoder) {
  4565. conn->state->best_encoder = sde_conn->encoder;
  4566. SDE_DEBUG_ENC(sde_enc,
  4567. "configured cstate->best_encoder to ID = %d\n",
  4568. conn->state->best_encoder->base.id);
  4569. } else {
  4570. SDE_ERROR_ENC(sde_enc, "No encoder mapped to connector=%d\n",
  4571. conn->base.id);
  4572. }
  4573. ret = sde_rm_reserve(&sde_kms->rm, encoder, encoder->crtc->state,
  4574. conn->state, false);
  4575. if (ret) {
  4576. SDE_ERROR_ENC(sde_enc,
  4577. "failed to reserve hw resources, %d\n", ret);
  4578. return ret;
  4579. }
  4580. SDE_DEBUG_ENC(sde_enc, "connector topology = %llu\n",
  4581. sde_connector_get_topology_name(conn));
  4582. SDE_DEBUG_ENC(sde_enc, "hdisplay = %d, vdisplay = %d\n",
  4583. drm_mode->hdisplay, drm_mode->vdisplay);
  4584. drm_set_preferred_mode(conn, drm_mode->hdisplay, drm_mode->vdisplay);
  4585. bridge = drm_bridge_chain_get_first_bridge(encoder);
  4586. if (bridge) {
  4587. SDE_DEBUG_ENC(sde_enc, "Bridge mapped to encoder\n");
  4588. /*
  4589. * For cont-splash use case, we update the mode
  4590. * configurations manually. This will skip the
  4591. * usually mode set call when actual frame is
  4592. * pushed from framework. The bridge needs to
  4593. * be updated with the current drm mode by
  4594. * calling the bridge mode set ops.
  4595. */
  4596. drm_bridge_chain_mode_set(bridge, drm_mode, drm_mode);
  4597. } else {
  4598. SDE_ERROR_ENC(sde_enc, "No bridge attached to encoder\n");
  4599. }
  4600. _sde_encoder_cache_hw_res_cont_splash(encoder, sde_kms);
  4601. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4602. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4603. if (!phys) {
  4604. SDE_ERROR_ENC(sde_enc,
  4605. "phys encoders not initialized\n");
  4606. return -EINVAL;
  4607. }
  4608. /* update connector for master and slave phys encoders */
  4609. phys->connector = conn;
  4610. phys->cont_splash_enabled = true;
  4611. phys->hw_pp = sde_enc->hw_pp[i];
  4612. if (phys->ops.cont_splash_mode_set)
  4613. phys->ops.cont_splash_mode_set(phys, drm_mode);
  4614. if (phys->ops.is_master && phys->ops.is_master(phys))
  4615. sde_enc->cur_master = phys;
  4616. }
  4617. return ret;
  4618. }
  4619. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  4620. bool skip_pre_kickoff)
  4621. {
  4622. struct msm_drm_thread *event_thread = NULL;
  4623. struct msm_drm_private *priv = NULL;
  4624. struct sde_encoder_virt *sde_enc = NULL;
  4625. if (!enc || !enc->dev || !enc->dev->dev_private) {
  4626. SDE_ERROR("invalid parameters\n");
  4627. return -EINVAL;
  4628. }
  4629. priv = enc->dev->dev_private;
  4630. sde_enc = to_sde_encoder_virt(enc);
  4631. if (!sde_enc->crtc || (sde_enc->crtc->index
  4632. >= ARRAY_SIZE(priv->event_thread))) {
  4633. SDE_DEBUG_ENC(sde_enc,
  4634. "invalid cached CRTC: %d or crtc index: %d\n",
  4635. sde_enc->crtc == NULL,
  4636. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  4637. return -EINVAL;
  4638. }
  4639. SDE_EVT32_VERBOSE(DRMID(enc));
  4640. event_thread = &priv->event_thread[sde_enc->crtc->index];
  4641. if (!skip_pre_kickoff) {
  4642. sde_enc->delay_kickoff = true;
  4643. kthread_queue_work(&event_thread->worker,
  4644. &sde_enc->esd_trigger_work);
  4645. kthread_flush_work(&sde_enc->esd_trigger_work);
  4646. }
  4647. /*
  4648. * panel may stop generating te signal (vsync) during esd failure. rsc
  4649. * hardware may hang without vsync. Avoid rsc hang by generating the
  4650. * vsync from watchdog timer instead of panel.
  4651. */
  4652. sde_encoder_helper_switch_vsync(enc, true);
  4653. if (!skip_pre_kickoff) {
  4654. sde_encoder_wait_for_event(enc, MSM_ENC_TX_COMPLETE);
  4655. sde_enc->delay_kickoff = false;
  4656. }
  4657. return 0;
  4658. }
  4659. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder)
  4660. {
  4661. struct sde_encoder_virt *sde_enc;
  4662. if (!encoder) {
  4663. SDE_ERROR("invalid drm enc\n");
  4664. return false;
  4665. }
  4666. sde_enc = to_sde_encoder_virt(encoder);
  4667. return sde_enc->recovery_events_enabled;
  4668. }
  4669. void sde_encoder_enable_recovery_event(struct drm_encoder *encoder)
  4670. {
  4671. struct sde_encoder_virt *sde_enc;
  4672. if (!encoder) {
  4673. SDE_ERROR("invalid drm enc\n");
  4674. return;
  4675. }
  4676. sde_enc = to_sde_encoder_virt(encoder);
  4677. sde_enc->recovery_events_enabled = true;
  4678. }