6c483e3b23
Adding debug, info and error prefix for log messages in dsi files. To enable debug logs run "echo 0x1 > /sys/module/drm/parameters/debug" Change-Id: I438ac16954bd1d39450f8adeb7fb17f9ea6f8140 Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
476 строки
14 KiB
C
476 строки
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include "dsi_ctrl_hw.h"
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#include "dsi_ctrl_reg.h"
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#include "dsi_hw.h"
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#define MMSS_MISC_CLAMP_REG_OFF 0x0014
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/**
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* dsi_ctrl_hw_14_setup_lane_map() - setup mapping between
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* logical and physical lanes
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* @ctrl: Pointer to the controller host hardware.
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* @lane_map: Structure defining the mapping between DSI logical
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* lanes and physical lanes.
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*/
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void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl,
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struct dsi_lane_map *lane_map)
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{
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DSI_W32(ctrl, DSI_LANE_SWAP_CTRL, lane_map->lane_map_v1);
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DSI_CTRL_HW_DBG(ctrl, "Lane swap setup complete\n");
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}
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/**
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* dsi_ctrl_hw_14_wait_for_lane_idle()
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* This function waits for all the active DSI lanes to be idle by polling all
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* the FIFO_EMPTY bits and polling he lane status to ensure that all the lanes
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* are in stop state. This function assumes that the bus clocks required to
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* access the registers are already turned on.
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*
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* @ctrl: Pointer to the controller host hardware.
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* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
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* to be stopped.
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*
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* return: Error code.
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*/
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int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes)
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{
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int rc = 0, val = 0;
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u32 stop_state_mask = 0, fifo_empty_mask = 0;
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u32 const sleep_us = 10;
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u32 const timeout_us = 100;
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if (lanes & DSI_DATA_LANE_0) {
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stop_state_mask |= BIT(0);
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fifo_empty_mask |= (BIT(12) | BIT(16));
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}
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if (lanes & DSI_DATA_LANE_1) {
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stop_state_mask |= BIT(1);
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fifo_empty_mask |= BIT(20);
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}
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if (lanes & DSI_DATA_LANE_2) {
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stop_state_mask |= BIT(2);
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fifo_empty_mask |= BIT(24);
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}
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if (lanes & DSI_DATA_LANE_3) {
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stop_state_mask |= BIT(3);
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fifo_empty_mask |= BIT(28);
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}
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DSI_CTRL_HW_DBG(ctrl, "polling for fifo empty, mask=0x%08x\n",
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fifo_empty_mask);
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rc = readl_poll_timeout(ctrl->base + DSI_FIFO_STATUS, val,
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(val & fifo_empty_mask), sleep_us, timeout_us);
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if (rc) {
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DSI_CTRL_HW_ERR(ctrl, "fifo not empty, FIFO_STATUS=0x%08x\n",
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val);
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goto error;
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}
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DSI_CTRL_HW_DBG(ctrl, "polling for lanes to be in stop state, mask=0x%08x\n",
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stop_state_mask);
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rc = readl_poll_timeout(ctrl->base + DSI_LANE_STATUS, val,
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(val & stop_state_mask), sleep_us, timeout_us);
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if (rc) {
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DSI_CTRL_HW_ERR(ctrl, "lanes not in stop state, LANE_STATUS=0x%08x\n",
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val);
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goto error;
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}
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error:
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return rc;
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}
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/**
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* ulps_request() - request ulps entry for specified lanes
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* @ctrl: Pointer to the controller host hardware.
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* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
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* to enter ULPS.
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*
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* Caller should check if lanes are in ULPS mode by calling
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* get_lanes_in_ulps() operation.
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*/
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void dsi_ctrl_hw_cmn_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes)
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{
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u32 reg = 0;
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reg = DSI_R32(ctrl, DSI_LANE_CTRL);
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if (lanes & DSI_CLOCK_LANE)
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reg |= BIT(4);
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if (lanes & DSI_DATA_LANE_0)
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reg |= BIT(0);
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if (lanes & DSI_DATA_LANE_1)
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reg |= BIT(1);
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if (lanes & DSI_DATA_LANE_2)
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reg |= BIT(2);
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if (lanes & DSI_DATA_LANE_3)
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reg |= BIT(3);
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/*
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* ULPS entry request. Wait for short time to make sure
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* that the lanes enter ULPS. Recommended as per HPG.
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*/
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DSI_W32(ctrl, DSI_LANE_CTRL, reg);
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usleep_range(100, 110);
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DSI_CTRL_HW_DBG(ctrl, "ULPS requested for lanes 0x%x\n", lanes);
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}
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/**
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* ulps_exit() - exit ULPS on specified lanes
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* @ctrl: Pointer to the controller host hardware.
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* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
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* to exit ULPS.
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*
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* Caller should check if lanes are in active mode by calling
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* get_lanes_in_ulps() operation.
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*/
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void dsi_ctrl_hw_cmn_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes)
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{
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u32 reg = 0;
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u32 prev_reg = 0;
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prev_reg = DSI_R32(ctrl, DSI_LANE_CTRL);
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prev_reg &= BIT(24);
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if (lanes & DSI_CLOCK_LANE)
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reg |= BIT(12);
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if (lanes & DSI_DATA_LANE_0)
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reg |= BIT(8);
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if (lanes & DSI_DATA_LANE_1)
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reg |= BIT(9);
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if (lanes & DSI_DATA_LANE_2)
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reg |= BIT(10);
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if (lanes & DSI_DATA_LANE_3)
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reg |= BIT(11);
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/*
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* ULPS Exit Request
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* Hardware requirement is to wait for at least 1ms
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*/
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DSI_W32(ctrl, DSI_LANE_CTRL, reg | prev_reg);
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usleep_range(1000, 1010);
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/*
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* Sometimes when exiting ULPS, it is possible that some DSI
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* lanes are not in the stop state which could lead to DSI
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* commands not going through. To avoid this, force the lanes
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* to be in stop state.
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*/
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DSI_W32(ctrl, DSI_LANE_CTRL, (reg << 8) | prev_reg);
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wmb(); /* ensure lanes are put to stop state */
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DSI_W32(ctrl, DSI_LANE_CTRL, 0x0 | prev_reg);
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wmb(); /* ensure lanes are put to stop state */
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DSI_CTRL_HW_DBG(ctrl, "ULPS exit request for lanes=0x%x\n", lanes);
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}
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/**
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* get_lanes_in_ulps() - returns the list of lanes in ULPS mode
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* @ctrl: Pointer to the controller host hardware.
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*
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* Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS
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* state. If 0 is returned, all the lanes are active.
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*
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* Return: List of lanes in ULPS state.
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*/
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u32 dsi_ctrl_hw_cmn_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl)
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{
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u32 reg = 0;
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u32 lanes = 0;
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reg = DSI_R32(ctrl, DSI_LANE_STATUS);
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if (!(reg & BIT(8)))
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lanes |= DSI_DATA_LANE_0;
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if (!(reg & BIT(9)))
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lanes |= DSI_DATA_LANE_1;
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if (!(reg & BIT(10)))
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lanes |= DSI_DATA_LANE_2;
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if (!(reg & BIT(11)))
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lanes |= DSI_DATA_LANE_3;
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if (!(reg & BIT(12)))
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lanes |= DSI_CLOCK_LANE;
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DSI_CTRL_HW_DBG(ctrl, "lanes in ulps = 0x%x\n", lanes);
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return lanes;
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}
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/**
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* clamp_enable() - enable DSI clamps to keep PHY driving a stable link
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* @ctrl: Pointer to the controller host hardware.
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* @lanes: ORed list of lanes which need to be clamped.
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* @enable_ulps: Boolean to specify if ULPS is enabled in DSI controller
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*/
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void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl,
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u32 lanes,
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bool enable_ulps)
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{
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u32 clamp_reg = 0;
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u32 bit_shift = 0;
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u32 reg = 0;
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if (ctrl->index == 1)
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bit_shift = 16;
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if (lanes & DSI_CLOCK_LANE) {
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clamp_reg |= BIT(9);
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if (enable_ulps)
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clamp_reg |= BIT(8);
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}
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if (lanes & DSI_DATA_LANE_0) {
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clamp_reg |= BIT(7);
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if (enable_ulps)
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clamp_reg |= BIT(6);
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}
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if (lanes & DSI_DATA_LANE_1) {
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clamp_reg |= BIT(5);
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if (enable_ulps)
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clamp_reg |= BIT(4);
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}
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if (lanes & DSI_DATA_LANE_2) {
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clamp_reg |= BIT(3);
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if (enable_ulps)
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clamp_reg |= BIT(2);
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}
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if (lanes & DSI_DATA_LANE_3) {
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clamp_reg |= BIT(1);
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if (enable_ulps)
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clamp_reg |= BIT(0);
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}
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reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
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reg |= (clamp_reg << bit_shift);
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DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
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reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
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reg |= (BIT(15) << bit_shift); /* Enable clamp */
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DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
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DSI_CTRL_HW_DBG(ctrl, "Clamps enabled for lanes=0x%x\n", lanes);
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}
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/**
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* clamp_disable() - disable DSI clamps
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* @ctrl: Pointer to the controller host hardware.
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* @lanes: ORed list of lanes which need to have clamps released.
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* @disable_ulps: Boolean to specify if ULPS is enabled in DSI controller
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*/
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void dsi_ctrl_hw_14_clamp_disable(struct dsi_ctrl_hw *ctrl,
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u32 lanes,
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bool disable_ulps)
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{
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u32 clamp_reg = 0;
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u32 bit_shift = 0;
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u32 reg = 0;
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if (ctrl->index == 1)
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bit_shift = 16;
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if (lanes & DSI_CLOCK_LANE) {
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clamp_reg |= BIT(9);
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if (disable_ulps)
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clamp_reg |= BIT(8);
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}
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if (lanes & DSI_DATA_LANE_0) {
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clamp_reg |= BIT(7);
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if (disable_ulps)
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clamp_reg |= BIT(6);
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}
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if (lanes & DSI_DATA_LANE_1) {
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clamp_reg |= BIT(5);
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if (disable_ulps)
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clamp_reg |= BIT(4);
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}
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if (lanes & DSI_DATA_LANE_2) {
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clamp_reg |= BIT(3);
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if (disable_ulps)
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clamp_reg |= BIT(2);
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}
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if (lanes & DSI_DATA_LANE_3) {
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clamp_reg |= BIT(1);
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if (disable_ulps)
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clamp_reg |= BIT(0);
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}
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clamp_reg |= BIT(15); /* Enable clamp */
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clamp_reg <<= bit_shift;
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reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
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reg &= ~(clamp_reg);
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DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
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DSI_CTRL_HW_DBG(ctrl, "Disable clamps for lanes=%d\n", lanes);
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}
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#define DUMP_REG_VALUE(off) "\t%-30s: 0x%08x\n", #off, DSI_R32(ctrl, off)
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ssize_t dsi_ctrl_hw_14_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
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char *buf,
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u32 size)
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{
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u32 len = 0;
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len += snprintf((buf + len), (size - len), "CONFIGURATION REGS:\n");
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_HW_VERSION));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_STATUS));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_FIFO_STATUS));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_SYNC_DATATYPE));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_PIXEL_DATATYPE));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_BLANKING_DATATYPE));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_DATA_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_ACTIVE_H));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_ACTIVE_V));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_TOTAL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_HSYNC));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_VSYNC));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_VIDEO_MODE_VSYNC_VPOS));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_COMMAND_MODE_DMA_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_DMA_CMD_OFFSET));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_DMA_CMD_LENGTH));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_DMA_FIFO_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_DMA_NULL_PACKET_DATA));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM0_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM0_TOTAL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM1_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM1_TOTAL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_ACK_ERR_STATUS));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_RDBK_DATA0));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_RDBK_DATA1));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_RDBK_DATA2));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_RDBK_DATA3));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_RDBK_DATATYPE0));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_RDBK_DATATYPE1));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_TRIG_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_EXT_MUX));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_EXT_MUX_TE_PULSE_DETECT_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_CMD_MODE_DMA_SW_TRIGGER));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_CMD_MODE_MDP_SW_TRIGGER));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_CMD_MODE_BTA_SW_TRIGGER));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_RESET_SW_TRIGGER));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_LANE_STATUS));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_LANE_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_LANE_SWAP_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_DLN0_PHY_ERR));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_LP_TIMER_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_HS_TIMER_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_TIMEOUT_STATUS));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_CLKOUT_TIMING_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_EOT_PACKET));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_EOT_PACKET_CTRL));
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len += snprintf((buf + len), (size - len),
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DUMP_REG_VALUE(DSI_GENERIC_ESC_TX_TRIGGER));
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len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_ERR_INT_MASK0));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_INT_CTRL));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_SOFT_RESET));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_CLK_CTRL));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_CLK_STATUS));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_PHY_SW_RESET));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_AXI2AHB_CTRL));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_CTRL2));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM2_CTRL));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM2_TOTAL));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_VBIF_CTRL));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_AES_CTRL));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_RDBK_DATA_CTRL));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL2));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_STATUS));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_WRITE_TRIGGER));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_DSI_TIMING_FLUSH));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_DSI_TIMING_DB_MODE));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_RESET));
|
|
len += snprintf((buf + len), (size - len),
|
|
DUMP_REG_VALUE(DSI_VERSION));
|
|
|
|
DSI_CTRL_HW_ERR(ctrl, "LLENGTH = %d\n", len);
|
|
return len;
|
|
}
|