qcs405.c 207 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/input.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pm_qos.h>
  23. #include <sound/core.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/info.h>
  29. #include <dsp/audio_notifier.h>
  30. #include <dsp/q6afe-v2.h>
  31. #include <dsp/q6core.h>
  32. #include "device_event.h"
  33. #include "msm-pcm-routing-v2.h"
  34. #include "codecs/msm-cdc-pinctrl.h"
  35. #include "codecs/wcd9335.h"
  36. #include "codecs/wsa881x.h"
  37. #include <dt-bindings/sound/audio-codec-port-types.h>
  38. #define DRV_NAME "qcs405-asoc-snd"
  39. #define __CHIPSET__ "QCS405 "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define DEV_NAME_STR_LEN 32
  42. #define SAMPLING_RATE_8KHZ 8000
  43. #define SAMPLING_RATE_11P025KHZ 11025
  44. #define SAMPLING_RATE_16KHZ 16000
  45. #define SAMPLING_RATE_22P05KHZ 22050
  46. #define SAMPLING_RATE_32KHZ 32000
  47. #define SAMPLING_RATE_44P1KHZ 44100
  48. #define SAMPLING_RATE_48KHZ 48000
  49. #define SAMPLING_RATE_88P2KHZ 88200
  50. #define SAMPLING_RATE_96KHZ 96000
  51. #define SAMPLING_RATE_176P4KHZ 176400
  52. #define SAMPLING_RATE_192KHZ 192000
  53. #define SAMPLING_RATE_352P8KHZ 352800
  54. #define SAMPLING_RATE_384KHZ 384000
  55. #define WSA8810_NAME_1 "wsa881x.20170211"
  56. #define WSA8810_NAME_2 "wsa881x.20170212"
  57. #define WCN_CDC_SLIM_RX_CH_MAX 2
  58. #define WCN_CDC_SLIM_TX_CH_MAX 3
  59. #define TDM_CHANNEL_MAX 8
  60. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  61. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  62. enum {
  63. SLIM_RX_0 = 0,
  64. SLIM_RX_1,
  65. SLIM_RX_2,
  66. SLIM_RX_3,
  67. SLIM_RX_4,
  68. SLIM_RX_5,
  69. SLIM_RX_6,
  70. SLIM_RX_7,
  71. SLIM_RX_MAX,
  72. };
  73. enum {
  74. SLIM_TX_0 = 0,
  75. SLIM_TX_1,
  76. SLIM_TX_2,
  77. SLIM_TX_3,
  78. SLIM_TX_4,
  79. SLIM_TX_5,
  80. SLIM_TX_6,
  81. SLIM_TX_7,
  82. SLIM_TX_8,
  83. SLIM_TX_MAX,
  84. };
  85. enum {
  86. PRIM_MI2S = 0,
  87. SEC_MI2S,
  88. TERT_MI2S,
  89. QUAT_MI2S,
  90. QUIN_MI2S,
  91. MI2S_MAX,
  92. };
  93. enum {
  94. PRIM_AUX_PCM = 0,
  95. SEC_AUX_PCM,
  96. TERT_AUX_PCM,
  97. QUAT_AUX_PCM,
  98. QUIN_AUX_PCM,
  99. AUX_PCM_MAX,
  100. };
  101. enum {
  102. WSA_CDC_DMA_RX_0 = 0,
  103. WSA_CDC_DMA_RX_1,
  104. CDC_DMA_RX_MAX,
  105. };
  106. enum {
  107. WSA_CDC_DMA_TX_0 = 0,
  108. WSA_CDC_DMA_TX_1,
  109. WSA_CDC_DMA_TX_2,
  110. VA_CDC_DMA_TX_0,
  111. VA_CDC_DMA_TX_1,
  112. CDC_DMA_TX_MAX,
  113. };
  114. struct mi2s_conf {
  115. struct mutex lock;
  116. u32 ref_cnt;
  117. u32 msm_is_mi2s_master;
  118. };
  119. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  120. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  121. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  122. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  123. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  124. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  125. };
  126. struct dev_config {
  127. u32 sample_rate;
  128. u32 bit_format;
  129. u32 channels;
  130. };
  131. struct msm_wsa881x_dev_info {
  132. struct device_node *of_node;
  133. u32 index;
  134. };
  135. enum pinctrl_pin_state {
  136. STATE_DISABLE = 0, /* All pins are in sleep state */
  137. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  138. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  139. };
  140. struct msm_pinctrl_info {
  141. struct pinctrl *pinctrl;
  142. struct pinctrl_state *mi2s_disable;
  143. struct pinctrl_state *tdm_disable;
  144. struct pinctrl_state *mi2s_active;
  145. struct pinctrl_state *tdm_active;
  146. enum pinctrl_pin_state curr_state;
  147. };
  148. struct msm_asoc_mach_data {
  149. struct snd_info_entry *codec_root;
  150. struct msm_pinctrl_info pinctrl_info;
  151. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  152. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  153. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  154. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  155. int dmic_01_gpio_cnt;
  156. int dmic_23_gpio_cnt;
  157. int dmic_45_gpio_cnt;
  158. int dmic_67_gpio_cnt;
  159. };
  160. struct msm_asoc_wcd93xx_codec {
  161. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  162. enum afe_config_type config_type);
  163. };
  164. static const char *const pin_states[] = {"sleep", "i2s-active",
  165. "tdm-active"};
  166. enum {
  167. TDM_0 = 0,
  168. TDM_1,
  169. TDM_2,
  170. TDM_3,
  171. TDM_4,
  172. TDM_5,
  173. TDM_6,
  174. TDM_7,
  175. TDM_PORT_MAX,
  176. };
  177. enum {
  178. TDM_PRI = 0,
  179. TDM_SEC,
  180. TDM_TERT,
  181. TDM_QUAT,
  182. TDM_QUIN,
  183. TDM_INTERFACE_MAX,
  184. };
  185. struct tdm_port {
  186. u32 mode;
  187. u32 channel;
  188. };
  189. /* TDM default config */
  190. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  191. { /* PRI TDM */
  192. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  193. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  194. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  195. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  196. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  197. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  198. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  199. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  200. },
  201. { /* SEC TDM */
  202. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  203. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  210. },
  211. { /* TERT TDM */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  220. },
  221. { /* QUAT TDM */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  230. },
  231. { /* QUIN TDM */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  240. }
  241. };
  242. /* TDM default config */
  243. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  244. { /* PRI TDM */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  253. },
  254. { /* SEC TDM */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  263. },
  264. { /* TERT TDM */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  273. },
  274. { /* QUAT TDM */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  283. },
  284. { /* QUIN TDM */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  293. }
  294. };
  295. /* Default configuration of slimbus channels */
  296. static struct dev_config slim_rx_cfg[] = {
  297. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  298. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  299. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  300. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  301. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  302. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  303. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  304. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  305. };
  306. static struct dev_config slim_tx_cfg[] = {
  307. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  308. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  309. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  316. };
  317. /* Default configuration of Codec DMA Interface Tx */
  318. static struct dev_config cdc_dma_rx_cfg[] = {
  319. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  320. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  321. };
  322. /* Default configuration of Codec DMA Interface Rx */
  323. static struct dev_config cdc_dma_tx_cfg[] = {
  324. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  325. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  326. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  327. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  328. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  329. };
  330. static struct dev_config usb_rx_cfg = {
  331. .sample_rate = SAMPLING_RATE_48KHZ,
  332. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  333. .channels = 2,
  334. };
  335. static struct dev_config usb_tx_cfg = {
  336. .sample_rate = SAMPLING_RATE_48KHZ,
  337. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  338. .channels = 1,
  339. };
  340. static struct dev_config proxy_rx_cfg = {
  341. .sample_rate = SAMPLING_RATE_48KHZ,
  342. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  343. .channels = 2,
  344. };
  345. /* Default configuration of MI2S channels */
  346. static struct dev_config mi2s_rx_cfg[] = {
  347. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  349. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  350. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  351. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  352. };
  353. static struct dev_config mi2s_tx_cfg[] = {
  354. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  355. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  356. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  357. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  358. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  359. };
  360. static struct dev_config aux_pcm_rx_cfg[] = {
  361. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  362. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  363. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  364. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  365. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  366. };
  367. static struct dev_config aux_pcm_tx_cfg[] = {
  368. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  369. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  370. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  371. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  372. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  373. };
  374. static int msm_vi_feed_tx_ch = 2;
  375. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  376. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  377. "Five", "Six", "Seven",
  378. "Eight"};
  379. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  380. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  381. "S32_LE"};
  382. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  383. "KHZ_32", "KHZ_44P1", "KHZ_48",
  384. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  385. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  386. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  387. "KHZ_44P1", "KHZ_48",
  388. "KHZ_88P2", "KHZ_96"};
  389. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  390. "Five", "Six", "Seven",
  391. "Eight"};
  392. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  393. "Six", "Seven", "Eight"};
  394. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  395. "KHZ_16", "KHZ_22P05",
  396. "KHZ_32", "KHZ_44P1", "KHZ_48",
  397. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  398. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  399. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  400. "Five", "Six", "Seven", "Eight"};
  401. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  402. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  403. "KHZ_48", "KHZ_176P4",
  404. "KHZ_352P8"};
  405. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  406. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  407. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  408. "KHZ_48", "KHZ_96", "KHZ_192"};
  409. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  410. "Five", "Six", "Seven",
  411. "Eight"};
  412. static const char *const qos_text[] = {"Disable", "Enable"};
  413. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  414. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  415. "Five", "Six", "Seven",
  416. "Eight"};
  417. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  418. "KHZ_32", "KHZ_44P1", "KHZ_48",
  419. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  420. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  421. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  422. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  423. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  424. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  425. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  426. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  427. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  428. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  429. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  499. cdc_dma_sample_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  501. cdc_dma_sample_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  503. cdc_dma_sample_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  505. cdc_dma_sample_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  507. cdc_dma_sample_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  509. cdc_dma_sample_rate_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  511. cdc_dma_sample_rate_text);
  512. static struct platform_device *spdev;
  513. static bool is_initial_boot;
  514. static bool codec_reg_done;
  515. static struct snd_soc_aux_dev *msm_aux_dev;
  516. static struct snd_soc_codec_conf *msm_codec_conf;
  517. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  518. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  519. int enable, bool dapm);
  520. static int msm_wsa881x_init(struct snd_soc_component *component);
  521. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  522. struct snd_ctl_elem_value *ucontrol);
  523. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  524. {"MIC BIAS1", NULL, "MCLK TX"},
  525. {"MIC BIAS2", NULL, "MCLK TX"},
  526. {"MIC BIAS3", NULL, "MCLK TX"},
  527. {"MIC BIAS4", NULL, "MCLK TX"},
  528. };
  529. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  530. {
  531. AFE_API_VERSION_I2S_CONFIG,
  532. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  533. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  534. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  535. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  536. 0,
  537. },
  538. {
  539. AFE_API_VERSION_I2S_CONFIG,
  540. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  541. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  542. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  543. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  544. 0,
  545. },
  546. {
  547. AFE_API_VERSION_I2S_CONFIG,
  548. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  549. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  550. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  551. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  552. 0,
  553. },
  554. {
  555. AFE_API_VERSION_I2S_CONFIG,
  556. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  557. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  558. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  559. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  560. 0,
  561. },
  562. {
  563. AFE_API_VERSION_I2S_CONFIG,
  564. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  565. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  566. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  567. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  568. 0,
  569. }
  570. };
  571. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  572. static int slim_get_sample_rate_val(int sample_rate)
  573. {
  574. int sample_rate_val = 0;
  575. switch (sample_rate) {
  576. case SAMPLING_RATE_8KHZ:
  577. sample_rate_val = 0;
  578. break;
  579. case SAMPLING_RATE_16KHZ:
  580. sample_rate_val = 1;
  581. break;
  582. case SAMPLING_RATE_32KHZ:
  583. sample_rate_val = 2;
  584. break;
  585. case SAMPLING_RATE_44P1KHZ:
  586. sample_rate_val = 3;
  587. break;
  588. case SAMPLING_RATE_48KHZ:
  589. sample_rate_val = 4;
  590. break;
  591. case SAMPLING_RATE_88P2KHZ:
  592. sample_rate_val = 5;
  593. break;
  594. case SAMPLING_RATE_96KHZ:
  595. sample_rate_val = 6;
  596. break;
  597. case SAMPLING_RATE_176P4KHZ:
  598. sample_rate_val = 7;
  599. break;
  600. case SAMPLING_RATE_192KHZ:
  601. sample_rate_val = 8;
  602. break;
  603. case SAMPLING_RATE_352P8KHZ:
  604. sample_rate_val = 9;
  605. break;
  606. case SAMPLING_RATE_384KHZ:
  607. sample_rate_val = 10;
  608. break;
  609. default:
  610. sample_rate_val = 4;
  611. break;
  612. }
  613. return sample_rate_val;
  614. }
  615. static int slim_get_sample_rate(int value)
  616. {
  617. int sample_rate = 0;
  618. switch (value) {
  619. case 0:
  620. sample_rate = SAMPLING_RATE_8KHZ;
  621. break;
  622. case 1:
  623. sample_rate = SAMPLING_RATE_16KHZ;
  624. break;
  625. case 2:
  626. sample_rate = SAMPLING_RATE_32KHZ;
  627. break;
  628. case 3:
  629. sample_rate = SAMPLING_RATE_44P1KHZ;
  630. break;
  631. case 4:
  632. sample_rate = SAMPLING_RATE_48KHZ;
  633. break;
  634. case 5:
  635. sample_rate = SAMPLING_RATE_88P2KHZ;
  636. break;
  637. case 6:
  638. sample_rate = SAMPLING_RATE_96KHZ;
  639. break;
  640. case 7:
  641. sample_rate = SAMPLING_RATE_176P4KHZ;
  642. break;
  643. case 8:
  644. sample_rate = SAMPLING_RATE_192KHZ;
  645. break;
  646. case 9:
  647. sample_rate = SAMPLING_RATE_352P8KHZ;
  648. break;
  649. case 10:
  650. sample_rate = SAMPLING_RATE_384KHZ;
  651. break;
  652. default:
  653. sample_rate = SAMPLING_RATE_48KHZ;
  654. break;
  655. }
  656. return sample_rate;
  657. }
  658. static int slim_get_bit_format_val(int bit_format)
  659. {
  660. int val = 0;
  661. switch (bit_format) {
  662. case SNDRV_PCM_FORMAT_S32_LE:
  663. val = 3;
  664. break;
  665. case SNDRV_PCM_FORMAT_S24_3LE:
  666. val = 2;
  667. break;
  668. case SNDRV_PCM_FORMAT_S24_LE:
  669. val = 1;
  670. break;
  671. case SNDRV_PCM_FORMAT_S16_LE:
  672. default:
  673. val = 0;
  674. break;
  675. }
  676. return val;
  677. }
  678. static int slim_get_bit_format(int val)
  679. {
  680. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  681. switch (val) {
  682. case 0:
  683. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  684. break;
  685. case 1:
  686. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  687. break;
  688. case 2:
  689. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  690. break;
  691. case 3:
  692. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  693. break;
  694. default:
  695. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  696. break;
  697. }
  698. return bit_fmt;
  699. }
  700. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  701. {
  702. int port_id = 0;
  703. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  704. port_id = SLIM_RX_0;
  705. } else if (strnstr(kcontrol->id.name,
  706. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  707. port_id = SLIM_RX_2;
  708. } else if (strnstr(kcontrol->id.name,
  709. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  710. port_id = SLIM_RX_5;
  711. } else if (strnstr(kcontrol->id.name,
  712. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  713. port_id = SLIM_RX_6;
  714. } else if (strnstr(kcontrol->id.name,
  715. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  716. port_id = SLIM_TX_0;
  717. } else if (strnstr(kcontrol->id.name,
  718. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  719. port_id = SLIM_TX_1;
  720. } else {
  721. pr_err("%s: unsupported channel: %s",
  722. __func__, kcontrol->id.name);
  723. return -EINVAL;
  724. }
  725. return port_id;
  726. }
  727. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  728. struct snd_ctl_elem_value *ucontrol)
  729. {
  730. int ch_num = slim_get_port_idx(kcontrol);
  731. if (ch_num < 0)
  732. return ch_num;
  733. ucontrol->value.enumerated.item[0] =
  734. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  735. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  736. ch_num, slim_rx_cfg[ch_num].sample_rate,
  737. ucontrol->value.enumerated.item[0]);
  738. return 0;
  739. }
  740. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  741. struct snd_ctl_elem_value *ucontrol)
  742. {
  743. int ch_num = slim_get_port_idx(kcontrol);
  744. if (ch_num < 0)
  745. return ch_num;
  746. slim_rx_cfg[ch_num].sample_rate =
  747. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  748. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  749. ch_num, slim_rx_cfg[ch_num].sample_rate,
  750. ucontrol->value.enumerated.item[0]);
  751. return 0;
  752. }
  753. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  754. struct snd_ctl_elem_value *ucontrol)
  755. {
  756. int ch_num = slim_get_port_idx(kcontrol);
  757. if (ch_num < 0)
  758. return ch_num;
  759. ucontrol->value.enumerated.item[0] =
  760. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  761. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  762. ch_num, slim_tx_cfg[ch_num].sample_rate,
  763. ucontrol->value.enumerated.item[0]);
  764. return 0;
  765. }
  766. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  767. struct snd_ctl_elem_value *ucontrol)
  768. {
  769. int sample_rate = 0;
  770. int ch_num = slim_get_port_idx(kcontrol);
  771. if (ch_num < 0)
  772. return ch_num;
  773. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  774. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  775. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  776. __func__, sample_rate);
  777. return -EINVAL;
  778. }
  779. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  780. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  781. ch_num, slim_tx_cfg[ch_num].sample_rate,
  782. ucontrol->value.enumerated.item[0]);
  783. return 0;
  784. }
  785. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  786. struct snd_ctl_elem_value *ucontrol)
  787. {
  788. int ch_num = slim_get_port_idx(kcontrol);
  789. if (ch_num < 0)
  790. return ch_num;
  791. ucontrol->value.enumerated.item[0] =
  792. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  793. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  794. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  795. ucontrol->value.enumerated.item[0]);
  796. return 0;
  797. }
  798. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  799. struct snd_ctl_elem_value *ucontrol)
  800. {
  801. int ch_num = slim_get_port_idx(kcontrol);
  802. if (ch_num < 0)
  803. return ch_num;
  804. slim_rx_cfg[ch_num].bit_format =
  805. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  806. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  807. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  808. ucontrol->value.enumerated.item[0]);
  809. return 0;
  810. }
  811. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  812. struct snd_ctl_elem_value *ucontrol)
  813. {
  814. int ch_num = slim_get_port_idx(kcontrol);
  815. if (ch_num < 0)
  816. return ch_num;
  817. ucontrol->value.enumerated.item[0] =
  818. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  819. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  820. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  821. ucontrol->value.enumerated.item[0]);
  822. return 0;
  823. }
  824. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  825. struct snd_ctl_elem_value *ucontrol)
  826. {
  827. int ch_num = slim_get_port_idx(kcontrol);
  828. if (ch_num < 0)
  829. return ch_num;
  830. slim_tx_cfg[ch_num].bit_format =
  831. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  832. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  833. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  834. ucontrol->value.enumerated.item[0]);
  835. return 0;
  836. }
  837. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  838. struct snd_ctl_elem_value *ucontrol)
  839. {
  840. int ch_num = slim_get_port_idx(kcontrol);
  841. if (ch_num < 0)
  842. return ch_num;
  843. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  844. ch_num, slim_rx_cfg[ch_num].channels);
  845. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  846. return 0;
  847. }
  848. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  849. struct snd_ctl_elem_value *ucontrol)
  850. {
  851. int ch_num = slim_get_port_idx(kcontrol);
  852. if (ch_num < 0)
  853. return ch_num;
  854. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  855. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  856. ch_num, slim_rx_cfg[ch_num].channels);
  857. return 1;
  858. }
  859. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  860. struct snd_ctl_elem_value *ucontrol)
  861. {
  862. int ch_num = slim_get_port_idx(kcontrol);
  863. if (ch_num < 0)
  864. return ch_num;
  865. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  866. ch_num, slim_tx_cfg[ch_num].channels);
  867. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  868. return 0;
  869. }
  870. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  871. struct snd_ctl_elem_value *ucontrol)
  872. {
  873. int ch_num = slim_get_port_idx(kcontrol);
  874. if (ch_num < 0)
  875. return ch_num;
  876. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  877. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  878. ch_num, slim_tx_cfg[ch_num].channels);
  879. return 1;
  880. }
  881. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  882. struct snd_ctl_elem_value *ucontrol)
  883. {
  884. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  885. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  886. ucontrol->value.integer.value[0]);
  887. return 0;
  888. }
  889. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  890. struct snd_ctl_elem_value *ucontrol)
  891. {
  892. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  893. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  894. return 1;
  895. }
  896. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  897. struct snd_ctl_elem_value *ucontrol)
  898. {
  899. /*
  900. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  901. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  902. * value.
  903. */
  904. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  905. case SAMPLING_RATE_96KHZ:
  906. ucontrol->value.integer.value[0] = 5;
  907. break;
  908. case SAMPLING_RATE_88P2KHZ:
  909. ucontrol->value.integer.value[0] = 4;
  910. break;
  911. case SAMPLING_RATE_48KHZ:
  912. ucontrol->value.integer.value[0] = 3;
  913. break;
  914. case SAMPLING_RATE_44P1KHZ:
  915. ucontrol->value.integer.value[0] = 2;
  916. break;
  917. case SAMPLING_RATE_16KHZ:
  918. ucontrol->value.integer.value[0] = 1;
  919. break;
  920. case SAMPLING_RATE_8KHZ:
  921. default:
  922. ucontrol->value.integer.value[0] = 0;
  923. break;
  924. }
  925. pr_debug("%s: sample rate = %d", __func__,
  926. slim_rx_cfg[SLIM_RX_7].sample_rate);
  927. return 0;
  928. }
  929. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  930. struct snd_ctl_elem_value *ucontrol)
  931. {
  932. switch (ucontrol->value.integer.value[0]) {
  933. case 1:
  934. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  935. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  936. break;
  937. case 2:
  938. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  939. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  940. break;
  941. case 3:
  942. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  943. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  944. break;
  945. case 4:
  946. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  947. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  948. break;
  949. case 5:
  950. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  951. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  952. break;
  953. case 0:
  954. default:
  955. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  956. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  957. break;
  958. }
  959. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  960. __func__,
  961. slim_rx_cfg[SLIM_RX_7].sample_rate,
  962. slim_tx_cfg[SLIM_TX_7].sample_rate,
  963. ucontrol->value.enumerated.item[0]);
  964. return 0;
  965. }
  966. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  967. {
  968. int idx = 0;
  969. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  970. sizeof("WSA_CDC_DMA_RX_0")))
  971. idx = WSA_CDC_DMA_RX_0;
  972. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  973. sizeof("WSA_CDC_DMA_RX_0")))
  974. idx = WSA_CDC_DMA_RX_1;
  975. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  976. sizeof("WSA_CDC_DMA_TX_0")))
  977. idx = WSA_CDC_DMA_TX_0;
  978. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  979. sizeof("WSA_CDC_DMA_TX_1")))
  980. idx = WSA_CDC_DMA_TX_1;
  981. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  982. sizeof("WSA_CDC_DMA_TX_2")))
  983. idx = WSA_CDC_DMA_TX_2;
  984. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  985. sizeof("VA_CDC_DMA_TX_0")))
  986. idx = VA_CDC_DMA_TX_0;
  987. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  988. sizeof("VA_CDC_DMA_TX_1")))
  989. idx = VA_CDC_DMA_TX_1;
  990. else {
  991. pr_err("%s: unsupported port: %s\n",
  992. __func__, kcontrol->id.name);
  993. return -EINVAL;
  994. }
  995. return idx;
  996. }
  997. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  998. struct snd_ctl_elem_value *ucontrol)
  999. {
  1000. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1001. if (ch_num < 0)
  1002. return ch_num;
  1003. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1004. cdc_dma_rx_cfg[ch_num].channels - 1);
  1005. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1006. return 0;
  1007. }
  1008. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1009. struct snd_ctl_elem_value *ucontrol)
  1010. {
  1011. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1012. if (ch_num < 0)
  1013. return ch_num;
  1014. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1015. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1016. cdc_dma_rx_cfg[ch_num].channels);
  1017. return 1;
  1018. }
  1019. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1020. struct snd_ctl_elem_value *ucontrol)
  1021. {
  1022. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1023. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1024. case SNDRV_PCM_FORMAT_S32_LE:
  1025. ucontrol->value.integer.value[0] = 3;
  1026. break;
  1027. case SNDRV_PCM_FORMAT_S24_3LE:
  1028. ucontrol->value.integer.value[0] = 2;
  1029. break;
  1030. case SNDRV_PCM_FORMAT_S24_LE:
  1031. ucontrol->value.integer.value[0] = 1;
  1032. break;
  1033. case SNDRV_PCM_FORMAT_S16_LE:
  1034. default:
  1035. ucontrol->value.integer.value[0] = 0;
  1036. break;
  1037. }
  1038. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1039. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1040. ucontrol->value.integer.value[0]);
  1041. return 0;
  1042. }
  1043. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1044. struct snd_ctl_elem_value *ucontrol)
  1045. {
  1046. int rc = 0;
  1047. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1048. switch (ucontrol->value.integer.value[0]) {
  1049. case 3:
  1050. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1051. break;
  1052. case 2:
  1053. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1054. break;
  1055. case 1:
  1056. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1057. break;
  1058. case 0:
  1059. default:
  1060. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1061. break;
  1062. }
  1063. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1064. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1065. ucontrol->value.integer.value[0]);
  1066. return rc;
  1067. }
  1068. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1069. {
  1070. int sample_rate_val = 0;
  1071. switch (sample_rate) {
  1072. case SAMPLING_RATE_8KHZ:
  1073. sample_rate_val = 0;
  1074. break;
  1075. case SAMPLING_RATE_16KHZ:
  1076. sample_rate_val = 1;
  1077. break;
  1078. case SAMPLING_RATE_32KHZ:
  1079. sample_rate_val = 2;
  1080. break;
  1081. case SAMPLING_RATE_44P1KHZ:
  1082. sample_rate_val = 3;
  1083. break;
  1084. case SAMPLING_RATE_48KHZ:
  1085. sample_rate_val = 4;
  1086. break;
  1087. case SAMPLING_RATE_88P2KHZ:
  1088. sample_rate_val = 5;
  1089. break;
  1090. case SAMPLING_RATE_96KHZ:
  1091. sample_rate_val = 6;
  1092. break;
  1093. case SAMPLING_RATE_176P4KHZ:
  1094. sample_rate_val = 7;
  1095. break;
  1096. case SAMPLING_RATE_192KHZ:
  1097. sample_rate_val = 8;
  1098. break;
  1099. case SAMPLING_RATE_352P8KHZ:
  1100. sample_rate_val = 9;
  1101. break;
  1102. case SAMPLING_RATE_384KHZ:
  1103. sample_rate_val = 10;
  1104. break;
  1105. default:
  1106. sample_rate_val = 4;
  1107. break;
  1108. }
  1109. return sample_rate_val;
  1110. }
  1111. static int cdc_dma_get_sample_rate(int value)
  1112. {
  1113. int sample_rate = 0;
  1114. switch (value) {
  1115. case 0:
  1116. sample_rate = SAMPLING_RATE_8KHZ;
  1117. break;
  1118. case 1:
  1119. sample_rate = SAMPLING_RATE_16KHZ;
  1120. break;
  1121. case 2:
  1122. sample_rate = SAMPLING_RATE_32KHZ;
  1123. break;
  1124. case 3:
  1125. sample_rate = SAMPLING_RATE_44P1KHZ;
  1126. break;
  1127. case 4:
  1128. sample_rate = SAMPLING_RATE_48KHZ;
  1129. break;
  1130. case 5:
  1131. sample_rate = SAMPLING_RATE_88P2KHZ;
  1132. break;
  1133. case 6:
  1134. sample_rate = SAMPLING_RATE_96KHZ;
  1135. break;
  1136. case 7:
  1137. sample_rate = SAMPLING_RATE_176P4KHZ;
  1138. break;
  1139. case 8:
  1140. sample_rate = SAMPLING_RATE_192KHZ;
  1141. break;
  1142. case 9:
  1143. sample_rate = SAMPLING_RATE_352P8KHZ;
  1144. break;
  1145. case 10:
  1146. sample_rate = SAMPLING_RATE_384KHZ;
  1147. break;
  1148. default:
  1149. sample_rate = SAMPLING_RATE_48KHZ;
  1150. break;
  1151. }
  1152. return sample_rate;
  1153. }
  1154. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1155. struct snd_ctl_elem_value *ucontrol)
  1156. {
  1157. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1158. if (ch_num < 0)
  1159. return ch_num;
  1160. ucontrol->value.enumerated.item[0] =
  1161. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1162. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1163. cdc_dma_rx_cfg[ch_num].sample_rate);
  1164. return 0;
  1165. }
  1166. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1167. struct snd_ctl_elem_value *ucontrol)
  1168. {
  1169. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1170. if (ch_num < 0)
  1171. return ch_num;
  1172. cdc_dma_rx_cfg[ch_num].sample_rate =
  1173. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1174. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1175. __func__, ucontrol->value.enumerated.item[0],
  1176. cdc_dma_rx_cfg[ch_num].sample_rate);
  1177. return 0;
  1178. }
  1179. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1180. struct snd_ctl_elem_value *ucontrol)
  1181. {
  1182. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1183. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1184. cdc_dma_tx_cfg[ch_num].channels);
  1185. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1186. return 0;
  1187. }
  1188. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1189. struct snd_ctl_elem_value *ucontrol)
  1190. {
  1191. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1192. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1193. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1194. cdc_dma_tx_cfg[ch_num].channels);
  1195. return 1;
  1196. }
  1197. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1198. struct snd_ctl_elem_value *ucontrol)
  1199. {
  1200. int sample_rate_val;
  1201. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1202. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1203. case SAMPLING_RATE_384KHZ:
  1204. sample_rate_val = 12;
  1205. break;
  1206. case SAMPLING_RATE_352P8KHZ:
  1207. sample_rate_val = 11;
  1208. break;
  1209. case SAMPLING_RATE_192KHZ:
  1210. sample_rate_val = 10;
  1211. break;
  1212. case SAMPLING_RATE_176P4KHZ:
  1213. sample_rate_val = 9;
  1214. break;
  1215. case SAMPLING_RATE_96KHZ:
  1216. sample_rate_val = 8;
  1217. break;
  1218. case SAMPLING_RATE_88P2KHZ:
  1219. sample_rate_val = 7;
  1220. break;
  1221. case SAMPLING_RATE_48KHZ:
  1222. sample_rate_val = 6;
  1223. break;
  1224. case SAMPLING_RATE_44P1KHZ:
  1225. sample_rate_val = 5;
  1226. break;
  1227. case SAMPLING_RATE_32KHZ:
  1228. sample_rate_val = 4;
  1229. break;
  1230. case SAMPLING_RATE_22P05KHZ:
  1231. sample_rate_val = 3;
  1232. break;
  1233. case SAMPLING_RATE_16KHZ:
  1234. sample_rate_val = 2;
  1235. break;
  1236. case SAMPLING_RATE_11P025KHZ:
  1237. sample_rate_val = 1;
  1238. break;
  1239. case SAMPLING_RATE_8KHZ:
  1240. sample_rate_val = 0;
  1241. break;
  1242. default:
  1243. sample_rate_val = 6;
  1244. break;
  1245. }
  1246. ucontrol->value.integer.value[0] = sample_rate_val;
  1247. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1248. cdc_dma_tx_cfg[ch_num].sample_rate);
  1249. return 0;
  1250. }
  1251. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1252. struct snd_ctl_elem_value *ucontrol)
  1253. {
  1254. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1255. switch (ucontrol->value.integer.value[0]) {
  1256. case 12:
  1257. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1258. break;
  1259. case 11:
  1260. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1261. break;
  1262. case 10:
  1263. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1264. break;
  1265. case 9:
  1266. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1267. break;
  1268. case 8:
  1269. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1270. break;
  1271. case 7:
  1272. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1273. break;
  1274. case 6:
  1275. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1276. break;
  1277. case 5:
  1278. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1279. break;
  1280. case 4:
  1281. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1282. break;
  1283. case 3:
  1284. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1285. break;
  1286. case 2:
  1287. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1288. break;
  1289. case 1:
  1290. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1291. break;
  1292. case 0:
  1293. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1294. break;
  1295. default:
  1296. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1297. break;
  1298. }
  1299. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1300. __func__, ucontrol->value.integer.value[0],
  1301. cdc_dma_tx_cfg[ch_num].sample_rate);
  1302. return 0;
  1303. }
  1304. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1305. struct snd_ctl_elem_value *ucontrol)
  1306. {
  1307. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1308. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1309. case SNDRV_PCM_FORMAT_S32_LE:
  1310. ucontrol->value.integer.value[0] = 3;
  1311. break;
  1312. case SNDRV_PCM_FORMAT_S24_3LE:
  1313. ucontrol->value.integer.value[0] = 2;
  1314. break;
  1315. case SNDRV_PCM_FORMAT_S24_LE:
  1316. ucontrol->value.integer.value[0] = 1;
  1317. break;
  1318. case SNDRV_PCM_FORMAT_S16_LE:
  1319. default:
  1320. ucontrol->value.integer.value[0] = 0;
  1321. break;
  1322. }
  1323. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1324. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1325. ucontrol->value.integer.value[0]);
  1326. return 0;
  1327. }
  1328. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1329. struct snd_ctl_elem_value *ucontrol)
  1330. {
  1331. int rc = 0;
  1332. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1333. switch (ucontrol->value.integer.value[0]) {
  1334. case 3:
  1335. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1336. break;
  1337. case 2:
  1338. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1339. break;
  1340. case 1:
  1341. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1342. break;
  1343. case 0:
  1344. default:
  1345. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1346. break;
  1347. }
  1348. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1349. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1350. ucontrol->value.integer.value[0]);
  1351. return rc;
  1352. }
  1353. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1354. struct snd_ctl_elem_value *ucontrol)
  1355. {
  1356. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1357. usb_rx_cfg.channels);
  1358. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1359. return 0;
  1360. }
  1361. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1362. struct snd_ctl_elem_value *ucontrol)
  1363. {
  1364. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1365. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1366. return 1;
  1367. }
  1368. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1369. struct snd_ctl_elem_value *ucontrol)
  1370. {
  1371. int sample_rate_val;
  1372. switch (usb_rx_cfg.sample_rate) {
  1373. case SAMPLING_RATE_384KHZ:
  1374. sample_rate_val = 12;
  1375. break;
  1376. case SAMPLING_RATE_352P8KHZ:
  1377. sample_rate_val = 11;
  1378. break;
  1379. case SAMPLING_RATE_192KHZ:
  1380. sample_rate_val = 10;
  1381. break;
  1382. case SAMPLING_RATE_176P4KHZ:
  1383. sample_rate_val = 9;
  1384. break;
  1385. case SAMPLING_RATE_96KHZ:
  1386. sample_rate_val = 8;
  1387. break;
  1388. case SAMPLING_RATE_88P2KHZ:
  1389. sample_rate_val = 7;
  1390. break;
  1391. case SAMPLING_RATE_48KHZ:
  1392. sample_rate_val = 6;
  1393. break;
  1394. case SAMPLING_RATE_44P1KHZ:
  1395. sample_rate_val = 5;
  1396. break;
  1397. case SAMPLING_RATE_32KHZ:
  1398. sample_rate_val = 4;
  1399. break;
  1400. case SAMPLING_RATE_22P05KHZ:
  1401. sample_rate_val = 3;
  1402. break;
  1403. case SAMPLING_RATE_16KHZ:
  1404. sample_rate_val = 2;
  1405. break;
  1406. case SAMPLING_RATE_11P025KHZ:
  1407. sample_rate_val = 1;
  1408. break;
  1409. case SAMPLING_RATE_8KHZ:
  1410. default:
  1411. sample_rate_val = 0;
  1412. break;
  1413. }
  1414. ucontrol->value.integer.value[0] = sample_rate_val;
  1415. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1416. usb_rx_cfg.sample_rate);
  1417. return 0;
  1418. }
  1419. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1420. struct snd_ctl_elem_value *ucontrol)
  1421. {
  1422. switch (ucontrol->value.integer.value[0]) {
  1423. case 12:
  1424. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1425. break;
  1426. case 11:
  1427. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1428. break;
  1429. case 10:
  1430. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1431. break;
  1432. case 9:
  1433. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1434. break;
  1435. case 8:
  1436. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1437. break;
  1438. case 7:
  1439. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1440. break;
  1441. case 6:
  1442. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1443. break;
  1444. case 5:
  1445. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1446. break;
  1447. case 4:
  1448. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1449. break;
  1450. case 3:
  1451. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1452. break;
  1453. case 2:
  1454. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1455. break;
  1456. case 1:
  1457. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1458. break;
  1459. case 0:
  1460. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1461. break;
  1462. default:
  1463. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1464. break;
  1465. }
  1466. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1467. __func__, ucontrol->value.integer.value[0],
  1468. usb_rx_cfg.sample_rate);
  1469. return 0;
  1470. }
  1471. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1472. struct snd_ctl_elem_value *ucontrol)
  1473. {
  1474. switch (usb_rx_cfg.bit_format) {
  1475. case SNDRV_PCM_FORMAT_S32_LE:
  1476. ucontrol->value.integer.value[0] = 3;
  1477. break;
  1478. case SNDRV_PCM_FORMAT_S24_3LE:
  1479. ucontrol->value.integer.value[0] = 2;
  1480. break;
  1481. case SNDRV_PCM_FORMAT_S24_LE:
  1482. ucontrol->value.integer.value[0] = 1;
  1483. break;
  1484. case SNDRV_PCM_FORMAT_S16_LE:
  1485. default:
  1486. ucontrol->value.integer.value[0] = 0;
  1487. break;
  1488. }
  1489. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1490. __func__, usb_rx_cfg.bit_format,
  1491. ucontrol->value.integer.value[0]);
  1492. return 0;
  1493. }
  1494. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1495. struct snd_ctl_elem_value *ucontrol)
  1496. {
  1497. int rc = 0;
  1498. switch (ucontrol->value.integer.value[0]) {
  1499. case 3:
  1500. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1501. break;
  1502. case 2:
  1503. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1504. break;
  1505. case 1:
  1506. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1507. break;
  1508. case 0:
  1509. default:
  1510. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1511. break;
  1512. }
  1513. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1514. __func__, usb_rx_cfg.bit_format,
  1515. ucontrol->value.integer.value[0]);
  1516. return rc;
  1517. }
  1518. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1519. struct snd_ctl_elem_value *ucontrol)
  1520. {
  1521. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1522. usb_tx_cfg.channels);
  1523. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1524. return 0;
  1525. }
  1526. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1527. struct snd_ctl_elem_value *ucontrol)
  1528. {
  1529. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1530. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1531. return 1;
  1532. }
  1533. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1534. struct snd_ctl_elem_value *ucontrol)
  1535. {
  1536. int sample_rate_val;
  1537. switch (usb_tx_cfg.sample_rate) {
  1538. case SAMPLING_RATE_384KHZ:
  1539. sample_rate_val = 12;
  1540. break;
  1541. case SAMPLING_RATE_352P8KHZ:
  1542. sample_rate_val = 11;
  1543. break;
  1544. case SAMPLING_RATE_192KHZ:
  1545. sample_rate_val = 10;
  1546. break;
  1547. case SAMPLING_RATE_176P4KHZ:
  1548. sample_rate_val = 9;
  1549. break;
  1550. case SAMPLING_RATE_96KHZ:
  1551. sample_rate_val = 8;
  1552. break;
  1553. case SAMPLING_RATE_88P2KHZ:
  1554. sample_rate_val = 7;
  1555. break;
  1556. case SAMPLING_RATE_48KHZ:
  1557. sample_rate_val = 6;
  1558. break;
  1559. case SAMPLING_RATE_44P1KHZ:
  1560. sample_rate_val = 5;
  1561. break;
  1562. case SAMPLING_RATE_32KHZ:
  1563. sample_rate_val = 4;
  1564. break;
  1565. case SAMPLING_RATE_22P05KHZ:
  1566. sample_rate_val = 3;
  1567. break;
  1568. case SAMPLING_RATE_16KHZ:
  1569. sample_rate_val = 2;
  1570. break;
  1571. case SAMPLING_RATE_11P025KHZ:
  1572. sample_rate_val = 1;
  1573. break;
  1574. case SAMPLING_RATE_8KHZ:
  1575. sample_rate_val = 0;
  1576. break;
  1577. default:
  1578. sample_rate_val = 6;
  1579. break;
  1580. }
  1581. ucontrol->value.integer.value[0] = sample_rate_val;
  1582. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1583. usb_tx_cfg.sample_rate);
  1584. return 0;
  1585. }
  1586. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1587. struct snd_ctl_elem_value *ucontrol)
  1588. {
  1589. switch (ucontrol->value.integer.value[0]) {
  1590. case 12:
  1591. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1592. break;
  1593. case 11:
  1594. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1595. break;
  1596. case 10:
  1597. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1598. break;
  1599. case 9:
  1600. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1601. break;
  1602. case 8:
  1603. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1604. break;
  1605. case 7:
  1606. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1607. break;
  1608. case 6:
  1609. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1610. break;
  1611. case 5:
  1612. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1613. break;
  1614. case 4:
  1615. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1616. break;
  1617. case 3:
  1618. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1619. break;
  1620. case 2:
  1621. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1622. break;
  1623. case 1:
  1624. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1625. break;
  1626. case 0:
  1627. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1628. break;
  1629. default:
  1630. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1631. break;
  1632. }
  1633. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1634. __func__, ucontrol->value.integer.value[0],
  1635. usb_tx_cfg.sample_rate);
  1636. return 0;
  1637. }
  1638. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1639. struct snd_ctl_elem_value *ucontrol)
  1640. {
  1641. switch (usb_tx_cfg.bit_format) {
  1642. case SNDRV_PCM_FORMAT_S32_LE:
  1643. ucontrol->value.integer.value[0] = 3;
  1644. break;
  1645. case SNDRV_PCM_FORMAT_S24_3LE:
  1646. ucontrol->value.integer.value[0] = 2;
  1647. break;
  1648. case SNDRV_PCM_FORMAT_S24_LE:
  1649. ucontrol->value.integer.value[0] = 1;
  1650. break;
  1651. case SNDRV_PCM_FORMAT_S16_LE:
  1652. default:
  1653. ucontrol->value.integer.value[0] = 0;
  1654. break;
  1655. }
  1656. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1657. __func__, usb_tx_cfg.bit_format,
  1658. ucontrol->value.integer.value[0]);
  1659. return 0;
  1660. }
  1661. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1662. struct snd_ctl_elem_value *ucontrol)
  1663. {
  1664. int rc = 0;
  1665. switch (ucontrol->value.integer.value[0]) {
  1666. case 3:
  1667. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1668. break;
  1669. case 2:
  1670. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1671. break;
  1672. case 1:
  1673. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1674. break;
  1675. case 0:
  1676. default:
  1677. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1678. break;
  1679. }
  1680. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1681. __func__, usb_tx_cfg.bit_format,
  1682. ucontrol->value.integer.value[0]);
  1683. return rc;
  1684. }
  1685. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1686. struct snd_ctl_elem_value *ucontrol)
  1687. {
  1688. pr_debug("%s: proxy_rx channels = %d\n",
  1689. __func__, proxy_rx_cfg.channels);
  1690. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1691. return 0;
  1692. }
  1693. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1694. struct snd_ctl_elem_value *ucontrol)
  1695. {
  1696. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1697. pr_debug("%s: proxy_rx channels = %d\n",
  1698. __func__, proxy_rx_cfg.channels);
  1699. return 1;
  1700. }
  1701. static int tdm_get_sample_rate(int value)
  1702. {
  1703. int sample_rate = 0;
  1704. switch (value) {
  1705. case 0:
  1706. sample_rate = SAMPLING_RATE_8KHZ;
  1707. break;
  1708. case 1:
  1709. sample_rate = SAMPLING_RATE_16KHZ;
  1710. break;
  1711. case 2:
  1712. sample_rate = SAMPLING_RATE_32KHZ;
  1713. break;
  1714. case 3:
  1715. sample_rate = SAMPLING_RATE_48KHZ;
  1716. break;
  1717. case 4:
  1718. sample_rate = SAMPLING_RATE_176P4KHZ;
  1719. break;
  1720. case 5:
  1721. sample_rate = SAMPLING_RATE_352P8KHZ;
  1722. break;
  1723. default:
  1724. sample_rate = SAMPLING_RATE_48KHZ;
  1725. break;
  1726. }
  1727. return sample_rate;
  1728. }
  1729. static int aux_pcm_get_sample_rate(int value)
  1730. {
  1731. int sample_rate;
  1732. switch (value) {
  1733. case 1:
  1734. sample_rate = SAMPLING_RATE_16KHZ;
  1735. break;
  1736. case 0:
  1737. default:
  1738. sample_rate = SAMPLING_RATE_8KHZ;
  1739. break;
  1740. }
  1741. return sample_rate;
  1742. }
  1743. static int tdm_get_sample_rate_val(int sample_rate)
  1744. {
  1745. int sample_rate_val = 0;
  1746. switch (sample_rate) {
  1747. case SAMPLING_RATE_8KHZ:
  1748. sample_rate_val = 0;
  1749. break;
  1750. case SAMPLING_RATE_16KHZ:
  1751. sample_rate_val = 1;
  1752. break;
  1753. case SAMPLING_RATE_32KHZ:
  1754. sample_rate_val = 2;
  1755. break;
  1756. case SAMPLING_RATE_48KHZ:
  1757. sample_rate_val = 3;
  1758. break;
  1759. case SAMPLING_RATE_176P4KHZ:
  1760. sample_rate_val = 4;
  1761. break;
  1762. case SAMPLING_RATE_352P8KHZ:
  1763. sample_rate_val = 5;
  1764. break;
  1765. default:
  1766. sample_rate_val = 3;
  1767. break;
  1768. }
  1769. return sample_rate_val;
  1770. }
  1771. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1772. {
  1773. int sample_rate_val;
  1774. switch (sample_rate) {
  1775. case SAMPLING_RATE_16KHZ:
  1776. sample_rate_val = 1;
  1777. break;
  1778. case SAMPLING_RATE_8KHZ:
  1779. default:
  1780. sample_rate_val = 0;
  1781. break;
  1782. }
  1783. return sample_rate_val;
  1784. }
  1785. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1786. struct tdm_port *port)
  1787. {
  1788. if (port) {
  1789. if (strnstr(kcontrol->id.name, "PRI",
  1790. sizeof(kcontrol->id.name))) {
  1791. port->mode = TDM_PRI;
  1792. } else if (strnstr(kcontrol->id.name, "SEC",
  1793. sizeof(kcontrol->id.name))) {
  1794. port->mode = TDM_SEC;
  1795. } else if (strnstr(kcontrol->id.name, "TERT",
  1796. sizeof(kcontrol->id.name))) {
  1797. port->mode = TDM_TERT;
  1798. } else if (strnstr(kcontrol->id.name, "QUAT",
  1799. sizeof(kcontrol->id.name))) {
  1800. port->mode = TDM_QUAT;
  1801. } else if (strnstr(kcontrol->id.name, "QUIN",
  1802. sizeof(kcontrol->id.name))) {
  1803. port->mode = TDM_QUIN;
  1804. } else {
  1805. pr_err("%s: unsupported mode in: %s",
  1806. __func__, kcontrol->id.name);
  1807. return -EINVAL;
  1808. }
  1809. if (strnstr(kcontrol->id.name, "RX_0",
  1810. sizeof(kcontrol->id.name)) ||
  1811. strnstr(kcontrol->id.name, "TX_0",
  1812. sizeof(kcontrol->id.name))) {
  1813. port->channel = TDM_0;
  1814. } else if (strnstr(kcontrol->id.name, "RX_1",
  1815. sizeof(kcontrol->id.name)) ||
  1816. strnstr(kcontrol->id.name, "TX_1",
  1817. sizeof(kcontrol->id.name))) {
  1818. port->channel = TDM_1;
  1819. } else if (strnstr(kcontrol->id.name, "RX_2",
  1820. sizeof(kcontrol->id.name)) ||
  1821. strnstr(kcontrol->id.name, "TX_2",
  1822. sizeof(kcontrol->id.name))) {
  1823. port->channel = TDM_2;
  1824. } else if (strnstr(kcontrol->id.name, "RX_3",
  1825. sizeof(kcontrol->id.name)) ||
  1826. strnstr(kcontrol->id.name, "TX_3",
  1827. sizeof(kcontrol->id.name))) {
  1828. port->channel = TDM_3;
  1829. } else if (strnstr(kcontrol->id.name, "RX_4",
  1830. sizeof(kcontrol->id.name)) ||
  1831. strnstr(kcontrol->id.name, "TX_4",
  1832. sizeof(kcontrol->id.name))) {
  1833. port->channel = TDM_4;
  1834. } else if (strnstr(kcontrol->id.name, "RX_5",
  1835. sizeof(kcontrol->id.name)) ||
  1836. strnstr(kcontrol->id.name, "TX_5",
  1837. sizeof(kcontrol->id.name))) {
  1838. port->channel = TDM_5;
  1839. } else if (strnstr(kcontrol->id.name, "RX_6",
  1840. sizeof(kcontrol->id.name)) ||
  1841. strnstr(kcontrol->id.name, "TX_6",
  1842. sizeof(kcontrol->id.name))) {
  1843. port->channel = TDM_6;
  1844. } else if (strnstr(kcontrol->id.name, "RX_7",
  1845. sizeof(kcontrol->id.name)) ||
  1846. strnstr(kcontrol->id.name, "TX_7",
  1847. sizeof(kcontrol->id.name))) {
  1848. port->channel = TDM_7;
  1849. } else {
  1850. pr_err("%s: unsupported channel in: %s",
  1851. __func__, kcontrol->id.name);
  1852. return -EINVAL;
  1853. }
  1854. } else
  1855. return -EINVAL;
  1856. return 0;
  1857. }
  1858. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1859. struct snd_ctl_elem_value *ucontrol)
  1860. {
  1861. struct tdm_port port;
  1862. int ret = tdm_get_port_idx(kcontrol, &port);
  1863. if (ret) {
  1864. pr_err("%s: unsupported control: %s",
  1865. __func__, kcontrol->id.name);
  1866. } else {
  1867. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1868. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1869. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1870. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1871. ucontrol->value.enumerated.item[0]);
  1872. }
  1873. return ret;
  1874. }
  1875. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1876. struct snd_ctl_elem_value *ucontrol)
  1877. {
  1878. struct tdm_port port;
  1879. int ret = tdm_get_port_idx(kcontrol, &port);
  1880. if (ret) {
  1881. pr_err("%s: unsupported control: %s",
  1882. __func__, kcontrol->id.name);
  1883. } else {
  1884. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1885. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1886. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1887. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1888. ucontrol->value.enumerated.item[0]);
  1889. }
  1890. return ret;
  1891. }
  1892. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1893. struct snd_ctl_elem_value *ucontrol)
  1894. {
  1895. struct tdm_port port;
  1896. int ret = tdm_get_port_idx(kcontrol, &port);
  1897. if (ret) {
  1898. pr_err("%s: unsupported control: %s",
  1899. __func__, kcontrol->id.name);
  1900. } else {
  1901. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1902. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1903. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1904. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1905. ucontrol->value.enumerated.item[0]);
  1906. }
  1907. return ret;
  1908. }
  1909. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1910. struct snd_ctl_elem_value *ucontrol)
  1911. {
  1912. struct tdm_port port;
  1913. int ret = tdm_get_port_idx(kcontrol, &port);
  1914. if (ret) {
  1915. pr_err("%s: unsupported control: %s",
  1916. __func__, kcontrol->id.name);
  1917. } else {
  1918. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1919. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1920. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1921. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1922. ucontrol->value.enumerated.item[0]);
  1923. }
  1924. return ret;
  1925. }
  1926. static int tdm_get_format(int value)
  1927. {
  1928. int format = 0;
  1929. switch (value) {
  1930. case 0:
  1931. format = SNDRV_PCM_FORMAT_S16_LE;
  1932. break;
  1933. case 1:
  1934. format = SNDRV_PCM_FORMAT_S24_LE;
  1935. break;
  1936. case 2:
  1937. format = SNDRV_PCM_FORMAT_S32_LE;
  1938. break;
  1939. default:
  1940. format = SNDRV_PCM_FORMAT_S16_LE;
  1941. break;
  1942. }
  1943. return format;
  1944. }
  1945. static int tdm_get_format_val(int format)
  1946. {
  1947. int value = 0;
  1948. switch (format) {
  1949. case SNDRV_PCM_FORMAT_S16_LE:
  1950. value = 0;
  1951. break;
  1952. case SNDRV_PCM_FORMAT_S24_LE:
  1953. value = 1;
  1954. break;
  1955. case SNDRV_PCM_FORMAT_S32_LE:
  1956. value = 2;
  1957. break;
  1958. default:
  1959. value = 0;
  1960. break;
  1961. }
  1962. return value;
  1963. }
  1964. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1965. struct snd_ctl_elem_value *ucontrol)
  1966. {
  1967. struct tdm_port port;
  1968. int ret = tdm_get_port_idx(kcontrol, &port);
  1969. if (ret) {
  1970. pr_err("%s: unsupported control: %s",
  1971. __func__, kcontrol->id.name);
  1972. } else {
  1973. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1974. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1975. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1976. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1977. ucontrol->value.enumerated.item[0]);
  1978. }
  1979. return ret;
  1980. }
  1981. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1982. struct snd_ctl_elem_value *ucontrol)
  1983. {
  1984. struct tdm_port port;
  1985. int ret = tdm_get_port_idx(kcontrol, &port);
  1986. if (ret) {
  1987. pr_err("%s: unsupported control: %s",
  1988. __func__, kcontrol->id.name);
  1989. } else {
  1990. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1991. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1992. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1993. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1994. ucontrol->value.enumerated.item[0]);
  1995. }
  1996. return ret;
  1997. }
  1998. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1999. struct snd_ctl_elem_value *ucontrol)
  2000. {
  2001. struct tdm_port port;
  2002. int ret = tdm_get_port_idx(kcontrol, &port);
  2003. if (ret) {
  2004. pr_err("%s: unsupported control: %s",
  2005. __func__, kcontrol->id.name);
  2006. } else {
  2007. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2008. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2009. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2010. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2011. ucontrol->value.enumerated.item[0]);
  2012. }
  2013. return ret;
  2014. }
  2015. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2016. struct snd_ctl_elem_value *ucontrol)
  2017. {
  2018. struct tdm_port port;
  2019. int ret = tdm_get_port_idx(kcontrol, &port);
  2020. if (ret) {
  2021. pr_err("%s: unsupported control: %s",
  2022. __func__, kcontrol->id.name);
  2023. } else {
  2024. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2025. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2026. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2027. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2028. ucontrol->value.enumerated.item[0]);
  2029. }
  2030. return ret;
  2031. }
  2032. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2033. struct snd_ctl_elem_value *ucontrol)
  2034. {
  2035. struct tdm_port port;
  2036. int ret = tdm_get_port_idx(kcontrol, &port);
  2037. if (ret) {
  2038. pr_err("%s: unsupported control: %s",
  2039. __func__, kcontrol->id.name);
  2040. } else {
  2041. ucontrol->value.enumerated.item[0] =
  2042. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2043. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2044. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2045. ucontrol->value.enumerated.item[0]);
  2046. }
  2047. return ret;
  2048. }
  2049. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2050. struct snd_ctl_elem_value *ucontrol)
  2051. {
  2052. struct tdm_port port;
  2053. int ret = tdm_get_port_idx(kcontrol, &port);
  2054. if (ret) {
  2055. pr_err("%s: unsupported control: %s",
  2056. __func__, kcontrol->id.name);
  2057. } else {
  2058. tdm_rx_cfg[port.mode][port.channel].channels =
  2059. ucontrol->value.enumerated.item[0] + 1;
  2060. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2061. tdm_rx_cfg[port.mode][port.channel].channels,
  2062. ucontrol->value.enumerated.item[0] + 1);
  2063. }
  2064. return ret;
  2065. }
  2066. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2067. struct snd_ctl_elem_value *ucontrol)
  2068. {
  2069. struct tdm_port port;
  2070. int ret = tdm_get_port_idx(kcontrol, &port);
  2071. if (ret) {
  2072. pr_err("%s: unsupported control: %s",
  2073. __func__, kcontrol->id.name);
  2074. } else {
  2075. ucontrol->value.enumerated.item[0] =
  2076. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2077. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2078. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2079. ucontrol->value.enumerated.item[0]);
  2080. }
  2081. return ret;
  2082. }
  2083. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2084. struct snd_ctl_elem_value *ucontrol)
  2085. {
  2086. struct tdm_port port;
  2087. int ret = tdm_get_port_idx(kcontrol, &port);
  2088. if (ret) {
  2089. pr_err("%s: unsupported control: %s",
  2090. __func__, kcontrol->id.name);
  2091. } else {
  2092. tdm_tx_cfg[port.mode][port.channel].channels =
  2093. ucontrol->value.enumerated.item[0] + 1;
  2094. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2095. tdm_tx_cfg[port.mode][port.channel].channels,
  2096. ucontrol->value.enumerated.item[0] + 1);
  2097. }
  2098. return ret;
  2099. }
  2100. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2101. {
  2102. int idx;
  2103. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2104. sizeof("PRIM_AUX_PCM")))
  2105. idx = PRIM_AUX_PCM;
  2106. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2107. sizeof("SEC_AUX_PCM")))
  2108. idx = SEC_AUX_PCM;
  2109. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2110. sizeof("TERT_AUX_PCM")))
  2111. idx = TERT_AUX_PCM;
  2112. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2113. sizeof("QUAT_AUX_PCM")))
  2114. idx = QUAT_AUX_PCM;
  2115. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2116. sizeof("QUIN_AUX_PCM")))
  2117. idx = QUIN_AUX_PCM;
  2118. else {
  2119. pr_err("%s: unsupported port: %s",
  2120. __func__, kcontrol->id.name);
  2121. idx = -EINVAL;
  2122. }
  2123. return idx;
  2124. }
  2125. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2126. struct snd_ctl_elem_value *ucontrol)
  2127. {
  2128. int idx = aux_pcm_get_port_idx(kcontrol);
  2129. if (idx < 0)
  2130. return idx;
  2131. aux_pcm_rx_cfg[idx].sample_rate =
  2132. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2133. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2134. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2135. ucontrol->value.enumerated.item[0]);
  2136. return 0;
  2137. }
  2138. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2139. struct snd_ctl_elem_value *ucontrol)
  2140. {
  2141. int idx = aux_pcm_get_port_idx(kcontrol);
  2142. if (idx < 0)
  2143. return idx;
  2144. ucontrol->value.enumerated.item[0] =
  2145. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2146. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2147. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2148. ucontrol->value.enumerated.item[0]);
  2149. return 0;
  2150. }
  2151. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2152. struct snd_ctl_elem_value *ucontrol)
  2153. {
  2154. int idx = aux_pcm_get_port_idx(kcontrol);
  2155. if (idx < 0)
  2156. return idx;
  2157. aux_pcm_tx_cfg[idx].sample_rate =
  2158. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2159. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2160. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2161. ucontrol->value.enumerated.item[0]);
  2162. return 0;
  2163. }
  2164. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2165. struct snd_ctl_elem_value *ucontrol)
  2166. {
  2167. int idx = aux_pcm_get_port_idx(kcontrol);
  2168. if (idx < 0)
  2169. return idx;
  2170. ucontrol->value.enumerated.item[0] =
  2171. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2172. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2173. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2174. ucontrol->value.enumerated.item[0]);
  2175. return 0;
  2176. }
  2177. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2178. {
  2179. int idx;
  2180. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2181. sizeof("PRIM_MI2S_RX")))
  2182. idx = PRIM_MI2S;
  2183. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2184. sizeof("SEC_MI2S_RX")))
  2185. idx = SEC_MI2S;
  2186. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2187. sizeof("TERT_MI2S_RX")))
  2188. idx = TERT_MI2S;
  2189. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2190. sizeof("QUAT_MI2S_RX")))
  2191. idx = QUAT_MI2S;
  2192. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2193. sizeof("QUIN_MI2S_RX")))
  2194. idx = QUIN_MI2S;
  2195. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2196. sizeof("PRIM_MI2S_TX")))
  2197. idx = PRIM_MI2S;
  2198. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2199. sizeof("SEC_MI2S_TX")))
  2200. idx = SEC_MI2S;
  2201. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2202. sizeof("TERT_MI2S_TX")))
  2203. idx = TERT_MI2S;
  2204. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2205. sizeof("QUAT_MI2S_TX")))
  2206. idx = QUAT_MI2S;
  2207. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2208. sizeof("QUIN_MI2S_TX")))
  2209. idx = QUIN_MI2S;
  2210. else {
  2211. pr_err("%s: unsupported channel: %s",
  2212. __func__, kcontrol->id.name);
  2213. idx = -EINVAL;
  2214. }
  2215. return idx;
  2216. }
  2217. static int mi2s_get_sample_rate_val(int sample_rate)
  2218. {
  2219. int sample_rate_val;
  2220. switch (sample_rate) {
  2221. case SAMPLING_RATE_8KHZ:
  2222. sample_rate_val = 0;
  2223. break;
  2224. case SAMPLING_RATE_11P025KHZ:
  2225. sample_rate_val = 1;
  2226. break;
  2227. case SAMPLING_RATE_16KHZ:
  2228. sample_rate_val = 2;
  2229. break;
  2230. case SAMPLING_RATE_22P05KHZ:
  2231. sample_rate_val = 3;
  2232. break;
  2233. case SAMPLING_RATE_32KHZ:
  2234. sample_rate_val = 4;
  2235. break;
  2236. case SAMPLING_RATE_44P1KHZ:
  2237. sample_rate_val = 5;
  2238. break;
  2239. case SAMPLING_RATE_48KHZ:
  2240. sample_rate_val = 6;
  2241. break;
  2242. case SAMPLING_RATE_96KHZ:
  2243. sample_rate_val = 7;
  2244. break;
  2245. case SAMPLING_RATE_192KHZ:
  2246. sample_rate_val = 8;
  2247. break;
  2248. default:
  2249. sample_rate_val = 6;
  2250. break;
  2251. }
  2252. return sample_rate_val;
  2253. }
  2254. static int mi2s_get_sample_rate(int value)
  2255. {
  2256. int sample_rate;
  2257. switch (value) {
  2258. case 0:
  2259. sample_rate = SAMPLING_RATE_8KHZ;
  2260. break;
  2261. case 1:
  2262. sample_rate = SAMPLING_RATE_11P025KHZ;
  2263. break;
  2264. case 2:
  2265. sample_rate = SAMPLING_RATE_16KHZ;
  2266. break;
  2267. case 3:
  2268. sample_rate = SAMPLING_RATE_22P05KHZ;
  2269. break;
  2270. case 4:
  2271. sample_rate = SAMPLING_RATE_32KHZ;
  2272. break;
  2273. case 5:
  2274. sample_rate = SAMPLING_RATE_44P1KHZ;
  2275. break;
  2276. case 6:
  2277. sample_rate = SAMPLING_RATE_48KHZ;
  2278. break;
  2279. case 7:
  2280. sample_rate = SAMPLING_RATE_96KHZ;
  2281. break;
  2282. case 8:
  2283. sample_rate = SAMPLING_RATE_192KHZ;
  2284. break;
  2285. default:
  2286. sample_rate = SAMPLING_RATE_48KHZ;
  2287. break;
  2288. }
  2289. return sample_rate;
  2290. }
  2291. static int mi2s_auxpcm_get_format(int value)
  2292. {
  2293. int format;
  2294. switch (value) {
  2295. case 0:
  2296. format = SNDRV_PCM_FORMAT_S16_LE;
  2297. break;
  2298. case 1:
  2299. format = SNDRV_PCM_FORMAT_S24_LE;
  2300. break;
  2301. case 2:
  2302. format = SNDRV_PCM_FORMAT_S24_3LE;
  2303. break;
  2304. case 3:
  2305. format = SNDRV_PCM_FORMAT_S32_LE;
  2306. break;
  2307. default:
  2308. format = SNDRV_PCM_FORMAT_S16_LE;
  2309. break;
  2310. }
  2311. return format;
  2312. }
  2313. static int mi2s_auxpcm_get_format_value(int format)
  2314. {
  2315. int value;
  2316. switch (format) {
  2317. case SNDRV_PCM_FORMAT_S16_LE:
  2318. value = 0;
  2319. break;
  2320. case SNDRV_PCM_FORMAT_S24_LE:
  2321. value = 1;
  2322. break;
  2323. case SNDRV_PCM_FORMAT_S24_3LE:
  2324. value = 2;
  2325. break;
  2326. case SNDRV_PCM_FORMAT_S32_LE:
  2327. value = 3;
  2328. break;
  2329. default:
  2330. value = 0;
  2331. break;
  2332. }
  2333. return value;
  2334. }
  2335. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2336. struct snd_ctl_elem_value *ucontrol)
  2337. {
  2338. int idx = mi2s_get_port_idx(kcontrol);
  2339. if (idx < 0)
  2340. return idx;
  2341. mi2s_rx_cfg[idx].sample_rate =
  2342. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2343. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2344. idx, mi2s_rx_cfg[idx].sample_rate,
  2345. ucontrol->value.enumerated.item[0]);
  2346. return 0;
  2347. }
  2348. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2349. struct snd_ctl_elem_value *ucontrol)
  2350. {
  2351. int idx = mi2s_get_port_idx(kcontrol);
  2352. if (idx < 0)
  2353. return idx;
  2354. ucontrol->value.enumerated.item[0] =
  2355. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2356. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2357. idx, mi2s_rx_cfg[idx].sample_rate,
  2358. ucontrol->value.enumerated.item[0]);
  2359. return 0;
  2360. }
  2361. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2362. struct snd_ctl_elem_value *ucontrol)
  2363. {
  2364. int idx = mi2s_get_port_idx(kcontrol);
  2365. if (idx < 0)
  2366. return idx;
  2367. mi2s_tx_cfg[idx].sample_rate =
  2368. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2369. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2370. idx, mi2s_tx_cfg[idx].sample_rate,
  2371. ucontrol->value.enumerated.item[0]);
  2372. return 0;
  2373. }
  2374. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2375. struct snd_ctl_elem_value *ucontrol)
  2376. {
  2377. int idx = mi2s_get_port_idx(kcontrol);
  2378. if (idx < 0)
  2379. return idx;
  2380. ucontrol->value.enumerated.item[0] =
  2381. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2382. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2383. idx, mi2s_tx_cfg[idx].sample_rate,
  2384. ucontrol->value.enumerated.item[0]);
  2385. return 0;
  2386. }
  2387. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2388. struct snd_ctl_elem_value *ucontrol)
  2389. {
  2390. int idx = mi2s_get_port_idx(kcontrol);
  2391. if (idx < 0)
  2392. return idx;
  2393. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2394. idx, mi2s_rx_cfg[idx].channels);
  2395. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2396. return 0;
  2397. }
  2398. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2399. struct snd_ctl_elem_value *ucontrol)
  2400. {
  2401. int idx = mi2s_get_port_idx(kcontrol);
  2402. if (idx < 0)
  2403. return idx;
  2404. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2405. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2406. idx, mi2s_rx_cfg[idx].channels);
  2407. return 1;
  2408. }
  2409. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2410. struct snd_ctl_elem_value *ucontrol)
  2411. {
  2412. int idx = mi2s_get_port_idx(kcontrol);
  2413. if (idx < 0)
  2414. return idx;
  2415. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2416. idx, mi2s_tx_cfg[idx].channels);
  2417. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2418. return 0;
  2419. }
  2420. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2421. struct snd_ctl_elem_value *ucontrol)
  2422. {
  2423. int idx = mi2s_get_port_idx(kcontrol);
  2424. if (idx < 0)
  2425. return idx;
  2426. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2427. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2428. idx, mi2s_tx_cfg[idx].channels);
  2429. return 1;
  2430. }
  2431. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2432. struct snd_ctl_elem_value *ucontrol)
  2433. {
  2434. int idx = mi2s_get_port_idx(kcontrol);
  2435. if (idx < 0)
  2436. return idx;
  2437. ucontrol->value.enumerated.item[0] =
  2438. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2439. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2440. idx, mi2s_rx_cfg[idx].bit_format,
  2441. ucontrol->value.enumerated.item[0]);
  2442. return 0;
  2443. }
  2444. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2445. struct snd_ctl_elem_value *ucontrol)
  2446. {
  2447. int idx = mi2s_get_port_idx(kcontrol);
  2448. if (idx < 0)
  2449. return idx;
  2450. mi2s_rx_cfg[idx].bit_format =
  2451. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2452. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2453. idx, mi2s_rx_cfg[idx].bit_format,
  2454. ucontrol->value.enumerated.item[0]);
  2455. return 0;
  2456. }
  2457. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2458. struct snd_ctl_elem_value *ucontrol)
  2459. {
  2460. int idx = mi2s_get_port_idx(kcontrol);
  2461. if (idx < 0)
  2462. return idx;
  2463. ucontrol->value.enumerated.item[0] =
  2464. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2465. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2466. idx, mi2s_tx_cfg[idx].bit_format,
  2467. ucontrol->value.enumerated.item[0]);
  2468. return 0;
  2469. }
  2470. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2471. struct snd_ctl_elem_value *ucontrol)
  2472. {
  2473. int idx = mi2s_get_port_idx(kcontrol);
  2474. if (idx < 0)
  2475. return idx;
  2476. mi2s_tx_cfg[idx].bit_format =
  2477. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2478. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2479. idx, mi2s_tx_cfg[idx].bit_format,
  2480. ucontrol->value.enumerated.item[0]);
  2481. return 0;
  2482. }
  2483. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2484. struct snd_ctl_elem_value *ucontrol)
  2485. {
  2486. int idx = aux_pcm_get_port_idx(kcontrol);
  2487. if (idx < 0)
  2488. return idx;
  2489. ucontrol->value.enumerated.item[0] =
  2490. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2491. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2492. idx, aux_pcm_rx_cfg[idx].bit_format,
  2493. ucontrol->value.enumerated.item[0]);
  2494. return 0;
  2495. }
  2496. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2497. struct snd_ctl_elem_value *ucontrol)
  2498. {
  2499. int idx = aux_pcm_get_port_idx(kcontrol);
  2500. if (idx < 0)
  2501. return idx;
  2502. aux_pcm_rx_cfg[idx].bit_format =
  2503. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2504. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2505. idx, aux_pcm_rx_cfg[idx].bit_format,
  2506. ucontrol->value.enumerated.item[0]);
  2507. return 0;
  2508. }
  2509. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2510. struct snd_ctl_elem_value *ucontrol)
  2511. {
  2512. int idx = aux_pcm_get_port_idx(kcontrol);
  2513. if (idx < 0)
  2514. return idx;
  2515. ucontrol->value.enumerated.item[0] =
  2516. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2517. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2518. idx, aux_pcm_tx_cfg[idx].bit_format,
  2519. ucontrol->value.enumerated.item[0]);
  2520. return 0;
  2521. }
  2522. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2523. struct snd_ctl_elem_value *ucontrol)
  2524. {
  2525. int idx = aux_pcm_get_port_idx(kcontrol);
  2526. if (idx < 0)
  2527. return idx;
  2528. aux_pcm_tx_cfg[idx].bit_format =
  2529. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2530. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2531. idx, aux_pcm_tx_cfg[idx].bit_format,
  2532. ucontrol->value.enumerated.item[0]);
  2533. return 0;
  2534. }
  2535. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2536. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2537. slim_rx_ch_get, slim_rx_ch_put),
  2538. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2539. slim_rx_ch_get, slim_rx_ch_put),
  2540. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2541. slim_tx_ch_get, slim_tx_ch_put),
  2542. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2543. slim_tx_ch_get, slim_tx_ch_put),
  2544. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2545. slim_rx_ch_get, slim_rx_ch_put),
  2546. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2547. slim_rx_ch_get, slim_rx_ch_put),
  2548. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2549. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2550. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2551. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2552. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2553. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2554. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2555. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2556. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2557. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2558. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2559. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2560. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2561. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2562. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2563. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2564. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2565. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2566. };
  2567. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2568. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2569. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2570. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2571. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2572. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2573. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2574. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2575. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2576. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2577. va_cdc_dma_tx_0_sample_rate,
  2578. cdc_dma_tx_sample_rate_get,
  2579. cdc_dma_tx_sample_rate_put),
  2580. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2581. va_cdc_dma_tx_1_sample_rate,
  2582. cdc_dma_tx_sample_rate_get,
  2583. cdc_dma_tx_sample_rate_put),
  2584. };
  2585. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2586. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2587. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2588. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2589. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2590. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2591. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2592. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2593. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2594. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2595. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2596. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2597. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2598. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2599. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2600. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2601. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2602. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2603. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2604. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2605. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2606. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2607. wsa_cdc_dma_rx_0_sample_rate,
  2608. cdc_dma_rx_sample_rate_get,
  2609. cdc_dma_rx_sample_rate_put),
  2610. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2611. wsa_cdc_dma_rx_1_sample_rate,
  2612. cdc_dma_rx_sample_rate_get,
  2613. cdc_dma_rx_sample_rate_put),
  2614. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2615. wsa_cdc_dma_tx_0_sample_rate,
  2616. cdc_dma_tx_sample_rate_get,
  2617. cdc_dma_tx_sample_rate_put),
  2618. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2619. wsa_cdc_dma_tx_1_sample_rate,
  2620. cdc_dma_tx_sample_rate_get,
  2621. cdc_dma_tx_sample_rate_put),
  2622. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2623. wsa_cdc_dma_tx_2_sample_rate,
  2624. cdc_dma_tx_sample_rate_get,
  2625. cdc_dma_tx_sample_rate_put),
  2626. };
  2627. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2628. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2629. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2630. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2631. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2632. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2633. proxy_rx_ch_get, proxy_rx_ch_put),
  2634. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2635. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2636. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2637. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2638. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2639. msm_bt_sample_rate_get,
  2640. msm_bt_sample_rate_put),
  2641. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2642. usb_audio_rx_sample_rate_get,
  2643. usb_audio_rx_sample_rate_put),
  2644. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2645. usb_audio_tx_sample_rate_get,
  2646. usb_audio_tx_sample_rate_put),
  2647. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2648. tdm_rx_sample_rate_get,
  2649. tdm_rx_sample_rate_put),
  2650. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2651. tdm_tx_sample_rate_get,
  2652. tdm_tx_sample_rate_put),
  2653. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2654. tdm_rx_format_get,
  2655. tdm_rx_format_put),
  2656. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2657. tdm_tx_format_get,
  2658. tdm_tx_format_put),
  2659. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2660. tdm_rx_ch_get,
  2661. tdm_rx_ch_put),
  2662. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2663. tdm_tx_ch_get,
  2664. tdm_tx_ch_put),
  2665. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2666. tdm_rx_sample_rate_get,
  2667. tdm_rx_sample_rate_put),
  2668. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2669. tdm_tx_sample_rate_get,
  2670. tdm_tx_sample_rate_put),
  2671. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2672. tdm_rx_format_get,
  2673. tdm_rx_format_put),
  2674. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2675. tdm_tx_format_get,
  2676. tdm_tx_format_put),
  2677. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2678. tdm_rx_ch_get,
  2679. tdm_rx_ch_put),
  2680. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2681. tdm_tx_ch_get,
  2682. tdm_tx_ch_put),
  2683. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2684. tdm_rx_sample_rate_get,
  2685. tdm_rx_sample_rate_put),
  2686. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2687. tdm_tx_sample_rate_get,
  2688. tdm_tx_sample_rate_put),
  2689. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2690. tdm_rx_format_get,
  2691. tdm_rx_format_put),
  2692. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2693. tdm_tx_format_get,
  2694. tdm_tx_format_put),
  2695. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2696. tdm_rx_ch_get,
  2697. tdm_rx_ch_put),
  2698. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2699. tdm_tx_ch_get,
  2700. tdm_tx_ch_put),
  2701. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2702. tdm_rx_sample_rate_get,
  2703. tdm_rx_sample_rate_put),
  2704. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2705. tdm_tx_sample_rate_get,
  2706. tdm_tx_sample_rate_put),
  2707. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  2708. tdm_rx_format_get,
  2709. tdm_rx_format_put),
  2710. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  2711. tdm_tx_format_get,
  2712. tdm_tx_format_put),
  2713. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  2714. tdm_rx_ch_get,
  2715. tdm_rx_ch_put),
  2716. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  2717. tdm_tx_ch_get,
  2718. tdm_tx_ch_put),
  2719. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2720. tdm_rx_sample_rate_get,
  2721. tdm_rx_sample_rate_put),
  2722. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2723. tdm_tx_sample_rate_get,
  2724. tdm_tx_sample_rate_put),
  2725. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  2726. tdm_rx_format_get,
  2727. tdm_rx_format_put),
  2728. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  2729. tdm_tx_format_get,
  2730. tdm_tx_format_put),
  2731. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  2732. tdm_rx_ch_get,
  2733. tdm_rx_ch_put),
  2734. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  2735. tdm_tx_ch_get,
  2736. tdm_tx_ch_put),
  2737. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2738. aux_pcm_rx_sample_rate_get,
  2739. aux_pcm_rx_sample_rate_put),
  2740. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2741. aux_pcm_rx_sample_rate_get,
  2742. aux_pcm_rx_sample_rate_put),
  2743. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2744. aux_pcm_rx_sample_rate_get,
  2745. aux_pcm_rx_sample_rate_put),
  2746. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  2747. aux_pcm_rx_sample_rate_get,
  2748. aux_pcm_rx_sample_rate_put),
  2749. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  2750. aux_pcm_rx_sample_rate_get,
  2751. aux_pcm_rx_sample_rate_put),
  2752. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2753. aux_pcm_tx_sample_rate_get,
  2754. aux_pcm_tx_sample_rate_put),
  2755. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2756. aux_pcm_tx_sample_rate_get,
  2757. aux_pcm_tx_sample_rate_put),
  2758. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2759. aux_pcm_tx_sample_rate_get,
  2760. aux_pcm_tx_sample_rate_put),
  2761. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  2762. aux_pcm_tx_sample_rate_get,
  2763. aux_pcm_tx_sample_rate_put),
  2764. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  2765. aux_pcm_tx_sample_rate_get,
  2766. aux_pcm_tx_sample_rate_put),
  2767. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2768. mi2s_rx_sample_rate_get,
  2769. mi2s_rx_sample_rate_put),
  2770. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2771. mi2s_rx_sample_rate_get,
  2772. mi2s_rx_sample_rate_put),
  2773. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2774. mi2s_rx_sample_rate_get,
  2775. mi2s_rx_sample_rate_put),
  2776. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  2777. mi2s_rx_sample_rate_get,
  2778. mi2s_rx_sample_rate_put),
  2779. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  2780. mi2s_rx_sample_rate_get,
  2781. mi2s_rx_sample_rate_put),
  2782. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  2783. mi2s_tx_sample_rate_get,
  2784. mi2s_tx_sample_rate_put),
  2785. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2786. mi2s_tx_sample_rate_get,
  2787. mi2s_tx_sample_rate_put),
  2788. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2789. mi2s_tx_sample_rate_get,
  2790. mi2s_tx_sample_rate_put),
  2791. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  2792. mi2s_tx_sample_rate_get,
  2793. mi2s_tx_sample_rate_put),
  2794. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  2795. mi2s_tx_sample_rate_get,
  2796. mi2s_tx_sample_rate_put),
  2797. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2798. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2799. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2800. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2801. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2802. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2803. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2804. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2805. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2806. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2807. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2808. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2809. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  2810. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2811. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  2812. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2813. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  2814. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2815. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  2816. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2817. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2818. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2819. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2820. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2821. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2822. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2823. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2824. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2825. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2826. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2827. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2828. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2829. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  2830. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2831. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  2832. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2833. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  2834. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2835. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  2836. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2837. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2838. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2839. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2840. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2841. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2842. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2843. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2844. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2845. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2846. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2847. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2848. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2849. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2850. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2851. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2852. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2853. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  2854. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2855. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  2856. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2857. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  2858. msm_snd_vad_cfg_put),
  2859. };
  2860. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  2861. int enable, bool dapm)
  2862. {
  2863. int ret = 0;
  2864. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2865. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  2866. } else {
  2867. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  2868. __func__);
  2869. ret = -EINVAL;
  2870. }
  2871. return ret;
  2872. }
  2873. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  2874. int enable, bool dapm)
  2875. {
  2876. int ret = 0;
  2877. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2878. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  2879. } else {
  2880. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  2881. __func__);
  2882. ret = -EINVAL;
  2883. }
  2884. return ret;
  2885. }
  2886. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  2887. struct snd_kcontrol *kcontrol, int event)
  2888. {
  2889. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2890. pr_debug("%s: event = %d\n", __func__, event);
  2891. switch (event) {
  2892. case SND_SOC_DAPM_PRE_PMU:
  2893. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  2894. case SND_SOC_DAPM_POST_PMD:
  2895. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  2896. }
  2897. return 0;
  2898. }
  2899. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  2900. struct snd_kcontrol *kcontrol, int event)
  2901. {
  2902. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2903. pr_debug("%s: event = %d\n", __func__, event);
  2904. switch (event) {
  2905. case SND_SOC_DAPM_PRE_PMU:
  2906. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  2907. case SND_SOC_DAPM_POST_PMD:
  2908. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  2909. }
  2910. return 0;
  2911. }
  2912. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  2913. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  2914. msm_mclk_event,
  2915. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2916. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  2917. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2918. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  2919. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  2920. };
  2921. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  2922. struct snd_kcontrol *kcontrol, int event)
  2923. {
  2924. struct msm_asoc_mach_data *pdata = NULL;
  2925. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2926. int ret = 0;
  2927. uint32_t dmic_idx;
  2928. int *dmic_gpio_cnt;
  2929. struct device_node *dmic_gpio;
  2930. char *wname;
  2931. wname = strpbrk(w->name, "01234567");
  2932. if (!wname) {
  2933. dev_err(codec->dev, "%s: widget not found\n", __func__);
  2934. return -EINVAL;
  2935. }
  2936. ret = kstrtouint(wname, 10, &dmic_idx);
  2937. if (ret < 0) {
  2938. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  2939. __func__);
  2940. return -EINVAL;
  2941. }
  2942. pdata = snd_soc_card_get_drvdata(codec->component.card);
  2943. switch (dmic_idx) {
  2944. case 0:
  2945. case 1:
  2946. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  2947. dmic_gpio = pdata->dmic_01_gpio_p;
  2948. break;
  2949. case 2:
  2950. case 3:
  2951. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  2952. dmic_gpio = pdata->dmic_23_gpio_p;
  2953. break;
  2954. case 4:
  2955. case 5:
  2956. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  2957. dmic_gpio = pdata->dmic_45_gpio_p;
  2958. break;
  2959. case 6:
  2960. case 7:
  2961. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  2962. dmic_gpio = pdata->dmic_67_gpio_p;
  2963. break;
  2964. default:
  2965. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  2966. __func__);
  2967. return -EINVAL;
  2968. }
  2969. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  2970. __func__, event, dmic_idx, *dmic_gpio_cnt);
  2971. switch (event) {
  2972. case SND_SOC_DAPM_PRE_PMU:
  2973. (*dmic_gpio_cnt)++;
  2974. if (*dmic_gpio_cnt == 1) {
  2975. ret = msm_cdc_pinctrl_select_active_state(
  2976. dmic_gpio);
  2977. if (ret < 0) {
  2978. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  2979. __func__, "dmic_gpio");
  2980. return ret;
  2981. }
  2982. }
  2983. break;
  2984. case SND_SOC_DAPM_POST_PMD:
  2985. (*dmic_gpio_cnt)--;
  2986. if (*dmic_gpio_cnt == 0) {
  2987. ret = msm_cdc_pinctrl_select_sleep_state(
  2988. dmic_gpio);
  2989. if (ret < 0) {
  2990. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  2991. __func__, "dmic_gpio");
  2992. return ret;
  2993. }
  2994. }
  2995. break;
  2996. default:
  2997. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  2998. __func__, event);
  2999. return -EINVAL;
  3000. }
  3001. return 0;
  3002. }
  3003. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3004. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3005. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3006. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3007. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3008. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3009. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3010. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3011. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3012. };
  3013. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3014. };
  3015. static inline int param_is_mask(int p)
  3016. {
  3017. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3018. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3019. }
  3020. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3021. int n)
  3022. {
  3023. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3024. }
  3025. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3026. unsigned int bit)
  3027. {
  3028. if (bit >= SNDRV_MASK_MAX)
  3029. return;
  3030. if (param_is_mask(n)) {
  3031. struct snd_mask *m = param_to_mask(p, n);
  3032. m->bits[0] = 0;
  3033. m->bits[1] = 0;
  3034. m->bits[bit >> 5] |= (1 << (bit & 31));
  3035. }
  3036. }
  3037. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3038. {
  3039. int ch_id = 0;
  3040. switch (be_id) {
  3041. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3042. ch_id = SLIM_RX_0;
  3043. break;
  3044. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3045. ch_id = SLIM_RX_1;
  3046. break;
  3047. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3048. ch_id = SLIM_RX_2;
  3049. break;
  3050. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3051. ch_id = SLIM_RX_3;
  3052. break;
  3053. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3054. ch_id = SLIM_RX_4;
  3055. break;
  3056. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3057. ch_id = SLIM_RX_6;
  3058. break;
  3059. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3060. ch_id = SLIM_TX_0;
  3061. break;
  3062. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3063. ch_id = SLIM_TX_3;
  3064. break;
  3065. default:
  3066. ch_id = SLIM_RX_0;
  3067. break;
  3068. }
  3069. return ch_id;
  3070. }
  3071. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3072. {
  3073. *port_id = 0xFFFF;
  3074. switch (be_id) {
  3075. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3076. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3077. break;
  3078. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3079. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3080. break;
  3081. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3082. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3083. break;
  3084. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3085. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3086. break;
  3087. default:
  3088. return -EINVAL;
  3089. }
  3090. return 0;
  3091. }
  3092. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3093. {
  3094. int idx = 0;
  3095. switch (be_id) {
  3096. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3097. idx = WSA_CDC_DMA_RX_0;
  3098. break;
  3099. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3100. idx = WSA_CDC_DMA_TX_0;
  3101. break;
  3102. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3103. idx = WSA_CDC_DMA_RX_1;
  3104. break;
  3105. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3106. idx = WSA_CDC_DMA_TX_1;
  3107. break;
  3108. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3109. idx = WSA_CDC_DMA_TX_2;
  3110. break;
  3111. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3112. idx = VA_CDC_DMA_TX_0;
  3113. break;
  3114. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3115. idx = VA_CDC_DMA_TX_1;
  3116. break;
  3117. default:
  3118. idx = VA_CDC_DMA_TX_0;
  3119. break;
  3120. }
  3121. return idx;
  3122. }
  3123. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3124. struct snd_pcm_hw_params *params)
  3125. {
  3126. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3127. struct snd_interval *rate = hw_param_interval(params,
  3128. SNDRV_PCM_HW_PARAM_RATE);
  3129. struct snd_interval *channels = hw_param_interval(params,
  3130. SNDRV_PCM_HW_PARAM_CHANNELS);
  3131. int rc = 0;
  3132. int idx;
  3133. void *config = NULL;
  3134. struct snd_soc_codec *codec = NULL;
  3135. pr_debug("%s: format = %d, rate = %d\n",
  3136. __func__, params_format(params), params_rate(params));
  3137. switch (dai_link->id) {
  3138. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3139. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3140. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3141. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3142. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3143. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3144. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3145. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3146. slim_rx_cfg[idx].bit_format);
  3147. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3148. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3149. break;
  3150. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3151. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3152. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3153. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3154. slim_tx_cfg[idx].bit_format);
  3155. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3156. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3157. break;
  3158. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3159. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3160. slim_tx_cfg[1].bit_format);
  3161. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3162. channels->min = channels->max = slim_tx_cfg[1].channels;
  3163. break;
  3164. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3165. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3166. SNDRV_PCM_FORMAT_S32_LE);
  3167. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3168. channels->min = channels->max = msm_vi_feed_tx_ch;
  3169. break;
  3170. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3171. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3172. slim_rx_cfg[5].bit_format);
  3173. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3174. channels->min = channels->max = slim_rx_cfg[5].channels;
  3175. break;
  3176. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3177. codec = rtd->codec;
  3178. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3179. channels->min = channels->max = 1;
  3180. config = msm_codec_fn.get_afe_config_fn(codec,
  3181. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3182. if (config) {
  3183. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3184. config, SLIMBUS_5_TX);
  3185. if (rc)
  3186. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3187. __func__, rc);
  3188. }
  3189. break;
  3190. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3191. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3192. slim_rx_cfg[SLIM_RX_7].bit_format);
  3193. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3194. channels->min = channels->max =
  3195. slim_rx_cfg[SLIM_RX_7].channels;
  3196. break;
  3197. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3198. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3199. channels->min = channels->max =
  3200. slim_tx_cfg[SLIM_TX_7].channels;
  3201. break;
  3202. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3203. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3204. channels->min = channels->max =
  3205. slim_tx_cfg[SLIM_TX_8].channels;
  3206. break;
  3207. case MSM_BACKEND_DAI_USB_RX:
  3208. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3209. usb_rx_cfg.bit_format);
  3210. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3211. channels->min = channels->max = usb_rx_cfg.channels;
  3212. break;
  3213. case MSM_BACKEND_DAI_USB_TX:
  3214. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3215. usb_tx_cfg.bit_format);
  3216. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3217. channels->min = channels->max = usb_tx_cfg.channels;
  3218. break;
  3219. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3220. channels->min = channels->max = proxy_rx_cfg.channels;
  3221. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3222. break;
  3223. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3224. channels->min = channels->max =
  3225. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3226. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3227. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3228. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3229. break;
  3230. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3231. channels->min = channels->max =
  3232. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3233. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3234. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3235. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3236. break;
  3237. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3238. channels->min = channels->max =
  3239. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3240. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3241. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3242. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3243. break;
  3244. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3245. channels->min = channels->max =
  3246. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3247. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3248. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3249. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3250. break;
  3251. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3252. channels->min = channels->max =
  3253. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3254. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3255. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3256. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3257. break;
  3258. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3259. channels->min = channels->max =
  3260. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3261. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3262. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3263. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3264. break;
  3265. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3266. channels->min = channels->max =
  3267. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3268. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3269. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3270. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3271. break;
  3272. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3273. channels->min = channels->max =
  3274. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3275. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3276. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3277. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3278. break;
  3279. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3280. channels->min = channels->max =
  3281. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3282. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3283. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3284. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3285. break;
  3286. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3287. channels->min = channels->max =
  3288. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3289. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3290. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3291. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3292. break;
  3293. case MSM_BACKEND_DAI_AUXPCM_RX:
  3294. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3295. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3296. rate->min = rate->max =
  3297. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3298. channels->min = channels->max =
  3299. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3300. break;
  3301. case MSM_BACKEND_DAI_AUXPCM_TX:
  3302. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3303. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3304. rate->min = rate->max =
  3305. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3306. channels->min = channels->max =
  3307. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3308. break;
  3309. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3310. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3311. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3312. rate->min = rate->max =
  3313. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3314. channels->min = channels->max =
  3315. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3316. break;
  3317. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3318. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3319. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3320. rate->min = rate->max =
  3321. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3322. channels->min = channels->max =
  3323. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3324. break;
  3325. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3326. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3327. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3328. rate->min = rate->max =
  3329. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3330. channels->min = channels->max =
  3331. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3332. break;
  3333. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3334. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3335. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3336. rate->min = rate->max =
  3337. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3338. channels->min = channels->max =
  3339. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3340. break;
  3341. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3342. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3343. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3344. rate->min = rate->max =
  3345. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3346. channels->min = channels->max =
  3347. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3348. break;
  3349. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3350. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3351. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3352. rate->min = rate->max =
  3353. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3354. channels->min = channels->max =
  3355. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3356. break;
  3357. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3358. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3359. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3360. rate->min = rate->max =
  3361. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3362. channels->min = channels->max =
  3363. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3364. break;
  3365. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3366. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3367. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3368. rate->min = rate->max =
  3369. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3370. channels->min = channels->max =
  3371. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3372. break;
  3373. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3374. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3375. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3376. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3377. channels->min = channels->max =
  3378. mi2s_rx_cfg[PRIM_MI2S].channels;
  3379. break;
  3380. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3381. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3382. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3383. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3384. channels->min = channels->max =
  3385. mi2s_tx_cfg[PRIM_MI2S].channels;
  3386. break;
  3387. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3388. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3389. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3390. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3391. channels->min = channels->max =
  3392. mi2s_rx_cfg[SEC_MI2S].channels;
  3393. break;
  3394. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3395. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3396. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3397. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3398. channels->min = channels->max =
  3399. mi2s_tx_cfg[SEC_MI2S].channels;
  3400. break;
  3401. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3402. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3403. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3404. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3405. channels->min = channels->max =
  3406. mi2s_rx_cfg[TERT_MI2S].channels;
  3407. break;
  3408. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3409. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3410. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3411. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3412. channels->min = channels->max =
  3413. mi2s_tx_cfg[TERT_MI2S].channels;
  3414. break;
  3415. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3416. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3417. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3418. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3419. channels->min = channels->max =
  3420. mi2s_rx_cfg[QUAT_MI2S].channels;
  3421. break;
  3422. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3423. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3424. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3425. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3426. channels->min = channels->max =
  3427. mi2s_tx_cfg[QUAT_MI2S].channels;
  3428. break;
  3429. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3430. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3431. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3432. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3433. channels->min = channels->max =
  3434. mi2s_rx_cfg[QUIN_MI2S].channels;
  3435. break;
  3436. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3437. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3438. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3439. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3440. channels->min = channels->max =
  3441. mi2s_tx_cfg[QUIN_MI2S].channels;
  3442. break;
  3443. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3444. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3445. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3446. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3447. cdc_dma_rx_cfg[idx].bit_format);
  3448. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3449. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3450. break;
  3451. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3452. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3453. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3454. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3455. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3456. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3457. cdc_dma_tx_cfg[idx].bit_format);
  3458. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3459. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3460. break;
  3461. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3462. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3463. SNDRV_PCM_FORMAT_S32_LE);
  3464. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3465. channels->min = channels->max = msm_vi_feed_tx_ch;
  3466. break;
  3467. default:
  3468. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3469. break;
  3470. }
  3471. return rc;
  3472. }
  3473. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3474. {
  3475. int ret = 0;
  3476. void *config_data = NULL;
  3477. if (!msm_codec_fn.get_afe_config_fn) {
  3478. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3479. __func__);
  3480. return -EINVAL;
  3481. }
  3482. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3483. AFE_CDC_REGISTERS_CONFIG);
  3484. if (config_data) {
  3485. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3486. if (ret) {
  3487. dev_err(codec->dev,
  3488. "%s: Failed to set codec registers config %d\n",
  3489. __func__, ret);
  3490. return ret;
  3491. }
  3492. }
  3493. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3494. AFE_CDC_REGISTER_PAGE_CONFIG);
  3495. if (config_data) {
  3496. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3497. 0);
  3498. if (ret)
  3499. dev_err(codec->dev,
  3500. "%s: Failed to set cdc register page config\n",
  3501. __func__);
  3502. }
  3503. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3504. AFE_SLIMBUS_SLAVE_CONFIG);
  3505. if (config_data) {
  3506. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3507. if (ret) {
  3508. dev_err(codec->dev,
  3509. "%s: Failed to set slimbus slave config %d\n",
  3510. __func__, ret);
  3511. return ret;
  3512. }
  3513. }
  3514. return 0;
  3515. }
  3516. static void msm_afe_clear_config(void)
  3517. {
  3518. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3519. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3520. }
  3521. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3522. struct snd_card *card)
  3523. {
  3524. int ret = 0;
  3525. unsigned long timeout;
  3526. int adsp_ready = 0;
  3527. bool snd_card_online = 0;
  3528. timeout = jiffies +
  3529. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3530. do {
  3531. if (!snd_card_online) {
  3532. snd_card_online = snd_card_is_online_state(card);
  3533. pr_debug("%s: Sound card is %s\n", __func__,
  3534. snd_card_online ? "Online" : "Offline");
  3535. }
  3536. if (!adsp_ready) {
  3537. adsp_ready = q6core_is_adsp_ready();
  3538. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3539. adsp_ready ? "ready" : "not ready");
  3540. }
  3541. if (snd_card_online && adsp_ready)
  3542. break;
  3543. /*
  3544. * Sound card/ADSP will be coming up after subsystem restart and
  3545. * it might not be fully up when the control reaches
  3546. * here. So, wait for 50msec before checking ADSP state
  3547. */
  3548. msleep(50);
  3549. } while (time_after(timeout, jiffies));
  3550. if (!snd_card_online || !adsp_ready) {
  3551. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3552. __func__,
  3553. snd_card_online ? "Online" : "Offline",
  3554. adsp_ready ? "ready" : "not ready");
  3555. ret = -ETIMEDOUT;
  3556. goto err;
  3557. }
  3558. ret = msm_afe_set_config(codec);
  3559. if (ret)
  3560. pr_err("%s: Failed to set AFE config. err %d\n",
  3561. __func__, ret);
  3562. return 0;
  3563. err:
  3564. return ret;
  3565. }
  3566. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3567. unsigned long opcode, void *ptr)
  3568. {
  3569. int ret;
  3570. struct snd_soc_card *card = NULL;
  3571. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3572. struct snd_soc_pcm_runtime *rtd;
  3573. struct snd_soc_codec *codec;
  3574. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3575. switch (opcode) {
  3576. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3577. /*
  3578. * Use flag to ignore initial boot notifications
  3579. * On initial boot msm_adsp_power_up_config is
  3580. * called on init. There is no need to clear
  3581. * and set the config again on initial boot.
  3582. */
  3583. if (is_initial_boot)
  3584. break;
  3585. msm_afe_clear_config();
  3586. break;
  3587. case AUDIO_NOTIFIER_SERVICE_UP:
  3588. if (is_initial_boot) {
  3589. is_initial_boot = false;
  3590. break;
  3591. }
  3592. if (!spdev)
  3593. return -EINVAL;
  3594. card = platform_get_drvdata(spdev);
  3595. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3596. if (!rtd) {
  3597. dev_err(card->dev,
  3598. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3599. __func__, be_dl_name);
  3600. ret = -EINVAL;
  3601. goto err;
  3602. }
  3603. codec = rtd->codec;
  3604. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3605. if (ret < 0) {
  3606. dev_err(card->dev,
  3607. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3608. __func__, ret);
  3609. goto err;
  3610. }
  3611. break;
  3612. default:
  3613. break;
  3614. }
  3615. err:
  3616. return NOTIFY_OK;
  3617. }
  3618. static struct notifier_block service_nb = {
  3619. .notifier_call = qcs405_notifier_service_cb,
  3620. .priority = -INT_MAX,
  3621. };
  3622. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3623. {
  3624. int ret = 0;
  3625. void *config_data;
  3626. struct snd_soc_codec *codec = rtd->codec;
  3627. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3628. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3629. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3630. struct snd_card *card;
  3631. struct snd_info_entry *entry;
  3632. struct msm_asoc_mach_data *pdata =
  3633. snd_soc_card_get_drvdata(rtd->card);
  3634. /*
  3635. * Codec SLIMBUS configuration
  3636. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  3637. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  3638. * TX14, TX15, TX16
  3639. */
  3640. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  3641. 151, 152, 153, 154, 155, 156};
  3642. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  3643. 134, 135, 136, 137, 138, 139,
  3644. 140, 141, 142, 143};
  3645. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  3646. rtd->pmdown_time = 0;
  3647. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  3648. ARRAY_SIZE(msm_snd_sb_controls));
  3649. if (ret < 0) {
  3650. pr_err("%s: add_codec_controls failed, err %d\n",
  3651. __func__, ret);
  3652. return ret;
  3653. }
  3654. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  3655. ARRAY_SIZE(msm_dapm_widgets));
  3656. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  3657. ARRAY_SIZE(wcd_audio_paths));
  3658. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  3659. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  3660. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3661. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3662. snd_soc_dapm_sync(dapm);
  3663. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3664. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3665. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  3666. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  3667. if (ret) {
  3668. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  3669. __func__, ret);
  3670. goto err;
  3671. }
  3672. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3673. AFE_AANC_VERSION);
  3674. if (config_data) {
  3675. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  3676. if (ret) {
  3677. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  3678. __func__, ret);
  3679. goto err;
  3680. }
  3681. }
  3682. card = rtd->card->snd_card;
  3683. entry = snd_info_create_subdir(card->module, "codecs",
  3684. card->proc_root);
  3685. if (!entry) {
  3686. pr_debug("%s: Cannot create codecs module entry\n",
  3687. __func__);
  3688. ret = 0;
  3689. goto err;
  3690. }
  3691. pdata->codec_root = entry;
  3692. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  3693. codec_reg_done = true;
  3694. return 0;
  3695. err:
  3696. return ret;
  3697. }
  3698. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3699. {
  3700. int ret = 0;
  3701. struct snd_soc_codec *codec = rtd->codec;
  3702. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3703. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  3704. ARRAY_SIZE(msm_snd_va_controls));
  3705. if (ret < 0) {
  3706. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3707. __func__, ret);
  3708. return ret;
  3709. }
  3710. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  3711. ARRAY_SIZE(msm_va_dapm_widgets));
  3712. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3713. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3714. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3715. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3716. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  3717. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  3718. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  3719. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  3720. snd_soc_dapm_sync(dapm);
  3721. return ret;
  3722. }
  3723. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3724. {
  3725. int ret = 0;
  3726. struct snd_soc_codec *codec = rtd->codec;
  3727. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3728. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  3729. ARRAY_SIZE(msm_snd_wsa_controls));
  3730. if (ret < 0) {
  3731. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3732. __func__, ret);
  3733. return ret;
  3734. }
  3735. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  3736. ARRAY_SIZE(msm_wsa_dapm_widgets));
  3737. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  3738. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  3739. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  3740. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  3741. snd_soc_dapm_sync(dapm);
  3742. return ret;
  3743. }
  3744. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3745. {
  3746. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3747. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  3748. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3749. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3750. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3751. }
  3752. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  3753. struct snd_pcm_hw_params *params)
  3754. {
  3755. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3756. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3757. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3758. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3759. int ret = 0;
  3760. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3761. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3762. u32 user_set_tx_ch = 0;
  3763. u32 rx_ch_count;
  3764. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3765. ret = snd_soc_dai_get_channel_map(codec_dai,
  3766. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3767. if (ret < 0) {
  3768. pr_err("%s: failed to get codec chan map, err:%d\n",
  3769. __func__, ret);
  3770. goto err;
  3771. }
  3772. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  3773. pr_debug("%s: rx_5_ch=%d\n", __func__,
  3774. slim_rx_cfg[5].channels);
  3775. rx_ch_count = slim_rx_cfg[5].channels;
  3776. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  3777. pr_debug("%s: rx_2_ch=%d\n", __func__,
  3778. slim_rx_cfg[2].channels);
  3779. rx_ch_count = slim_rx_cfg[2].channels;
  3780. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  3781. pr_debug("%s: rx_6_ch=%d\n", __func__,
  3782. slim_rx_cfg[6].channels);
  3783. rx_ch_count = slim_rx_cfg[6].channels;
  3784. } else {
  3785. pr_debug("%s: rx_0_ch=%d\n", __func__,
  3786. slim_rx_cfg[0].channels);
  3787. rx_ch_count = slim_rx_cfg[0].channels;
  3788. }
  3789. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3790. rx_ch_count, rx_ch);
  3791. if (ret < 0) {
  3792. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3793. __func__, ret);
  3794. goto err;
  3795. }
  3796. } else {
  3797. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  3798. codec_dai->name, codec_dai->id, user_set_tx_ch);
  3799. ret = snd_soc_dai_get_channel_map(codec_dai,
  3800. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3801. if (ret < 0) {
  3802. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3803. __func__, ret);
  3804. goto err;
  3805. }
  3806. /* For <codec>_tx1 case */
  3807. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  3808. user_set_tx_ch = slim_tx_cfg[0].channels;
  3809. /* For <codec>_tx3 case */
  3810. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  3811. user_set_tx_ch = slim_tx_cfg[1].channels;
  3812. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  3813. user_set_tx_ch = msm_vi_feed_tx_ch;
  3814. else
  3815. user_set_tx_ch = tx_ch_cnt;
  3816. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  3817. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  3818. tx_ch_cnt, dai_link->id);
  3819. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3820. user_set_tx_ch, tx_ch, 0, 0);
  3821. if (ret < 0)
  3822. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3823. __func__, ret);
  3824. }
  3825. err:
  3826. return ret;
  3827. }
  3828. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3829. struct snd_pcm_hw_params *params)
  3830. {
  3831. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3832. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3833. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3834. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3835. int ret = 0;
  3836. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3837. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3838. u32 user_set_tx_ch = 0;
  3839. u32 user_set_rx_ch = 0;
  3840. u32 ch_id;
  3841. ret = snd_soc_dai_get_channel_map(codec_dai,
  3842. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3843. &rx_ch_cdc_dma);
  3844. if (ret < 0) {
  3845. pr_err("%s: failed to get codec chan map, err:%d\n",
  3846. __func__, ret);
  3847. goto err;
  3848. }
  3849. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3850. switch (dai_link->id) {
  3851. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3852. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3853. {
  3854. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3855. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3856. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3857. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3858. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3859. user_set_rx_ch, &rx_ch_cdc_dma);
  3860. if (ret < 0) {
  3861. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3862. __func__, ret);
  3863. goto err;
  3864. }
  3865. }
  3866. break;
  3867. }
  3868. } else {
  3869. switch (dai_link->id) {
  3870. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3871. {
  3872. user_set_tx_ch = msm_vi_feed_tx_ch;
  3873. }
  3874. break;
  3875. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3876. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3877. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3878. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3879. {
  3880. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3881. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3882. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3883. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3884. }
  3885. break;
  3886. }
  3887. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3888. &tx_ch_cdc_dma, 0, 0);
  3889. if (ret < 0) {
  3890. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3891. __func__, ret);
  3892. goto err;
  3893. }
  3894. }
  3895. err:
  3896. return ret;
  3897. }
  3898. static int msm_slimbus_2_hw_params(struct snd_pcm_substream *substream,
  3899. struct snd_pcm_hw_params *params)
  3900. {
  3901. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3902. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3903. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3904. unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3905. unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0;
  3906. unsigned int num_tx_ch = 0;
  3907. unsigned int num_rx_ch = 0;
  3908. int ret = 0;
  3909. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3910. num_rx_ch = params_channels(params);
  3911. pr_debug("%s: %s rx_dai_id = %d num_ch = %d\n", __func__,
  3912. codec_dai->name, codec_dai->id, num_rx_ch);
  3913. ret = snd_soc_dai_get_channel_map(codec_dai,
  3914. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3915. if (ret < 0) {
  3916. pr_err("%s: failed to get codec chan map, err:%d\n",
  3917. __func__, ret);
  3918. goto err;
  3919. }
  3920. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3921. num_rx_ch, rx_ch);
  3922. if (ret < 0) {
  3923. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3924. __func__, ret);
  3925. goto err;
  3926. }
  3927. } else {
  3928. num_tx_ch = params_channels(params);
  3929. pr_debug("%s: %s tx_dai_id = %d num_ch = %d\n", __func__,
  3930. codec_dai->name, codec_dai->id, num_tx_ch);
  3931. ret = snd_soc_dai_get_channel_map(codec_dai,
  3932. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3933. if (ret < 0) {
  3934. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3935. __func__, ret);
  3936. goto err;
  3937. }
  3938. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3939. num_tx_ch, tx_ch, 0, 0);
  3940. if (ret < 0) {
  3941. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3942. __func__, ret);
  3943. goto err;
  3944. }
  3945. }
  3946. err:
  3947. return ret;
  3948. }
  3949. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3950. struct snd_pcm_hw_params *params)
  3951. {
  3952. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3953. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3954. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3955. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3956. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3957. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3958. int ret;
  3959. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3960. codec_dai->name, codec_dai->id);
  3961. ret = snd_soc_dai_get_channel_map(codec_dai,
  3962. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3963. if (ret) {
  3964. dev_err(rtd->dev,
  3965. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3966. __func__, ret);
  3967. goto err;
  3968. }
  3969. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3970. __func__, tx_ch_cnt, dai_link->id);
  3971. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3972. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3973. if (ret)
  3974. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3975. __func__, ret);
  3976. err:
  3977. return ret;
  3978. }
  3979. static int msm_get_port_id(int be_id)
  3980. {
  3981. int afe_port_id;
  3982. switch (be_id) {
  3983. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3984. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  3985. break;
  3986. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3987. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  3988. break;
  3989. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3990. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  3991. break;
  3992. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3993. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  3994. break;
  3995. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3996. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  3997. break;
  3998. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3999. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4000. break;
  4001. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4002. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4003. break;
  4004. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4005. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4006. break;
  4007. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4008. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4009. break;
  4010. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4011. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4012. break;
  4013. default:
  4014. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4015. afe_port_id = -EINVAL;
  4016. }
  4017. return afe_port_id;
  4018. }
  4019. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4020. {
  4021. u32 bit_per_sample;
  4022. switch (bit_format) {
  4023. case SNDRV_PCM_FORMAT_S32_LE:
  4024. case SNDRV_PCM_FORMAT_S24_3LE:
  4025. case SNDRV_PCM_FORMAT_S24_LE:
  4026. bit_per_sample = 32;
  4027. break;
  4028. case SNDRV_PCM_FORMAT_S16_LE:
  4029. default:
  4030. bit_per_sample = 16;
  4031. break;
  4032. }
  4033. return bit_per_sample;
  4034. }
  4035. static void update_mi2s_clk_val(int dai_id, int stream)
  4036. {
  4037. u32 bit_per_sample;
  4038. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4039. bit_per_sample =
  4040. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4041. mi2s_clk[dai_id].clk_freq_in_hz =
  4042. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4043. } else {
  4044. bit_per_sample =
  4045. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4046. mi2s_clk[dai_id].clk_freq_in_hz =
  4047. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4048. }
  4049. }
  4050. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4051. {
  4052. int ret = 0;
  4053. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4054. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4055. int port_id = 0;
  4056. int index = cpu_dai->id;
  4057. port_id = msm_get_port_id(rtd->dai_link->id);
  4058. if (port_id < 0) {
  4059. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4060. ret = port_id;
  4061. goto err;
  4062. }
  4063. if (enable) {
  4064. update_mi2s_clk_val(index, substream->stream);
  4065. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4066. mi2s_clk[index].clk_freq_in_hz);
  4067. }
  4068. mi2s_clk[index].enable = enable;
  4069. ret = afe_set_lpass_clock_v2(port_id,
  4070. &mi2s_clk[index]);
  4071. if (ret < 0) {
  4072. dev_err(rtd->card->dev,
  4073. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4074. __func__, port_id, ret);
  4075. goto err;
  4076. }
  4077. err:
  4078. return ret;
  4079. }
  4080. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4081. enum pinctrl_pin_state new_state)
  4082. {
  4083. int ret = 0;
  4084. int curr_state = 0;
  4085. if (pinctrl_info == NULL) {
  4086. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4087. ret = -EINVAL;
  4088. goto err;
  4089. }
  4090. if (pinctrl_info->pinctrl == NULL) {
  4091. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4092. ret = -EINVAL;
  4093. goto err;
  4094. }
  4095. curr_state = pinctrl_info->curr_state;
  4096. pinctrl_info->curr_state = new_state;
  4097. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4098. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4099. if (curr_state == pinctrl_info->curr_state) {
  4100. pr_debug("%s: Already in same state\n", __func__);
  4101. goto err;
  4102. }
  4103. if (curr_state != STATE_DISABLE &&
  4104. pinctrl_info->curr_state != STATE_DISABLE) {
  4105. pr_debug("%s: state already active cannot switch\n", __func__);
  4106. ret = -EIO;
  4107. goto err;
  4108. }
  4109. switch (pinctrl_info->curr_state) {
  4110. case STATE_MI2S_ACTIVE:
  4111. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4112. pinctrl_info->mi2s_active);
  4113. if (ret) {
  4114. pr_err("%s: MI2S state select failed with %d\n",
  4115. __func__, ret);
  4116. ret = -EIO;
  4117. goto err;
  4118. }
  4119. break;
  4120. case STATE_TDM_ACTIVE:
  4121. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4122. pinctrl_info->tdm_active);
  4123. if (ret) {
  4124. pr_err("%s: TDM state select failed with %d\n",
  4125. __func__, ret);
  4126. ret = -EIO;
  4127. goto err;
  4128. }
  4129. break;
  4130. case STATE_DISABLE:
  4131. if (curr_state == STATE_MI2S_ACTIVE) {
  4132. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4133. pinctrl_info->mi2s_disable);
  4134. } else {
  4135. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4136. pinctrl_info->tdm_disable);
  4137. }
  4138. if (ret) {
  4139. pr_err("%s: state disable failed with %d\n",
  4140. __func__, ret);
  4141. ret = -EIO;
  4142. goto err;
  4143. }
  4144. break;
  4145. default:
  4146. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4147. return -EINVAL;
  4148. }
  4149. err:
  4150. return ret;
  4151. }
  4152. static void msm_release_pinctrl(struct platform_device *pdev)
  4153. {
  4154. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4155. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4156. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4157. if (pinctrl_info->pinctrl) {
  4158. devm_pinctrl_put(pinctrl_info->pinctrl);
  4159. pinctrl_info->pinctrl = NULL;
  4160. }
  4161. }
  4162. static int msm_get_pinctrl(struct platform_device *pdev)
  4163. {
  4164. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4165. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4166. struct msm_pinctrl_info *pinctrl_info = NULL;
  4167. struct pinctrl *pinctrl;
  4168. int ret;
  4169. pinctrl_info = &pdata->pinctrl_info;
  4170. if (pinctrl_info == NULL) {
  4171. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4172. return -EINVAL;
  4173. }
  4174. pinctrl = devm_pinctrl_get(&pdev->dev);
  4175. if (IS_ERR_OR_NULL(pinctrl)) {
  4176. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4177. return -EINVAL;
  4178. }
  4179. pinctrl_info->pinctrl = pinctrl;
  4180. /* get all the states handles from Device Tree */
  4181. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4182. "quat-mi2s-sleep");
  4183. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4184. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4185. goto err;
  4186. }
  4187. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4188. "quat-mi2s-active");
  4189. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4190. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4191. goto err;
  4192. }
  4193. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4194. "quat-tdm-sleep");
  4195. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4196. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4197. goto err;
  4198. }
  4199. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4200. "quat-tdm-active");
  4201. if (IS_ERR(pinctrl_info->tdm_active)) {
  4202. pr_err("%s: could not get tdm_active pinstate\n",
  4203. __func__);
  4204. goto err;
  4205. }
  4206. /* Reset the TLMM pins to a default state */
  4207. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4208. pinctrl_info->mi2s_disable);
  4209. if (ret != 0) {
  4210. pr_err("%s: Disable TLMM pins failed with %d\n",
  4211. __func__, ret);
  4212. ret = -EIO;
  4213. goto err;
  4214. }
  4215. pinctrl_info->curr_state = STATE_DISABLE;
  4216. return 0;
  4217. err:
  4218. devm_pinctrl_put(pinctrl);
  4219. pinctrl_info->pinctrl = NULL;
  4220. return -EINVAL;
  4221. }
  4222. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4223. struct snd_pcm_hw_params *params)
  4224. {
  4225. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4226. struct snd_interval *rate = hw_param_interval(params,
  4227. SNDRV_PCM_HW_PARAM_RATE);
  4228. struct snd_interval *channels = hw_param_interval(params,
  4229. SNDRV_PCM_HW_PARAM_CHANNELS);
  4230. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4231. channels->min = channels->max =
  4232. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4233. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4234. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4235. rate->min = rate->max =
  4236. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4237. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4238. channels->min = channels->max =
  4239. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4240. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4241. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4242. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4243. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4244. channels->min = channels->max =
  4245. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4246. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4247. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4248. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4249. } else {
  4250. pr_err("%s: dai id 0x%x not supported\n",
  4251. __func__, cpu_dai->id);
  4252. return -EINVAL;
  4253. }
  4254. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4255. __func__, cpu_dai->id, channels->max, rate->max,
  4256. params_format(params));
  4257. return 0;
  4258. }
  4259. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4260. struct snd_pcm_hw_params *params)
  4261. {
  4262. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4263. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4264. int ret = 0;
  4265. int slot_width = 32;
  4266. int channels, slots;
  4267. unsigned int slot_mask, rate, clk_freq;
  4268. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4269. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4270. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4271. switch (cpu_dai->id) {
  4272. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4273. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4274. break;
  4275. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4276. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4277. break;
  4278. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4279. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4280. break;
  4281. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4282. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4283. break;
  4284. case AFE_PORT_ID_QUINARY_TDM_RX:
  4285. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4286. break;
  4287. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4288. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4289. break;
  4290. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4291. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4292. break;
  4293. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4294. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4295. break;
  4296. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4297. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4298. break;
  4299. case AFE_PORT_ID_QUINARY_TDM_TX:
  4300. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4301. break;
  4302. default:
  4303. pr_err("%s: dai id 0x%x not supported\n",
  4304. __func__, cpu_dai->id);
  4305. return -EINVAL;
  4306. }
  4307. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4308. /*2 slot config - bits 0 and 1 set for the first two slots */
  4309. slot_mask = 0x0000FFFF >> (16-slots);
  4310. channels = slots;
  4311. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4312. __func__, slot_width, slots);
  4313. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4314. slots, slot_width);
  4315. if (ret < 0) {
  4316. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4317. __func__, ret);
  4318. goto end;
  4319. }
  4320. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4321. 0, NULL, channels, slot_offset);
  4322. if (ret < 0) {
  4323. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4324. __func__, ret);
  4325. goto end;
  4326. }
  4327. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4328. /*2 slot config - bits 0 and 1 set for the first two slots */
  4329. slot_mask = 0x0000FFFF >> (16-slots);
  4330. channels = slots;
  4331. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4332. __func__, slot_width, slots);
  4333. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4334. slots, slot_width);
  4335. if (ret < 0) {
  4336. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4337. __func__, ret);
  4338. goto end;
  4339. }
  4340. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4341. channels, slot_offset, 0, NULL);
  4342. if (ret < 0) {
  4343. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4344. __func__, ret);
  4345. goto end;
  4346. }
  4347. } else {
  4348. ret = -EINVAL;
  4349. pr_err("%s: invalid use case, err:%d\n",
  4350. __func__, ret);
  4351. goto end;
  4352. }
  4353. rate = params_rate(params);
  4354. clk_freq = rate * slot_width * slots;
  4355. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4356. if (ret < 0)
  4357. pr_err("%s: failed to set tdm clk, err:%d\n",
  4358. __func__, ret);
  4359. end:
  4360. return ret;
  4361. }
  4362. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4363. {
  4364. int ret = 0;
  4365. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4366. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4367. struct snd_soc_card *card = rtd->card;
  4368. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4369. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4370. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4371. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4372. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4373. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4374. if (ret)
  4375. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4376. __func__, ret);
  4377. }
  4378. return ret;
  4379. }
  4380. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4381. {
  4382. int ret = 0;
  4383. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4384. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4385. struct snd_soc_card *card = rtd->card;
  4386. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4387. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4388. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4389. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4390. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4391. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4392. if (ret)
  4393. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4394. __func__, ret);
  4395. }
  4396. }
  4397. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4398. .hw_params = qcs405_tdm_snd_hw_params,
  4399. .startup = qcs405_tdm_snd_startup,
  4400. .shutdown = qcs405_tdm_snd_shutdown
  4401. };
  4402. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4403. {
  4404. cpumask_t mask;
  4405. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4406. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4407. cpumask_clear(&mask);
  4408. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4409. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4410. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4411. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4412. pm_qos_add_request(&substream->latency_pm_qos_req,
  4413. PM_QOS_CPU_DMA_LATENCY,
  4414. MSM_LL_QOS_VALUE);
  4415. return 0;
  4416. }
  4417. static struct snd_soc_ops msm_fe_qos_ops = {
  4418. .prepare = msm_fe_qos_prepare,
  4419. };
  4420. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4421. {
  4422. int ret = 0;
  4423. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4424. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4425. int index = cpu_dai->id;
  4426. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4427. struct snd_soc_card *card = rtd->card;
  4428. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4429. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4430. int ret_pinctrl = 0;
  4431. dev_dbg(rtd->card->dev,
  4432. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4433. __func__, substream->name, substream->stream,
  4434. cpu_dai->name, cpu_dai->id);
  4435. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4436. ret = -EINVAL;
  4437. dev_err(rtd->card->dev,
  4438. "%s: CPU DAI id (%d) out of range\n",
  4439. __func__, cpu_dai->id);
  4440. goto err;
  4441. }
  4442. /*
  4443. * Mutex protection in case the same MI2S
  4444. * interface using for both TX and RX so
  4445. * that the same clock won't be enable twice.
  4446. */
  4447. mutex_lock(&mi2s_intf_conf[index].lock);
  4448. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4449. /* Check if msm needs to provide the clock to the interface */
  4450. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4451. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4452. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4453. }
  4454. ret = msm_mi2s_set_sclk(substream, true);
  4455. if (ret < 0) {
  4456. dev_err(rtd->card->dev,
  4457. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4458. __func__, ret);
  4459. goto clean_up;
  4460. }
  4461. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4462. if (ret < 0) {
  4463. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4464. __func__, index, ret);
  4465. goto clk_off;
  4466. }
  4467. if (index == QUAT_MI2S) {
  4468. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4469. STATE_MI2S_ACTIVE);
  4470. if (ret_pinctrl)
  4471. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4472. __func__, ret_pinctrl);
  4473. }
  4474. }
  4475. clk_off:
  4476. if (ret < 0)
  4477. msm_mi2s_set_sclk(substream, false);
  4478. clean_up:
  4479. if (ret < 0)
  4480. mi2s_intf_conf[index].ref_cnt--;
  4481. mutex_unlock(&mi2s_intf_conf[index].lock);
  4482. err:
  4483. return ret;
  4484. }
  4485. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4486. {
  4487. int ret;
  4488. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4489. int index = rtd->cpu_dai->id;
  4490. struct snd_soc_card *card = rtd->card;
  4491. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4492. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4493. int ret_pinctrl = 0;
  4494. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4495. substream->name, substream->stream);
  4496. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4497. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4498. return;
  4499. }
  4500. mutex_lock(&mi2s_intf_conf[index].lock);
  4501. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4502. ret = msm_mi2s_set_sclk(substream, false);
  4503. if (ret < 0)
  4504. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4505. __func__, index, ret);
  4506. if (index == QUAT_MI2S) {
  4507. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4508. STATE_DISABLE);
  4509. if (ret_pinctrl)
  4510. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4511. __func__, ret_pinctrl);
  4512. }
  4513. }
  4514. mutex_unlock(&mi2s_intf_conf[index].lock);
  4515. }
  4516. static struct snd_soc_ops msm_mi2s_be_ops = {
  4517. .startup = msm_mi2s_snd_startup,
  4518. .shutdown = msm_mi2s_snd_shutdown,
  4519. };
  4520. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4521. .hw_params = msm_snd_cdc_dma_hw_params,
  4522. };
  4523. static struct snd_soc_ops msm_be_ops = {
  4524. .hw_params = msm_snd_hw_params,
  4525. };
  4526. static struct snd_soc_ops msm_slimbus_2_be_ops = {
  4527. .hw_params = msm_slimbus_2_hw_params,
  4528. };
  4529. static struct snd_soc_ops msm_wcn_ops = {
  4530. .hw_params = msm_wcn_hw_params,
  4531. };
  4532. /* Digital audio interface glue - connects codec <---> CPU */
  4533. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4534. /* FrontEnd DAI Links */
  4535. {
  4536. .name = MSM_DAILINK_NAME(Media1),
  4537. .stream_name = "MultiMedia1",
  4538. .cpu_dai_name = "MultiMedia1",
  4539. .platform_name = "msm-pcm-dsp.0",
  4540. .dynamic = 1,
  4541. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4542. .dpcm_playback = 1,
  4543. .dpcm_capture = 1,
  4544. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4545. SND_SOC_DPCM_TRIGGER_POST},
  4546. .codec_dai_name = "snd-soc-dummy-dai",
  4547. .codec_name = "snd-soc-dummy",
  4548. .ignore_suspend = 1,
  4549. /* this dainlink has playback support */
  4550. .ignore_pmdown_time = 1,
  4551. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4552. },
  4553. {
  4554. .name = MSM_DAILINK_NAME(Media2),
  4555. .stream_name = "MultiMedia2",
  4556. .cpu_dai_name = "MultiMedia2",
  4557. .platform_name = "msm-pcm-dsp.0",
  4558. .dynamic = 1,
  4559. .dpcm_playback = 1,
  4560. .dpcm_capture = 1,
  4561. .codec_dai_name = "snd-soc-dummy-dai",
  4562. .codec_name = "snd-soc-dummy",
  4563. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4564. SND_SOC_DPCM_TRIGGER_POST},
  4565. .ignore_suspend = 1,
  4566. /* this dainlink has playback support */
  4567. .ignore_pmdown_time = 1,
  4568. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4569. },
  4570. {
  4571. .name = "VoiceMMode1",
  4572. .stream_name = "VoiceMMode1",
  4573. .cpu_dai_name = "VoiceMMode1",
  4574. .platform_name = "msm-pcm-voice",
  4575. .dynamic = 1,
  4576. .dpcm_playback = 1,
  4577. .dpcm_capture = 1,
  4578. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4579. SND_SOC_DPCM_TRIGGER_POST},
  4580. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4581. .ignore_suspend = 1,
  4582. .ignore_pmdown_time = 1,
  4583. .codec_dai_name = "snd-soc-dummy-dai",
  4584. .codec_name = "snd-soc-dummy",
  4585. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4586. },
  4587. {
  4588. .name = "MSM VoIP",
  4589. .stream_name = "VoIP",
  4590. .cpu_dai_name = "VoIP",
  4591. .platform_name = "msm-voip-dsp",
  4592. .dynamic = 1,
  4593. .dpcm_playback = 1,
  4594. .dpcm_capture = 1,
  4595. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4596. SND_SOC_DPCM_TRIGGER_POST},
  4597. .codec_dai_name = "snd-soc-dummy-dai",
  4598. .codec_name = "snd-soc-dummy",
  4599. .ignore_suspend = 1,
  4600. /* this dainlink has playback support */
  4601. .ignore_pmdown_time = 1,
  4602. .id = MSM_FRONTEND_DAI_VOIP,
  4603. },
  4604. {
  4605. .name = MSM_DAILINK_NAME(ULL),
  4606. .stream_name = "MultiMedia3",
  4607. .cpu_dai_name = "MultiMedia3",
  4608. .platform_name = "msm-pcm-dsp.2",
  4609. .dynamic = 1,
  4610. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4611. .dpcm_playback = 1,
  4612. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4613. SND_SOC_DPCM_TRIGGER_POST},
  4614. .codec_dai_name = "snd-soc-dummy-dai",
  4615. .codec_name = "snd-soc-dummy",
  4616. .ignore_suspend = 1,
  4617. /* this dainlink has playback support */
  4618. .ignore_pmdown_time = 1,
  4619. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4620. },
  4621. /* Hostless PCM purpose */
  4622. {
  4623. .name = "SLIMBUS_0 Hostless",
  4624. .stream_name = "SLIMBUS_0 Hostless",
  4625. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  4626. .platform_name = "msm-pcm-hostless",
  4627. .dynamic = 1,
  4628. .dpcm_playback = 1,
  4629. .dpcm_capture = 1,
  4630. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4631. SND_SOC_DPCM_TRIGGER_POST},
  4632. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4633. .ignore_suspend = 1,
  4634. /* this dailink has playback support */
  4635. .ignore_pmdown_time = 1,
  4636. .codec_dai_name = "snd-soc-dummy-dai",
  4637. .codec_name = "snd-soc-dummy",
  4638. },
  4639. {
  4640. .name = "MSM AFE-PCM RX",
  4641. .stream_name = "AFE-PROXY RX",
  4642. .cpu_dai_name = "msm-dai-q6-dev.241",
  4643. .codec_name = "msm-stub-codec.1",
  4644. .codec_dai_name = "msm-stub-rx",
  4645. .platform_name = "msm-pcm-afe",
  4646. .dpcm_playback = 1,
  4647. .ignore_suspend = 1,
  4648. /* this dainlink has playback support */
  4649. .ignore_pmdown_time = 1,
  4650. },
  4651. {
  4652. .name = "MSM AFE-PCM TX",
  4653. .stream_name = "AFE-PROXY TX",
  4654. .cpu_dai_name = "msm-dai-q6-dev.240",
  4655. .codec_name = "msm-stub-codec.1",
  4656. .codec_dai_name = "msm-stub-tx",
  4657. .platform_name = "msm-pcm-afe",
  4658. .dpcm_capture = 1,
  4659. .ignore_suspend = 1,
  4660. },
  4661. {
  4662. .name = MSM_DAILINK_NAME(Compress1),
  4663. .stream_name = "Compress1",
  4664. .cpu_dai_name = "MultiMedia4",
  4665. .platform_name = "msm-compress-dsp",
  4666. .dynamic = 1,
  4667. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4668. .dpcm_playback = 1,
  4669. .dpcm_capture = 1,
  4670. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4671. SND_SOC_DPCM_TRIGGER_POST},
  4672. .codec_dai_name = "snd-soc-dummy-dai",
  4673. .codec_name = "snd-soc-dummy",
  4674. .ignore_suspend = 1,
  4675. .ignore_pmdown_time = 1,
  4676. /* this dainlink has playback support */
  4677. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4678. },
  4679. {
  4680. .name = "AUXPCM Hostless",
  4681. .stream_name = "AUXPCM Hostless",
  4682. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4683. .platform_name = "msm-pcm-hostless",
  4684. .dynamic = 1,
  4685. .dpcm_playback = 1,
  4686. .dpcm_capture = 1,
  4687. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4688. SND_SOC_DPCM_TRIGGER_POST},
  4689. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4690. .ignore_suspend = 1,
  4691. /* this dainlink has playback support */
  4692. .ignore_pmdown_time = 1,
  4693. .codec_dai_name = "snd-soc-dummy-dai",
  4694. .codec_name = "snd-soc-dummy",
  4695. },
  4696. {
  4697. .name = "SLIMBUS_1 Hostless",
  4698. .stream_name = "SLIMBUS_1 Hostless",
  4699. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  4700. .platform_name = "msm-pcm-hostless",
  4701. .dynamic = 1,
  4702. .dpcm_playback = 1,
  4703. .dpcm_capture = 1,
  4704. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4705. SND_SOC_DPCM_TRIGGER_POST},
  4706. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4707. .ignore_suspend = 1,
  4708. /* this dailink has playback support */
  4709. .ignore_pmdown_time = 1,
  4710. .codec_dai_name = "snd-soc-dummy-dai",
  4711. .codec_name = "snd-soc-dummy",
  4712. },
  4713. {
  4714. .name = "SLIMBUS_3 Hostless",
  4715. .stream_name = "SLIMBUS_3 Hostless",
  4716. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  4717. .platform_name = "msm-pcm-hostless",
  4718. .dynamic = 1,
  4719. .dpcm_playback = 1,
  4720. .dpcm_capture = 1,
  4721. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4722. SND_SOC_DPCM_TRIGGER_POST},
  4723. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4724. .ignore_suspend = 1,
  4725. /* this dailink has playback support */
  4726. .ignore_pmdown_time = 1,
  4727. .codec_dai_name = "snd-soc-dummy-dai",
  4728. .codec_name = "snd-soc-dummy",
  4729. },
  4730. {
  4731. .name = "SLIMBUS_4 Hostless",
  4732. .stream_name = "SLIMBUS_4 Hostless",
  4733. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  4734. .platform_name = "msm-pcm-hostless",
  4735. .dynamic = 1,
  4736. .dpcm_playback = 1,
  4737. .dpcm_capture = 1,
  4738. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4739. SND_SOC_DPCM_TRIGGER_POST},
  4740. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4741. .ignore_suspend = 1,
  4742. /* this dailink has playback support */
  4743. .ignore_pmdown_time = 1,
  4744. .codec_dai_name = "snd-soc-dummy-dai",
  4745. .codec_name = "snd-soc-dummy",
  4746. },
  4747. {
  4748. .name = MSM_DAILINK_NAME(LowLatency),
  4749. .stream_name = "MultiMedia5",
  4750. .cpu_dai_name = "MultiMedia5",
  4751. .platform_name = "msm-pcm-dsp.1",
  4752. .dynamic = 1,
  4753. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4754. .dpcm_playback = 1,
  4755. .dpcm_capture = 1,
  4756. .codec_dai_name = "snd-soc-dummy-dai",
  4757. .codec_name = "snd-soc-dummy",
  4758. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4759. SND_SOC_DPCM_TRIGGER_POST},
  4760. .ignore_suspend = 1,
  4761. /* this dainlink has playback support */
  4762. .ignore_pmdown_time = 1,
  4763. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4764. .ops = &msm_fe_qos_ops,
  4765. },
  4766. {
  4767. .name = "Listen 1 Audio Service",
  4768. .stream_name = "Listen 1 Audio Service",
  4769. .cpu_dai_name = "LSM1",
  4770. .platform_name = "msm-lsm-client",
  4771. .dynamic = 1,
  4772. .dpcm_capture = 1,
  4773. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4774. SND_SOC_DPCM_TRIGGER_POST },
  4775. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4776. .ignore_suspend = 1,
  4777. .codec_dai_name = "snd-soc-dummy-dai",
  4778. .codec_name = "snd-soc-dummy",
  4779. .id = MSM_FRONTEND_DAI_LSM1,
  4780. },
  4781. /* Multiple Tunnel instances */
  4782. {
  4783. .name = MSM_DAILINK_NAME(Compress2),
  4784. .stream_name = "Compress2",
  4785. .cpu_dai_name = "MultiMedia7",
  4786. .platform_name = "msm-compress-dsp",
  4787. .dynamic = 1,
  4788. .dpcm_playback = 1,
  4789. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4790. SND_SOC_DPCM_TRIGGER_POST},
  4791. .codec_dai_name = "snd-soc-dummy-dai",
  4792. .codec_name = "snd-soc-dummy",
  4793. .ignore_suspend = 1,
  4794. .ignore_pmdown_time = 1,
  4795. /* this dainlink has playback support */
  4796. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4797. },
  4798. {
  4799. .name = MSM_DAILINK_NAME(MultiMedia10),
  4800. .stream_name = "MultiMedia10",
  4801. .cpu_dai_name = "MultiMedia10",
  4802. .platform_name = "msm-pcm-dsp.1",
  4803. .dynamic = 1,
  4804. .dpcm_playback = 1,
  4805. .dpcm_capture = 1,
  4806. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4807. SND_SOC_DPCM_TRIGGER_POST},
  4808. .codec_dai_name = "snd-soc-dummy-dai",
  4809. .codec_name = "snd-soc-dummy",
  4810. .ignore_suspend = 1,
  4811. .ignore_pmdown_time = 1,
  4812. /* this dainlink has playback support */
  4813. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4814. },
  4815. {
  4816. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4817. .stream_name = "MM_NOIRQ",
  4818. .cpu_dai_name = "MultiMedia8",
  4819. .platform_name = "msm-pcm-dsp-noirq",
  4820. .dynamic = 1,
  4821. .dpcm_playback = 1,
  4822. .dpcm_capture = 1,
  4823. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4824. SND_SOC_DPCM_TRIGGER_POST},
  4825. .codec_dai_name = "snd-soc-dummy-dai",
  4826. .codec_name = "snd-soc-dummy",
  4827. .ignore_suspend = 1,
  4828. .ignore_pmdown_time = 1,
  4829. /* this dainlink has playback support */
  4830. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4831. .ops = &msm_fe_qos_ops,
  4832. },
  4833. /* HDMI Hostless */
  4834. {
  4835. .name = "HDMI_RX_HOSTLESS",
  4836. .stream_name = "HDMI_RX_HOSTLESS",
  4837. .cpu_dai_name = "HDMI_HOSTLESS",
  4838. .platform_name = "msm-pcm-hostless",
  4839. .dynamic = 1,
  4840. .dpcm_playback = 1,
  4841. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4842. SND_SOC_DPCM_TRIGGER_POST},
  4843. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4844. .ignore_suspend = 1,
  4845. .ignore_pmdown_time = 1,
  4846. .codec_dai_name = "snd-soc-dummy-dai",
  4847. .codec_name = "snd-soc-dummy",
  4848. },
  4849. {
  4850. .name = "VoiceMMode2",
  4851. .stream_name = "VoiceMMode2",
  4852. .cpu_dai_name = "VoiceMMode2",
  4853. .platform_name = "msm-pcm-voice",
  4854. .dynamic = 1,
  4855. .dpcm_playback = 1,
  4856. .dpcm_capture = 1,
  4857. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4858. SND_SOC_DPCM_TRIGGER_POST},
  4859. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4860. .ignore_suspend = 1,
  4861. .ignore_pmdown_time = 1,
  4862. .codec_dai_name = "snd-soc-dummy-dai",
  4863. .codec_name = "snd-soc-dummy",
  4864. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4865. },
  4866. /* LSM FE */
  4867. {
  4868. .name = "Listen 2 Audio Service",
  4869. .stream_name = "Listen 2 Audio Service",
  4870. .cpu_dai_name = "LSM2",
  4871. .platform_name = "msm-lsm-client",
  4872. .dynamic = 1,
  4873. .dpcm_capture = 1,
  4874. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4875. SND_SOC_DPCM_TRIGGER_POST },
  4876. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4877. .ignore_suspend = 1,
  4878. .codec_dai_name = "snd-soc-dummy-dai",
  4879. .codec_name = "snd-soc-dummy",
  4880. .id = MSM_FRONTEND_DAI_LSM2,
  4881. },
  4882. {
  4883. .name = "Listen 3 Audio Service",
  4884. .stream_name = "Listen 3 Audio Service",
  4885. .cpu_dai_name = "LSM3",
  4886. .platform_name = "msm-lsm-client",
  4887. .dynamic = 1,
  4888. .dpcm_capture = 1,
  4889. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4890. SND_SOC_DPCM_TRIGGER_POST },
  4891. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4892. .ignore_suspend = 1,
  4893. .codec_dai_name = "snd-soc-dummy-dai",
  4894. .codec_name = "snd-soc-dummy",
  4895. .id = MSM_FRONTEND_DAI_LSM3,
  4896. },
  4897. {
  4898. .name = "Listen 4 Audio Service",
  4899. .stream_name = "Listen 4 Audio Service",
  4900. .cpu_dai_name = "LSM4",
  4901. .platform_name = "msm-lsm-client",
  4902. .dynamic = 1,
  4903. .dpcm_capture = 1,
  4904. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4905. SND_SOC_DPCM_TRIGGER_POST },
  4906. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4907. .ignore_suspend = 1,
  4908. .codec_dai_name = "snd-soc-dummy-dai",
  4909. .codec_name = "snd-soc-dummy",
  4910. .id = MSM_FRONTEND_DAI_LSM4,
  4911. },
  4912. {
  4913. .name = "Listen 5 Audio Service",
  4914. .stream_name = "Listen 5 Audio Service",
  4915. .cpu_dai_name = "LSM5",
  4916. .platform_name = "msm-lsm-client",
  4917. .dynamic = 1,
  4918. .dpcm_capture = 1,
  4919. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4920. SND_SOC_DPCM_TRIGGER_POST },
  4921. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4922. .ignore_suspend = 1,
  4923. .codec_dai_name = "snd-soc-dummy-dai",
  4924. .codec_name = "snd-soc-dummy",
  4925. .id = MSM_FRONTEND_DAI_LSM5,
  4926. },
  4927. {
  4928. .name = "Listen 6 Audio Service",
  4929. .stream_name = "Listen 6 Audio Service",
  4930. .cpu_dai_name = "LSM6",
  4931. .platform_name = "msm-lsm-client",
  4932. .dynamic = 1,
  4933. .dpcm_capture = 1,
  4934. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4935. SND_SOC_DPCM_TRIGGER_POST },
  4936. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4937. .ignore_suspend = 1,
  4938. .codec_dai_name = "snd-soc-dummy-dai",
  4939. .codec_name = "snd-soc-dummy",
  4940. .id = MSM_FRONTEND_DAI_LSM6,
  4941. },
  4942. {
  4943. .name = "Listen 7 Audio Service",
  4944. .stream_name = "Listen 7 Audio Service",
  4945. .cpu_dai_name = "LSM7",
  4946. .platform_name = "msm-lsm-client",
  4947. .dynamic = 1,
  4948. .dpcm_capture = 1,
  4949. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4950. SND_SOC_DPCM_TRIGGER_POST },
  4951. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4952. .ignore_suspend = 1,
  4953. .codec_dai_name = "snd-soc-dummy-dai",
  4954. .codec_name = "snd-soc-dummy",
  4955. .id = MSM_FRONTEND_DAI_LSM7,
  4956. },
  4957. {
  4958. .name = "Listen 8 Audio Service",
  4959. .stream_name = "Listen 8 Audio Service",
  4960. .cpu_dai_name = "LSM8",
  4961. .platform_name = "msm-lsm-client",
  4962. .dynamic = 1,
  4963. .dpcm_capture = 1,
  4964. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4965. SND_SOC_DPCM_TRIGGER_POST },
  4966. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4967. .ignore_suspend = 1,
  4968. .codec_dai_name = "snd-soc-dummy-dai",
  4969. .codec_name = "snd-soc-dummy",
  4970. .id = MSM_FRONTEND_DAI_LSM8,
  4971. },
  4972. {
  4973. .name = MSM_DAILINK_NAME(Media9),
  4974. .stream_name = "MultiMedia9",
  4975. .cpu_dai_name = "MultiMedia9",
  4976. .platform_name = "msm-pcm-dsp.0",
  4977. .dynamic = 1,
  4978. .dpcm_playback = 1,
  4979. .dpcm_capture = 1,
  4980. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4981. SND_SOC_DPCM_TRIGGER_POST},
  4982. .codec_dai_name = "snd-soc-dummy-dai",
  4983. .codec_name = "snd-soc-dummy",
  4984. .ignore_suspend = 1,
  4985. /* this dainlink has playback support */
  4986. .ignore_pmdown_time = 1,
  4987. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4988. },
  4989. {
  4990. .name = MSM_DAILINK_NAME(Compress4),
  4991. .stream_name = "Compress4",
  4992. .cpu_dai_name = "MultiMedia11",
  4993. .platform_name = "msm-compress-dsp",
  4994. .dynamic = 1,
  4995. .dpcm_playback = 1,
  4996. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4997. SND_SOC_DPCM_TRIGGER_POST},
  4998. .codec_dai_name = "snd-soc-dummy-dai",
  4999. .codec_name = "snd-soc-dummy",
  5000. .ignore_suspend = 1,
  5001. .ignore_pmdown_time = 1,
  5002. /* this dainlink has playback support */
  5003. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5004. },
  5005. {
  5006. .name = MSM_DAILINK_NAME(Compress5),
  5007. .stream_name = "Compress5",
  5008. .cpu_dai_name = "MultiMedia12",
  5009. .platform_name = "msm-compress-dsp",
  5010. .dynamic = 1,
  5011. .dpcm_playback = 1,
  5012. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5013. SND_SOC_DPCM_TRIGGER_POST},
  5014. .codec_dai_name = "snd-soc-dummy-dai",
  5015. .codec_name = "snd-soc-dummy",
  5016. .ignore_suspend = 1,
  5017. .ignore_pmdown_time = 1,
  5018. /* this dainlink has playback support */
  5019. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5020. },
  5021. {
  5022. .name = MSM_DAILINK_NAME(Compress6),
  5023. .stream_name = "Compress6",
  5024. .cpu_dai_name = "MultiMedia13",
  5025. .platform_name = "msm-compress-dsp",
  5026. .dynamic = 1,
  5027. .dpcm_playback = 1,
  5028. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5029. SND_SOC_DPCM_TRIGGER_POST},
  5030. .codec_dai_name = "snd-soc-dummy-dai",
  5031. .codec_name = "snd-soc-dummy",
  5032. .ignore_suspend = 1,
  5033. .ignore_pmdown_time = 1,
  5034. /* this dainlink has playback support */
  5035. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5036. },
  5037. {
  5038. .name = MSM_DAILINK_NAME(Compress7),
  5039. .stream_name = "Compress7",
  5040. .cpu_dai_name = "MultiMedia14",
  5041. .platform_name = "msm-compress-dsp",
  5042. .dynamic = 1,
  5043. .dpcm_playback = 1,
  5044. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5045. SND_SOC_DPCM_TRIGGER_POST},
  5046. .codec_dai_name = "snd-soc-dummy-dai",
  5047. .codec_name = "snd-soc-dummy",
  5048. .ignore_suspend = 1,
  5049. .ignore_pmdown_time = 1,
  5050. /* this dainlink has playback support */
  5051. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5052. },
  5053. {
  5054. .name = MSM_DAILINK_NAME(Compress8),
  5055. .stream_name = "Compress8",
  5056. .cpu_dai_name = "MultiMedia15",
  5057. .platform_name = "msm-compress-dsp",
  5058. .dynamic = 1,
  5059. .dpcm_playback = 1,
  5060. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5061. SND_SOC_DPCM_TRIGGER_POST},
  5062. .codec_dai_name = "snd-soc-dummy-dai",
  5063. .codec_name = "snd-soc-dummy",
  5064. .ignore_suspend = 1,
  5065. .ignore_pmdown_time = 1,
  5066. /* this dainlink has playback support */
  5067. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5068. },
  5069. {
  5070. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5071. .stream_name = "MM_NOIRQ_2",
  5072. .cpu_dai_name = "MultiMedia16",
  5073. .platform_name = "msm-pcm-dsp-noirq",
  5074. .dynamic = 1,
  5075. .dpcm_playback = 1,
  5076. .dpcm_capture = 1,
  5077. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5078. SND_SOC_DPCM_TRIGGER_POST},
  5079. .codec_dai_name = "snd-soc-dummy-dai",
  5080. .codec_name = "snd-soc-dummy",
  5081. .ignore_suspend = 1,
  5082. .ignore_pmdown_time = 1,
  5083. /* this dainlink has playback support */
  5084. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5085. },
  5086. {
  5087. .name = "SLIMBUS_8 Hostless",
  5088. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5089. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5090. .platform_name = "msm-pcm-hostless",
  5091. .dynamic = 1,
  5092. .dpcm_capture = 1,
  5093. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5094. SND_SOC_DPCM_TRIGGER_POST},
  5095. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5096. .ignore_suspend = 1,
  5097. .codec_dai_name = "snd-soc-dummy-dai",
  5098. .codec_name = "snd-soc-dummy",
  5099. },
  5100. };
  5101. static struct snd_soc_dai_link msm_tasha_fe_dai_links[] = {
  5102. /* Ultrasound RX DAI Link */
  5103. {
  5104. .name = "SLIMBUS_2 Hostless Playback",
  5105. .stream_name = "SLIMBUS_2 Hostless Playback",
  5106. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5107. .platform_name = "msm-pcm-hostless",
  5108. .codec_name = "tasha_codec",
  5109. .codec_dai_name = "tasha_rx2",
  5110. .ignore_suspend = 1,
  5111. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5112. .ops = &msm_slimbus_2_be_ops,
  5113. },
  5114. /* Ultrasound TX DAI Link */
  5115. {
  5116. .name = "SLIMBUS_2 Hostless Capture",
  5117. .stream_name = "SLIMBUS_2 Hostless Capture",
  5118. .cpu_dai_name = "msm-dai-q6-dev.16389",
  5119. .platform_name = "msm-pcm-hostless",
  5120. .codec_name = "tasha_codec",
  5121. .codec_dai_name = "tasha_tx2",
  5122. .ignore_suspend = 1,
  5123. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5124. .ops = &msm_slimbus_2_be_ops,
  5125. },
  5126. {
  5127. .name = "SLIMBUS_6 Hostless Playback",
  5128. .stream_name = "SLIMBUS_6 Hostless",
  5129. .cpu_dai_name = "SLIMBUS6_HOSTLESS",
  5130. .platform_name = "msm-pcm-hostless",
  5131. .dynamic = 1,
  5132. .dpcm_playback = 1,
  5133. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5134. SND_SOC_DPCM_TRIGGER_POST},
  5135. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5136. .ignore_suspend = 1,
  5137. /* this dailink has playback support */
  5138. .ignore_pmdown_time = 1,
  5139. .codec_dai_name = "snd-soc-dummy-dai",
  5140. .codec_name = "snd-soc-dummy",
  5141. },
  5142. };
  5143. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5144. {
  5145. .name = MSM_DAILINK_NAME(ASM Loopback),
  5146. .stream_name = "MultiMedia6",
  5147. .cpu_dai_name = "MultiMedia6",
  5148. .platform_name = "msm-pcm-loopback",
  5149. .dynamic = 1,
  5150. .dpcm_playback = 1,
  5151. .dpcm_capture = 1,
  5152. .codec_dai_name = "snd-soc-dummy-dai",
  5153. .codec_name = "snd-soc-dummy",
  5154. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5155. SND_SOC_DPCM_TRIGGER_POST},
  5156. .ignore_suspend = 1,
  5157. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5158. .ignore_pmdown_time = 1,
  5159. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5160. },
  5161. {
  5162. .name = "USB Audio Hostless",
  5163. .stream_name = "USB Audio Hostless",
  5164. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5165. .platform_name = "msm-pcm-hostless",
  5166. .dynamic = 1,
  5167. .dpcm_playback = 1,
  5168. .dpcm_capture = 1,
  5169. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5170. SND_SOC_DPCM_TRIGGER_POST},
  5171. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5172. .ignore_suspend = 1,
  5173. .ignore_pmdown_time = 1,
  5174. .codec_dai_name = "snd-soc-dummy-dai",
  5175. .codec_name = "snd-soc-dummy",
  5176. },
  5177. {
  5178. .name = "SLIMBUS_7 Hostless",
  5179. .stream_name = "SLIMBUS_7 Hostless",
  5180. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5181. .platform_name = "msm-pcm-hostless",
  5182. .dynamic = 1,
  5183. .dpcm_capture = 1,
  5184. .dpcm_playback = 1,
  5185. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5186. SND_SOC_DPCM_TRIGGER_POST},
  5187. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5188. .ignore_suspend = 1,
  5189. .ignore_pmdown_time = 1,
  5190. .codec_dai_name = "snd-soc-dummy-dai",
  5191. .codec_name = "snd-soc-dummy",
  5192. },
  5193. };
  5194. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5195. /* Backend AFE DAI Links */
  5196. {
  5197. .name = LPASS_BE_AFE_PCM_RX,
  5198. .stream_name = "AFE Playback",
  5199. .cpu_dai_name = "msm-dai-q6-dev.224",
  5200. .platform_name = "msm-pcm-routing",
  5201. .codec_name = "msm-stub-codec.1",
  5202. .codec_dai_name = "msm-stub-rx",
  5203. .no_pcm = 1,
  5204. .dpcm_playback = 1,
  5205. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5206. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5207. /* this dainlink has playback support */
  5208. .ignore_pmdown_time = 1,
  5209. .ignore_suspend = 1,
  5210. },
  5211. {
  5212. .name = LPASS_BE_AFE_PCM_TX,
  5213. .stream_name = "AFE Capture",
  5214. .cpu_dai_name = "msm-dai-q6-dev.225",
  5215. .platform_name = "msm-pcm-routing",
  5216. .codec_name = "msm-stub-codec.1",
  5217. .codec_dai_name = "msm-stub-tx",
  5218. .no_pcm = 1,
  5219. .dpcm_capture = 1,
  5220. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5221. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5222. .ignore_suspend = 1,
  5223. },
  5224. /* Incall Record Uplink BACK END DAI Link */
  5225. {
  5226. .name = LPASS_BE_INCALL_RECORD_TX,
  5227. .stream_name = "Voice Uplink Capture",
  5228. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5229. .platform_name = "msm-pcm-routing",
  5230. .codec_name = "msm-stub-codec.1",
  5231. .codec_dai_name = "msm-stub-tx",
  5232. .no_pcm = 1,
  5233. .dpcm_capture = 1,
  5234. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5235. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5236. .ignore_suspend = 1,
  5237. },
  5238. /* Incall Record Downlink BACK END DAI Link */
  5239. {
  5240. .name = LPASS_BE_INCALL_RECORD_RX,
  5241. .stream_name = "Voice Downlink Capture",
  5242. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5243. .platform_name = "msm-pcm-routing",
  5244. .codec_name = "msm-stub-codec.1",
  5245. .codec_dai_name = "msm-stub-tx",
  5246. .no_pcm = 1,
  5247. .dpcm_capture = 1,
  5248. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5249. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5250. .ignore_suspend = 1,
  5251. },
  5252. /* Incall Music BACK END DAI Link */
  5253. {
  5254. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5255. .stream_name = "Voice Farend Playback",
  5256. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5257. .platform_name = "msm-pcm-routing",
  5258. .codec_name = "msm-stub-codec.1",
  5259. .codec_dai_name = "msm-stub-rx",
  5260. .no_pcm = 1,
  5261. .dpcm_playback = 1,
  5262. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5263. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5264. .ignore_suspend = 1,
  5265. .ignore_pmdown_time = 1,
  5266. },
  5267. /* Incall Music 2 BACK END DAI Link */
  5268. {
  5269. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5270. .stream_name = "Voice2 Farend Playback",
  5271. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5272. .platform_name = "msm-pcm-routing",
  5273. .codec_name = "msm-stub-codec.1",
  5274. .codec_dai_name = "msm-stub-rx",
  5275. .no_pcm = 1,
  5276. .dpcm_playback = 1,
  5277. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5278. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5279. .ignore_suspend = 1,
  5280. .ignore_pmdown_time = 1,
  5281. },
  5282. {
  5283. .name = LPASS_BE_USB_AUDIO_RX,
  5284. .stream_name = "USB Audio Playback",
  5285. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5286. .platform_name = "msm-pcm-routing",
  5287. .codec_name = "msm-stub-codec.1",
  5288. .codec_dai_name = "msm-stub-rx",
  5289. .no_pcm = 1,
  5290. .dpcm_playback = 1,
  5291. .id = MSM_BACKEND_DAI_USB_RX,
  5292. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5293. .ignore_pmdown_time = 1,
  5294. .ignore_suspend = 1,
  5295. },
  5296. {
  5297. .name = LPASS_BE_USB_AUDIO_TX,
  5298. .stream_name = "USB Audio Capture",
  5299. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5300. .platform_name = "msm-pcm-routing",
  5301. .codec_name = "msm-stub-codec.1",
  5302. .codec_dai_name = "msm-stub-tx",
  5303. .no_pcm = 1,
  5304. .dpcm_capture = 1,
  5305. .id = MSM_BACKEND_DAI_USB_TX,
  5306. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5307. .ignore_suspend = 1,
  5308. },
  5309. {
  5310. .name = LPASS_BE_PRI_TDM_RX_0,
  5311. .stream_name = "Primary TDM0 Playback",
  5312. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5313. .platform_name = "msm-pcm-routing",
  5314. .codec_name = "msm-stub-codec.1",
  5315. .codec_dai_name = "msm-stub-rx",
  5316. .no_pcm = 1,
  5317. .dpcm_playback = 1,
  5318. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5319. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5320. .ops = &qcs405_tdm_be_ops,
  5321. .ignore_suspend = 1,
  5322. .ignore_pmdown_time = 1,
  5323. },
  5324. {
  5325. .name = LPASS_BE_PRI_TDM_TX_0,
  5326. .stream_name = "Primary TDM0 Capture",
  5327. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5328. .platform_name = "msm-pcm-routing",
  5329. .codec_name = "msm-stub-codec.1",
  5330. .codec_dai_name = "msm-stub-tx",
  5331. .no_pcm = 1,
  5332. .dpcm_capture = 1,
  5333. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5334. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5335. .ops = &qcs405_tdm_be_ops,
  5336. .ignore_suspend = 1,
  5337. },
  5338. {
  5339. .name = LPASS_BE_SEC_TDM_RX_0,
  5340. .stream_name = "Secondary TDM0 Playback",
  5341. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5342. .platform_name = "msm-pcm-routing",
  5343. .codec_name = "msm-stub-codec.1",
  5344. .codec_dai_name = "msm-stub-rx",
  5345. .no_pcm = 1,
  5346. .dpcm_playback = 1,
  5347. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5348. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5349. .ops = &qcs405_tdm_be_ops,
  5350. .ignore_suspend = 1,
  5351. .ignore_pmdown_time = 1,
  5352. },
  5353. {
  5354. .name = LPASS_BE_SEC_TDM_TX_0,
  5355. .stream_name = "Secondary TDM0 Capture",
  5356. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5357. .platform_name = "msm-pcm-routing",
  5358. .codec_name = "msm-stub-codec.1",
  5359. .codec_dai_name = "msm-stub-tx",
  5360. .no_pcm = 1,
  5361. .dpcm_capture = 1,
  5362. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5363. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5364. .ops = &qcs405_tdm_be_ops,
  5365. .ignore_suspend = 1,
  5366. },
  5367. {
  5368. .name = LPASS_BE_TERT_TDM_RX_0,
  5369. .stream_name = "Tertiary TDM0 Playback",
  5370. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5371. .platform_name = "msm-pcm-routing",
  5372. .codec_name = "msm-stub-codec.1",
  5373. .codec_dai_name = "msm-stub-rx",
  5374. .no_pcm = 1,
  5375. .dpcm_playback = 1,
  5376. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5377. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5378. .ops = &qcs405_tdm_be_ops,
  5379. .ignore_suspend = 1,
  5380. .ignore_pmdown_time = 1,
  5381. },
  5382. {
  5383. .name = LPASS_BE_TERT_TDM_TX_0,
  5384. .stream_name = "Tertiary TDM0 Capture",
  5385. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5386. .platform_name = "msm-pcm-routing",
  5387. .codec_name = "msm-stub-codec.1",
  5388. .codec_dai_name = "msm-stub-tx",
  5389. .no_pcm = 1,
  5390. .dpcm_capture = 1,
  5391. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5392. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5393. .ops = &qcs405_tdm_be_ops,
  5394. .ignore_suspend = 1,
  5395. },
  5396. {
  5397. .name = LPASS_BE_QUAT_TDM_RX_0,
  5398. .stream_name = "Quaternary TDM0 Playback",
  5399. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5400. .platform_name = "msm-pcm-routing",
  5401. .codec_name = "msm-stub-codec.1",
  5402. .codec_dai_name = "msm-stub-rx",
  5403. .no_pcm = 1,
  5404. .dpcm_playback = 1,
  5405. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5406. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5407. .ops = &qcs405_tdm_be_ops,
  5408. .ignore_suspend = 1,
  5409. .ignore_pmdown_time = 1,
  5410. },
  5411. {
  5412. .name = LPASS_BE_QUAT_TDM_TX_0,
  5413. .stream_name = "Quaternary TDM0 Capture",
  5414. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5415. .platform_name = "msm-pcm-routing",
  5416. .codec_name = "msm-stub-codec.1",
  5417. .codec_dai_name = "msm-stub-tx",
  5418. .no_pcm = 1,
  5419. .dpcm_capture = 1,
  5420. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5421. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5422. .ops = &qcs405_tdm_be_ops,
  5423. .ignore_suspend = 1,
  5424. },
  5425. };
  5426. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5427. {
  5428. .name = LPASS_BE_SLIMBUS_0_RX,
  5429. .stream_name = "Slimbus Playback",
  5430. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5431. .platform_name = "msm-pcm-routing",
  5432. .codec_name = "tasha_codec",
  5433. .codec_dai_name = "tasha_rx1",
  5434. .no_pcm = 1,
  5435. .dpcm_playback = 1,
  5436. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5437. .init = &msm_audrx_init,
  5438. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5439. /* this dainlink has playback support */
  5440. .ignore_pmdown_time = 1,
  5441. .ignore_suspend = 1,
  5442. .ops = &msm_be_ops,
  5443. },
  5444. {
  5445. .name = LPASS_BE_SLIMBUS_0_TX,
  5446. .stream_name = "Slimbus Capture",
  5447. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5448. .platform_name = "msm-pcm-routing",
  5449. .codec_name = "tasha_codec",
  5450. .codec_dai_name = "tasha_tx1",
  5451. .no_pcm = 1,
  5452. .dpcm_capture = 1,
  5453. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5454. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5455. .ignore_suspend = 1,
  5456. .ops = &msm_be_ops,
  5457. },
  5458. {
  5459. .name = LPASS_BE_SLIMBUS_1_RX,
  5460. .stream_name = "Slimbus1 Playback",
  5461. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5462. .platform_name = "msm-pcm-routing",
  5463. .codec_name = "tasha_codec",
  5464. .codec_dai_name = "tasha_rx1",
  5465. .no_pcm = 1,
  5466. .dpcm_playback = 1,
  5467. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5468. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5469. .ops = &msm_be_ops,
  5470. /* dai link has playback support */
  5471. .ignore_pmdown_time = 1,
  5472. .ignore_suspend = 1,
  5473. },
  5474. {
  5475. .name = LPASS_BE_SLIMBUS_1_TX,
  5476. .stream_name = "Slimbus1 Capture",
  5477. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5478. .platform_name = "msm-pcm-routing",
  5479. .codec_name = "tasha_codec",
  5480. .codec_dai_name = "tasha_tx3",
  5481. .no_pcm = 1,
  5482. .dpcm_capture = 1,
  5483. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5484. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5485. .ops = &msm_be_ops,
  5486. .ignore_suspend = 1,
  5487. },
  5488. {
  5489. .name = LPASS_BE_SLIMBUS_2_RX,
  5490. .stream_name = "Slimbus2 Playback",
  5491. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5492. .platform_name = "msm-pcm-routing",
  5493. .codec_name = "tasha_codec",
  5494. .codec_dai_name = "tasha_rx2",
  5495. .no_pcm = 1,
  5496. .dpcm_playback = 1,
  5497. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  5498. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5499. .ops = &msm_be_ops,
  5500. .ignore_pmdown_time = 1,
  5501. .ignore_suspend = 1,
  5502. },
  5503. {
  5504. .name = LPASS_BE_SLIMBUS_3_RX,
  5505. .stream_name = "Slimbus3 Playback",
  5506. .cpu_dai_name = "msm-dai-q6-dev.16390",
  5507. .platform_name = "msm-pcm-routing",
  5508. .codec_name = "tasha_codec",
  5509. .codec_dai_name = "tasha_rx1",
  5510. .no_pcm = 1,
  5511. .dpcm_playback = 1,
  5512. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  5513. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5514. .ops = &msm_be_ops,
  5515. /* dai link has playback support */
  5516. .ignore_pmdown_time = 1,
  5517. .ignore_suspend = 1,
  5518. },
  5519. {
  5520. .name = LPASS_BE_SLIMBUS_3_TX,
  5521. .stream_name = "Slimbus3 Capture",
  5522. .cpu_dai_name = "msm-dai-q6-dev.16391",
  5523. .platform_name = "msm-pcm-routing",
  5524. .codec_name = "tasha_codec",
  5525. .codec_dai_name = "tasha_tx1",
  5526. .no_pcm = 1,
  5527. .dpcm_capture = 1,
  5528. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  5529. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5530. .ops = &msm_be_ops,
  5531. .ignore_suspend = 1,
  5532. },
  5533. {
  5534. .name = LPASS_BE_SLIMBUS_4_RX,
  5535. .stream_name = "Slimbus4 Playback",
  5536. .cpu_dai_name = "msm-dai-q6-dev.16392",
  5537. .platform_name = "msm-pcm-routing",
  5538. .codec_name = "tasha_codec",
  5539. .codec_dai_name = "tasha_rx1",
  5540. .no_pcm = 1,
  5541. .dpcm_playback = 1,
  5542. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  5543. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5544. .ops = &msm_be_ops,
  5545. /* dai link has playback support */
  5546. .ignore_pmdown_time = 1,
  5547. .ignore_suspend = 1,
  5548. },
  5549. {
  5550. .name = LPASS_BE_SLIMBUS_5_RX,
  5551. .stream_name = "Slimbus5 Playback",
  5552. .cpu_dai_name = "msm-dai-q6-dev.16394",
  5553. .platform_name = "msm-pcm-routing",
  5554. .codec_name = "tasha_codec",
  5555. .codec_dai_name = "tasha_rx3",
  5556. .no_pcm = 1,
  5557. .dpcm_playback = 1,
  5558. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  5559. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5560. .ops = &msm_be_ops,
  5561. /* dai link has playback support */
  5562. .ignore_pmdown_time = 1,
  5563. .ignore_suspend = 1,
  5564. },
  5565. {
  5566. .name = LPASS_BE_SLIMBUS_6_RX,
  5567. .stream_name = "Slimbus6 Playback",
  5568. .cpu_dai_name = "msm-dai-q6-dev.16396",
  5569. .platform_name = "msm-pcm-routing",
  5570. .codec_name = "tasha_codec",
  5571. .codec_dai_name = "tasha_rx4",
  5572. .no_pcm = 1,
  5573. .dpcm_playback = 1,
  5574. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  5575. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5576. .ops = &msm_be_ops,
  5577. /* dai link has playback support */
  5578. .ignore_pmdown_time = 1,
  5579. .ignore_suspend = 1,
  5580. },
  5581. /* Slimbus VI Recording */
  5582. {
  5583. .name = LPASS_BE_SLIMBUS_TX_VI,
  5584. .stream_name = "Slimbus4 Capture",
  5585. .cpu_dai_name = "msm-dai-q6-dev.16393",
  5586. .platform_name = "msm-pcm-routing",
  5587. .codec_name = "tasha_codec",
  5588. .codec_dai_name = "tasha_vifeedback",
  5589. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  5590. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5591. .ops = &msm_be_ops,
  5592. .ignore_suspend = 1,
  5593. .no_pcm = 1,
  5594. .dpcm_capture = 1,
  5595. .ignore_pmdown_time = 1,
  5596. },
  5597. };
  5598. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5599. {
  5600. .name = LPASS_BE_SLIMBUS_7_RX,
  5601. .stream_name = "Slimbus7 Playback",
  5602. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5603. .platform_name = "msm-pcm-routing",
  5604. .codec_name = "btfmslim_slave",
  5605. /* BT codec driver determines capabilities based on
  5606. * dai name, bt codecdai name should always contains
  5607. * supported usecase information
  5608. */
  5609. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5610. .no_pcm = 1,
  5611. .dpcm_playback = 1,
  5612. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5613. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5614. .ops = &msm_wcn_ops,
  5615. /* dai link has playback support */
  5616. .ignore_pmdown_time = 1,
  5617. .ignore_suspend = 1,
  5618. },
  5619. {
  5620. .name = LPASS_BE_SLIMBUS_7_TX,
  5621. .stream_name = "Slimbus7 Capture",
  5622. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5623. .platform_name = "msm-pcm-routing",
  5624. .codec_name = "btfmslim_slave",
  5625. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5626. .no_pcm = 1,
  5627. .dpcm_capture = 1,
  5628. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5629. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5630. .ops = &msm_wcn_ops,
  5631. .ignore_suspend = 1,
  5632. },
  5633. {
  5634. .name = LPASS_BE_SLIMBUS_8_TX,
  5635. .stream_name = "Slimbus8 Capture",
  5636. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5637. .platform_name = "msm-pcm-routing",
  5638. .codec_name = "btfmslim_slave",
  5639. .codec_dai_name = "btfm_fm_slim_tx",
  5640. .no_pcm = 1,
  5641. .dpcm_capture = 1,
  5642. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5643. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5644. .init = &msm_wcn_init,
  5645. .ops = &msm_wcn_ops,
  5646. .ignore_suspend = 1,
  5647. },
  5648. };
  5649. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5650. {
  5651. .name = LPASS_BE_PRI_MI2S_RX,
  5652. .stream_name = "Primary MI2S Playback",
  5653. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5654. .platform_name = "msm-pcm-routing",
  5655. .codec_name = "msm-stub-codec.1",
  5656. .codec_dai_name = "msm-stub-rx",
  5657. .no_pcm = 1,
  5658. .dpcm_playback = 1,
  5659. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5660. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5661. .ops = &msm_mi2s_be_ops,
  5662. .ignore_suspend = 1,
  5663. .ignore_pmdown_time = 1,
  5664. },
  5665. {
  5666. .name = LPASS_BE_PRI_MI2S_TX,
  5667. .stream_name = "Primary MI2S Capture",
  5668. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5669. .platform_name = "msm-pcm-routing",
  5670. .codec_name = "msm-stub-codec.1",
  5671. .codec_dai_name = "msm-stub-tx",
  5672. .no_pcm = 1,
  5673. .dpcm_capture = 1,
  5674. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5675. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5676. .ops = &msm_mi2s_be_ops,
  5677. .ignore_suspend = 1,
  5678. },
  5679. {
  5680. .name = LPASS_BE_SEC_MI2S_RX,
  5681. .stream_name = "Secondary MI2S Playback",
  5682. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5683. .platform_name = "msm-pcm-routing",
  5684. .codec_name = "msm-stub-codec.1",
  5685. .codec_dai_name = "msm-stub-rx",
  5686. .no_pcm = 1,
  5687. .dpcm_playback = 1,
  5688. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5689. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5690. .ops = &msm_mi2s_be_ops,
  5691. .ignore_suspend = 1,
  5692. .ignore_pmdown_time = 1,
  5693. },
  5694. {
  5695. .name = LPASS_BE_SEC_MI2S_TX,
  5696. .stream_name = "Secondary MI2S Capture",
  5697. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5698. .platform_name = "msm-pcm-routing",
  5699. .codec_name = "msm-stub-codec.1",
  5700. .codec_dai_name = "msm-stub-tx",
  5701. .no_pcm = 1,
  5702. .dpcm_capture = 1,
  5703. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5704. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5705. .ops = &msm_mi2s_be_ops,
  5706. .ignore_suspend = 1,
  5707. },
  5708. {
  5709. .name = LPASS_BE_TERT_MI2S_RX,
  5710. .stream_name = "Tertiary MI2S Playback",
  5711. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5712. .platform_name = "msm-pcm-routing",
  5713. .codec_name = "msm-stub-codec.1",
  5714. .codec_dai_name = "msm-stub-rx",
  5715. .no_pcm = 1,
  5716. .dpcm_playback = 1,
  5717. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5718. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5719. .ops = &msm_mi2s_be_ops,
  5720. .ignore_suspend = 1,
  5721. .ignore_pmdown_time = 1,
  5722. },
  5723. {
  5724. .name = LPASS_BE_TERT_MI2S_TX,
  5725. .stream_name = "Tertiary MI2S Capture",
  5726. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5727. .platform_name = "msm-pcm-routing",
  5728. .codec_name = "msm-stub-codec.1",
  5729. .codec_dai_name = "msm-stub-tx",
  5730. .no_pcm = 1,
  5731. .dpcm_capture = 1,
  5732. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5733. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5734. .ops = &msm_mi2s_be_ops,
  5735. .ignore_suspend = 1,
  5736. },
  5737. {
  5738. .name = LPASS_BE_QUAT_MI2S_RX,
  5739. .stream_name = "Quaternary MI2S Playback",
  5740. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5741. .platform_name = "msm-pcm-routing",
  5742. .codec_name = "msm-stub-codec.1",
  5743. .codec_dai_name = "msm-stub-rx",
  5744. .no_pcm = 1,
  5745. .dpcm_playback = 1,
  5746. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5747. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5748. .ops = &msm_mi2s_be_ops,
  5749. .ignore_suspend = 1,
  5750. .ignore_pmdown_time = 1,
  5751. },
  5752. {
  5753. .name = LPASS_BE_QUAT_MI2S_TX,
  5754. .stream_name = "Quaternary MI2S Capture",
  5755. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5756. .platform_name = "msm-pcm-routing",
  5757. .codec_name = "msm-stub-codec.1",
  5758. .codec_dai_name = "msm-stub-tx",
  5759. .no_pcm = 1,
  5760. .dpcm_capture = 1,
  5761. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5762. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5763. .ops = &msm_mi2s_be_ops,
  5764. .ignore_suspend = 1,
  5765. },
  5766. {
  5767. .name = LPASS_BE_QUIN_MI2S_RX,
  5768. .stream_name = "Quinary MI2S Playback",
  5769. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5770. .platform_name = "msm-pcm-routing",
  5771. .codec_name = "msm-stub-codec.1",
  5772. .codec_dai_name = "msm-stub-rx",
  5773. .no_pcm = 1,
  5774. .dpcm_playback = 1,
  5775. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5776. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5777. .ops = &msm_mi2s_be_ops,
  5778. .ignore_suspend = 1,
  5779. .ignore_pmdown_time = 1,
  5780. },
  5781. {
  5782. .name = LPASS_BE_QUIN_MI2S_TX,
  5783. .stream_name = "Quinary MI2S Capture",
  5784. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5785. .platform_name = "msm-pcm-routing",
  5786. .codec_name = "msm-stub-codec.1",
  5787. .codec_dai_name = "msm-stub-tx",
  5788. .no_pcm = 1,
  5789. .dpcm_capture = 1,
  5790. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5791. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5792. .ops = &msm_mi2s_be_ops,
  5793. .ignore_suspend = 1,
  5794. },
  5795. };
  5796. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5797. /* Primary AUX PCM Backend DAI Links */
  5798. {
  5799. .name = LPASS_BE_AUXPCM_RX,
  5800. .stream_name = "AUX PCM Playback",
  5801. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5802. .platform_name = "msm-pcm-routing",
  5803. .codec_name = "msm-stub-codec.1",
  5804. .codec_dai_name = "msm-stub-rx",
  5805. .no_pcm = 1,
  5806. .dpcm_playback = 1,
  5807. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5808. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5809. .ignore_pmdown_time = 1,
  5810. .ignore_suspend = 1,
  5811. },
  5812. {
  5813. .name = LPASS_BE_AUXPCM_TX,
  5814. .stream_name = "AUX PCM Capture",
  5815. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5816. .platform_name = "msm-pcm-routing",
  5817. .codec_name = "msm-stub-codec.1",
  5818. .codec_dai_name = "msm-stub-tx",
  5819. .no_pcm = 1,
  5820. .dpcm_capture = 1,
  5821. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5822. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5823. .ignore_suspend = 1,
  5824. },
  5825. /* Secondary AUX PCM Backend DAI Links */
  5826. {
  5827. .name = LPASS_BE_SEC_AUXPCM_RX,
  5828. .stream_name = "Sec AUX PCM Playback",
  5829. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5830. .platform_name = "msm-pcm-routing",
  5831. .codec_name = "msm-stub-codec.1",
  5832. .codec_dai_name = "msm-stub-rx",
  5833. .no_pcm = 1,
  5834. .dpcm_playback = 1,
  5835. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5836. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5837. .ignore_pmdown_time = 1,
  5838. .ignore_suspend = 1,
  5839. },
  5840. {
  5841. .name = LPASS_BE_SEC_AUXPCM_TX,
  5842. .stream_name = "Sec AUX PCM Capture",
  5843. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5844. .platform_name = "msm-pcm-routing",
  5845. .codec_name = "msm-stub-codec.1",
  5846. .codec_dai_name = "msm-stub-tx",
  5847. .no_pcm = 1,
  5848. .dpcm_capture = 1,
  5849. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5850. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5851. .ignore_suspend = 1,
  5852. },
  5853. /* Tertiary AUX PCM Backend DAI Links */
  5854. {
  5855. .name = LPASS_BE_TERT_AUXPCM_RX,
  5856. .stream_name = "Tert AUX PCM Playback",
  5857. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5858. .platform_name = "msm-pcm-routing",
  5859. .codec_name = "msm-stub-codec.1",
  5860. .codec_dai_name = "msm-stub-rx",
  5861. .no_pcm = 1,
  5862. .dpcm_playback = 1,
  5863. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5864. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5865. .ignore_suspend = 1,
  5866. },
  5867. {
  5868. .name = LPASS_BE_TERT_AUXPCM_TX,
  5869. .stream_name = "Tert AUX PCM Capture",
  5870. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5871. .platform_name = "msm-pcm-routing",
  5872. .codec_name = "msm-stub-codec.1",
  5873. .codec_dai_name = "msm-stub-tx",
  5874. .no_pcm = 1,
  5875. .dpcm_capture = 1,
  5876. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5877. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5878. .ignore_suspend = 1,
  5879. },
  5880. /* Quaternary AUX PCM Backend DAI Links */
  5881. {
  5882. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5883. .stream_name = "Quat AUX PCM Playback",
  5884. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5885. .platform_name = "msm-pcm-routing",
  5886. .codec_name = "msm-stub-codec.1",
  5887. .codec_dai_name = "msm-stub-rx",
  5888. .no_pcm = 1,
  5889. .dpcm_playback = 1,
  5890. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5891. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5892. .ignore_pmdown_time = 1,
  5893. .ignore_suspend = 1,
  5894. },
  5895. {
  5896. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5897. .stream_name = "Quat AUX PCM Capture",
  5898. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5899. .platform_name = "msm-pcm-routing",
  5900. .codec_name = "msm-stub-codec.1",
  5901. .codec_dai_name = "msm-stub-tx",
  5902. .no_pcm = 1,
  5903. .dpcm_capture = 1,
  5904. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5905. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5906. .ignore_suspend = 1,
  5907. },
  5908. /* Quinary AUX PCM Backend DAI Links */
  5909. {
  5910. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5911. .stream_name = "Quin AUX PCM Playback",
  5912. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5913. .platform_name = "msm-pcm-routing",
  5914. .codec_name = "msm-stub-codec.1",
  5915. .codec_dai_name = "msm-stub-rx",
  5916. .no_pcm = 1,
  5917. .dpcm_playback = 1,
  5918. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5919. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5920. .ignore_pmdown_time = 1,
  5921. .ignore_suspend = 1,
  5922. },
  5923. {
  5924. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5925. .stream_name = "Quin AUX PCM Capture",
  5926. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5927. .platform_name = "msm-pcm-routing",
  5928. .codec_name = "msm-stub-codec.1",
  5929. .codec_dai_name = "msm-stub-tx",
  5930. .no_pcm = 1,
  5931. .dpcm_capture = 1,
  5932. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5933. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5934. .ignore_suspend = 1,
  5935. },
  5936. };
  5937. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5938. /* WSA CDC DMA Backend DAI Links */
  5939. {
  5940. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5941. .stream_name = "WSA CDC DMA0 Playback",
  5942. .cpu_dai_name = "msm-dai-cdc-dma.45056",
  5943. .platform_name = "msm-pcm-routing",
  5944. .codec_name = "bolero_codec",
  5945. .codec_dai_name = "wsa_macro_rx1",
  5946. .no_pcm = 1,
  5947. .dpcm_playback = 1,
  5948. .init = &msm_wsa_cdc_dma_init,
  5949. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  5950. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5951. .ignore_pmdown_time = 1,
  5952. .ignore_suspend = 1,
  5953. .ops = &msm_cdc_dma_be_ops,
  5954. },
  5955. {
  5956. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5957. .stream_name = "WSA CDC DMA0 Capture",
  5958. .cpu_dai_name = "msm-dai-cdc-dma.45057",
  5959. .platform_name = "msm-pcm-hostless",
  5960. .codec_name = "bolero_codec",
  5961. .codec_dai_name = "wsa_macro_vifeedback",
  5962. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5963. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5964. .ignore_suspend = 1,
  5965. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5966. .ops = &msm_cdc_dma_be_ops,
  5967. },
  5968. {
  5969. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5970. .stream_name = "WSA CDC DMA1 Playback",
  5971. .cpu_dai_name = "msm-dai-cdc-dma.45058",
  5972. .platform_name = "msm-pcm-routing",
  5973. .codec_name = "bolero_codec",
  5974. .codec_dai_name = "wsa_macro_rx_mix",
  5975. .no_pcm = 1,
  5976. .dpcm_playback = 1,
  5977. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5978. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5979. .ignore_pmdown_time = 1,
  5980. .ignore_suspend = 1,
  5981. .ops = &msm_cdc_dma_be_ops,
  5982. },
  5983. {
  5984. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  5985. .stream_name = "WSA CDC DMA1 Capture",
  5986. .cpu_dai_name = "msm-dai-cdc-dma.45059",
  5987. .platform_name = "msm-pcm-routing",
  5988. .codec_name = "bolero_codec",
  5989. .codec_dai_name = "wsa_macro_echo",
  5990. .no_pcm = 1,
  5991. .dpcm_capture = 1,
  5992. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  5993. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5994. .ignore_suspend = 1,
  5995. .ops = &msm_cdc_dma_be_ops,
  5996. },
  5997. {
  5998. .name = LPASS_BE_WSA_CDC_DMA_TX_2,
  5999. .stream_name = "WSA CDC DMA2 Capture",
  6000. .cpu_dai_name = "msm-dai-cdc-dma.45061",
  6001. .platform_name = "msm-pcm-routing",
  6002. .codec_name = "bolero_codec",
  6003. .codec_dai_name = "msm-stub-tx",
  6004. .no_pcm = 1,
  6005. .dpcm_capture = 1,
  6006. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2,
  6007. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6008. .ignore_suspend = 1,
  6009. .ops = &msm_cdc_dma_be_ops,
  6010. },
  6011. };
  6012. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6013. {
  6014. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6015. .stream_name = "VA CDC DMA0 Capture",
  6016. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6017. .platform_name = "msm-pcm-routing",
  6018. .codec_name = "bolero_codec",
  6019. .codec_dai_name = "va_macro_tx1",
  6020. .no_pcm = 1,
  6021. .dpcm_capture = 1,
  6022. .init = &msm_va_cdc_dma_init,
  6023. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6024. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6025. .ignore_suspend = 1,
  6026. .ops = &msm_cdc_dma_be_ops,
  6027. },
  6028. {
  6029. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6030. .stream_name = "VA CDC DMA1 Capture",
  6031. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6032. .platform_name = "msm-pcm-routing",
  6033. .codec_name = "bolero_codec",
  6034. .codec_dai_name = "va_macro_tx2",
  6035. .no_pcm = 1,
  6036. .dpcm_capture = 1,
  6037. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6038. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6039. .ignore_suspend = 1,
  6040. .ops = &msm_cdc_dma_be_ops,
  6041. },
  6042. };
  6043. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6044. ARRAY_SIZE(msm_common_dai_links) +
  6045. ARRAY_SIZE(msm_tasha_fe_dai_links) +
  6046. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6047. ARRAY_SIZE(msm_common_be_dai_links) +
  6048. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6049. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6050. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6051. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6052. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6053. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links)];
  6054. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6055. {
  6056. int ret = 0;
  6057. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6058. &service_nb);
  6059. if (ret < 0)
  6060. pr_err("%s: Audio notifier register failed ret = %d\n",
  6061. __func__, ret);
  6062. return ret;
  6063. }
  6064. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6065. struct snd_ctl_elem_value *ucontrol)
  6066. {
  6067. int ret = 0;
  6068. int port_id;
  6069. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6070. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6071. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6072. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6073. (vad_enable < 0) || (vad_enable > 1) ||
  6074. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6075. pr_err("%s: Invalid arguments\n", __func__);
  6076. ret = -EINVAL;
  6077. goto done;
  6078. }
  6079. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6080. vad_enable, preroll_config, vad_intf);
  6081. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6082. if (ret) {
  6083. pr_err("%s: Invalid vad interface\n", __func__);
  6084. goto done;
  6085. }
  6086. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6087. done:
  6088. return ret;
  6089. }
  6090. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6091. {
  6092. int ret = 0;
  6093. uint32_t tasha_codec = 0;
  6094. ret = afe_cal_init_hwdep(card);
  6095. if (ret) {
  6096. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6097. ret = 0;
  6098. }
  6099. /* tasha late probe when it is present */
  6100. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6101. &tasha_codec);
  6102. if (ret) {
  6103. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6104. ret = 0;
  6105. } else {
  6106. if (tasha_codec) {
  6107. ret = msm_snd_card_tasha_late_probe(card);
  6108. if (ret)
  6109. dev_err(card->dev, "%s: tasha late probe err\n",
  6110. __func__);
  6111. }
  6112. }
  6113. return ret;
  6114. }
  6115. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6116. .name = "qcs405-snd-card",
  6117. .controls = msm_snd_controls,
  6118. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6119. .late_probe = msm_snd_card_codec_late_probe,
  6120. };
  6121. static int msm_populate_dai_link_component_of_node(
  6122. struct snd_soc_card *card)
  6123. {
  6124. int i, index, ret = 0;
  6125. struct device *cdev = card->dev;
  6126. struct snd_soc_dai_link *dai_link = card->dai_link;
  6127. struct device_node *np;
  6128. if (!cdev) {
  6129. pr_err("%s: Sound card device memory NULL\n", __func__);
  6130. return -ENODEV;
  6131. }
  6132. for (i = 0; i < card->num_links; i++) {
  6133. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6134. continue;
  6135. /* populate platform_of_node for snd card dai links */
  6136. if (dai_link[i].platform_name &&
  6137. !dai_link[i].platform_of_node) {
  6138. index = of_property_match_string(cdev->of_node,
  6139. "asoc-platform-names",
  6140. dai_link[i].platform_name);
  6141. if (index < 0) {
  6142. pr_err("%s: No match found for platform name: %s\n",
  6143. __func__, dai_link[i].platform_name);
  6144. ret = index;
  6145. goto err;
  6146. }
  6147. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6148. index);
  6149. if (!np) {
  6150. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6151. __func__, dai_link[i].platform_name,
  6152. index);
  6153. ret = -ENODEV;
  6154. goto err;
  6155. }
  6156. dai_link[i].platform_of_node = np;
  6157. dai_link[i].platform_name = NULL;
  6158. }
  6159. /* populate cpu_of_node for snd card dai links */
  6160. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6161. index = of_property_match_string(cdev->of_node,
  6162. "asoc-cpu-names",
  6163. dai_link[i].cpu_dai_name);
  6164. if (index >= 0) {
  6165. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6166. index);
  6167. if (!np) {
  6168. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6169. __func__,
  6170. dai_link[i].cpu_dai_name);
  6171. ret = -ENODEV;
  6172. goto err;
  6173. }
  6174. dai_link[i].cpu_of_node = np;
  6175. dai_link[i].cpu_dai_name = NULL;
  6176. }
  6177. }
  6178. /* populate codec_of_node for snd card dai links */
  6179. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6180. index = of_property_match_string(cdev->of_node,
  6181. "asoc-codec-names",
  6182. dai_link[i].codec_name);
  6183. if (index < 0)
  6184. continue;
  6185. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6186. index);
  6187. if (!np) {
  6188. pr_err("%s: retrieving phandle for codec %s failed\n",
  6189. __func__, dai_link[i].codec_name);
  6190. ret = -ENODEV;
  6191. goto err;
  6192. }
  6193. dai_link[i].codec_of_node = np;
  6194. dai_link[i].codec_name = NULL;
  6195. }
  6196. }
  6197. err:
  6198. return ret;
  6199. }
  6200. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6201. /* FrontEnd DAI Links */
  6202. {
  6203. .name = "MSMSTUB Media1",
  6204. .stream_name = "MultiMedia1",
  6205. .cpu_dai_name = "MultiMedia1",
  6206. .platform_name = "msm-pcm-dsp.0",
  6207. .dynamic = 1,
  6208. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6209. .dpcm_playback = 1,
  6210. .dpcm_capture = 1,
  6211. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6212. SND_SOC_DPCM_TRIGGER_POST},
  6213. .codec_dai_name = "snd-soc-dummy-dai",
  6214. .codec_name = "snd-soc-dummy",
  6215. .ignore_suspend = 1,
  6216. /* this dainlink has playback support */
  6217. .ignore_pmdown_time = 1,
  6218. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6219. },
  6220. };
  6221. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6222. /* Backend DAI Links */
  6223. {
  6224. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6225. .stream_name = "VA CDC DMA0 Capture",
  6226. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6227. .platform_name = "msm-pcm-routing",
  6228. .codec_name = "bolero_codec",
  6229. .codec_dai_name = "va_macro_tx1",
  6230. .no_pcm = 1,
  6231. .dpcm_capture = 1,
  6232. .init = &msm_va_cdc_dma_init,
  6233. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6234. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6235. .ignore_suspend = 1,
  6236. .ops = &msm_cdc_dma_be_ops,
  6237. },
  6238. {
  6239. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6240. .stream_name = "VA CDC DMA1 Capture",
  6241. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6242. .platform_name = "msm-pcm-routing",
  6243. .codec_name = "bolero_codec",
  6244. .codec_dai_name = "va_macro_tx2",
  6245. .no_pcm = 1,
  6246. .dpcm_capture = 1,
  6247. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6248. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6249. .ignore_suspend = 1,
  6250. .ops = &msm_cdc_dma_be_ops,
  6251. },
  6252. };
  6253. static struct snd_soc_dai_link msm_stub_dai_links[
  6254. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6255. ARRAY_SIZE(msm_stub_be_dai_links)];
  6256. struct snd_soc_card snd_soc_card_stub_msm = {
  6257. .name = "qcs405-stub-snd-card",
  6258. };
  6259. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6260. { .compatible = "qcom,qcs405-asoc-snd",
  6261. .data = "codec"},
  6262. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6263. .data = "stub_codec"},
  6264. {},
  6265. };
  6266. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6267. {
  6268. struct snd_soc_card *card = NULL;
  6269. struct snd_soc_dai_link *dailink;
  6270. int total_links = 0;
  6271. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6272. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6273. const struct of_device_id *match;
  6274. int rc = 0;
  6275. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6276. if (!match) {
  6277. dev_err(dev, "%s: No DT match found for sound card\n",
  6278. __func__);
  6279. return NULL;
  6280. }
  6281. if (!strcmp(match->data, "codec")) {
  6282. card = &snd_soc_card_qcs405_msm;
  6283. memcpy(msm_qcs405_dai_links + total_links,
  6284. msm_common_dai_links,
  6285. sizeof(msm_common_dai_links));
  6286. total_links += ARRAY_SIZE(msm_common_dai_links);
  6287. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6288. &tasha_codec);
  6289. if (rc) {
  6290. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6291. __func__);
  6292. } else {
  6293. if (tasha_codec) {
  6294. dev_dbg(dev, "%s(): Tasha codec is present\n",
  6295. __func__);
  6296. memcpy(msm_qcs405_dai_links + total_links,
  6297. msm_tasha_fe_dai_links,
  6298. sizeof(msm_tasha_fe_dai_links));
  6299. total_links +=
  6300. ARRAY_SIZE(msm_tasha_fe_dai_links);
  6301. }
  6302. }
  6303. memcpy(msm_qcs405_dai_links + total_links,
  6304. msm_common_misc_fe_dai_links,
  6305. sizeof(msm_common_misc_fe_dai_links));
  6306. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6307. memcpy(msm_qcs405_dai_links + total_links,
  6308. msm_common_be_dai_links,
  6309. sizeof(msm_common_be_dai_links));
  6310. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6311. if (tasha_codec) {
  6312. memcpy(msm_qcs405_dai_links + total_links,
  6313. msm_tasha_be_dai_links,
  6314. sizeof(msm_tasha_be_dai_links));
  6315. total_links += ARRAY_SIZE(msm_tasha_be_dai_links);
  6316. }
  6317. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6318. &va_bolero_codec);
  6319. if (rc) {
  6320. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6321. __func__);
  6322. } else {
  6323. if (va_bolero_codec) {
  6324. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6325. __func__);
  6326. memcpy(msm_qcs405_dai_links + total_links,
  6327. msm_va_cdc_dma_be_dai_links,
  6328. sizeof(msm_va_cdc_dma_be_dai_links));
  6329. total_links +=
  6330. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6331. }
  6332. }
  6333. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6334. &wsa_bolero_codec);
  6335. if (rc) {
  6336. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6337. __func__);
  6338. } else {
  6339. if (wsa_bolero_codec) {
  6340. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6341. __func__);
  6342. memcpy(msm_qcs405_dai_links + total_links,
  6343. msm_wsa_cdc_dma_be_dai_links,
  6344. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6345. total_links +=
  6346. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6347. }
  6348. }
  6349. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6350. &mi2s_audio_intf);
  6351. if (rc) {
  6352. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6353. __func__);
  6354. } else {
  6355. if (mi2s_audio_intf) {
  6356. memcpy(msm_qcs405_dai_links + total_links,
  6357. msm_mi2s_be_dai_links,
  6358. sizeof(msm_mi2s_be_dai_links));
  6359. total_links +=
  6360. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6361. }
  6362. }
  6363. rc = of_property_read_u32(dev->of_node,
  6364. "qcom,auxpcm-audio-intf",
  6365. &auxpcm_audio_intf);
  6366. if (rc) {
  6367. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6368. __func__);
  6369. } else {
  6370. if (auxpcm_audio_intf) {
  6371. memcpy(msm_qcs405_dai_links + total_links,
  6372. msm_auxpcm_be_dai_links,
  6373. sizeof(msm_auxpcm_be_dai_links));
  6374. total_links +=
  6375. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6376. }
  6377. }
  6378. dailink = msm_qcs405_dai_links;
  6379. } else if (!strcmp(match->data, "stub_codec")) {
  6380. card = &snd_soc_card_stub_msm;
  6381. memcpy(msm_stub_dai_links + total_links,
  6382. msm_stub_fe_dai_links,
  6383. sizeof(msm_stub_fe_dai_links));
  6384. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6385. memcpy(msm_stub_dai_links + total_links,
  6386. msm_stub_be_dai_links,
  6387. sizeof(msm_stub_be_dai_links));
  6388. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6389. dailink = msm_stub_dai_links;
  6390. }
  6391. if (card) {
  6392. card->dai_link = dailink;
  6393. card->num_links = total_links;
  6394. }
  6395. return card;
  6396. }
  6397. static int msm_wsa881x_init(struct snd_soc_component *component)
  6398. {
  6399. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6400. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6401. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6402. SPKR_L_BOOST, SPKR_L_VI};
  6403. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6404. SPKR_R_BOOST, SPKR_R_VI};
  6405. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6406. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6407. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6408. struct msm_asoc_mach_data *pdata;
  6409. struct snd_soc_dapm_context *dapm;
  6410. int ret = 0;
  6411. if (!codec) {
  6412. pr_err("%s codec is NULL\n", __func__);
  6413. return -EINVAL;
  6414. }
  6415. dapm = snd_soc_codec_get_dapm(codec);
  6416. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6417. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6418. __func__, codec->component.name);
  6419. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6420. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6421. &ch_rate[0], &spkleft_port_types[0]);
  6422. if (dapm->component) {
  6423. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6424. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6425. }
  6426. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6427. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6428. __func__, codec->component.name);
  6429. wsa881x_set_channel_map(codec, &spkright_ports[0],
  6430. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6431. &ch_rate[0], &spkright_port_types[0]);
  6432. if (dapm->component) {
  6433. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6434. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6435. }
  6436. } else {
  6437. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  6438. codec->component.name);
  6439. ret = -EINVAL;
  6440. goto err;
  6441. }
  6442. pdata = snd_soc_card_get_drvdata(component->card);
  6443. if (pdata && pdata->codec_root)
  6444. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6445. codec);
  6446. err:
  6447. return ret;
  6448. }
  6449. static int msm_init_wsa_dev(struct platform_device *pdev,
  6450. struct snd_soc_card *card)
  6451. {
  6452. struct device_node *wsa_of_node;
  6453. u32 wsa_max_devs;
  6454. u32 wsa_dev_cnt;
  6455. int i;
  6456. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6457. const char *wsa_auxdev_name_prefix[1];
  6458. char *dev_name_str = NULL;
  6459. int found = 0;
  6460. int ret = 0;
  6461. /* Get maximum WSA device count for this platform */
  6462. ret = of_property_read_u32(pdev->dev.of_node,
  6463. "qcom,wsa-max-devs", &wsa_max_devs);
  6464. if (ret) {
  6465. dev_info(&pdev->dev,
  6466. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6467. __func__, pdev->dev.of_node->full_name, ret);
  6468. card->num_aux_devs = 0;
  6469. return 0;
  6470. }
  6471. if (wsa_max_devs == 0) {
  6472. dev_warn(&pdev->dev,
  6473. "%s: Max WSA devices is 0 for this target?\n",
  6474. __func__);
  6475. card->num_aux_devs = 0;
  6476. return 0;
  6477. }
  6478. /* Get count of WSA device phandles for this platform */
  6479. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6480. "qcom,wsa-devs", NULL);
  6481. if (wsa_dev_cnt == -ENOENT) {
  6482. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6483. __func__);
  6484. goto err;
  6485. } else if (wsa_dev_cnt <= 0) {
  6486. dev_err(&pdev->dev,
  6487. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6488. __func__, wsa_dev_cnt);
  6489. ret = -EINVAL;
  6490. goto err;
  6491. }
  6492. /*
  6493. * Expect total phandles count to be NOT less than maximum possible
  6494. * WSA count. However, if it is less, then assign same value to
  6495. * max count as well.
  6496. */
  6497. if (wsa_dev_cnt < wsa_max_devs) {
  6498. dev_dbg(&pdev->dev,
  6499. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6500. __func__, wsa_max_devs, wsa_dev_cnt);
  6501. wsa_max_devs = wsa_dev_cnt;
  6502. }
  6503. /* Make sure prefix string passed for each WSA device */
  6504. ret = of_property_count_strings(pdev->dev.of_node,
  6505. "qcom,wsa-aux-dev-prefix");
  6506. if (ret != wsa_dev_cnt) {
  6507. dev_err(&pdev->dev,
  6508. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6509. __func__, wsa_dev_cnt, ret);
  6510. ret = -EINVAL;
  6511. goto err;
  6512. }
  6513. /*
  6514. * Alloc mem to store phandle and index info of WSA device, if already
  6515. * registered with ALSA core
  6516. */
  6517. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6518. sizeof(struct msm_wsa881x_dev_info),
  6519. GFP_KERNEL);
  6520. if (!wsa881x_dev_info) {
  6521. ret = -ENOMEM;
  6522. goto err;
  6523. }
  6524. /*
  6525. * search and check whether all WSA devices are already
  6526. * registered with ALSA core or not. If found a node, store
  6527. * the node and the index in a local array of struct for later
  6528. * use.
  6529. */
  6530. for (i = 0; i < wsa_dev_cnt; i++) {
  6531. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6532. "qcom,wsa-devs", i);
  6533. if (unlikely(!wsa_of_node)) {
  6534. /* we should not be here */
  6535. dev_err(&pdev->dev,
  6536. "%s: wsa dev node is not present\n",
  6537. __func__);
  6538. ret = -EINVAL;
  6539. goto err_free_dev_info;
  6540. }
  6541. if (soc_find_component(wsa_of_node, NULL)) {
  6542. /* WSA device registered with ALSA core */
  6543. wsa881x_dev_info[found].of_node = wsa_of_node;
  6544. wsa881x_dev_info[found].index = i;
  6545. found++;
  6546. if (found == wsa_max_devs)
  6547. break;
  6548. }
  6549. }
  6550. if (found < wsa_max_devs) {
  6551. dev_dbg(&pdev->dev,
  6552. "%s: failed to find %d components. Found only %d\n",
  6553. __func__, wsa_max_devs, found);
  6554. return -EPROBE_DEFER;
  6555. }
  6556. dev_info(&pdev->dev,
  6557. "%s: found %d wsa881x devices registered with ALSA core\n",
  6558. __func__, found);
  6559. card->num_aux_devs = wsa_max_devs;
  6560. card->num_configs = wsa_max_devs;
  6561. /* Alloc array of AUX devs struct */
  6562. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6563. sizeof(struct snd_soc_aux_dev),
  6564. GFP_KERNEL);
  6565. if (!msm_aux_dev) {
  6566. ret = -ENOMEM;
  6567. goto err_free_dev_info;
  6568. }
  6569. /* Alloc array of codec conf struct */
  6570. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6571. sizeof(struct snd_soc_codec_conf),
  6572. GFP_KERNEL);
  6573. if (!msm_codec_conf) {
  6574. ret = -ENOMEM;
  6575. goto err_free_aux_dev;
  6576. }
  6577. for (i = 0; i < card->num_aux_devs; i++) {
  6578. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6579. GFP_KERNEL);
  6580. if (!dev_name_str) {
  6581. ret = -ENOMEM;
  6582. goto err_free_cdc_conf;
  6583. }
  6584. ret = of_property_read_string_index(pdev->dev.of_node,
  6585. "qcom,wsa-aux-dev-prefix",
  6586. wsa881x_dev_info[i].index,
  6587. wsa_auxdev_name_prefix);
  6588. if (ret) {
  6589. dev_err(&pdev->dev,
  6590. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6591. __func__, ret);
  6592. ret = -EINVAL;
  6593. goto err_free_dev_name_str;
  6594. }
  6595. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6596. msm_aux_dev[i].name = dev_name_str;
  6597. msm_aux_dev[i].codec_name = NULL;
  6598. msm_aux_dev[i].codec_of_node =
  6599. wsa881x_dev_info[i].of_node;
  6600. msm_aux_dev[i].init = msm_wsa881x_init;
  6601. msm_codec_conf[i].dev_name = NULL;
  6602. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  6603. msm_codec_conf[i].of_node =
  6604. wsa881x_dev_info[i].of_node;
  6605. }
  6606. card->codec_conf = msm_codec_conf;
  6607. card->aux_dev = msm_aux_dev;
  6608. return 0;
  6609. err_free_dev_name_str:
  6610. devm_kfree(&pdev->dev, dev_name_str);
  6611. err_free_cdc_conf:
  6612. devm_kfree(&pdev->dev, msm_codec_conf);
  6613. err_free_aux_dev:
  6614. devm_kfree(&pdev->dev, msm_aux_dev);
  6615. err_free_dev_info:
  6616. devm_kfree(&pdev->dev, wsa881x_dev_info);
  6617. err:
  6618. return ret;
  6619. }
  6620. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6621. {
  6622. int count;
  6623. u32 mi2s_master_slave[MI2S_MAX];
  6624. int ret;
  6625. for (count = 0; count < MI2S_MAX; count++) {
  6626. mutex_init(&mi2s_intf_conf[count].lock);
  6627. mi2s_intf_conf[count].ref_cnt = 0;
  6628. }
  6629. ret = of_property_read_u32_array(pdev->dev.of_node,
  6630. "qcom,msm-mi2s-master",
  6631. mi2s_master_slave, MI2S_MAX);
  6632. if (ret) {
  6633. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6634. __func__);
  6635. } else {
  6636. for (count = 0; count < MI2S_MAX; count++) {
  6637. mi2s_intf_conf[count].msm_is_mi2s_master =
  6638. mi2s_master_slave[count];
  6639. }
  6640. }
  6641. }
  6642. static void msm_i2s_auxpcm_deinit(void)
  6643. {
  6644. int count;
  6645. for (count = 0; count < MI2S_MAX; count++) {
  6646. mutex_destroy(&mi2s_intf_conf[count].lock);
  6647. mi2s_intf_conf[count].ref_cnt = 0;
  6648. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6649. }
  6650. }
  6651. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6652. {
  6653. struct snd_soc_card *card;
  6654. struct msm_asoc_mach_data *pdata;
  6655. int ret;
  6656. if (!pdev->dev.of_node) {
  6657. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  6658. return -EINVAL;
  6659. }
  6660. pdata = devm_kzalloc(&pdev->dev,
  6661. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6662. if (!pdata)
  6663. return -ENOMEM;
  6664. card = populate_snd_card_dailinks(&pdev->dev);
  6665. if (!card) {
  6666. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6667. ret = -EINVAL;
  6668. goto err;
  6669. }
  6670. card->dev = &pdev->dev;
  6671. platform_set_drvdata(pdev, card);
  6672. snd_soc_card_set_drvdata(card, pdata);
  6673. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6674. if (ret) {
  6675. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  6676. ret);
  6677. goto err;
  6678. }
  6679. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6680. if (ret) {
  6681. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  6682. ret);
  6683. goto err;
  6684. }
  6685. ret = msm_populate_dai_link_component_of_node(card);
  6686. if (ret) {
  6687. ret = -EPROBE_DEFER;
  6688. goto err;
  6689. }
  6690. ret = msm_init_wsa_dev(pdev, card);
  6691. if (ret)
  6692. goto err;
  6693. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6694. "qcom,cdc-dmic01-gpios",
  6695. 0);
  6696. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6697. "qcom,cdc-dmic23-gpios",
  6698. 0);
  6699. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6700. "qcom,cdc-dmic45-gpios",
  6701. 0);
  6702. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6703. "qcom,cdc-dmic67-gpios",
  6704. 0);
  6705. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6706. if (ret == -EPROBE_DEFER) {
  6707. if (codec_reg_done)
  6708. ret = -EINVAL;
  6709. goto err;
  6710. } else if (ret) {
  6711. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  6712. ret);
  6713. goto err;
  6714. }
  6715. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  6716. spdev = pdev;
  6717. /* Parse pinctrl info from devicetree */
  6718. ret = msm_get_pinctrl(pdev);
  6719. if (!ret) {
  6720. pr_debug("%s: pinctrl parsing successful\n", __func__);
  6721. } else {
  6722. dev_dbg(&pdev->dev,
  6723. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  6724. __func__, ret);
  6725. ret = 0;
  6726. }
  6727. msm_i2s_auxpcm_init(pdev);
  6728. is_initial_boot = true;
  6729. return 0;
  6730. err:
  6731. msm_release_pinctrl(pdev);
  6732. return ret;
  6733. }
  6734. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6735. {
  6736. audio_notifier_deregister("qcs405");
  6737. msm_i2s_auxpcm_deinit();
  6738. msm_release_pinctrl(pdev);
  6739. return 0;
  6740. }
  6741. static struct platform_driver qcs405_asoc_machine_driver = {
  6742. .driver = {
  6743. .name = DRV_NAME,
  6744. .owner = THIS_MODULE,
  6745. .pm = &snd_soc_pm_ops,
  6746. .of_match_table = qcs405_asoc_machine_of_match,
  6747. },
  6748. .probe = msm_asoc_machine_probe,
  6749. .remove = msm_asoc_machine_remove,
  6750. };
  6751. module_platform_driver(qcs405_asoc_machine_driver);
  6752. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  6753. MODULE_LICENSE("GPL v2");
  6754. MODULE_ALIAS("platform:" DRV_NAME);
  6755. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);