hal_api_mon.h 37 KB

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  1. /*
  2. * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_API_MON_H_
  19. #define _HAL_API_MON_H_
  20. #include "qdf_types.h"
  21. #include "hal_internal.h"
  22. #include <target_type.h>
  23. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  24. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  25. #define HAL_RX_MASk(block, field) block##_##field##_MASK
  26. #define HAL_RX_GET(_ptr, block, field) \
  27. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  28. HAL_RX_MASk(block, field)) >> \
  29. HAL_RX_LSB(block, field))
  30. #define HAL_RX_PHY_DATA_RADAR 0x01
  31. #define HAL_SU_MU_CODING_LDPC 0x01
  32. #define HAL_RX_FCS_LEN (4)
  33. #define KEY_EXTIV 0x20
  34. #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000
  35. #define HAL_RX_USER_TLV32_TYPE_LSB 1
  36. #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE
  37. #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000
  38. #define HAL_RX_USER_TLV32_LEN_LSB 10
  39. #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00
  40. #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000
  41. #define HAL_RX_USER_TLV32_USERID_LSB 26
  42. #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000
  43. #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1)
  44. #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask))
  45. #define HAL_RX_TLV32_HDR_SIZE 4
  46. #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \
  47. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  48. HAL_RX_USER_TLV32_TYPE_MASK) >> \
  49. HAL_RX_USER_TLV32_TYPE_LSB)
  50. #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \
  51. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  52. HAL_RX_USER_TLV32_LEN_MASK) >> \
  53. HAL_RX_USER_TLV32_LEN_LSB)
  54. #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \
  55. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  56. HAL_RX_USER_TLV32_USERID_MASK) >> \
  57. HAL_RX_USER_TLV32_USERID_LSB)
  58. #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
  59. #define HAL_TLV_STATUS_PPDU_DONE 1
  60. #define HAL_TLV_STATUS_BUF_DONE 2
  61. #define HAL_MAX_UL_MU_USERS 8
  62. #define HAL_RX_PKT_TYPE_11A 0
  63. #define HAL_RX_PKT_TYPE_11B 1
  64. #define HAL_RX_PKT_TYPE_11N 2
  65. #define HAL_RX_PKT_TYPE_11AC 3
  66. #define HAL_RX_PKT_TYPE_11AX 4
  67. #define HAL_RX_RECEPTION_TYPE_SU 0
  68. #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1
  69. #define HAL_RX_RECEPTION_TYPE_OFDMA 2
  70. #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3
  71. /* Multiply rate by 2 to avoid float point
  72. * and get rate in units of 500kbps
  73. */
  74. #define HAL_11B_RATE_0MCS 11*2
  75. #define HAL_11B_RATE_1MCS 5.5*2
  76. #define HAL_11B_RATE_2MCS 2*2
  77. #define HAL_11B_RATE_3MCS 1*2
  78. #define HAL_11B_RATE_4MCS 11*2
  79. #define HAL_11B_RATE_5MCS 5.5*2
  80. #define HAL_11B_RATE_6MCS 2*2
  81. #define HAL_11A_RATE_0MCS 48*2
  82. #define HAL_11A_RATE_1MCS 24*2
  83. #define HAL_11A_RATE_2MCS 12*2
  84. #define HAL_11A_RATE_3MCS 6*2
  85. #define HAL_11A_RATE_4MCS 54*2
  86. #define HAL_11A_RATE_5MCS 36*2
  87. #define HAL_11A_RATE_6MCS 18*2
  88. #define HAL_11A_RATE_7MCS 9*2
  89. #define HE_GI_0_8 0
  90. #define HE_GI_1_6 1
  91. #define HE_GI_3_2 2
  92. #define HT_SGI_PRESENT 0x80
  93. #define HE_LTF_1_X 0
  94. #define HE_LTF_2_X 1
  95. #define HE_LTF_4_X 2
  96. #define VHT_SIG_SU_NSS_MASK 0x7
  97. #define HAL_TID_INVALID 31
  98. #define HAL_AST_IDX_INVALID 0xFFFF
  99. #ifdef GET_MSDU_AGGREGATION
  100. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\
  101. {\
  102. struct rx_msdu_end *rx_msdu_end;\
  103. bool first_msdu, last_msdu; \
  104. rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\
  105. first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\
  106. last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\
  107. if (first_msdu && last_msdu)\
  108. rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\
  109. else\
  110. rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \
  111. } \
  112. #else
  113. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)
  114. #endif
  115. enum {
  116. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  117. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  118. HAL_HW_RX_DECAP_FORMAT_ETH2,
  119. HAL_HW_RX_DECAP_FORMAT_8023,
  120. };
  121. enum {
  122. DP_PPDU_STATUS_START,
  123. DP_PPDU_STATUS_DONE,
  124. };
  125. static inline
  126. uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void)
  127. {
  128. /* return the HW_RX_DESC size */
  129. return sizeof(struct rx_pkt_tlvs);
  130. }
  131. static inline
  132. uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data)
  133. {
  134. return data;
  135. }
  136. static inline
  137. uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr)
  138. {
  139. struct rx_attention *rx_attn;
  140. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  141. rx_attn = &rx_desc->attn_tlv.rx_attn;
  142. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
  143. }
  144. static inline
  145. uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr)
  146. {
  147. struct rx_attention *rx_attn;
  148. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  149. rx_attn = &rx_desc->attn_tlv.rx_attn;
  150. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
  151. }
  152. static inline
  153. uint32_t
  154. HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) {
  155. struct rx_msdu_start *rx_msdu_start;
  156. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  157. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  158. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  159. }
  160. static inline
  161. uint8_t *
  162. HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
  163. uint8_t *rx_pkt_hdr;
  164. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  165. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  166. return rx_pkt_hdr;
  167. }
  168. static inline
  169. uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr)
  170. {
  171. struct rx_mpdu_info *rx_mpdu_info;
  172. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  173. rx_mpdu_info =
  174. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  175. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
  176. }
  177. /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */
  178. static inline
  179. uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr)
  180. {
  181. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  182. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  183. return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
  184. }
  185. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  186. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  187. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
  188. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
  189. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
  190. #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \
  191. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  192. (((struct reo_entrance_ring *)reo_ent_desc) \
  193. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  194. #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \
  195. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  196. (((struct reo_entrance_ring *)reo_ent_desc) \
  197. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  198. #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \
  199. (HAL_RX_BUF_COOKIE_GET(& \
  200. (((struct reo_entrance_ring *)reo_ent_desc) \
  201. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  202. /**
  203. * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and
  204. * cookie from the REO entrance ring element
  205. *
  206. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  207. * the current descriptor
  208. * @ buf_info: structure to return the buffer information
  209. * @ msdu_cnt: pointer to msdu count in MPDU
  210. * Return: void
  211. */
  212. static inline
  213. void hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
  214. struct hal_buf_info *buf_info,
  215. void **pp_buf_addr_info,
  216. uint32_t *msdu_cnt
  217. )
  218. {
  219. struct reo_entrance_ring *reo_ent_ring =
  220. (struct reo_entrance_ring *)rx_desc;
  221. struct buffer_addr_info *buf_addr_info;
  222. struct rx_mpdu_desc_info *rx_mpdu_desc_info_details;
  223. uint32_t loop_cnt;
  224. rx_mpdu_desc_info_details =
  225. &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
  226. *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details,
  227. RX_MPDU_DESC_INFO_0, MSDU_COUNT);
  228. loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT);
  229. buf_addr_info =
  230. &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
  231. buf_info->paddr =
  232. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  233. ((uint64_t)
  234. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  235. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  236. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  237. "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d\n",
  238. __func__, __LINE__, reo_ent_ring, buf_addr_info,
  239. (unsigned long long)buf_info->paddr, loop_cnt);
  240. *pp_buf_addr_info = (void *)buf_addr_info;
  241. }
  242. static inline
  243. void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
  244. struct hal_buf_info *buf_info, void **pp_buf_addr_info)
  245. {
  246. struct rx_msdu_link *msdu_link =
  247. (struct rx_msdu_link *)rx_msdu_link_desc;
  248. struct buffer_addr_info *buf_addr_info;
  249. buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info;
  250. buf_info->paddr =
  251. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  252. ((uint64_t)
  253. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  254. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  255. *pp_buf_addr_info = (void *)buf_addr_info;
  256. }
  257. /**
  258. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  259. *
  260. * @ soc : HAL version of the SOC pointer
  261. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  262. * @ buf_addr_info : void pointer to the buffer_addr_info
  263. *
  264. * Return: void
  265. */
  266. static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc,
  267. void *src_srng_desc, void *buf_addr_info)
  268. {
  269. struct buffer_addr_info *wbm_srng_buffer_addr_info =
  270. (struct buffer_addr_info *)src_srng_desc;
  271. uint64_t paddr;
  272. struct buffer_addr_info *p_buffer_addr_info =
  273. (struct buffer_addr_info *)buf_addr_info;
  274. paddr =
  275. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  276. ((uint64_t)
  277. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  278. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  279. "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx\n",
  280. __func__, __LINE__, src_srng_desc, (unsigned long long)paddr,
  281. (unsigned long long)p_buffer_addr_info->sw_buffer_cookie);
  282. /* Structure copy !!! */
  283. *wbm_srng_buffer_addr_info =
  284. *((struct buffer_addr_info *)buf_addr_info);
  285. }
  286. static inline
  287. uint32 hal_get_rx_msdu_link_desc_size(void)
  288. {
  289. return sizeof(struct rx_msdu_link);
  290. }
  291. enum {
  292. HAL_PKT_TYPE_OFDM = 0,
  293. HAL_PKT_TYPE_CCK,
  294. HAL_PKT_TYPE_HT,
  295. HAL_PKT_TYPE_VHT,
  296. HAL_PKT_TYPE_HE,
  297. };
  298. enum {
  299. HAL_SGI_0_8_US,
  300. HAL_SGI_0_4_US,
  301. HAL_SGI_1_6_US,
  302. HAL_SGI_3_2_US,
  303. };
  304. enum {
  305. HAL_FULL_RX_BW_20,
  306. HAL_FULL_RX_BW_40,
  307. HAL_FULL_RX_BW_80,
  308. HAL_FULL_RX_BW_160,
  309. };
  310. enum {
  311. HAL_RX_TYPE_SU,
  312. HAL_RX_TYPE_MU_MIMO,
  313. HAL_RX_TYPE_MU_OFDMA,
  314. HAL_RX_TYPE_MU_OFDMA_MIMO,
  315. };
  316. /**
  317. * enum
  318. * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL
  319. * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL
  320. */
  321. enum {
  322. HAL_RX_MON_PPDU_START = 0,
  323. HAL_RX_MON_PPDU_END,
  324. };
  325. struct hal_rx_ppdu_user_info {
  326. };
  327. struct hal_rx_ppdu_common_info {
  328. uint32_t ppdu_id;
  329. uint32_t last_ppdu_id;
  330. uint32_t ppdu_timestamp;
  331. uint32_t mpdu_cnt_fcs_ok;
  332. uint32_t mpdu_cnt_fcs_err;
  333. };
  334. struct hal_rx_msdu_payload_info {
  335. uint8_t *first_msdu_payload;
  336. uint32_t payload_len;
  337. };
  338. struct hal_rx_ppdu_info {
  339. struct hal_rx_ppdu_common_info com_info;
  340. struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS];
  341. struct mon_rx_status rx_status;
  342. struct hal_rx_msdu_payload_info msdu_info;
  343. /* status ring PPDU start and end state */
  344. uint32_t rx_state;
  345. };
  346. static inline uint32_t
  347. hal_get_rx_status_buf_size(void) {
  348. /* RX status buffer size is hard coded for now */
  349. return 2048;
  350. }
  351. static inline uint8_t*
  352. hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
  353. uint32_t tlv_len, tlv_tag;
  354. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
  355. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  356. /* The actual length of PPDU_END is the combined length of many PHY
  357. * TLVs that follow. Skip the TLV header and
  358. * rx_rxpcu_classification_overview that follows the header to get to
  359. * next TLV.
  360. */
  361. if (tlv_tag == WIFIRX_PPDU_END_E)
  362. tlv_len = sizeof(struct rx_rxpcu_classification_overview);
  363. return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len +
  364. HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3)));
  365. }
  366. static void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc,
  367. void *rx_tlv_hdr,
  368. struct hal_rx_ppdu_info
  369. *ppdu_info)
  370. {
  371. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr,
  372. (void *)ppdu_info);
  373. }
  374. /**
  375. * hal_rx_status_get_tlv_info() - process receive info TLV
  376. * @rx_tlv_hdr: pointer to TLV header
  377. * @ppdu_info: pointer to ppdu_info
  378. *
  379. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  380. */
  381. static inline uint32_t
  382. hal_rx_status_get_tlv_info(void *rx_tlv_hdr, struct hal_rx_ppdu_info *ppdu_info,
  383. struct hal_soc *hal)
  384. {
  385. uint32_t tlv_tag, user_id, tlv_len, value;
  386. uint8_t group_id = 0;
  387. uint8_t he_dcm = 0;
  388. uint8_t he_stbc = 0;
  389. uint16_t he_gi = 0;
  390. uint16_t he_ltf = 0;
  391. void *rx_tlv;
  392. bool unhandled = false;
  393. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  394. user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
  395. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  396. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  397. switch (tlv_tag) {
  398. case WIFIRX_PPDU_START_E:
  399. ppdu_info->com_info.ppdu_id =
  400. HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
  401. PHY_PPDU_ID);
  402. /* channel number is set in PHY meta data */
  403. ppdu_info->rx_status.chan_num =
  404. HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
  405. SW_PHY_META_DATA);
  406. ppdu_info->com_info.ppdu_timestamp =
  407. HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
  408. PPDU_START_TIMESTAMP);
  409. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  410. break;
  411. case WIFIRX_PPDU_START_USER_INFO_E:
  412. break;
  413. case WIFIRX_PPDU_END_E:
  414. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  415. "[%s][%d] ppdu_end_e len=%d",
  416. __func__, __LINE__, tlv_len);
  417. /* This is followed by sub-TLVs of PPDU_END */
  418. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  419. break;
  420. case WIFIRXPCU_PPDU_END_INFO_E:
  421. ppdu_info->rx_status.tsft =
  422. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
  423. WB_TIMESTAMP_UPPER_32);
  424. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  425. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
  426. WB_TIMESTAMP_LOWER_32);
  427. ppdu_info->rx_status.duration =
  428. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_8,
  429. RX_PPDU_DURATION);
  430. break;
  431. case WIFIRX_PPDU_END_USER_STATS_E:
  432. {
  433. unsigned long tid = 0;
  434. uint16_t seq = 0;
  435. ppdu_info->rx_status.ast_index =
  436. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
  437. AST_INDEX);
  438. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
  439. RECEIVED_QOS_DATA_TID_BITMAP);
  440. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8);
  441. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  442. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  443. ppdu_info->rx_status.tcp_msdu_count =
  444. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  445. TCP_MSDU_COUNT) +
  446. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  447. TCP_ACK_MSDU_COUNT);
  448. ppdu_info->rx_status.udp_msdu_count =
  449. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  450. UDP_MSDU_COUNT);
  451. ppdu_info->rx_status.other_msdu_count =
  452. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  453. OTHER_MSDU_COUNT);
  454. ppdu_info->rx_status.frame_control_info_valid =
  455. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  456. DATA_SEQUENCE_CONTROL_INFO_VALID);
  457. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
  458. FIRST_DATA_SEQ_CTRL);
  459. if (ppdu_info->rx_status.frame_control_info_valid)
  460. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  461. ppdu_info->rx_status.preamble_type =
  462. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  463. HT_CONTROL_FIELD_PKT_TYPE);
  464. switch (ppdu_info->rx_status.preamble_type) {
  465. case HAL_RX_PKT_TYPE_11N:
  466. ppdu_info->rx_status.ht_flags = 1;
  467. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  468. break;
  469. case HAL_RX_PKT_TYPE_11AC:
  470. ppdu_info->rx_status.vht_flags = 1;
  471. break;
  472. case HAL_RX_PKT_TYPE_11AX:
  473. ppdu_info->rx_status.he_flags = 1;
  474. break;
  475. default:
  476. break;
  477. }
  478. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  479. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  480. MPDU_CNT_FCS_OK);
  481. ppdu_info->com_info.mpdu_cnt_fcs_err =
  482. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
  483. MPDU_CNT_FCS_ERR);
  484. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  485. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  486. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  487. else
  488. ppdu_info->rx_status.rs_flags &=
  489. (~IEEE80211_AMPDU_FLAG);
  490. break;
  491. }
  492. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  493. break;
  494. case WIFIRX_PPDU_END_STATUS_DONE_E:
  495. return HAL_TLV_STATUS_PPDU_DONE;
  496. case WIFIDUMMY_E:
  497. return HAL_TLV_STATUS_BUF_DONE;
  498. case WIFIPHYRX_HT_SIG_E:
  499. {
  500. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  501. HAL_RX_OFFSET(PHYRX_HT_SIG_0,
  502. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  503. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
  504. FEC_CODING);
  505. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  506. 1 : 0;
  507. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  508. HT_SIG_INFO_0, MCS);
  509. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  510. HT_SIG_INFO_0, CBW);
  511. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  512. HT_SIG_INFO_1, SHORT_GI);
  513. break;
  514. }
  515. case WIFIPHYRX_L_SIG_B_E:
  516. {
  517. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  518. HAL_RX_OFFSET(PHYRX_L_SIG_B_0,
  519. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  520. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
  521. switch (value) {
  522. case 1:
  523. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  524. break;
  525. case 2:
  526. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  527. break;
  528. case 3:
  529. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  530. break;
  531. case 4:
  532. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  533. break;
  534. case 5:
  535. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  536. break;
  537. case 6:
  538. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  539. break;
  540. case 7:
  541. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  542. break;
  543. default:
  544. break;
  545. }
  546. ppdu_info->rx_status.cck_flag = 1;
  547. break;
  548. }
  549. case WIFIPHYRX_L_SIG_A_E:
  550. {
  551. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  552. HAL_RX_OFFSET(PHYRX_L_SIG_A_0,
  553. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  554. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
  555. switch (value) {
  556. case 8:
  557. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  558. break;
  559. case 9:
  560. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  561. break;
  562. case 10:
  563. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  564. break;
  565. case 11:
  566. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  567. break;
  568. case 12:
  569. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  570. break;
  571. case 13:
  572. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  573. break;
  574. case 14:
  575. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  576. break;
  577. case 15:
  578. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  579. break;
  580. default:
  581. break;
  582. }
  583. ppdu_info->rx_status.ofdm_flag = 1;
  584. break;
  585. }
  586. case WIFIPHYRX_VHT_SIG_A_E:
  587. {
  588. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  589. HAL_RX_OFFSET(PHYRX_VHT_SIG_A_0,
  590. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  591. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
  592. SU_MU_CODING);
  593. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  594. 1 : 0;
  595. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID);
  596. ppdu_info->rx_status.vht_flag_values5 = group_id;
  597. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  598. VHT_SIG_A_INFO_1, MCS);
  599. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  600. VHT_SIG_A_INFO_1, GI_SETTING);
  601. switch (hal->target_type) {
  602. case TARGET_TYPE_QCA8074:
  603. ppdu_info->rx_status.is_stbc =
  604. HAL_RX_GET(vht_sig_a_info,
  605. VHT_SIG_A_INFO_0, STBC);
  606. value = HAL_RX_GET(vht_sig_a_info,
  607. VHT_SIG_A_INFO_0, N_STS);
  608. if (ppdu_info->rx_status.is_stbc && (value > 0))
  609. value = ((value + 1) >> 1) - 1;
  610. ppdu_info->rx_status.nss =
  611. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  612. break;
  613. case TARGET_TYPE_QCA6290:
  614. #if !defined(QCA_WIFI_QCA6290_11AX)
  615. ppdu_info->rx_status.is_stbc =
  616. HAL_RX_GET(vht_sig_a_info,
  617. VHT_SIG_A_INFO_0, STBC);
  618. value = HAL_RX_GET(vht_sig_a_info,
  619. VHT_SIG_A_INFO_0, N_STS);
  620. if (ppdu_info->rx_status.is_stbc && (value > 0))
  621. value = ((value + 1) >> 1) - 1;
  622. ppdu_info->rx_status.nss =
  623. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  624. #else
  625. ppdu_info->rx_status.nss = 0;
  626. #endif
  627. break;
  628. #ifdef QCA_WIFI_QCA6390
  629. case TARGET_TYPE_QCA6390:
  630. ppdu_info->rx_status.nss = 0;
  631. break;
  632. #endif
  633. default:
  634. break;
  635. }
  636. ppdu_info->rx_status.vht_flag_values3[0] =
  637. (((ppdu_info->rx_status.mcs) << 4)
  638. | ppdu_info->rx_status.nss);
  639. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  640. VHT_SIG_A_INFO_0, BANDWIDTH);
  641. ppdu_info->rx_status.vht_flag_values2 =
  642. ppdu_info->rx_status.bw;
  643. ppdu_info->rx_status.vht_flag_values4 =
  644. HAL_RX_GET(vht_sig_a_info,
  645. VHT_SIG_A_INFO_1, SU_MU_CODING);
  646. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  647. VHT_SIG_A_INFO_1, BEAMFORMED);
  648. break;
  649. }
  650. case WIFIPHYRX_HE_SIG_A_SU_E:
  651. {
  652. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  653. HAL_RX_OFFSET(PHYRX_HE_SIG_A_SU_0,
  654. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  655. ppdu_info->rx_status.he_flags = 1;
  656. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  657. FORMAT_INDICATION);
  658. if (value == 0) {
  659. ppdu_info->rx_status.he_data1 =
  660. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  661. } else {
  662. ppdu_info->rx_status.he_data1 =
  663. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  664. }
  665. /* data1 */
  666. ppdu_info->rx_status.he_data1 |=
  667. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  668. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  669. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  670. QDF_MON_STATUS_HE_MCS_KNOWN |
  671. QDF_MON_STATUS_HE_DCM_KNOWN |
  672. QDF_MON_STATUS_HE_CODING_KNOWN |
  673. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  674. QDF_MON_STATUS_HE_STBC_KNOWN |
  675. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  676. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  677. /* data2 */
  678. ppdu_info->rx_status.he_data2 =
  679. QDF_MON_STATUS_HE_GI_KNOWN;
  680. ppdu_info->rx_status.he_data2 |=
  681. QDF_MON_STATUS_TXBF_KNOWN |
  682. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  683. QDF_MON_STATUS_TXOP_KNOWN |
  684. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  685. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  686. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  687. /* data3 */
  688. value = HAL_RX_GET(he_sig_a_su_info,
  689. HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
  690. ppdu_info->rx_status.he_data3 = value;
  691. value = HAL_RX_GET(he_sig_a_su_info,
  692. HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
  693. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  694. ppdu_info->rx_status.he_data3 |= value;
  695. value = HAL_RX_GET(he_sig_a_su_info,
  696. HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
  697. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  698. ppdu_info->rx_status.he_data3 |= value;
  699. value = HAL_RX_GET(he_sig_a_su_info,
  700. HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
  701. ppdu_info->rx_status.mcs = value;
  702. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  703. ppdu_info->rx_status.he_data3 |= value;
  704. value = HAL_RX_GET(he_sig_a_su_info,
  705. HE_SIG_A_SU_INFO_0, DCM);
  706. he_dcm = value;
  707. value = value << QDF_MON_STATUS_DCM_SHIFT;
  708. ppdu_info->rx_status.he_data3 |= value;
  709. value = HAL_RX_GET(he_sig_a_su_info,
  710. HE_SIG_A_SU_INFO_1, CODING);
  711. value = value << QDF_MON_STATUS_CODING_SHIFT;
  712. ppdu_info->rx_status.he_data3 |= value;
  713. value = HAL_RX_GET(he_sig_a_su_info,
  714. HE_SIG_A_SU_INFO_1,
  715. LDPC_EXTRA_SYMBOL);
  716. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  717. ppdu_info->rx_status.he_data3 |= value;
  718. value = HAL_RX_GET(he_sig_a_su_info,
  719. HE_SIG_A_SU_INFO_1, STBC);
  720. he_stbc = value;
  721. value = value << QDF_MON_STATUS_STBC_SHIFT;
  722. ppdu_info->rx_status.he_data3 |= value;
  723. /* data4 */
  724. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  725. SPATIAL_REUSE);
  726. ppdu_info->rx_status.he_data4 = value;
  727. /* data5 */
  728. value = HAL_RX_GET(he_sig_a_su_info,
  729. HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
  730. ppdu_info->rx_status.he_data5 = value;
  731. ppdu_info->rx_status.bw = value;
  732. value = HAL_RX_GET(he_sig_a_su_info,
  733. HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
  734. switch (value) {
  735. case 0:
  736. he_gi = HE_GI_0_8;
  737. he_ltf = HE_LTF_1_X;
  738. break;
  739. case 1:
  740. he_gi = HE_GI_0_8;
  741. he_ltf = HE_LTF_2_X;
  742. break;
  743. case 2:
  744. he_gi = HE_GI_1_6;
  745. he_ltf = HE_LTF_2_X;
  746. break;
  747. case 3:
  748. if (he_dcm && he_stbc) {
  749. he_gi = HE_GI_0_8;
  750. he_ltf = HE_LTF_4_X;
  751. } else {
  752. he_gi = HE_GI_3_2;
  753. he_ltf = HE_LTF_4_X;
  754. }
  755. break;
  756. }
  757. ppdu_info->rx_status.sgi = he_gi;
  758. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  759. ppdu_info->rx_status.he_data5 |= value;
  760. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  761. ppdu_info->rx_status.he_data5 |= value;
  762. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  763. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  764. ppdu_info->rx_status.he_data5 |= value;
  765. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  766. PACKET_EXTENSION_A_FACTOR);
  767. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  768. ppdu_info->rx_status.he_data5 |= value;
  769. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
  770. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  771. ppdu_info->rx_status.he_data5 |= value;
  772. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  773. PACKET_EXTENSION_PE_DISAMBIGUITY);
  774. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  775. ppdu_info->rx_status.he_data5 |= value;
  776. /* data6 */
  777. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  778. value++;
  779. ppdu_info->rx_status.nss = value;
  780. ppdu_info->rx_status.he_data6 = value;
  781. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  782. DOPPLER_INDICATION);
  783. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  784. ppdu_info->rx_status.he_data6 |= value;
  785. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  786. TXOP_DURATION);
  787. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  788. ppdu_info->rx_status.he_data6 |= value;
  789. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  790. HE_SIG_A_SU_INFO_1, TXBF);
  791. break;
  792. }
  793. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  794. {
  795. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  796. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_DL_0,
  797. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  798. ppdu_info->rx_status.he_mu_flags = 1;
  799. /* HE Flags */
  800. /*data1*/
  801. ppdu_info->rx_status.he_data1 =
  802. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  803. ppdu_info->rx_status.he_data1 |=
  804. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  805. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  806. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  807. QDF_MON_STATUS_HE_STBC_KNOWN |
  808. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  809. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  810. /* data2 */
  811. ppdu_info->rx_status.he_data2 =
  812. QDF_MON_STATUS_HE_GI_KNOWN;
  813. ppdu_info->rx_status.he_data2 |=
  814. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  815. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  816. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  817. QDF_MON_STATUS_TXOP_KNOWN |
  818. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  819. /*data3*/
  820. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  821. HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
  822. ppdu_info->rx_status.he_data3 = value;
  823. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  824. HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
  825. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  826. ppdu_info->rx_status.he_data3 |= value;
  827. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  828. HE_SIG_A_MU_DL_INFO_1,
  829. LDPC_EXTRA_SYMBOL);
  830. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  831. ppdu_info->rx_status.he_data3 |= value;
  832. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  833. HE_SIG_A_MU_DL_INFO_1, STBC);
  834. he_stbc = value;
  835. value = value << QDF_MON_STATUS_STBC_SHIFT;
  836. ppdu_info->rx_status.he_data3 |= value;
  837. /*data4*/
  838. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  839. SPATIAL_REUSE);
  840. ppdu_info->rx_status.he_data4 = value;
  841. /*data5*/
  842. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  843. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  844. ppdu_info->rx_status.he_data5 = value;
  845. ppdu_info->rx_status.bw = value;
  846. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  847. HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
  848. switch (value) {
  849. case 0:
  850. he_gi = HE_GI_0_8;
  851. he_ltf = HE_LTF_4_X;
  852. break;
  853. case 1:
  854. he_gi = HE_GI_0_8;
  855. he_ltf = HE_LTF_2_X;
  856. break;
  857. case 2:
  858. he_gi = HE_GI_1_6;
  859. he_ltf = HE_LTF_2_X;
  860. break;
  861. case 3:
  862. he_gi = HE_GI_3_2;
  863. he_ltf = HE_LTF_4_X;
  864. break;
  865. }
  866. ppdu_info->rx_status.sgi = he_gi;
  867. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  868. ppdu_info->rx_status.he_data5 |= value;
  869. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  870. ppdu_info->rx_status.he_data5 |= value;
  871. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  872. HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS);
  873. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  874. ppdu_info->rx_status.he_data5 |= value;
  875. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  876. PACKET_EXTENSION_A_FACTOR);
  877. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  878. ppdu_info->rx_status.he_data5 |= value;
  879. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  880. PACKET_EXTENSION_PE_DISAMBIGUITY);
  881. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  882. ppdu_info->rx_status.he_data5 |= value;
  883. /*data6*/
  884. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  885. DOPPLER_INDICATION);
  886. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  887. ppdu_info->rx_status.he_data6 |= value;
  888. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  889. TXOP_DURATION);
  890. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  891. ppdu_info->rx_status.he_data6 |= value;
  892. /* HE-MU Flags */
  893. /* HE-MU-flags1 */
  894. ppdu_info->rx_status.he_flags1 =
  895. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  896. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  897. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  898. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  899. QDF_MON_STATUS_RU_0_KNOWN;
  900. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  901. HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
  902. ppdu_info->rx_status.he_flags1 |= value;
  903. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  904. HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
  905. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  906. ppdu_info->rx_status.he_flags1 |= value;
  907. /* HE-MU-flags2 */
  908. ppdu_info->rx_status.he_flags2 =
  909. QDF_MON_STATUS_BW_KNOWN;
  910. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  911. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  912. ppdu_info->rx_status.he_flags2 |= value;
  913. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  914. HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
  915. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  916. ppdu_info->rx_status.he_flags2 |= value;
  917. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  918. HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
  919. value = value - 1;
  920. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  921. ppdu_info->rx_status.he_flags2 |= value;
  922. break;
  923. }
  924. case WIFIPHYRX_HE_SIG_B1_MU_E:
  925. {
  926. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  927. HAL_RX_OFFSET(PHYRX_HE_SIG_B1_MU_0,
  928. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  929. ppdu_info->rx_status.he_sig_b_common_known |=
  930. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  931. /* TODO: Check on the availability of other fields in
  932. * sig_b_common
  933. */
  934. value = HAL_RX_GET(he_sig_b1_mu_info,
  935. HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
  936. ppdu_info->rx_status.he_RU[0] = value;
  937. break;
  938. }
  939. case WIFIPHYRX_HE_SIG_B2_MU_E:
  940. {
  941. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  942. HAL_RX_OFFSET(PHYRX_HE_SIG_B2_MU_0,
  943. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  944. /*
  945. * Not all "HE" fields can be updated from
  946. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  947. * to populate rest of the "HE" fields for MU scenarios.
  948. */
  949. /* HE-data1 */
  950. ppdu_info->rx_status.he_data1 |=
  951. QDF_MON_STATUS_HE_MCS_KNOWN |
  952. QDF_MON_STATUS_HE_CODING_KNOWN;
  953. /* HE-data2 */
  954. /* HE-data3 */
  955. value = HAL_RX_GET(he_sig_b2_mu_info,
  956. HE_SIG_B2_MU_INFO_0, STA_MCS);
  957. ppdu_info->rx_status.mcs = value;
  958. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  959. ppdu_info->rx_status.he_data3 |= value;
  960. value = HAL_RX_GET(he_sig_b2_mu_info,
  961. HE_SIG_B2_MU_INFO_0, STA_CODING);
  962. value = value << QDF_MON_STATUS_CODING_SHIFT;
  963. ppdu_info->rx_status.he_data3 |= value;
  964. /* HE-data4 */
  965. value = HAL_RX_GET(he_sig_b2_mu_info,
  966. HE_SIG_B2_MU_INFO_0, STA_ID);
  967. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  968. ppdu_info->rx_status.he_data4 |= value;
  969. /* HE-data5 */
  970. /* HE-data6 */
  971. value = HAL_RX_GET(he_sig_b2_mu_info,
  972. HE_SIG_B2_MU_INFO_0, NSTS);
  973. /* value n indicates n+1 spatial streams */
  974. value++;
  975. ppdu_info->rx_status.nss = value;
  976. ppdu_info->rx_status.he_data6 |= value;
  977. break;
  978. }
  979. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  980. {
  981. uint8_t *he_sig_b2_ofdma_info =
  982. (uint8_t *)rx_tlv +
  983. HAL_RX_OFFSET(PHYRX_HE_SIG_B2_OFDMA_0,
  984. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  985. /*
  986. * Not all "HE" fields can be updated from
  987. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  988. * to populate rest of "HE" fields for MU OFDMA scenarios.
  989. */
  990. /* HE-data1 */
  991. ppdu_info->rx_status.he_data1 |=
  992. QDF_MON_STATUS_HE_MCS_KNOWN |
  993. QDF_MON_STATUS_HE_DCM_KNOWN |
  994. QDF_MON_STATUS_HE_CODING_KNOWN;
  995. /* HE-data2 */
  996. ppdu_info->rx_status.he_data2 |=
  997. QDF_MON_STATUS_TXBF_KNOWN;
  998. /* HE-data3 */
  999. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1000. HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
  1001. ppdu_info->rx_status.mcs = value;
  1002. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1003. ppdu_info->rx_status.he_data3 |= value;
  1004. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1005. HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
  1006. he_dcm = value;
  1007. value = value << QDF_MON_STATUS_DCM_SHIFT;
  1008. ppdu_info->rx_status.he_data3 |= value;
  1009. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1010. HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
  1011. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1012. ppdu_info->rx_status.he_data3 |= value;
  1013. /* HE-data4 */
  1014. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1015. HE_SIG_B2_OFDMA_INFO_0, STA_ID);
  1016. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1017. ppdu_info->rx_status.he_data4 |= value;
  1018. /* HE-data5 */
  1019. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1020. HE_SIG_B2_OFDMA_INFO_0, TXBF);
  1021. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1022. ppdu_info->rx_status.he_data5 |= value;
  1023. /* HE-data6 */
  1024. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1025. HE_SIG_B2_OFDMA_INFO_0, NSTS);
  1026. /* value n indicates n+1 spatial streams */
  1027. value++;
  1028. ppdu_info->rx_status.nss = value;
  1029. ppdu_info->rx_status.he_data6 |= value;
  1030. break;
  1031. }
  1032. case WIFIPHYRX_RSSI_LEGACY_E:
  1033. {
  1034. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1035. HAL_RX_OFFSET(PHYRX_RSSI_LEGACY_3,
  1036. RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS);
  1037. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1038. PHYRX_RSSI_LEGACY_35, RSSI_COMB);
  1039. ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
  1040. ppdu_info->rx_status.he_re = 0;
  1041. ppdu_info->rx_status.reception_type = HAL_RX_GET(rx_tlv,
  1042. PHYRX_RSSI_LEGACY_0, RECEPTION_TYPE);
  1043. value = HAL_RX_GET(rssi_info_tlv,
  1044. RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
  1045. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1046. "RSSI_PRI20_CHAIN0: %d\n", value);
  1047. value = HAL_RX_GET(rssi_info_tlv,
  1048. RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0);
  1049. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1050. "RSSI_EXT20_CHAIN0: %d\n", value);
  1051. value = HAL_RX_GET(rssi_info_tlv,
  1052. RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0);
  1053. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1054. "RSSI_EXT40_LOW20_CHAIN0: %d\n", value);
  1055. value = HAL_RX_GET(rssi_info_tlv,
  1056. RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0);
  1057. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1058. "RSSI_EXT40_HIGH20_CHAIN0: %d\n", value);
  1059. value = HAL_RX_GET(rssi_info_tlv,
  1060. RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0);
  1061. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1062. "RSSI_EXT80_LOW20_CHAIN0: %d\n", value);
  1063. value = HAL_RX_GET(rssi_info_tlv,
  1064. RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0);
  1065. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1066. "RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value);
  1067. value = HAL_RX_GET(rssi_info_tlv,
  1068. RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0);
  1069. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1070. "RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value);
  1071. value = HAL_RX_GET(rssi_info_tlv,
  1072. RECEIVE_RSSI_INFO_1,
  1073. RSSI_EXT80_HIGH20_CHAIN0);
  1074. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1075. "RSSI_EXT80_HIGH20_CHAIN0: %d\n", value);
  1076. break;
  1077. }
  1078. case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
  1079. hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
  1080. ppdu_info);
  1081. break;
  1082. case WIFIRX_HEADER_E:
  1083. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1084. ppdu_info->msdu_info.payload_len = tlv_len;
  1085. break;
  1086. case WIFIRX_MPDU_START_E:
  1087. {
  1088. uint8_t *rx_mpdu_start =
  1089. (uint8_t *)rx_tlv + HAL_RX_OFFSET(RX_MPDU_START_0,
  1090. RX_MPDU_INFO_RX_MPDU_INFO_DETAILS);
  1091. uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0,
  1092. PHY_PPDU_ID);
  1093. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1094. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1095. ppdu_info->rx_status.ppdu_len =
  1096. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1097. MPDU_LENGTH);
  1098. } else {
  1099. ppdu_info->rx_status.ppdu_len +=
  1100. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1101. MPDU_LENGTH);
  1102. }
  1103. break;
  1104. }
  1105. case 0:
  1106. return HAL_TLV_STATUS_PPDU_DONE;
  1107. default:
  1108. unhandled = true;
  1109. break;
  1110. }
  1111. if (!unhandled)
  1112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1113. "%s TLV type: %d, TLV len:%d %s",
  1114. __func__, tlv_tag, tlv_len,
  1115. unhandled == true ? "unhandled" : "");
  1116. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, rx_tlv, tlv_len);
  1117. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1118. }
  1119. static inline
  1120. uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc)
  1121. {
  1122. return HAL_RX_TLV32_HDR_SIZE;
  1123. }
  1124. static inline QDF_STATUS
  1125. hal_get_rx_status_done(uint8_t *rx_tlv)
  1126. {
  1127. uint32_t tlv_tag;
  1128. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  1129. if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E)
  1130. return QDF_STATUS_SUCCESS;
  1131. else
  1132. return QDF_STATUS_E_EMPTY;
  1133. }
  1134. static inline QDF_STATUS
  1135. hal_clear_rx_status_done(uint8_t *rx_tlv)
  1136. {
  1137. *(uint32_t *)rx_tlv = 0;
  1138. return QDF_STATUS_SUCCESS;
  1139. }
  1140. #endif