03c268ac2d
Fix to receive correct descriptor buffer address for tx monitor Fix to send correct filter settings enabled Disabled default filter display log level to debug. Change-Id: I7ca1b1110cdcb10ca65ab8c414c19a81f1f4d331 CRs-Fixed: 3121965
276 linhas
8.6 KiB
C
276 linhas
8.6 KiB
C
/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_BE_API_MON_H_
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#define _HAL_BE_API_MON_H_
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#ifdef QCA_MONITOR_2_0_SUPPORT
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#include <mon_ingress_ring.h>
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#include <mon_destination_ring.h>
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#include "hal_be_hw_headers.h"
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#include <mon_ingress_ring.h>
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#include <mon_destination_ring.h>
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#include <hal_be_hw_headers.h>
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#include "hal_api_mon.h"
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#include <hal_generic_api.h>
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#include <hal_generic_api.h>
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#include <hal_api_mon.h>
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#define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000
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#define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0
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#define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff
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#define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004
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#define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0
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#define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff
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#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008
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#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
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#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
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#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
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#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c
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#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
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#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
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#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
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#define HAL_MON_PADDR_LO_SET(buff_addr_info, paddr_lo) \
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((*(((unsigned int *) buff_addr_info) + \
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(HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
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((paddr_lo) << HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \
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HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK)
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#define HAL_MON_PADDR_HI_SET(buff_addr_info, paddr_hi) \
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((*(((unsigned int *) buff_addr_info) + \
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(HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
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((paddr_hi) << HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \
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HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK)
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#define HAL_MON_VADDR_LO_SET(buff_addr_info, vaddr_lo) \
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((*(((unsigned int *) buff_addr_info) + \
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(HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET >> 2))) = \
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((vaddr_lo) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB) & \
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HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK)
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#define HAL_MON_VADDR_HI_SET(buff_addr_info, vaddr_hi) \
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((*(((unsigned int *) buff_addr_info) + \
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(HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET >> 2))) = \
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((vaddr_hi) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB) & \
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HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK)
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enum hal_dest_desc_end_reason {
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HAL_TX_MON_STATUS_BUFFER_FULL = 0,
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HAL_TX_MON_FLUSH_DETECTED,
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HAL_TX_MON_END_OF_PPDU,
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HAL_TX_MON_PPDU_TRUNCATED
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};
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/**
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* struct hal_mon_desc () - HAL Monitor descriptor
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*
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* @buf_addr: virtual buffer address
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* @ppdu_id: ppdu id
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* - TxMon fills scheduler id
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* - RxMON fills phy_ppdu_id
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* @end_offset: offset (units in 4 bytes) where status buffer ended
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* i.e offset of TLV + last TLV size
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* @end_reason: 0 - status buffer is full
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* 1 - flush detected
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* 2 - TX_FES_STATUS_END or RX_PPDU_END
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* 3 - PPDU truncated due to system error
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* @initiator: 1 - descriptor belongs to TX FES
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* 0 - descriptor belongs to TX RESPONSE
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* @empty_descriptor: 0 - this descriptor is written on a flush
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* or end of ppdu or end of status buffer
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* 1 - descriptor provided to indicate drop
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* @ring_id: ring id for debugging
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* @looping_count: count to indicate number of times producer
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* of entries has looped around the ring
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*/
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struct hal_mon_desc {
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uint64_t buf_addr;
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uint32_t ppdu_id;
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uint32_t end_offset:12,
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reserved_3a:4,
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end_reason:2,
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initiator:1,
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empty_descriptor:1,
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ring_id:8,
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looping_count:4;
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};
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typedef struct hal_mon_desc *hal_mon_desc_t;
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/**
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* struct hal_mon_buf_addr_status () - HAL buffer address tlv get status
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*
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* @buf_addr_31_0: Lower 32 bits of virtual address of status buffer
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* @buf_addr_63_32: Upper 32 bits of virtual address of status buffer
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* @dma_length: DMA length
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* @msdu_continuation: is msdu size more than fragment size
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* @truncated: is msdu got truncated
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* @tlv_padding: tlv paddding
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*/
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struct hal_mon_buf_addr_status {
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uint32_t buffer_virt_addr_31_0;
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uint32_t buffer_virt_addr_63_32;
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uint32_t dma_length:12,
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reserved_2a:4,
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msdu_continuation:1,
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truncated:1,
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reserved_2b:14;
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uint32_t tlv64_padding;
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};
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/**
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* hal_be_get_mon_dest_status() - Get monitor descriptor
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* @hal_soc_hdl: HAL Soc handle
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* @desc: HAL monitor descriptor
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*
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* Return: none
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*/
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static inline void
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hal_be_get_mon_dest_status(hal_soc_handle_t hal_soc,
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void *hw_desc,
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struct hal_mon_desc *status)
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{
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struct mon_destination_ring *desc = hw_desc;
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status->buf_addr = HAL_RX_GET(desc, MON_DESTINATION_RING_STAT,
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BUF_VIRT_ADDR_31_0) |
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(((uint64_t)HAL_RX_GET(desc,
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MON_DESTINATION_RING_STAT,
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BUF_VIRT_ADDR_63_32)) << 32);
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status->ppdu_id = desc->ppdu_id;
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status->end_offset = desc->end_offset;
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status->end_reason = desc->end_reason;
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status->initiator = desc->initiator;
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status->empty_descriptor = desc->empty_descriptor;
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status->looping_count = desc->looping_count;
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}
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/**
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* hal_mon_buff_addr_info_set() - set desc address in cookie
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* @hal_soc_hdl: HAL Soc handle
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* @mon_entry: monitor srng
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* @desc: HAL monitor descriptor
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*
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* Return: none
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*/
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static inline
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void hal_mon_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl,
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void *mon_entry,
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void *mon_desc_addr,
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qdf_dma_addr_t phy_addr)
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{
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uint32_t paddr_lo = ((uintptr_t)phy_addr & 0x00000000ffffffff);
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uint32_t paddr_hi = ((uintptr_t)phy_addr & 0xffffffff00000000) >> 32;
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uint32_t vaddr_lo = ((uintptr_t)mon_desc_addr & 0x00000000ffffffff);
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uint32_t vaddr_hi = ((uintptr_t)mon_desc_addr & 0xffffffff00000000) >> 32;
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HAL_MON_PADDR_LO_SET(mon_entry, paddr_lo);
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HAL_MON_PADDR_HI_SET(mon_entry, paddr_hi);
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HAL_MON_VADDR_LO_SET(mon_entry, vaddr_lo);
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HAL_MON_VADDR_HI_SET(mon_entry, vaddr_hi);
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}
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/* TX monitor */
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#define TX_MON_STATUS_BUF_SIZE 2048
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#define HAL_INVALID_PPDU_ID 0xFFFFFFFF
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enum hal_tx_tlv_status {
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HAL_MON_TX_FES_SETUP,
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HAL_MON_TX_FES_STATUS_END,
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HAL_MON_RX_RESPONSE_REQUIRED_INFO,
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HAL_MON_RESPONSE_END_STATUS_INFO,
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HAL_MON_TX_PCU_PPDU_SETUP_INIT,
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HAL_MON_TX_MPDU_START,
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HAL_MON_TX_MSDU_START,
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HAL_MON_TX_BUFFER_ADDR,
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HAL_MON_TX_DATA,
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HAL_MON_TX_FES_STATUS_START,
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HAL_MON_TX_FES_STATUS_PROT,
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HAL_MON_TX_FES_STATUS_START_PROT,
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HAL_MON_TX_FES_STATUS_START_PPDU,
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HAL_MON_TX_FES_STATUS_USER_PPDU,
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HAL_MON_RX_FRAME_BITMAP_ACK,
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HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_256,
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HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K,
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HAL_MON_COEX_TX_STATUS,
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HAL_MON_MACTX_HE_SIG_A_SU,
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HAL_MON_MACTX_HE_SIG_A_MU_DL,
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HAL_MON_MACTX_HE_SIG_B1_MU,
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HAL_MON_MACTX_HE_SIG_B2_MU,
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HAL_MON_MACTX_HE_SIG_B2_OFDMA,
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HAL_MON_MACTX_L_SIG_A,
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HAL_MON_MACTX_L_SIG_B,
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HAL_MON_MACTX_HT_SIG,
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HAL_MON_MACTX_VHT_SIG_A,
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HAL_MON_MACTX_USER_DESC_PER_USER,
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HAL_MON_MACTX_USER_DESC_COMMON,
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HAL_MON_MACTX_PHY_DESC,
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HAL_MON_TX_STATUS_PPDU_NOT_DONE,
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};
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/**
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* hal_tx_status_get_next_tlv() - get next tx status TLV
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* @tx_tlv: pointer to TLV header
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*
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* Return: pointer to next tlv info
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*/
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static inline uint8_t*
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hal_tx_status_get_next_tlv(uint8_t *tx_tlv) {
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uint32_t tlv_len, tlv_tag;
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tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv);
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tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv);
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return (uint8_t *)(((unsigned long)(tx_tlv + tlv_len +
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HAL_RX_TLV32_HDR_SIZE + 3)) & (~3));
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}
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/*
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* hal_txmon_status_free_buffer() - api to free status buffer
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* @hal_soc: HAL soc handle
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* @status_frag: qdf_frag_t buffer
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*
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* Return void
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*/
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static inline void
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hal_txmon_status_free_buffer(hal_soc_handle_t hal_soc_hdl,
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qdf_frag_t status_frag)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (hal_soc->ops->hal_txmon_status_free_buffer)
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hal_soc->ops->hal_txmon_status_free_buffer(status_frag);
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}
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#endif /* QCA_MONITOR_2_0_SUPPORT */
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#endif /* _HAL_BE_API_MON_H_ */
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