dp_tx.c 78 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891
  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include <wlan_cfg.h>
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #ifdef TX_PER_PDEV_DESC_POOL
  31. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  32. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  33. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  34. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  35. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  36. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  37. #else
  38. #ifdef TX_PER_VDEV_DESC_POOL
  39. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  40. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  41. #else
  42. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  43. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  44. #endif /* TX_PER_VDEV_DESC_POOL */
  45. #endif /* TX_PER_PDEV_DESC_POOL */
  46. /* TODO Add support in TSO */
  47. #define DP_DESC_NUM_FRAG(x) 0
  48. /* disable TQM_BYPASS */
  49. #define TQM_BYPASS_WAR 0
  50. /**
  51. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  52. * @vdev: DP Virtual device handle
  53. * @nbuf: Buffer pointer
  54. * @queue: queue ids container for nbuf
  55. *
  56. * TX packet queue has 2 instances, software descriptors id and dma ring id
  57. * Based on tx feature and hardware configuration queue id combination could be
  58. * different.
  59. * For example -
  60. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  61. * With no XPS,lock based resource protection, Descriptor pool ids are different
  62. * for each vdev, dma ring id will be same as single pdev id
  63. *
  64. * Return: None
  65. */
  66. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  67. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  68. {
  69. /* get flow id */
  70. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  71. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  72. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  73. "%s, pool_id:%d ring_id: %d",
  74. __func__, queue->desc_pool_id, queue->ring_id);
  75. return;
  76. }
  77. #if defined(FEATURE_TSO)
  78. /**
  79. * dp_tx_tso_desc_release() - Release the tso segment
  80. * after unmapping all the fragments
  81. *
  82. * @pdev - physical device handle
  83. * @tx_desc - Tx software descriptor
  84. */
  85. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  86. struct dp_tx_desc_s *tx_desc)
  87. {
  88. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  89. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  91. "%s %d TSO desc is NULL!",
  92. __func__, __LINE__);
  93. qdf_assert(0);
  94. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  95. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  96. "%s %d TSO common info is NULL!",
  97. __func__, __LINE__);
  98. qdf_assert(0);
  99. } else {
  100. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  101. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  102. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  103. tso_num_desc->num_seg.tso_cmn_num_seg--;
  104. qdf_nbuf_unmap_tso_segment(soc->osdev,
  105. tx_desc->tso_desc, false);
  106. } else {
  107. tso_num_desc->num_seg.tso_cmn_num_seg--;
  108. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  109. qdf_nbuf_unmap_tso_segment(soc->osdev,
  110. tx_desc->tso_desc, true);
  111. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  112. tx_desc->tso_num_desc);
  113. tx_desc->tso_num_desc = NULL;
  114. }
  115. dp_tx_tso_desc_free(soc,
  116. tx_desc->pool_id, tx_desc->tso_desc);
  117. tx_desc->tso_desc = NULL;
  118. }
  119. }
  120. #else
  121. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  122. struct dp_tx_desc_s *tx_desc)
  123. {
  124. return;
  125. }
  126. #endif
  127. /**
  128. * dp_tx_desc_release() - Release Tx Descriptor
  129. * @tx_desc : Tx Descriptor
  130. * @desc_pool_id: Descriptor Pool ID
  131. *
  132. * Deallocate all resources attached to Tx descriptor and free the Tx
  133. * descriptor.
  134. *
  135. * Return:
  136. */
  137. static void
  138. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  139. {
  140. struct dp_pdev *pdev = tx_desc->pdev;
  141. struct dp_soc *soc;
  142. uint8_t comp_status = 0;
  143. qdf_assert(pdev);
  144. soc = pdev->soc;
  145. if (tx_desc->frm_type == dp_tx_frm_tso)
  146. dp_tx_tso_desc_release(soc, tx_desc);
  147. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  148. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  149. qdf_atomic_dec(&pdev->num_tx_outstanding);
  150. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  151. qdf_atomic_dec(&pdev->num_tx_exception);
  152. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  153. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  154. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  155. else
  156. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  157. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  158. "Tx Completion Release desc %d status %d outstanding %d",
  159. tx_desc->id, comp_status,
  160. qdf_atomic_read(&pdev->num_tx_outstanding));
  161. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  162. return;
  163. }
  164. /**
  165. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  166. * @vdev: DP vdev Handle
  167. * @nbuf: skb
  168. *
  169. * Prepares and fills HTT metadata in the frame pre-header for special frames
  170. * that should be transmitted using varying transmit parameters.
  171. * There are 2 VDEV modes that currently needs this special metadata -
  172. * 1) Mesh Mode
  173. * 2) DSRC Mode
  174. *
  175. * Return: HTT metadata size
  176. *
  177. */
  178. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  179. uint32_t *meta_data)
  180. {
  181. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  182. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  183. uint8_t htt_desc_size;
  184. /* Size rounded of multiple of 8 bytes */
  185. uint8_t htt_desc_size_aligned;
  186. uint8_t *hdr = NULL;
  187. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  188. /*
  189. * Metadata - HTT MSDU Extension header
  190. */
  191. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  192. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  193. if (vdev->mesh_vdev) {
  194. /* Fill and add HTT metaheader */
  195. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  196. if (hdr == NULL) {
  197. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  198. "Error in filling HTT metadata\n");
  199. return 0;
  200. }
  201. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  202. } else if (vdev->opmode == wlan_op_mode_ocb) {
  203. /* Todo - Add support for DSRC */
  204. }
  205. return htt_desc_size_aligned;
  206. }
  207. /**
  208. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  209. * @tso_seg: TSO segment to process
  210. * @ext_desc: Pointer to MSDU extension descriptor
  211. *
  212. * Return: void
  213. */
  214. #if defined(FEATURE_TSO)
  215. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  216. void *ext_desc)
  217. {
  218. uint8_t num_frag;
  219. uint32_t tso_flags;
  220. /*
  221. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  222. * tcp_flag_mask
  223. *
  224. * Checksum enable flags are set in TCL descriptor and not in Extension
  225. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  226. */
  227. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  228. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  229. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  230. tso_seg->tso_flags.ip_len);
  231. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  232. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  233. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  234. uint32_t lo = 0;
  235. uint32_t hi = 0;
  236. qdf_dmaaddr_to_32s(
  237. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  238. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  239. tso_seg->tso_frags[num_frag].length);
  240. }
  241. return;
  242. }
  243. #else
  244. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  245. void *ext_desc)
  246. {
  247. return;
  248. }
  249. #endif
  250. #if defined(FEATURE_TSO)
  251. /**
  252. * dp_tx_free_tso_seg() - Loop through the tso segments
  253. * allocated and free them
  254. *
  255. * @soc: soc handle
  256. * @free_seg: list of tso segments
  257. * @msdu_info: msdu descriptor
  258. *
  259. * Return - void
  260. */
  261. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  262. struct qdf_tso_seg_elem_t *free_seg,
  263. struct dp_tx_msdu_info_s *msdu_info)
  264. {
  265. struct qdf_tso_seg_elem_t *next_seg;
  266. while (free_seg) {
  267. next_seg = free_seg->next;
  268. dp_tx_tso_desc_free(soc,
  269. msdu_info->tx_queue.desc_pool_id,
  270. free_seg);
  271. free_seg = next_seg;
  272. }
  273. }
  274. /**
  275. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  276. * allocated and free them
  277. *
  278. * @soc: soc handle
  279. * @free_seg: list of tso segments
  280. * @msdu_info: msdu descriptor
  281. * Return - void
  282. */
  283. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  284. struct qdf_tso_num_seg_elem_t *free_seg,
  285. struct dp_tx_msdu_info_s *msdu_info)
  286. {
  287. struct qdf_tso_num_seg_elem_t *next_seg;
  288. while (free_seg) {
  289. next_seg = free_seg->next;
  290. dp_tso_num_seg_free(soc,
  291. msdu_info->tx_queue.desc_pool_id,
  292. free_seg);
  293. free_seg = next_seg;
  294. }
  295. }
  296. /**
  297. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  298. * @vdev: virtual device handle
  299. * @msdu: network buffer
  300. * @msdu_info: meta data associated with the msdu
  301. *
  302. * Return: QDF_STATUS_SUCCESS success
  303. */
  304. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  305. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  306. {
  307. struct qdf_tso_seg_elem_t *tso_seg;
  308. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  309. struct dp_soc *soc = vdev->pdev->soc;
  310. struct qdf_tso_info_t *tso_info;
  311. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  312. tso_info = &msdu_info->u.tso_info;
  313. tso_info->curr_seg = NULL;
  314. tso_info->tso_seg_list = NULL;
  315. tso_info->num_segs = num_seg;
  316. msdu_info->frm_type = dp_tx_frm_tso;
  317. tso_info->tso_num_seg_list = NULL;
  318. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  319. while (num_seg) {
  320. tso_seg = dp_tx_tso_desc_alloc(
  321. soc, msdu_info->tx_queue.desc_pool_id);
  322. if (tso_seg) {
  323. tso_seg->next = tso_info->tso_seg_list;
  324. tso_info->tso_seg_list = tso_seg;
  325. num_seg--;
  326. } else {
  327. struct qdf_tso_seg_elem_t *free_seg =
  328. tso_info->tso_seg_list;
  329. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  330. return QDF_STATUS_E_NOMEM;
  331. }
  332. }
  333. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  334. tso_num_seg = dp_tso_num_seg_alloc(soc,
  335. msdu_info->tx_queue.desc_pool_id);
  336. if (tso_num_seg) {
  337. tso_num_seg->next = tso_info->tso_num_seg_list;
  338. tso_info->tso_num_seg_list = tso_num_seg;
  339. } else {
  340. /* Bug: free tso_num_seg and tso_seg */
  341. /* Free the already allocated num of segments */
  342. struct qdf_tso_seg_elem_t *free_seg =
  343. tso_info->tso_seg_list;
  344. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  345. __func__);
  346. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  347. return QDF_STATUS_E_NOMEM;
  348. }
  349. msdu_info->num_seg =
  350. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  351. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  352. msdu_info->num_seg);
  353. if (!(msdu_info->num_seg)) {
  354. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  355. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  356. msdu_info);
  357. return QDF_STATUS_E_INVAL;
  358. }
  359. tso_info->curr_seg = tso_info->tso_seg_list;
  360. return QDF_STATUS_SUCCESS;
  361. }
  362. #else
  363. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  364. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  365. {
  366. return QDF_STATUS_E_NOMEM;
  367. }
  368. #endif
  369. /**
  370. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  371. * @vdev: DP Vdev handle
  372. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  373. * @desc_pool_id: Descriptor Pool ID
  374. *
  375. * Return:
  376. */
  377. static
  378. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  379. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  380. {
  381. uint8_t i;
  382. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  383. struct dp_tx_seg_info_s *seg_info;
  384. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  385. struct dp_soc *soc = vdev->pdev->soc;
  386. /* Allocate an extension descriptor */
  387. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  388. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  389. if (!msdu_ext_desc) {
  390. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  391. return NULL;
  392. }
  393. if (qdf_unlikely(vdev->mesh_vdev)) {
  394. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  395. &msdu_info->meta_data[0],
  396. sizeof(struct htt_tx_msdu_desc_ext2_t));
  397. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  398. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  399. }
  400. switch (msdu_info->frm_type) {
  401. case dp_tx_frm_sg:
  402. case dp_tx_frm_me:
  403. case dp_tx_frm_raw:
  404. seg_info = msdu_info->u.sg_info.curr_seg;
  405. /* Update the buffer pointers in MSDU Extension Descriptor */
  406. for (i = 0; i < seg_info->frag_cnt; i++) {
  407. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  408. seg_info->frags[i].paddr_lo,
  409. seg_info->frags[i].paddr_hi,
  410. seg_info->frags[i].len);
  411. }
  412. break;
  413. case dp_tx_frm_tso:
  414. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  415. &cached_ext_desc[0]);
  416. break;
  417. default:
  418. break;
  419. }
  420. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  421. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  422. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  423. msdu_ext_desc->vaddr);
  424. return msdu_ext_desc;
  425. }
  426. /**
  427. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  428. * @vdev: DP vdev handle
  429. * @nbuf: skb
  430. * @desc_pool_id: Descriptor pool ID
  431. * Allocate and prepare Tx descriptor with msdu information.
  432. *
  433. * Return: Pointer to Tx Descriptor on success,
  434. * NULL on failure
  435. */
  436. static
  437. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  438. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  439. uint32_t *meta_data)
  440. {
  441. uint8_t align_pad;
  442. uint8_t is_exception = 0;
  443. uint8_t htt_hdr_size;
  444. struct ether_header *eh;
  445. struct dp_tx_desc_s *tx_desc;
  446. struct dp_pdev *pdev = vdev->pdev;
  447. struct dp_soc *soc = pdev->soc;
  448. /* Allocate software Tx descriptor */
  449. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  450. if (qdf_unlikely(!tx_desc)) {
  451. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  452. "%s Tx Desc Alloc Failed\n", __func__);
  453. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  454. return NULL;
  455. }
  456. /* Flow control/Congestion Control counters */
  457. qdf_atomic_inc(&pdev->num_tx_outstanding);
  458. /* Initialize the SW tx descriptor */
  459. tx_desc->nbuf = nbuf;
  460. tx_desc->frm_type = dp_tx_frm_std;
  461. tx_desc->tx_encap_type = vdev->tx_encap_type;
  462. tx_desc->vdev = vdev;
  463. tx_desc->pdev = pdev;
  464. tx_desc->msdu_ext_desc = NULL;
  465. tx_desc->pkt_offset = 0;
  466. /*
  467. * For special modes (vdev_type == ocb or mesh), data frames should be
  468. * transmitted using varying transmit parameters (tx spec) which include
  469. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  470. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  471. * These frames are sent as exception packets to firmware.
  472. *
  473. * HW requirement is that metadata should always point to a
  474. * 8-byte aligned address. So we add alignment pad to start of buffer.
  475. * HTT Metadata should be ensured to be multiple of 8-bytes,
  476. * to get 8-byte aligned start address along with align_pad added
  477. *
  478. * |-----------------------------|
  479. * | |
  480. * |-----------------------------| <-----Buffer Pointer Address given
  481. * | | ^ in HW descriptor (aligned)
  482. * | HTT Metadata | |
  483. * | | |
  484. * | | | Packet Offset given in descriptor
  485. * | | |
  486. * |-----------------------------| |
  487. * | Alignment Pad | v
  488. * |-----------------------------| <----- Actual buffer start address
  489. * | SKB Data | (Unaligned)
  490. * | |
  491. * | |
  492. * | |
  493. * | |
  494. * | |
  495. * |-----------------------------|
  496. */
  497. if (qdf_unlikely(vdev->mesh_vdev ||
  498. (vdev->opmode == wlan_op_mode_ocb))) {
  499. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  500. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  501. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  502. "qdf_nbuf_push_head failed\n");
  503. goto failure;
  504. }
  505. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  506. meta_data);
  507. if (htt_hdr_size == 0)
  508. goto failure;
  509. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  510. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  511. is_exception = 1;
  512. }
  513. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  514. qdf_nbuf_map(soc->osdev, nbuf,
  515. QDF_DMA_TO_DEVICE))) {
  516. /* Handle failure */
  517. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  518. "qdf_nbuf_map failed\n");
  519. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  520. goto failure;
  521. }
  522. if (qdf_unlikely(vdev->nawds_enabled)) {
  523. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  524. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  525. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  526. is_exception = 1;
  527. }
  528. }
  529. #if !TQM_BYPASS_WAR
  530. if (is_exception)
  531. #endif
  532. {
  533. /* Temporary WAR due to TQM VP issues */
  534. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  535. qdf_atomic_inc(&pdev->num_tx_exception);
  536. }
  537. return tx_desc;
  538. failure:
  539. dp_tx_desc_release(tx_desc, desc_pool_id);
  540. return NULL;
  541. }
  542. /**
  543. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  544. * @vdev: DP vdev handle
  545. * @nbuf: skb
  546. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  547. * @desc_pool_id : Descriptor Pool ID
  548. *
  549. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  550. * information. For frames wth fragments, allocate and prepare
  551. * an MSDU extension descriptor
  552. *
  553. * Return: Pointer to Tx Descriptor on success,
  554. * NULL on failure
  555. */
  556. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  557. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  558. uint8_t desc_pool_id)
  559. {
  560. struct dp_tx_desc_s *tx_desc;
  561. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  562. struct dp_pdev *pdev = vdev->pdev;
  563. struct dp_soc *soc = pdev->soc;
  564. /* Allocate software Tx descriptor */
  565. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  566. if (!tx_desc) {
  567. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  568. return NULL;
  569. }
  570. /* Flow control/Congestion Control counters */
  571. qdf_atomic_inc(&pdev->num_tx_outstanding);
  572. /* Initialize the SW tx descriptor */
  573. tx_desc->nbuf = nbuf;
  574. tx_desc->frm_type = msdu_info->frm_type;
  575. tx_desc->tx_encap_type = vdev->tx_encap_type;
  576. tx_desc->vdev = vdev;
  577. tx_desc->pdev = pdev;
  578. tx_desc->pkt_offset = 0;
  579. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  580. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  581. /* Handle scattered frames - TSO/SG/ME */
  582. /* Allocate and prepare an extension descriptor for scattered frames */
  583. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  584. if (!msdu_ext_desc) {
  585. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  586. "%s Tx Extension Descriptor Alloc Fail\n",
  587. __func__);
  588. goto failure;
  589. }
  590. #if TQM_BYPASS_WAR
  591. /* Temporary WAR due to TQM VP issues */
  592. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  593. qdf_atomic_inc(&pdev->num_tx_exception);
  594. #endif
  595. if (qdf_unlikely(vdev->mesh_vdev))
  596. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  597. tx_desc->msdu_ext_desc = msdu_ext_desc;
  598. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  599. return tx_desc;
  600. failure:
  601. dp_tx_desc_release(tx_desc, desc_pool_id);
  602. return NULL;
  603. }
  604. /**
  605. * dp_tx_prepare_raw() - Prepare RAW packet TX
  606. * @vdev: DP vdev handle
  607. * @nbuf: buffer pointer
  608. * @seg_info: Pointer to Segment info Descriptor to be prepared
  609. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  610. * descriptor
  611. *
  612. * Return:
  613. */
  614. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  615. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  616. {
  617. qdf_nbuf_t curr_nbuf = NULL;
  618. uint16_t total_len = 0;
  619. qdf_dma_addr_t paddr;
  620. int32_t i;
  621. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  622. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  623. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  624. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  625. if ((qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  626. && (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU)) {
  627. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  628. }
  629. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  630. QDF_DMA_TO_DEVICE)) {
  631. qdf_print("dma map error\n");
  632. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  633. qdf_nbuf_free(nbuf);
  634. return NULL;
  635. }
  636. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  637. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  638. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  639. seg_info->frags[i].paddr_lo = paddr;
  640. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  641. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  642. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  643. total_len += qdf_nbuf_len(curr_nbuf);
  644. }
  645. seg_info->frag_cnt = i;
  646. seg_info->total_len = total_len;
  647. seg_info->next = NULL;
  648. sg_info->curr_seg = seg_info;
  649. msdu_info->frm_type = dp_tx_frm_raw;
  650. msdu_info->num_seg = 1;
  651. return nbuf;
  652. }
  653. /**
  654. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  655. * @soc: DP Soc Handle
  656. * @vdev: DP vdev handle
  657. * @tx_desc: Tx Descriptor Handle
  658. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  659. * @fw_metadata: Metadata to send to Target Firmware along with frame
  660. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  661. *
  662. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  663. * from software Tx descriptor
  664. *
  665. * Return:
  666. */
  667. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  668. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  669. uint16_t fw_metadata, uint8_t ring_id)
  670. {
  671. uint8_t type;
  672. uint16_t length;
  673. void *hal_tx_desc, *hal_tx_desc_cached;
  674. qdf_dma_addr_t dma_addr;
  675. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  676. /* Return Buffer Manager ID */
  677. uint8_t bm_id = ring_id;
  678. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  679. hal_tx_desc_cached = (void *) cached_desc;
  680. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  681. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  682. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  683. type = HAL_TX_BUF_TYPE_EXT_DESC;
  684. dma_addr = tx_desc->msdu_ext_desc->paddr;
  685. } else {
  686. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  687. type = HAL_TX_BUF_TYPE_BUFFER;
  688. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  689. }
  690. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  691. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  692. dma_addr , bm_id, tx_desc->id, type);
  693. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  694. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  695. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  696. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  697. vdev->dscp_tid_map_id);
  698. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  699. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  700. __func__, length, type, (uint64_t)dma_addr,
  701. tx_desc->pkt_offset, tx_desc->id);
  702. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  703. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  704. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  705. vdev->hal_desc_addr_search_flags);
  706. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  707. || qdf_nbuf_is_tso(tx_desc->nbuf)) {
  708. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  709. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  710. }
  711. if (tid != HTT_TX_EXT_TID_INVALID)
  712. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  713. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  714. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  715. /* Sync cached descriptor with HW */
  716. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  717. if (!hal_tx_desc) {
  718. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  719. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  720. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  721. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  722. return QDF_STATUS_E_RESOURCES;
  723. }
  724. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  725. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  726. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  727. /*
  728. * If one packet is enqueued in HW, PM usage count needs to be
  729. * incremented by one to prevent future runtime suspend. This
  730. * should be tied with the success of enqueuing. It will be
  731. * decremented after the packet has been sent.
  732. */
  733. hif_pm_runtime_get_noresume(soc->hif_handle);
  734. return QDF_STATUS_SUCCESS;
  735. }
  736. /**
  737. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  738. * @vdev: DP vdev handle
  739. * @nbuf: skb
  740. *
  741. * Extract the DSCP or PCP information from frame and map into TID value.
  742. * Software based TID classification is required when more than 2 DSCP-TID
  743. * mapping tables are needed.
  744. * Hardware supports 2 DSCP-TID mapping tables
  745. *
  746. * Return: void
  747. */
  748. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  749. struct dp_tx_msdu_info_s *msdu_info)
  750. {
  751. uint8_t tos = 0, dscp_tid_override = 0;
  752. uint8_t *hdr_ptr, *L3datap;
  753. uint8_t is_mcast = 0;
  754. struct ether_header *eh = NULL;
  755. qdf_ethervlan_header_t *evh = NULL;
  756. uint16_t ether_type;
  757. qdf_llc_t *llcHdr;
  758. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  759. /* for mesh packets don't do any classification */
  760. if (qdf_unlikely(vdev->mesh_vdev))
  761. return;
  762. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  763. eh = (struct ether_header *) nbuf->data;
  764. hdr_ptr = eh->ether_dhost;
  765. L3datap = hdr_ptr + sizeof(struct ether_header);
  766. } else {
  767. qdf_dot3_qosframe_t *qos_wh =
  768. (qdf_dot3_qosframe_t *) nbuf->data;
  769. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  770. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  771. return;
  772. }
  773. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  774. ether_type = eh->ether_type;
  775. /*
  776. * Check if packet is dot3 or eth2 type.
  777. */
  778. if (IS_LLC_PRESENT(ether_type)) {
  779. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  780. sizeof(*llcHdr));
  781. if (ether_type == htons(ETHERTYPE_8021Q)) {
  782. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  783. sizeof(*llcHdr);
  784. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  785. + sizeof(*llcHdr) +
  786. sizeof(qdf_net_vlanhdr_t));
  787. } else {
  788. L3datap = hdr_ptr + sizeof(struct ether_header) +
  789. sizeof(*llcHdr);
  790. }
  791. } else {
  792. if (ether_type == htons(ETHERTYPE_8021Q)) {
  793. evh = (qdf_ethervlan_header_t *) eh;
  794. ether_type = evh->ether_type;
  795. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  796. }
  797. }
  798. /*
  799. * Find priority from IP TOS DSCP field
  800. */
  801. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  802. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  803. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  804. /* Only for unicast frames */
  805. if (!is_mcast) {
  806. /* send it on VO queue */
  807. msdu_info->tid = DP_VO_TID;
  808. }
  809. } else {
  810. /*
  811. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  812. * from TOS byte.
  813. */
  814. tos = ip->ip_tos;
  815. dscp_tid_override = 1;
  816. }
  817. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  818. /* TODO
  819. * use flowlabel
  820. *igmpmld cases to be handled in phase 2
  821. */
  822. unsigned long ver_pri_flowlabel;
  823. unsigned long pri;
  824. ver_pri_flowlabel = *(unsigned long *) L3datap;
  825. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  826. DP_IPV6_PRIORITY_SHIFT;
  827. tos = pri;
  828. dscp_tid_override = 1;
  829. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  830. msdu_info->tid = DP_VO_TID;
  831. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  832. /* Only for unicast frames */
  833. if (!is_mcast) {
  834. /* send ucast arp on VO queue */
  835. msdu_info->tid = DP_VO_TID;
  836. }
  837. }
  838. /*
  839. * Assign all MCAST packets to BE
  840. */
  841. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  842. if (is_mcast) {
  843. tos = 0;
  844. dscp_tid_override = 1;
  845. }
  846. }
  847. if (dscp_tid_override == 1) {
  848. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  849. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  850. }
  851. return;
  852. }
  853. #ifdef CONVERGED_TDLS_ENABLE
  854. /**
  855. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  856. * @tx_desc: TX descriptor
  857. *
  858. * Return: None
  859. */
  860. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  861. {
  862. if (tx_desc->vdev) {
  863. if (tx_desc->vdev->is_tdls_frame)
  864. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  865. tx_desc->vdev->is_tdls_frame = false;
  866. }
  867. }
  868. /**
  869. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  870. * @tx_desc: TX descriptor
  871. * @vdev: datapath vdev handle
  872. *
  873. * Return: None
  874. */
  875. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  876. struct dp_vdev *vdev)
  877. {
  878. struct hal_tx_completion_status ts = {0};
  879. qdf_nbuf_t nbuf = tx_desc->nbuf;
  880. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  881. if (vdev->tx_non_std_data_callback.func) {
  882. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  883. vdev->tx_non_std_data_callback.func(
  884. vdev->tx_non_std_data_callback.ctxt,
  885. nbuf, ts.status);
  886. return;
  887. }
  888. }
  889. #endif
  890. /**
  891. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  892. * @vdev: DP vdev handle
  893. * @nbuf: skb
  894. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  895. * @tx_q: Tx queue to be used for this Tx frame
  896. * @peer_id: peer_id of the peer in case of NAWDS frames
  897. *
  898. * Return: NULL on success,
  899. * nbuf when it fails to send
  900. */
  901. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  902. uint8_t tid, struct dp_tx_queue *tx_q,
  903. uint32_t *meta_data, uint16_t peer_id)
  904. {
  905. struct dp_pdev *pdev = vdev->pdev;
  906. struct dp_soc *soc = pdev->soc;
  907. struct dp_tx_desc_s *tx_desc;
  908. QDF_STATUS status;
  909. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  910. uint16_t htt_tcl_metadata = 0;
  911. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 0);
  912. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  913. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id, meta_data);
  914. if (!tx_desc) {
  915. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  916. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  917. __func__, vdev, tx_q->desc_pool_id);
  918. return nbuf;
  919. }
  920. dp_tx_update_tdls_flags(tx_desc);
  921. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  922. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  923. "%s %d : HAL RING Access Failed -- %pK\n",
  924. __func__, __LINE__, hal_srng);
  925. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  926. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  927. goto fail_return;
  928. }
  929. if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  930. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  931. HTT_TCL_METADATA_TYPE_PEER_BASED);
  932. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  933. peer_id);
  934. } else
  935. htt_tcl_metadata = vdev->htt_tcl_metadata;
  936. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  937. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  938. htt_tcl_metadata, tx_q->ring_id);
  939. if (status != QDF_STATUS_SUCCESS) {
  940. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  941. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  942. __func__, tx_desc, tx_q->ring_id);
  943. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  944. goto fail_return;
  945. }
  946. nbuf = NULL;
  947. fail_return:
  948. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  949. hal_srng_access_end(soc->hal_soc, hal_srng);
  950. hif_pm_runtime_put(soc->hif_handle);
  951. } else {
  952. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  953. }
  954. return nbuf;
  955. }
  956. /**
  957. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  958. * @vdev: DP vdev handle
  959. * @nbuf: skb
  960. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  961. *
  962. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  963. *
  964. * Return: NULL on success,
  965. * nbuf when it fails to send
  966. */
  967. #if QDF_LOCK_STATS
  968. static noinline
  969. #else
  970. static
  971. #endif
  972. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  973. struct dp_tx_msdu_info_s *msdu_info)
  974. {
  975. uint8_t i;
  976. struct dp_pdev *pdev = vdev->pdev;
  977. struct dp_soc *soc = pdev->soc;
  978. struct dp_tx_desc_s *tx_desc;
  979. QDF_STATUS status;
  980. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  981. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  982. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  983. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  984. "%s %d : HAL RING Access Failed -- %pK\n",
  985. __func__, __LINE__, hal_srng);
  986. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  987. return nbuf;
  988. }
  989. if (msdu_info->frm_type == dp_tx_frm_me)
  990. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  991. i = 0;
  992. /* Print statement to track i and num_seg */
  993. /*
  994. * For each segment (maps to 1 MSDU) , prepare software and hardware
  995. * descriptors using information in msdu_info
  996. */
  997. while (i < msdu_info->num_seg) {
  998. /*
  999. * Setup Tx descriptor for an MSDU, and MSDU extension
  1000. * descriptor
  1001. */
  1002. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1003. tx_q->desc_pool_id);
  1004. if (!tx_desc) {
  1005. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1006. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1007. __func__, vdev, tx_q->desc_pool_id);
  1008. if (msdu_info->frm_type == dp_tx_frm_me) {
  1009. dp_tx_me_free_buf(pdev,
  1010. (void *)(msdu_info->u.sg_info
  1011. .curr_seg->frags[0].vaddr));
  1012. }
  1013. goto done;
  1014. }
  1015. if (msdu_info->frm_type == dp_tx_frm_me) {
  1016. tx_desc->me_buffer =
  1017. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1018. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1019. }
  1020. /*
  1021. * Enqueue the Tx MSDU descriptor to HW for transmit
  1022. */
  1023. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1024. vdev->htt_tcl_metadata, tx_q->ring_id);
  1025. if (status != QDF_STATUS_SUCCESS) {
  1026. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1027. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1028. __func__, tx_desc, tx_q->ring_id);
  1029. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1030. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1031. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1032. goto done;
  1033. }
  1034. /*
  1035. * TODO
  1036. * if tso_info structure can be modified to have curr_seg
  1037. * as first element, following 2 blocks of code (for TSO and SG)
  1038. * can be combined into 1
  1039. */
  1040. /*
  1041. * For frames with multiple segments (TSO, ME), jump to next
  1042. * segment.
  1043. */
  1044. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1045. if (msdu_info->u.tso_info.curr_seg->next) {
  1046. msdu_info->u.tso_info.curr_seg =
  1047. msdu_info->u.tso_info.curr_seg->next;
  1048. /*
  1049. * If this is a jumbo nbuf, then increment the number of
  1050. * nbuf users for each additional segment of the msdu.
  1051. * This will ensure that the skb is freed only after
  1052. * receiving tx completion for all segments of an nbuf
  1053. */
  1054. qdf_nbuf_inc_users(nbuf);
  1055. /* Check with MCL if this is needed */
  1056. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1057. }
  1058. }
  1059. /*
  1060. * For Multicast-Unicast converted packets,
  1061. * each converted frame (for a client) is represented as
  1062. * 1 segment
  1063. */
  1064. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1065. (msdu_info->frm_type == dp_tx_frm_me)) {
  1066. if (msdu_info->u.sg_info.curr_seg->next) {
  1067. msdu_info->u.sg_info.curr_seg =
  1068. msdu_info->u.sg_info.curr_seg->next;
  1069. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1070. }
  1071. }
  1072. i++;
  1073. }
  1074. nbuf = NULL;
  1075. done:
  1076. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1077. hal_srng_access_end(soc->hal_soc, hal_srng);
  1078. hif_pm_runtime_put(soc->hif_handle);
  1079. } else {
  1080. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1081. }
  1082. return nbuf;
  1083. }
  1084. /**
  1085. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1086. * for SG frames
  1087. * @vdev: DP vdev handle
  1088. * @nbuf: skb
  1089. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1090. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1091. *
  1092. * Return: NULL on success,
  1093. * nbuf when it fails to send
  1094. */
  1095. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1096. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1097. {
  1098. uint32_t cur_frag, nr_frags;
  1099. qdf_dma_addr_t paddr;
  1100. struct dp_tx_sg_info_s *sg_info;
  1101. sg_info = &msdu_info->u.sg_info;
  1102. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1103. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1104. QDF_DMA_TO_DEVICE)) {
  1105. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1106. "dma map error\n");
  1107. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1108. qdf_nbuf_free(nbuf);
  1109. return NULL;
  1110. }
  1111. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1112. seg_info->frags[0].paddr_lo = paddr;
  1113. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1114. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1115. seg_info->frags[0].vaddr = (void *) nbuf;
  1116. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1117. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1118. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1119. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1120. "frag dma map error\n");
  1121. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1122. qdf_nbuf_free(nbuf);
  1123. return NULL;
  1124. }
  1125. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1126. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1127. seg_info->frags[cur_frag + 1].paddr_hi =
  1128. ((uint64_t) paddr) >> 32;
  1129. seg_info->frags[cur_frag + 1].len =
  1130. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1131. }
  1132. seg_info->frag_cnt = (cur_frag + 1);
  1133. seg_info->total_len = qdf_nbuf_len(nbuf);
  1134. seg_info->next = NULL;
  1135. sg_info->curr_seg = seg_info;
  1136. msdu_info->frm_type = dp_tx_frm_sg;
  1137. msdu_info->num_seg = 1;
  1138. return nbuf;
  1139. }
  1140. #ifdef MESH_MODE_SUPPORT
  1141. /**
  1142. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1143. and prepare msdu_info for mesh frames.
  1144. * @vdev: DP vdev handle
  1145. * @nbuf: skb
  1146. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1147. *
  1148. * Return: NULL on failure,
  1149. * nbuf when extracted successfully
  1150. */
  1151. static
  1152. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1153. struct dp_tx_msdu_info_s *msdu_info)
  1154. {
  1155. struct meta_hdr_s *mhdr;
  1156. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1157. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1158. nbuf = qdf_nbuf_unshare(nbuf);
  1159. if (nbuf == NULL) {
  1160. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1161. "qdf_nbuf_unshare failed\n");
  1162. return nbuf;
  1163. }
  1164. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1165. qdf_mem_set(meta_data, 0, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1166. meta_data->host_tx_desc_pool = 1;
  1167. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1168. meta_data->power = mhdr->power;
  1169. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1170. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1171. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1172. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1173. meta_data->dyn_bw = 1;
  1174. meta_data->valid_pwr = 1;
  1175. meta_data->valid_mcs_mask = 1;
  1176. meta_data->valid_nss_mask = 1;
  1177. meta_data->valid_preamble_type = 1;
  1178. meta_data->valid_retries = 1;
  1179. meta_data->valid_bw_info = 1;
  1180. }
  1181. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1182. meta_data->encrypt_type = 0;
  1183. meta_data->valid_encrypt_type = 1;
  1184. }
  1185. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1186. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1187. else
  1188. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1189. meta_data->valid_key_flags = 1;
  1190. meta_data->key_flags = (mhdr->keyix & 0x3);
  1191. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1192. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1193. "qdf_nbuf_pull_head failed\n");
  1194. qdf_nbuf_free(nbuf);
  1195. return NULL;
  1196. }
  1197. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1198. "%s , Meta hdr %0x %0x %0x %0x %0x\n",
  1199. __func__, msdu_info->meta_data[0],
  1200. msdu_info->meta_data[1],
  1201. msdu_info->meta_data[2],
  1202. msdu_info->meta_data[3],
  1203. msdu_info->meta_data[4]);
  1204. return nbuf;
  1205. }
  1206. #else
  1207. static
  1208. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1209. struct dp_tx_msdu_info_s *msdu_info)
  1210. {
  1211. return nbuf;
  1212. }
  1213. #endif
  1214. /**
  1215. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1216. * @vdev: dp_vdev handle
  1217. * @nbuf: skb
  1218. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1219. * @tx_q: Tx queue to be used for this Tx frame
  1220. * @meta_data: Meta date for mesh
  1221. * @peer_id: peer_id of the peer in case of NAWDS frames
  1222. *
  1223. * return: NULL on success nbuf on failure
  1224. */
  1225. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1226. uint8_t tid, struct dp_tx_queue *tx_q, uint32_t *meta_data,
  1227. uint32_t peer_id)
  1228. {
  1229. struct dp_peer *peer = NULL;
  1230. qdf_nbuf_t nbuf_copy;
  1231. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1232. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1233. (peer->nawds_enabled || peer->bss_peer)) {
  1234. nbuf_copy = qdf_nbuf_copy(nbuf);
  1235. if (!nbuf_copy) {
  1236. QDF_TRACE(QDF_MODULE_ID_DP,
  1237. QDF_TRACE_LEVEL_ERROR,
  1238. "nbuf copy failed");
  1239. }
  1240. peer_id = peer->peer_ids[0];
  1241. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy, tid,
  1242. tx_q, meta_data, peer_id);
  1243. if (nbuf_copy != NULL) {
  1244. qdf_nbuf_free(nbuf);
  1245. return nbuf_copy;
  1246. }
  1247. }
  1248. }
  1249. if (peer_id == HTT_INVALID_PEER)
  1250. return nbuf;
  1251. qdf_nbuf_free(nbuf);
  1252. return NULL;
  1253. }
  1254. /**
  1255. * dp_tx_send() - Transmit a frame on a given VAP
  1256. * @vap_dev: DP vdev handle
  1257. * @nbuf: skb
  1258. *
  1259. * Entry point for Core Tx layer (DP_TX) invoked from
  1260. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1261. * cases
  1262. *
  1263. * Return: NULL on success,
  1264. * nbuf when it fails to send
  1265. */
  1266. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1267. {
  1268. struct ether_header *eh = NULL;
  1269. struct dp_tx_msdu_info_s msdu_info;
  1270. struct dp_tx_seg_info_s seg_info;
  1271. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1272. uint16_t peer_id = HTT_INVALID_PEER;
  1273. qdf_nbuf_t nbuf_mesh = NULL;
  1274. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1275. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1276. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1277. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1278. "%s , skb %0x:%0x:%0x:%0x:%0x:%0x\n",
  1279. __func__, nbuf->data[0], nbuf->data[1], nbuf->data[2],
  1280. nbuf->data[3], nbuf->data[4], nbuf->data[5]);
  1281. /*
  1282. * Set Default Host TID value to invalid TID
  1283. * (TID override disabled)
  1284. */
  1285. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1286. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1287. if (qdf_unlikely(vdev->mesh_vdev)) {
  1288. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1289. &msdu_info);
  1290. if (nbuf_mesh == NULL) {
  1291. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1292. "Extracting mesh metadata failed\n");
  1293. return nbuf;
  1294. }
  1295. nbuf = nbuf_mesh;
  1296. }
  1297. /*
  1298. * Get HW Queue to use for this frame.
  1299. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1300. * dedicated for data and 1 for command.
  1301. * "queue_id" maps to one hardware ring.
  1302. * With each ring, we also associate a unique Tx descriptor pool
  1303. * to minimize lock contention for these resources.
  1304. */
  1305. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1306. /*
  1307. * TCL H/W supports 2 DSCP-TID mapping tables.
  1308. * Table 1 - Default DSCP-TID mapping table
  1309. * Table 2 - 1 DSCP-TID override table
  1310. *
  1311. * If we need a different DSCP-TID mapping for this vap,
  1312. * call tid_classify to extract DSCP/ToS from frame and
  1313. * map to a TID and store in msdu_info. This is later used
  1314. * to fill in TCL Input descriptor (per-packet TID override).
  1315. */
  1316. if (vdev->dscp_tid_map_id > 1)
  1317. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1318. /* Reset the control block */
  1319. qdf_nbuf_reset_ctxt(nbuf);
  1320. /*
  1321. * Classify the frame and call corresponding
  1322. * "prepare" function which extracts the segment (TSO)
  1323. * and fragmentation information (for TSO , SG, ME, or Raw)
  1324. * into MSDU_INFO structure which is later used to fill
  1325. * SW and HW descriptors.
  1326. */
  1327. if (qdf_nbuf_is_tso(nbuf)) {
  1328. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1329. "%s TSO frame %pK\n", __func__, vdev);
  1330. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1331. qdf_nbuf_len(nbuf));
  1332. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1333. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1334. "%s tso_prepare fail vdev_id:%d\n",
  1335. __func__, vdev->vdev_id);
  1336. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1337. return nbuf;
  1338. }
  1339. goto send_multiple;
  1340. }
  1341. /* SG */
  1342. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1343. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1344. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1345. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1346. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1347. qdf_nbuf_len(nbuf));
  1348. goto send_multiple;
  1349. }
  1350. #ifdef ATH_SUPPORT_IQUE
  1351. /* Mcast to Ucast Conversion*/
  1352. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1353. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1354. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1355. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1356. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1357. DP_STATS_INC_PKT(vdev,
  1358. tx_i.mcast_en.mcast_pkt, 1,
  1359. qdf_nbuf_len(nbuf));
  1360. if (dp_tx_prepare_send_me(vdev, nbuf)) {
  1361. qdf_nbuf_free(nbuf);
  1362. return NULL;
  1363. }
  1364. return nbuf;
  1365. }
  1366. }
  1367. #endif
  1368. /* RAW */
  1369. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1370. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1371. if (nbuf == NULL)
  1372. return NULL;
  1373. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1374. "%s Raw frame %pK\n", __func__, vdev);
  1375. goto send_multiple;
  1376. }
  1377. if (vdev->nawds_enabled) {
  1378. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1379. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1380. nbuf = dp_tx_prepare_nawds(vdev, nbuf, msdu_info.tid,
  1381. &msdu_info.tx_queue,
  1382. msdu_info.meta_data, peer_id);
  1383. return nbuf;
  1384. }
  1385. }
  1386. /* Single linear frame */
  1387. /*
  1388. * If nbuf is a simple linear frame, use send_single function to
  1389. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1390. * SRNG. There is no need to setup a MSDU extension descriptor.
  1391. */
  1392. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info.tid,
  1393. &msdu_info.tx_queue, msdu_info.meta_data, peer_id);
  1394. return nbuf;
  1395. send_multiple:
  1396. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1397. return nbuf;
  1398. }
  1399. /**
  1400. * dp_tx_reinject_handler() - Tx Reinject Handler
  1401. * @tx_desc: software descriptor head pointer
  1402. * @status : Tx completion status from HTT descriptor
  1403. *
  1404. * This function reinjects frames back to Target.
  1405. * Todo - Host queue needs to be added
  1406. *
  1407. * Return: none
  1408. */
  1409. static
  1410. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1411. {
  1412. struct dp_vdev *vdev;
  1413. struct dp_peer *peer = NULL;
  1414. uint32_t peer_id = HTT_INVALID_PEER;
  1415. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1416. qdf_nbuf_t nbuf_copy = NULL;
  1417. struct dp_tx_msdu_info_s msdu_info;
  1418. vdev = tx_desc->vdev;
  1419. qdf_assert(vdev);
  1420. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1421. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1422. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1423. "%s Tx reinject path\n", __func__);
  1424. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1425. qdf_nbuf_len(tx_desc->nbuf));
  1426. if (!vdev->osif_proxy_arp) {
  1427. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1428. "function pointer to proxy arp not present\n");
  1429. return;
  1430. }
  1431. if (qdf_unlikely(vdev->mesh_vdev)) {
  1432. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1433. } else {
  1434. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1435. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1436. (peer->bss_peer || peer->nawds_enabled)
  1437. && !(vdev->osif_proxy_arp(
  1438. vdev->osif_vdev,
  1439. nbuf))) {
  1440. nbuf_copy = qdf_nbuf_copy(nbuf);
  1441. if (!nbuf_copy) {
  1442. QDF_TRACE(QDF_MODULE_ID_DP,
  1443. QDF_TRACE_LEVEL_DEBUG,
  1444. FL("nbuf copy failed"));
  1445. break;
  1446. }
  1447. if (peer->nawds_enabled)
  1448. peer_id = peer->peer_ids[0];
  1449. else
  1450. peer_id = HTT_INVALID_PEER;
  1451. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1452. nbuf_copy, msdu_info.tid,
  1453. &msdu_info.tx_queue,
  1454. msdu_info.meta_data, peer_id);
  1455. if (nbuf_copy) {
  1456. QDF_TRACE(QDF_MODULE_ID_DP,
  1457. QDF_TRACE_LEVEL_DEBUG,
  1458. FL("pkt send failed"));
  1459. qdf_nbuf_free(nbuf_copy);
  1460. }
  1461. }
  1462. }
  1463. }
  1464. qdf_nbuf_free(nbuf);
  1465. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1466. }
  1467. /**
  1468. * dp_tx_inspect_handler() - Tx Inspect Handler
  1469. * @tx_desc: software descriptor head pointer
  1470. * @status : Tx completion status from HTT descriptor
  1471. *
  1472. * Handles Tx frames sent back to Host for inspection
  1473. * (ProxyARP)
  1474. *
  1475. * Return: none
  1476. */
  1477. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1478. {
  1479. struct dp_soc *soc;
  1480. struct dp_pdev *pdev = tx_desc->pdev;
  1481. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1482. "%s Tx inspect path\n",
  1483. __func__);
  1484. qdf_assert(pdev);
  1485. soc = pdev->soc;
  1486. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1487. qdf_nbuf_len(tx_desc->nbuf));
  1488. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1489. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1490. }
  1491. #ifdef FEATURE_PERPKT_INFO
  1492. static QDF_STATUS
  1493. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  1494. uint16_t peer_id, uint32_t ppdu_id)
  1495. {
  1496. struct tx_capture_hdr *ppdu_hdr;
  1497. struct dp_peer *peer = NULL;
  1498. qdf_nbuf_t netbuf = desc->nbuf;
  1499. if (!desc->pdev->tx_sniffer_enable)
  1500. return QDF_STATUS_E_NOSUPPORT;
  1501. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1502. dp_peer_find_by_id(soc, peer_id);
  1503. if (!peer) {
  1504. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1505. FL("Peer Invalid"));
  1506. return QDF_STATUS_E_INVAL;
  1507. }
  1508. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1509. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1510. FL("No headroom"));
  1511. return QDF_STATUS_E_NOMEM;
  1512. }
  1513. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1514. qdf_mem_copy(ppdu_hdr->ta, desc->vdev->mac_addr.raw, IEEE80211_ADDR_LEN);
  1515. ppdu_hdr->ppdu_id = ppdu_id;
  1516. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1517. IEEE80211_ADDR_LEN);
  1518. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1519. netbuf, peer_id,
  1520. WDI_NO_VAL, desc->pdev->pdev_id);
  1521. return QDF_STATUS_SUCCESS;
  1522. }
  1523. #else
  1524. static QDF_STATUS
  1525. dp_send_compl_to_stack(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  1526. uint16_t peer_id, uint32_t ppdu_id)
  1527. {
  1528. return QDF_STATUS_E_NOSUPPORT;
  1529. }
  1530. #endif
  1531. /**
  1532. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1533. * @soc: Soc handle
  1534. * @desc: software Tx descriptor to be processed
  1535. *
  1536. * Return: none
  1537. */
  1538. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1539. struct dp_tx_desc_s *desc)
  1540. {
  1541. struct dp_vdev *vdev = desc->vdev;
  1542. qdf_nbuf_t nbuf = desc->nbuf;
  1543. struct hal_tx_completion_status ts = {0};
  1544. if (desc)
  1545. hal_tx_comp_get_status(&desc->comp, &ts);
  1546. /* If it is TDLS mgmt, don't unmap or free the frame */
  1547. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1548. return dp_non_std_tx_comp_free_buff(desc, vdev);
  1549. /* 0 : MSDU buffer, 1 : MLE */
  1550. if (desc->msdu_ext_desc) {
  1551. /* TSO free */
  1552. if (hal_tx_ext_desc_get_tso_enable(
  1553. desc->msdu_ext_desc->vaddr)) {
  1554. /* If remaining number of segment is 0
  1555. * actual TSO may unmap and free */
  1556. if (!DP_DESC_NUM_FRAG(desc)) {
  1557. qdf_nbuf_unmap(soc->osdev, nbuf,
  1558. QDF_DMA_TO_DEVICE);
  1559. qdf_nbuf_free(nbuf);
  1560. return;
  1561. }
  1562. }
  1563. }
  1564. if (desc->flags & DP_TX_DESC_FLAG_ME)
  1565. dp_tx_me_free_buf(desc->pdev, desc->me_buffer);
  1566. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1567. if (dp_send_compl_to_stack(soc, desc, ts.peer_id, ts.ppdu_id) ==
  1568. QDF_STATUS_SUCCESS)
  1569. return;
  1570. if (!vdev->mesh_vdev) {
  1571. qdf_nbuf_free(nbuf);
  1572. } else {
  1573. vdev->osif_tx_free_ext((nbuf));
  1574. }
  1575. }
  1576. /**
  1577. * dp_tx_mec_handler() - Tx MEC Notify Handler
  1578. * @vdev: pointer to dp dev handler
  1579. * @status : Tx completion status from HTT descriptor
  1580. *
  1581. * Handles MEC notify event sent from fw to Host
  1582. *
  1583. * Return: none
  1584. */
  1585. #ifdef FEATURE_WDS
  1586. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1587. {
  1588. struct dp_soc *soc;
  1589. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  1590. struct dp_peer *peer;
  1591. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  1592. soc = vdev->pdev->soc;
  1593. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1594. peer = TAILQ_FIRST(&vdev->peer_list);
  1595. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1596. if (!peer) {
  1597. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1598. FL("peer is NULL"));
  1599. return;
  1600. }
  1601. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1602. "%s Tx MEC Handler\n",
  1603. __func__);
  1604. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  1605. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  1606. status[(DP_MAC_ADDR_LEN - 2) + i];
  1607. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN) &&
  1608. !dp_peer_add_ast(soc, peer, mac_addr, 2)) {
  1609. soc->cdp_soc.ol_ops->peer_add_wds_entry(
  1610. vdev->pdev->osif_pdev,
  1611. mac_addr,
  1612. vdev->mac_addr.raw,
  1613. flags);
  1614. }
  1615. }
  1616. #else
  1617. static void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1618. {
  1619. }
  1620. #endif
  1621. /**
  1622. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  1623. * @tx_desc: software descriptor head pointer
  1624. * @status : Tx completion status from HTT descriptor
  1625. *
  1626. * This function will process HTT Tx indication messages from Target
  1627. *
  1628. * Return: none
  1629. */
  1630. static
  1631. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1632. {
  1633. uint8_t tx_status;
  1634. struct dp_pdev *pdev;
  1635. struct dp_vdev *vdev;
  1636. struct dp_soc *soc;
  1637. uint32_t *htt_status_word = (uint32_t *) status;
  1638. qdf_assert(tx_desc->pdev);
  1639. pdev = tx_desc->pdev;
  1640. vdev = tx_desc->vdev;
  1641. soc = pdev->soc;
  1642. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  1643. switch (tx_status) {
  1644. case HTT_TX_FW2WBM_TX_STATUS_OK:
  1645. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  1646. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  1647. {
  1648. dp_tx_comp_free_buf(soc, tx_desc);
  1649. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1650. break;
  1651. }
  1652. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  1653. {
  1654. dp_tx_reinject_handler(tx_desc, status);
  1655. break;
  1656. }
  1657. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  1658. {
  1659. dp_tx_inspect_handler(tx_desc, status);
  1660. break;
  1661. }
  1662. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  1663. {
  1664. dp_tx_mec_handler(vdev, status);
  1665. break;
  1666. }
  1667. default:
  1668. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1669. "%s Invalid HTT tx_status %d\n",
  1670. __func__, tx_status);
  1671. break;
  1672. }
  1673. }
  1674. #ifdef MESH_MODE_SUPPORT
  1675. /**
  1676. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  1677. * in mesh meta header
  1678. * @tx_desc: software descriptor head pointer
  1679. * @ts: pointer to tx completion stats
  1680. * Return: none
  1681. */
  1682. static
  1683. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1684. struct hal_tx_completion_status *ts)
  1685. {
  1686. struct meta_hdr_s *mhdr;
  1687. qdf_nbuf_t netbuf = tx_desc->nbuf;
  1688. if (!tx_desc->msdu_ext_desc) {
  1689. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  1690. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1691. "netbuf %pK offset %d\n",
  1692. netbuf, tx_desc->pkt_offset);
  1693. return;
  1694. }
  1695. }
  1696. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1697. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1698. "netbuf %pK offset %d\n", netbuf,
  1699. sizeof(struct meta_hdr_s));
  1700. return;
  1701. }
  1702. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  1703. mhdr->rssi = ts->ack_frame_rssi;
  1704. mhdr->channel = tx_desc->pdev->operating_channel;
  1705. }
  1706. #else
  1707. static
  1708. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1709. struct hal_tx_completion_status *ts)
  1710. {
  1711. }
  1712. #endif
  1713. /**
  1714. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  1715. * @peer: Handle to DP peer
  1716. * @ts: pointer to HAL Tx completion stats
  1717. * @length: MSDU length
  1718. *
  1719. * Return: None
  1720. */
  1721. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  1722. struct hal_tx_completion_status *ts, uint32_t length)
  1723. {
  1724. struct dp_pdev *pdev = peer->vdev->pdev;
  1725. struct dp_soc *soc = pdev->soc;
  1726. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  1727. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  1728. return;
  1729. DP_STATS_INCC(peer, tx.tx_failed, 1,
  1730. !(ts->status == HAL_TX_TQM_RR_FRAME_ACKED));
  1731. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  1732. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  1733. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  1734. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  1735. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  1736. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  1737. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  1738. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  1739. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  1740. return;
  1741. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1742. ((ts->mcs >= MAX_MCS_11A) && (ts->pkt_type == DOT11_A)));
  1743. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1744. ((ts->mcs <= MAX_MCS_11A) && (ts->pkt_type == DOT11_A)));
  1745. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1746. ((ts->mcs >= MAX_MCS_11B) && (ts->pkt_type == DOT11_B)));
  1747. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1748. ((ts->mcs <= MAX_MCS_11B) && (ts->pkt_type == DOT11_B)));
  1749. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1750. ((ts->mcs >= MAX_MCS_11A) && (ts->pkt_type == DOT11_N)));
  1751. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1752. ((ts->mcs <= MAX_MCS_11A) && (ts->pkt_type == DOT11_N)));
  1753. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1754. ((ts->mcs >= MAX_MCS_11AC) && (ts->pkt_type == DOT11_AC)));
  1755. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1756. ((ts->mcs <= MAX_MCS_11AC) && (ts->pkt_type == DOT11_AC)));
  1757. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1758. ((ts->mcs >= (MAX_MCS-1)) && (ts->pkt_type == DOT11_AX)));
  1759. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1760. ((ts->mcs <= (MAX_MCS-1)) && (ts->pkt_type == DOT11_AX)));
  1761. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  1762. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  1763. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  1764. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  1765. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  1766. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  1767. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  1768. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  1769. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  1770. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  1771. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  1772. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  1773. &peer->stats, ts->peer_id,
  1774. UPDATE_PEER_STATS);
  1775. }
  1776. }
  1777. /**
  1778. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  1779. * @tx_desc: software descriptor head pointer
  1780. * @length: packet length
  1781. *
  1782. * Return: none
  1783. */
  1784. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  1785. uint32_t length)
  1786. {
  1787. struct hal_tx_completion_status ts;
  1788. struct dp_soc *soc = NULL;
  1789. struct dp_vdev *vdev = tx_desc->vdev;
  1790. struct dp_peer *peer = NULL;
  1791. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1792. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1793. "-------------------- \n"
  1794. "Tx Completion Stats: \n"
  1795. "-------------------- \n"
  1796. "ack_frame_rssi = %d \n"
  1797. "first_msdu = %d \n"
  1798. "last_msdu = %d \n"
  1799. "msdu_part_of_amsdu = %d \n"
  1800. "rate_stats valid = %d \n"
  1801. "bw = %d \n"
  1802. "pkt_type = %d \n"
  1803. "stbc = %d \n"
  1804. "ldpc = %d \n"
  1805. "sgi = %d \n"
  1806. "mcs = %d \n"
  1807. "ofdma = %d \n"
  1808. "tones_in_ru = %d \n"
  1809. "tsf = %d \n"
  1810. "ppdu_id = %d \n"
  1811. "transmit_cnt = %d \n"
  1812. "tid = %d \n"
  1813. "peer_id = %d \n",
  1814. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  1815. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  1816. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  1817. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  1818. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  1819. ts.peer_id);
  1820. if (!vdev) {
  1821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1822. "invalid vdev");
  1823. goto out;
  1824. }
  1825. soc = vdev->pdev->soc;
  1826. /* Update SoC level stats */
  1827. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  1828. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  1829. /* Update per-packet stats */
  1830. if (qdf_unlikely(vdev->mesh_vdev))
  1831. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  1832. /* Update peer level stats */
  1833. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1834. if (!peer) {
  1835. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1836. "invalid peer");
  1837. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  1838. goto out;
  1839. }
  1840. dp_tx_update_peer_stats(peer, &ts, length);
  1841. out:
  1842. return;
  1843. }
  1844. /**
  1845. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  1846. * @soc: core txrx main context
  1847. * @comp_head: software descriptor head pointer
  1848. *
  1849. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  1850. * and release the software descriptors after processing is complete
  1851. *
  1852. * Return: none
  1853. */
  1854. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  1855. struct dp_tx_desc_s *comp_head)
  1856. {
  1857. struct dp_tx_desc_s *desc;
  1858. struct dp_tx_desc_s *next;
  1859. struct hal_tx_completion_status ts = {0};
  1860. uint32_t length;
  1861. struct dp_peer *peer;
  1862. DP_HIST_INIT();
  1863. desc = comp_head;
  1864. while (desc) {
  1865. hal_tx_comp_get_status(&desc->comp, &ts);
  1866. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1867. length = qdf_nbuf_len(desc->nbuf);
  1868. /* Process Tx status in descriptor */
  1869. if (soc->process_tx_status ||
  1870. (desc->vdev && desc->vdev->mesh_vdev))
  1871. dp_tx_comp_process_tx_status(desc, length);
  1872. dp_tx_comp_free_buf(soc, desc);
  1873. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  1874. next = desc->next;
  1875. dp_tx_desc_release(desc, desc->pool_id);
  1876. desc = next;
  1877. }
  1878. DP_TX_HIST_STATS_PER_PDEV();
  1879. }
  1880. /**
  1881. * dp_tx_comp_handler() - Tx completion handler
  1882. * @soc: core txrx main context
  1883. * @ring_id: completion ring id
  1884. * @quota: No. of packets/descriptors that can be serviced in one loop
  1885. *
  1886. * This function will collect hardware release ring element contents and
  1887. * handle descriptor contents. Based on contents, free packet or handle error
  1888. * conditions
  1889. *
  1890. * Return: none
  1891. */
  1892. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  1893. {
  1894. void *tx_comp_hal_desc;
  1895. uint8_t buffer_src;
  1896. uint8_t pool_id;
  1897. uint32_t tx_desc_id;
  1898. struct dp_tx_desc_s *tx_desc = NULL;
  1899. struct dp_tx_desc_s *head_desc = NULL;
  1900. struct dp_tx_desc_s *tail_desc = NULL;
  1901. uint32_t num_processed;
  1902. uint32_t count;
  1903. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1904. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1905. "%s %d : HAL RING Access Failed -- %pK\n",
  1906. __func__, __LINE__, hal_srng);
  1907. return 0;
  1908. }
  1909. num_processed = 0;
  1910. count = 0;
  1911. /* Find head descriptor from completion ring */
  1912. while (qdf_likely(tx_comp_hal_desc =
  1913. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  1914. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  1915. /* If this buffer was not released by TQM or FW, then it is not
  1916. * Tx completion indication, assert */
  1917. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  1918. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1919. QDF_TRACE(QDF_MODULE_ID_DP,
  1920. QDF_TRACE_LEVEL_FATAL,
  1921. "Tx comp release_src != TQM | FW");
  1922. qdf_assert_always(0);
  1923. }
  1924. /* Get descriptor id */
  1925. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  1926. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  1927. DP_TX_DESC_ID_POOL_OS;
  1928. /* Pool ID is out of limit. Error */
  1929. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  1930. soc->wlan_cfg_ctx)) {
  1931. QDF_TRACE(QDF_MODULE_ID_DP,
  1932. QDF_TRACE_LEVEL_FATAL,
  1933. "Tx Comp pool id %d not valid",
  1934. pool_id);
  1935. qdf_assert_always(0);
  1936. }
  1937. /* Find Tx descriptor */
  1938. tx_desc = dp_tx_desc_find(soc, pool_id,
  1939. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  1940. DP_TX_DESC_ID_PAGE_OS,
  1941. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  1942. DP_TX_DESC_ID_OFFSET_OS);
  1943. /* Pool id is not matching. Error */
  1944. if (tx_desc && (tx_desc->pool_id != pool_id)) {
  1945. QDF_TRACE(QDF_MODULE_ID_DP,
  1946. QDF_TRACE_LEVEL_FATAL,
  1947. "Tx Comp pool id %d not matched %d",
  1948. pool_id, tx_desc->pool_id);
  1949. qdf_assert_always(0);
  1950. }
  1951. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  1952. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  1953. QDF_TRACE(QDF_MODULE_ID_DP,
  1954. QDF_TRACE_LEVEL_FATAL,
  1955. "Txdesc invalid, flgs = %x,id = %d",
  1956. tx_desc->flags, tx_desc_id);
  1957. qdf_assert_always(0);
  1958. }
  1959. /*
  1960. * If the release source is FW, process the HTT status
  1961. */
  1962. if (qdf_unlikely(buffer_src ==
  1963. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1964. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1965. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  1966. htt_tx_status);
  1967. dp_tx_process_htt_completion(tx_desc,
  1968. htt_tx_status);
  1969. } else {
  1970. /* First ring descriptor on the cycle */
  1971. if (!head_desc) {
  1972. head_desc = tx_desc;
  1973. tail_desc = tx_desc;
  1974. }
  1975. tail_desc->next = tx_desc;
  1976. tx_desc->next = NULL;
  1977. tail_desc = tx_desc;
  1978. /* Collect hw completion contents */
  1979. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1980. &tx_desc->comp, soc->process_tx_status);
  1981. }
  1982. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  1983. /* Decrement PM usage count if the packet has been sent.*/
  1984. hif_pm_runtime_put(soc->hif_handle);
  1985. /*
  1986. * Processed packet count is more than given quota
  1987. * stop to processing
  1988. */
  1989. if ((num_processed >= quota))
  1990. break;
  1991. count++;
  1992. }
  1993. hal_srng_access_end(soc->hal_soc, hal_srng);
  1994. /* Process the reaped descriptors */
  1995. if (head_desc)
  1996. dp_tx_comp_process_desc(soc, head_desc);
  1997. return num_processed;
  1998. }
  1999. #ifdef CONVERGED_TDLS_ENABLE
  2000. /**
  2001. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2002. *
  2003. * @data_vdev - which vdev should transmit the tx data frames
  2004. * @tx_spec - what non-standard handling to apply to the tx data frames
  2005. * @msdu_list - NULL-terminated list of tx MSDUs
  2006. *
  2007. * Return: NULL on success,
  2008. * nbuf when it fails to send
  2009. */
  2010. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2011. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2012. {
  2013. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2014. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2015. vdev->is_tdls_frame = true;
  2016. return dp_tx_send(vdev_handle, msdu_list);
  2017. }
  2018. #endif
  2019. /**
  2020. * dp_tx_vdev_attach() - attach vdev to dp tx
  2021. * @vdev: virtual device instance
  2022. *
  2023. * Return: QDF_STATUS_SUCCESS: success
  2024. * QDF_STATUS_E_RESOURCES: Error return
  2025. */
  2026. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2027. {
  2028. /*
  2029. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2030. */
  2031. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2032. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2033. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2034. vdev->vdev_id);
  2035. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2036. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2037. /*
  2038. * Set HTT Extension Valid bit to 0 by default
  2039. */
  2040. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2041. dp_tx_vdev_update_search_flags(vdev);
  2042. return QDF_STATUS_SUCCESS;
  2043. }
  2044. /**
  2045. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2046. * @vdev: virtual device instance
  2047. *
  2048. * Return: void
  2049. *
  2050. */
  2051. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2052. {
  2053. /*
  2054. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2055. * for TDLS link
  2056. *
  2057. * Enable AddrY (SA based search) only for non-WDS STA and
  2058. * ProxySTA VAP modes.
  2059. *
  2060. * In all other VAP modes, only DA based search should be
  2061. * enabled
  2062. */
  2063. if (vdev->opmode == wlan_op_mode_sta &&
  2064. vdev->tdls_link_connected)
  2065. vdev->hal_desc_addr_search_flags =
  2066. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2067. else if ((vdev->opmode == wlan_op_mode_sta &&
  2068. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2069. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2070. else
  2071. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2072. }
  2073. /**
  2074. * dp_tx_vdev_detach() - detach vdev from dp tx
  2075. * @vdev: virtual device instance
  2076. *
  2077. * Return: QDF_STATUS_SUCCESS: success
  2078. * QDF_STATUS_E_RESOURCES: Error return
  2079. */
  2080. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2081. {
  2082. return QDF_STATUS_SUCCESS;
  2083. }
  2084. /**
  2085. * dp_tx_pdev_attach() - attach pdev to dp tx
  2086. * @pdev: physical device instance
  2087. *
  2088. * Return: QDF_STATUS_SUCCESS: success
  2089. * QDF_STATUS_E_RESOURCES: Error return
  2090. */
  2091. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2092. {
  2093. struct dp_soc *soc = pdev->soc;
  2094. /* Initialize Flow control counters */
  2095. qdf_atomic_init(&pdev->num_tx_exception);
  2096. qdf_atomic_init(&pdev->num_tx_outstanding);
  2097. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2098. /* Initialize descriptors in TCL Ring */
  2099. hal_tx_init_data_ring(soc->hal_soc,
  2100. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2101. }
  2102. return QDF_STATUS_SUCCESS;
  2103. }
  2104. /**
  2105. * dp_tx_pdev_detach() - detach pdev from dp tx
  2106. * @pdev: physical device instance
  2107. *
  2108. * Return: QDF_STATUS_SUCCESS: success
  2109. * QDF_STATUS_E_RESOURCES: Error return
  2110. */
  2111. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2112. {
  2113. /* What should do here? */
  2114. return QDF_STATUS_SUCCESS;
  2115. }
  2116. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2117. /* Pools will be allocated dynamically */
  2118. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2119. int num_desc)
  2120. {
  2121. uint8_t i;
  2122. for (i = 0; i < num_pool; i++) {
  2123. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2124. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2125. }
  2126. return 0;
  2127. }
  2128. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2129. {
  2130. uint8_t i;
  2131. for (i = 0; i < num_pool; i++)
  2132. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2133. }
  2134. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2135. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2136. int num_desc)
  2137. {
  2138. uint8_t i;
  2139. /* Allocate software Tx descriptor pools */
  2140. for (i = 0; i < num_pool; i++) {
  2141. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2142. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2143. "%s Tx Desc Pool alloc %d failed %pK\n",
  2144. __func__, i, soc);
  2145. return ENOMEM;
  2146. }
  2147. }
  2148. return 0;
  2149. }
  2150. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2151. {
  2152. uint8_t i;
  2153. for (i = 0; i < num_pool; i++) {
  2154. if (dp_tx_desc_pool_free(soc, i)) {
  2155. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2156. "%s Tx Desc Pool Free failed\n", __func__);
  2157. }
  2158. }
  2159. }
  2160. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2161. /**
  2162. * dp_tx_soc_detach() - detach soc from dp tx
  2163. * @soc: core txrx main context
  2164. *
  2165. * This function will detach dp tx into main device context
  2166. * will free dp tx resource and initialize resources
  2167. *
  2168. * Return: QDF_STATUS_SUCCESS: success
  2169. * QDF_STATUS_E_RESOURCES: Error return
  2170. */
  2171. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2172. {
  2173. uint8_t num_pool;
  2174. uint16_t num_desc;
  2175. uint16_t num_ext_desc;
  2176. uint8_t i;
  2177. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2178. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2179. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2180. dp_tx_flow_control_deinit(soc);
  2181. dp_tx_delete_static_pools(soc, num_pool);
  2182. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2183. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2184. __func__, num_pool, num_desc);
  2185. for (i = 0; i < num_pool; i++) {
  2186. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2187. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2188. "%s Tx Ext Desc Pool Free failed\n",
  2189. __func__);
  2190. return QDF_STATUS_E_RESOURCES;
  2191. }
  2192. }
  2193. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2194. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2195. __func__, num_pool, num_ext_desc);
  2196. for (i = 0; i < num_pool; i++) {
  2197. dp_tx_tso_desc_pool_free(soc, i);
  2198. }
  2199. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2200. "%s TSO Desc Pool %d Free descs = %d\n",
  2201. __func__, num_pool, num_desc);
  2202. for (i = 0; i < num_pool; i++)
  2203. dp_tx_tso_num_seg_pool_free(soc, i);
  2204. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2205. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2206. __func__, num_pool, num_desc);
  2207. return QDF_STATUS_SUCCESS;
  2208. }
  2209. /**
  2210. * dp_tx_soc_attach() - attach soc to dp tx
  2211. * @soc: core txrx main context
  2212. *
  2213. * This function will attach dp tx into main device context
  2214. * will allocate dp tx resource and initialize resources
  2215. *
  2216. * Return: QDF_STATUS_SUCCESS: success
  2217. * QDF_STATUS_E_RESOURCES: Error return
  2218. */
  2219. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2220. {
  2221. uint8_t i;
  2222. uint8_t num_pool;
  2223. uint32_t num_desc;
  2224. uint32_t num_ext_desc;
  2225. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2226. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2227. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2228. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2229. goto fail;
  2230. dp_tx_flow_control_init(soc);
  2231. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2232. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2233. __func__, num_pool, num_desc);
  2234. /* Allocate extension tx descriptor pools */
  2235. for (i = 0; i < num_pool; i++) {
  2236. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2237. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2238. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2239. i, soc);
  2240. goto fail;
  2241. }
  2242. }
  2243. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2244. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2245. __func__, num_pool, num_ext_desc);
  2246. for (i = 0; i < num_pool; i++) {
  2247. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2248. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2249. "TSO Desc Pool alloc %d failed %pK\n",
  2250. i, soc);
  2251. goto fail;
  2252. }
  2253. }
  2254. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2255. "%s TSO Desc Alloc %d, descs = %d\n",
  2256. __func__, num_pool, num_desc);
  2257. for (i = 0; i < num_pool; i++) {
  2258. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2259. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2260. "TSO Num of seg Pool alloc %d failed %pK\n",
  2261. i, soc);
  2262. goto fail;
  2263. }
  2264. }
  2265. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2266. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2267. __func__, num_pool, num_desc);
  2268. /* Initialize descriptors in TCL Rings */
  2269. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2270. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2271. hal_tx_init_data_ring(soc->hal_soc,
  2272. soc->tcl_data_ring[i].hal_srng);
  2273. }
  2274. }
  2275. /*
  2276. * todo - Add a runtime config option to enable this.
  2277. */
  2278. /*
  2279. * Due to multiple issues on NPR EMU, enable it selectively
  2280. * only for NPR EMU, should be removed, once NPR platforms
  2281. * are stable.
  2282. */
  2283. soc->process_tx_status = 1;
  2284. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2285. "%s HAL Tx init Success\n", __func__);
  2286. return QDF_STATUS_SUCCESS;
  2287. fail:
  2288. /* Detach will take care of freeing only allocated resources */
  2289. dp_tx_soc_detach(soc);
  2290. return QDF_STATUS_E_RESOURCES;
  2291. }
  2292. /*
  2293. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2294. * pdev: pointer to DP PDEV structure
  2295. * seg_info_head: Pointer to the head of list
  2296. *
  2297. * return: void
  2298. */
  2299. static inline void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2300. struct dp_tx_seg_info_s *seg_info_head)
  2301. {
  2302. struct dp_tx_me_buf_t *mc_uc_buf;
  2303. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2304. qdf_nbuf_t nbuf = NULL;
  2305. uint64_t phy_addr;
  2306. while (seg_info_head) {
  2307. nbuf = seg_info_head->nbuf;
  2308. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2309. seg_info_new->frags[0].vaddr;
  2310. phy_addr = seg_info_head->frags[0].paddr_hi;
  2311. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2312. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2313. phy_addr,
  2314. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2315. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2316. qdf_nbuf_free(nbuf);
  2317. seg_info_new = seg_info_head;
  2318. seg_info_head = seg_info_head->next;
  2319. qdf_mem_free(seg_info_new);
  2320. }
  2321. }
  2322. /**
  2323. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2324. * @vdev: DP VDEV handle
  2325. * @nbuf: Multicast nbuf
  2326. * @newmac: Table of the clients to which packets have to be sent
  2327. * @new_mac_cnt: No of clients
  2328. *
  2329. * return: no of converted packets
  2330. */
  2331. uint16_t
  2332. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2333. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2334. {
  2335. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2336. struct dp_pdev *pdev = vdev->pdev;
  2337. struct ether_header *eh;
  2338. uint8_t *data;
  2339. uint16_t len;
  2340. /* reference to frame dst addr */
  2341. uint8_t *dstmac;
  2342. /* copy of original frame src addr */
  2343. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2344. /* local index into newmac */
  2345. uint8_t new_mac_idx = 0;
  2346. struct dp_tx_me_buf_t *mc_uc_buf;
  2347. qdf_nbuf_t nbuf_clone;
  2348. struct dp_tx_msdu_info_s msdu_info;
  2349. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2350. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2351. struct dp_tx_seg_info_s *seg_info_new;
  2352. struct dp_tx_frag_info_s data_frag;
  2353. qdf_dma_addr_t paddr_data;
  2354. qdf_dma_addr_t paddr_mcbuf = 0;
  2355. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2356. QDF_STATUS status;
  2357. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2358. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2359. eh = (struct ether_header *) nbuf;
  2360. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2361. len = qdf_nbuf_len(nbuf);
  2362. data = qdf_nbuf_data(nbuf);
  2363. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2364. QDF_DMA_TO_DEVICE);
  2365. if (status) {
  2366. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2367. "Mapping failure Error:%d", status);
  2368. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2369. return 0;
  2370. }
  2371. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2372. /*preparing data fragment*/
  2373. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2374. data_frag.paddr_lo = (uint32_t)paddr_data;
  2375. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2376. data_frag.len = len - DP_MAC_ADDR_LEN;
  2377. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2378. dstmac = newmac[new_mac_idx];
  2379. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2380. "added mac addr (%pM)", dstmac);
  2381. /* Check for NULL Mac Address */
  2382. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2383. continue;
  2384. /* frame to self mac. skip */
  2385. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2386. continue;
  2387. /*
  2388. * TODO: optimize to avoid malloc in per-packet path
  2389. * For eg. seg_pool can be made part of vdev structure
  2390. */
  2391. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2392. if (!seg_info_new) {
  2393. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2394. "alloc failed");
  2395. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2396. goto fail_seg_alloc;
  2397. }
  2398. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2399. if (mc_uc_buf == NULL)
  2400. goto fail_buf_alloc;
  2401. /*
  2402. * TODO: Check if we need to clone the nbuf
  2403. * Or can we just use the reference for all cases
  2404. */
  2405. if (new_mac_idx < (new_mac_cnt - 1)) {
  2406. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2407. if (nbuf_clone == NULL) {
  2408. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2409. goto fail_clone;
  2410. }
  2411. } else {
  2412. /*
  2413. * Update the ref
  2414. * to account for frame sent without cloning
  2415. */
  2416. qdf_nbuf_ref(nbuf);
  2417. nbuf_clone = nbuf;
  2418. }
  2419. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2420. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2421. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2422. &paddr_mcbuf);
  2423. if (status) {
  2424. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2425. "Mapping failure Error:%d", status);
  2426. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2427. goto fail_map;
  2428. }
  2429. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2430. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2431. seg_info_new->frags[0].paddr_hi =
  2432. ((uint64_t) paddr_mcbuf >> 32);
  2433. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2434. seg_info_new->frags[1] = data_frag;
  2435. seg_info_new->nbuf = nbuf_clone;
  2436. seg_info_new->frag_cnt = 2;
  2437. seg_info_new->total_len = len;
  2438. seg_info_new->next = NULL;
  2439. if (seg_info_head == NULL)
  2440. seg_info_head = seg_info_new;
  2441. else
  2442. seg_info_tail->next = seg_info_new;
  2443. seg_info_tail = seg_info_new;
  2444. }
  2445. if (!seg_info_head)
  2446. return 0;
  2447. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2448. msdu_info.num_seg = new_mac_cnt;
  2449. msdu_info.frm_type = dp_tx_frm_me;
  2450. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2451. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2452. while (seg_info_head->next) {
  2453. seg_info_new = seg_info_head;
  2454. seg_info_head = seg_info_head->next;
  2455. qdf_mem_free(seg_info_new);
  2456. }
  2457. qdf_mem_free(seg_info_head);
  2458. return new_mac_cnt;
  2459. fail_map:
  2460. qdf_nbuf_free(nbuf_clone);
  2461. fail_clone:
  2462. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2463. fail_buf_alloc:
  2464. qdf_mem_free(seg_info_new);
  2465. fail_seg_alloc:
  2466. dp_tx_me_mem_free(pdev, seg_info_head);
  2467. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2468. return 0;
  2469. }