rx_msdu_end.h 80 KB

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  1. /*
  2. * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _RX_MSDU_END_H_
  17. #define _RX_MSDU_END_H_
  18. #define NUM_OF_DWORDS_RX_MSDU_END 32
  19. struct rx_msdu_end {
  20. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  21. uint32_t rxpcu_mpdu_filter_in_category : 2,
  22. sw_frame_group_id : 7,
  23. reserved_0 : 7,
  24. phy_ppdu_id : 16;
  25. uint32_t ip_hdr_chksum : 16,
  26. reported_mpdu_length : 14,
  27. reserved_1a : 2;
  28. uint32_t reserved_2a : 8,
  29. cce_super_rule : 6,
  30. cce_classify_not_done_truncate : 1,
  31. cce_classify_not_done_cce_dis : 1,
  32. cumulative_l3_checksum : 16;
  33. uint32_t rule_indication_31_0 : 32;
  34. uint32_t ipv6_options_crc : 32;
  35. uint32_t da_offset : 6,
  36. sa_offset : 6,
  37. da_offset_valid : 1,
  38. sa_offset_valid : 1,
  39. reserved_5a : 2,
  40. l3_type : 16;
  41. uint32_t rule_indication_63_32 : 32;
  42. uint32_t tcp_seq_number : 32;
  43. uint32_t tcp_ack_number : 32;
  44. uint32_t tcp_flag : 9,
  45. lro_eligible : 1,
  46. reserved_9a : 6,
  47. window_size : 16;
  48. uint32_t sa_sw_peer_id : 16,
  49. sa_idx_timeout : 1,
  50. da_idx_timeout : 1,
  51. to_ds : 1,
  52. tid : 4,
  53. sa_is_valid : 1,
  54. da_is_valid : 1,
  55. da_is_mcbc : 1,
  56. l3_header_padding : 2,
  57. first_msdu : 1,
  58. last_msdu : 1,
  59. fr_ds : 1,
  60. ip_chksum_fail_copy : 1;
  61. uint32_t sa_idx : 16,
  62. da_idx_or_sw_peer_id : 16;
  63. uint32_t msdu_drop : 1,
  64. reo_destination_indication : 5,
  65. flow_idx : 20,
  66. use_ppe : 1,
  67. __reserved_g_0003 : 2,
  68. vlan_ctag_stripped : 1,
  69. vlan_stag_stripped : 1,
  70. fragment_flag : 1;
  71. uint32_t fse_metadata : 32;
  72. uint32_t cce_metadata : 16,
  73. tcp_udp_chksum : 16;
  74. uint32_t aggregation_count : 8,
  75. flow_aggregation_continuation : 1,
  76. fisa_timeout : 1,
  77. tcp_udp_chksum_fail_copy : 1,
  78. msdu_limit_error : 1,
  79. flow_idx_timeout : 1,
  80. flow_idx_invalid : 1,
  81. cce_match : 1,
  82. amsdu_parser_error : 1,
  83. cumulative_ip_length : 16;
  84. uint32_t key_id_octet : 8,
  85. reserved_16a : 24;
  86. uint32_t reserved_17a : 6,
  87. service_code : 9,
  88. priority_valid : 1,
  89. intra_bss : 1,
  90. dest_chip_id : 2,
  91. multicast_echo : 1,
  92. wds_learning_event : 1,
  93. wds_roaming_event : 1,
  94. wds_keep_alive_event : 1,
  95. __reserved_g_0015 : 1,
  96. reserved_17b : 8;
  97. uint32_t msdu_length : 14,
  98. stbc : 1,
  99. ipsec_esp : 1,
  100. l3_offset : 7,
  101. ipsec_ah : 1,
  102. l4_offset : 8;
  103. uint32_t msdu_number : 8,
  104. decap_format : 2,
  105. ipv4_proto : 1,
  106. ipv6_proto : 1,
  107. tcp_proto : 1,
  108. udp_proto : 1,
  109. ip_frag : 1,
  110. tcp_only_ack : 1,
  111. da_is_bcast_mcast : 1,
  112. toeplitz_hash_sel : 2,
  113. ip_fixed_header_valid : 1,
  114. ip_extn_header_valid : 1,
  115. tcp_udp_header_valid : 1,
  116. mesh_control_present : 1,
  117. ldpc : 1,
  118. ip4_protocol_ip6_next_header : 8;
  119. uint32_t vlan_ctag_ci : 16,
  120. vlan_stag_ci : 16;
  121. uint32_t peer_meta_data : 32;
  122. uint32_t user_rssi : 8,
  123. pkt_type : 4,
  124. sgi : 2,
  125. rate_mcs : 4,
  126. receive_bandwidth : 3,
  127. reception_type : 3,
  128. mimo_ss_bitmap : 7,
  129. msdu_done_copy : 1;
  130. uint32_t flow_id_toeplitz : 32;
  131. uint32_t ppdu_start_timestamp_63_32 : 32;
  132. uint32_t sw_phy_meta_data : 32;
  133. uint32_t ppdu_start_timestamp_31_0 : 32;
  134. uint32_t toeplitz_hash_2_or_4 : 32;
  135. uint32_t reserved_28a : 16,
  136. sa_15_0 : 16;
  137. uint32_t sa_47_16 : 32;
  138. uint32_t first_mpdu : 1,
  139. reserved_30a : 1,
  140. mcast_bcast : 1,
  141. ast_index_not_found : 1,
  142. ast_index_timeout : 1,
  143. power_mgmt : 1,
  144. non_qos : 1,
  145. null_data : 1,
  146. mgmt_type : 1,
  147. ctrl_type : 1,
  148. more_data : 1,
  149. eosp : 1,
  150. a_msdu_error : 1,
  151. reserved_30b : 1,
  152. order : 1,
  153. wifi_parser_error : 1,
  154. overflow_err : 1,
  155. msdu_length_err : 1,
  156. tcp_udp_chksum_fail : 1,
  157. ip_chksum_fail : 1,
  158. sa_idx_invalid : 1,
  159. da_idx_invalid : 1,
  160. amsdu_addr_mismatch : 1,
  161. rx_in_tx_decrypt_byp : 1,
  162. encrypt_required : 1,
  163. directed : 1,
  164. buffer_fragment : 1,
  165. mpdu_length_err : 1,
  166. tkip_mic_err : 1,
  167. decrypt_err : 1,
  168. unencrypted_frame_err : 1,
  169. fcs_err : 1;
  170. uint32_t reserved_31a : 10,
  171. decrypt_status_code : 3,
  172. rx_bitmap_not_updated : 1,
  173. reserved_31b : 17,
  174. msdu_done : 1;
  175. #else
  176. uint32_t phy_ppdu_id : 16,
  177. reserved_0 : 7,
  178. sw_frame_group_id : 7,
  179. rxpcu_mpdu_filter_in_category : 2;
  180. uint32_t reserved_1a : 2,
  181. reported_mpdu_length : 14,
  182. ip_hdr_chksum : 16;
  183. uint32_t cumulative_l3_checksum : 16,
  184. cce_classify_not_done_cce_dis : 1,
  185. cce_classify_not_done_truncate : 1,
  186. cce_super_rule : 6,
  187. reserved_2a : 8;
  188. uint32_t rule_indication_31_0 : 32;
  189. uint32_t ipv6_options_crc : 32;
  190. uint32_t l3_type : 16,
  191. reserved_5a : 2,
  192. sa_offset_valid : 1,
  193. da_offset_valid : 1,
  194. sa_offset : 6,
  195. da_offset : 6;
  196. uint32_t rule_indication_63_32 : 32;
  197. uint32_t tcp_seq_number : 32;
  198. uint32_t tcp_ack_number : 32;
  199. uint32_t window_size : 16,
  200. reserved_9a : 6,
  201. lro_eligible : 1,
  202. tcp_flag : 9;
  203. uint32_t ip_chksum_fail_copy : 1,
  204. fr_ds : 1,
  205. last_msdu : 1,
  206. first_msdu : 1,
  207. l3_header_padding : 2,
  208. da_is_mcbc : 1,
  209. da_is_valid : 1,
  210. sa_is_valid : 1,
  211. tid : 4,
  212. to_ds : 1,
  213. da_idx_timeout : 1,
  214. sa_idx_timeout : 1,
  215. sa_sw_peer_id : 16;
  216. uint32_t da_idx_or_sw_peer_id : 16,
  217. sa_idx : 16;
  218. uint32_t fragment_flag : 1,
  219. vlan_stag_stripped : 1,
  220. vlan_ctag_stripped : 1,
  221. __reserved_g_0003 : 2,
  222. use_ppe : 1,
  223. flow_idx : 20,
  224. reo_destination_indication : 5,
  225. msdu_drop : 1;
  226. uint32_t fse_metadata : 32;
  227. uint32_t tcp_udp_chksum : 16,
  228. cce_metadata : 16;
  229. uint32_t cumulative_ip_length : 16,
  230. amsdu_parser_error : 1,
  231. cce_match : 1,
  232. flow_idx_invalid : 1,
  233. flow_idx_timeout : 1,
  234. msdu_limit_error : 1,
  235. tcp_udp_chksum_fail_copy : 1,
  236. fisa_timeout : 1,
  237. flow_aggregation_continuation : 1,
  238. aggregation_count : 8;
  239. uint32_t reserved_16a : 24,
  240. key_id_octet : 8;
  241. uint32_t reserved_17b : 8,
  242. __reserved_g_0015 : 1,
  243. wds_keep_alive_event : 1,
  244. wds_roaming_event : 1,
  245. wds_learning_event : 1,
  246. multicast_echo : 1,
  247. dest_chip_id : 2,
  248. intra_bss : 1,
  249. priority_valid : 1,
  250. service_code : 9,
  251. reserved_17a : 6;
  252. uint32_t l4_offset : 8,
  253. ipsec_ah : 1,
  254. l3_offset : 7,
  255. ipsec_esp : 1,
  256. stbc : 1,
  257. msdu_length : 14;
  258. uint32_t ip4_protocol_ip6_next_header : 8,
  259. ldpc : 1,
  260. mesh_control_present : 1,
  261. tcp_udp_header_valid : 1,
  262. ip_extn_header_valid : 1,
  263. ip_fixed_header_valid : 1,
  264. toeplitz_hash_sel : 2,
  265. da_is_bcast_mcast : 1,
  266. tcp_only_ack : 1,
  267. ip_frag : 1,
  268. udp_proto : 1,
  269. tcp_proto : 1,
  270. ipv6_proto : 1,
  271. ipv4_proto : 1,
  272. decap_format : 2,
  273. msdu_number : 8;
  274. uint32_t vlan_stag_ci : 16,
  275. vlan_ctag_ci : 16;
  276. uint32_t peer_meta_data : 32;
  277. uint32_t msdu_done_copy : 1,
  278. mimo_ss_bitmap : 7,
  279. reception_type : 3,
  280. receive_bandwidth : 3,
  281. rate_mcs : 4,
  282. sgi : 2,
  283. pkt_type : 4,
  284. user_rssi : 8;
  285. uint32_t flow_id_toeplitz : 32;
  286. uint32_t ppdu_start_timestamp_63_32 : 32;
  287. uint32_t sw_phy_meta_data : 32;
  288. uint32_t ppdu_start_timestamp_31_0 : 32;
  289. uint32_t toeplitz_hash_2_or_4 : 32;
  290. uint32_t sa_15_0 : 16,
  291. reserved_28a : 16;
  292. uint32_t sa_47_16 : 32;
  293. uint32_t fcs_err : 1,
  294. unencrypted_frame_err : 1,
  295. decrypt_err : 1,
  296. tkip_mic_err : 1,
  297. mpdu_length_err : 1,
  298. buffer_fragment : 1,
  299. directed : 1,
  300. encrypt_required : 1,
  301. rx_in_tx_decrypt_byp : 1,
  302. amsdu_addr_mismatch : 1,
  303. da_idx_invalid : 1,
  304. sa_idx_invalid : 1,
  305. ip_chksum_fail : 1,
  306. tcp_udp_chksum_fail : 1,
  307. msdu_length_err : 1,
  308. overflow_err : 1,
  309. wifi_parser_error : 1,
  310. order : 1,
  311. reserved_30b : 1,
  312. a_msdu_error : 1,
  313. eosp : 1,
  314. more_data : 1,
  315. ctrl_type : 1,
  316. mgmt_type : 1,
  317. null_data : 1,
  318. non_qos : 1,
  319. power_mgmt : 1,
  320. ast_index_timeout : 1,
  321. ast_index_not_found : 1,
  322. mcast_bcast : 1,
  323. reserved_30a : 1,
  324. first_mpdu : 1;
  325. uint32_t msdu_done : 1,
  326. reserved_31b : 17,
  327. rx_bitmap_not_updated : 1,
  328. decrypt_status_code : 3,
  329. reserved_31a : 10;
  330. #endif
  331. };
  332. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
  333. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
  334. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
  335. #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
  336. #define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000
  337. #define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2
  338. #define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8
  339. #define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc
  340. #define RX_MSDU_END_RESERVED_0_OFFSET 0x00000000
  341. #define RX_MSDU_END_RESERVED_0_LSB 9
  342. #define RX_MSDU_END_RESERVED_0_MSB 15
  343. #define RX_MSDU_END_RESERVED_0_MASK 0x0000fe00
  344. #define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x00000000
  345. #define RX_MSDU_END_PHY_PPDU_ID_LSB 16
  346. #define RX_MSDU_END_PHY_PPDU_ID_MSB 31
  347. #define RX_MSDU_END_PHY_PPDU_ID_MASK 0xffff0000
  348. #define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x00000004
  349. #define RX_MSDU_END_IP_HDR_CHKSUM_LSB 0
  350. #define RX_MSDU_END_IP_HDR_CHKSUM_MSB 15
  351. #define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff
  352. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x00000004
  353. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 16
  354. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 29
  355. #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff0000
  356. #define RX_MSDU_END_RESERVED_1A_OFFSET 0x00000004
  357. #define RX_MSDU_END_RESERVED_1A_LSB 30
  358. #define RX_MSDU_END_RESERVED_1A_MSB 31
  359. #define RX_MSDU_END_RESERVED_1A_MASK 0xc0000000
  360. #define RX_MSDU_END_RESERVED_2A_OFFSET 0x00000008
  361. #define RX_MSDU_END_RESERVED_2A_LSB 0
  362. #define RX_MSDU_END_RESERVED_2A_MSB 7
  363. #define RX_MSDU_END_RESERVED_2A_MASK 0x000000ff
  364. #define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x00000008
  365. #define RX_MSDU_END_CCE_SUPER_RULE_LSB 8
  366. #define RX_MSDU_END_CCE_SUPER_RULE_MSB 13
  367. #define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x00003f00
  368. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008
  369. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14
  370. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14
  371. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000
  372. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008
  373. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15
  374. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15
  375. #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000
  376. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008
  377. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16
  378. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31
  379. #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000
  380. #define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000c
  381. #define RX_MSDU_END_RULE_INDICATION_31_0_LSB 0
  382. #define RX_MSDU_END_RULE_INDICATION_31_0_MSB 31
  383. #define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff
  384. #define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x00000010
  385. #define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0
  386. #define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31
  387. #define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0xffffffff
  388. #define RX_MSDU_END_DA_OFFSET_OFFSET 0x00000014
  389. #define RX_MSDU_END_DA_OFFSET_LSB 0
  390. #define RX_MSDU_END_DA_OFFSET_MSB 5
  391. #define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f
  392. #define RX_MSDU_END_SA_OFFSET_OFFSET 0x00000014
  393. #define RX_MSDU_END_SA_OFFSET_LSB 6
  394. #define RX_MSDU_END_SA_OFFSET_MSB 11
  395. #define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc0
  396. #define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x00000014
  397. #define RX_MSDU_END_DA_OFFSET_VALID_LSB 12
  398. #define RX_MSDU_END_DA_OFFSET_VALID_MSB 12
  399. #define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x00001000
  400. #define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x00000014
  401. #define RX_MSDU_END_SA_OFFSET_VALID_LSB 13
  402. #define RX_MSDU_END_SA_OFFSET_VALID_MSB 13
  403. #define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x00002000
  404. #define RX_MSDU_END_RESERVED_5A_OFFSET 0x00000014
  405. #define RX_MSDU_END_RESERVED_5A_LSB 14
  406. #define RX_MSDU_END_RESERVED_5A_MSB 15
  407. #define RX_MSDU_END_RESERVED_5A_MASK 0x0000c000
  408. #define RX_MSDU_END_L3_TYPE_OFFSET 0x00000014
  409. #define RX_MSDU_END_L3_TYPE_LSB 16
  410. #define RX_MSDU_END_L3_TYPE_MSB 31
  411. #define RX_MSDU_END_L3_TYPE_MASK 0xffff0000
  412. #define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x00000018
  413. #define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0
  414. #define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31
  415. #define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0xffffffff
  416. #define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000001c
  417. #define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 0
  418. #define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 31
  419. #define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff
  420. #define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x00000020
  421. #define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0
  422. #define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31
  423. #define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0xffffffff
  424. #define RX_MSDU_END_TCP_FLAG_OFFSET 0x00000024
  425. #define RX_MSDU_END_TCP_FLAG_LSB 0
  426. #define RX_MSDU_END_TCP_FLAG_MSB 8
  427. #define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff
  428. #define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x00000024
  429. #define RX_MSDU_END_LRO_ELIGIBLE_LSB 9
  430. #define RX_MSDU_END_LRO_ELIGIBLE_MSB 9
  431. #define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x00000200
  432. #define RX_MSDU_END_RESERVED_9A_OFFSET 0x00000024
  433. #define RX_MSDU_END_RESERVED_9A_LSB 10
  434. #define RX_MSDU_END_RESERVED_9A_MSB 15
  435. #define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc00
  436. #define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x00000024
  437. #define RX_MSDU_END_WINDOW_SIZE_LSB 16
  438. #define RX_MSDU_END_WINDOW_SIZE_MSB 31
  439. #define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff0000
  440. #define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x00000028
  441. #define RX_MSDU_END_SA_SW_PEER_ID_LSB 0
  442. #define RX_MSDU_END_SA_SW_PEER_ID_MSB 15
  443. #define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x0000ffff
  444. #define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x00000028
  445. #define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16
  446. #define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16
  447. #define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x00010000
  448. #define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x00000028
  449. #define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17
  450. #define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17
  451. #define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x00020000
  452. #define RX_MSDU_END_TO_DS_OFFSET 0x00000028
  453. #define RX_MSDU_END_TO_DS_LSB 18
  454. #define RX_MSDU_END_TO_DS_MSB 18
  455. #define RX_MSDU_END_TO_DS_MASK 0x00040000
  456. #define RX_MSDU_END_TID_OFFSET 0x00000028
  457. #define RX_MSDU_END_TID_LSB 19
  458. #define RX_MSDU_END_TID_MSB 22
  459. #define RX_MSDU_END_TID_MASK 0x00780000
  460. #define RX_MSDU_END_SA_IS_VALID_OFFSET 0x00000028
  461. #define RX_MSDU_END_SA_IS_VALID_LSB 23
  462. #define RX_MSDU_END_SA_IS_VALID_MSB 23
  463. #define RX_MSDU_END_SA_IS_VALID_MASK 0x00800000
  464. #define RX_MSDU_END_DA_IS_VALID_OFFSET 0x00000028
  465. #define RX_MSDU_END_DA_IS_VALID_LSB 24
  466. #define RX_MSDU_END_DA_IS_VALID_MSB 24
  467. #define RX_MSDU_END_DA_IS_VALID_MASK 0x01000000
  468. #define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x00000028
  469. #define RX_MSDU_END_DA_IS_MCBC_LSB 25
  470. #define RX_MSDU_END_DA_IS_MCBC_MSB 25
  471. #define RX_MSDU_END_DA_IS_MCBC_MASK 0x02000000
  472. #define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x00000028
  473. #define RX_MSDU_END_L3_HEADER_PADDING_LSB 26
  474. #define RX_MSDU_END_L3_HEADER_PADDING_MSB 27
  475. #define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x0c000000
  476. #define RX_MSDU_END_FIRST_MSDU_OFFSET 0x00000028
  477. #define RX_MSDU_END_FIRST_MSDU_LSB 28
  478. #define RX_MSDU_END_FIRST_MSDU_MSB 28
  479. #define RX_MSDU_END_FIRST_MSDU_MASK 0x10000000
  480. #define RX_MSDU_END_LAST_MSDU_OFFSET 0x00000028
  481. #define RX_MSDU_END_LAST_MSDU_LSB 29
  482. #define RX_MSDU_END_LAST_MSDU_MSB 29
  483. #define RX_MSDU_END_LAST_MSDU_MASK 0x20000000
  484. #define RX_MSDU_END_FR_DS_OFFSET 0x00000028
  485. #define RX_MSDU_END_FR_DS_LSB 30
  486. #define RX_MSDU_END_FR_DS_MSB 30
  487. #define RX_MSDU_END_FR_DS_MASK 0x40000000
  488. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x00000028
  489. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31
  490. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31
  491. #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x80000000
  492. #define RX_MSDU_END_SA_IDX_OFFSET 0x0000002c
  493. #define RX_MSDU_END_SA_IDX_LSB 0
  494. #define RX_MSDU_END_SA_IDX_MSB 15
  495. #define RX_MSDU_END_SA_IDX_MASK 0x0000ffff
  496. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c
  497. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 16
  498. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 31
  499. #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000
  500. #define RX_MSDU_END_MSDU_DROP_OFFSET 0x00000030
  501. #define RX_MSDU_END_MSDU_DROP_LSB 0
  502. #define RX_MSDU_END_MSDU_DROP_MSB 0
  503. #define RX_MSDU_END_MSDU_DROP_MASK 0x00000001
  504. #define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x00000030
  505. #define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1
  506. #define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5
  507. #define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x0000003e
  508. #define RX_MSDU_END_FLOW_IDX_OFFSET 0x00000030
  509. #define RX_MSDU_END_FLOW_IDX_LSB 6
  510. #define RX_MSDU_END_FLOW_IDX_MSB 25
  511. #define RX_MSDU_END_FLOW_IDX_MASK 0x03ffffc0
  512. #define RX_MSDU_END_USE_PPE_OFFSET 0x00000030
  513. #define RX_MSDU_END_USE_PPE_LSB 26
  514. #define RX_MSDU_END_USE_PPE_MSB 26
  515. #define RX_MSDU_END_USE_PPE_MASK 0x04000000
  516. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x00000030
  517. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29
  518. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29
  519. #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x20000000
  520. #define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x00000030
  521. #define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30
  522. #define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30
  523. #define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x40000000
  524. #define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x00000030
  525. #define RX_MSDU_END_FRAGMENT_FLAG_LSB 31
  526. #define RX_MSDU_END_FRAGMENT_FLAG_MSB 31
  527. #define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x80000000
  528. #define RX_MSDU_END_FSE_METADATA_OFFSET 0x00000034
  529. #define RX_MSDU_END_FSE_METADATA_LSB 0
  530. #define RX_MSDU_END_FSE_METADATA_MSB 31
  531. #define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff
  532. #define RX_MSDU_END_CCE_METADATA_OFFSET 0x00000038
  533. #define RX_MSDU_END_CCE_METADATA_LSB 0
  534. #define RX_MSDU_END_CCE_METADATA_MSB 15
  535. #define RX_MSDU_END_CCE_METADATA_MASK 0x0000ffff
  536. #define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x00000038
  537. #define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16
  538. #define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31
  539. #define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0xffff0000
  540. #define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000003c
  541. #define RX_MSDU_END_AGGREGATION_COUNT_LSB 0
  542. #define RX_MSDU_END_AGGREGATION_COUNT_MSB 7
  543. #define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff
  544. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c
  545. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 8
  546. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 8
  547. #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100
  548. #define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000003c
  549. #define RX_MSDU_END_FISA_TIMEOUT_LSB 9
  550. #define RX_MSDU_END_FISA_TIMEOUT_MSB 9
  551. #define RX_MSDU_END_FISA_TIMEOUT_MASK 0x00000200
  552. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000003c
  553. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 10
  554. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 10
  555. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x00000400
  556. #define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000003c
  557. #define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 11
  558. #define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 11
  559. #define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x00000800
  560. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000003c
  561. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 12
  562. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 12
  563. #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x00001000
  564. #define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000003c
  565. #define RX_MSDU_END_FLOW_IDX_INVALID_LSB 13
  566. #define RX_MSDU_END_FLOW_IDX_INVALID_MSB 13
  567. #define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x00002000
  568. #define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000003c
  569. #define RX_MSDU_END_CCE_MATCH_LSB 14
  570. #define RX_MSDU_END_CCE_MATCH_MSB 14
  571. #define RX_MSDU_END_CCE_MATCH_MASK 0x00004000
  572. #define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000003c
  573. #define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 15
  574. #define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 15
  575. #define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x00008000
  576. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000003c
  577. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 16
  578. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 31
  579. #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
  580. #define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x00000040
  581. #define RX_MSDU_END_KEY_ID_OCTET_LSB 0
  582. #define RX_MSDU_END_KEY_ID_OCTET_MSB 7
  583. #define RX_MSDU_END_KEY_ID_OCTET_MASK 0x000000ff
  584. #define RX_MSDU_END_RESERVED_16A_OFFSET 0x00000040
  585. #define RX_MSDU_END_RESERVED_16A_LSB 8
  586. #define RX_MSDU_END_RESERVED_16A_MSB 31
  587. #define RX_MSDU_END_RESERVED_16A_MASK 0xffffff00
  588. #define RX_MSDU_END_RESERVED_17A_OFFSET 0x00000044
  589. #define RX_MSDU_END_RESERVED_17A_LSB 0
  590. #define RX_MSDU_END_RESERVED_17A_MSB 5
  591. #define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f
  592. #define RX_MSDU_END_SERVICE_CODE_OFFSET 0x00000044
  593. #define RX_MSDU_END_SERVICE_CODE_LSB 6
  594. #define RX_MSDU_END_SERVICE_CODE_MSB 14
  595. #define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc0
  596. #define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x00000044
  597. #define RX_MSDU_END_PRIORITY_VALID_LSB 15
  598. #define RX_MSDU_END_PRIORITY_VALID_MSB 15
  599. #define RX_MSDU_END_PRIORITY_VALID_MASK 0x00008000
  600. #define RX_MSDU_END_INTRA_BSS_OFFSET 0x00000044
  601. #define RX_MSDU_END_INTRA_BSS_LSB 16
  602. #define RX_MSDU_END_INTRA_BSS_MSB 16
  603. #define RX_MSDU_END_INTRA_BSS_MASK 0x00010000
  604. #define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x00000044
  605. #define RX_MSDU_END_DEST_CHIP_ID_LSB 17
  606. #define RX_MSDU_END_DEST_CHIP_ID_MSB 18
  607. #define RX_MSDU_END_DEST_CHIP_ID_MASK 0x00060000
  608. #define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x00000044
  609. #define RX_MSDU_END_MULTICAST_ECHO_LSB 19
  610. #define RX_MSDU_END_MULTICAST_ECHO_MSB 19
  611. #define RX_MSDU_END_MULTICAST_ECHO_MASK 0x00080000
  612. #define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x00000044
  613. #define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 20
  614. #define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 20
  615. #define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x00100000
  616. #define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x00000044
  617. #define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 21
  618. #define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 21
  619. #define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x00200000
  620. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x00000044
  621. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 22
  622. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 22
  623. #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x00400000
  624. #define RX_MSDU_END_RESERVED_17B_OFFSET 0x00000044
  625. #define RX_MSDU_END_RESERVED_17B_LSB 24
  626. #define RX_MSDU_END_RESERVED_17B_MSB 31
  627. #define RX_MSDU_END_RESERVED_17B_MASK 0xff000000
  628. #define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x00000048
  629. #define RX_MSDU_END_MSDU_LENGTH_LSB 0
  630. #define RX_MSDU_END_MSDU_LENGTH_MSB 13
  631. #define RX_MSDU_END_MSDU_LENGTH_MASK 0x00003fff
  632. #define RX_MSDU_END_STBC_OFFSET 0x00000048
  633. #define RX_MSDU_END_STBC_LSB 14
  634. #define RX_MSDU_END_STBC_MSB 14
  635. #define RX_MSDU_END_STBC_MASK 0x00004000
  636. #define RX_MSDU_END_IPSEC_ESP_OFFSET 0x00000048
  637. #define RX_MSDU_END_IPSEC_ESP_LSB 15
  638. #define RX_MSDU_END_IPSEC_ESP_MSB 15
  639. #define RX_MSDU_END_IPSEC_ESP_MASK 0x00008000
  640. #define RX_MSDU_END_L3_OFFSET_OFFSET 0x00000048
  641. #define RX_MSDU_END_L3_OFFSET_LSB 16
  642. #define RX_MSDU_END_L3_OFFSET_MSB 22
  643. #define RX_MSDU_END_L3_OFFSET_MASK 0x007f0000
  644. #define RX_MSDU_END_IPSEC_AH_OFFSET 0x00000048
  645. #define RX_MSDU_END_IPSEC_AH_LSB 23
  646. #define RX_MSDU_END_IPSEC_AH_MSB 23
  647. #define RX_MSDU_END_IPSEC_AH_MASK 0x00800000
  648. #define RX_MSDU_END_L4_OFFSET_OFFSET 0x00000048
  649. #define RX_MSDU_END_L4_OFFSET_LSB 24
  650. #define RX_MSDU_END_L4_OFFSET_MSB 31
  651. #define RX_MSDU_END_L4_OFFSET_MASK 0xff000000
  652. #define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000004c
  653. #define RX_MSDU_END_MSDU_NUMBER_LSB 0
  654. #define RX_MSDU_END_MSDU_NUMBER_MSB 7
  655. #define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff
  656. #define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000004c
  657. #define RX_MSDU_END_DECAP_FORMAT_LSB 8
  658. #define RX_MSDU_END_DECAP_FORMAT_MSB 9
  659. #define RX_MSDU_END_DECAP_FORMAT_MASK 0x00000300
  660. #define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000004c
  661. #define RX_MSDU_END_IPV4_PROTO_LSB 10
  662. #define RX_MSDU_END_IPV4_PROTO_MSB 10
  663. #define RX_MSDU_END_IPV4_PROTO_MASK 0x00000400
  664. #define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000004c
  665. #define RX_MSDU_END_IPV6_PROTO_LSB 11
  666. #define RX_MSDU_END_IPV6_PROTO_MSB 11
  667. #define RX_MSDU_END_IPV6_PROTO_MASK 0x00000800
  668. #define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000004c
  669. #define RX_MSDU_END_TCP_PROTO_LSB 12
  670. #define RX_MSDU_END_TCP_PROTO_MSB 12
  671. #define RX_MSDU_END_TCP_PROTO_MASK 0x00001000
  672. #define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000004c
  673. #define RX_MSDU_END_UDP_PROTO_LSB 13
  674. #define RX_MSDU_END_UDP_PROTO_MSB 13
  675. #define RX_MSDU_END_UDP_PROTO_MASK 0x00002000
  676. #define RX_MSDU_END_IP_FRAG_OFFSET 0x0000004c
  677. #define RX_MSDU_END_IP_FRAG_LSB 14
  678. #define RX_MSDU_END_IP_FRAG_MSB 14
  679. #define RX_MSDU_END_IP_FRAG_MASK 0x00004000
  680. #define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000004c
  681. #define RX_MSDU_END_TCP_ONLY_ACK_LSB 15
  682. #define RX_MSDU_END_TCP_ONLY_ACK_MSB 15
  683. #define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x00008000
  684. #define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000004c
  685. #define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 16
  686. #define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 16
  687. #define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x00010000
  688. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000004c
  689. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 17
  690. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 18
  691. #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x00060000
  692. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000004c
  693. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 19
  694. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 19
  695. #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x00080000
  696. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000004c
  697. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 20
  698. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 20
  699. #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x00100000
  700. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000004c
  701. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 21
  702. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 21
  703. #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x00200000
  704. #define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000004c
  705. #define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 22
  706. #define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 22
  707. #define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x00400000
  708. #define RX_MSDU_END_LDPC_OFFSET 0x0000004c
  709. #define RX_MSDU_END_LDPC_LSB 23
  710. #define RX_MSDU_END_LDPC_MSB 23
  711. #define RX_MSDU_END_LDPC_MASK 0x00800000
  712. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000004c
  713. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24
  714. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31
  715. #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000
  716. #define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x00000050
  717. #define RX_MSDU_END_VLAN_CTAG_CI_LSB 0
  718. #define RX_MSDU_END_VLAN_CTAG_CI_MSB 15
  719. #define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x0000ffff
  720. #define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x00000050
  721. #define RX_MSDU_END_VLAN_STAG_CI_LSB 16
  722. #define RX_MSDU_END_VLAN_STAG_CI_MSB 31
  723. #define RX_MSDU_END_VLAN_STAG_CI_MASK 0xffff0000
  724. #define RX_MSDU_END_PEER_META_DATA_OFFSET 0x00000054
  725. #define RX_MSDU_END_PEER_META_DATA_LSB 0
  726. #define RX_MSDU_END_PEER_META_DATA_MSB 31
  727. #define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff
  728. #define RX_MSDU_END_USER_RSSI_OFFSET 0x00000058
  729. #define RX_MSDU_END_USER_RSSI_LSB 0
  730. #define RX_MSDU_END_USER_RSSI_MSB 7
  731. #define RX_MSDU_END_USER_RSSI_MASK 0x000000ff
  732. #define RX_MSDU_END_PKT_TYPE_OFFSET 0x00000058
  733. #define RX_MSDU_END_PKT_TYPE_LSB 8
  734. #define RX_MSDU_END_PKT_TYPE_MSB 11
  735. #define RX_MSDU_END_PKT_TYPE_MASK 0x00000f00
  736. #define RX_MSDU_END_SGI_OFFSET 0x00000058
  737. #define RX_MSDU_END_SGI_LSB 12
  738. #define RX_MSDU_END_SGI_MSB 13
  739. #define RX_MSDU_END_SGI_MASK 0x00003000
  740. #define RX_MSDU_END_RATE_MCS_OFFSET 0x00000058
  741. #define RX_MSDU_END_RATE_MCS_LSB 14
  742. #define RX_MSDU_END_RATE_MCS_MSB 17
  743. #define RX_MSDU_END_RATE_MCS_MASK 0x0003c000
  744. #define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x00000058
  745. #define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18
  746. #define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20
  747. #define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x001c0000
  748. #define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x00000058
  749. #define RX_MSDU_END_RECEPTION_TYPE_LSB 21
  750. #define RX_MSDU_END_RECEPTION_TYPE_MSB 23
  751. #define RX_MSDU_END_RECEPTION_TYPE_MASK 0x00e00000
  752. #define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x00000058
  753. #define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24
  754. #define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30
  755. #define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x7f000000
  756. #define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x00000058
  757. #define RX_MSDU_END_MSDU_DONE_COPY_LSB 31
  758. #define RX_MSDU_END_MSDU_DONE_COPY_MSB 31
  759. #define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x80000000
  760. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000005c
  761. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 0
  762. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 31
  763. #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff
  764. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000060
  765. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0
  766. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31
  767. #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
  768. #define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x00000064
  769. #define RX_MSDU_END_SW_PHY_META_DATA_LSB 0
  770. #define RX_MSDU_END_SW_PHY_META_DATA_MSB 31
  771. #define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff
  772. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000068
  773. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0
  774. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31
  775. #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
  776. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000006c
  777. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 0
  778. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 31
  779. #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff
  780. #define RX_MSDU_END_RESERVED_28A_OFFSET 0x00000070
  781. #define RX_MSDU_END_RESERVED_28A_LSB 0
  782. #define RX_MSDU_END_RESERVED_28A_MSB 15
  783. #define RX_MSDU_END_RESERVED_28A_MASK 0x0000ffff
  784. #define RX_MSDU_END_SA_15_0_OFFSET 0x00000070
  785. #define RX_MSDU_END_SA_15_0_LSB 16
  786. #define RX_MSDU_END_SA_15_0_MSB 31
  787. #define RX_MSDU_END_SA_15_0_MASK 0xffff0000
  788. #define RX_MSDU_END_SA_47_16_OFFSET 0x00000074
  789. #define RX_MSDU_END_SA_47_16_LSB 0
  790. #define RX_MSDU_END_SA_47_16_MSB 31
  791. #define RX_MSDU_END_SA_47_16_MASK 0xffffffff
  792. #define RX_MSDU_END_FIRST_MPDU_OFFSET 0x00000078
  793. #define RX_MSDU_END_FIRST_MPDU_LSB 0
  794. #define RX_MSDU_END_FIRST_MPDU_MSB 0
  795. #define RX_MSDU_END_FIRST_MPDU_MASK 0x00000001
  796. #define RX_MSDU_END_RESERVED_30A_OFFSET 0x00000078
  797. #define RX_MSDU_END_RESERVED_30A_LSB 1
  798. #define RX_MSDU_END_RESERVED_30A_MSB 1
  799. #define RX_MSDU_END_RESERVED_30A_MASK 0x00000002
  800. #define RX_MSDU_END_MCAST_BCAST_OFFSET 0x00000078
  801. #define RX_MSDU_END_MCAST_BCAST_LSB 2
  802. #define RX_MSDU_END_MCAST_BCAST_MSB 2
  803. #define RX_MSDU_END_MCAST_BCAST_MASK 0x00000004
  804. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x00000078
  805. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3
  806. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3
  807. #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x00000008
  808. #define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x00000078
  809. #define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4
  810. #define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4
  811. #define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x00000010
  812. #define RX_MSDU_END_POWER_MGMT_OFFSET 0x00000078
  813. #define RX_MSDU_END_POWER_MGMT_LSB 5
  814. #define RX_MSDU_END_POWER_MGMT_MSB 5
  815. #define RX_MSDU_END_POWER_MGMT_MASK 0x00000020
  816. #define RX_MSDU_END_NON_QOS_OFFSET 0x00000078
  817. #define RX_MSDU_END_NON_QOS_LSB 6
  818. #define RX_MSDU_END_NON_QOS_MSB 6
  819. #define RX_MSDU_END_NON_QOS_MASK 0x00000040
  820. #define RX_MSDU_END_NULL_DATA_OFFSET 0x00000078
  821. #define RX_MSDU_END_NULL_DATA_LSB 7
  822. #define RX_MSDU_END_NULL_DATA_MSB 7
  823. #define RX_MSDU_END_NULL_DATA_MASK 0x00000080
  824. #define RX_MSDU_END_MGMT_TYPE_OFFSET 0x00000078
  825. #define RX_MSDU_END_MGMT_TYPE_LSB 8
  826. #define RX_MSDU_END_MGMT_TYPE_MSB 8
  827. #define RX_MSDU_END_MGMT_TYPE_MASK 0x00000100
  828. #define RX_MSDU_END_CTRL_TYPE_OFFSET 0x00000078
  829. #define RX_MSDU_END_CTRL_TYPE_LSB 9
  830. #define RX_MSDU_END_CTRL_TYPE_MSB 9
  831. #define RX_MSDU_END_CTRL_TYPE_MASK 0x00000200
  832. #define RX_MSDU_END_MORE_DATA_OFFSET 0x00000078
  833. #define RX_MSDU_END_MORE_DATA_LSB 10
  834. #define RX_MSDU_END_MORE_DATA_MSB 10
  835. #define RX_MSDU_END_MORE_DATA_MASK 0x00000400
  836. #define RX_MSDU_END_EOSP_OFFSET 0x00000078
  837. #define RX_MSDU_END_EOSP_LSB 11
  838. #define RX_MSDU_END_EOSP_MSB 11
  839. #define RX_MSDU_END_EOSP_MASK 0x00000800
  840. #define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x00000078
  841. #define RX_MSDU_END_A_MSDU_ERROR_LSB 12
  842. #define RX_MSDU_END_A_MSDU_ERROR_MSB 12
  843. #define RX_MSDU_END_A_MSDU_ERROR_MASK 0x00001000
  844. #define RX_MSDU_END_RESERVED_30B_OFFSET 0x00000078
  845. #define RX_MSDU_END_RESERVED_30B_LSB 13
  846. #define RX_MSDU_END_RESERVED_30B_MSB 13
  847. #define RX_MSDU_END_RESERVED_30B_MASK 0x00002000
  848. #define RX_MSDU_END_ORDER_OFFSET 0x00000078
  849. #define RX_MSDU_END_ORDER_LSB 14
  850. #define RX_MSDU_END_ORDER_MSB 14
  851. #define RX_MSDU_END_ORDER_MASK 0x00004000
  852. #define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x00000078
  853. #define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15
  854. #define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15
  855. #define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x00008000
  856. #define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x00000078
  857. #define RX_MSDU_END_OVERFLOW_ERR_LSB 16
  858. #define RX_MSDU_END_OVERFLOW_ERR_MSB 16
  859. #define RX_MSDU_END_OVERFLOW_ERR_MASK 0x00010000
  860. #define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000078
  861. #define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17
  862. #define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17
  863. #define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x00020000
  864. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078
  865. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18
  866. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18
  867. #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000
  868. #define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x00000078
  869. #define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19
  870. #define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19
  871. #define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x00080000
  872. #define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x00000078
  873. #define RX_MSDU_END_SA_IDX_INVALID_LSB 20
  874. #define RX_MSDU_END_SA_IDX_INVALID_MSB 20
  875. #define RX_MSDU_END_SA_IDX_INVALID_MASK 0x00100000
  876. #define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x00000078
  877. #define RX_MSDU_END_DA_IDX_INVALID_LSB 21
  878. #define RX_MSDU_END_DA_IDX_INVALID_MSB 21
  879. #define RX_MSDU_END_DA_IDX_INVALID_MASK 0x00200000
  880. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x00000078
  881. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22
  882. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22
  883. #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x00400000
  884. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000078
  885. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23
  886. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23
  887. #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000
  888. #define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x00000078
  889. #define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24
  890. #define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24
  891. #define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x01000000
  892. #define RX_MSDU_END_DIRECTED_OFFSET 0x00000078
  893. #define RX_MSDU_END_DIRECTED_LSB 25
  894. #define RX_MSDU_END_DIRECTED_MSB 25
  895. #define RX_MSDU_END_DIRECTED_MASK 0x02000000
  896. #define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x00000078
  897. #define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26
  898. #define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26
  899. #define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x04000000
  900. #define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000078
  901. #define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27
  902. #define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27
  903. #define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x08000000
  904. #define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x00000078
  905. #define RX_MSDU_END_TKIP_MIC_ERR_LSB 28
  906. #define RX_MSDU_END_TKIP_MIC_ERR_MSB 28
  907. #define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x10000000
  908. #define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x00000078
  909. #define RX_MSDU_END_DECRYPT_ERR_LSB 29
  910. #define RX_MSDU_END_DECRYPT_ERR_MSB 29
  911. #define RX_MSDU_END_DECRYPT_ERR_MASK 0x20000000
  912. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000078
  913. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30
  914. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30
  915. #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x40000000
  916. #define RX_MSDU_END_FCS_ERR_OFFSET 0x00000078
  917. #define RX_MSDU_END_FCS_ERR_LSB 31
  918. #define RX_MSDU_END_FCS_ERR_MSB 31
  919. #define RX_MSDU_END_FCS_ERR_MASK 0x80000000
  920. #define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000007c
  921. #define RX_MSDU_END_RESERVED_31A_LSB 0
  922. #define RX_MSDU_END_RESERVED_31A_MSB 9
  923. #define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff
  924. #define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000007c
  925. #define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 10
  926. #define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 12
  927. #define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c00
  928. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000007c
  929. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 13
  930. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 13
  931. #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x00002000
  932. #define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000007c
  933. #define RX_MSDU_END_RESERVED_31B_LSB 14
  934. #define RX_MSDU_END_RESERVED_31B_MSB 30
  935. #define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc000
  936. #define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000007c
  937. #define RX_MSDU_END_MSDU_DONE_LSB 31
  938. #define RX_MSDU_END_MSDU_DONE_MSB 31
  939. #define RX_MSDU_END_MSDU_DONE_MASK 0x80000000
  940. #endif