txpcu_buffer_status.h 3.4 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697
  1. /*
  2. * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  3. * SPDX-License-Identifier: ISC
  4. */
  5. #ifndef _TXPCU_BUFFER_STATUS_H_
  6. #define _TXPCU_BUFFER_STATUS_H_
  7. #if !defined(__ASSEMBLER__)
  8. #endif
  9. #include "txpcu_buffer_basics.h"
  10. #define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2
  11. #define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1
  12. struct txpcu_buffer_status {
  13. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  14. struct txpcu_buffer_basics txpcu_basix_buffer_info;
  15. uint32_t reserved : 15,
  16. msdu_end : 1,
  17. tx_data_sync_value : 16;
  18. #else
  19. struct txpcu_buffer_basics txpcu_basix_buffer_info;
  20. uint32_t tx_data_sync_value : 16,
  21. msdu_end : 1,
  22. reserved : 15;
  23. #endif
  24. };
  25. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000
  26. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0
  27. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7
  28. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff
  29. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
  30. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
  31. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
  32. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00
  33. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
  34. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16
  35. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31
  36. #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000
  37. #define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000
  38. #define TXPCU_BUFFER_STATUS_RESERVED_LSB 32
  39. #define TXPCU_BUFFER_STATUS_RESERVED_MSB 46
  40. #define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000
  41. #define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000
  42. #define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47
  43. #define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47
  44. #define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000
  45. #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000
  46. #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48
  47. #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63
  48. #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000
  49. #endif