tx_flush_req.h 3.6 KB

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  1. /*
  2. * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  3. * SPDX-License-Identifier: ISC
  4. */
  5. #ifndef _TX_FLUSH_REQ_H_
  6. #define _TX_FLUSH_REQ_H_
  7. #if !defined(__ASSEMBLER__)
  8. #endif
  9. #define NUM_OF_DWORDS_TX_FLUSH_REQ 2
  10. #define NUM_OF_QWORDS_TX_FLUSH_REQ 1
  11. struct tx_flush_req {
  12. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  13. uint32_t flush_req_reason : 8,
  14. phytx_abort_reason : 8,
  15. flush_req_user_number_or_link_id : 6,
  16. mlo_abort_reason : 5,
  17. reserved_0a : 5;
  18. uint32_t tlv64_padding : 32;
  19. #else
  20. uint32_t reserved_0a : 5,
  21. mlo_abort_reason : 5,
  22. flush_req_user_number_or_link_id : 6,
  23. phytx_abort_reason : 8,
  24. flush_req_reason : 8;
  25. uint32_t tlv64_padding : 32;
  26. #endif
  27. };
  28. #define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000
  29. #define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0
  30. #define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7
  31. #define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff
  32. #define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
  33. #define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8
  34. #define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15
  35. #define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00
  36. #define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000
  37. #define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16
  38. #define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21
  39. #define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000
  40. #define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000
  41. #define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22
  42. #define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26
  43. #define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000
  44. #define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000
  45. #define TX_FLUSH_REQ_RESERVED_0A_LSB 27
  46. #define TX_FLUSH_REQ_RESERVED_0A_MSB 31
  47. #define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000
  48. #define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000
  49. #define TX_FLUSH_REQ_TLV64_PADDING_LSB 32
  50. #define TX_FLUSH_REQ_TLV64_PADDING_MSB 63
  51. #define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000
  52. #endif