tcl_entrance_from_ppe_ring.h 18 KB

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  1. /*
  2. * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  3. * SPDX-License-Identifier: ISC
  4. */
  5. #ifndef _TCL_ENTRANCE_FROM_PPE_RING_H_
  6. #define _TCL_ENTRANCE_FROM_PPE_RING_H_
  7. #if !defined(__ASSEMBLER__)
  8. #endif
  9. #define NUM_OF_DWORDS_TCL_ENTRANCE_FROM_PPE_RING 8
  10. struct tcl_entrance_from_ppe_ring {
  11. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  12. uint32_t buffer_addr_lo : 32;
  13. uint32_t buffer_addr_hi : 8,
  14. drop_prec : 2,
  15. fake_mac_header : 1,
  16. known_ind : 1,
  17. cpu_code_valid : 1,
  18. tunnel_term_ind : 1,
  19. tunnel_type : 1,
  20. wifi_qos_flag : 1,
  21. service_code : 9,
  22. reserved_1b : 1,
  23. int_pri : 4,
  24. more : 1,
  25. reserved_1a : 1;
  26. uint32_t opaque_lo : 32;
  27. uint32_t opaque_hi : 32;
  28. uint32_t src_info : 16,
  29. dst_info : 16;
  30. uint32_t data_length : 18,
  31. pool_id : 6,
  32. wifi_qos : 8;
  33. uint32_t data_offset : 12,
  34. l4_csum_status : 1,
  35. l3_csum_status : 1,
  36. hash_flag : 2,
  37. hash_value : 16;
  38. uint32_t dscp : 8,
  39. valid_toggle : 1,
  40. pppoe_flag : 1,
  41. svlan_flag : 1,
  42. cvlan_flag : 1,
  43. pid : 4,
  44. l3_offset : 8,
  45. l4_offset : 8;
  46. #else
  47. uint32_t buffer_addr_lo : 32;
  48. uint32_t reserved_1a : 1,
  49. more : 1,
  50. int_pri : 4,
  51. reserved_1b : 1,
  52. service_code : 9,
  53. wifi_qos_flag : 1,
  54. tunnel_type : 1,
  55. tunnel_term_ind : 1,
  56. cpu_code_valid : 1,
  57. known_ind : 1,
  58. fake_mac_header : 1,
  59. drop_prec : 2,
  60. buffer_addr_hi : 8;
  61. uint32_t opaque_lo : 32;
  62. uint32_t opaque_hi : 32;
  63. uint32_t dst_info : 16,
  64. src_info : 16;
  65. uint32_t wifi_qos : 8,
  66. pool_id : 6,
  67. data_length : 18;
  68. uint32_t hash_value : 16,
  69. hash_flag : 2,
  70. l3_csum_status : 1,
  71. l4_csum_status : 1,
  72. data_offset : 12;
  73. uint32_t l4_offset : 8,
  74. l3_offset : 8,
  75. pid : 4,
  76. cvlan_flag : 1,
  77. svlan_flag : 1,
  78. pppoe_flag : 1,
  79. valid_toggle : 1,
  80. dscp : 8;
  81. #endif
  82. };
  83. #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_OFFSET 0x00000000
  84. #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_LSB 0
  85. #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MSB 31
  86. #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MASK 0xffffffff
  87. #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_OFFSET 0x00000004
  88. #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_LSB 0
  89. #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MSB 7
  90. #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MASK 0x000000ff
  91. #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_OFFSET 0x00000004
  92. #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_LSB 8
  93. #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MSB 9
  94. #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MASK 0x00000300
  95. #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_OFFSET 0x00000004
  96. #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_LSB 10
  97. #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MSB 10
  98. #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MASK 0x00000400
  99. #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_OFFSET 0x00000004
  100. #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_LSB 11
  101. #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MSB 11
  102. #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MASK 0x00000800
  103. #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_OFFSET 0x00000004
  104. #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_LSB 12
  105. #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MSB 12
  106. #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MASK 0x00001000
  107. #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_OFFSET 0x00000004
  108. #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_LSB 13
  109. #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MSB 13
  110. #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MASK 0x00002000
  111. #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_OFFSET 0x00000004
  112. #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_LSB 14
  113. #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MSB 14
  114. #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MASK 0x00004000
  115. #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_OFFSET 0x00000004
  116. #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_LSB 15
  117. #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MSB 15
  118. #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MASK 0x00008000
  119. #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_OFFSET 0x00000004
  120. #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_LSB 16
  121. #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MSB 24
  122. #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MASK 0x01ff0000
  123. #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_OFFSET 0x00000004
  124. #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_LSB 25
  125. #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MSB 25
  126. #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MASK 0x02000000
  127. #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_OFFSET 0x00000004
  128. #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_LSB 26
  129. #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MSB 29
  130. #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MASK 0x3c000000
  131. #define TCL_ENTRANCE_FROM_PPE_RING_MORE_OFFSET 0x00000004
  132. #define TCL_ENTRANCE_FROM_PPE_RING_MORE_LSB 30
  133. #define TCL_ENTRANCE_FROM_PPE_RING_MORE_MSB 30
  134. #define TCL_ENTRANCE_FROM_PPE_RING_MORE_MASK 0x40000000
  135. #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_OFFSET 0x00000004
  136. #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_LSB 31
  137. #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MSB 31
  138. #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MASK 0x80000000
  139. #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_OFFSET 0x00000008
  140. #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_LSB 0
  141. #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MSB 31
  142. #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MASK 0xffffffff
  143. #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_OFFSET 0x0000000c
  144. #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_LSB 0
  145. #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MSB 31
  146. #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MASK 0xffffffff
  147. #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_OFFSET 0x00000010
  148. #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_LSB 0
  149. #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MSB 15
  150. #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MASK 0x0000ffff
  151. #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_OFFSET 0x00000010
  152. #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_LSB 16
  153. #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MSB 31
  154. #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MASK 0xffff0000
  155. #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_OFFSET 0x00000014
  156. #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_LSB 0
  157. #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MSB 17
  158. #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MASK 0x0003ffff
  159. #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_OFFSET 0x00000014
  160. #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_LSB 18
  161. #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MSB 23
  162. #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MASK 0x00fc0000
  163. #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_OFFSET 0x00000014
  164. #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_LSB 24
  165. #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MSB 31
  166. #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MASK 0xff000000
  167. #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_OFFSET 0x00000018
  168. #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_LSB 0
  169. #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MSB 11
  170. #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MASK 0x00000fff
  171. #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_OFFSET 0x00000018
  172. #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_LSB 12
  173. #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MSB 12
  174. #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MASK 0x00001000
  175. #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_OFFSET 0x00000018
  176. #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_LSB 13
  177. #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MSB 13
  178. #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MASK 0x00002000
  179. #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_OFFSET 0x00000018
  180. #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_LSB 14
  181. #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MSB 15
  182. #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MASK 0x0000c000
  183. #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_OFFSET 0x00000018
  184. #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_LSB 16
  185. #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MSB 31
  186. #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MASK 0xffff0000
  187. #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_OFFSET 0x0000001c
  188. #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_LSB 0
  189. #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MSB 7
  190. #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MASK 0x000000ff
  191. #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_OFFSET 0x0000001c
  192. #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_LSB 8
  193. #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MSB 8
  194. #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MASK 0x00000100
  195. #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_OFFSET 0x0000001c
  196. #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_LSB 9
  197. #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MSB 9
  198. #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MASK 0x00000200
  199. #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_OFFSET 0x0000001c
  200. #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_LSB 10
  201. #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MSB 10
  202. #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MASK 0x00000400
  203. #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_OFFSET 0x0000001c
  204. #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_LSB 11
  205. #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MSB 11
  206. #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MASK 0x00000800
  207. #define TCL_ENTRANCE_FROM_PPE_RING_PID_OFFSET 0x0000001c
  208. #define TCL_ENTRANCE_FROM_PPE_RING_PID_LSB 12
  209. #define TCL_ENTRANCE_FROM_PPE_RING_PID_MSB 15
  210. #define TCL_ENTRANCE_FROM_PPE_RING_PID_MASK 0x0000f000
  211. #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_OFFSET 0x0000001c
  212. #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_LSB 16
  213. #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MSB 23
  214. #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MASK 0x00ff0000
  215. #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_OFFSET 0x0000001c
  216. #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_LSB 24
  217. #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MSB 31
  218. #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MASK 0xff000000
  219. #endif