response_start_status.h 4.2 KB

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  1. /*
  2. * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  3. * SPDX-License-Identifier: ISC
  4. */
  5. #ifndef _RESPONSE_START_STATUS_H_
  6. #define _RESPONSE_START_STATUS_H_
  7. #if !defined(__ASSEMBLER__)
  8. #endif
  9. #define NUM_OF_DWORDS_RESPONSE_START_STATUS 2
  10. #define NUM_OF_QWORDS_RESPONSE_START_STATUS 1
  11. struct response_start_status {
  12. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  13. uint32_t generated_response : 3,
  14. ftm_tm : 2,
  15. trig_response_related : 1,
  16. response_sta_count : 7,
  17. reserved : 19;
  18. uint32_t phy_ppdu_id : 16,
  19. sw_peer_id : 16;
  20. #else
  21. uint32_t reserved : 19,
  22. response_sta_count : 7,
  23. trig_response_related : 1,
  24. ftm_tm : 2,
  25. generated_response : 3;
  26. uint32_t sw_peer_id : 16,
  27. phy_ppdu_id : 16;
  28. #endif
  29. };
  30. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000
  31. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0
  32. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2
  33. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007
  34. #define RESPONSE_START_STATUS_FTM_TM_OFFSET 0x0000000000000000
  35. #define RESPONSE_START_STATUS_FTM_TM_LSB 3
  36. #define RESPONSE_START_STATUS_FTM_TM_MSB 4
  37. #define RESPONSE_START_STATUS_FTM_TM_MASK 0x0000000000000018
  38. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000
  39. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5
  40. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5
  41. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020
  42. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000
  43. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6
  44. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12
  45. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0
  46. #define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000
  47. #define RESPONSE_START_STATUS_RESERVED_LSB 13
  48. #define RESPONSE_START_STATUS_RESERVED_MSB 31
  49. #define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000
  50. #define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000
  51. #define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32
  52. #define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47
  53. #define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000
  54. #define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000
  55. #define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48
  56. #define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63
  57. #define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000
  58. #endif