received_trigger_info_details.h 9.4 KB

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  1. /*
  2. * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  3. * SPDX-License-Identifier: ISC
  4. */
  5. #ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
  6. #define _RECEIVED_TRIGGER_INFO_DETAILS_H_
  7. #if !defined(__ASSEMBLER__)
  8. #endif
  9. #define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5
  10. struct received_trigger_info_details {
  11. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  12. uint32_t trigger_type : 4,
  13. ax_trigger_source : 1,
  14. ax_trigger_type : 4,
  15. trigger_source_sta_full_aid : 13,
  16. frame_control_valid : 1,
  17. qos_control_valid : 1,
  18. he_control_info_valid : 1,
  19. ranging_trigger_subtype : 4,
  20. reserved_0b : 3;
  21. uint32_t phy_ppdu_id : 16,
  22. lsig_response_length : 12,
  23. reserved_1a : 4;
  24. uint32_t frame_control : 16,
  25. qos_control : 16;
  26. uint32_t sw_peer_id : 16,
  27. reserved_3a : 16;
  28. uint32_t he_control : 32;
  29. #else
  30. uint32_t reserved_0b : 3,
  31. ranging_trigger_subtype : 4,
  32. he_control_info_valid : 1,
  33. qos_control_valid : 1,
  34. frame_control_valid : 1,
  35. trigger_source_sta_full_aid : 13,
  36. ax_trigger_type : 4,
  37. ax_trigger_source : 1,
  38. trigger_type : 4;
  39. uint32_t reserved_1a : 4,
  40. lsig_response_length : 12,
  41. phy_ppdu_id : 16;
  42. uint32_t qos_control : 16,
  43. frame_control : 16;
  44. uint32_t reserved_3a : 16,
  45. sw_peer_id : 16;
  46. uint32_t he_control : 32;
  47. #endif
  48. };
  49. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000
  50. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0
  51. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3
  52. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f
  53. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000
  54. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4
  55. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4
  56. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010
  57. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000
  58. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5
  59. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8
  60. #define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0
  61. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000
  62. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
  63. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
  64. #define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00
  65. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000
  66. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22
  67. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22
  68. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000
  69. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000
  70. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23
  71. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23
  72. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000
  73. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000
  74. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
  75. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
  76. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000
  77. #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000
  78. #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25
  79. #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28
  80. #define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000
  81. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
  82. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_LSB 29
  83. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MSB 31
  84. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MASK 0xe0000000
  85. #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004
  86. #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
  87. #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
  88. #define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
  89. #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004
  90. #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16
  91. #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27
  92. #define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000
  93. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
  94. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28
  95. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31
  96. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000
  97. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008
  98. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0
  99. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15
  100. #define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff
  101. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008
  102. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16
  103. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31
  104. #define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000
  105. #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c
  106. #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0
  107. #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15
  108. #define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff
  109. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c
  110. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 16
  111. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31
  112. #define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xffff0000
  113. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010
  114. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0
  115. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31
  116. #define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff
  117. #endif