reo_entrance_ring.h 45 KB

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  1. /*
  2. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _REO_ENTRANCE_RING_H_
  17. #define _REO_ENTRANCE_RING_H_
  18. #if !defined(__ASSEMBLER__)
  19. #endif
  20. #include "rx_mpdu_details.h"
  21. // ################ START SUMMARY #################
  22. //
  23. // Dword Fields
  24. // 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info;
  25. // 4 rx_reo_queue_desc_addr_31_0[31:0]
  26. // 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
  27. // 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], sw_exception[11], sw_exception_mpdu_delink[12], sw_exception_destination_ring_valid[13], sw_exception_destination_ring[18:14], reserved_6a[31:19]
  28. // 7 phy_ppdu_id[15:0], reserved_7a[19:16], ring_id[27:20], looping_count[31:28]
  29. //
  30. // ################ END SUMMARY #################
  31. #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
  32. struct reo_entrance_ring {
  33. struct rx_mpdu_details reo_level_mpdu_frame_info;
  34. uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
  35. uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
  36. rounded_mpdu_byte_count : 14, //[21:8]
  37. reo_destination_indication : 5, //[26:22]
  38. frameless_bar : 1, //[27]
  39. reserved_5a : 4; //[31:28]
  40. uint32_t rxdma_push_reason : 2, //[1:0]
  41. rxdma_error_code : 5, //[6:2]
  42. mpdu_fragment_number : 4, //[10:7]
  43. sw_exception : 1, //[11]
  44. sw_exception_mpdu_delink : 1, //[12]
  45. sw_exception_destination_ring_valid: 1, //[13]
  46. sw_exception_destination_ring : 5, //[18:14]
  47. reserved_6a : 13; //[31:19]
  48. uint32_t phy_ppdu_id : 16, //[15:0]
  49. reserved_7a : 4, //[19:16]
  50. ring_id : 8, //[27:20]
  51. looping_count : 4; //[31:28]
  52. };
  53. /*
  54. struct rx_mpdu_details reo_level_mpdu_frame_info
  55. Consumer: REO
  56. Producer: RXDMA
  57. Details related to the MPDU being pushed into the REO
  58. rx_reo_queue_desc_addr_31_0
  59. Consumer: REO
  60. Producer: RXDMA
  61. Address (lower 32 bits) of the REO queue descriptor.
  62. <legal all>
  63. rx_reo_queue_desc_addr_39_32
  64. Consumer: REO
  65. Producer: RXDMA
  66. Address (upper 8 bits) of the REO queue descriptor.
  67. <legal all>
  68. rounded_mpdu_byte_count
  69. An approximation of the number of bytes received in this
  70. MPDU.
  71. Used to keeps stats on the amount of data flowing
  72. through a queue.
  73. <legal all>
  74. reo_destination_indication
  75. RXDMA copy the MPDU's first MSDU's destination
  76. indication field here. This is used for REO to be able to
  77. re-route the packet to a different SW destination ring if
  78. the packet is detected as error in REO.
  79. The ID of the REO exit ring where the MSDU frame shall
  80. push after (MPDU level) reordering has finished.
  81. <enum 0 reo_destination_tcl> Reo will push the frame
  82. into the REO2TCL ring
  83. <enum 1 reo_destination_sw1> Reo will push the frame
  84. into the REO2SW1 ring
  85. <enum 2 reo_destination_sw2> Reo will push the frame
  86. into the REO2SW2 ring
  87. <enum 3 reo_destination_sw3> Reo will push the frame
  88. into the REO2SW3 ring
  89. <enum 4 reo_destination_sw4> Reo will push the frame
  90. into the REO2SW4 ring
  91. <enum 5 reo_destination_release> Reo will push the frame
  92. into the REO_release ring
  93. <enum 6 reo_destination_fw> Reo will push the frame into
  94. the REO2FW ring
  95. <enum 7 reo_destination_sw5> Reo will push the frame
  96. into the REO2SW5 ring (REO remaps this in chips without
  97. REO2SW5 ring, e.g. Pine)
  98. <enum 8 reo_destination_sw6> Reo will push the frame
  99. into the REO2SW6 ring (REO remaps this in chips without
  100. REO2SW6 ring, e.g. Pine)
  101. <enum 9 reo_destination_9> REO remaps this <enum 10
  102. reo_destination_10> REO remaps this
  103. <enum 11 reo_destination_11> REO remaps this
  104. <enum 12 reo_destination_12> REO remaps this <enum 13
  105. reo_destination_13> REO remaps this
  106. <enum 14 reo_destination_14> REO remaps this
  107. <enum 15 reo_destination_15> REO remaps this
  108. <enum 16 reo_destination_16> REO remaps this
  109. <enum 17 reo_destination_17> REO remaps this
  110. <enum 18 reo_destination_18> REO remaps this
  111. <enum 19 reo_destination_19> REO remaps this
  112. <enum 20 reo_destination_20> REO remaps this
  113. <enum 21 reo_destination_21> REO remaps this
  114. <enum 22 reo_destination_22> REO remaps this
  115. <enum 23 reo_destination_23> REO remaps this
  116. <enum 24 reo_destination_24> REO remaps this
  117. <enum 25 reo_destination_25> REO remaps this
  118. <enum 26 reo_destination_26> REO remaps this
  119. <enum 27 reo_destination_27> REO remaps this
  120. <enum 28 reo_destination_28> REO remaps this
  121. <enum 29 reo_destination_29> REO remaps this
  122. <enum 30 reo_destination_30> REO remaps this
  123. <enum 31 reo_destination_31> REO remaps this
  124. <legal all>
  125. frameless_bar
  126. When set, this REO entrance ring struct contains BAR
  127. info from a multi TID BAR frame. The original multi TID BAR
  128. frame itself contained all the REO info for the first TID,
  129. but all the subsequent TID info and their linkage to the REO
  130. descriptors is passed down as 'frameless' BAR info.
  131. The only fields valid in this descriptor when this bit
  132. is set are:
  133. Rx_reo_queue_desc_addr_31_0
  134. RX_reo_queue_desc_addr_39_32
  135. And within the
  136. Reo_level_mpdu_frame_info:
  137. Within Rx_mpdu_desc_info_details:
  138. Mpdu_Sequence_number
  139. BAR_frame
  140. Peer_meta_data
  141. All other fields shall be set to 0
  142. <legal all>
  143. reserved_5a
  144. <legal 0>
  145. rxdma_push_reason
  146. Indicates why rxdma pushed the frame to this ring
  147. This field is ignored by REO.
  148. <enum 0 rxdma_error_detected> RXDMA detected an error an
  149. pushed this frame to this queue
  150. <enum 1 rxdma_routing_instruction> RXDMA pushed the
  151. frame to this queue per received routing instructions. No
  152. error within RXDMA was detected
  153. <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
  154. result the MSDU link descriptor might not have the
  155. last_msdu_in_mpdu_flag set, but instead WBM might just see a
  156. NULL pointer in the MSDU link descriptor. This is to be
  157. considered a normal condition for this scenario.
  158. <legal 0 - 2>
  159. rxdma_error_code
  160. Field only valid when 'rxdma_push_reason' set to
  161. 'rxdma_error_detected'.
  162. This field is ignored by REO.
  163. <enum 0 rxdma_overflow_err>MPDU frame is not complete
  164. due to a FIFO overflow error in RXPCU.
  165. <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
  166. due to receiving incomplete MPDU from the PHY
  167. <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
  168. error or CRYPTO received an encrypted frame, but did not get
  169. a valid corresponding key id in the peer entry.
  170. <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
  171. error
  172. <enum 5 rxdma_unecrypted_err>CRYPTO reported an
  173. unencrypted frame error when encrypted was expected
  174. <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
  175. length error
  176. <enum 7 rxdma_msdu_limit_err>RX OLE reported that max
  177. number of MSDUs allowed in an MPDU got exceeded
  178. <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
  179. error
  180. <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
  181. parsing error
  182. <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
  183. during SA search
  184. <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
  185. during DA search
  186. <enum 12 rxdma_flow_timeout_err>RX OLE reported a
  187. timeout during flow search
  188. <enum 13 rxdma_flush_request>RXDMA received a flush
  189. request
  190. <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU
  191. present as well as a fragmented MPDU. A-MSDU defragmentation
  192. is not supported in Lithium SW so this is treated as an
  193. error.
  194. mpdu_fragment_number
  195. Field only valid when Reo_level_mpdu_frame_info.
  196. Rx_mpdu_desc_info_details.Fragment_flag is set.
  197. The fragment number from the 802.11 header.
  198. Note that the sequence number is embedded in the field:
  199. Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.
  200. Mpdu_sequence_number
  201. <legal all>
  202. sw_exception
  203. When not set, REO is performing all its default MPDU
  204. processing operations,
  205. When set, this REO entrance descriptor is generated by
  206. FW, and should be processed as an exception. This implies:
  207. NO re-order function is needed.
  208. MPDU delinking is determined by the setting of field
  209. SW_excection_mpdu_delink
  210. Destination ring selection is based on the setting of
  211. the field SW_exception_destination_ring_valid
  212. In the destination ring descriptor set bit:
  213. SW_exception_entry
  214. Feature supported only in HastingsPrime
  215. <legal all>
  216. sw_exception_mpdu_delink
  217. Field only valid when SW_exception is set.
  218. 1'b0: REO should NOT delink the MPDU, and thus pass this
  219. MPDU on to the destination ring as is. This implies that in
  220. the REO_DESTINATION_RING struct field
  221. Buf_or_link_desc_addr_info should point to an MSDU link
  222. descriptor
  223. 1'b1: REO should perform the normal MPDU delink into
  224. MSDU operations.
  225. Feature supported only in HastingsPrime
  226. <legal all>
  227. sw_exception_destination_ring_valid
  228. Field only valid when SW_exception is set.
  229. 1'b0: REO shall push the MPDU (or delinked MPDU based on
  230. the setting of SW_exception_mpdu_delink) to the destination
  231. ring according to field reo_destination_indication.
  232. 1'b1: REO shall push the MPDU (or delinked MPDU based on
  233. the setting of SW_exception_mpdu_delink) to the destination
  234. ring according to field SW_exception_destination_ring.
  235. Feature supported only in HastingsPrime
  236. <legal all>
  237. sw_exception_destination_ring
  238. Field only valid when fields SW_exception and
  239. SW_exception_destination_ring_valid are set.
  240. The ID of the ring where REO shall push this frame.
  241. <enum 0 reo_destination_tcl> Reo will push the frame
  242. into the REO2TCL ring
  243. <enum 1 reo_destination_sw1> Reo will push the frame
  244. into the REO2SW1 ring
  245. <enum 2 reo_destination_sw2> Reo will push the frame
  246. into the REO2SW1 ring
  247. <enum 3 reo_destination_sw3> Reo will push the frame
  248. into the REO2SW1 ring
  249. <enum 4 reo_destination_sw4> Reo will push the frame
  250. into the REO2SW1 ring
  251. <enum 5 reo_destination_release> Reo will push the frame
  252. into the REO_release ring
  253. <enum 6 reo_destination_fw> Reo will push the frame into
  254. the REO2FW ring
  255. <enum 7 reo_destination_sw5> REO remaps this
  256. <enum 8 reo_destination_sw6> REO remaps this
  257. <enum 9 reo_destination_9> REO remaps this
  258. <enum 10 reo_destination_10> REO remaps this
  259. <enum 11 reo_destination_11> REO remaps this
  260. <enum 12 reo_destination_12> REO remaps this <enum 13
  261. reo_destination_13> REO remaps this
  262. <enum 14 reo_destination_14> REO remaps this
  263. <enum 15 reo_destination_15> REO remaps this
  264. <enum 16 reo_destination_16> REO remaps this
  265. <enum 17 reo_destination_17> REO remaps this
  266. <enum 18 reo_destination_18> REO remaps this
  267. <enum 19 reo_destination_19> REO remaps this
  268. <enum 20 reo_destination_20> REO remaps this
  269. <enum 21 reo_destination_21> REO remaps this
  270. <enum 22 reo_destination_22> REO remaps this
  271. <enum 23 reo_destination_23> REO remaps this
  272. <enum 24 reo_destination_24> REO remaps this
  273. <enum 25 reo_destination_25> REO remaps this
  274. <enum 26 reo_destination_26> REO remaps this
  275. <enum 27 reo_destination_27> REO remaps this
  276. <enum 28 reo_destination_28> REO remaps this
  277. <enum 29 reo_destination_29> REO remaps this
  278. <enum 30 reo_destination_30> REO remaps this
  279. <enum 31 reo_destination_31> REO remaps this
  280. Feature supported only in HastingsPrime
  281. <legal all>
  282. reserved_6a
  283. <legal 0>
  284. phy_ppdu_id
  285. A PPDU counter value that PHY increments for every PPDU
  286. received
  287. The counter value wraps around. Pine RXDMA can be
  288. configured to copy this from the RX_PPDU_START TLV for every
  289. output descriptor.
  290. This field is ignored by REO.
  291. Feature supported only in Pine
  292. <legal all>
  293. reserved_7a
  294. <legal 0>
  295. ring_id
  296. Consumer: SW/REO/DEBUG
  297. Producer: SRNG (of RXDMA)
  298. For debugging.
  299. This field is filled in by the SRNG module.
  300. It help to identify the ring that is being looked <legal
  301. all>
  302. looping_count
  303. Consumer: SW/REO/DEBUG
  304. Producer: SRNG (of RXDMA)
  305. For debugging.
  306. This field is filled in by the SRNG module.
  307. A count value that indicates the number of times the
  308. producer of entries into this Ring has looped around the
  309. ring.
  310. At initialization time, this value is set to 0. On the
  311. first loop, this value is set to 1. After the max value is
  312. reached allowed by the number of bits for this field, the
  313. count value continues with 0 again.
  314. In case SW is the consumer of the ring entries, it can
  315. use this field to figure out up to where the producer of
  316. entries has created new entries. This eliminates the need to
  317. check where the head pointer' of the ring is located once
  318. the SW starts processing an interrupt indicating that new
  319. entries have been put into this ring...
  320. Also note that SW if it wants only needs to look at the
  321. LSB bit of this count value.
  322. <legal all>
  323. */
  324. /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */
  325. /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */
  326. /* Description REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  327. Address (lower 32 bits) of the MSDU buffer OR
  328. MSDU_EXTENSION descriptor OR Link Descriptor
  329. In case of 'NULL' pointer, this field is set to 0
  330. <legal all>
  331. */
  332. #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
  333. #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  334. #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  335. /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  336. Address (upper 8 bits) of the MSDU buffer OR
  337. MSDU_EXTENSION descriptor OR Link Descriptor
  338. In case of 'NULL' pointer, this field is set to 0
  339. <legal all>
  340. */
  341. #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
  342. #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  343. #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  344. /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  345. Consumer: WBM
  346. Producer: SW/FW
  347. In case of 'NULL' pointer, this field is set to 0
  348. Indicates to which buffer manager the buffer OR
  349. MSDU_EXTENSION descriptor OR link descriptor that is being
  350. pointed to shall be returned after the frame has been
  351. processed. It is used by WBM for routing purposes.
  352. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  353. to the WMB buffer idle list
  354. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  355. returned to the WMB idle link descriptor idle list
  356. <enum 2 FW_BM> This buffer shall be returned to the FW
  357. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  358. ring 0
  359. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  360. ring 1
  361. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  362. ring 2
  363. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  364. ring 3
  365. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  366. ring 4
  367. <legal all>
  368. */
  369. #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
  370. #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  371. #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  372. /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  373. Cookie field exclusively used by SW.
  374. In case of 'NULL' pointer, this field is set to 0
  375. HW ignores the contents, accept that it passes the
  376. programmed value on to other descriptors together with the
  377. physical address
  378. Field can be used by SW to for example associate the
  379. buffers physical address with the virtual address
  380. The bit definitions as used by SW are within SW HLD
  381. specification
  382. NOTE1:
  383. The three most significant bits can have a special
  384. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  385. STRUCT, and field transmit_bw_restriction is set
  386. In case of NON punctured transmission:
  387. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  388. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  389. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  390. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  391. In case of punctured transmission:
  392. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  393. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  394. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  395. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  396. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  397. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  398. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  399. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  400. Note: a punctured transmission is indicated by the
  401. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  402. TLV
  403. NOTE 2:The five most significant bits can have a special
  404. meaning in case this struct is embedded in an
  405. RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
  406. configured for passing on the additional info
  407. from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
  408. (FR56821). This is not supported in HastingsPrime, Pine or
  409. Moselle.
  410. Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
  411. control field
  412. Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
  413. indicates MPDUs with a QoS control field.
  414. <legal all>
  415. */
  416. #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
  417. #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  418. #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  419. /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */
  420. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT
  421. Consumer: REO/SW/FW
  422. Producer: RXDMA
  423. The number of MSDUs within the MPDU
  424. <legal all>
  425. */
  426. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
  427. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
  428. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
  429. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
  430. Consumer: REO/SW/FW
  431. Producer: RXDMA
  432. The field can have two different meanings based on the
  433. setting of field 'BAR_frame':
  434. 'BAR_frame' is NOT set:
  435. The MPDU sequence number of the received frame.
  436. 'BAR_frame' is set.
  437. The MPDU Start sequence number from the BAR frame
  438. <legal all>
  439. */
  440. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
  441. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
  442. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
  443. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG
  444. Consumer: REO/SW/FW
  445. Producer: RXDMA
  446. When set, this MPDU is a fragment and REO should forward
  447. this fragment MPDU to the REO destination ring without any
  448. reorder checks, pn checks or bitmap update. This implies
  449. that REO is forwarding the pointer to the MSDU link
  450. descriptor. The destination ring is coming from a
  451. programmable register setting in REO
  452. <legal all>
  453. */
  454. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
  455. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
  456. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
  457. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT
  458. Consumer: REO/SW/FW
  459. Producer: RXDMA
  460. The retry bit setting from the MPDU header of the
  461. received frame
  462. <legal all>
  463. */
  464. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
  465. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
  466. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
  467. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG
  468. Consumer: REO/SW/FW
  469. Producer: RXDMA
  470. When set, the MPDU was received as part of an A-MPDU.
  471. <legal all>
  472. */
  473. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
  474. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
  475. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
  476. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME
  477. Consumer: REO/SW/FW
  478. Producer: RXDMA
  479. When set, the received frame is a BAR frame. After
  480. processing, this frame shall be pushed to SW or deleted.
  481. <legal all>
  482. */
  483. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
  484. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
  485. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
  486. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO
  487. Consumer: REO/SW/FW
  488. Producer: RXDMA
  489. Copied here by RXDMA from RX_MPDU_END
  490. When not set, REO will Not perform a PN sequence number
  491. check
  492. */
  493. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
  494. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
  495. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
  496. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID
  497. When set, OLE found a valid SA entry for all MSDUs in
  498. this MPDU
  499. <legal all>
  500. */
  501. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
  502. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
  503. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
  504. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
  505. When set, at least 1 MSDU within the MPDU has an
  506. unsuccessful MAC source address search due to the expiration
  507. of the search timer.
  508. <legal all>
  509. */
  510. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
  511. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
  512. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
  513. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID
  514. When set, OLE found a valid DA entry for all MSDUs in
  515. this MPDU
  516. <legal all>
  517. */
  518. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
  519. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
  520. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
  521. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC
  522. Field Only valid if da_is_valid is set
  523. When set, at least one of the DA addresses is a
  524. Multicast or Broadcast address.
  525. <legal all>
  526. */
  527. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
  528. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
  529. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
  530. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
  531. When set, at least 1 MSDU within the MPDU has an
  532. unsuccessful MAC destination address search due to the
  533. expiration of the search timer.
  534. <legal all>
  535. */
  536. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
  537. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
  538. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
  539. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU
  540. Field only valid when first_msdu_in_mpdu_flag is set.
  541. When set, the contents in the MSDU buffer contains a
  542. 'RAW' MPDU. This 'RAW' MPDU might be spread out over
  543. multiple MSDU buffers.
  544. <legal all>
  545. */
  546. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
  547. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
  548. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
  549. /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG
  550. The More Fragment bit setting from the MPDU header of
  551. the received frame
  552. <legal all>
  553. */
  554. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
  555. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
  556. #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
  557. /* Description REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA
  558. Meta data that SW has programmed in the Peer table entry
  559. of the transmitting STA.
  560. <legal all>
  561. */
  562. #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
  563. #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
  564. #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
  565. /* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0
  566. Consumer: REO
  567. Producer: RXDMA
  568. Address (lower 32 bits) of the REO queue descriptor.
  569. <legal all>
  570. */
  571. #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
  572. #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
  573. #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
  574. /* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32
  575. Consumer: REO
  576. Producer: RXDMA
  577. Address (upper 8 bits) of the REO queue descriptor.
  578. <legal all>
  579. */
  580. #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
  581. #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
  582. #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
  583. /* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT
  584. An approximation of the number of bytes received in this
  585. MPDU.
  586. Used to keeps stats on the amount of data flowing
  587. through a queue.
  588. <legal all>
  589. */
  590. #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
  591. #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8
  592. #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
  593. /* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION
  594. RXDMA copy the MPDU's first MSDU's destination
  595. indication field here. This is used for REO to be able to
  596. re-route the packet to a different SW destination ring if
  597. the packet is detected as error in REO.
  598. The ID of the REO exit ring where the MSDU frame shall
  599. push after (MPDU level) reordering has finished.
  600. <enum 0 reo_destination_tcl> Reo will push the frame
  601. into the REO2TCL ring
  602. <enum 1 reo_destination_sw1> Reo will push the frame
  603. into the REO2SW1 ring
  604. <enum 2 reo_destination_sw2> Reo will push the frame
  605. into the REO2SW2 ring
  606. <enum 3 reo_destination_sw3> Reo will push the frame
  607. into the REO2SW3 ring
  608. <enum 4 reo_destination_sw4> Reo will push the frame
  609. into the REO2SW4 ring
  610. <enum 5 reo_destination_release> Reo will push the frame
  611. into the REO_release ring
  612. <enum 6 reo_destination_fw> Reo will push the frame into
  613. the REO2FW ring
  614. <enum 7 reo_destination_sw5> Reo will push the frame
  615. into the REO2SW5 ring (REO remaps this in chips without
  616. REO2SW5 ring, e.g. Pine)
  617. <enum 8 reo_destination_sw6> Reo will push the frame
  618. into the REO2SW6 ring (REO remaps this in chips without
  619. REO2SW6 ring, e.g. Pine)
  620. <enum 9 reo_destination_9> REO remaps this <enum 10
  621. reo_destination_10> REO remaps this
  622. <enum 11 reo_destination_11> REO remaps this
  623. <enum 12 reo_destination_12> REO remaps this <enum 13
  624. reo_destination_13> REO remaps this
  625. <enum 14 reo_destination_14> REO remaps this
  626. <enum 15 reo_destination_15> REO remaps this
  627. <enum 16 reo_destination_16> REO remaps this
  628. <enum 17 reo_destination_17> REO remaps this
  629. <enum 18 reo_destination_18> REO remaps this
  630. <enum 19 reo_destination_19> REO remaps this
  631. <enum 20 reo_destination_20> REO remaps this
  632. <enum 21 reo_destination_21> REO remaps this
  633. <enum 22 reo_destination_22> REO remaps this
  634. <enum 23 reo_destination_23> REO remaps this
  635. <enum 24 reo_destination_24> REO remaps this
  636. <enum 25 reo_destination_25> REO remaps this
  637. <enum 26 reo_destination_26> REO remaps this
  638. <enum 27 reo_destination_27> REO remaps this
  639. <enum 28 reo_destination_28> REO remaps this
  640. <enum 29 reo_destination_29> REO remaps this
  641. <enum 30 reo_destination_30> REO remaps this
  642. <enum 31 reo_destination_31> REO remaps this
  643. <legal all>
  644. */
  645. #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014
  646. #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22
  647. #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000
  648. /* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR
  649. When set, this REO entrance ring struct contains BAR
  650. info from a multi TID BAR frame. The original multi TID BAR
  651. frame itself contained all the REO info for the first TID,
  652. but all the subsequent TID info and their linkage to the REO
  653. descriptors is passed down as 'frameless' BAR info.
  654. The only fields valid in this descriptor when this bit
  655. is set are:
  656. Rx_reo_queue_desc_addr_31_0
  657. RX_reo_queue_desc_addr_39_32
  658. And within the
  659. Reo_level_mpdu_frame_info:
  660. Within Rx_mpdu_desc_info_details:
  661. Mpdu_Sequence_number
  662. BAR_frame
  663. Peer_meta_data
  664. All other fields shall be set to 0
  665. <legal all>
  666. */
  667. #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014
  668. #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27
  669. #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000
  670. /* Description REO_ENTRANCE_RING_5_RESERVED_5A
  671. <legal 0>
  672. */
  673. #define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014
  674. #define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28
  675. #define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000
  676. /* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON
  677. Indicates why rxdma pushed the frame to this ring
  678. This field is ignored by REO.
  679. <enum 0 rxdma_error_detected> RXDMA detected an error an
  680. pushed this frame to this queue
  681. <enum 1 rxdma_routing_instruction> RXDMA pushed the
  682. frame to this queue per received routing instructions. No
  683. error within RXDMA was detected
  684. <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
  685. result the MSDU link descriptor might not have the
  686. last_msdu_in_mpdu_flag set, but instead WBM might just see a
  687. NULL pointer in the MSDU link descriptor. This is to be
  688. considered a normal condition for this scenario.
  689. <legal 0 - 2>
  690. */
  691. #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018
  692. #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0
  693. #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003
  694. /* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE
  695. Field only valid when 'rxdma_push_reason' set to
  696. 'rxdma_error_detected'.
  697. This field is ignored by REO.
  698. <enum 0 rxdma_overflow_err>MPDU frame is not complete
  699. due to a FIFO overflow error in RXPCU.
  700. <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
  701. due to receiving incomplete MPDU from the PHY
  702. <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
  703. error or CRYPTO received an encrypted frame, but did not get
  704. a valid corresponding key id in the peer entry.
  705. <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
  706. error
  707. <enum 5 rxdma_unecrypted_err>CRYPTO reported an
  708. unencrypted frame error when encrypted was expected
  709. <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
  710. length error
  711. <enum 7 rxdma_msdu_limit_err>RX OLE reported that max
  712. number of MSDUs allowed in an MPDU got exceeded
  713. <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
  714. error
  715. <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
  716. parsing error
  717. <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
  718. during SA search
  719. <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
  720. during DA search
  721. <enum 12 rxdma_flow_timeout_err>RX OLE reported a
  722. timeout during flow search
  723. <enum 13 rxdma_flush_request>RXDMA received a flush
  724. request
  725. <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU
  726. present as well as a fragmented MPDU. A-MSDU defragmentation
  727. is not supported in Lithium SW so this is treated as an
  728. error.
  729. */
  730. #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018
  731. #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2
  732. #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c
  733. /* Description REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER
  734. Field only valid when Reo_level_mpdu_frame_info.
  735. Rx_mpdu_desc_info_details.Fragment_flag is set.
  736. The fragment number from the 802.11 header.
  737. Note that the sequence number is embedded in the field:
  738. Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.
  739. Mpdu_sequence_number
  740. <legal all>
  741. */
  742. #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018
  743. #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7
  744. #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
  745. /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION
  746. When not set, REO is performing all its default MPDU
  747. processing operations,
  748. When set, this REO entrance descriptor is generated by
  749. FW, and should be processed as an exception. This implies:
  750. NO re-order function is needed.
  751. MPDU delinking is determined by the setting of field
  752. SW_excection_mpdu_delink
  753. Destination ring selection is based on the setting of
  754. the field SW_exception_destination_ring_valid
  755. In the destination ring descriptor set bit:
  756. SW_exception_entry
  757. Feature supported only in HastingsPrime
  758. <legal all>
  759. */
  760. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET 0x00000018
  761. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB 11
  762. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK 0x00000800
  763. /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK
  764. Field only valid when SW_exception is set.
  765. 1'b0: REO should NOT delink the MPDU, and thus pass this
  766. MPDU on to the destination ring as is. This implies that in
  767. the REO_DESTINATION_RING struct field
  768. Buf_or_link_desc_addr_info should point to an MSDU link
  769. descriptor
  770. 1'b1: REO should perform the normal MPDU delink into
  771. MSDU operations.
  772. Feature supported only in HastingsPrime
  773. <legal all>
  774. */
  775. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018
  776. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB 12
  777. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000
  778. /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID
  779. Field only valid when SW_exception is set.
  780. 1'b0: REO shall push the MPDU (or delinked MPDU based on
  781. the setting of SW_exception_mpdu_delink) to the destination
  782. ring according to field reo_destination_indication.
  783. 1'b1: REO shall push the MPDU (or delinked MPDU based on
  784. the setting of SW_exception_mpdu_delink) to the destination
  785. ring according to field SW_exception_destination_ring.
  786. Feature supported only in HastingsPrime
  787. <legal all>
  788. */
  789. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
  790. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13
  791. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
  792. /* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING
  793. Field only valid when fields SW_exception and
  794. SW_exception_destination_ring_valid are set.
  795. The ID of the ring where REO shall push this frame.
  796. <enum 0 reo_destination_tcl> Reo will push the frame
  797. into the REO2TCL ring
  798. <enum 1 reo_destination_sw1> Reo will push the frame
  799. into the REO2SW1 ring
  800. <enum 2 reo_destination_sw2> Reo will push the frame
  801. into the REO2SW1 ring
  802. <enum 3 reo_destination_sw3> Reo will push the frame
  803. into the REO2SW1 ring
  804. <enum 4 reo_destination_sw4> Reo will push the frame
  805. into the REO2SW1 ring
  806. <enum 5 reo_destination_release> Reo will push the frame
  807. into the REO_release ring
  808. <enum 6 reo_destination_fw> Reo will push the frame into
  809. the REO2FW ring
  810. <enum 7 reo_destination_sw5> REO remaps this
  811. <enum 8 reo_destination_sw6> REO remaps this
  812. <enum 9 reo_destination_9> REO remaps this
  813. <enum 10 reo_destination_10> REO remaps this
  814. <enum 11 reo_destination_11> REO remaps this
  815. <enum 12 reo_destination_12> REO remaps this <enum 13
  816. reo_destination_13> REO remaps this
  817. <enum 14 reo_destination_14> REO remaps this
  818. <enum 15 reo_destination_15> REO remaps this
  819. <enum 16 reo_destination_16> REO remaps this
  820. <enum 17 reo_destination_17> REO remaps this
  821. <enum 18 reo_destination_18> REO remaps this
  822. <enum 19 reo_destination_19> REO remaps this
  823. <enum 20 reo_destination_20> REO remaps this
  824. <enum 21 reo_destination_21> REO remaps this
  825. <enum 22 reo_destination_22> REO remaps this
  826. <enum 23 reo_destination_23> REO remaps this
  827. <enum 24 reo_destination_24> REO remaps this
  828. <enum 25 reo_destination_25> REO remaps this
  829. <enum 26 reo_destination_26> REO remaps this
  830. <enum 27 reo_destination_27> REO remaps this
  831. <enum 28 reo_destination_28> REO remaps this
  832. <enum 29 reo_destination_29> REO remaps this
  833. <enum 30 reo_destination_30> REO remaps this
  834. <enum 31 reo_destination_31> REO remaps this
  835. Feature supported only in HastingsPrime
  836. <legal all>
  837. */
  838. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018
  839. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB 14
  840. #define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000
  841. /* Description REO_ENTRANCE_RING_6_RESERVED_6A
  842. <legal 0>
  843. */
  844. #define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018
  845. #define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 19
  846. #define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfff80000
  847. /* Description REO_ENTRANCE_RING_7_PHY_PPDU_ID
  848. A PPDU counter value that PHY increments for every PPDU
  849. received
  850. The counter value wraps around. Pine RXDMA can be
  851. configured to copy this from the RX_PPDU_START TLV for every
  852. output descriptor.
  853. This field is ignored by REO.
  854. Feature supported only in Pine
  855. <legal all>
  856. */
  857. #define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c
  858. #define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB 0
  859. #define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK 0x0000ffff
  860. /* Description REO_ENTRANCE_RING_7_RESERVED_7A
  861. <legal 0>
  862. */
  863. #define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c
  864. #define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 16
  865. #define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000f0000
  866. /* Description REO_ENTRANCE_RING_7_RING_ID
  867. Consumer: SW/REO/DEBUG
  868. Producer: SRNG (of RXDMA)
  869. For debugging.
  870. This field is filled in by the SRNG module.
  871. It help to identify the ring that is being looked <legal
  872. all>
  873. */
  874. #define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c
  875. #define REO_ENTRANCE_RING_7_RING_ID_LSB 20
  876. #define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000
  877. /* Description REO_ENTRANCE_RING_7_LOOPING_COUNT
  878. Consumer: SW/REO/DEBUG
  879. Producer: SRNG (of RXDMA)
  880. For debugging.
  881. This field is filled in by the SRNG module.
  882. A count value that indicates the number of times the
  883. producer of entries into this Ring has looped around the
  884. ring.
  885. At initialization time, this value is set to 0. On the
  886. first loop, this value is set to 1. After the max value is
  887. reached allowed by the number of bits for this field, the
  888. count value continues with 0 again.
  889. In case SW is the consumer of the ring entries, it can
  890. use this field to figure out up to where the producer of
  891. entries has created new entries. This eliminates the need to
  892. check where the head pointer' of the ring is located once
  893. the SW starts processing an interrupt indicating that new
  894. entries have been put into this ring...
  895. Also note that SW if it wants only needs to look at the
  896. LSB bit of this count value.
  897. <legal all>
  898. */
  899. #define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
  900. #define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28
  901. #define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000
  902. #endif // _REO_ENTRANCE_RING_H_