rx_response_required_info.h 51 KB

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  1. /*
  2. * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _RX_RESPONSE_REQUIRED_INFO_H_
  17. #define _RX_RESPONSE_REQUIRED_INFO_H_
  18. #include "mlo_sta_id_details.h"
  19. #define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 15
  20. struct rx_response_required_info {
  21. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  22. uint32_t phy_ppdu_id : 16,
  23. su_or_uplink_mu_reception : 1,
  24. trigger_frame_received : 1,
  25. __reserved_g_0012 : 2,
  26. tb___reserved_g_0005_response_required : 2,
  27. mac_security : 1,
  28. filter_pass_monitor_ovrd : 1,
  29. ast_search_incomplete : 1,
  30. r2r_end_status_to_follow : 1,
  31. __reserved_g_0016_listen_cca_check_at_phy_desc : 1,
  32. __reserved_g_0016_listen_indication : 1,
  33. three_or_more_type_subtypes : 1,
  34. wait_sifs_config_valid : 1,
  35. wait_sifs : 2;
  36. uint32_t general_frame_control : 16,
  37. second_frame_control : 16;
  38. uint32_t duration : 16,
  39. pkt_type : 4,
  40. dot11ax_su_extended : 1,
  41. rate_mcs : 4,
  42. sgi : 2,
  43. stbc : 1,
  44. ldpc : 1,
  45. ampdu : 1,
  46. vht_ack : 1,
  47. rts_ta_grp_bit : 1;
  48. uint32_t ctrl_frame_soliciting_resp : 1,
  49. ast_fail_for_dot11ax_su_ext : 1,
  50. service_dynamic : 1,
  51. m_pkt : 1,
  52. sta_partial_aid : 12,
  53. group_id : 6,
  54. ctrl_resp_pwr_mgmt : 1,
  55. response_indication : 2,
  56. ndp_indication : 1,
  57. ndp_frame_type : 3,
  58. second_frame_control_valid : 1,
  59. ack_ba_resp_more_data : 1,
  60. reserved_3a : 1;
  61. uint32_t ack_id : 16,
  62. ack_id_ext : 10,
  63. agc_cbw : 3,
  64. service_cbw : 3;
  65. uint32_t response_sta_count : 7,
  66. reserved : 4,
  67. ht_vht_sig_cbw : 3,
  68. cts_cbw : 3,
  69. response_ack_count : 7,
  70. response_assoc_ack_count : 7,
  71. txop_duration_all_ones : 1;
  72. uint32_t response_ba32_count : 7,
  73. response_ba64_count : 7,
  74. response_ba128_count : 7,
  75. response_ba256_count : 7,
  76. multi_tid : 1,
  77. sw_response_tlv_from_crypto : 1,
  78. dot11ax_dl_ul_flag : 1,
  79. emlsr_main_tlv_if : 1;
  80. uint32_t sw_response_frame_length : 16,
  81. response_ba512_count : 7,
  82. response_ba1024_count : 7,
  83. reserved_7a : 2;
  84. uint32_t addr1_31_0 : 32;
  85. uint32_t addr1_47_32 : 16,
  86. addr2_15_0 : 16;
  87. uint32_t addr2_47_16 : 32;
  88. uint32_t dot11ax_received_format_indication : 1,
  89. dot11ax_received_dl_ul_flag : 1,
  90. dot11ax_received_bss_color_id : 6,
  91. dot11ax_received_spatial_reuse : 4,
  92. dot11ax_received_cp_size : 2,
  93. dot11ax_received_ltf_size : 2,
  94. dot11ax_received_coding : 1,
  95. dot11ax_received_dcm : 1,
  96. dot11ax_received_doppler_indication : 1,
  97. dot11ax_received_ext_ru_size : 4,
  98. ftm_fields_valid : 1,
  99. ftm_pe_nss : 3,
  100. ftm_pe_ltf_size : 2,
  101. ftm_pe_content : 1,
  102. ftm_chain_csd_en : 1,
  103. ftm_pe_chain_csd_en : 1;
  104. uint32_t dot11ax_response_rate_source : 8,
  105. dot11ax_ext_response_rate_source : 8,
  106. sw_peer_id : 16;
  107. uint32_t dot11be_puncture_bitmap : 16,
  108. dot11be_response : 1,
  109. punctured_response : 1,
  110. eht_duplicate_mode : 2,
  111. force_extra_symbol : 1,
  112. reserved_13a : 5,
  113. u_sig_puncture_pattern_encoding : 6;
  114. struct mlo_sta_id_details mlo_sta_id_details_rx;
  115. uint16_t he_a_control_response_time : 12,
  116. reserved_after_struct16 : 4;
  117. #else
  118. uint32_t wait_sifs : 2,
  119. wait_sifs_config_valid : 1,
  120. three_or_more_type_subtypes : 1,
  121. __reserved_g_0016_listen_indication : 1,
  122. __reserved_g_0016_listen_cca_check_at_phy_desc : 1,
  123. r2r_end_status_to_follow : 1,
  124. ast_search_incomplete : 1,
  125. filter_pass_monitor_ovrd : 1,
  126. mac_security : 1,
  127. tb___reserved_g_0005_response_required : 2,
  128. __reserved_g_0012 : 2,
  129. trigger_frame_received : 1,
  130. su_or_uplink_mu_reception : 1,
  131. phy_ppdu_id : 16;
  132. uint32_t second_frame_control : 16,
  133. general_frame_control : 16;
  134. uint32_t rts_ta_grp_bit : 1,
  135. vht_ack : 1,
  136. ampdu : 1,
  137. ldpc : 1,
  138. stbc : 1,
  139. sgi : 2,
  140. rate_mcs : 4,
  141. dot11ax_su_extended : 1,
  142. pkt_type : 4,
  143. duration : 16;
  144. uint32_t reserved_3a : 1,
  145. ack_ba_resp_more_data : 1,
  146. second_frame_control_valid : 1,
  147. ndp_frame_type : 3,
  148. ndp_indication : 1,
  149. response_indication : 2,
  150. ctrl_resp_pwr_mgmt : 1,
  151. group_id : 6,
  152. sta_partial_aid : 12,
  153. m_pkt : 1,
  154. service_dynamic : 1,
  155. ast_fail_for_dot11ax_su_ext : 1,
  156. ctrl_frame_soliciting_resp : 1;
  157. uint32_t service_cbw : 3,
  158. agc_cbw : 3,
  159. ack_id_ext : 10,
  160. ack_id : 16;
  161. uint32_t txop_duration_all_ones : 1,
  162. response_assoc_ack_count : 7,
  163. response_ack_count : 7,
  164. cts_cbw : 3,
  165. ht_vht_sig_cbw : 3,
  166. reserved : 4,
  167. response_sta_count : 7;
  168. uint32_t emlsr_main_tlv_if : 1,
  169. dot11ax_dl_ul_flag : 1,
  170. sw_response_tlv_from_crypto : 1,
  171. multi_tid : 1,
  172. response_ba256_count : 7,
  173. response_ba128_count : 7,
  174. response_ba64_count : 7,
  175. response_ba32_count : 7;
  176. uint32_t reserved_7a : 2,
  177. response_ba1024_count : 7,
  178. response_ba512_count : 7,
  179. sw_response_frame_length : 16;
  180. uint32_t addr1_31_0 : 32;
  181. uint32_t addr2_15_0 : 16,
  182. addr1_47_32 : 16;
  183. uint32_t addr2_47_16 : 32;
  184. uint32_t ftm_pe_chain_csd_en : 1,
  185. ftm_chain_csd_en : 1,
  186. ftm_pe_content : 1,
  187. ftm_pe_ltf_size : 2,
  188. ftm_pe_nss : 3,
  189. ftm_fields_valid : 1,
  190. dot11ax_received_ext_ru_size : 4,
  191. dot11ax_received_doppler_indication : 1,
  192. dot11ax_received_dcm : 1,
  193. dot11ax_received_coding : 1,
  194. dot11ax_received_ltf_size : 2,
  195. dot11ax_received_cp_size : 2,
  196. dot11ax_received_spatial_reuse : 4,
  197. dot11ax_received_bss_color_id : 6,
  198. dot11ax_received_dl_ul_flag : 1,
  199. dot11ax_received_format_indication : 1;
  200. uint32_t sw_peer_id : 16,
  201. dot11ax_ext_response_rate_source : 8,
  202. dot11ax_response_rate_source : 8;
  203. uint32_t u_sig_puncture_pattern_encoding : 6,
  204. reserved_13a : 5,
  205. force_extra_symbol : 1,
  206. eht_duplicate_mode : 2,
  207. punctured_response : 1,
  208. dot11be_response : 1,
  209. dot11be_puncture_bitmap : 16;
  210. uint32_t reserved_after_struct16 : 4,
  211. he_a_control_response_time : 12;
  212. struct mlo_sta_id_details mlo_sta_id_details_rx;
  213. #endif
  214. };
  215. #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x00000000
  216. #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0
  217. #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15
  218. #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x0000ffff
  219. #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x00000000
  220. #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16
  221. #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16
  222. #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x00010000
  223. #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x00000000
  224. #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17
  225. #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17
  226. #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x00020000
  227. #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x00000000
  228. #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20
  229. #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21
  230. #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x00300000
  231. #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x00000000
  232. #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22
  233. #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22
  234. #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x00400000
  235. #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x00000000
  236. #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23
  237. #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23
  238. #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x00800000
  239. #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x00000000
  240. #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24
  241. #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24
  242. #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x01000000
  243. #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x00000000
  244. #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25
  245. #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25
  246. #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x02000000
  247. #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x00000000
  248. #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28
  249. #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28
  250. #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x10000000
  251. #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x00000000
  252. #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29
  253. #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29
  254. #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x20000000
  255. #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x00000000
  256. #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30
  257. #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31
  258. #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0xc0000000
  259. #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x00000004
  260. #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 0
  261. #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 15
  262. #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff
  263. #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x00000004
  264. #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 16
  265. #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 31
  266. #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff0000
  267. #define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x00000008
  268. #define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0
  269. #define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15
  270. #define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x0000ffff
  271. #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x00000008
  272. #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16
  273. #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19
  274. #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x000f0000
  275. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000008
  276. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20
  277. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20
  278. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x00100000
  279. #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x00000008
  280. #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21
  281. #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24
  282. #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x01e00000
  283. #define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x00000008
  284. #define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25
  285. #define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26
  286. #define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x06000000
  287. #define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x00000008
  288. #define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27
  289. #define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27
  290. #define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x08000000
  291. #define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x00000008
  292. #define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28
  293. #define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28
  294. #define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x10000000
  295. #define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x00000008
  296. #define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29
  297. #define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29
  298. #define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x20000000
  299. #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x00000008
  300. #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30
  301. #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30
  302. #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x40000000
  303. #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x00000008
  304. #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31
  305. #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31
  306. #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x80000000
  307. #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000c
  308. #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 0
  309. #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 0
  310. #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x00000001
  311. #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000c
  312. #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 1
  313. #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 1
  314. #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x00000002
  315. #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000c
  316. #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 2
  317. #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 2
  318. #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x00000004
  319. #define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000c
  320. #define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 3
  321. #define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 3
  322. #define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x00000008
  323. #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000c
  324. #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 4
  325. #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 15
  326. #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff0
  327. #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000c
  328. #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 16
  329. #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 21
  330. #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f0000
  331. #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000c
  332. #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 22
  333. #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 22
  334. #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x00400000
  335. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000c
  336. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 23
  337. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 24
  338. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x01800000
  339. #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000c
  340. #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 25
  341. #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 25
  342. #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x02000000
  343. #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000c
  344. #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 26
  345. #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 28
  346. #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c000000
  347. #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000c
  348. #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 29
  349. #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 29
  350. #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x20000000
  351. #define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000c
  352. #define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 30
  353. #define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 30
  354. #define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x40000000
  355. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000c
  356. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 31
  357. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 31
  358. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0x80000000
  359. #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x00000010
  360. #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0
  361. #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15
  362. #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x0000ffff
  363. #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x00000010
  364. #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16
  365. #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25
  366. #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x03ff0000
  367. #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x00000010
  368. #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26
  369. #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28
  370. #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x1c000000
  371. #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x00000010
  372. #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29
  373. #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31
  374. #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0xe0000000
  375. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x00000014
  376. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 0
  377. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 6
  378. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f
  379. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x00000014
  380. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 7
  381. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 10
  382. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x00000780
  383. #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x00000014
  384. #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 11
  385. #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 13
  386. #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x00003800
  387. #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x00000014
  388. #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 14
  389. #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 16
  390. #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c000
  391. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x00000014
  392. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 17
  393. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 23
  394. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe0000
  395. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x00000014
  396. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 24
  397. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 30
  398. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f000000
  399. #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x00000014
  400. #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 31
  401. #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 31
  402. #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x80000000
  403. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x00000018
  404. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0
  405. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6
  406. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x0000007f
  407. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x00000018
  408. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7
  409. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13
  410. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x00003f80
  411. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x00000018
  412. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14
  413. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20
  414. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x001fc000
  415. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x00000018
  416. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21
  417. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27
  418. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x0fe00000
  419. #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x00000018
  420. #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28
  421. #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28
  422. #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x10000000
  423. #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x00000018
  424. #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29
  425. #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29
  426. #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x20000000
  427. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000018
  428. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30
  429. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30
  430. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x40000000
  431. #define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x00000018
  432. #define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31
  433. #define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31
  434. #define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x80000000
  435. #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000001c
  436. #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0
  437. #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15
  438. #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff
  439. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000001c
  440. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 16
  441. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 22
  442. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f0000
  443. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000001c
  444. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 23
  445. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 29
  446. #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f800000
  447. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000001c
  448. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 30
  449. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 31
  450. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc0000000
  451. #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x00000020
  452. #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0
  453. #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31
  454. #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0xffffffff
  455. #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x00000024
  456. #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 0
  457. #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 15
  458. #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff
  459. #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x00000024
  460. #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 16
  461. #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 31
  462. #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff0000
  463. #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x00000028
  464. #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0
  465. #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31
  466. #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0xffffffff
  467. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000002c
  468. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 0
  469. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 0
  470. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x00000001
  471. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000002c
  472. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 1
  473. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 1
  474. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x00000002
  475. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000002c
  476. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 2
  477. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 7
  478. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc
  479. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000002c
  480. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 8
  481. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 11
  482. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f00
  483. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000002c
  484. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 12
  485. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 13
  486. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x00003000
  487. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000002c
  488. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 14
  489. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 15
  490. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c000
  491. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000002c
  492. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 16
  493. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 16
  494. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x00010000
  495. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000002c
  496. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 17
  497. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 17
  498. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x00020000
  499. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000002c
  500. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 18
  501. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 18
  502. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x00040000
  503. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000002c
  504. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 19
  505. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 22
  506. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00780000
  507. #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000002c
  508. #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 23
  509. #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 23
  510. #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x00800000
  511. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000002c
  512. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 24
  513. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 26
  514. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x07000000
  515. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000002c
  516. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 27
  517. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 28
  518. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x18000000
  519. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000002c
  520. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 29
  521. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 29
  522. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x20000000
  523. #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000002c
  524. #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 30
  525. #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 30
  526. #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x40000000
  527. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000002c
  528. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 31
  529. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 31
  530. #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x80000000
  531. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x00000030
  532. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0
  533. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7
  534. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x000000ff
  535. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x00000030
  536. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8
  537. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15
  538. #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x0000ff00
  539. #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x00000030
  540. #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16
  541. #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31
  542. #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0xffff0000
  543. #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000034
  544. #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 0
  545. #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 15
  546. #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff
  547. #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x00000034
  548. #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 16
  549. #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 16
  550. #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x00010000
  551. #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x00000034
  552. #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 17
  553. #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 17
  554. #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x00020000
  555. #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000034
  556. #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 18
  557. #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 19
  558. #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c0000
  559. #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000034
  560. #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 20
  561. #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 20
  562. #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x00100000
  563. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x00000034
  564. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 21
  565. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 25
  566. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e00000
  567. #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000034
  568. #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
  569. #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
  570. #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
  571. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000038
  572. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
  573. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
  574. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
  575. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000038
  576. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
  577. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
  578. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
  579. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000038
  580. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
  581. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
  582. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
  583. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000038
  584. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
  585. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
  586. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
  587. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000038
  588. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
  589. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
  590. #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
  591. #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x00000038
  592. #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16
  593. #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27
  594. #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x0fff0000
  595. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x00000038
  596. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28
  597. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31
  598. #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0xf0000000
  599. #endif