tx_cbf_info.h 34 KB

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  1. /*
  2. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _TX_CBF_INFO_H_
  17. #define _TX_CBF_INFO_H_
  18. #if !defined(__ASSEMBLER__)
  19. #endif
  20. #define NUM_OF_DWORDS_TX_CBF_INFO 16
  21. #define NUM_OF_QWORDS_TX_CBF_INFO 8
  22. struct tx_cbf_info {
  23. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  24. uint32_t sw_peer_id : 16,
  25. pre_cbf_duration : 16;
  26. uint32_t brpoll_info_valid : 1,
  27. trigger_brpoll_info_valid : 1,
  28. npda_info_11ac_valid : 1,
  29. npda_info_11ax_valid : 1,
  30. dot11ax_su_extended : 1,
  31. bandwidth : 3,
  32. brpoll_info : 8,
  33. cbf_response_table_base_index : 8,
  34. peer_index : 3,
  35. pkt_type : 4,
  36. txop_duration_all_ones : 1;
  37. uint32_t trigger_brpoll_common_info_15_0 : 16,
  38. trigger_brpoll_common_info_31_16 : 16;
  39. uint32_t trigger_brpoll_user_info_15_0 : 16,
  40. trigger_brpoll_user_info_31_16 : 16;
  41. uint32_t addr1_31_0 : 32;
  42. uint32_t addr1_47_32 : 16,
  43. addr2_15_0 : 16;
  44. uint32_t addr2_47_16 : 32;
  45. uint32_t addr3_31_0 : 32;
  46. uint32_t addr3_47_32 : 16,
  47. sta_partial_aid : 11,
  48. reserved_8a : 4,
  49. cbf_resp_pwr_mgmt : 1;
  50. uint32_t group_id : 6,
  51. rssi_comb : 8,
  52. reserved_9a : 2,
  53. vht_ndpa_sta_info : 16;
  54. uint32_t he_eht_sta_info_15_0 : 16,
  55. he_eht_sta_info_31_16 : 16;
  56. uint32_t dot11ax_received_format_indication : 1,
  57. dot11ax_received_dl_ul_flag : 1,
  58. dot11ax_received_bss_color_id : 6,
  59. dot11ax_received_spatial_reuse : 4,
  60. dot11ax_received_cp_size : 2,
  61. dot11ax_received_ltf_size : 2,
  62. dot11ax_received_coding : 1,
  63. dot11ax_received_dcm : 1,
  64. dot11ax_received_doppler_indication : 1,
  65. dot11ax_received_ext_ru_size : 4,
  66. dot11ax_dl_ul_flag : 1,
  67. reserved_11a : 8;
  68. uint32_t sw_response_frame_length : 16,
  69. sw_response_tlv_from_crypto : 1,
  70. wait_sifs_config_valid : 1,
  71. wait_sifs : 2,
  72. __reserved_g_0005 : 1,
  73. secure : 1,
  74. tb___reserved_g_0005_response_required : 2,
  75. reserved_12a : 2,
  76. u_sig_puncture_pattern_encoding : 6;
  77. uint32_t dot11be_puncture_bitmap : 16,
  78. dot11be_response : 1,
  79. punctured_response : 1,
  80. npda_info_11be_valid : 1,
  81. eht_duplicate_mode : 2,
  82. reserved_13a : 11;
  83. uint32_t eht_sta_info_39_32 : 8,
  84. reserved_14a : 24;
  85. uint32_t tlv64_padding : 32;
  86. #else
  87. uint32_t pre_cbf_duration : 16,
  88. sw_peer_id : 16;
  89. uint32_t txop_duration_all_ones : 1,
  90. pkt_type : 4,
  91. peer_index : 3,
  92. cbf_response_table_base_index : 8,
  93. brpoll_info : 8,
  94. bandwidth : 3,
  95. dot11ax_su_extended : 1,
  96. npda_info_11ax_valid : 1,
  97. npda_info_11ac_valid : 1,
  98. trigger_brpoll_info_valid : 1,
  99. brpoll_info_valid : 1;
  100. uint32_t trigger_brpoll_common_info_31_16 : 16,
  101. trigger_brpoll_common_info_15_0 : 16;
  102. uint32_t trigger_brpoll_user_info_31_16 : 16,
  103. trigger_brpoll_user_info_15_0 : 16;
  104. uint32_t addr1_31_0 : 32;
  105. uint32_t addr2_15_0 : 16,
  106. addr1_47_32 : 16;
  107. uint32_t addr2_47_16 : 32;
  108. uint32_t addr3_31_0 : 32;
  109. uint32_t cbf_resp_pwr_mgmt : 1,
  110. reserved_8a : 4,
  111. sta_partial_aid : 11,
  112. addr3_47_32 : 16;
  113. uint32_t vht_ndpa_sta_info : 16,
  114. reserved_9a : 2,
  115. rssi_comb : 8,
  116. group_id : 6;
  117. uint32_t he_eht_sta_info_31_16 : 16,
  118. he_eht_sta_info_15_0 : 16;
  119. uint32_t reserved_11a : 8,
  120. dot11ax_dl_ul_flag : 1,
  121. dot11ax_received_ext_ru_size : 4,
  122. dot11ax_received_doppler_indication : 1,
  123. dot11ax_received_dcm : 1,
  124. dot11ax_received_coding : 1,
  125. dot11ax_received_ltf_size : 2,
  126. dot11ax_received_cp_size : 2,
  127. dot11ax_received_spatial_reuse : 4,
  128. dot11ax_received_bss_color_id : 6,
  129. dot11ax_received_dl_ul_flag : 1,
  130. dot11ax_received_format_indication : 1;
  131. uint32_t u_sig_puncture_pattern_encoding : 6,
  132. reserved_12a : 2,
  133. tb___reserved_g_0005_response_required : 2,
  134. secure : 1,
  135. __reserved_g_0005 : 1,
  136. wait_sifs : 2,
  137. wait_sifs_config_valid : 1,
  138. sw_response_tlv_from_crypto : 1,
  139. sw_response_frame_length : 16;
  140. uint32_t reserved_13a : 11,
  141. eht_duplicate_mode : 2,
  142. npda_info_11be_valid : 1,
  143. punctured_response : 1,
  144. dot11be_response : 1,
  145. dot11be_puncture_bitmap : 16;
  146. uint32_t reserved_14a : 24,
  147. eht_sta_info_39_32 : 8;
  148. uint32_t tlv64_padding : 32;
  149. #endif
  150. };
  151. #define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000
  152. #define TX_CBF_INFO_SW_PEER_ID_LSB 0
  153. #define TX_CBF_INFO_SW_PEER_ID_MSB 15
  154. #define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff
  155. #define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000
  156. #define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16
  157. #define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31
  158. #define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000
  159. #define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000
  160. #define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32
  161. #define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32
  162. #define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000
  163. #define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000
  164. #define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33
  165. #define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33
  166. #define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000
  167. #define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000
  168. #define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34
  169. #define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34
  170. #define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000
  171. #define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000
  172. #define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35
  173. #define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35
  174. #define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000
  175. #define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
  176. #define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36
  177. #define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36
  178. #define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000
  179. #define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000
  180. #define TX_CBF_INFO_BANDWIDTH_LSB 37
  181. #define TX_CBF_INFO_BANDWIDTH_MSB 39
  182. #define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000
  183. #define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000
  184. #define TX_CBF_INFO_BRPOLL_INFO_LSB 40
  185. #define TX_CBF_INFO_BRPOLL_INFO_MSB 47
  186. #define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000
  187. #define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000
  188. #define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48
  189. #define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55
  190. #define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000
  191. #define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000
  192. #define TX_CBF_INFO_PEER_INDEX_LSB 56
  193. #define TX_CBF_INFO_PEER_INDEX_MSB 58
  194. #define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000
  195. #define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000
  196. #define TX_CBF_INFO_PKT_TYPE_LSB 59
  197. #define TX_CBF_INFO_PKT_TYPE_MSB 62
  198. #define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000
  199. #define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000
  200. #define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63
  201. #define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63
  202. #define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000
  203. #define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008
  204. #define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0
  205. #define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15
  206. #define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff
  207. #define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008
  208. #define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16
  209. #define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31
  210. #define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000
  211. #define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008
  212. #define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32
  213. #define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47
  214. #define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000
  215. #define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008
  216. #define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48
  217. #define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63
  218. #define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000
  219. #define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010
  220. #define TX_CBF_INFO_ADDR1_31_0_LSB 0
  221. #define TX_CBF_INFO_ADDR1_31_0_MSB 31
  222. #define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff
  223. #define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010
  224. #define TX_CBF_INFO_ADDR1_47_32_LSB 32
  225. #define TX_CBF_INFO_ADDR1_47_32_MSB 47
  226. #define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000
  227. #define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010
  228. #define TX_CBF_INFO_ADDR2_15_0_LSB 48
  229. #define TX_CBF_INFO_ADDR2_15_0_MSB 63
  230. #define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000
  231. #define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018
  232. #define TX_CBF_INFO_ADDR2_47_16_LSB 0
  233. #define TX_CBF_INFO_ADDR2_47_16_MSB 31
  234. #define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff
  235. #define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018
  236. #define TX_CBF_INFO_ADDR3_31_0_LSB 32
  237. #define TX_CBF_INFO_ADDR3_31_0_MSB 63
  238. #define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000
  239. #define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020
  240. #define TX_CBF_INFO_ADDR3_47_32_LSB 0
  241. #define TX_CBF_INFO_ADDR3_47_32_MSB 15
  242. #define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff
  243. #define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020
  244. #define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16
  245. #define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26
  246. #define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000
  247. #define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020
  248. #define TX_CBF_INFO_RESERVED_8A_LSB 27
  249. #define TX_CBF_INFO_RESERVED_8A_MSB 30
  250. #define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000078000000
  251. #define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020
  252. #define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31
  253. #define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31
  254. #define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000
  255. #define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020
  256. #define TX_CBF_INFO_GROUP_ID_LSB 32
  257. #define TX_CBF_INFO_GROUP_ID_MSB 37
  258. #define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000
  259. #define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020
  260. #define TX_CBF_INFO_RSSI_COMB_LSB 38
  261. #define TX_CBF_INFO_RSSI_COMB_MSB 45
  262. #define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000
  263. #define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020
  264. #define TX_CBF_INFO_RESERVED_9A_LSB 46
  265. #define TX_CBF_INFO_RESERVED_9A_MSB 47
  266. #define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000
  267. #define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020
  268. #define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48
  269. #define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63
  270. #define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000
  271. #define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028
  272. #define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0
  273. #define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15
  274. #define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff
  275. #define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028
  276. #define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16
  277. #define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31
  278. #define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000
  279. #define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028
  280. #define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32
  281. #define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32
  282. #define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000
  283. #define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028
  284. #define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33
  285. #define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33
  286. #define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000
  287. #define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028
  288. #define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34
  289. #define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39
  290. #define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000
  291. #define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028
  292. #define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40
  293. #define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43
  294. #define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000
  295. #define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028
  296. #define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44
  297. #define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45
  298. #define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000
  299. #define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028
  300. #define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46
  301. #define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47
  302. #define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000
  303. #define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028
  304. #define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48
  305. #define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48
  306. #define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000
  307. #define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028
  308. #define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49
  309. #define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49
  310. #define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000
  311. #define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028
  312. #define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50
  313. #define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50
  314. #define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000
  315. #define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028
  316. #define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51
  317. #define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54
  318. #define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000
  319. #define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028
  320. #define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55
  321. #define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55
  322. #define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000
  323. #define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028
  324. #define TX_CBF_INFO_RESERVED_11A_LSB 56
  325. #define TX_CBF_INFO_RESERVED_11A_MSB 63
  326. #define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000
  327. #define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030
  328. #define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0
  329. #define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15
  330. #define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff
  331. #define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030
  332. #define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16
  333. #define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16
  334. #define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000
  335. #define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030
  336. #define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17
  337. #define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17
  338. #define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000
  339. #define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030
  340. #define TX_CBF_INFO_WAIT_SIFS_LSB 18
  341. #define TX_CBF_INFO_WAIT_SIFS_MSB 19
  342. #define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000
  343. #define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030
  344. #define TX_CBF_INFO_SECURE_LSB 21
  345. #define TX_CBF_INFO_SECURE_MSB 21
  346. #define TX_CBF_INFO_SECURE_MASK 0x0000000000200000
  347. #define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000030
  348. #define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22
  349. #define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23
  350. #define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000c00000
  351. #define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030
  352. #define TX_CBF_INFO_RESERVED_12A_LSB 24
  353. #define TX_CBF_INFO_RESERVED_12A_MSB 25
  354. #define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000003000000
  355. #define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030
  356. #define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
  357. #define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
  358. #define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
  359. #define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030
  360. #define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32
  361. #define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47
  362. #define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000
  363. #define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030
  364. #define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48
  365. #define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48
  366. #define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000
  367. #define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030
  368. #define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49
  369. #define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49
  370. #define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000
  371. #define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030
  372. #define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50
  373. #define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50
  374. #define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000
  375. #define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030
  376. #define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51
  377. #define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52
  378. #define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000
  379. #define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030
  380. #define TX_CBF_INFO_RESERVED_13A_LSB 53
  381. #define TX_CBF_INFO_RESERVED_13A_MSB 63
  382. #define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000
  383. #define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038
  384. #define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0
  385. #define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7
  386. #define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff
  387. #define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038
  388. #define TX_CBF_INFO_RESERVED_14A_LSB 8
  389. #define TX_CBF_INFO_RESERVED_14A_MSB 31
  390. #define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000ffffff00
  391. #define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038
  392. #define TX_CBF_INFO_TLV64_PADDING_LSB 32
  393. #define TX_CBF_INFO_TLV64_PADDING_MSB 63
  394. #define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000
  395. #endif