response_start_status.h 4.5 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879
  1. /*
  2. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _RESPONSE_START_STATUS_H_
  17. #define _RESPONSE_START_STATUS_H_
  18. #if !defined(__ASSEMBLER__)
  19. #endif
  20. #define NUM_OF_DWORDS_RESPONSE_START_STATUS 2
  21. #define NUM_OF_QWORDS_RESPONSE_START_STATUS 1
  22. struct response_start_status {
  23. #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
  24. uint32_t generated_response : 3,
  25. __reserved_g_0012 : 2,
  26. trig_response_related : 1,
  27. response_sta_count : 7,
  28. reserved : 19;
  29. uint32_t phy_ppdu_id : 16,
  30. sw_peer_id : 16;
  31. #else
  32. uint32_t reserved : 19,
  33. response_sta_count : 7,
  34. trig_response_related : 1,
  35. __reserved_g_0012 : 2,
  36. generated_response : 3;
  37. uint32_t sw_peer_id : 16,
  38. phy_ppdu_id : 16;
  39. #endif
  40. };
  41. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000
  42. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0
  43. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2
  44. #define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007
  45. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000
  46. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5
  47. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5
  48. #define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020
  49. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000
  50. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6
  51. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12
  52. #define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0
  53. #define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000
  54. #define RESPONSE_START_STATUS_RESERVED_LSB 13
  55. #define RESPONSE_START_STATUS_RESERVED_MSB 31
  56. #define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000
  57. #define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000
  58. #define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32
  59. #define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47
  60. #define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000
  61. #define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000
  62. #define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48
  63. #define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63
  64. #define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000
  65. #endif