htt.h 1.1 MB

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  1. /*
  2. * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  6. *
  7. *
  8. * Permission to use, copy, modify, and/or distribute this software for
  9. * any purpose with or without fee is hereby granted, provided that the
  10. * above copyright notice and this permission notice appear in all
  11. * copies.
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  14. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  15. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  16. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  17. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  18. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  20. * PERFORMANCE OF THIS SOFTWARE.
  21. */
  22. /*
  23. * This file was originally distributed by Qualcomm Atheros, Inc.
  24. * under proprietary terms before Copyright ownership was assigned
  25. * to the Linux Foundation.
  26. */
  27. /**
  28. * @file htt.h
  29. *
  30. * @details the public header file of HTT layer
  31. */
  32. #ifndef _HTT_H_
  33. #define _HTT_H_
  34. #include <htt_deps.h>
  35. #include <htt_common.h>
  36. /*
  37. * Unless explicitly specified to use 64 bits to represent physical addresses
  38. * (or more precisely, bus addresses), default to 32 bits.
  39. */
  40. #ifndef HTT_PADDR64
  41. #define HTT_PADDR64 0
  42. #endif
  43. #ifndef offsetof
  44. #define offsetof(type, field) ((unsigned int)(&((type *)0)->field))
  45. #endif
  46. /*
  47. * HTT version history:
  48. * 1.0 initial numbered version
  49. * 1.1 modifications to STATS messages.
  50. * These modifications are not backwards compatible, but since the
  51. * STATS messages themselves are non-essential (they are for debugging),
  52. * the 1.1 version of the HTT message library as a whole is compatible
  53. * with the 1.0 version.
  54. * 1.2 reset mask IE added to STATS_REQ message
  55. * 1.3 stat config IE added to STATS_REQ message
  56. *----
  57. * 2.0 FW rx PPDU desc added to RX_IND message
  58. * 2.1 Enable msdu_ext/frag_desc banking change for WIFI2.0
  59. *----
  60. * 3.0 Remove HTT_H2T_MSG_TYPE_MGMT_TX message
  61. * 3.1 Added HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND message
  62. * 3.2 Added HTT_H2T_MSG_TYPE_WDI_IPA_CFG,
  63. * HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST messages
  64. * 3.3 Added HTT_H2T_MSG_TYPE_AGGR_CFG_EX message
  65. * 3.4 Added tx_compl_req flag in HTT tx descriptor
  66. * 3.5 Added flush and fail stats in rx_reorder stats structure
  67. * 3.6 Added frag flag in HTT RX INORDER PADDR IND header
  68. * 3.7 Made changes to support EOS Mac_core 3.0
  69. * 3.8 Added txq_group information element definition;
  70. * added optional txq_group suffix to TX_CREDIT_UPDATE_IND message
  71. * 3.9 Added HTT_T2H CHAN_CHANGE message;
  72. * Allow buffer addresses in bus-address format to be stored as
  73. * either 32 bits or 64 bits.
  74. * 3.10 Add optional TLV extensions to the VERSION_REQ and VERSION_CONF
  75. * messages to specify which HTT options to use.
  76. * Initial TLV options cover:
  77. * - whether to use 32 or 64 bits to represent LL bus addresses
  78. * - whether to use TX_COMPL_IND or TX_CREDIT_UPDATE_IND in HL systems
  79. * - how many tx queue groups to use
  80. * 3.11 Expand rx debug stats:
  81. * - Expand the rx_reorder_stats struct with stats about successful and
  82. * failed rx buffer allcoations.
  83. * - Add a new rx_remote_buffer_mgmt_stats struct with stats about
  84. * the supply, allocation, use, and recycling of rx buffers for the
  85. * "remote ring" of rx buffers in host member in LL systems.
  86. * Add RX_REMOTE_RING_BUFFER_INFO stats type for uploading these stats.
  87. * 3.12 Add "rx offload packet error" message with initial "MIC error" subtype
  88. * 3.13 Add constants + macros to support 64-bit address format for the
  89. * tx fragments descriptor, the rx ring buffer, and the rx ring
  90. * index shadow register.
  91. * 3.14 Add a method for the host to provide detailed per-frame tx specs:
  92. * - Add htt_tx_msdu_desc_ext_t struct def.
  93. * - Add TLV to specify whether the target supports the HTT tx MSDU
  94. * extension descriptor.
  95. * - Change a reserved bit in the HTT tx MSDU descriptor to an
  96. * "extension" bit, to specify whether a HTT tx MSDU extension
  97. * descriptor is present.
  98. * 3.15 Add HW rx desc info to per-MSDU info elems in RX_IN_ORD_PADDR_IND msg.
  99. * (This allows the host to obtain key information about the MSDU
  100. * from a memory location already in the cache, rather than taking a
  101. * cache miss for each MSDU by reading the HW rx descs.)
  102. * 3.16 Add htt_pkt_type_eth2 and define pkt_subtype flags to indicate
  103. * whether a copy-engine classification result is appended to TX_FRM.
  104. * 3.17 Add a version of the WDI_IPA_CFG message; add RX_RING2 to WDI_IPA_CFG
  105. * 3.18 Add a PEER_DEL tx completion indication status, for HL cleanup of
  106. * tx frames in the target after the peer has already been deleted.
  107. * 3.19 Add HTT_DBG_STATS_RX_RATE_INFO_V2 and HTT_DBG_STATS_TX_RATE_INFO_V2
  108. * 3.20 Expand rx_reorder_stats.
  109. * 3.21 Add optional rx channel spec to HL RX_IND.
  110. * 3.22 Expand rx_reorder_stats
  111. * (distinguish duplicates within vs. outside block ack window)
  112. * 3.23 Add HTT_T2H_MSG_TYPE_RATE_REPORT to report peer justified rate.
  113. * The justified rate is calculated by two steps. The first is to multiply
  114. * user-rate by (1 - PER) and the other is to smooth the step 1's result
  115. * by a low pass filter.
  116. * This change allows HL download scheduling to consider the WLAN rate
  117. * that will be used for transmitting the downloaded frames.
  118. * 3.24 Expand rx_reorder_stats
  119. * (add counter for decrypt / MIC errors)
  120. * 3.25 Expand rx_reorder_stats
  121. * (add counter of frames received into both local + remote rings)
  122. * 3.26 Add stats struct for counting rx of tx BF, MU, SU, and NDPA frames
  123. * (HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT, rx_txbf_musu_ndpa_pkts_stats)
  124. * 3.27 Add a new interface for flow-control. The following t2h messages have
  125. * been included: HTT_T2H_MSG_TYPE_FLOW_POOL_MAP and
  126. * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP
  127. * 3.28 Add a new interface for ring interface change. The following two h2t
  128. * and one t2h messages have been included:
  129. * HTT_H2T_MSG_TYPE_SRING_SETUP, HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG,
  130. * and HTT_T2H_MSG_TYPE_SRING_SETUP_DONE
  131. * 3.29 Add definitions of htt_tx_msdu_desc_ext2_t descriptor and other
  132. * information elements passed from the host to a Lithium target,
  133. * Add definitions of the HTT_H2T ADD_WDS_ENTRY and DELETE_WDS_ENTRY
  134. * messages and the HTT_T2H MAP_FLOW_INFO message (for use with Lithium
  135. * targets).
  136. * 3.30 Add pktlog flag inside HTT_T2H RX_IN_ORD_PADDR_IND message
  137. * 3.31 Add HTT_H2T_MSG_TYPE_RFS_CONFIG
  138. * 3.32 Add HTT_WDI_IPA_OPCODE_SHARING_STATS, HTT_WDI_IPA_OPCODE_SET_QUOTA and
  139. * HTT_WDI_IPA_OPCODE_IND_QUOTA for getting quota and reporting WiFi
  140. * sharing stats
  141. * 3.33 Add HTT_TX_COMPL_IND_STAT_DROP and HTT_TX_COMPL_IND_STAT_HOST_INSPECT
  142. * 3.34 Add HW_PEER_ID field to PEER_MAP
  143. * 3.35 Revise bitfield defs of HTT_SRING_SETUP message
  144. * (changes are not backwards compatible, but HTT_SRING_SETUP message is
  145. * not yet in use)
  146. * 3.36 Add HTT_H2T_MSG_TYPE_EXT_STATS_REQ and HTT_T2H_MSG_TYPE_EXT_STATS_CONF
  147. * 3.37 Add HTT_PEER_TYPE and htt_mac_addr defs
  148. * 3.38 Add holes_no_filled field to rx_reorder_stats
  149. * 3.39 Add host_inspected flag to htt_tx_tcl_vdev_metadata
  150. * 3.40 Add optional timestamps in the HTT tx completion
  151. * 3.41 Add optional tx power spec in the HTT tx completion (for DSRC use)
  152. * 3.42 Add PPDU_STATS_CFG + PPDU_STATS_IND
  153. * 3.43 Add HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR defs
  154. * 3.44 Add htt_tx_wbm_completion_v2
  155. * 3.45 Add host_tx_desc_pool flag in htt_tx_msdu_desc_ext2_t
  156. * 3.46 Add MAC ID and payload size fields to HTT_T2H_MSG_TYPE_PKTLOG header
  157. * 3.47 Add HTT_T2H PEER_MAP_V2 and PEER_UNMAP_V2
  158. * 3.48 Add pdev ID field to HTT_T2H_MSG_TYPE_PPDU_STATS_IND and
  159. * HTT_T2H_MSG_TYPE_PKTLOG
  160. * 3.49 Add HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND def
  161. * 3.50 Add learning_frame flag to htt_tx_msdu_desc_ext2_t
  162. * 3.51 Add SW peer ID and TID num to HTT TX WBM COMPLETION
  163. * 3.52 Add HTT_T2H FLOW_POOL_RESIZE msg def
  164. * 3.53 Update HTT_T2H FLOW_POOL_RESIZE msg def
  165. * 3.54 Define mcast and mcast_valid flags within htt_tx_wbm_transmit_status
  166. * 3.55 Add initiator / responder flags to RX_DELBA indication
  167. * 3.56 Fix HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE bit-mask defs
  168. * 3.57 Add support for in-band data within HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND
  169. * 3.58 Add optional MSDU ack RSSI array to end of HTT_T2H TX_COMPL_IND msg
  170. * 3.59 Add HTT_RXDMA_HOST_BUF_RING2 def
  171. * 3.60 Add HTT_T2H_MSG_TYPE_PEER_STATS_IND def
  172. * 3.61 Add rx offset fields to HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG msg
  173. * 3.62 Add antenna mask to reserved space in htt_rx_ppdu_desc_t
  174. * 3.63 Add HTT_HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND def
  175. * 3.64 Add struct htt_tx_compl_ind_append_tx_tsf64 and add tx_tsf64
  176. * array to the end of HTT_T2H TX_COMPL_IND msg
  177. * 3.65 Add fields in htt_tx_msdu_desc_ext2_t to allow the host to provide
  178. * a "cookie" to identify a MSDU, and to specify to not apply aggregation
  179. * for a MSDU.
  180. * 3.66 Add HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND msg.
  181. * Add PKT_CAPTURE_MODE flag within HTT_T2H TX_I_ORD_PADDR_IND msg.
  182. * 3.67 Add drop threshold field to HTT_H2T RX_RING_SELECTION_CFG msg.
  183. * 3.68 Add ipa_drop threshold fields to HTT_H2T_MSG_TYPE_SRING_SETUP
  184. * 3.69 Add htt_ul_ofdma_user_info_v0 defs
  185. * 3.70 Add AST1-AST3 fields to HTT_T2H PEER_MAP_V2 msg
  186. * 3.71 Add rx offload engine / flow search engine htt setup message defs for
  187. * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG, HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG
  188. * 3.72 Add tx_retry_cnt fields to htt_tx_offload_deliver_ind_hdr_t and
  189. * htt_tx_data_hdr_information
  190. * 3.73 Add channel pre-calibration data upload and download messages defs for
  191. * HTT_T2H_MSG_TYPE_CHAN_CALDATA and HTT_H2T_MSG_TYPE_CHAN_CALDATA
  192. * 3.74 Add HTT_T2H_MSG_TYPE_RX_FISA_CFG msg.
  193. * 3.75 Add fp_ndp and mo_ndp flags in HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG.
  194. * 3.76 Add HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG msg.
  195. * 3.77 Add HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE msg.
  196. * 3.78 Add htt_ppdu_id def.
  197. * 3.79 Add HTT_NUM_AC_WMM def.
  198. * 3.80 Add add WDS_FREE_COUNT bitfield in T2H PEER_UNMAP_V2 msg.
  199. * 3.81 Add ppdu_start_tsf field in HTT_TX_WBM_COMPLETION_V2.
  200. * 3.82 Add WIN_SIZE field to HTT_T2H_MSG_TYPE_RX_DELBA msg.
  201. * 3.83 Shrink seq_idx field in HTT PPDU ID from 3 bits to 2.
  202. * 3.84 Add fisa_control_bits_v2 def.
  203. * 3.85 Add HTT_RX_PEER_META_DATA defs.
  204. * 3.86 Add HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND def.
  205. * 3.87 Add on-chip AST index field to PEER_MAP_V2 msg.
  206. * 3.88 Add HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE def.
  207. * 3.89 Add MSDU queue enumerations.
  208. * 3.90 Add HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND def.
  209. * 3.91 Add HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP, _UNMAP defs.
  210. * 3.92 Add HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG def.
  211. * 3.93 Add HTT_T2H_MSG_TYPE_PEER_MAP_V3 def.
  212. * 3.94 Add HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG,
  213. * HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND defs.
  214. * 3.95 Add HTT_H2T_MSG_TYPE_TX_MONITOR_CFG def.
  215. * 3.96 Modify HTT_H2T_MSG_TYPE_TX_MONITOR_CFG def.
  216. * 3.97 Add tx MSDU drop byte count fields in vdev_txrx_stats_hw_stats TLV.
  217. * 3.98 Add htt_tx_tcl_metadata_v2 def.
  218. * 3.99 Add HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ, _UNMAP_REQ, _MAP_REPORT_REQ and
  219. * HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF defs.
  220. * 3.100 Add htt_tx_wbm_completion_v3 def.
  221. * 3.101 Add HTT_UL_OFDMA_USER_INFO_V1_BITMAP defs.
  222. * 3.102 Add HTT_H2T_MSG_TYPE_MSI_SETUP def.
  223. * 3.103 Add HTT_T2H_SAWF_MSDUQ_INFO_IND defs.
  224. * 3.104 Add mgmt/ctrl/data specs in rx ring cfg.
  225. * 3.105 Add HTT_H2T STREAMING_STATS_REQ + HTT_T2H STREAMING_STATS_IND defs.
  226. * 3.106 Add HTT_T2H_PPDU_ID_FMT_IND def.
  227. * 3.107 Add traffic_end_indication bitfield in htt_tx_msdu_desc_ext2_t.
  228. * 3.108 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP def.
  229. * 3.109 Add HTT_T2H RX_ADDBA_EXTN,RX_DELBA_EXTN defs.
  230. * 3.110 Add more word_mask fields in htt_tx_monitor_cfg_t.
  231. * 3.111 Add RXPCU filter enable flag in RX_RING_SELECTION_CFG msg.
  232. * 3.112 Add logical_link_id field in rx_peer_metadata_v1.
  233. * 3.113 Add add rx msdu,mpdu,ppdu fields in rx_ring_selection_cfg_t
  234. * 3.114 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET def.
  235. * 3.115 Add HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP and
  236. * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs.
  237. * 3.116 Add HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag.
  238. * 3.117 Add HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND def.
  239. * 3.118 Add HTT_T2H_MSG_TYPE_RX_DATA_IND and _SOFT_UMAC_TX_COMPL_IND defs.
  240. * 3.119 Add RX_PEER_META_DATA V1A and V1B defs.
  241. * 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs.
  242. * 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def.
  243. * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg
  244. * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def.
  245. * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def.
  246. * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2.
  247. * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def.
  248. * 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs.
  249. * 3.128 Add H2T TX_LATENCY_STATS_CFG + T2H TX_LATENCY_STATS_PERIODIC_IND
  250. * msg defs.
  251. * 3.129 Add HTT_TX_FW2WBM_REINJECT_REASON_SAWF_SVC_CLASS_ID_ABSENT def.
  252. * 3.130 Add H2T TX_LCE_SUPER_RULE_SETUP and T2H TX_LCE_SUPER_RULE_SETUP_DONE
  253. * msg defs.
  254. * 3.131 Add H2T TYPE_MSDUQ_RECFG_REQ + T2H MSDUQ_CFG_IND msg defs.
  255. * 3.132 Add flow_classification_3_tuple_field_enable in H2T 3_TUPLE_HASH_CFG.
  256. * 3.133 Add packet_type_enable_data_flags fields in rx_ring_selection_cfg.
  257. * 3.134 Add qdata_refill flag in rx_peer_metadata_v1a.
  258. * 3.135 Add HTT_HOST4_TO_FW_RXBUF_RING def.
  259. * 3.136 Add htt_ext_present flag in htt_tx_tcl_global_seq_metadata.
  260. */
  261. #define HTT_CURRENT_VERSION_MAJOR 3
  262. #define HTT_CURRENT_VERSION_MINOR 136
  263. #define HTT_NUM_TX_FRAG_DESC 1024
  264. #define HTT_WIFI_IP_VERSION(x,y) ((x) == (y))
  265. #define HTT_CHECK_SET_VAL(field, val) \
  266. A_ASSERT(!((val) & ~((field ## _M) >> (field ## _S))))
  267. /* macros to assist in sign-extending fields from HTT messages */
  268. #define HTT_SIGN_BIT_MASK(field) \
  269. ((field ## _M + (1 << field ## _S)) >> 1)
  270. #define HTT_SIGN_BIT(_val, field) \
  271. (_val & HTT_SIGN_BIT_MASK(field))
  272. #define HTT_SIGN_BIT_UNSHIFTED(_val, field) \
  273. (HTT_SIGN_BIT(_val, field) >> field ## _S)
  274. #define HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field) \
  275. (HTT_SIGN_BIT_UNSHIFTED(_val, field) - 1)
  276. #define HTT_SIGN_BIT_EXTENSION(_val, field) \
  277. (~(HTT_SIGN_BIT_UNSHIFTED(_val, field) | \
  278. HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field)))
  279. #define HTT_SIGN_BIT_EXTENSION_MASK(_val, field) \
  280. (HTT_SIGN_BIT_EXTENSION(_val, field) & ~(field ## _M >> field ## _S))
  281. /*
  282. * TEMPORARY:
  283. * Provide HTT_H2T_MSG_TYPE_MGMT_TX as an alias for
  284. * DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX until all code
  285. * that refers to HTT_H2T_MSG_TYPE_MGMT_TX has been
  286. * updated.
  287. */
  288. #define HTT_H2T_MSG_TYPE_MGMT_TX DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX
  289. /*
  290. * TEMPORARY:
  291. * Provide HTT_T2H_MSG_TYPE_RC_UPDATE_IND as an alias for
  292. * DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND until all code
  293. * that refers to HTT_T2H_MSG_TYPE_RC_UPDATE_IND has been
  294. * updated.
  295. */
  296. #define HTT_T2H_MSG_TYPE_RC_UPDATE_IND DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND
  297. /**
  298. * htt_dbg_stats_type -
  299. * bit positions for each stats type within a stats type bitmask
  300. * The bitmask contains 24 bits.
  301. */
  302. enum htt_dbg_stats_type {
  303. HTT_DBG_STATS_WAL_PDEV_TXRX = 0, /* bit 0 -> 0x1 */
  304. HTT_DBG_STATS_RX_REORDER = 1, /* bit 1 -> 0x2 */
  305. HTT_DBG_STATS_RX_RATE_INFO = 2, /* bit 2 -> 0x4 */
  306. HTT_DBG_STATS_TX_PPDU_LOG = 3, /* bit 3 -> 0x8 */
  307. HTT_DBG_STATS_TX_RATE_INFO = 4, /* bit 4 -> 0x10 */
  308. HTT_DBG_STATS_TIDQ = 5, /* bit 5 -> 0x20 */
  309. HTT_DBG_STATS_TXBF_INFO = 6, /* bit 6 -> 0x40 */
  310. HTT_DBG_STATS_SND_INFO = 7, /* bit 7 -> 0x80 */
  311. HTT_DBG_STATS_ERROR_INFO = 8, /* bit 8 -> 0x100 */
  312. HTT_DBG_STATS_TX_SELFGEN_INFO = 9, /* bit 9 -> 0x200 */
  313. HTT_DBG_STATS_TX_MU_INFO = 10, /* bit 10 -> 0x400 */
  314. HTT_DBG_STATS_SIFS_RESP_INFO = 11, /* bit 11 -> 0x800 */
  315. HTT_DBG_STATS_RX_REMOTE_RING_BUFFER_INFO = 12, /* bit 12 -> 0x1000 */
  316. HTT_DBG_STATS_RX_RATE_INFO_V2 = 13, /* bit 13 -> 0x2000 */
  317. HTT_DBG_STATS_TX_RATE_INFO_V2 = 14, /* bit 14 -> 0x4000 */
  318. HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT = 15, /* bit 15 -> 0x8000 */
  319. /* bits 16-23 currently reserved */
  320. /* keep this last */
  321. HTT_DBG_NUM_STATS
  322. };
  323. /*=== HTT option selection TLVs ===
  324. * Certain HTT messages have alternatives or options.
  325. * For such cases, the host and target need to agree on which option to use.
  326. * Option specification TLVs can be appended to the VERSION_REQ and
  327. * VERSION_CONF messages to select options other than the default.
  328. * These TLVs are entirely optional - if they are not provided, there is a
  329. * well-defined default for each option. If they are provided, they can be
  330. * provided in any order. Each TLV can be present or absent independent of
  331. * the presence / absence of other TLVs.
  332. *
  333. * The HTT option selection TLVs use the following format:
  334. * |31 16|15 8|7 0|
  335. * |---------------------------------+----------------+----------------|
  336. * | value (payload) | length | tag |
  337. * |-------------------------------------------------------------------|
  338. * The value portion need not be only 2 bytes; it can be extended by any
  339. * integer number of 4-byte units. The total length of the TLV, including
  340. * the tag and length fields, must be a multiple of 4 bytes. The length
  341. * field specifies the total TLV size in 4-byte units. Thus, the typical
  342. * TLV, with a 1-byte tag field, a 1-byte length field, and a 2-byte value
  343. * field, would store 0x1 in its length field, to show that the TLV occupies
  344. * a single 4-byte unit.
  345. */
  346. /*--- TLV header format - applies to all HTT option TLVs ---*/
  347. enum HTT_OPTION_TLV_TAGS {
  348. HTT_OPTION_TLV_TAG_RESERVED0 = 0x0,
  349. HTT_OPTION_TLV_TAG_LL_BUS_ADDR_SIZE = 0x1,
  350. HTT_OPTION_TLV_TAG_HL_SUPPRESS_TX_COMPL_IND = 0x2,
  351. HTT_OPTION_TLV_TAG_MAX_TX_QUEUE_GROUPS = 0x3,
  352. HTT_OPTION_TLV_TAG_SUPPORT_TX_MSDU_DESC_EXT = 0x4,
  353. /* TCL_METADATA_VER: added to support V2 and higher of the TCL Data Cmd */
  354. HTT_OPTION_TLV_TAG_TCL_METADATA_VER = 0x5,
  355. };
  356. #define HTT_TCL_METADATA_VER_SZ 4
  357. PREPACK struct htt_option_tlv_header_t {
  358. A_UINT8 tag;
  359. A_UINT8 length;
  360. } POSTPACK;
  361. #define HTT_OPTION_TLV_TAG_M 0x000000ff
  362. #define HTT_OPTION_TLV_TAG_S 0
  363. #define HTT_OPTION_TLV_LENGTH_M 0x0000ff00
  364. #define HTT_OPTION_TLV_LENGTH_S 8
  365. /*
  366. * value0 - 16 bit value field stored in word0
  367. * The TLV's value field may be longer than 2 bytes, in which case
  368. * the remainder of the value is stored in word1, word2, etc.
  369. */
  370. #define HTT_OPTION_TLV_VALUE0_M 0xffff0000
  371. #define HTT_OPTION_TLV_VALUE0_S 16
  372. #define HTT_OPTION_TLV_TAG_SET(word, tag) \
  373. do { \
  374. HTT_CHECK_SET_VAL(HTT_OPTION_TLV_TAG, tag); \
  375. (word) |= ((tag) << HTT_OPTION_TLV_TAG_S); \
  376. } while (0)
  377. #define HTT_OPTION_TLV_TAG_GET(word) \
  378. (((word) & HTT_OPTION_TLV_TAG_M) >> HTT_OPTION_TLV_TAG_S)
  379. #define HTT_OPTION_TLV_LENGTH_SET(word, tag) \
  380. do { \
  381. HTT_CHECK_SET_VAL(HTT_OPTION_TLV_LENGTH, tag); \
  382. (word) |= ((tag) << HTT_OPTION_TLV_LENGTH_S); \
  383. } while (0)
  384. #define HTT_OPTION_TLV_LENGTH_GET(word) \
  385. (((word) & HTT_OPTION_TLV_LENGTH_M) >> HTT_OPTION_TLV_LENGTH_S)
  386. #define HTT_OPTION_TLV_VALUE0_SET(word, tag) \
  387. do { \
  388. HTT_CHECK_SET_VAL(HTT_OPTION_TLV_VALUE0, tag); \
  389. (word) |= ((tag) << HTT_OPTION_TLV_VALUE0_S); \
  390. } while (0)
  391. #define HTT_OPTION_TLV_VALUE0_GET(word) \
  392. (((word) & HTT_OPTION_TLV_VALUE0_M) >> HTT_OPTION_TLV_VALUE0_S)
  393. /*--- format of specific HTT option TLVs ---*/
  394. /*
  395. * HTT option TLV for specifying LL bus address size
  396. * Some chips require bus addresses used by the target to access buffers
  397. * within the host's memory to be 32 bits; others require bus addresses
  398. * used by the target to access buffers within the host's memory to be
  399. * 64 bits.
  400. * The LL_BUS_ADDR_SIZE TLV can be sent from the target to the host as
  401. * a suffix to the VERSION_CONF message to specify which bus address format
  402. * the target requires.
  403. * If this LL_BUS_ADDR_SIZE TLV is not sent by the target, the host should
  404. * default to providing bus addresses to the target in 32-bit format.
  405. */
  406. enum HTT_OPTION_TLV_LL_BUS_ADDR_SIZE_VALUES {
  407. HTT_OPTION_TLV_LL_BUS_ADDR_SIZE32 = 0x0,
  408. HTT_OPTION_TLV_LL_BUS_ADDR_SIZE64 = 0x1,
  409. };
  410. PREPACK struct htt_option_tlv_ll_bus_addr_size_t {
  411. struct htt_option_tlv_header_t hdr;
  412. A_UINT16 ll_bus_addr_size; /* LL_BUS_ADDR_SIZE_VALUES enum */
  413. } POSTPACK;
  414. /*
  415. * HTT option TLV for specifying whether HL systems should indicate
  416. * over-the-air tx completion for individual frames, or should instead
  417. * send a bulk TX_CREDIT_UPDATE_IND except when the host explicitly
  418. * requests an OTA tx completion for a particular tx frame.
  419. * This option does not apply to LL systems, where the TX_COMPL_IND
  420. * is mandatory.
  421. * This option is primarily intended for HL systems in which the tx frame
  422. * downloads over the host --> target bus are as slow as or slower than
  423. * the transmissions over the WLAN PHY. For cases where the bus is faster
  424. * than the WLAN PHY, the target will transmit relatively large A-MPDUs,
  425. * and consequently will send one TX_COMPL_IND message that covers several
  426. * tx frames. For cases where the WLAN PHY is faster than the bus,
  427. * the target will end up transmitting very short A-MPDUs, and consequently
  428. * sending many TX_COMPL_IND messages, which each cover a very small number
  429. * of tx frames.
  430. * The HL_SUPPRESS_TX_COMPL_IND TLV can be sent by the host to the target as
  431. * a suffix to the VERSION_REQ message to request whether the host desires to
  432. * use TX_CREDIT_UPDATE_IND rather than TX_COMPL_IND. The target can then
  433. * send a HTT_SUPPRESS_TX_COMPL_IND TLV to the host as a suffix to the
  434. * VERSION_CONF message to confirm whether TX_CREDIT_UPDATE_IND will be used
  435. * rather than TX_COMPL_IND. TX_CREDIT_UPDATE_IND shall only be used if the
  436. * host sends a HL_SUPPRESS_TX_COMPL_IND TLV requesting use of
  437. * TX_CREDIT_UPDATE_IND, and the target sends a HL_SUPPRESS_TX_COMPLE_IND TLV
  438. * back to the host confirming use of TX_CREDIT_UPDATE_IND.
  439. * Lack of a HL_SUPPRESS_TX_COMPL_IND TLV from either host --> target or
  440. * target --> host is equivalent to a HL_SUPPRESS_TX_COMPL_IND that
  441. * explicitly specifies HL_ALLOW_TX_COMPL_IND in the value payload of the
  442. * TLV.
  443. */
  444. enum HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND_VALUES {
  445. HTT_OPTION_TLV_HL_ALLOW_TX_COMPL_IND = 0x0,
  446. HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND = 0x1,
  447. };
  448. PREPACK struct htt_option_tlv_hl_suppress_tx_compl_ind_t {
  449. struct htt_option_tlv_header_t hdr;
  450. A_UINT16 hl_suppress_tx_compl_ind; /* HL_SUPPRESS_TX_COMPL_IND enum */
  451. } POSTPACK;
  452. /*
  453. * HTT option TLV for specifying how many tx queue groups the target
  454. * may establish.
  455. * This TLV specifies the maximum value the target may send in the
  456. * txq_group_id field of any TXQ_GROUP information elements sent by
  457. * the target to the host. This allows the host to pre-allocate an
  458. * appropriate number of tx queue group structs.
  459. *
  460. * The MAX_TX_QUEUE_GROUPS_TLV can be sent from the host to the target as
  461. * a suffix to the VERSION_REQ message to specify whether the host supports
  462. * tx queue groups at all, and if so if there is any limit on the number of
  463. * tx queue groups that the host supports.
  464. * The MAX_TX_QUEUE_GROUPS TLV can be sent from the target to the host as
  465. * a suffix to the VERSION_CONF message. If the host has specified in the
  466. * VER_REQ message a limit on the number of tx queue groups the host can
  467. * support, the target shall limit its specification of the maximum tx groups
  468. * to be no larger than this host-specified limit.
  469. *
  470. * If the target does not provide a MAX_TX_QUEUE_GROUPS TLV, then the host
  471. * shall preallocate 4 tx queue group structs, and the target shall not
  472. * specify a txq_group_id larger than 3.
  473. */
  474. enum HTT_OPTION_TLV_MAX_TX_QUEUE_GROUPS_VALUES {
  475. HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNSUPPORTED = 0,
  476. /*
  477. * values 1 through N specify the max number of tx queue groups
  478. * the sender supports
  479. */
  480. HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNLIMITED = 0xffff,
  481. };
  482. /* TEMPORARY backwards-compatibility alias for a typo fix -
  483. * The htt_option_tlv_mac_tx_queue_groups_t typo has been corrected
  484. * to htt_option_tlv_max_tx_queue_groups_t, but an alias is provided
  485. * to support the old name (with the typo) until all references to the
  486. * old name are replaced with the new name.
  487. */
  488. #define htt_option_tlv_mac_tx_queue_groups_t htt_option_tlv_max_tx_queue_groups_t
  489. PREPACK struct htt_option_tlv_max_tx_queue_groups_t {
  490. struct htt_option_tlv_header_t hdr;
  491. A_UINT16 max_tx_queue_groups; /* max txq_group_id + 1 */
  492. } POSTPACK;
  493. /*
  494. * HTT option TLV for specifying whether the target supports an extended
  495. * version of the HTT tx descriptor. If the target provides this TLV
  496. * and specifies in the TLV that the target supports an extended version
  497. * of the HTT tx descriptor, the target must check the "extension" bit in
  498. * the HTT tx descriptor, and if the extension bit is set, to expect a
  499. * HTT tx MSDU extension descriptor immediately following the HTT tx MSDU
  500. * descriptor. Furthermore, the target must provide room for the HTT
  501. * tx MSDU extension descriptor in the target's TX_FRM buffer.
  502. * This option is intended for systems where the host needs to explicitly
  503. * control the transmission parameters such as tx power for individual
  504. * tx frames.
  505. * The SUPPORT_TX_MSDU_DESC_EXT TLB can be sent by the target to the host
  506. * as a suffix to the VERSION_CONF message to explicitly specify whether
  507. * the target supports the HTT tx MSDU extension descriptor.
  508. * Lack of a SUPPORT_TX_MSDU_DESC_EXT from the target shall be interpreted
  509. * by the host as lack of target support for the HTT tx MSDU extension
  510. * descriptor; the host shall provide HTT tx MSDU extension descriptors in
  511. * the HTT_H2T TX_FRM messages only if the target indicates it supports
  512. * the HTT tx MSDU extension descriptor.
  513. * The host is not required to provide the HTT tx MSDU extension descriptor
  514. * just because the target supports it; the target must check the
  515. * "extension" bit in the HTT tx MSDU descriptor to determine whether an
  516. * extension descriptor is present.
  517. */
  518. enum HTT_OPTION_TLV_SUPPORT_TX_MSDU_DESC_EXT_VALUES {
  519. HTT_OPTION_TLV_TX_MSDU_DESC_EXT_NO_SUPPORT = 0x0,
  520. HTT_OPTION_TLV_TX_MSDU_DESC_EXT_SUPPORT = 0x1,
  521. };
  522. PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t {
  523. struct htt_option_tlv_header_t hdr;
  524. A_UINT16 tx_msdu_desc_ext_support; /* SUPPORT_TX_MSDU_DESC_EXT enum */
  525. } POSTPACK;
  526. /*
  527. * For the tcl data command V2 and higher support added a new
  528. * version tag HTT_OPTION_TLV_TAG_TCL_METADATA_VER.
  529. * This will be used as a TLV in HTT_H2T_MSG_TYPE_VERSION_REQ and
  530. * HTT_T2H_MSG_TYPE_VERSION_CONF.
  531. * HTT option TLV for specifying which version of the TCL metadata struct
  532. * should be used:
  533. * V1 -> use htt_tx_tcl_metadata struct
  534. * V2 -> use htt_tx_tcl_metadata_v2 struct
  535. * Old FW will only support V1.
  536. * New FW will support V2. New FW will still support V1, at least during
  537. * a transition period.
  538. * Similarly, old host will only support V1, and new host will support V1 + V2.
  539. *
  540. * The host can provide a HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the
  541. * HTT_H2T_MSG_TYPE_VERSION_REQ to indicate to the target which version(s)
  542. * of TCL metadata the host supports. If the host doesn't provide a
  543. * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_REQ message, it
  544. * is implicitly understood that the host only supports V1.
  545. * The target can provide a HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the
  546. * HTT_T2H_MSG_TYPE_VERSION_CONF to indicate which version of TCL metadata
  547. * the host shall use. The target shall only select one of the versions
  548. * supported by the host. If the target doesn't provide a
  549. * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_CONF message, it
  550. * is implicitly understood that the V1 TCL metadata shall be used.
  551. *
  552. * Feb 2023: Added version HTT_OPTION_TLV_TCL_METADATA_V21 = 21
  553. * read as version 2.1. We added support for Dynamic AST Index Allocation
  554. * for Alder+Pine in version 2.1. For HTT_OPTION_TLV_TCL_METADATA_V2 = 2
  555. * we will retain older behavior of making sure the AST Index for SAWF
  556. * in Pine is allocated using wifitool ath2 setUnitTestCmd 0x48 2 536 1
  557. * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and
  558. * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index
  559. * in TCLV2 command and do the dynamic AST allocations.
  560. */
  561. enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES {
  562. HTT_OPTION_TLV_TCL_METADATA_V1 = 1,
  563. HTT_OPTION_TLV_TCL_METADATA_V2 = 2,
  564. /* values 3-20 reserved */
  565. HTT_OPTION_TLV_TCL_METADATA_V21 = 21,
  566. };
  567. PREPACK struct htt_option_tlv_tcl_metadata_ver_t {
  568. struct htt_option_tlv_header_t hdr;
  569. A_UINT16 tcl_metadata_ver; /* TCL_METADATA_VER_VALUES enum */
  570. } POSTPACK;
  571. #define HTT_OPTION_TLV_TCL_METADATA_VER_SET(word, value) \
  572. HTT_OPTION_TLV_VALUE0_SET(word, value)
  573. #define HTT_OPTION_TLV_TCL_METADATA_VER_GET(word) \
  574. HTT_OPTION_TLV_VALUE0_GET(word)
  575. typedef struct {
  576. union {
  577. /* BIT [11 : 0] :- tag
  578. * BIT [23 : 12] :- length
  579. * BIT [31 : 24] :- reserved
  580. */
  581. A_UINT32 tag__length;
  582. /*
  583. * The following struct is not endian-portable.
  584. * It is suitable for use within the target, which is known to be
  585. * little-endian.
  586. * The host should use the above endian-portable macros to access
  587. * the tag and length bitfields in an endian-neutral manner.
  588. */
  589. struct {
  590. A_UINT32 tag : 12, /* BIT [11 : 0] */
  591. length : 12, /* BIT [23 : 12] */
  592. reserved : 8; /* BIT [31 : 24] */
  593. };
  594. };
  595. } htt_tlv_hdr_t;
  596. /** HTT stats TLV tag values */
  597. typedef enum {
  598. HTT_STATS_TX_PDEV_CMN_TAG = 0, /* htt_tx_pdev_stats_cmn_tlv */
  599. HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, /* htt_tx_pdev_stats_urrn_tlv_v */
  600. HTT_STATS_TX_PDEV_SIFS_TAG = 2, /* htt_tx_pdev_stats_sifs_tlv_v */
  601. HTT_STATS_TX_PDEV_FLUSH_TAG = 3, /* htt_tx_pdev_stats_flush_tlv_v */
  602. HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, /* htt_tx_pdev_stats_phy_err_tlv_v */
  603. HTT_STATS_STRING_TAG = 5, /* htt_stats_string_tlv, PUBLISH_FUNC=get_sring_name_data */
  604. HTT_STATS_TX_HWQ_CMN_TAG = 6, /* htt_tx_hwq_stats_cmn_tlv, PUBLISH_CODE=#inbound_req->tx_hwq_id_mac_id_word = ((htt_tx_hwq_stats_cmn_tlv *)tag_buf)->mac_id__hwq_id__word;#, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */
  605. HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, /* htt_tx_hwq_difs_latency_stats_tlv_v */
  606. HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, /* htt_tx_hwq_cmd_result_stats_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */
  607. HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, /* htt_tx_hwq_cmd_stall_stats_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */
  608. HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, /* htt_tx_hwq_fes_result_stats_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_tx_hwq */
  609. HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, /* htt_tx_tqm_gen_mpdu_stats_tlv_v */
  610. HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, /* htt_tx_tqm_list_mpdu_stats_tlv_v */
  611. HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, /* htt_tx_tqm_list_mpdu_cnt_tlv_v */
  612. HTT_STATS_TX_TQM_CMN_TAG = 14, /* htt_tx_tqm_cmn_stats_tlv */
  613. HTT_STATS_TX_TQM_PDEV_TAG = 15, /* htt_tx_tqm_pdev_stats_tlv_v */
  614. HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, /* htt_tx_tqm_cmdq_status_tlv */
  615. HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, /* htt_tx_de_eapol_packets_stats_tlv */
  616. HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, /* htt_tx_de_classify_failed_stats_tlv */
  617. HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, /* htt_tx_de_classify_stats_tlv */
  618. HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, /* htt_tx_de_classify_status_stats_tlv */
  619. HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, /* htt_tx_de_enqueue_packets_stats_tlv */
  620. HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, /* htt_tx_de_enqueue_discard_stats_tlv */
  621. HTT_STATS_TX_DE_CMN_TAG = 23, /* htt_tx_de_cmn_stats_tlv */
  622. HTT_STATS_RING_IF_TAG = 24, /* htt_ring_if_stats_tlv */
  623. HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, /* htt_tx_pdev_mu_mimo_sch_stats_tlv */
  624. HTT_STATS_SFM_CMN_TAG = 26, /* htt_sfm_cmn_tlv */
  625. HTT_STATS_SRING_STATS_TAG = 27, /* htt_sring_stats_tlv, PUBLISH_FUNC=create_json_response_for_sring_stats */
  626. HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, /* htt_rx_pdev_fw_stats_tlv */
  627. HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, /* htt_rx_pdev_fw_ring_mpdu_err_tlv_v */
  628. HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, /* htt_rx_pdev_fw_mpdu_drop_tlv_v */
  629. HTT_STATS_RX_SOC_FW_STATS_TAG = 31, /* htt_rx_soc_fw_stats_tlv */
  630. HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, /* htt_rx_soc_fw_refill_ring_empty_tlv_v */
  631. HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, /* htt_rx_soc_fw_refill_ring_num_refill_tlv_v */
  632. HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, /* htt_tx_pdev_rate_stats_tlv */
  633. HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, /* htt_rx_pdev_rate_stats_tlv */
  634. HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, /* htt_tx_pdev_stats_sched_per_txq_tlv, PUBLISH_CODE=#inbound_req->tx_sched_txq_id_mac_id_word = ((htt_tx_pdev_stats_sched_per_txq_tlv *)tag_buf)->mac_id__txq_id__word;#, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */
  635. HTT_STATS_TX_SCHED_CMN_TAG = 37, /* htt_stats_tx_sched_cmn_tlv, PUBLISH_SKIP */
  636. HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, /* htt_tx_pdev_mu_mimo_mpdu_stats_tlv */
  637. HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, /* htt_sched_txq_cmd_posted_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */
  638. HTT_STATS_RING_IF_CMN_TAG = 40, /* htt_ring_if_cmn_tlv */
  639. HTT_STATS_SFM_CLIENT_USER_TAG = 41, /* htt_sfm_client_user_tlv_v, PUBLISH_FUNC=create_json_response_for_sfm_client */
  640. HTT_STATS_SFM_CLIENT_TAG = 42, /* htt_sfm_client_tlv, PUBLISH_FUNC=create_json_response_for_sfm_client */
  641. HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, /* htt_tx_tqm_error_stats_tlv */
  642. HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, /* htt_sched_txq_cmd_reaped_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */
  643. HTT_STATS_SRING_CMN_TAG = 45, /* htt_sring_cmn_tlv */
  644. HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, /* htt_tx_selfgen_ac_err_stats_tlv */
  645. HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, /* htt_tx_selfgen_cmn_stats_tlv */
  646. HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, /* htt_tx_selfgen_ac_stats_tlv */
  647. HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, /* htt_tx_selfgen_ax_stats_tlv */
  648. HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, /* htt_tx_selfgen_ax_err_stats_tlv */
  649. HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, /* htt_tx_hwq_mu_mimo_sch_stats_tlv */
  650. HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, /* htt_tx_hwq_mu_mimo_mpdu_stats_tlv */
  651. HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, /* htt_tx_hwq_mu_mimo_cmn_stats_tlv */
  652. HTT_STATS_HW_INTR_MISC_TAG = 54, /* htt_hw_stats_intr_misc_tlv, PUBLISH_FUNC=create_json_response_for_hwstats_intr_misc */
  653. HTT_STATS_HW_WD_TIMEOUT_TAG = 55, /* htt_hw_stats_wd_timeout_tlv */
  654. HTT_STATS_HW_PDEV_ERRS_TAG = 56, /* htt_hw_stats_pdev_errs_tlv */
  655. HTT_STATS_COUNTER_NAME_TAG = 57, /* htt_counter_tlv */
  656. HTT_STATS_TX_TID_DETAILS_TAG = 58, /* htt_tx_tid_stats_tlv */
  657. HTT_STATS_RX_TID_DETAILS_TAG = 59, /* htt_rx_tid_stats_tlv */
  658. HTT_STATS_PEER_STATS_CMN_TAG = 60, /* htt_peer_stats_cmn_tlv */
  659. HTT_STATS_PEER_DETAILS_TAG = 61, /* htt_peer_details_tlv */
  660. HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, /* htt_tx_peer_rate_stats_tlv */
  661. HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, /* htt_rx_peer_rate_stats_tlv, TOPIC=advanced */
  662. HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, /* htt_msdu_flow_stats_tlv */
  663. HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, /* htt_tx_de_compl_stats_tlv */
  664. HTT_STATS_WHAL_TX_TAG = 66, /* htt_hw_stats_whal_tx_tlv */
  665. HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, /* htt_tx_pdev_stats_sifs_hist_tlv_v */
  666. HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, /* htt_rx_pdev_fw_stats_phy_err_tlv */
  667. HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, /* htt_tx_tid_stats_v1_tlv */
  668. HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, /* htt_pdev_cca_stats_hist_tlv (for 1 sec interval stats), PUBLISH_FUNC=update_htt_pdev_cca_stat_context */
  669. HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, /* htt_pdev_cca_stats_hist_tlv (for 100 msec interval stats), PUBLISH_FUNC=update_htt_pdev_cca_stat_context */
  670. HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, /* htt_pdev_stats_cca_stats_tlv, PUBLISH_FUNC=update_htt_pdev_cca_stat_context */
  671. HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, /* htt_pdev_stats_cca_counters_tlv, PUBLISH_FUNC=create_json_response_for_htt_pdev_cca_stat */
  672. HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, /* htt_tx_pdev_mpdu_stats_tlv, PUBLISH_FUNC=create_json_response_for_htt_tx_pdev_mpdu_stat */
  673. HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, /* htt_pdev_stats_twt_sessions_tlv */
  674. HTT_STATS_PDEV_TWT_SESSION_TAG = 76, /* htt_pdev_stats_twt_session_tlv */
  675. HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, /* htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v */
  676. HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, /* htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v */
  677. HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, /* htt_rx_reo_debug_stats_tlv_v */
  678. HTT_STATS_TX_SOUNDING_STATS_TAG = 80, /* htt_tx_sounding_stats_tlv */
  679. HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81, /* htt_tx_pdev_stats_tx_ppdu_stats_tlv_v */
  680. HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82, /* htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v */
  681. HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83, /* htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v */
  682. HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84, /* htt_tx_hwq_txop_used_cnt_hist_tlv_v */
  683. HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85, /* htt_tx_de_fw2wbm_ring_full_hist_tlv */
  684. HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, /* htt_sched_txq_sched_order_su_tlv, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */
  685. HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, /* htt_sched_txq_sched_eligibility_tlv, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */
  686. HTT_STATS_PDEV_OBSS_PD_TAG = 88, /* htt_pdev_obss_pd_stats_tlv */
  687. HTT_STATS_HW_WAR_TAG = 89, /* htt_hw_war_stats_tlv */
  688. HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90, /* htt_ring_backpressure_stats_tlv, PUBLISH_FUNC=create_json_response_for_ring_bkp_pressure_stats */
  689. HTT_STATS_LATENCY_PROF_STATS_TAG = 91, /* htt_latency_prof_stats_tlv, PUBLISH_FUNC=create_json_response_for_latency_prof_stats */
  690. HTT_STATS_LATENCY_CTX_TAG = 92, /* htt_latency_prof_ctx_tlv */
  691. HTT_STATS_LATENCY_CNT_TAG = 93, /* htt_latency_prof_cnt_tlv */
  692. HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG = 94, /* htt_rx_pdev_ul_trigger_stats_tlv */
  693. HTT_STATS_RX_PDEV_UL_OFDMA_USER_STATS_TAG = 95, /* htt_rx_pdev_ul_ofdma_user_stats_tlv, PUBLISH_FUNC=create_json_response_for_htt_rx_pdev_ul_ofdma_user_stat */
  694. HTT_STATS_RX_PDEV_UL_MIMO_USER_STATS_TAG = 96, /* htt_rx_pdev_ul_mimo_user_stats_tlv */
  695. HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG = 97, /* htt_rx_pdev_ul_mumimo_trig_stats_tlv */
  696. HTT_STATS_RX_FSE_STATS_TAG = 98, /* htt_rx_fse_stats_tlv */
  697. HTT_STATS_PEER_SCHED_STATS_TAG = 99, /* htt_peer_sched_stats_tlv, TOPIC=peer */
  698. HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, /* htt_sched_txq_supercycle_triggers_tlv_v, PUBLISH_FUNC=create_json_response_for_htt_stats_sched_txq */
  699. HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101, /* htt_peer_ctrl_path_txrx_stats_tlv */
  700. HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, /* htt_pdev_ctrl_path_tx_stats_tlv */
  701. HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG = 103, /* htt_rx_pdev_rate_ext_stats_tlv, PUBLISH_FUNC=create_json_response_for_rx_pdev_rate_ext */
  702. HTT_STATS_TX_PDEV_DL_MU_MIMO_STATS_TAG = 104, /* htt_tx_pdev_dl_mu_mimo_sch_stats_tlv */
  703. HTT_STATS_TX_PDEV_UL_MU_MIMO_STATS_TAG = 105, /* htt_tx_pdev_ul_mu_mimo_sch_stats_tlv */
  704. HTT_STATS_TX_PDEV_DL_MU_OFDMA_STATS_TAG = 106, /* htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv */
  705. HTT_STATS_TX_PDEV_UL_MU_OFDMA_STATS_TAG = 107, /* htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv */
  706. HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, /* htt_tx_peer_rate_txbf_stats_tlv */
  707. HTT_STATS_UNSUPPORTED_ERROR_STATS_TAG = 109, /* htt_stats_error_tlv_v */
  708. HTT_STATS_UNAVAILABLE_ERROR_STATS_TAG = 110, /* htt_stats_error_tlv_v */
  709. HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, /* htt_tx_selfgen_ac_sched_status_stats_tlv */
  710. HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, /* htt_tx_selfgen_ax_sched_status_stats_tlv */
  711. HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113, /* htt_txbf_ofdma_ndpa_stats_tlv - DEPRECATED */
  712. HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114, /* htt_txbf_ofdma_ndp_stats_tlv - DEPRECATED */
  713. HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115, /* htt_txbf_ofdma_brp_stats_tlv - DEPRECATED */
  714. HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116, /* htt_txbf_ofdma_steer_stats_tlv - DEPRECATED */
  715. HTT_STATS_STA_UL_OFDMA_STATS_TAG = 117, /* htt_sta_ul_ofdma_stats_tlv */
  716. HTT_STATS_VDEV_RTT_RESP_STATS_TAG = 118, /* htt_vdev_rtt_resp_stats_tlv */
  717. HTT_STATS_PKTLOG_AND_HTT_RING_STATS_TAG = 119, /* htt_pktlog_and_htt_ring_stats_tlv */
  718. HTT_STATS_DLPAGER_STATS_TAG = 120, /* htt_dlpager_stats_tlv */
  719. HTT_STATS_PHY_COUNTERS_TAG = 121, /* htt_phy_counters_tlv */
  720. HTT_STATS_PHY_STATS_TAG = 122, /* htt_phy_stats_tlv */
  721. HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, /* htt_phy_reset_counters_tlv */
  722. HTT_STATS_PHY_RESET_STATS_TAG = 124, /* htt_phy_reset_stats_tlv */
  723. HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, /* htt_t2h_soc_txrx_stats_common_tlv */
  724. HTT_STATS_VDEV_TXRX_STATS_HW_STATS_TAG = 126, /* htt_t2h_vdev_txrx_stats_hw_stats_tlv */
  725. HTT_STATS_VDEV_RTT_INIT_STATS_TAG = 127, /* htt_vdev_rtt_init_stats_tlv */
  726. HTT_STATS_PER_RATE_STATS_TAG = 128, /* htt_tx_rate_stats_per_tlv, PUBLISH_FUNC=create_json_response_for_htt_tx_rate_stats_per */
  727. HTT_STATS_MU_PPDU_DIST_TAG = 129, /* htt_pdev_mu_ppdu_dist_tlv, PUBLISH_FUNC=create_json_response_for_htt_stats_mu_ppdu */
  728. HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, /* htt_tx_pdev_mumimo_grp_stats_tlv */
  729. HTT_STATS_TX_PDEV_BE_RATE_STATS_TAG = 131, /* htt_tx_pdev_rate_stats_be_tlv, TOPIC=advanced */
  730. HTT_STATS_AST_ENTRY_TAG = 132, /* htt_ast_entry_tlv */
  731. HTT_STATS_TX_PDEV_BE_DL_MU_OFDMA_STATS_TAG = 133, /* htt_tx_pdev_dl_be_mu_ofdma_sch_stats_tlv, TOPIC=advanced */
  732. HTT_STATS_TX_PDEV_BE_UL_MU_OFDMA_STATS_TAG = 134, /* htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv, TOPIC=advanced */
  733. HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, /* htt_tx_pdev_rate_stats_be_ofdma_tlv */
  734. HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG = 136, /* htt_rx_pdev_ul_mumimo_trig_be_stats_tlv, TOPIC=advanced */
  735. HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, /* htt_tx_selfgen_be_err_stats_tlv, TOPIC=advanced */
  736. HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, /* htt_tx_selfgen_be_stats_tlv, TOPIC=advanced */
  737. HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, /* htt_tx_selfgen_be_sched_status_stats_tlv, TOPIC=advanced */
  738. HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG = 140, /* htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv */
  739. HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, /* htt_rx_pdev_be_ul_mimo_user_stats_tlv */
  740. HTT_STATS_RX_RING_STATS_TAG = 142, /* htt_rx_fw_ring_stats_tlv_v */
  741. HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = 143, /* htt_rx_pdev_be_ul_trigger_stats_tlv, TOPIC=advanced */
  742. HTT_STATS_TX_PDEV_SAWF_RATE_STATS_TAG = 144, /* htt_tx_pdev_rate_stats_sawf_tlv, TOPIC=advanced */
  743. HTT_STATS_STRM_GEN_MPDUS_TAG = 145, /* htt_stats_strm_gen_mpdus_tlv_t */
  744. HTT_STATS_STRM_GEN_MPDUS_DETAILS_TAG = 146, /* htt_stats_strm_gen_mpdus_details_tlv_t */
  745. HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG = 147, /* htt_txbf_ofdma_ax_ndpa_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */
  746. HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG = 148, /* htt_txbf_ofdma_ax_ndp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */
  747. HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG = 149, /* htt_txbf_ofdma_ax_brp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */
  748. HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG = 150, /* htt_txbf_ofdma_ax_steer_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */
  749. HTT_STATS_TXBF_OFDMA_BE_NDPA_STATS_TAG = 151, /* htt_txbf_ofdma_be_ndpa_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */
  750. HTT_STATS_TXBF_OFDMA_BE_NDP_STATS_TAG = 152, /* htt_txbf_ofdma_be_ndp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */
  751. HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG = 153, /* htt_txbf_ofdma_be_brp_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */
  752. HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG = 154, /* htt_txbf_ofdma_be_steer_stats_tlv, PUBLISH_FUNC_FILE=create_json_response_for_txbf_ofdma_wrapper */
  753. HTT_STATS_DMAC_RESET_STATS_TAG = 155, /* htt_dmac_reset_stats_tlv */
  754. HTT_STATS_RX_PDEV_BE_UL_OFDMA_USER_STATS_TAG = 156, /* htt_rx_pdev_be_ul_ofdma_user_stats_tlv, TOPIC=advanced */
  755. HTT_STATS_PHY_TPC_STATS_TAG = 157, /* htt_phy_tpc_stats_tlv */
  756. HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, /* htt_pdev_puncture_stats_tlv */
  757. HTT_STATS_ML_PEER_DETAILS_TAG = 159, /* htt_ml_peer_details_tlv */
  758. HTT_STATS_ML_PEER_EXT_DETAILS_TAG = 160, /* htt_ml_peer_ext_details_tlv */
  759. HTT_STATS_ML_LINK_INFO_DETAILS_TAG = 161, /* htt_ml_link_info_tlv */
  760. HTT_STATS_TX_PDEV_PPDU_DUR_TAG = 162, /* htt_tx_pdev_ppdu_dur_stats_tlv, TOPIC=advanced */
  761. HTT_STATS_RX_PDEV_PPDU_DUR_TAG = 163, /* htt_rx_pdev_ppdu_dur_stats_tlv, TOPIC=advanced */
  762. HTT_STATS_ODD_PDEV_MANDATORY_TAG = 164, /* htt_odd_mandatory_pdev_stats_tlv */
  763. HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, /* htt_pdev_sched_algo_ofdma_stats_tlv, PUBLISH_FUNC=create_json_response_for_htt_pdev_sched_algo_ofdma_stats */
  764. HTT_DBG_ODD_MANDATORY_MUMIMO_TAG = 166, /* htt_odd_mandatory_mumimo_pdev_stats_tlv */
  765. HTT_DBG_ODD_MANDATORY_MUOFDMA_TAG = 167, /* htt_odd_mandatory_muofdma_pdev_stats_tlv */
  766. HTT_STATS_LATENCY_PROF_CAL_STATS_TAG = 168, /* htt_latency_prof_cal_stats_tlv - DEPRECATED */
  767. HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v - DEPRECATED */
  768. HTT_STATS_PDEV_BW_MGR_STATS_TAG = 170, /* htt_pdev_bw_mgr_stats_tlv */
  769. HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v, TOPIC=advanced */
  770. HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, /* htt_txbf_ofdma_ax_steer_mpdu_stats_tlv, TOPIC=advanced */
  771. HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG = 173, /* htt_txbf_ofdma_be_steer_mpdu_stats_tlv, TOPIC=advanced */
  772. HTT_STATS_PEER_AX_OFDMA_STATS_TAG = 174, /* htt_peer_ax_ofdma_stats_tlv */
  773. HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG = 175, /* htt_tx_pdev_mu_edca_params_stats_tlv_v, TOPIC=advanced */
  774. HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */
  775. HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */
  776. HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */
  777. HTT_STATS_UMAC_SSR_TAG = 179, /* htt_umac_ssr_stats_tlv */
  778. HTT_STATS_PEER_BE_OFDMA_STATS_TAG = 180, /* htt_peer_be_ofdma_stats_tlv */
  779. HTT_STATS_MLO_UMAC_SSR_TRIGGER_TAG = 181, /* htt_mlo_umac_ssr_trigger_stats_tlv */
  780. HTT_STATS_MLO_UMAC_SSR_CMN_TAG = 182, /* htt_mlo_umac_ssr_common_stats_tlv */
  781. HTT_STATS_MLO_UMAC_SSR_KPI_TSTMP_TAG = 183, /* htt_mlo_umac_ssr_kpi_tstamp_stats_tlv */
  782. HTT_STATS_MLO_UMAC_SSR_DBG_TAG = 184, /* htt_mlo_umac_ssr_dbg_tlv */
  783. HTT_STATS_MLO_UMAC_SSR_HANDSHAKE_TAG = 185, /* htt_mlo_umac_htt_handshake_stats_tlv */
  784. HTT_STATS_MLO_UMAC_SSR_MLO_TAG = 186, /* htt_mlo_umac_ssr_mlo_stats_tlv */
  785. HTT_STATS_PDEV_TDMA_TAG = 187, /* htt_pdev_tdma_stats_tlv */
  786. HTT_STATS_CODEL_SVC_CLASS_TAG = 188, /* htt_codel_svc_class_stats_tlv */
  787. HTT_STATS_CODEL_MSDUQ_TAG = 189, /* htt_codel_msduq_stats_tlv */
  788. HTT_STATS_MLO_SCHED_STATS_TAG = 190, /* htt_mlo_sched_stats_tlv */
  789. HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, /* htt_pdev_mlo_ipc_stats_tlv */
  790. HTT_STATS_WHAL_WSI_TAG = 192, /* htt_stats_whal_wsi_tlv */
  791. HTT_STATS_LATENCY_PROF_CAL_DATA_TAG = 193, /* htt_stats_latency_prof_cal_data_tlv */
  792. HTT_STATS_PDEV_RTT_RESP_STATS_TAG = 194, /* htt_stats_pdev_rtt_resp_stats_tlv */
  793. HTT_STATS_PDEV_RTT_INIT_STATS_TAG = 195, /* htt_stats_pdev_rtt_init_stats_tlv */
  794. HTT_STATS_PDEV_RTT_HW_STATS_TAG = 196, /* htt_stats_pdev_rtt_hw_stats_tlv */
  795. HTT_STATS_PDEV_RTT_TBR_SELFGEN_QUEUED_STATS_TAG = 197, /* htt_stats_pdev_rtt_tbr_selfgen_queued_stats_tlv */
  796. HTT_STATS_PDEV_RTT_TBR_CMD_RESULT_STATS_TAG = 198, /* htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv */
  797. HTT_STATS_GTX_TAG = 199, /* htt_stats_gtx_tlv */
  798. HTT_STATS_TX_PDEV_WIFI_RADAR_TAG = 200, /* htt_stats_tx_pdev_wifi_radar_tlv */
  799. HTT_STATS_TXBF_OFDMA_BE_PARBW_TAG = 201, /* htt_stats_txbf_ofdma_be_parbw_tlv */
  800. HTT_STATS_RX_PDEV_RSSI_HIST_TAG = 202, /* htt_stats_rx_pdev_rssi_hist_tlv */
  801. HTT_STATS_MAX_TAG,
  802. } htt_stats_tlv_tag_t;
  803. /* retain deprecated enum name as an alias for the current enum name */
  804. typedef htt_stats_tlv_tag_t htt_tlv_tag_t;
  805. #define HTT_STATS_TLV_TAG_M 0x00000fff
  806. #define HTT_STATS_TLV_TAG_S 0
  807. #define HTT_STATS_TLV_LENGTH_M 0x00fff000
  808. #define HTT_STATS_TLV_LENGTH_S 12
  809. #define HTT_STATS_TLV_TAG_GET(_var) \
  810. (((_var) & HTT_STATS_TLV_TAG_M) >> \
  811. HTT_STATS_TLV_TAG_S)
  812. #define HTT_STATS_TLV_TAG_SET(_var, _val) \
  813. do { \
  814. HTT_CHECK_SET_VAL(HTT_STATS_TLV_TAG, _val); \
  815. ((_var) |= ((_val) << HTT_STATS_TLV_TAG_S)); \
  816. } while (0)
  817. #define HTT_STATS_TLV_LENGTH_GET(_var) \
  818. (((_var) & HTT_STATS_TLV_LENGTH_M) >> \
  819. HTT_STATS_TLV_LENGTH_S)
  820. #define HTT_STATS_TLV_LENGTH_SET(_var, _val) \
  821. do { \
  822. HTT_CHECK_SET_VAL(HTT_STATS_TLV_LENGTH, _val); \
  823. ((_var) |= ((_val) << HTT_STATS_TLV_LENGTH_S)); \
  824. } while (0)
  825. /*=== host -> target messages ===============================================*/
  826. enum htt_h2t_msg_type {
  827. HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0,
  828. HTT_H2T_MSG_TYPE_TX_FRM = 0x1,
  829. HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2,
  830. HTT_H2T_MSG_TYPE_STATS_REQ = 0x3,
  831. HTT_H2T_MSG_TYPE_SYNC = 0x4,
  832. HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5,
  833. HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6,
  834. DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */
  835. HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8,
  836. HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9,
  837. HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /* per vdev amsdu subfrm limit */
  838. HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb,
  839. HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,
  840. HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY = 0xd,
  841. HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY = 0xe,
  842. HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf,
  843. HTT_H2T_MSG_TYPE_EXT_STATS_REQ = 0x10,
  844. HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
  845. HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12,
  846. HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13,
  847. HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14,
  848. HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15,
  849. HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG = 0x16,
  850. HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17,
  851. HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE = 0x18,
  852. HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG = 0x19,
  853. HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG = 0x1a,
  854. HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b,
  855. HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ = 0x1c,
  856. HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ = 0x1d,
  857. HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ = 0x1e,
  858. HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f,
  859. HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20,
  860. HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21,
  861. HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22,
  862. HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23,
  863. HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24,
  864. HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25,
  865. HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP = 0x26,
  866. HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ = 0x27,
  867. /* keep this last */
  868. HTT_H2T_NUM_MSGS
  869. };
  870. /*
  871. * HTT host to target message type -
  872. * stored in bits 7:0 of the first word of the message
  873. */
  874. #define HTT_H2T_MSG_TYPE_M 0xff
  875. #define HTT_H2T_MSG_TYPE_S 0
  876. #define HTT_H2T_MSG_TYPE_SET(word, msg_type) \
  877. do { \
  878. HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE, msg_type); \
  879. (word) |= ((msg_type) << HTT_H2T_MSG_TYPE_S); \
  880. } while (0)
  881. #define HTT_H2T_MSG_TYPE_GET(word) \
  882. (((word) & HTT_H2T_MSG_TYPE_M) >> HTT_H2T_MSG_TYPE_S)
  883. /**
  884. * @brief host -> target version number request message definition
  885. *
  886. * MSG_TYPE => HTT_H2T_MSG_TYPE_VERSION_REQ
  887. *
  888. *
  889. * |31 24|23 16|15 8|7 0|
  890. * |----------------+----------------+----------------+----------------|
  891. * | reserved | msg type |
  892. * |-------------------------------------------------------------------|
  893. * : option request TLV (optional) |
  894. * :...................................................................:
  895. *
  896. * The VER_REQ message may consist of a single 4-byte word, or may be
  897. * extended with TLVs that specify which HTT options the host is requesting
  898. * from the target.
  899. * The following option TLVs may be appended to the VER_REQ message:
  900. * - HL_SUPPRESS_TX_COMPL_IND
  901. * - HL_MAX_TX_QUEUE_GROUPS
  902. * These TLVs may appear in an arbitrary order. Any number of these TLVs
  903. * may be appended to the VER_REQ message (but only one TLV of each type).
  904. *
  905. * Header fields:
  906. * - MSG_TYPE
  907. * Bits 7:0
  908. * Purpose: identifies this as a version number request message
  909. * Value: 0x0 (HTT_H2T_MSG_TYPE_VERSION_REQ)
  910. */
  911. #define HTT_VER_REQ_BYTES 4
  912. /* TBDXXX: figure out a reasonable number */
  913. #define HTT_HL_DATA_SVC_PIPE_DEPTH 24
  914. #define HTT_LL_DATA_SVC_PIPE_DEPTH 64
  915. /**
  916. * @brief HTT tx MSDU descriptor
  917. *
  918. * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_FRM
  919. *
  920. * @details
  921. * The HTT tx MSDU descriptor is created by the host HTT SW for each
  922. * tx MSDU. The HTT tx MSDU descriptor contains the information that
  923. * the target firmware needs for the FW's tx processing, particularly
  924. * for creating the HW msdu descriptor.
  925. * The same HTT tx descriptor is used for HL and LL systems, though
  926. * a few fields within the tx descriptor are used only by LL or
  927. * only by HL.
  928. * The HTT tx descriptor is defined in two manners: by a struct with
  929. * bitfields, and by a series of [dword offset, bit mask, bit shift]
  930. * definitions.
  931. * The target should use the struct def, for simplicitly and clarity,
  932. * but the host shall use the bit-mast + bit-shift defs, to be endian-
  933. * neutral. Specifically, the host shall use the get/set macros built
  934. * around the mask + shift defs.
  935. */
  936. #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_S 0
  937. #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_M 0x1
  938. #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_S 1
  939. #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_M 0x2
  940. #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_S 2
  941. #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_M 0x4
  942. #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_S 3
  943. #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_M 0x8
  944. #define HTT_TX_VDEV_ID_WORD 0
  945. #define HTT_TX_VDEV_ID_MASK 0x3f
  946. #define HTT_TX_VDEV_ID_SHIFT 16
  947. #define HTT_TX_L3_CKSUM_OFFLOAD 1
  948. #define HTT_TX_L4_CKSUM_OFFLOAD 2
  949. #define HTT_TX_MSDU_LEN_DWORD 1
  950. #define HTT_TX_MSDU_LEN_MASK 0xffff;
  951. /*
  952. * HTT_VAR_PADDR macros
  953. * Allow physical / bus addresses to be either a single 32-bit value,
  954. * or a 64-bit value, stored as a little-endian lo,hi pair of 32-bit parts
  955. */
  956. #define HTT_VAR_PADDR32(var_name) \
  957. A_UINT32 var_name
  958. #define HTT_VAR_PADDR64_LE(var_name) \
  959. struct { \
  960. /* little-endian: lo precedes hi */ \
  961. A_UINT32 lo; \
  962. A_UINT32 hi; \
  963. } var_name
  964. /*
  965. * TEMPLATE_HTT_TX_MSDU_DESC_T:
  966. * This macro defines a htt_tx_msdu_descXXX_t in which any physical
  967. * addresses are stored in a XXX-bit field.
  968. * This macro is used to define both htt_tx_msdu_desc32_t and
  969. * htt_tx_msdu_desc64_t structs.
  970. */
  971. #define TEMPLATE_HTT_TX_MSDU_DESC_T(_paddr_bits_, _paddr__frags_desc_ptr_) \
  972. PREPACK struct htt_tx_msdu_desc ## _paddr_bits_ ## _t \
  973. { \
  974. /* DWORD 0: flags and meta-data */ \
  975. A_UINT32 \
  976. msg_type: 8, /* HTT_H2T_MSG_TYPE_TX_FRM */ \
  977. \
  978. /* pkt_subtype - \
  979. * Detailed specification of the tx frame contents, extending the \
  980. * general specification provided by pkt_type. \
  981. * FIX THIS: ADD COMPLETE SPECS FOR THIS FIELDS VALUE, e.g. \
  982. * pkt_type | pkt_subtype \
  983. * ============================================================== \
  984. * 802.3 | bit 0:3 - Reserved \
  985. * | bit 4: 0x0 - Copy-Engine Classification Results \
  986. * | not appended to the HTT message \
  987. * | 0x1 - Copy-Engine Classification Results \
  988. * | appended to the HTT message in the \
  989. * | format: \
  990. * | [HTT tx desc, frame header, \
  991. * | CE classification results] \
  992. * | The CE classification results begin \
  993. * | at the next 4-byte boundary after \
  994. * | the frame header. \
  995. * ------------+------------------------------------------------- \
  996. * Eth2 | bit 0:3 - Reserved \
  997. * | bit 4: 0x0 - Copy-Engine Classification Results \
  998. * | not appended to the HTT message \
  999. * | 0x1 - Copy-Engine Classification Results \
  1000. * | appended to the HTT message. \
  1001. * | See the above specification of the \
  1002. * | CE classification results location. \
  1003. * ------------+------------------------------------------------- \
  1004. * native WiFi | bit 0:3 - Reserved \
  1005. * | bit 4: 0x0 - Copy-Engine Classification Results \
  1006. * | not appended to the HTT message \
  1007. * | 0x1 - Copy-Engine Classification Results \
  1008. * | appended to the HTT message. \
  1009. * | See the above specification of the \
  1010. * | CE classification results location. \
  1011. * ------------+------------------------------------------------- \
  1012. * mgmt | 0x0 - 802.11 MAC header absent \
  1013. * | 0x1 - 802.11 MAC header present \
  1014. * ------------+------------------------------------------------- \
  1015. * raw | bit 0: 0x0 - 802.11 MAC header absent \
  1016. * | 0x1 - 802.11 MAC header present \
  1017. * | bit 1: 0x0 - allow aggregation \
  1018. * | 0x1 - don't allow aggregation \
  1019. * | bit 2: 0x0 - perform encryption \
  1020. * | 0x1 - don't perform encryption \
  1021. * | bit 3: 0x0 - perform tx classification / queuing \
  1022. * | 0x1 - don't perform tx classification; \
  1023. * | insert the frame into the "misc" \
  1024. * | tx queue \
  1025. * | bit 4: 0x0 - Copy-Engine Classification Results \
  1026. * | not appended to the HTT message \
  1027. * | 0x1 - Copy-Engine Classification Results \
  1028. * | appended to the HTT message. \
  1029. * | See the above specification of the \
  1030. * | CE classification results location. \
  1031. */ \
  1032. pkt_subtype: 5, \
  1033. \
  1034. /* pkt_type - \
  1035. * General specification of the tx frame contents. \
  1036. * The htt_pkt_type enum should be used to specify and check the \
  1037. * value of this field. \
  1038. */ \
  1039. pkt_type: 3, \
  1040. \
  1041. /* vdev_id - \
  1042. * ID for the vdev that is sending this tx frame. \
  1043. * For certain non-standard packet types, e.g. pkt_type == raw \
  1044. * and (pkt_subtype >> 3) == 1, this field is not relevant/valid. \
  1045. * This field is used primarily for determining where to queue \
  1046. * broadcast and multicast frames. \
  1047. */ \
  1048. vdev_id: 6, \
  1049. /* ext_tid - \
  1050. * The extended traffic ID. \
  1051. * If the TID is unknown, the extended TID is set to \
  1052. * HTT_TX_EXT_TID_INVALID. \
  1053. * If the tx frame is QoS data, then the extended TID has the 0-15 \
  1054. * value of the QoS TID. \
  1055. * If the tx frame is non-QoS data, then the extended TID is set to \
  1056. * HTT_TX_EXT_TID_NON_QOS. \
  1057. * If the tx frame is multicast or broadcast, then the extended TID \
  1058. * is set to HTT_TX_EXT_TID_MCAST_BCAST. \
  1059. */ \
  1060. ext_tid: 5, \
  1061. \
  1062. /* postponed - \
  1063. * This flag indicates whether the tx frame has been downloaded to \
  1064. * the target before but discarded by the target, and now is being \
  1065. * downloaded again; or if this is a new frame that is being \
  1066. * downloaded for the first time. \
  1067. * This flag allows the target to determine the correct order for \
  1068. * transmitting new vs. old frames. \
  1069. * value: 0 -> new frame, 1 -> re-send of a previously sent frame \
  1070. * This flag only applies to HL systems, since in LL systems, \
  1071. * the tx flow control is handled entirely within the target. \
  1072. */ \
  1073. postponed: 1, \
  1074. \
  1075. /* extension - \
  1076. * This flag indicates whether a HTT tx MSDU extension descriptor \
  1077. * (htt_tx_msdu_desc_ext_t) follows this HTT tx MSDU descriptor. \
  1078. * \
  1079. * 0x0 - no extension MSDU descriptor is present \
  1080. * 0x1 - an extension MSDU descriptor immediately follows the \
  1081. * regular MSDU descriptor \
  1082. */ \
  1083. extension: 1, \
  1084. \
  1085. /* cksum_offload - \
  1086. * This flag indicates whether checksum offload is enabled or not \
  1087. * for this frame. Target FW use this flag to turn on HW checksumming \
  1088. * 0x0 - No checksum offload \
  1089. * 0x1 - L3 header checksum only \
  1090. * 0x2 - L4 checksum only \
  1091. * 0x3 - L3 header checksum + L4 checksum \
  1092. */ \
  1093. cksum_offload: 2, \
  1094. \
  1095. /* tx_comp_req - \
  1096. * This flag indicates whether Tx Completion \
  1097. * from fw is required or not. \
  1098. * This flag is only relevant if tx completion is not \
  1099. * universally enabled. \
  1100. * For all LL systems, tx completion is mandatory, \
  1101. * so this flag will be irrelevant. \
  1102. * For HL systems tx completion is optional, but HL systems in which \
  1103. * the bus throughput exceeds the WLAN throughput will \
  1104. * probably want to always use tx completion, and thus \
  1105. * would not check this flag. \
  1106. * This flag is required when tx completions are not used universally, \
  1107. * but are still required for certain tx frames for which \
  1108. * an OTA delivery acknowledgment is needed by the host. \
  1109. * In practice, this would be for HL systems in which the \
  1110. * bus throughput is less than the WLAN throughput. \
  1111. * \
  1112. * 0x0 - Tx Completion Indication from Fw not required \
  1113. * 0x1 - Tx Completion Indication from Fw is required \
  1114. */ \
  1115. tx_compl_req: 1; \
  1116. \
  1117. \
  1118. /* DWORD 1: MSDU length and ID */ \
  1119. A_UINT32 \
  1120. len: 16, /* MSDU length, in bytes */ \
  1121. id: 16; /* MSDU ID used to identify the MSDU to the host, \
  1122. * and this id is used to calculate fragmentation \
  1123. * descriptor pointer inside the target based on \
  1124. * the base address, configured inside the target. \
  1125. */ \
  1126. \
  1127. /* DWORD 2 (or 2-3): fragmentation descriptor bus address */ \
  1128. /* frags_desc_ptr - \
  1129. * The fragmentation descriptor pointer tells the HW's MAC DMA \
  1130. * where the tx frame's fragments reside in memory. \
  1131. * This field only applies to LL systems, since in HL systems the \
  1132. * (degenerate single-fragment) fragmentation descriptor is created \
  1133. * within the target. \
  1134. */ \
  1135. _paddr__frags_desc_ptr_; \
  1136. \
  1137. /* DWORD 3 (or 4): peerid, chanfreq */ \
  1138. /* \
  1139. * Peer ID : Target can use this value to know which peer-id packet \
  1140. * destined to. \
  1141. * It's intended to be specified by host in case of NAWDS. \
  1142. */ \
  1143. A_UINT16 peerid; \
  1144. \
  1145. /* \
  1146. * Channel frequency: This identifies the desired channel \
  1147. * frequency (in mhz) for tx frames. This is used by FW to help \
  1148. * determine when it is safe to transmit or drop frames for \
  1149. * off-channel operation. \
  1150. * The default value of zero indicates to FW that the corresponding \
  1151. * VDEV's home channel (if there is one) is the desired channel \
  1152. * frequency. \
  1153. */ \
  1154. A_UINT16 chanfreq; \
  1155. \
  1156. /* Reason reserved is commented is increasing the htt structure size \
  1157. * leads to some weird issues. \
  1158. * A_UINT32 reserved_dword3_bits0_31; \
  1159. */ \
  1160. } POSTPACK
  1161. /* define a htt_tx_msdu_desc32_t type */
  1162. TEMPLATE_HTT_TX_MSDU_DESC_T(32, HTT_VAR_PADDR32(frags_desc_ptr));
  1163. /* define a htt_tx_msdu_desc64_t type */
  1164. TEMPLATE_HTT_TX_MSDU_DESC_T(64, HTT_VAR_PADDR64_LE(frags_desc_ptr));
  1165. /*
  1166. * Make htt_tx_msdu_desc_t be an alias for either
  1167. * htt_tx_msdu_desc32_t or htt_tx_msdu_desc64_t
  1168. */
  1169. #if HTT_PADDR64
  1170. #define htt_tx_msdu_desc_t htt_tx_msdu_desc64_t
  1171. #else
  1172. #define htt_tx_msdu_desc_t htt_tx_msdu_desc32_t
  1173. #endif
  1174. /* decriptor information for Management frame*/
  1175. /*
  1176. * THIS htt_mgmt_tx_desc_t STRUCT IS DEPRECATED - DON'T USE IT.
  1177. * BOTH MANAGEMENT AND DATA FRAMES SHOULD USE htt_tx_msdu_desc_t.
  1178. */
  1179. #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32
  1180. extern A_UINT32 mgmt_hdr_len;
  1181. PREPACK struct htt_mgmt_tx_desc_t {
  1182. A_UINT32 msg_type;
  1183. #if HTT_PADDR64
  1184. A_UINT64 frag_paddr; /* DMAble address of the data */
  1185. #else
  1186. A_UINT32 frag_paddr; /* DMAble address of the data */
  1187. #endif
  1188. A_UINT32 desc_id; /* returned to host during completion
  1189. * to free the meory*/
  1190. A_UINT32 len; /* Fragment length */
  1191. A_UINT32 vdev_id; /* virtual device ID*/
  1192. A_UINT8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; /* frm header */
  1193. } POSTPACK;
  1194. PREPACK struct htt_mgmt_tx_compl_ind {
  1195. A_UINT32 desc_id;
  1196. A_UINT32 status;
  1197. } POSTPACK;
  1198. /*
  1199. * This SDU header size comes from the summation of the following:
  1200. * 1. Max of:
  1201. * a. Native WiFi header, for native WiFi frames: 24 bytes
  1202. * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4)
  1203. * b. 802.11 header, for raw frames: 36 bytes
  1204. * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4,
  1205. * QoS header, HT header)
  1206. * c. 802.3 header, for ethernet frames: 14 bytes
  1207. * (destination address, source address, ethertype / length)
  1208. * 2. Max of:
  1209. * a. IPv4 header, up through the DiffServ Code Point: 2 bytes
  1210. * b. IPv6 header, up through the Traffic Class: 2 bytes
  1211. * 3. 802.1Q VLAN header: 4 bytes
  1212. * 4. LLC/SNAP header: 8 bytes
  1213. */
  1214. #define HTT_TX_HDR_SIZE_NATIVE_WIFI 30
  1215. #define HTT_TX_HDR_SIZE_802_11_RAW 36
  1216. #define HTT_TX_HDR_SIZE_ETHERNET 14
  1217. #define HTT_TX_HDR_SIZE_OUTER_HDR_MAX HTT_TX_HDR_SIZE_802_11_RAW
  1218. A_COMPILE_TIME_ASSERT(
  1219. htt_encap_hdr_size_max_check_nwifi,
  1220. HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_NATIVE_WIFI);
  1221. A_COMPILE_TIME_ASSERT(
  1222. htt_encap_hdr_size_max_check_enet,
  1223. HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_ETHERNET);
  1224. #define HTT_HL_TX_HDR_SIZE_IP 1600 /* also include payload */
  1225. #define HTT_LL_TX_HDR_SIZE_IP 16 /* up to the end of UDP header for IPv4 case */
  1226. #define HTT_TX_HDR_SIZE_802_1Q 4
  1227. #define HTT_TX_HDR_SIZE_LLC_SNAP 8
  1228. #define HTT_COMMON_TX_FRM_HDR_LEN \
  1229. (HTT_TX_HDR_SIZE_OUTER_HDR_MAX + \
  1230. HTT_TX_HDR_SIZE_802_1Q + \
  1231. HTT_TX_HDR_SIZE_LLC_SNAP)
  1232. #define HTT_HL_TX_FRM_HDR_LEN \
  1233. (HTT_COMMON_TX_FRM_HDR_LEN + HTT_HL_TX_HDR_SIZE_IP)
  1234. #define HTT_LL_TX_FRM_HDR_LEN \
  1235. (HTT_COMMON_TX_FRM_HDR_LEN + HTT_LL_TX_HDR_SIZE_IP)
  1236. #define HTT_TX_DESC_LEN sizeof(struct htt_tx_msdu_desc_t)
  1237. /* dword 0 */
  1238. #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_BYTES 0
  1239. #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_DWORD 0
  1240. #define HTT_TX_DESC_PKT_SUBTYPE_M 0x00001f00
  1241. #define HTT_TX_DESC_PKT_SUBTYPE_S 8
  1242. #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_BYTES 0
  1243. #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_DWORD 0
  1244. #define HTT_TX_DESC_NO_ENCRYPT_M 0x00000400
  1245. #define HTT_TX_DESC_NO_ENCRYPT_S 10
  1246. #define HTT_TX_DESC_PKT_TYPE_OFFSET_BYTES 0
  1247. #define HTT_TX_DESC_PKT_TYPE_OFFSET_DWORD 0
  1248. #define HTT_TX_DESC_PKT_TYPE_M 0x0000e000
  1249. #define HTT_TX_DESC_PKT_TYPE_S 13
  1250. #define HTT_TX_DESC_VDEV_ID_OFFSET_BYTES 0
  1251. #define HTT_TX_DESC_VDEV_ID_OFFSET_DWORD 0
  1252. #define HTT_TX_DESC_VDEV_ID_M 0x003f0000
  1253. #define HTT_TX_DESC_VDEV_ID_S 16
  1254. #define HTT_TX_DESC_EXT_TID_OFFSET_BYTES 0
  1255. #define HTT_TX_DESC_EXT_TID_OFFSET_DWORD 0
  1256. #define HTT_TX_DESC_EXT_TID_M 0x07c00000
  1257. #define HTT_TX_DESC_EXT_TID_S 22
  1258. #define HTT_TX_DESC_POSTPONED_OFFSET_BYTES 0
  1259. #define HTT_TX_DESC_POSTPONED_OFFSET_DWORD 0
  1260. #define HTT_TX_DESC_POSTPONED_M 0x08000000
  1261. #define HTT_TX_DESC_POSTPONED_S 27
  1262. #define HTT_TX_DESC_EXTENSION_OFFSET_BYTE 0
  1263. #define HTT_TX_DESC_EXTENSION_OFFSET_DWORD 0
  1264. #define HTT_TX_DESC_EXTENSION_M 0x10000000
  1265. #define HTT_TX_DESC_EXTENSION_S 28
  1266. #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_BYTES 0
  1267. #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_DWORD 0
  1268. #define HTT_TX_DESC_CKSUM_OFFLOAD_M 0x60000000
  1269. #define HTT_TX_DESC_CKSUM_OFFLOAD_S 29
  1270. #define HTT_TX_DESC_TX_COMP_OFFSET_BYTES 0
  1271. #define HTT_TX_DESC_TX_COMP_OFFSET_DWORD 0
  1272. #define HTT_TX_DESC_TX_COMP_M 0x80000000
  1273. #define HTT_TX_DESC_TX_COMP_S 31
  1274. /* dword 1 */
  1275. #define HTT_TX_DESC_FRM_LEN_OFFSET_BYTES 4
  1276. #define HTT_TX_DESC_FRM_LEN_OFFSET_DWORD 1
  1277. #define HTT_TX_DESC_FRM_LEN_M 0x0000ffff
  1278. #define HTT_TX_DESC_FRM_LEN_S 0
  1279. #define HTT_TX_DESC_FRM_ID_OFFSET_BYTES 4
  1280. #define HTT_TX_DESC_FRM_ID_OFFSET_DWORD 1
  1281. #define HTT_TX_DESC_FRM_ID_M 0xffff0000
  1282. #define HTT_TX_DESC_FRM_ID_S 16
  1283. /* dword 2 */
  1284. #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_BYTES 8
  1285. #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_DWORD 2
  1286. /* for systems using 64-bit format for bus addresses */
  1287. #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_M 0xffffffff
  1288. #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_S 0
  1289. #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_M 0xffffffff
  1290. #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_S 0
  1291. /* for systems using 32-bit format for bus addresses */
  1292. #define HTT_TX_DESC_FRAGS_DESC_PADDR_M 0xffffffff
  1293. #define HTT_TX_DESC_FRAGS_DESC_PADDR_S 0
  1294. /* dword 3 */
  1295. #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 16
  1296. #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 12
  1297. #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 \
  1298. (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 >> 2)
  1299. #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 \
  1300. (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 >> 2)
  1301. #if HTT_PADDR64
  1302. #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64
  1303. #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64
  1304. #else
  1305. #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32
  1306. #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32
  1307. #endif
  1308. #define HTT_TX_DESC_PEER_ID_M 0x0000ffff
  1309. #define HTT_TX_DESC_PEER_ID_S 0
  1310. /*
  1311. * TEMPORARY:
  1312. * The original definitions for the PEER_ID fields contained typos
  1313. * (with _DESC_PADDR appended to this PEER_ID field name).
  1314. * Retain deprecated original names for PEER_ID fields until all code that
  1315. * refers to them has been updated.
  1316. */
  1317. #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_BYTES \
  1318. HTT_TX_DESC_PEER_ID_OFFSET_BYTES
  1319. #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_DWORD \
  1320. HTT_TX_DESC_PEER_ID_OFFSET_DWORD
  1321. #define HTT_TX_DESC_PEERID_DESC_PADDR_M \
  1322. HTT_TX_DESC_PEER_ID_M
  1323. #define HTT_TX_DESC_PEERID_DESC_PADDR_S \
  1324. HTT_TX_DESC_PEER_ID_S
  1325. #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 16 /* to dword with chan freq */
  1326. #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 12 /* to dword with chan freq */
  1327. #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 \
  1328. (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 >> 2)
  1329. #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 \
  1330. (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 >> 2)
  1331. #if HTT_PADDR64
  1332. #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64
  1333. #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64
  1334. #else
  1335. #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32
  1336. #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32
  1337. #endif
  1338. #define HTT_TX_DESC_CHAN_FREQ_M 0xffff0000
  1339. #define HTT_TX_DESC_CHAN_FREQ_S 16
  1340. #define HTT_TX_DESC_PKT_SUBTYPE_GET(_var) \
  1341. (((_var) & HTT_TX_DESC_PKT_SUBTYPE_M) >> HTT_TX_DESC_PKT_SUBTYPE_S)
  1342. #define HTT_TX_DESC_PKT_SUBTYPE_SET(_var, _val) \
  1343. do { \
  1344. HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_SUBTYPE, _val); \
  1345. ((_var) |= ((_val) << HTT_TX_DESC_PKT_SUBTYPE_S)); \
  1346. } while (0)
  1347. #define HTT_TX_DESC_NO_ENCRYPT_GET(_var) \
  1348. (((_var) & HTT_TX_DESC_NO_ENCRYPT_M) >> HTT_TX_DESC_NO_ENCRYPT_S)
  1349. #define HTT_TX_DESC_NO_ENCRYPT_SET(_var, _val) \
  1350. do { \
  1351. HTT_CHECK_SET_VAL(HTT_TX_DESC_NO_ENCRYPT, _val); \
  1352. ((_var) |= ((_val) << HTT_TX_DESC_NO_ENCRYPT_S)); \
  1353. } while (0)
  1354. #define HTT_TX_DESC_PKT_TYPE_GET(_var) \
  1355. (((_var) & HTT_TX_DESC_PKT_TYPE_M) >> HTT_TX_DESC_PKT_TYPE_S)
  1356. #define HTT_TX_DESC_PKT_TYPE_SET(_var, _val) \
  1357. do { \
  1358. HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_TYPE, _val); \
  1359. ((_var) |= ((_val) << HTT_TX_DESC_PKT_TYPE_S)); \
  1360. } while (0)
  1361. #define HTT_TX_DESC_VDEV_ID_GET(_var) \
  1362. (((_var) & HTT_TX_DESC_VDEV_ID_M) >> HTT_TX_DESC_VDEV_ID_S)
  1363. #define HTT_TX_DESC_VDEV_ID_SET(_var, _val) \
  1364. do { \
  1365. HTT_CHECK_SET_VAL(HTT_TX_DESC_VDEV_ID, _val); \
  1366. ((_var) |= ((_val) << HTT_TX_DESC_VDEV_ID_S)); \
  1367. } while (0)
  1368. #define HTT_TX_DESC_EXT_TID_GET(_var) \
  1369. (((_var) & HTT_TX_DESC_EXT_TID_M) >> HTT_TX_DESC_EXT_TID_S)
  1370. #define HTT_TX_DESC_EXT_TID_SET(_var, _val) \
  1371. do { \
  1372. HTT_CHECK_SET_VAL(HTT_TX_DESC_EXT_TID, _val); \
  1373. ((_var) |= ((_val) << HTT_TX_DESC_EXT_TID_S)); \
  1374. } while (0)
  1375. #define HTT_TX_DESC_POSTPONED_GET(_var) \
  1376. (((_var) & HTT_TX_DESC_POSTPONED_M) >> HTT_TX_DESC_POSTPONED_S)
  1377. #define HTT_TX_DESC_POSTPONED_SET(_var, _val) \
  1378. do { \
  1379. HTT_CHECK_SET_VAL(HTT_TX_DESC_POSTPONED, _val); \
  1380. ((_var) |= ((_val) << HTT_TX_DESC_POSTPONED_S)); \
  1381. } while (0)
  1382. #define HTT_TX_DESC_EXTENSION_GET(_var) \
  1383. (((_var) & HTT_TX_DESC_EXTENSION_M) >> HTT_TX_DESC_EXTENSION_S)
  1384. #define HTT_TX_DESC_EXTENSION_SET(_var, _val) \
  1385. do { \
  1386. HTT_CHECK_SET_VAL(HTT_TX_DESC_EXTENSION, _val); \
  1387. ((_var) |= ((_val) << HTT_TX_DESC_EXTENSION_S)); \
  1388. } while (0)
  1389. #define HTT_TX_DESC_FRM_LEN_GET(_var) \
  1390. (((_var) & HTT_TX_DESC_FRM_LEN_M) >> HTT_TX_DESC_FRM_LEN_S)
  1391. #define HTT_TX_DESC_FRM_LEN_SET(_var, _val) \
  1392. do { \
  1393. HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_LEN, _val); \
  1394. ((_var) |= ((_val) << HTT_TX_DESC_FRM_LEN_S)); \
  1395. } while (0)
  1396. #define HTT_TX_DESC_FRM_ID_GET(_var) \
  1397. (((_var) & HTT_TX_DESC_FRM_ID_M) >> HTT_TX_DESC_FRM_ID_S)
  1398. #define HTT_TX_DESC_FRM_ID_SET(_var, _val) \
  1399. do { \
  1400. HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_ID, _val); \
  1401. ((_var) |= ((_val) << HTT_TX_DESC_FRM_ID_S)); \
  1402. } while (0)
  1403. #define HTT_TX_DESC_CKSUM_OFFLOAD_GET(_var) \
  1404. (((_var) & HTT_TX_DESC_CKSUM_OFFLOAD_M) >> HTT_TX_DESC_CKSUM_OFFLOAD_S)
  1405. #define HTT_TX_DESC_CKSUM_OFFLOAD_SET(_var, _val) \
  1406. do { \
  1407. HTT_CHECK_SET_VAL(HTT_TX_DESC_CKSUM_OFFLOAD, _val); \
  1408. ((_var) |= ((_val) << HTT_TX_DESC_CKSUM_OFFLOAD_S)); \
  1409. } while (0)
  1410. #define HTT_TX_DESC_TX_COMP_GET(_var) \
  1411. (((_var) & HTT_TX_DESC_TX_COMP_M) >> HTT_TX_DESC_TX_COMP_S)
  1412. #define HTT_TX_DESC_TX_COMP_SET(_var, _val) \
  1413. do { \
  1414. HTT_CHECK_SET_VAL(HTT_TX_DESC_TX_COMP, _val); \
  1415. ((_var) |= ((_val) << HTT_TX_DESC_TX_COMP_S)); \
  1416. } while (0)
  1417. #define HTT_TX_DESC_PEER_ID_GET(_var) \
  1418. (((_var) & HTT_TX_DESC_PEER_ID_M) >> HTT_TX_DESC_PEER_ID_S)
  1419. #define HTT_TX_DESC_PEER_ID_SET(_var, _val) \
  1420. do { \
  1421. HTT_CHECK_SET_VAL(HTT_TX_DESC_PEER_ID, _val); \
  1422. ((_var) |= ((_val) << HTT_TX_DESC_PEER_ID_S)); \
  1423. } while (0)
  1424. #define HTT_TX_DESC_CHAN_FREQ_GET(_var) \
  1425. (((_var) & HTT_TX_DESC_CHAN_FREQ_M) >> HTT_TX_DESC_CHAN_FREQ_S)
  1426. #define HTT_TX_DESC_CHAN_FREQ_SET(_var, _val) \
  1427. do { \
  1428. HTT_CHECK_SET_VAL(HTT_TX_DESC_CHAN_FREQ, _val); \
  1429. ((_var) |= ((_val) << HTT_TX_DESC_CHAN_FREQ_S)); \
  1430. } while (0)
  1431. /* enums used in the HTT tx MSDU extension descriptor */
  1432. enum {
  1433. htt_tx_guard_interval_regular = 0,
  1434. htt_tx_guard_interval_short = 1,
  1435. };
  1436. enum {
  1437. htt_tx_preamble_type_ofdm = 0,
  1438. htt_tx_preamble_type_cck = 1,
  1439. htt_tx_preamble_type_ht = 2,
  1440. htt_tx_preamble_type_vht = 3,
  1441. };
  1442. enum {
  1443. htt_tx_bandwidth_5MHz = 0,
  1444. htt_tx_bandwidth_10MHz = 1,
  1445. htt_tx_bandwidth_20MHz = 2,
  1446. htt_tx_bandwidth_40MHz = 3,
  1447. htt_tx_bandwidth_80MHz = 4,
  1448. htt_tx_bandwidth_160MHz = 5, /* includes 80+80 */
  1449. };
  1450. /**
  1451. * @brief HTT tx MSDU extension descriptor
  1452. * @details
  1453. * If the target supports HTT tx MSDU extension descriptors, the host has
  1454. * the option of appending the following struct following the regular
  1455. * HTT tx MSDU descriptor (and setting the "extension" flag in the regular
  1456. * HTT tx MSDU descriptor, to show that the extension descriptor is present).
  1457. * The HTT tx MSDU extension descriptors allows the host to provide detailed
  1458. * tx specs for each frame.
  1459. */
  1460. PREPACK struct htt_tx_msdu_desc_ext_t {
  1461. /* DWORD 0: flags */
  1462. A_UINT32
  1463. valid_pwr: 1, /* bit 0: if set, tx pwr spec is valid */
  1464. valid_mcs_mask: 1, /* bit 1: if set, tx MCS mask spec is valid */
  1465. valid_nss_mask: 1, /* bit 2: if set, tx Nss mask spec is valid */
  1466. valid_guard_interval: 1, /* bit 3: if set, tx guard intv spec is valid*/
  1467. valid_preamble_type_mask: 1, /* 4: if set, tx preamble mask is valid */
  1468. valid_chainmask: 1, /* bit 5: if set, tx chainmask spec is valid */
  1469. valid_retries: 1, /* bit 6: if set, tx retries spec is valid */
  1470. valid_bandwidth: 1, /* bit 7: if set, tx bandwidth spec is valid */
  1471. valid_expire_tsf: 1, /* bit 8: if set, tx expire TSF spec is valid*/
  1472. is_dsrc: 1, /* bit 9: if set, MSDU is a DSRC frame */
  1473. reserved0_31_7: 22; /* bits 31:10 - unused, set to 0x0 */
  1474. /* DWORD 1: tx power, tx rate, tx BW */
  1475. A_UINT32
  1476. /* pwr -
  1477. * Specify what power the tx frame needs to be transmitted at.
  1478. * The power a signed (two's complement) value is in units of 0.5 dBm.
  1479. * The value needs to be appropriately sign-extended when extracting
  1480. * the value from the message and storing it in a variable that is
  1481. * larger than A_INT8. (The HTT_TX_MSDU_EXT_DESC_FLAG_PWR_GET macro
  1482. * automatically handles this sign-extension.)
  1483. * If the transmission uses multiple tx chains, this power spec is
  1484. * the total transmit power, assuming incoherent combination of
  1485. * per-chain power to produce the total power.
  1486. */
  1487. pwr: 8,
  1488. /* mcs_mask -
  1489. * Specify the allowable values for MCS index (modulation and coding)
  1490. * to use for transmitting the frame.
  1491. *
  1492. * For HT / VHT preamble types, this mask directly corresponds to
  1493. * the HT or VHT MCS indices that are allowed. For each bit N set
  1494. * within the mask, MCS index N is allowed for transmitting the frame.
  1495. * For legacy CCK and OFDM rates, separate bits are provided for CCK
  1496. * rates versus OFDM rates, so the host has the option of specifying
  1497. * that the target must transmit the frame with CCK or OFDM rates
  1498. * (not HT or VHT), but leaving the decision to the target whether
  1499. * to use CCK or OFDM.
  1500. *
  1501. * For CCK and OFDM, the bits within this mask are interpreted as
  1502. * follows:
  1503. * bit 0 -> CCK 1 Mbps rate is allowed
  1504. * bit 1 -> CCK 2 Mbps rate is allowed
  1505. * bit 2 -> CCK 5.5 Mbps rate is allowed
  1506. * bit 3 -> CCK 11 Mbps rate is allowed
  1507. * bit 4 -> OFDM BPSK modulation, 1/2 coding rate is allowed
  1508. * bit 5 -> OFDM BPSK modulation, 3/4 coding rate is allowed
  1509. * bit 6 -> OFDM QPSK modulation, 1/2 coding rate is allowed
  1510. * bit 7 -> OFDM QPSK modulation, 3/4 coding rate is allowed
  1511. * bit 8 -> OFDM 16-QAM modulation, 1/2 coding rate is allowed
  1512. * bit 9 -> OFDM 16-QAM modulation, 3/4 coding rate is allowed
  1513. * bit 10 -> OFDM 64-QAM modulation, 2/3 coding rate is allowed
  1514. * bit 11 -> OFDM 64-QAM modulation, 3/4 coding rate is allowed
  1515. *
  1516. * The MCS index specification needs to be compatible with the
  1517. * bandwidth mask specification. For example, a MCS index == 9
  1518. * specification is inconsistent with a preamble type == VHT,
  1519. * Nss == 1, and channel bandwidth == 20 MHz.
  1520. *
  1521. * Furthermore, the host has only a limited ability to specify to
  1522. * the target to select from HT + legacy rates, or VHT + legacy rates,
  1523. * since this mcs_mask can specify either HT/VHT rates or legacy rates.
  1524. */
  1525. mcs_mask: 12,
  1526. /* nss_mask -
  1527. * Specify which numbers of spatial streams (MIMO factor) are permitted.
  1528. * Each bit in this mask corresponds to a Nss value:
  1529. * bit 0: if set, Nss = 1 (non-MIMO) is permitted
  1530. * bit 1: if set, Nss = 2 (2x2 MIMO) is permitted
  1531. * bit 2: if set, Nss = 3 (3x3 MIMO) is permitted
  1532. * bit 3: if set, Nss = 4 (4x4 MIMO) is permitted
  1533. * The values in the Nss mask must be suitable for the recipient, e.g.
  1534. * a value of 0x4 (Nss = 3) cannot be specified for a tx frame to a
  1535. * recipient which only supports 2x2 MIMO.
  1536. */
  1537. nss_mask: 4,
  1538. /* guard_interval -
  1539. * Specify a htt_tx_guard_interval enum value to indicate whether
  1540. * the transmission should use a regular guard interval or a
  1541. * short guard interval.
  1542. */
  1543. guard_interval: 1,
  1544. /* preamble_type_mask -
  1545. * Specify which preamble types (CCK, OFDM, HT, VHT) the target
  1546. * may choose from for transmitting this frame.
  1547. * The bits in this mask correspond to the values in the
  1548. * htt_tx_preamble_type enum. For example, to allow the target
  1549. * to transmit the frame as either CCK or OFDM, this field would
  1550. * be set to
  1551. * (1 << htt_tx_preamble_type_ofdm) |
  1552. * (1 << htt_tx_preamble_type_cck)
  1553. */
  1554. preamble_type_mask: 4,
  1555. reserved1_31_29: 3; /* unused, set to 0x0 */
  1556. /* DWORD 2: tx chain mask, tx retries */
  1557. A_UINT32
  1558. /* chain_mask - specify which chains to transmit from */
  1559. chain_mask: 4,
  1560. /* retry_limit -
  1561. * Specify the maximum number of transmissions, including the
  1562. * initial transmission, to attempt before giving up if no ack
  1563. * is received.
  1564. * If the tx rate is specified, then all retries shall use the
  1565. * same rate as the initial transmission.
  1566. * If no tx rate is specified, the target can choose whether to
  1567. * retain the original rate during the retransmissions, or to
  1568. * fall back to a more robust rate.
  1569. */
  1570. retry_limit: 4,
  1571. /* bandwidth_mask -
  1572. * Specify what channel widths may be used for the transmission.
  1573. * A value of zero indicates "don't care" - the target may choose
  1574. * the transmission bandwidth.
  1575. * The bits within this mask correspond to the htt_tx_bandwidth
  1576. * enum values - bit 0 is for 5 MHz, bit 1 is for 10 MHz, etc.
  1577. * The bandwidth_mask must be consistent with the preamble_type_mask
  1578. * and mcs_mask specs, if they are provided. For example, 80 MHz and
  1579. * 160 MHz can only be enabled in the mask if preamble_type == VHT.
  1580. */
  1581. bandwidth_mask: 6,
  1582. reserved2_31_14: 18; /* unused, set to 0x0 */
  1583. /* DWORD 3: tx expiry time (TSF) LSBs */
  1584. A_UINT32 expire_tsf_lo;
  1585. /* DWORD 4: tx expiry time (TSF) MSBs */
  1586. A_UINT32 expire_tsf_hi;
  1587. A_UINT32 reserved_for_future_expansion_set_to_zero[3];
  1588. } POSTPACK;
  1589. /* DWORD 0 */
  1590. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M 0x00000001
  1591. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S 0
  1592. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M 0x00000002
  1593. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S 1
  1594. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_M 0x00000004
  1595. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_S 2
  1596. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M 0x00000008
  1597. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S 3
  1598. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M 0x00000010
  1599. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S 4
  1600. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M 0x00000020
  1601. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S 5
  1602. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M 0x00000040
  1603. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S 6
  1604. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M 0x00000080
  1605. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S 7
  1606. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M 0x00000100
  1607. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S 8
  1608. #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M 0x00000200
  1609. #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S 9
  1610. /* DWORD 1 */
  1611. #define HTT_TX_MSDU_EXT_DESC_PWR_M 0x000000ff
  1612. #define HTT_TX_MSDU_EXT_DESC_PWR_S 0
  1613. #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_M 0x000fff00
  1614. #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_S 8
  1615. #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_M 0x00f00000
  1616. #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_S 20
  1617. #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M 0x01000000
  1618. #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S 24
  1619. #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M 0x1c000000
  1620. #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S 25
  1621. /* DWORD 2 */
  1622. #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M 0x0000000f
  1623. #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S 0
  1624. #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M 0x000000f0
  1625. #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S 4
  1626. #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M 0x00003f00
  1627. #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S 8
  1628. /* DWORD 0 */
  1629. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_GET(_var) \
  1630. (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \
  1631. HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S)
  1632. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_SET(_var, _val) \
  1633. do { \
  1634. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR, _val); \
  1635. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S)); \
  1636. } while (0)
  1637. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_GET(_var) \
  1638. (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M) >> \
  1639. HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S)
  1640. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \
  1641. do { \
  1642. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK, _val); \
  1643. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S)); \
  1644. } while (0)
  1645. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \
  1646. (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \
  1647. HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S)
  1648. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \
  1649. do { \
  1650. HTT_CHECK_SET_VAL( \
  1651. HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \
  1652. ((_var) |= ((_val) \
  1653. << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \
  1654. } while (0)
  1655. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_GET(_var) \
  1656. (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M) >> \
  1657. HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S)
  1658. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_SET(_var, _val) \
  1659. do { \
  1660. HTT_CHECK_SET_VAL( \
  1661. HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK, _val); \
  1662. ((_var) |= ((_val) \
  1663. << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S)); \
  1664. } while (0)
  1665. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \
  1666. (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M) >> \
  1667. HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S)
  1668. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \
  1669. do { \
  1670. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK, _val); \
  1671. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S)); \
  1672. } while (0)
  1673. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_GET(_var) \
  1674. (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M) >> \
  1675. HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S)
  1676. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \
  1677. do { \
  1678. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES, _val); \
  1679. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S)); \
  1680. } while (0)
  1681. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_GET(_var) \
  1682. (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M) >> \
  1683. HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S)
  1684. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_SET(_var, _val) \
  1685. do { \
  1686. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH, _val); \
  1687. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S)); \
  1688. } while (0)
  1689. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \
  1690. (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \
  1691. HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S)
  1692. #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \
  1693. do { \
  1694. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME, _val); \
  1695. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S));\
  1696. } while (0)
  1697. #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_GET(_var) \
  1698. (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M) >> \
  1699. HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S)
  1700. #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_SET(_var, _val) \
  1701. do { \
  1702. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC, _val); \
  1703. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S)); \
  1704. } while (0)
  1705. /* DWORD 1 */
  1706. #define HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) \
  1707. (((_var) & HTT_TX_MSDU_EXT_DESC_PWR_M) >> \
  1708. HTT_TX_MSDU_EXT_DESC_PWR_S)
  1709. #define HTT_TX_MSDU_EXT_DESC_PWR_GET(_var) \
  1710. (HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) | \
  1711. HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT_DESC_PWR))
  1712. #define HTT_TX_MSDU_EXT_DESC_PWR_SET(_var, _val) \
  1713. ((_var) |= (((_val) << HTT_TX_MSDU_EXT_DESC_PWR_S)) & \
  1714. HTT_TX_MSDU_EXT_DESC_PWR_M)
  1715. #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_GET(_var) \
  1716. (((_var) & HTT_TX_MSDU_EXT_DESC_MCS_MASK_M) >> \
  1717. HTT_TX_MSDU_EXT_DESC_MCS_MASK_S)
  1718. #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_SET(_var, _val) \
  1719. do { \
  1720. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_MCS_MASK, _val); \
  1721. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_MCS_MASK_S)); \
  1722. } while (0)
  1723. #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_GET(_var) \
  1724. (((_var) & HTT_TX_MSDU_EXT_DESC_NSS_MASK_M) >> \
  1725. HTT_TX_MSDU_EXT_DESC_NSS_MASK_S)
  1726. #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_SET(_var, _val) \
  1727. do { \
  1728. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_NSS_MASK, _val); \
  1729. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_NSS_MASK_S)); \
  1730. } while (0)
  1731. #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_GET(_var) \
  1732. (((_var) & HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M) >> \
  1733. HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S)
  1734. #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_SET(_var, _val) \
  1735. do { \
  1736. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL, _val); \
  1737. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S)); \
  1738. } while (0)
  1739. #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_GET(_var) \
  1740. (((_var) & HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M) >> \
  1741. HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S)
  1742. #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_SET(_var, _val) \
  1743. do { \
  1744. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK, _val); \
  1745. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S)); \
  1746. } while (0)
  1747. /* DWORD 2 */
  1748. #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_GET(_var) \
  1749. (((_var) & HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M) >> \
  1750. HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S)
  1751. #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_SET(_var, _val) \
  1752. do { \
  1753. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_CHAIN_MASK, _val); \
  1754. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S)); \
  1755. } while (0)
  1756. #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_GET(_var) \
  1757. (((_var) & HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M) >> \
  1758. HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S)
  1759. #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_SET(_var, _val) \
  1760. do { \
  1761. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT, _val); \
  1762. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S)); \
  1763. } while (0)
  1764. #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_GET(_var) \
  1765. (((_var) & HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M) >> \
  1766. HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S)
  1767. #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_SET(_var, _val) \
  1768. do { \
  1769. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK, _val); \
  1770. ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S)); \
  1771. } while (0)
  1772. typedef enum {
  1773. HTT_11AX_HE_LTF_SUBTYPE_1X,
  1774. HTT_11AX_HE_LTF_SUBTYPE_2X,
  1775. HTT_11AX_HE_LTF_SUBTYPE_4X,
  1776. } htt_11ax_ltf_subtype_t;
  1777. typedef enum {
  1778. HTT_TX_MSDU_EXT2_DESC_PREAM_OFDM,
  1779. HTT_TX_MSDU_EXT2_DESC_PREAM_CCK,
  1780. HTT_TX_MSDU_EXT2_DESC_PREAM_HT ,
  1781. HTT_TX_MSDU_EXT2_DESC_PREAM_VHT,
  1782. HTT_TX_MSDU_EXT2_DESC_PREAM_HE_SU,
  1783. HTT_TX_MSDU_EXT2_DESC_PREAM_HE_EXT_SU,
  1784. } htt_tx_ext2_preamble_type_t;
  1785. #define HTT_TX_MSDU_EXT2_DESC_BW_5MHZ_M 0x00000001
  1786. #define HTT_TX_MSDU_EXT2_DESC_BW_5MHZ_S 0
  1787. #define HTT_TX_MSDU_EXT2_DESC_BW_10MHZ_M 0x00000002
  1788. #define HTT_TX_MSDU_EXT2_DESC_BW_10MHZ_S 1
  1789. #define HTT_TX_MSDU_EXT2_DESC_BW_20MHZ_M 0x00000004
  1790. #define HTT_TX_MSDU_EXT2_DESC_BW_20MHZ_S 2
  1791. #define HTT_TX_MSDU_EXT2_DESC_BW_40MHZ_M 0x00000008
  1792. #define HTT_TX_MSDU_EXT2_DESC_BW_40MHZ_S 3
  1793. #define HTT_TX_MSDU_EXT2_DESC_BW_80MHZ_M 0x00000010
  1794. #define HTT_TX_MSDU_EXT2_DESC_BW_80MHZ_S 4
  1795. #define HTT_TX_MSDU_EXT2_DESC_BW_160MHZ_M 0x00000020
  1796. #define HTT_TX_MSDU_EXT2_DESC_BW_160MHZ_S 5
  1797. /* Rx buffer addr qdata ctrl pkt */
  1798. struct htt_h2t_rx_buffer_addr_info {
  1799. A_UINT32 buffer_addr_31_0 : 32; // [31:0]
  1800. A_UINT32 buffer_addr_39_32 : 8, // [7:0]
  1801. return_buffer_manager : 4, // [11:8]
  1802. sw_buffer_cookie : 20; // [31:12]
  1803. };
  1804. /**
  1805. * @brief HTT tx MSDU extension descriptor v2
  1806. * @details
  1807. * In Lithium, if htt_tx_tcl_metadata->valid_htt_ext is set, this structure
  1808. * is received as tcl_exit_base->host_meta_info in firmware.
  1809. * Also there is no htt_tx_msdu_desc_t in Lithium since most of those fields
  1810. * are already part of tcl_exit_base.
  1811. */
  1812. PREPACK struct htt_tx_msdu_desc_ext2_t {
  1813. /* DWORD 0: flags */
  1814. A_UINT32
  1815. valid_pwr : 1, /* if set, tx pwr spec is valid */
  1816. valid_mcs_mask : 1, /* if set, tx MCS mask is valid */
  1817. valid_nss_mask : 1, /* if set, tx Nss mask is valid */
  1818. valid_preamble_type : 1, /* if set, tx preamble spec is valid */
  1819. valid_retries : 1, /* if set, tx retries spec is valid */
  1820. valid_bw_info : 1, /* if set, tx dyn_bw and bw_mask are valid */
  1821. valid_guard_interval : 1, /* if set, tx guard intv spec is valid */
  1822. valid_chainmask : 1, /* if set, tx chainmask is valid */
  1823. valid_encrypt_type : 1, /* if set, encrypt type is valid */
  1824. valid_key_flags : 1, /* if set, key flags is valid */
  1825. valid_expire_tsf : 1, /* if set, tx expire TSF spec is valid */
  1826. valid_chanfreq : 1, /* if set, chanfreq is valid */
  1827. is_dsrc : 1, /* if set, MSDU is a DSRC frame */
  1828. guard_interval : 2, /* 0.4us, 0.8us, 1.6us, 3.2us */
  1829. encrypt_type : 2, /* 0 = NO_ENCRYPT,
  1830. 1 = ENCRYPT,
  1831. 2 ~ 3 - Reserved */
  1832. /* retry_limit -
  1833. * Specify the maximum number of transmissions, including the
  1834. * initial transmission, to attempt before giving up if no ack
  1835. * is received.
  1836. * If the tx rate is specified, then all retries shall use the
  1837. * same rate as the initial transmission.
  1838. * If no tx rate is specified, the target can choose whether to
  1839. * retain the original rate during the retransmissions, or to
  1840. * fall back to a more robust rate.
  1841. */
  1842. retry_limit : 4,
  1843. use_dcm_11ax : 1, /* If set, Use Dual subcarrier modulation.
  1844. * Valid only for 11ax preamble types HE_SU
  1845. * and HE_EXT_SU
  1846. */
  1847. ltf_subtype_11ax : 2, /* Takes enum values of htt_11ax_ltf_subtype_t
  1848. * Valid only for 11ax preamble types HE_SU
  1849. * and HE_EXT_SU
  1850. */
  1851. dyn_bw : 1, /* 0 = static bw, 1 = dynamic bw */
  1852. bw_mask : 6, /* Valid only if dyn_bw == 0 (static bw).
  1853. * (Bit mask of 5, 10, 20, 40, 80, 160Mhz.
  1854. * Refer to HTT_TX_MSDU_EXT2_DESC_BW defs.)
  1855. */
  1856. host_tx_desc_pool : 1; /* If set, Firmware allocates tx_descriptors
  1857. * in WAL_BUFFERID_TX_HOST_DATA_EXP,instead
  1858. * of WAL_BUFFERID_TX_TCL_DATA_EXP.
  1859. * Use cases:
  1860. * Any time firmware uses TQM-BYPASS for Data
  1861. * TID, firmware expect host to set this bit.
  1862. */
  1863. /* DWORD 1: tx power, tx rate */
  1864. A_UINT32
  1865. power : 8, /* unit of the power field is 0.5 dbm
  1866. * similar to pwr field in htt_tx_msdu_desc_ext_t
  1867. * signed value ranging from -64dbm to 63.5 dbm
  1868. */
  1869. mcs_mask : 12, /* mcs bit mask of 0 ~ 11
  1870. * Setting more than one MCS isn't currently
  1871. * supported by the target (but is supported
  1872. * in the interface in case in the future
  1873. * the target supports specifications of
  1874. * a limited set of MCS values.
  1875. */
  1876. nss_mask : 8, /* Nss bit mask 0 ~ 7
  1877. * Setting more than one Nss isn't currently
  1878. * supported by the target (but is supported
  1879. * in the interface in case in the future
  1880. * the target supports specifications of
  1881. * a limited set of Nss values.
  1882. */
  1883. pream_type : 3, /* Takes enum values of htt_tx_ext2_preamble_type_t */
  1884. update_peer_cache : 1; /* When set these custom values will be
  1885. * used for all packets, until the next
  1886. * update via this ext header.
  1887. * This is to make sure not all packets
  1888. * need to include this header.
  1889. */
  1890. /* DWORD 2: tx chain mask, tx retries */
  1891. A_UINT32
  1892. /* chain_mask - specify which chains to transmit from */
  1893. chain_mask : 8,
  1894. key_flags : 8, /* Key Index and related flags - used in mesh mode
  1895. * TODO: Update Enum values for key_flags
  1896. */
  1897. /*
  1898. * Channel frequency: This identifies the desired channel
  1899. * frequency (in MHz) for tx frames. This is used by FW to help
  1900. * determine when it is safe to transmit or drop frames for
  1901. * off-channel operation.
  1902. * The default value of zero indicates to FW that the corresponding
  1903. * VDEV's home channel (if there is one) is the desired channel
  1904. * frequency.
  1905. */
  1906. chanfreq : 16;
  1907. /* DWORD 3: tx expiry time (TSF) LSBs */
  1908. A_UINT32 expire_tsf_lo;
  1909. /* DWORD 4: tx expiry time (TSF) MSBs */
  1910. A_UINT32 expire_tsf_hi;
  1911. /* DWORD 5: flags to control routing / processing of the MSDU */
  1912. A_UINT32
  1913. /* learning_frame
  1914. * When this flag is set, this frame will be dropped by FW
  1915. * rather than being enqueued to the Transmit Queue Manager (TQM) HW.
  1916. */
  1917. learning_frame : 1,
  1918. /* send_as_standalone
  1919. * This will indicate if the msdu needs to be sent as a singleton PPDU,
  1920. * i.e. with no A-MSDU or A-MPDU aggregation.
  1921. * The scope is extended to other use-cases.
  1922. */
  1923. send_as_standalone : 1,
  1924. /* is_host_opaque_valid
  1925. * Host should set this bit to 1 if the host_opaque_cookie is populated
  1926. * with valid information.
  1927. */
  1928. is_host_opaque_valid : 1,
  1929. traffic_end_indication: 1,
  1930. rsvd0 : 28;
  1931. /* DWORD 6 : Host opaque cookie for special frames */
  1932. A_UINT32 host_opaque_cookie : 16, /* see is_host_opaque_valid */
  1933. rsvd1 : 16;
  1934. /* DWORD 7-8 : Rx buffer addr for qdata frames */
  1935. struct htt_h2t_rx_buffer_addr_info rx_buffer_addr;
  1936. /*
  1937. * This structure can be expanded further up to 32 bytes
  1938. * by adding further DWORDs as needed.
  1939. */
  1940. } POSTPACK;
  1941. /* DWORD 0 */
  1942. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_M 0x00000001
  1943. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S 0
  1944. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_M 0x00000002
  1945. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S 1
  1946. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_M 0x00000004
  1947. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S 2
  1948. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_M 0x00000008
  1949. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S 3
  1950. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_M 0x00000010
  1951. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S 4
  1952. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_M 0x00000020
  1953. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S 5
  1954. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_M 0x00000040
  1955. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S 6
  1956. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_M 0x00000080
  1957. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S 7
  1958. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_M 0x00000100
  1959. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S 8
  1960. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_M 0x00000200
  1961. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S 9
  1962. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_M 0x00000400
  1963. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S 10
  1964. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_M 0x00000800
  1965. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S 11
  1966. #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_M 0x00001000
  1967. #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S 12
  1968. #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_M 0x00006000
  1969. #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S 13
  1970. #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_M 0x00018000
  1971. #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S 15
  1972. #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_M 0x001e0000
  1973. #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S 17
  1974. #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_M 0x00200000
  1975. #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S 21
  1976. #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_M 0x00c00000
  1977. #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S 22
  1978. #define HTT_TX_MSDU_EXT2_DESC_DYN_BW_M 0x01000000
  1979. #define HTT_TX_MSDU_EXT2_DESC_DYN_BW_S 24
  1980. #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_M 0x7e000000
  1981. #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_S 25
  1982. /* DWORD 1 */
  1983. #define HTT_TX_MSDU_EXT2_DESC_PWR_M 0x000000ff
  1984. #define HTT_TX_MSDU_EXT2_DESC_PWR_S 0
  1985. #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_M 0x000fff00
  1986. #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S 8
  1987. #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_M 0x0ff00000
  1988. #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S 20
  1989. #define HTT_TX_MSDU_EXT2_DESC_PREAM_TYPE_M 0x70000000
  1990. #define HTT_TX_MSDU_EXT2_DESC_PREAM_TYPE_S 28
  1991. #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_M 0x80000000
  1992. #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_S 31
  1993. /* DWORD 2 */
  1994. #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_M 0x000000ff
  1995. #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S 0
  1996. #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_M 0x0000ff00
  1997. #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S 8
  1998. #define HTT_TX_MSDU_EXT_DESC_CHANFREQ_M 0xffff0000
  1999. #define HTT_TX_MSDU_EXT_DESC_CHANFREQ_S 16
  2000. /* DWORD 5 */
  2001. #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_M 0x00000001
  2002. #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S 0
  2003. #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_M 0x00000002
  2004. #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S 1
  2005. #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_M 0x00000004
  2006. #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S 2
  2007. /* DWORD 6 */
  2008. #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_M 0x0000FFFF
  2009. #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S 0
  2010. /* DWORD 0 */
  2011. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_GET(_var) \
  2012. (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \
  2013. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S)
  2014. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_SET(_var, _val) \
  2015. do { \
  2016. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR, _val); \
  2017. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S)); \
  2018. } while (0)
  2019. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_GET(_var) \
  2020. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_M) >> \
  2021. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S)
  2022. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \
  2023. do { \
  2024. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK, _val); \
  2025. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S)); \
  2026. } while (0)
  2027. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_GET(_var) \
  2028. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_M) >> \
  2029. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S)
  2030. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_SET(_var, _val) \
  2031. do { \
  2032. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK, _val); \
  2033. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S)); \
  2034. } while (0)
  2035. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_GET(_var) \
  2036. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_M) >> \
  2037. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S)
  2038. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_SET(_var, _val) \
  2039. do { \
  2040. HTT_CHECK_SET_VAL( \
  2041. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE, _val); \
  2042. ((_var) |= ((_val) \
  2043. << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S)); \
  2044. } while (0)
  2045. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_GET(_var) \
  2046. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_M) >> \
  2047. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S)
  2048. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \
  2049. do { \
  2050. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES, _val); \
  2051. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S)); \
  2052. } while (0)
  2053. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_GET(_var) \
  2054. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_M) >> \
  2055. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S)
  2056. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_SET(_var, _val) \
  2057. do { \
  2058. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO, _val); \
  2059. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S)); \
  2060. } while (0)
  2061. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \
  2062. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \
  2063. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S)
  2064. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \
  2065. do { \
  2066. HTT_CHECK_SET_VAL( \
  2067. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \
  2068. ((_var) |= ((_val) \
  2069. << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \
  2070. } while (0)
  2071. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \
  2072. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_M) >> \
  2073. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S)
  2074. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \
  2075. do { \
  2076. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK, _val); \
  2077. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S)); \
  2078. } while (0)
  2079. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_GET(_var) \
  2080. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_M) >> \
  2081. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S)
  2082. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_SET(_var, _val) \
  2083. do { \
  2084. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE, _val); \
  2085. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S));\
  2086. } while (0)
  2087. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(_var) \
  2088. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_M) >> \
  2089. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S)
  2090. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(_var, _val) \
  2091. do { \
  2092. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS, _val); \
  2093. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S));\
  2094. } while (0)
  2095. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \
  2096. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \
  2097. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S)
  2098. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \
  2099. do { \
  2100. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME, _val); \
  2101. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S));\
  2102. } while (0)
  2103. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_GET(_var) \
  2104. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_M) >> \
  2105. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S)
  2106. #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_SET(_var, _val) \
  2107. do { \
  2108. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ, _val); \
  2109. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S)); \
  2110. } while (0)
  2111. #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_GET(_var) \
  2112. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_M) >> \
  2113. HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S)
  2114. #define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_SET(_var, _val) \
  2115. do { \
  2116. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC, _val); \
  2117. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S)); \
  2118. } while (0)
  2119. #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_GET(_var) \
  2120. (((_var) & HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_M) >> \
  2121. HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S)
  2122. #define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_SET(_var, _val) \
  2123. do { \
  2124. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL, _val); \
  2125. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S)); \
  2126. } while (0)
  2127. #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_GET(_var) \
  2128. (((_var) & HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_M) >> \
  2129. HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S)
  2130. #define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_SET(_var, _val) \
  2131. do { \
  2132. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE, _val); \
  2133. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S)); \
  2134. } while (0)
  2135. #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_GET(_var) \
  2136. (((_var) & HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_M) >> \
  2137. HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S)
  2138. #define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_SET(_var, _val) \
  2139. do { \
  2140. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT, _val); \
  2141. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S)); \
  2142. } while (0)
  2143. #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_GET(_var) \
  2144. (((_var) & HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_M) >> \
  2145. HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S)
  2146. #define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_SET(_var, _val) \
  2147. do { \
  2148. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX, _val); \
  2149. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S)); \
  2150. } while (0)
  2151. #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_GET(_var) \
  2152. (((_var) & HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_M) >> \
  2153. HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S)
  2154. #define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_SET(_var, _val) \
  2155. do { \
  2156. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX, _val); \
  2157. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S)); \
  2158. } while (0)
  2159. #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_GET(_var) \
  2160. (((_var) & HTT_TX_MSDU_EXT2_DESC_BW_MASK_M) >> \
  2161. HTT_TX_MSDU_EXT2_DESC_BW_MASK_S)
  2162. #define HTT_TX_MSDU_EXT2_DESC_BW_MASK_SET(_var, _val) \
  2163. do { \
  2164. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_BW_MASK, _val); \
  2165. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_BW_MASK_S)); \
  2166. } while (0)
  2167. #define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_GET(_var) \
  2168. (((_var) & HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_M) >> \
  2169. HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S)
  2170. #define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_SET(_var, _val) \
  2171. do { \
  2172. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK, _val); \
  2173. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S)); \
  2174. } while (0)
  2175. /* DWORD 1 */
  2176. #define HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) \
  2177. (((_var) & HTT_TX_MSDU_EXT2_DESC_PWR_M) >> \
  2178. HTT_TX_MSDU_EXT2_DESC_PWR_S)
  2179. #define HTT_TX_MSDU_EXT2_DESC_PWR_GET(_var) \
  2180. (HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) | \
  2181. HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT2_DESC_PWR))
  2182. #define HTT_TX_MSDU_EXT2_DESC_PWR_SET(_var, _val) \
  2183. ((_var) |= (((_val) << HTT_TX_MSDU_EXT2_DESC_PWR_S)) & \
  2184. HTT_TX_MSDU_EXT2_DESC_PWR_M)
  2185. #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_GET(_var) \
  2186. (((_var) & HTT_TX_MSDU_EXT2_DESC_MCS_MASK_M) >> \
  2187. HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S)
  2188. #define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_SET(_var, _val) \
  2189. do { \
  2190. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_MCS_MASK, _val); \
  2191. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S)); \
  2192. } while (0)
  2193. #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_GET(_var) \
  2194. (((_var) & HTT_TX_MSDU_EXT2_DESC_NSS_MASK_M) >> \
  2195. HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S)
  2196. #define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_SET(_var, _val) \
  2197. do { \
  2198. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_NSS_MASK, _val); \
  2199. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S)); \
  2200. } while (0)
  2201. #define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_GET(_var) \
  2202. (((_var) & HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_M) >> \
  2203. HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S)
  2204. #define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_SET(_var, _val) \
  2205. do { \
  2206. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE, _val); \
  2207. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S)); \
  2208. } while (0)
  2209. #define HTT_TX_MSDU_EXT2_DESC_UPDATE_PEER_CACHE_GET(_var) \
  2210. (((_var) & HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_M) >> \
  2211. HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_S)
  2212. #define HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_SET(_var, _val) \
  2213. do { \
  2214. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE, _val); \
  2215. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_UPDATE_PEER_CACHE_S)); \
  2216. } while (0)
  2217. /* DWORD 2 */
  2218. #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_GET(_var) \
  2219. (((_var) & HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_M) >> \
  2220. HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S)
  2221. #define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_SET(_var, _val) \
  2222. do { \
  2223. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK, _val); \
  2224. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S)); \
  2225. } while (0)
  2226. #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_GET(_var) \
  2227. (((_var) & HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_MASK_M) >> \
  2228. HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S)
  2229. #define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_SET(_var, _val) \
  2230. do { \
  2231. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS, _val); \
  2232. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S)); \
  2233. } while (0)
  2234. #define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_GET(_var) \
  2235. (((_var) & HTT_TX_MSDU_EXT2_DESC_CHANFREQ_MASK_M) >> \
  2236. HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S)
  2237. #define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_SET(_var, _val) \
  2238. do { \
  2239. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHANFREQ, _val); \
  2240. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S)); \
  2241. } while (0)
  2242. /* DWORD 5 */
  2243. #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_GET(_var) \
  2244. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_M) >> \
  2245. HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S)
  2246. #define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_SET(_var, _val) \
  2247. do { \
  2248. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME, _val); \
  2249. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S)); \
  2250. } while (0)
  2251. #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_GET(_var) \
  2252. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_M) >> \
  2253. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S)
  2254. #define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET(_var, _val) \
  2255. do { \
  2256. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE, _val); \
  2257. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S)); \
  2258. } while (0)
  2259. #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_GET(_var) \
  2260. (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_M) >> \
  2261. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S)
  2262. #define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET(_var, _val) \
  2263. do { \
  2264. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID, _val); \
  2265. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S)); \
  2266. } while (0)
  2267. /* DWORD 6 */
  2268. #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_GET(_var) \
  2269. (((_var) & HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_M) >> \
  2270. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S)
  2271. #define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET(_var, _val) \
  2272. do { \
  2273. HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE, _val); \
  2274. ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S)); \
  2275. } while (0)
  2276. /* DWORD 7 */
  2277. #define HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_M 0xFFFFFFFF
  2278. #define HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_S 0
  2279. #define HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_SET(word, value) \
  2280. do { \
  2281. HTT_CHECK_SET_VAL(HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0, value); \
  2282. (word) |= (value) << HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_S; \
  2283. } while (0)
  2284. #define HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_GET(word) \
  2285. (((word) & HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_M) >> HTT_RX_BUFFER_ADDR_INFO_ADDR_31_0_S)
  2286. /* DWORD 8 */
  2287. #define HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_M 0x000000FF
  2288. #define HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_S 0
  2289. #define HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_SET(word, value) \
  2290. do { \
  2291. HTT_CHECK_SET_VAL(HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32, value); \
  2292. (word) |= (value) << HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_S; \
  2293. } while (0)
  2294. #define HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_GET(word) \
  2295. (((word) & HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_M) >> HTT_RX_BUFFER_ADDR_INFO_ADDR_39_32_S)
  2296. #define HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_M 0x00000F00
  2297. #define HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_S 8
  2298. #define HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_SET(word, value) \
  2299. do { \
  2300. HTT_CHECK_SET_VAL(HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER, value); \
  2301. (word) |= (value) << HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_S; \
  2302. } while (0)
  2303. #define HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_GET(word) \
  2304. (((word) & HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_M) >> HTT_RX_BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_S)
  2305. #define HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M 0xFFFFF000
  2306. #define HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S 12
  2307. #define HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_SET(word, value) \
  2308. do { \
  2309. HTT_CHECK_SET_VAL(HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE, value); \
  2310. (word) |= (value) << HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S; \
  2311. } while (0)
  2312. #define HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_GET(word) \
  2313. (((word) & HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M) >> HTT_RX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S)
  2314. typedef enum {
  2315. HTT_TCL_METADATA_TYPE_PEER_BASED = 0,
  2316. HTT_TCL_METADATA_TYPE_VDEV_BASED = 1,
  2317. } htt_tcl_metadata_type;
  2318. /**
  2319. * @brief HTT TCL command number format
  2320. * @details
  2321. * This structure is passed from host as tcl_data_cmd->tcl_cmd_number and
  2322. * available to firmware as tcl_exit_base->tcl_status_number.
  2323. * For regular / multicast packets host will send vdev and mac id and for
  2324. * NAWDS packets, host will send peer id.
  2325. * A_UINT32 is used to avoid endianness conversion problems.
  2326. * tcl_status_number size is 16 bits, hence only 16 bits can be used.
  2327. */
  2328. typedef struct {
  2329. A_UINT32
  2330. type: 1, /* vdev_id based or peer_id based */
  2331. rsvd: 31;
  2332. } htt_tx_tcl_vdev_or_peer_t;
  2333. typedef struct {
  2334. A_UINT32
  2335. type: 1, /* vdev_id based or peer_id based */
  2336. valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */
  2337. vdev_id: 8,
  2338. pdev_id: 2,
  2339. host_inspected:1,
  2340. opt_dp_ctrl: 1, /* 1 -> qdata consent pkt */
  2341. rsvd: 18;
  2342. } htt_tx_tcl_vdev_metadata;
  2343. typedef struct {
  2344. A_UINT32
  2345. type: 1, /* vdev_id based or peer_id based */
  2346. valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */
  2347. peer_id: 14,
  2348. rsvd: 16;
  2349. } htt_tx_tcl_peer_metadata;
  2350. PREPACK struct htt_tx_tcl_metadata {
  2351. union {
  2352. htt_tx_tcl_vdev_or_peer_t vdev_or_peer;
  2353. htt_tx_tcl_vdev_metadata vdev_meta;
  2354. htt_tx_tcl_peer_metadata peer_meta;
  2355. };
  2356. } POSTPACK;
  2357. /* DWORD 0 */
  2358. #define HTT_TX_TCL_METADATA_TYPE_M 0x00000001
  2359. #define HTT_TX_TCL_METADATA_TYPE_S 0
  2360. #define HTT_TX_TCL_METADATA_VALID_HTT_M 0x00000002
  2361. #define HTT_TX_TCL_METADATA_VALID_HTT_S 1
  2362. /* VDEV metadata */
  2363. #define HTT_TX_TCL_METADATA_VDEV_ID_M 0x000003fc
  2364. #define HTT_TX_TCL_METADATA_VDEV_ID_S 2
  2365. #define HTT_TX_TCL_METADATA_PDEV_ID_M 0x00000c00
  2366. #define HTT_TX_TCL_METADATA_PDEV_ID_S 10
  2367. #define HTT_TX_TCL_METADATA_HOST_INSPECTED_M 0x00001000
  2368. #define HTT_TX_TCL_METADATA_HOST_INSPECTED_S 12
  2369. #define HTT_TX_TCL_METADATA_OPT_DP_CTRL_M 0x00002000
  2370. #define HTT_TX_TCL_METADATA_OPT_DP_CTRL_S 13
  2371. /* PEER metadata */
  2372. #define HTT_TX_TCL_METADATA_PEER_ID_M 0x0000fffc
  2373. #define HTT_TX_TCL_METADATA_PEER_ID_S 2
  2374. #define HTT_TX_TCL_METADATA_TYPE_GET(_var) \
  2375. (((_var) & HTT_TX_TCL_METADATA_TYPE_M) >> \
  2376. HTT_TX_TCL_METADATA_TYPE_S)
  2377. #define HTT_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  2378. do { \
  2379. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE, _val); \
  2380. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_S)); \
  2381. } while (0)
  2382. #define HTT_TX_TCL_METADATA_VALID_HTT_GET(_var) \
  2383. (((_var) & HTT_TX_TCL_METADATA_VALID_HTT_M) >> \
  2384. HTT_TX_TCL_METADATA_VALID_HTT_S)
  2385. #define HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  2386. do { \
  2387. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VALID_HTT, _val); \
  2388. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VALID_HTT_S)); \
  2389. } while (0)
  2390. #define HTT_TX_TCL_METADATA_VDEV_ID_GET(_var) \
  2391. (((_var) & HTT_TX_TCL_METADATA_VDEV_ID_M) >> \
  2392. HTT_TX_TCL_METADATA_VDEV_ID_S)
  2393. #define HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  2394. do { \
  2395. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VDEV_ID, _val); \
  2396. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VDEV_ID_S)); \
  2397. } while (0)
  2398. #define HTT_TX_TCL_METADATA_PDEV_ID_GET(_var) \
  2399. (((_var) & HTT_TX_TCL_METADATA_PDEV_ID_M) >> \
  2400. HTT_TX_TCL_METADATA_PDEV_ID_S)
  2401. #define HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val) \
  2402. do { \
  2403. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PDEV_ID, _val); \
  2404. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PDEV_ID_S)); \
  2405. } while (0)
  2406. #define HTT_TX_TCL_METADATA_HOST_INSPECTED_GET(_var) \
  2407. (((_var) & HTT_TX_TCL_METADATA_HOST_INSPECTED_M) >> \
  2408. HTT_TX_TCL_METADATA_HOST_INSPECTED_S)
  2409. #define HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  2410. do { \
  2411. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_HOST_INSPECTED, _val); \
  2412. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_HOST_INSPECTED_S)); \
  2413. } while (0)
  2414. #define HTT_TX_TCL_METADATA_PEER_ID_GET(_var) \
  2415. (((_var) & HTT_TX_TCL_METADATA_PEER_ID_M) >> \
  2416. HTT_TX_TCL_METADATA_PEER_ID_S)
  2417. #define HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  2418. do { \
  2419. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PEER_ID, _val); \
  2420. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PEER_ID_S)); \
  2421. } while (0)
  2422. #define HTT_TX_TCL_METADATA_OPT_DP_CTRL_GET(_var) \
  2423. (((_var) & HTT_TX_TCL_METADATA_OPT_DP_CTRL_M) >> \
  2424. HTT_TX_TCL_METADATA_OPT_DP_CTRL_S)
  2425. #define HTT_TX_TCL_METADATA_OPT_DP_CTRL_SET(_var, _val) \
  2426. do { \
  2427. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_OPT_DP_CTRL, _val); \
  2428. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_OPT_DP_CTRL_S)); \
  2429. } while (0)
  2430. /*------------------------------------------------------------------
  2431. * V2 Version of TCL Data Command
  2432. * V2 Version to support peer_id, vdev_id, svc_class_id and
  2433. * MLO global_seq all flavours of TCL Data Cmd.
  2434. *-----------------------------------------------------------------*/
  2435. typedef enum {
  2436. HTT_TCL_METADATA_V2_TYPE_PEER_BASED = 0,
  2437. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED = 1,
  2438. HTT_TCL_METADATA_V2_TYPE_SVC_ID_BASED = 2,
  2439. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED = 3,
  2440. } htt_tcl_metadata_type_v2;
  2441. /**
  2442. * @brief HTT TCL command number format
  2443. * @details
  2444. * This structure is passed from host as tcl_data_cmd->tcl_cmd_number and
  2445. * available to firmware as tcl_exit_base->tcl_status_number.
  2446. * A_UINT32 is used to avoid endianness conversion problems.
  2447. * tcl_status_number size is 16 bits, hence only 16 bits can be used.
  2448. */
  2449. typedef struct {
  2450. A_UINT32
  2451. type: 2, /* vdev_id based or peer_id or svc_id or global seq based */
  2452. valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */
  2453. vdev_id: 8,
  2454. pdev_id: 2,
  2455. host_inspected:1,
  2456. rsvd: 2,
  2457. padding: 16; /* These 16 bits cannot be used by FW for the tcl command */
  2458. } htt_tx_tcl_vdev_metadata_v2;
  2459. typedef struct {
  2460. A_UINT32
  2461. type: 2, /* vdev_id based or peer_id or svc_id or global seq based */
  2462. valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */
  2463. peer_id: 13,
  2464. padding: 16; /* These 16 bits cannot be used by FW for the tcl command */
  2465. } htt_tx_tcl_peer_metadata_v2;
  2466. typedef struct {
  2467. A_UINT32
  2468. type: 2, /* vdev_id based or peer_id or svc_id or global seq based */
  2469. valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */
  2470. svc_class_id: 8,
  2471. ast_index: 3, /* Indicates to firmware the AST index to be used for Pine for AST Override */
  2472. rsvd: 2,
  2473. padding: 16; /* These 16 bits cannot be used by FW for the tcl command */
  2474. } htt_tx_tcl_svc_class_id_metadata;
  2475. typedef struct {
  2476. A_UINT32
  2477. type: 2, /* vdev_id based or peer_id or svc_id or global seq based */
  2478. host_inspected: 1,
  2479. global_seq_no: 12,
  2480. htt_ext_present:1,
  2481. padding: 16; /* These 16 bits cannot be used by FW for the tcl command */
  2482. } htt_tx_tcl_global_seq_metadata;
  2483. PREPACK struct htt_tx_tcl_metadata_v2 {
  2484. union {
  2485. htt_tx_tcl_vdev_metadata_v2 vdev_meta_v2;
  2486. htt_tx_tcl_peer_metadata_v2 peer_meta_v2;
  2487. htt_tx_tcl_svc_class_id_metadata svc_class_id_meta;
  2488. htt_tx_tcl_global_seq_metadata global_seq_meta;
  2489. };
  2490. } POSTPACK;
  2491. /* DWORD 0 */
  2492. #define HTT_TX_TCL_METADATA_TYPE_V2_M 0x00000003
  2493. #define HTT_TX_TCL_METADATA_TYPE_V2_S 0
  2494. /* Valid htt ext for V2 tcl data cmd used by VDEV, PEER and SVC_ID meta */
  2495. #define HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_M 0x00000004
  2496. #define HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S 2
  2497. /* VDEV V2 metadata */
  2498. #define HTT_TX_TCL_METADATA_V2_VDEV_ID_M 0x000007f8
  2499. #define HTT_TX_TCL_METADATA_V2_VDEV_ID_S 3
  2500. #define HTT_TX_TCL_METADATA_V2_PDEV_ID_M 0x00001800
  2501. #define HTT_TX_TCL_METADATA_V2_PDEV_ID_S 11
  2502. #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_M 0x00002000
  2503. #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S 13
  2504. /* PEER V2 metadata */
  2505. #define HTT_TX_TCL_METADATA_V2_PEER_ID_M 0x0000fff8
  2506. #define HTT_TX_TCL_METADATA_V2_PEER_ID_S 3
  2507. /* SVC_CLASS_ID metadata */
  2508. #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_M 0x000007f8
  2509. #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_S 3
  2510. /* Global Seq no metadata */
  2511. #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_M 0x00000004
  2512. #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S 2
  2513. #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_M 0x00007ff8
  2514. #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S 3
  2515. /* HTT ext present flag:
  2516. * Specify whether there is a htt ext desc present for this packet,
  2517. * accompanying the global seq no metadata.
  2518. */
  2519. #define HTT_TX_TCL_METADATA_GLBL_SEQ_HTT_EXT_PRESENT_M 0x00008000
  2520. #define HTT_TX_TCL_METADATA_GLBL_SEQ_HTT_EXT_PRESENT_S 15
  2521. /*----- Get and Set V2 type field in Vdev, Peer, Svc_Class_Id, Global_seq_no */
  2522. #define HTT_TX_TCL_METADATA_TYPE_V2_GET(_var) \
  2523. (((_var) & HTT_TX_TCL_METADATA_TYPE_V2_M) >> \
  2524. HTT_TX_TCL_METADATA_TYPE_V2_S)
  2525. #define HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val) \
  2526. do { \
  2527. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE_V2, _val); \
  2528. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_V2_S)); \
  2529. } while (0)
  2530. #define HTT_TX_TCL_METADATA_V2_VALID_HTT_GET(_var) \
  2531. (((_var) & HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_M) >> \
  2532. HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S)
  2533. #define HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val) \
  2534. do { \
  2535. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID, _val); \
  2536. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_VALID_HTT_EXT_ID_S)); \
  2537. } while (0)
  2538. /*----- Get and Set V2 type field in Vdev meta fields ----*/
  2539. #define HTT_TX_TCL_METADATA_V2_VDEV_ID_GET(_var) \
  2540. (((_var) & HTT_TX_TCL_METADATA_V2_VDEV_ID_M) >> \
  2541. HTT_TX_TCL_METADATA_V2_VDEV_ID_S)
  2542. #define HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val) \
  2543. do { \
  2544. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_VDEV_ID, _val); \
  2545. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_VDEV_ID_S)); \
  2546. } while (0)
  2547. #define HTT_TX_TCL_METADATA_V2_PDEV_ID_GET(_var) \
  2548. (((_var) & HTT_TX_TCL_METADATA_V2_PDEV_ID_M) >> \
  2549. HTT_TX_TCL_METADATA_V2_PDEV_ID_S)
  2550. #define HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val) \
  2551. do { \
  2552. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_PDEV_ID, _val); \
  2553. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_PDEV_ID_S)); \
  2554. } while (0)
  2555. #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_GET(_var) \
  2556. (((_var) & HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_M) >> \
  2557. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S)
  2558. #define HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val) \
  2559. do { \
  2560. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_HOST_INSPECTED, _val); \
  2561. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_S)); \
  2562. } while (0)
  2563. /*----- Get and Set V2 type field in Peer meta fields ----*/
  2564. #define HTT_TX_TCL_METADATA_V2_PEER_ID_GET(_var) \
  2565. (((_var) & HTT_TX_TCL_METADATA_V2_PEER_ID_M) >> \
  2566. HTT_TX_TCL_METADATA_V2_PEER_ID_S)
  2567. #define HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val) \
  2568. do { \
  2569. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V2_PEER_ID, _val); \
  2570. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V2_PEER_ID_S)); \
  2571. } while (0)
  2572. /*----- Get and Set V2 type field in Service Class fields ----*/
  2573. #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_GET(_var) \
  2574. (((_var) & HTT_TX_TCL_METADATA_SVC_CLASS_ID_M) >> \
  2575. HTT_TX_TCL_METADATA_SVC_CLASS_ID_S)
  2576. #define HTT_TX_TCL_METADATA_SVC_CLASS_ID_SET(_var, _val) \
  2577. do { \
  2578. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_SVC_CLASS_ID, _val); \
  2579. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_SVC_CLASS_ID_S)); \
  2580. } while (0)
  2581. /*----- Get and Set V2 type field in Global sequence fields ----*/
  2582. #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_GET(_var) \
  2583. (((_var) & HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_M) >> \
  2584. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S)
  2585. #define HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(_var, _val) \
  2586. do { \
  2587. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED, _val); \
  2588. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_S)); \
  2589. } while (0)
  2590. #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_GET(_var) \
  2591. (((_var) & HTT_TX_TCL_METADATA_GLBL_SEQ_NO_M) >> \
  2592. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S)
  2593. #define HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(_var, _val) \
  2594. do { \
  2595. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_GLBL_SEQ_NO, _val); \
  2596. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_GLBL_SEQ_NO_S)); \
  2597. } while (0)
  2598. #define HTT_TX_TCL_METADATA_GLBL_SEQ_HTT_EXT_PRESENT_GET(_var) \
  2599. (((_var) & HTT_TX_TCL_METADATA_GLBL_SEQ_HTT_EXT_PRESENT_M) >> \
  2600. HTT_TX_TCL_METADATA_GLBL_SEQ_HTT_EXT_PRESENT_S)
  2601. #define HTT_TX_TCL_METADATA_GLBL_SEQ_HTT_EXT_PRESENT_SET(_var, _val) \
  2602. do { \
  2603. HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_GLBL_SEQ_HTT_EXT_PRESENT, _val); \
  2604. ((_var) |= ((_val) << HTT_TX_TCL_METADATA_GLBL_SEQ_HTT_EXT_PRESENT_S)); \
  2605. } while (0)
  2606. /*------------------------------------------------------------------
  2607. * End V2 Version of TCL Data Command
  2608. *-----------------------------------------------------------------*/
  2609. typedef enum {
  2610. HTT_TX_FW2WBM_TX_STATUS_OK,
  2611. HTT_TX_FW2WBM_TX_STATUS_DROP,
  2612. HTT_TX_FW2WBM_TX_STATUS_TTL,
  2613. HTT_TX_FW2WBM_TX_STATUS_REINJECT,
  2614. HTT_TX_FW2WBM_TX_STATUS_INSPECT,
  2615. HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY,
  2616. HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH,
  2617. HTT_TX_FW2WBM_TX_STATUS_MAX
  2618. } htt_tx_fw2wbm_tx_status_t;
  2619. typedef enum {
  2620. HTT_TX_FW2WBM_REINJECT_REASON_EAPOL_ENCAP_EXP, /* deprecated */
  2621. HTT_TX_FW2WBM_REINJECT_REASON_RAW_ENCAP_EXP /* current */ =
  2622. HTT_TX_FW2WBM_REINJECT_REASON_EAPOL_ENCAP_EXP,
  2623. HTT_TX_FW2WBM_REINJECT_REASON_INJECT_VIA_EXP,
  2624. HTT_TX_FW2WBM_REINJECT_REASON_MCAST,
  2625. HTT_TX_FW2WBM_REINJECT_REASON_ARP,
  2626. HTT_TX_FW2WBM_REINJECT_REASON_DHCP,
  2627. HTT_TX_FW2WBM_REINJECT_REASON_FLOW_CONTROL,
  2628. HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST,
  2629. HTT_TX_FW2WBM_REINJECT_REASON_SAWF_SVC_CLASS_ID_ABSENT,
  2630. HTT_TX_FW2WBM_REINJECT_REASON_OPT_DP_CTRL, /* tx qdata packet */
  2631. HTT_TX_FW2WBM_REINJECT_REASON_MAX,
  2632. } htt_tx_fw2wbm_reinject_reason_t;
  2633. /**
  2634. * @brief HTT TX WBM Completion from firmware to host
  2635. * @details
  2636. * This structure is passed from firmware to host overlaid on wbm_release_ring
  2637. * DWORD 3 and 4 for software based completions (Exception frames and
  2638. * TQM bypass frames)
  2639. * For software based completions, wbm_release_ring->release_source_module will
  2640. * be set to release_source_fw
  2641. */
  2642. PREPACK struct htt_tx_wbm_completion {
  2643. A_UINT32
  2644. sch_cmd_id: 24,
  2645. exception_frame: 1, /* If set, this packet was queued via exception path */
  2646. rsvd0_31_25: 7;
  2647. A_UINT32
  2648. ack_frame_rssi: 8, /* If this frame is removed as the result of the
  2649. * reception of an ACK or BA, this field indicates
  2650. * the RSSI of the received ACK or BA frame.
  2651. * When the frame is removed as result of a direct
  2652. * remove command from the SW, this field is set
  2653. * to 0x0 (which is never a valid value when real
  2654. * RSSI is available).
  2655. * Units: dB w.r.t noise floor
  2656. */
  2657. tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */
  2658. reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */
  2659. rsvd1_31_16: 16;
  2660. } POSTPACK;
  2661. /* DWORD 0 */
  2662. #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_M 0x00ffffff
  2663. #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S 0
  2664. #define HTT_TX_WBM_COMPLETION_EXP_FRAME_M 0x01000000
  2665. #define HTT_TX_WBM_COMPLETION_EXP_FRAME_S 24
  2666. /* DWORD 1 */
  2667. #define HTT_TX_WBM_COMPLETION_ACK_RSSI_M 0x000000ff
  2668. #define HTT_TX_WBM_COMPLETION_ACK_RSSI_S 0
  2669. #define HTT_TX_WBM_COMPLETION_TX_STATUS_M 0x00000f00
  2670. #define HTT_TX_WBM_COMPLETION_TX_STATUS_S 8
  2671. #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_M 0x0000f000
  2672. #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_S 12
  2673. /* DWORD 0 */
  2674. #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_GET(_var) \
  2675. (((_var) & HTT_TX_WBM_COMPLETION_SCH_CMD_ID_M) >> \
  2676. HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S)
  2677. #define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_SET(_var, _val) \
  2678. do { \
  2679. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_SCH_CMD_ID, _val); \
  2680. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S)); \
  2681. } while (0)
  2682. #define HTT_TX_WBM_COMPLETION_EXP_FRAME_GET(_var) \
  2683. (((_var) & HTT_TX_WBM_COMPLETION_EXP_FRAME_M) >> \
  2684. HTT_TX_WBM_COMPLETION_EXP_FRAME_S)
  2685. #define HTT_TX_WBM_COMPLETION_EXP_FRAME_SET(_var, _val) \
  2686. do { \
  2687. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_EXP_FRAME, _val); \
  2688. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_EXP_FRAME_S)); \
  2689. } while (0)
  2690. /* DWORD 1 */
  2691. #define HTT_TX_WBM_COMPLETION_ACK_RSSI_GET(_var) \
  2692. (((_var) & HTT_TX_WBM_COMPLETION_ACK_RSSI_M) >> \
  2693. HTT_TX_WBM_COMPLETION_ACK_RSSI_S)
  2694. #define HTT_TX_WBM_COMPLETION_ACK_RSSI_SET(_var, _val) \
  2695. do { \
  2696. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_ACK_RSSI, _val); \
  2697. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_ACK_RSSI_S)); \
  2698. } while (0)
  2699. #define HTT_TX_WBM_COMPLETION_TX_STATUS_GET(_var) \
  2700. (((_var) & HTT_TX_WBM_COMPLETION_TX_STATUS_M) >> \
  2701. HTT_TX_WBM_COMPLETION_TX_STATUS_S)
  2702. #define HTT_TX_WBM_COMPLETION_TX_STATUS_SET(_var, _val) \
  2703. do { \
  2704. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_TX_STATUS, _val); \
  2705. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_TX_STATUS_S)); \
  2706. } while (0)
  2707. #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_GET(_var) \
  2708. (((_var) & HTT_TX_WBM_COMPLETION_REINJECT_REASON_M) >> \
  2709. HTT_TX_WBM_COMPLETION_REINJECT_REASON_S)
  2710. #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_SET(_var, _val) \
  2711. do { \
  2712. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_REINJECT_REASON, _val); \
  2713. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_REINJECT_REASON_S)); \
  2714. } while (0)
  2715. /**
  2716. * @brief HTT TX WBM Completion from firmware to host
  2717. * @details
  2718. * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
  2719. * (WBM) offload HW.
  2720. * This structure is passed from firmware to host overlaid on wbm_release_ring
  2721. * For software based completions, release_source_module will
  2722. * be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using
  2723. * struct wbm_release_ring and then switch to this after looking at
  2724. * release_source_module.
  2725. */
  2726. PREPACK struct htt_tx_wbm_completion_v2 {
  2727. A_UINT32
  2728. used_by_hw0; /* Refer to struct wbm_release_ring */
  2729. A_UINT32
  2730. used_by_hw1; /* Refer to struct wbm_release_ring */
  2731. A_UINT32
  2732. used_by_hw2: 9, /* Refer to struct wbm_release_ring */
  2733. tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */
  2734. reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */
  2735. exception_frame: 1,
  2736. transmit_count: 7, /* Refer to struct wbm_release_ring */
  2737. rsvd0: 5, /* For future use */
  2738. used_by_hw4: 1, /* wbm_internal_error bit being used by HW */
  2739. rsvd1: 1; /* For future use */
  2740. A_UINT32
  2741. data0: 32; /* data0,1 and 2 changes based on tx_status type
  2742. * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP
  2743. * or HTT_TX_FW2WBM_TX_STATUS_TTL, struct htt_tx_wbm_transmit_status will be used.
  2744. * if HTT_TX_FW2WBM_TX_STATUS_REINJECT, struct htt_tx_wbm_reinject_status will be used.
  2745. * if HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, struct htt_tx_wbm_mec_addr_notify will be used.
  2746. */
  2747. A_UINT32
  2748. data1: 32;
  2749. A_UINT32
  2750. data2: 32;
  2751. A_UINT32
  2752. used_by_hw3; /* Refer to struct wbm_release_ring */
  2753. } POSTPACK;
  2754. /* DWORD 1, 2 and part of 3 are accessed via HW header files */
  2755. /* DWORD 3 */
  2756. #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_M 0x00001e00
  2757. #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S 9
  2758. #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_M 0x0001e000
  2759. #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S 13
  2760. #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M 0x00020000
  2761. #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S 17
  2762. #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M 0x01FC0000
  2763. #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S 18
  2764. /* DWORD 3 */
  2765. #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(_var) \
  2766. (((_var) & HTT_TX_WBM_COMPLETION_V2_TX_STATUS_M) >> \
  2767. HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S)
  2768. #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_SET(_var, _val) \
  2769. do { \
  2770. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TX_STATUS, _val); \
  2771. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TX_STATUS_S)); \
  2772. } while (0)
  2773. #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_GET(_var) \
  2774. (((_var) & HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_M) >> \
  2775. HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S)
  2776. #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_SET(_var, _val) \
  2777. do { \
  2778. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON, _val); \
  2779. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S)); \
  2780. } while (0)
  2781. #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_GET(_var) \
  2782. (((_var) & HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M) >> \
  2783. HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)
  2784. #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_SET(_var, _val) \
  2785. do { \
  2786. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_EXP_FRAME, _val); \
  2787. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)); \
  2788. } while (0)
  2789. #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(_var) \
  2790. (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M) >> \
  2791. HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)
  2792. #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_SET(_var, _val) \
  2793. do { \
  2794. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT, _val); \
  2795. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)); \
  2796. } while (0)
  2797. /**
  2798. * @brief HTT TX WBM Completion from firmware to host (V3)
  2799. * @details
  2800. * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
  2801. * (WBM) offload HW.
  2802. * This structure is passed from firmware to host overlaid on wbm_release_ring
  2803. * For software based completions, release_source_module will
  2804. * be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using
  2805. * struct wbm_release_ring and then switch to this after looking at
  2806. * release_source_module.
  2807. * Due to overlap with WBM block, htt_tx_wbm_completion_v3 will be used
  2808. * by new generations of targets.
  2809. */
  2810. PREPACK struct htt_tx_wbm_completion_v3 {
  2811. A_UINT32
  2812. used_by_hw0; /* Refer to struct wbm_release_ring */
  2813. A_UINT32
  2814. used_by_hw1; /* Refer to struct wbm_release_ring */
  2815. A_UINT32
  2816. used_by_hw2: 13, /* Refer to struct wbm_release_ring */
  2817. tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */
  2818. used_by_hw3: 15;
  2819. A_UINT32
  2820. reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */
  2821. exception_frame: 1,
  2822. transmit_count: 7, /* Refer to struct wbm_release_ring */
  2823. rsvd0: 20; /* For future use */
  2824. A_UINT32
  2825. data0: 32; /* data0,1 and 2 changes based on tx_status type
  2826. * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP
  2827. * or HTT_TX_FW2WBM_TX_STATUS_TTL, struct htt_tx_wbm_transmit_status will be used.
  2828. * if HTT_TX_FW2WBM_TX_STATUS_REINJECT, struct htt_tx_wbm_reinject_status will be used.
  2829. * if HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, struct htt_tx_wbm_mec_addr_notify will be used.
  2830. */
  2831. A_UINT32
  2832. data1: 32;
  2833. A_UINT32
  2834. data2: 32;
  2835. A_UINT32
  2836. rsvd1: 20,
  2837. used_by_hw4: 12; /* Refer to struct wbm_release_ring */
  2838. } POSTPACK;
  2839. /* DWORD 3 */
  2840. #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M 0x0001E000
  2841. #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S 13
  2842. /* DWORD 4 */
  2843. #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M 0x0000000F
  2844. #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S 0
  2845. #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M 0x00000010
  2846. #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S 4
  2847. #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M 0x00000FE0
  2848. #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S 5
  2849. #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(_var) \
  2850. (((_var) & HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M) >> \
  2851. HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S)
  2852. #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_SET(_var, _val) \
  2853. do { \
  2854. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TX_STATUS, _val); \
  2855. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S)); \
  2856. } while (0)
  2857. #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_GET(_var) \
  2858. (((_var) & HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M) >> \
  2859. HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S)
  2860. #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_SET(_var, _val) \
  2861. do { \
  2862. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON, _val); \
  2863. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S)); \
  2864. } while (0)
  2865. #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_GET(_var) \
  2866. (((_var) & HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M) >> \
  2867. HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)
  2868. #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_SET(_var, _val) \
  2869. do { \
  2870. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_EXP_FRAME, _val); \
  2871. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)); \
  2872. } while (0)
  2873. #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(_var) \
  2874. (((_var) & HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M) >> \
  2875. HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)
  2876. #define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_SET(_var, _val) \
  2877. do { \
  2878. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT, _val); \
  2879. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)); \
  2880. } while (0)
  2881. typedef enum {
  2882. TX_FRAME_TYPE_UNDEFINED = 0,
  2883. TX_FRAME_TYPE_EAPOL = 1,
  2884. } htt_tx_wbm_status_frame_type;
  2885. /**
  2886. * @brief HTT TX WBM transmit status from firmware to host
  2887. * @details
  2888. * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
  2889. * (WBM) offload HW.
  2890. * This structure is passed from firmware to host overlaid on wbm_release_ring.
  2891. * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP
  2892. * or HTT_TX_FW2WBM_TX_STATUS_TTL
  2893. */
  2894. PREPACK struct htt_tx_wbm_transmit_status {
  2895. A_UINT32
  2896. sch_cmd_id: 24,
  2897. ack_frame_rssi: 8; /* If this frame is removed as the result of the
  2898. * reception of an ACK or BA, this field indicates
  2899. * the RSSI of the received ACK or BA frame.
  2900. * When the frame is removed as result of a direct
  2901. * remove command from the SW, this field is set
  2902. * to 0x0 (which is never a valid value when real
  2903. * RSSI is available).
  2904. * Units: dB w.r.t noise floor
  2905. */
  2906. A_UINT32
  2907. sw_peer_id: 16,
  2908. tid_num: 5,
  2909. valid: 1, /* If this "valid" flag is set, the sw_peer_id
  2910. * and tid_num fields contain valid data.
  2911. * If this "valid" flag is not set, the
  2912. * sw_peer_id and tid_num fields must be ignored.
  2913. */
  2914. mcast: 1,
  2915. mcast_valid: 1, /* If this "mcast_valid" is set, the mcast field
  2916. * contains valid data.
  2917. */
  2918. frame_type: 4, /* holds htt_tx_wbm_status_frame_type value */
  2919. transmit_count_valid: 1, /* If this "transmit_count_valid" is set, the
  2920. * transmit_count field in struct
  2921. * htt_tx_wbm_completion_vx has valid data.
  2922. */
  2923. reserved: 3;
  2924. A_UINT32
  2925. ppdu_start_tsf: 32; /* PPDU Start timestamp added for multicast
  2926. * packets in the wbm completion path
  2927. */
  2928. } POSTPACK;
  2929. /* DWORD 4 */
  2930. #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_M 0x00ffffff
  2931. #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S 0
  2932. #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_M 0xff000000
  2933. #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S 24
  2934. /* DWORD 5 */
  2935. #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_M 0x0000ffff
  2936. #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S 0
  2937. #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_M 0x001f0000
  2938. #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_S 16
  2939. #define HTT_TX_WBM_COMPLETION_V2_VALID_M 0x00200000
  2940. #define HTT_TX_WBM_COMPLETION_V2_VALID_S 21
  2941. #define HTT_TX_WBM_COMPLETION_V2_MCAST_M 0x00400000
  2942. #define HTT_TX_WBM_COMPLETION_V2_MCAST_S 22
  2943. #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M 0x00800000
  2944. #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S 23
  2945. #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M 0x0F000000
  2946. #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S 24
  2947. #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M 0x10000000
  2948. #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S 28
  2949. /* DWORD 4 */
  2950. #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var) \
  2951. (((_var) & HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_M) >> \
  2952. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S)
  2953. #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_SET(_var, _val) \
  2954. do { \
  2955. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID, _val); \
  2956. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_S)); \
  2957. } while (0)
  2958. #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(_var) \
  2959. (((_var) & HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_M) >> \
  2960. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S)
  2961. #define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_SET(_var, _val) \
  2962. do { \
  2963. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI, _val); \
  2964. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S)); \
  2965. } while (0)
  2966. /* DWORD 5 */
  2967. #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(_var) \
  2968. (((_var) & HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_M) >> \
  2969. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S)
  2970. #define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_SET(_var, _val) \
  2971. do { \
  2972. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID, _val); \
  2973. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S)); \
  2974. } while (0)
  2975. #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(_var) \
  2976. (((_var) & HTT_TX_WBM_COMPLETION_V2_TID_NUM_M) >> \
  2977. HTT_TX_WBM_COMPLETION_V2_TID_NUM_S)
  2978. #define HTT_TX_WBM_COMPLETION_V2_TID_NUM_SET(_var, _val) \
  2979. do { \
  2980. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TID_NUM, _val); \
  2981. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TID_NUM_S)); \
  2982. } while (0)
  2983. #define HTT_TX_WBM_COMPLETION_V2_VALID_GET(_var) \
  2984. (((_var) & HTT_TX_WBM_COMPLETION_V2_VALID_M) >> \
  2985. HTT_TX_WBM_COMPLETION_V2_VALID_S)
  2986. #define HTT_TX_WBM_COMPLETION_V2_VALID_SET(_var, _val) \
  2987. do { \
  2988. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_VALID, _val); \
  2989. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_VALID_S)); \
  2990. } while (0)
  2991. #define HTT_TX_WBM_COMPLETION_V2_MCAST_GET(_var) \
  2992. (((_var) & HTT_TX_WBM_COMPLETION_V2_MCAST_M) >> \
  2993. HTT_TX_WBM_COMPLETION_V2_MCAST_S)
  2994. #define HTT_TX_WBM_COMPLETION_V2_MCAST_SET(_var, _val) \
  2995. do { \
  2996. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST, _val); \
  2997. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_S)); \
  2998. } while (0)
  2999. #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_GET(_var) \
  3000. (((_var) & HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M) >> \
  3001. HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)
  3002. #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_SET(_var, _val) \
  3003. do { \
  3004. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \
  3005. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)); \
  3006. } while (0)
  3007. #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_GET(_var) \
  3008. (((_var) & HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M) >> \
  3009. HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)
  3010. #define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_SET(_var, _val) \
  3011. do { \
  3012. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE, _val); \
  3013. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)); \
  3014. #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var) \
  3015. (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M) >> \
  3016. HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)
  3017. #define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_SET(_var, _val) \
  3018. do { \
  3019. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \
  3020. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)); \
  3021. } while (0)
  3022. /**
  3023. * @brief HTT TX WBM reinject status from firmware to host
  3024. * @details
  3025. * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
  3026. * (WBM) offload HW.
  3027. * This structure is passed from firmware to host overlaid on wbm_release_ring.
  3028. * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_REINJECT.
  3029. */
  3030. PREPACK struct htt_tx_wbm_reinject_status {
  3031. A_UINT32
  3032. sw_peer_id : 16,
  3033. data_length : 16;
  3034. A_UINT32
  3035. tid : 5,
  3036. msduq_idx : 4,
  3037. reserved1 : 23;
  3038. A_UINT32
  3039. reserved2: 32;
  3040. } POSTPACK;
  3041. #define HTT_TX_WBM_REINJECT_SW_PEER_ID_M 0x0000ffff
  3042. #define HTT_TX_WBM_REINJECT_SW_PEER_ID_S 0
  3043. #define HTT_TX_WBM_REINJECT_DATA_LEN_M 0xffff0000
  3044. #define HTT_TX_WBM_REINJECT_DATA_LEN_S 16
  3045. #define HTT_TX_WBM_REINJECT_TID_M 0x0000001f
  3046. #define HTT_TX_WBM_REINJECT_TID_S 0
  3047. #define HTT_TX_WBM_REINJECT_MSDUQ_ID_M 0x000001e0
  3048. #define HTT_TX_WBM_REINJECT_MSDUQ_ID_S 5
  3049. #define HTT_TX_WBM_REINJECT_SW_PEER_ID_GET(_var)\
  3050. (((_var) & HTT_TX_WBM_REINJECT_SW_PEER_ID_M) >>\
  3051. HTT_TX_WBM_REINJECT_SW_PEER_ID_S)\
  3052. #define HTT_TX_WBM_REINJECT_SW_PEER_ID_SET(_var, _val)\
  3053. do {\
  3054. HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_SW_PEER_ID, _val); \
  3055. ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_SW_PEER_ID_S));\
  3056. } while(0)
  3057. #define HTT_TX_WBM_REINJECT_DATA_LEN_GET(_var)\
  3058. (((_var) & HTT_TX_WBM_REINJECT_DATA_LEN_M) >>\
  3059. HTT_TX_WBM_REINJECT_DATA_LEN_S)\
  3060. #define HTT_TX_WBM_REINJECT_DATA_LEN_SET(_var, _val)\
  3061. do {\
  3062. HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_DATA_LEN, _val); \
  3063. ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_DATA_LEN_S));\
  3064. } while(0)
  3065. #define HTT_TX_WBM_REINJECT_TID_GET(_var)\
  3066. (((_var) & HTT_TX_WBM_REINJECT_TID_M) >>\
  3067. HTT_TX_WBM_REINJECT_TID_S)\
  3068. #define HTT_TX_WBM_REINJECT_TID_SET(_var, _val)\
  3069. do {\
  3070. HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_TID, _val); \
  3071. ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_TID_S));\
  3072. } while(0)
  3073. #define HTT_TX_WBM_REINJECT_MSDUQ_ID_GET(_var)\
  3074. (((_var) & HTT_TX_WBM_REINJECT_MSDUQ_ID_M) >>\
  3075. HTT_TX_WBM_REINJECT_MSDUQ_ID_S)\
  3076. #define HTT_TX_WBM_REINJECT_MSDUQ_ID_SET(_var, _val)\
  3077. do {\
  3078. HTT_CHECK_SET_VAL(HTT_TX_WBM_REINJECT_MSDUQ_ID, _val); \
  3079. ((_var) |= ((_val) << HTT_TX_WBM_REINJECT_MSDUQ_ID_S));\
  3080. } while(0)
  3081. /**
  3082. * @brief HTT TX WBM multicast echo check notification from firmware to host
  3083. * @details
  3084. * This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
  3085. * (WBM) offload HW.
  3086. * This structure is passed from firmware to host overlaid on wbm_release_ring.
  3087. * used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY.
  3088. * FW sends SA addresses to host for all multicast/broadcast packets received on
  3089. * STA side.
  3090. */
  3091. PREPACK struct htt_tx_wbm_mec_addr_notify {
  3092. A_UINT32
  3093. mec_sa_addr_31_0;
  3094. A_UINT32
  3095. mec_sa_addr_47_32: 16,
  3096. sa_ast_index: 16;
  3097. A_UINT32
  3098. vdev_id: 8,
  3099. reserved0: 24;
  3100. } POSTPACK;
  3101. /* DWORD 4 - mec_sa_addr_31_0 */
  3102. /* DWORD 5 */
  3103. #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_M 0x0000ffff
  3104. #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S 0
  3105. #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_M 0xffff0000
  3106. #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S 16
  3107. /* DWORD 6 */
  3108. #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_M 0x000000ff
  3109. #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S 0
  3110. #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_GET(_var) \
  3111. (((_var) & HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_M) >> \
  3112. HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S)
  3113. #define HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_SET(_var, _val) \
  3114. do { \
  3115. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32, _val); \
  3116. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MEC_SA_ADDR_47_32_S)); \
  3117. } while (0)
  3118. #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_GET(_var) \
  3119. (((_var) & HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_M) >> \
  3120. HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S)
  3121. #define HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_SET(_var, _val) \
  3122. do { \
  3123. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX, _val); \
  3124. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SA_AST_INDEX_S)); \
  3125. } while (0)
  3126. #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(_var) \
  3127. (((_var) & HTT_TX_WBM_COMPLETION_V2_VDEV_ID_M) >> \
  3128. HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S)
  3129. #define HTT_TX_WBM_COMPLETION_V2_VDEV_ID_SET(_var, _val) \
  3130. do { \
  3131. HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_VDEV_ID, _val); \
  3132. ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_VDEV_ID_S)); \
  3133. } while (0)
  3134. typedef enum {
  3135. TX_FLOW_PRIORITY_BE,
  3136. TX_FLOW_PRIORITY_HIGH,
  3137. TX_FLOW_PRIORITY_LOW,
  3138. } htt_tx_flow_priority_t;
  3139. typedef enum {
  3140. TX_FLOW_LATENCY_SENSITIVE,
  3141. TX_FLOW_LATENCY_INSENSITIVE,
  3142. } htt_tx_flow_latency_t;
  3143. typedef enum {
  3144. TX_FLOW_BEST_EFFORT_TRAFFIC,
  3145. TX_FLOW_INTERACTIVE_TRAFFIC,
  3146. TX_FLOW_PERIODIC_TRAFFIC,
  3147. TX_FLOW_BURSTY_TRAFFIC,
  3148. TX_FLOW_OVER_SUBSCRIBED_TRAFFIC,
  3149. } htt_tx_flow_traffic_pattern_t;
  3150. /**
  3151. * @brief HTT TX Flow search metadata format
  3152. * @details
  3153. * Host will set this metadata in flow table's flow search entry along with
  3154. * to_tqm_if_m0_fw. It indicates to forward the first MSDU to both the
  3155. * firmware and TQM ring if the flow search entry wins.
  3156. * This metadata is available to firmware in that first MSDU's
  3157. * tcl_exit_base->meta_data_fse. Firmware uses this metadata to map a new flow
  3158. * to one of the available flows for specific tid and returns the tqm flow
  3159. * pointer as part of htt_tx_map_flow_info message.
  3160. */
  3161. PREPACK struct htt_tx_flow_metadata {
  3162. A_UINT32
  3163. rsvd0_1_0: 2,
  3164. tid: 4,
  3165. priority: 3, /* Takes enum values of htt_tx_flow_priority_t */
  3166. traffic_pattern: 3, /* Takes enum values of htt_tx_flow_traffic_pattern_t */
  3167. tid_override: 1, /* If set, tid field in this struct is the final tid.
  3168. * Else choose final tid based on latency, priority.
  3169. */
  3170. dedicated_flowq: 1, /* Dedicated flowq per 5 tuple flow. */
  3171. latency_sensitive: 2, /* Takes enum values of htt_tx_flow_latency_t */
  3172. host_flow_identifier: 16; /* Used by host to map flow metadata with flow entry */
  3173. } POSTPACK;
  3174. /* DWORD 0 */
  3175. #define HTT_TX_FLOW_METADATA_TID_M 0x0000003c
  3176. #define HTT_TX_FLOW_METADATA_TID_S 2
  3177. #define HTT_TX_FLOW_METADATA_PRIORITY_M 0x000001c0
  3178. #define HTT_TX_FLOW_METADATA_PRIORITY_S 6
  3179. #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_M 0x00000e00
  3180. #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S 9
  3181. #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_M 0x00001000
  3182. #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_S 12
  3183. #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_M 0x00002000
  3184. #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S 13
  3185. #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_M 0x0000c000
  3186. #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_S 14
  3187. #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_M 0xffff0000
  3188. #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S 16
  3189. /* DWORD 0 */
  3190. #define HTT_TX_FLOW_METADATA_TID_GET(_var) \
  3191. (((_var) & HTT_TX_FLOW_METADATA_TID_M) >> \
  3192. HTT_TX_FLOW_METADATA_TID_S)
  3193. #define HTT_TX_FLOW_METADATA_TID_SET(_var, _val) \
  3194. do { \
  3195. HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID, _val); \
  3196. ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_S)); \
  3197. } while (0)
  3198. #define HTT_TX_FLOW_METADATA_PRIORITY_GET(_var) \
  3199. (((_var) & HTT_TX_FLOW_PRIORITY_M) >> \
  3200. HTT_TX_FLOW_METADATA_PRIORITY_S)
  3201. #define HTT_TX_FLOW_METADATA_PRIORITY_SET(_var, _val) \
  3202. do { \
  3203. HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_PRIORITY, _val); \
  3204. ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_PRIORITY_S)); \
  3205. } while (0)
  3206. #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_GET(_var) \
  3207. (((_var) & HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_M) >> \
  3208. HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S)
  3209. #define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_SET(_var, _val) \
  3210. do { \
  3211. HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN, _val); \
  3212. ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S)); \
  3213. } while (0)
  3214. #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_GET(_var) \
  3215. (((_var) & HTT_TX_FLOW_METADATA_TID_OVERRIDE_M) >> \
  3216. HTT_TX_FLOW_METADATA_TID_OVERRIDE_S)
  3217. #define HTT_TX_FLOW_METADATA_TID_OVERRIDE_SET(_var, _val) \
  3218. do { \
  3219. HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID_OVERRIDE, _val); \
  3220. ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_OVERRIDE_S)); \
  3221. } while (0)
  3222. #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_GET(_var) \
  3223. (((_var) & HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_M) >> \
  3224. HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S)
  3225. #define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_SET(_var, _val) \
  3226. do { \
  3227. HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ, _val); \
  3228. ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S)); \
  3229. } while (0)
  3230. #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_GET(_var) \
  3231. (((_var) & HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_M) >> \
  3232. HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_S)
  3233. #define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_SET(_var, _val) \
  3234. do { \
  3235. HTT_CHECK_SET_VAL(HTT_TX_FLOW_LATENCY_SENSITIVE, _val); \
  3236. ((_var) |= ((_val) << HTT_TX_FLOW_LATENCY_SENSITIVE_S)); \
  3237. } while (0)
  3238. #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_GET(_var) \
  3239. (((_var) & HTT_TX_FLOW_METADATA_HOST_FLOW_ID_M) >> \
  3240. HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S)
  3241. #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_SET(_var, _val) \
  3242. do { \
  3243. HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_HOST_FLOW_ID, _val); \
  3244. ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S)); \
  3245. } while (0)
  3246. /**
  3247. * @brief host -> target ADD WDS Entry
  3248. *
  3249. * MSG_TYPE => HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY
  3250. *
  3251. * @brief host -> target DELETE WDS Entry
  3252. *
  3253. * MSG_TYPE => HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY
  3254. *
  3255. * @details
  3256. * HTT wds entry from source port learning
  3257. * Host will learn wds entries from rx and send this message to firmware
  3258. * to enable firmware to configure/delete AST entries for wds clients.
  3259. * Firmware creates Source address's AST entry with Transmit MAC's peer_id
  3260. * and when SA's entry is deleted, firmware removes this AST entry
  3261. *
  3262. * The message would appear as follows:
  3263. *
  3264. * |31 30|29 |17 16|15 8|7 0|
  3265. * |----------------+----------------+----------------+----------------|
  3266. * | rsvd0 |PDVID| vdev_id | msg_type |
  3267. * |-------------------------------------------------------------------|
  3268. * | sa_addr_31_0 |
  3269. * |-------------------------------------------------------------------|
  3270. * | | ta_peer_id | sa_addr_47_32 |
  3271. * |-------------------------------------------------------------------|
  3272. * Where PDVID = pdev_id
  3273. *
  3274. * The message is interpreted as follows:
  3275. *
  3276. * dword0 - b'0:7 - msg_type: This will be set to
  3277. * 0xd (HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY) or
  3278. * 0xe (HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY)
  3279. *
  3280. * dword0 - b'8:15 - vdev_id
  3281. *
  3282. * dword0 - b'16:17 - pdev_id
  3283. *
  3284. * dword0 - b'18:31 - rsvd10: Reserved for future use
  3285. *
  3286. * dword1 - b'0:31 - sa_addr_31_0: Lower 32 bits of source mac address
  3287. *
  3288. * dword2 - b'0:15 - sa_addr_47_32: Upper 16 bits of source mac address
  3289. *
  3290. * dword2 - b'16:19 - ta_peer_id: peer id of Transmit MAC
  3291. */
  3292. PREPACK struct htt_wds_entry {
  3293. A_UINT32
  3294. msg_type: 8,
  3295. vdev_id: 8,
  3296. pdev_id: 2,
  3297. rsvd0: 14;
  3298. A_UINT32 sa_addr_31_0;
  3299. A_UINT32
  3300. sa_addr_47_32: 16,
  3301. ta_peer_id: 14,
  3302. rsvd2: 2;
  3303. } POSTPACK;
  3304. /* DWORD 0 */
  3305. #define HTT_WDS_ENTRY_VDEV_ID_M 0x0000ff00
  3306. #define HTT_WDS_ENTRY_VDEV_ID_S 8
  3307. #define HTT_WDS_ENTRY_PDEV_ID_M 0x00030000
  3308. #define HTT_WDS_ENTRY_PDEV_ID_S 16
  3309. /* DWORD 2 */
  3310. #define HTT_WDS_ENTRY_SA_ADDR_47_32_M 0x0000ffff
  3311. #define HTT_WDS_ENTRY_SA_ADDR_47_32_S 0
  3312. #define HTT_WDS_ENTRY_TA_PEER_ID_M 0x3fff0000
  3313. #define HTT_WDS_ENTRY_TA_PEER_ID_S 16
  3314. /* DWORD 0 */
  3315. #define HTT_WDS_ENTRY_VDEV_ID_GET(_var) \
  3316. (((_var) & HTT_WDS_ENTRY_VDEV_ID_M) >> \
  3317. HTT_WDS_ENTRY_VDEV_ID_S)
  3318. #define HTT_WDS_ENTRY_VDEV_ID_SET(_var, _val) \
  3319. do { \
  3320. HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_VDEV_ID, _val); \
  3321. ((_var) |= ((_val) << HTT_WDS_ENTRY_VDEV_ID_S)); \
  3322. } while (0)
  3323. #define HTT_WDS_ENTRY_PDEV_ID_GET(_var) \
  3324. (((_var) & HTT_WDS_ENTRY_PDEV_ID_M) >> \
  3325. HTT_WDS_ENTRY_PDEV_ID_S)
  3326. #define HTT_WDS_ENTRY_PDEV_ID_SET(_var, _val) \
  3327. do { \
  3328. HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_PDEV_ID, _val); \
  3329. ((_var) |= ((_val) << HTT_WDS_ENTRY_PDEV_ID_S)); \
  3330. } while (0)
  3331. /* DWORD 2 */
  3332. #define HTT_WDS_ENTRY_SA_ADDR_47_32_GET(_var) \
  3333. (((_var) & HTT_WDS_ENTRY_SA_ADDR_47_32_M) >> \
  3334. HTT_WDS_ENTRY_SA_ADDR_47_32_S)
  3335. #define HTT_WDS_ENTRY_SA_ADDR_47_32_SET(_var, _val) \
  3336. do { \
  3337. HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_SA_ADDR_47_32, _val); \
  3338. ((_var) |= ((_val) << HTT_WDS_ENTRY_SA_ADDR_47_32_S)); \
  3339. } while (0)
  3340. #define HTT_WDS_ENTRY_TA_PEER_ID_GET(_var) \
  3341. (((_var) & HTT_WDS_ENTRY_TA_PEER_ID_M) >> \
  3342. HTT_WDS_ENTRY_TA_PEER_ID_S)
  3343. #define HTT_WDS_ENTRY_TA_PEER_ID_SET(_var, _val) \
  3344. do { \
  3345. HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_TA_PEER_ID, _val); \
  3346. ((_var) |= ((_val) << HTT_WDS_ENTRY_TA_PEER_ID_S)); \
  3347. } while (0)
  3348. /**
  3349. * @brief MAC DMA rx ring setup specification
  3350. *
  3351. * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_RING_CFG
  3352. *
  3353. * @details
  3354. * To allow for dynamic rx ring reconfiguration and to avoid race
  3355. * conditions, the host SW never directly programs the MAC DMA rx ring(s)
  3356. * it uses. Instead, it sends this message to the target, indicating how
  3357. * the rx ring used by the host should be set up and maintained.
  3358. * The message consists of a 4-octet header followed by 1 or 2 rx ring setup
  3359. * specifications.
  3360. *
  3361. * |31 16|15 8|7 0|
  3362. * |---------------------------------------------------------------|
  3363. * header: | reserved | num rings | msg type |
  3364. * |---------------------------------------------------------------|
  3365. * payload 1: | FW_IDX shadow register physical address (bits 31:0) |
  3366. #if HTT_PADDR64
  3367. * | FW_IDX shadow register physical address (bits 63:32) |
  3368. #endif
  3369. * |---------------------------------------------------------------|
  3370. * | rx ring base physical address (bits 31:0) |
  3371. #if HTT_PADDR64
  3372. * | rx ring base physical address (bits 63:32) |
  3373. #endif
  3374. * |---------------------------------------------------------------|
  3375. * | rx ring buffer size | rx ring length |
  3376. * |---------------------------------------------------------------|
  3377. * | FW_IDX initial value | enabled flags |
  3378. * |---------------------------------------------------------------|
  3379. * | MSDU payload offset | 802.11 header offset |
  3380. * |---------------------------------------------------------------|
  3381. * | PPDU end offset | PPDU start offset |
  3382. * |---------------------------------------------------------------|
  3383. * | MPDU end offset | MPDU start offset |
  3384. * |---------------------------------------------------------------|
  3385. * | MSDU end offset | MSDU start offset |
  3386. * |---------------------------------------------------------------|
  3387. * | frag info offset | rx attention offset |
  3388. * |---------------------------------------------------------------|
  3389. * payload 2, if present, has the same format as payload 1
  3390. * Header fields:
  3391. * - MSG_TYPE
  3392. * Bits 7:0
  3393. * Purpose: identifies this as an rx ring configuration message
  3394. * Value: 0x2 (HTT_H2T_MSG_TYPE_RX_RING_CFG)
  3395. * - NUM_RINGS
  3396. * Bits 15:8
  3397. * Purpose: indicates whether the host is setting up one rx ring or two
  3398. * Value: 1 or 2
  3399. * Payload:
  3400. * for systems using 64-bit format for bus addresses:
  3401. * - IDX_SHADOW_REG_PADDR_LO
  3402. * Bits 31:0
  3403. * Value: lower 4 bytes of physical address of the host's
  3404. * FW_IDX shadow register
  3405. * - IDX_SHADOW_REG_PADDR_HI
  3406. * Bits 31:0
  3407. * Value: upper 4 bytes of physical address of the host's
  3408. * FW_IDX shadow register
  3409. * - RING_BASE_PADDR_LO
  3410. * Bits 31:0
  3411. * Value: lower 4 bytes of physical address of the host's rx ring
  3412. * - RING_BASE_PADDR_HI
  3413. * Bits 31:0
  3414. * Value: uppper 4 bytes of physical address of the host's rx ring
  3415. * for systems using 32-bit format for bus addresses:
  3416. * - IDX_SHADOW_REG_PADDR
  3417. * Bits 31:0
  3418. * Value: physical address of the host's FW_IDX shadow register
  3419. * - RING_BASE_PADDR
  3420. * Bits 31:0
  3421. * Value: physical address of the host's rx ring
  3422. * - RING_LEN
  3423. * Bits 15:0
  3424. * Value: number of elements in the rx ring
  3425. * - RING_BUF_SZ
  3426. * Bits 31:16
  3427. * Value: size of the buffers referenced by the rx ring, in byte units
  3428. * - ENABLED_FLAGS
  3429. * Bits 15:0
  3430. * Value: 1-bit flags to show whether different rx fields are enabled
  3431. * bit 0: 802.11 header enabled (1) or disabled (0)
  3432. * bit 1: MSDU payload enabled (1) or disabled (0)
  3433. * bit 2: PPDU start enabled (1) or disabled (0)
  3434. * bit 3: PPDU end enabled (1) or disabled (0)
  3435. * bit 4: MPDU start enabled (1) or disabled (0)
  3436. * bit 5: MPDU end enabled (1) or disabled (0)
  3437. * bit 6: MSDU start enabled (1) or disabled (0)
  3438. * bit 7: MSDU end enabled (1) or disabled (0)
  3439. * bit 8: rx attention enabled (1) or disabled (0)
  3440. * bit 9: frag info enabled (1) or disabled (0)
  3441. * bit 10: unicast rx enabled (1) or disabled (0)
  3442. * bit 11: multicast rx enabled (1) or disabled (0)
  3443. * bit 12: ctrl rx enabled (1) or disabled (0)
  3444. * bit 13: mgmt rx enabled (1) or disabled (0)
  3445. * bit 14: null rx enabled (1) or disabled (0)
  3446. * bit 15: phy data rx enabled (1) or disabled (0)
  3447. * - IDX_INIT_VAL
  3448. * Bits 31:16
  3449. * Purpose: Specify the initial value for the FW_IDX.
  3450. * Value: the number of buffers initially present in the host's rx ring
  3451. * - OFFSET_802_11_HDR
  3452. * Bits 15:0
  3453. * Value: offset in QUAD-bytes of 802.11 header from the buffer start
  3454. * - OFFSET_MSDU_PAYLOAD
  3455. * Bits 31:16
  3456. * Value: offset in QUAD-bytes of MSDU payload from the buffer start
  3457. * - OFFSET_PPDU_START
  3458. * Bits 15:0
  3459. * Value: offset in QUAD-bytes of PPDU start rx desc from the buffer start
  3460. * - OFFSET_PPDU_END
  3461. * Bits 31:16
  3462. * Value: offset in QUAD-bytes of PPDU end rx desc from the buffer start
  3463. * - OFFSET_MPDU_START
  3464. * Bits 15:0
  3465. * Value: offset in QUAD-bytes of MPDU start rx desc from the buffer start
  3466. * - OFFSET_MPDU_END
  3467. * Bits 31:16
  3468. * Value: offset in QUAD-bytes of MPDU end rx desc from the buffer start
  3469. * - OFFSET_MSDU_START
  3470. * Bits 15:0
  3471. * Value: offset in QUAD-bytes of MSDU start rx desc from the buffer start
  3472. * - OFFSET_MSDU_END
  3473. * Bits 31:16
  3474. * Value: offset in QUAD-bytes of MSDU end rx desc from the buffer start
  3475. * - OFFSET_RX_ATTN
  3476. * Bits 15:0
  3477. * Value: offset in QUAD-bytes of rx attention word from the buffer start
  3478. * - OFFSET_FRAG_INFO
  3479. * Bits 31:16
  3480. * Value: offset in QUAD-bytes of frag info table
  3481. */
  3482. /* header fields */
  3483. #define HTT_RX_RING_CFG_NUM_RINGS_M 0xff00
  3484. #define HTT_RX_RING_CFG_NUM_RINGS_S 8
  3485. /* payload fields */
  3486. /* for systems using a 64-bit format for bus addresses */
  3487. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_M 0xffffffff
  3488. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_S 0
  3489. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_M 0xffffffff
  3490. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_S 0
  3491. #define HTT_RX_RING_CFG_BASE_PADDR_HI_M 0xffffffff
  3492. #define HTT_RX_RING_CFG_BASE_PADDR_HI_S 0
  3493. #define HTT_RX_RING_CFG_BASE_PADDR_LO_M 0xffffffff
  3494. #define HTT_RX_RING_CFG_BASE_PADDR_LO_S 0
  3495. /* for systems using a 32-bit format for bus addresses */
  3496. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_M 0xffffffff
  3497. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_S 0
  3498. #define HTT_RX_RING_CFG_BASE_PADDR_M 0xffffffff
  3499. #define HTT_RX_RING_CFG_BASE_PADDR_S 0
  3500. #define HTT_RX_RING_CFG_LEN_M 0xffff
  3501. #define HTT_RX_RING_CFG_LEN_S 0
  3502. #define HTT_RX_RING_CFG_BUF_SZ_M 0xffff0000
  3503. #define HTT_RX_RING_CFG_BUF_SZ_S 16
  3504. #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_M 0x1
  3505. #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_S 0
  3506. #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M 0x2
  3507. #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S 1
  3508. #define HTT_RX_RING_CFG_ENABLED_PPDU_START_M 0x4
  3509. #define HTT_RX_RING_CFG_ENABLED_PPDU_START_S 2
  3510. #define HTT_RX_RING_CFG_ENABLED_PPDU_END_M 0x8
  3511. #define HTT_RX_RING_CFG_ENABLED_PPDU_END_S 3
  3512. #define HTT_RX_RING_CFG_ENABLED_MPDU_START_M 0x10
  3513. #define HTT_RX_RING_CFG_ENABLED_MPDU_START_S 4
  3514. #define HTT_RX_RING_CFG_ENABLED_MPDU_END_M 0x20
  3515. #define HTT_RX_RING_CFG_ENABLED_MPDU_END_S 5
  3516. #define HTT_RX_RING_CFG_ENABLED_MSDU_START_M 0x40
  3517. #define HTT_RX_RING_CFG_ENABLED_MSDU_START_S 6
  3518. #define HTT_RX_RING_CFG_ENABLED_MSDU_END_M 0x80
  3519. #define HTT_RX_RING_CFG_ENABLED_MSDU_END_S 7
  3520. #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_M 0x100
  3521. #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_S 8
  3522. #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M 0x200
  3523. #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S 9
  3524. #define HTT_RX_RING_CFG_ENABLED_UCAST_M 0x400
  3525. #define HTT_RX_RING_CFG_ENABLED_UCAST_S 10
  3526. #define HTT_RX_RING_CFG_ENABLED_MCAST_M 0x800
  3527. #define HTT_RX_RING_CFG_ENABLED_MCAST_S 11
  3528. #define HTT_RX_RING_CFG_ENABLED_CTRL_M 0x1000
  3529. #define HTT_RX_RING_CFG_ENABLED_CTRL_S 12
  3530. #define HTT_RX_RING_CFG_ENABLED_MGMT_M 0x2000
  3531. #define HTT_RX_RING_CFG_ENABLED_MGMT_S 13
  3532. #define HTT_RX_RING_CFG_ENABLED_NULL_M 0x4000
  3533. #define HTT_RX_RING_CFG_ENABLED_NULL_S 14
  3534. #define HTT_RX_RING_CFG_ENABLED_PHY_M 0x8000
  3535. #define HTT_RX_RING_CFG_ENABLED_PHY_S 15
  3536. #define HTT_RX_RING_CFG_IDX_INIT_VAL_M 0xffff0000
  3537. #define HTT_RX_RING_CFG_IDX_INIT_VAL_S 16
  3538. #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_M 0xffff
  3539. #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_S 0
  3540. #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M 0xffff0000
  3541. #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S 16
  3542. #define HTT_RX_RING_CFG_OFFSET_PPDU_START_M 0xffff
  3543. #define HTT_RX_RING_CFG_OFFSET_PPDU_START_S 0
  3544. #define HTT_RX_RING_CFG_OFFSET_PPDU_END_M 0xffff0000
  3545. #define HTT_RX_RING_CFG_OFFSET_PPDU_END_S 16
  3546. #define HTT_RX_RING_CFG_OFFSET_MPDU_START_M 0xffff
  3547. #define HTT_RX_RING_CFG_OFFSET_MPDU_START_S 0
  3548. #define HTT_RX_RING_CFG_OFFSET_MPDU_END_M 0xffff0000
  3549. #define HTT_RX_RING_CFG_OFFSET_MPDU_END_S 16
  3550. #define HTT_RX_RING_CFG_OFFSET_MSDU_START_M 0xffff
  3551. #define HTT_RX_RING_CFG_OFFSET_MSDU_START_S 0
  3552. #define HTT_RX_RING_CFG_OFFSET_MSDU_END_M 0xffff0000
  3553. #define HTT_RX_RING_CFG_OFFSET_MSDU_END_S 16
  3554. #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_M 0xffff
  3555. #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_S 0
  3556. #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M 0xffff0000
  3557. #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S 16
  3558. #define HTT_RX_RING_CFG_HDR_BYTES 4
  3559. #define HTT_RX_RING_CFG_PAYLD_BYTES_64 44
  3560. #define HTT_RX_RING_CFG_PAYLD_BYTES_32 36
  3561. #if HTT_PADDR64
  3562. #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_64
  3563. #else
  3564. #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_32
  3565. #endif
  3566. #define HTT_RX_RING_CFG_BYTES(num_rings) \
  3567. (HTT_RX_RING_CFG_HDR_BYTES + (num_rings) * HTT_RX_RING_CFG_PAYLD_BYTES)
  3568. #define HTT_RX_RING_CFG_NUM_RINGS_GET(_var) \
  3569. (((_var) & HTT_RX_RING_CFG_NUM_RINGS_M) >> HTT_RX_RING_CFG_NUM_RINGS_S)
  3570. #define HTT_RX_RING_CFG_NUM_RINGS_SET(_var, _val) \
  3571. do { \
  3572. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_NUM_RINGS, _val); \
  3573. ((_var) |= ((_val) << HTT_RX_RING_CFG_NUM_RINGS_S)); \
  3574. } while (0)
  3575. /* degenerate case for 32-bit fields */
  3576. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_GET(_var) (_var)
  3577. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_SET(_var, _val) \
  3578. ((_var) = (_val))
  3579. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_GET(_var) (_var)
  3580. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_SET(_var, _val) \
  3581. ((_var) = (_val))
  3582. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_GET(_var) (_var)
  3583. #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_SET(_var, _val) \
  3584. ((_var) = (_val))
  3585. /* degenerate case for 32-bit fields */
  3586. #define HTT_RX_RING_CFG_BASE_PADDR_HI_GET(_var) (_var)
  3587. #define HTT_RX_RING_CFG_BASE_PADDR_HI_SET(_var, _val) \
  3588. ((_var) = (_val))
  3589. #define HTT_RX_RING_CFG_BASE_PADDR_LO_GET(_var) (_var)
  3590. #define HTT_RX_RING_CFG_BASE_PADDR_LO_SET(_var, _val) \
  3591. ((_var) = (_val))
  3592. #define HTT_RX_RING_CFG_BASE_PADDR_GET(_var) (_var)
  3593. #define HTT_RX_RING_CFG_BASE_PADDR_SET(_var, _val) \
  3594. ((_var) = (_val))
  3595. #define HTT_RX_RING_CFG_LEN_GET(_var) \
  3596. (((_var) & HTT_RX_RING_CFG_LEN_M) >> HTT_RX_RING_CFG_LEN_S)
  3597. #define HTT_RX_RING_CFG_LEN_SET(_var, _val) \
  3598. do { \
  3599. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_LEN, _val); \
  3600. ((_var) |= ((_val) << HTT_RX_RING_CFG_LEN_S)); \
  3601. } while (0)
  3602. #define HTT_RX_RING_CFG_BUF_SZ_GET(_var) \
  3603. (((_var) & HTT_RX_RING_CFG_BUF_SZ_M) >> HTT_RX_RING_CFG_BUF_SZ_S)
  3604. #define HTT_RX_RING_CFG_BUF_SZ_SET(_var, _val) \
  3605. do { \
  3606. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_BUF_SZ, _val); \
  3607. ((_var) |= ((_val) << HTT_RX_RING_CFG_BUF_SZ_S)); \
  3608. } while (0)
  3609. #define HTT_RX_RING_CFG_IDX_INIT_VAL_GET(_var) \
  3610. (((_var) & HTT_RX_RING_CFG_IDX_INIT_VAL_M) >> \
  3611. HTT_RX_RING_CFG_IDX_INIT_VAL_S)
  3612. #define HTT_RX_RING_CFG_IDX_INIT_VAL_SET(_var, _val) \
  3613. do { \
  3614. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_IDX_INIT_VAL, _val); \
  3615. ((_var) |= ((_val) << HTT_RX_RING_CFG_IDX_INIT_VAL_S)); \
  3616. } while (0)
  3617. #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_GET(_var) \
  3618. (((_var) & HTT_RX_RING_CFG_ENABLED_802_11_HDR_M) >> \
  3619. HTT_RX_RING_CFG_ENABLED_802_11_HDR_S)
  3620. #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_SET(_var, _val) \
  3621. do { \
  3622. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_802_11_HDR, _val); \
  3623. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_802_11_HDR_S)); \
  3624. } while (0)
  3625. #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_GET(_var) \
  3626. (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M) >> \
  3627. HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S)
  3628. #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_SET(_var, _val) \
  3629. do { \
  3630. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD, _val); \
  3631. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S)); \
  3632. } while (0)
  3633. #define HTT_RX_RING_CFG_ENABLED_PPDU_START_GET(_var) \
  3634. (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_START_M) >> \
  3635. HTT_RX_RING_CFG_ENABLED_PPDU_START_S)
  3636. #define HTT_RX_RING_CFG_ENABLED_PPDU_START_SET(_var, _val) \
  3637. do { \
  3638. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_START, _val); \
  3639. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_START_S)); \
  3640. } while (0)
  3641. #define HTT_RX_RING_CFG_ENABLED_PPDU_END_GET(_var) \
  3642. (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_END_M) >> \
  3643. HTT_RX_RING_CFG_ENABLED_PPDU_END_S)
  3644. #define HTT_RX_RING_CFG_ENABLED_PPDU_END_SET(_var, _val) \
  3645. do { \
  3646. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_END, _val); \
  3647. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_END_S)); \
  3648. } while (0)
  3649. #define HTT_RX_RING_CFG_ENABLED_MPDU_START_GET(_var) \
  3650. (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_START_M) >> \
  3651. HTT_RX_RING_CFG_ENABLED_MPDU_START_S)
  3652. #define HTT_RX_RING_CFG_ENABLED_MPDU_START_SET(_var, _val) \
  3653. do { \
  3654. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_START, _val); \
  3655. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_START_S)); \
  3656. } while (0)
  3657. #define HTT_RX_RING_CFG_ENABLED_MPDU_END_GET(_var) \
  3658. (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_END_M) >> \
  3659. HTT_RX_RING_CFG_ENABLED_MPDU_END_S)
  3660. #define HTT_RX_RING_CFG_ENABLED_MPDU_END_SET(_var, _val) \
  3661. do { \
  3662. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_END, _val); \
  3663. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_END_S)); \
  3664. } while (0)
  3665. #define HTT_RX_RING_CFG_ENABLED_MSDU_START_GET(_var) \
  3666. (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_START_M) >> \
  3667. HTT_RX_RING_CFG_ENABLED_MSDU_START_S)
  3668. #define HTT_RX_RING_CFG_ENABLED_MSDU_START_SET(_var, _val) \
  3669. do { \
  3670. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_START, _val); \
  3671. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_START_S)); \
  3672. } while (0)
  3673. #define HTT_RX_RING_CFG_ENABLED_MSDU_END_GET(_var) \
  3674. (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_END_M) >> \
  3675. HTT_RX_RING_CFG_ENABLED_MSDU_END_S)
  3676. #define HTT_RX_RING_CFG_ENABLED_MSDU_END_SET(_var, _val) \
  3677. do { \
  3678. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_END, _val); \
  3679. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_END_S)); \
  3680. } while (0)
  3681. #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_GET(_var) \
  3682. (((_var) & HTT_RX_RING_CFG_ENABLED_RX_ATTN_M) >> \
  3683. HTT_RX_RING_CFG_ENABLED_RX_ATTN_S)
  3684. #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_SET(_var, _val) \
  3685. do { \
  3686. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_RX_ATTN, _val); \
  3687. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_RX_ATTN_S)); \
  3688. } while (0)
  3689. #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_GET(_var) \
  3690. (((_var) & HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M) >> \
  3691. HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S)
  3692. #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_SET(_var, _val) \
  3693. do { \
  3694. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_FRAG_INFO, _val); \
  3695. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S)); \
  3696. } while (0)
  3697. #define HTT_RX_RING_CFG_ENABLED_UCAST_GET(_var) \
  3698. (((_var) & HTT_RX_RING_CFG_ENABLED_UCAST_M) >> \
  3699. HTT_RX_RING_CFG_ENABLED_UCAST_S)
  3700. #define HTT_RX_RING_CFG_ENABLED_UCAST_SET(_var, _val) \
  3701. do { \
  3702. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_UCAST, _val); \
  3703. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_UCAST_S)); \
  3704. } while (0)
  3705. #define HTT_RX_RING_CFG_ENABLED_MCAST_GET(_var) \
  3706. (((_var) & HTT_RX_RING_CFG_ENABLED_MCAST_M) >> \
  3707. HTT_RX_RING_CFG_ENABLED_MCAST_S)
  3708. #define HTT_RX_RING_CFG_ENABLED_MCAST_SET(_var, _val) \
  3709. do { \
  3710. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MCAST, _val); \
  3711. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MCAST_S)); \
  3712. } while (0)
  3713. #define HTT_RX_RING_CFG_ENABLED_CTRL_GET(_var) \
  3714. (((_var) & HTT_RX_RING_CFG_ENABLED_CTRL_M) >> \
  3715. HTT_RX_RING_CFG_ENABLED_CTRL_S)
  3716. #define HTT_RX_RING_CFG_ENABLED_CTRL_SET(_var, _val) \
  3717. do { \
  3718. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_CTRL, _val); \
  3719. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_CTRL_S)); \
  3720. } while (0)
  3721. #define HTT_RX_RING_CFG_ENABLED_MGMT_GET(_var) \
  3722. (((_var) & HTT_RX_RING_CFG_ENABLED_MGMT_M) >> \
  3723. HTT_RX_RING_CFG_ENABLED_MGMT_S)
  3724. #define HTT_RX_RING_CFG_ENABLED_MGMT_SET(_var, _val) \
  3725. do { \
  3726. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MGMT, _val); \
  3727. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MGMT_S)); \
  3728. } while (0)
  3729. #define HTT_RX_RING_CFG_ENABLED_NULL_GET(_var) \
  3730. (((_var) & HTT_RX_RING_CFG_ENABLED_NULL_M) >> \
  3731. HTT_RX_RING_CFG_ENABLED_NULL_S)
  3732. #define HTT_RX_RING_CFG_ENABLED_NULL_SET(_var, _val) \
  3733. do { \
  3734. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_NULL, _val); \
  3735. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_NULL_S)); \
  3736. } while (0)
  3737. #define HTT_RX_RING_CFG_ENABLED_PHY_GET(_var) \
  3738. (((_var) & HTT_RX_RING_CFG_ENABLED_PHY_M) >> \
  3739. HTT_RX_RING_CFG_ENABLED_PHY_S)
  3740. #define HTT_RX_RING_CFG_ENABLED_PHY_SET(_var, _val) \
  3741. do { \
  3742. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PHY, _val); \
  3743. ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PHY_S)); \
  3744. } while (0)
  3745. #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_GET(_var) \
  3746. (((_var) & HTT_RX_RING_CFG_OFFSET_802_11_HDR_M) >> \
  3747. HTT_RX_RING_CFG_OFFSET_802_11_HDR_S)
  3748. #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_SET(_var, _val) \
  3749. do { \
  3750. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_802_11_HDR, _val); \
  3751. ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_802_11_HDR_S)); \
  3752. } while (0)
  3753. #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_GET(_var) \
  3754. (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M) >> \
  3755. HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S)
  3756. #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_SET(_var, _val) \
  3757. do { \
  3758. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD, _val); \
  3759. ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S)); \
  3760. } while (0)
  3761. #define HTT_RX_RING_CFG_OFFSET_PPDU_START_GET(_var) \
  3762. (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_START_M) >> \
  3763. HTT_RX_RING_CFG_OFFSET_PPDU_START_S)
  3764. #define HTT_RX_RING_CFG_OFFSET_PPDU_START_SET(_var, _val) \
  3765. do { \
  3766. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_START, _val); \
  3767. ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_START_S)); \
  3768. } while (0)
  3769. #define HTT_RX_RING_CFG_OFFSET_PPDU_END_GET(_var) \
  3770. (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_END_M) >> \
  3771. HTT_RX_RING_CFG_OFFSET_PPDU_END_S)
  3772. #define HTT_RX_RING_CFG_OFFSET_PPDU_END_SET(_var, _val) \
  3773. do { \
  3774. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_END, _val); \
  3775. ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_END_S)); \
  3776. } while (0)
  3777. #define HTT_RX_RING_CFG_OFFSET_MPDU_START_GET(_var) \
  3778. (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_START_M) >> \
  3779. HTT_RX_RING_CFG_OFFSET_MPDU_START_S)
  3780. #define HTT_RX_RING_CFG_OFFSET_MPDU_START_SET(_var, _val) \
  3781. do { \
  3782. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_START, _val); \
  3783. ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_START_S)); \
  3784. } while (0)
  3785. #define HTT_RX_RING_CFG_OFFSET_MPDU_END_GET(_var) \
  3786. (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_END_M) >> \
  3787. HTT_RX_RING_CFG_OFFSET_MPDU_END_S)
  3788. #define HTT_RX_RING_CFG_OFFSET_MPDU_END_SET(_var, _val) \
  3789. do { \
  3790. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_END, _val); \
  3791. ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_END_S)); \
  3792. } while (0)
  3793. #define HTT_RX_RING_CFG_OFFSET_MSDU_START_GET(_var) \
  3794. (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_START_M) >> \
  3795. HTT_RX_RING_CFG_OFFSET_MSDU_START_S)
  3796. #define HTT_RX_RING_CFG_OFFSET_MSDU_START_SET(_var, _val) \
  3797. do { \
  3798. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_START, _val); \
  3799. ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_START_S)); \
  3800. } while (0)
  3801. #define HTT_RX_RING_CFG_OFFSET_MSDU_END_GET(_var) \
  3802. (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_END_M) >> \
  3803. HTT_RX_RING_CFG_OFFSET_MSDU_END_S)
  3804. #define HTT_RX_RING_CFG_OFFSET_MSDU_END_SET(_var, _val) \
  3805. do { \
  3806. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_END, _val); \
  3807. ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_END_S)); \
  3808. } while (0)
  3809. #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_GET(_var) \
  3810. (((_var) & HTT_RX_RING_CFG_OFFSET_RX_ATTN_M) >> \
  3811. HTT_RX_RING_CFG_OFFSET_RX_ATTN_S)
  3812. #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_SET(_var, _val) \
  3813. do { \
  3814. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_RX_ATTN, _val); \
  3815. ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_RX_ATTN_S)); \
  3816. } while (0)
  3817. #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_GET(_var) \
  3818. (((_var) & HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M) >> \
  3819. HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S)
  3820. #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_SET(_var, _val) \
  3821. do { \
  3822. HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_FRAG_INFO, _val); \
  3823. ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S)); \
  3824. } while (0)
  3825. /**
  3826. * @brief host -> target FW statistics retrieve
  3827. *
  3828. * MSG_TYPE => HTT_H2T_MSG_TYPE_STATS_REQ
  3829. *
  3830. * @details
  3831. * The following field definitions describe the format of the HTT host
  3832. * to target FW stats retrieve message. The message specifies the type of
  3833. * stats host wants to retrieve.
  3834. *
  3835. * |31 24|23 16|15 8|7 0|
  3836. * |-----------------------------------------------------------|
  3837. * | stats types request bitmask | msg type |
  3838. * |-----------------------------------------------------------|
  3839. * | stats types reset bitmask | reserved |
  3840. * |-----------------------------------------------------------|
  3841. * | stats type | config value |
  3842. * |-----------------------------------------------------------|
  3843. * | cookie LSBs |
  3844. * |-----------------------------------------------------------|
  3845. * | cookie MSBs |
  3846. * |-----------------------------------------------------------|
  3847. * Header fields:
  3848. * - MSG_TYPE
  3849. * Bits 7:0
  3850. * Purpose: identifies this is a stats upload request message
  3851. * Value: 0x3 (HTT_H2T_MSG_TYPE_STATS_REQ)
  3852. * - UPLOAD_TYPES
  3853. * Bits 31:8
  3854. * Purpose: identifies which types of FW statistics to upload
  3855. * Value: mask with bits set in positions defined by htt_dbg_stats_type
  3856. * - RESET_TYPES
  3857. * Bits 31:8
  3858. * Purpose: identifies which types of FW statistics to reset
  3859. * Value: mask with bits set in positions defined by htt_dbg_stats_type
  3860. * - CFG_VAL
  3861. * Bits 23:0
  3862. * Purpose: give an opaque configuration value to the specified stats type
  3863. * Value: stats-type specific configuration value
  3864. * if stats type == tx PPDU log, then CONFIG_VAL has the format:
  3865. * bits 7:0 - how many per-MPDU byte counts to include in a record
  3866. * bits 15:8 - how many per-MPDU MSDU counts to include in a record
  3867. * bits 23:16 - how many per-MSDU byte counts to include in a record
  3868. * - CFG_STAT_TYPE
  3869. * Bits 31:24
  3870. * Purpose: specify which stats type (if any) the config value applies to
  3871. * Value: htt_dbg_stats_type value, or 0xff if the message doesn't have
  3872. * a valid configuration specification
  3873. * - COOKIE_LSBS
  3874. * Bits 31:0
  3875. * Purpose: Provide a mechanism to match a target->host stats confirmation
  3876. * message with its preceding host->target stats request message.
  3877. * Value: LSBs of the opaque cookie specified by the host-side requestor
  3878. * - COOKIE_MSBS
  3879. * Bits 31:0
  3880. * Purpose: Provide a mechanism to match a target->host stats confirmation
  3881. * message with its preceding host->target stats request message.
  3882. * Value: MSBs of the opaque cookie specified by the host-side requestor
  3883. */
  3884. #define HTT_H2T_STATS_REQ_MSG_SZ 20 /* bytes */
  3885. #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff
  3886. #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_M 0xffffff00
  3887. #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_S 8
  3888. #define HTT_H2T_STATS_REQ_RESET_TYPES_M 0xffffff00
  3889. #define HTT_H2T_STATS_REQ_RESET_TYPES_S 8
  3890. #define HTT_H2T_STATS_REQ_CFG_VAL_M 0x00ffffff
  3891. #define HTT_H2T_STATS_REQ_CFG_VAL_S 0
  3892. #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M 0xff000000
  3893. #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S 24
  3894. #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_GET(_var) \
  3895. (((_var) & HTT_H2T_STATS_REQ_UPLOAD_TYPES_M) >> \
  3896. HTT_H2T_STATS_REQ_UPLOAD_TYPES_S)
  3897. #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_SET(_var, _val) \
  3898. do { \
  3899. HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_UPLOAD_TYPES, _val); \
  3900. ((_var) |= ((_val) << HTT_H2T_STATS_REQ_UPLOAD_TYPES_S)); \
  3901. } while (0)
  3902. #define HTT_H2T_STATS_REQ_RESET_TYPES_GET(_var) \
  3903. (((_var) & HTT_H2T_STATS_REQ_RESET_TYPES_M) >> \
  3904. HTT_H2T_STATS_REQ_RESET_TYPES_S)
  3905. #define HTT_H2T_STATS_REQ_RESET_TYPES_SET(_var, _val) \
  3906. do { \
  3907. HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_RESET_TYPES, _val); \
  3908. ((_var) |= ((_val) << HTT_H2T_STATS_REQ_RESET_TYPES_S)); \
  3909. } while (0)
  3910. #define HTT_H2T_STATS_REQ_CFG_VAL_GET(_var) \
  3911. (((_var) & HTT_H2T_STATS_REQ_CFG_VAL_M) >> \
  3912. HTT_H2T_STATS_REQ_CFG_VAL_S)
  3913. #define HTT_H2T_STATS_REQ_CFG_VAL_SET(_var, _val) \
  3914. do { \
  3915. HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_VAL, _val); \
  3916. ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_VAL_S)); \
  3917. } while (0)
  3918. #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_GET(_var) \
  3919. (((_var) & HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M) >> \
  3920. HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S)
  3921. #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_SET(_var, _val) \
  3922. do { \
  3923. HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_STAT_TYPE, _val); \
  3924. ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S)); \
  3925. } while (0)
  3926. /**
  3927. * @brief host -> target HTT out-of-band sync request
  3928. *
  3929. * MSG_TYPE => HTT_H2T_MSG_TYPE_SYNC
  3930. *
  3931. * @details
  3932. * The HTT SYNC tells the target to suspend processing of subsequent
  3933. * HTT host-to-target messages until some other target agent locally
  3934. * informs the target HTT FW that the current sync counter is equal to
  3935. * or greater than (in a modulo sense) the sync counter specified in
  3936. * the SYNC message.
  3937. * This allows other host-target components to synchronize their operation
  3938. * with HTT, e.g. to ensure that tx frames don't get transmitted until a
  3939. * security key has been downloaded to and activated by the target.
  3940. * In the absence of any explicit synchronization counter value
  3941. * specification, the target HTT FW will use zero as the default current
  3942. * sync value.
  3943. *
  3944. * |31 24|23 16|15 8|7 0|
  3945. * |-----------------------------------------------------------|
  3946. * | reserved | sync count | msg type |
  3947. * |-----------------------------------------------------------|
  3948. * Header fields:
  3949. * - MSG_TYPE
  3950. * Bits 7:0
  3951. * Purpose: identifies this as a sync message
  3952. * Value: 0x4 (HTT_H2T_MSG_TYPE_SYNC)
  3953. * - SYNC_COUNT
  3954. * Bits 15:8
  3955. * Purpose: specifies what sync value the HTT FW will wait for from
  3956. * an out-of-band specification to resume its operation
  3957. * Value: in-band sync counter value to compare against the out-of-band
  3958. * counter spec.
  3959. * The HTT target FW will suspend its host->target message processing
  3960. * as long as
  3961. * 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128
  3962. */
  3963. #define HTT_H2T_SYNC_MSG_SZ 4
  3964. #define HTT_H2T_SYNC_COUNT_M 0x0000ff00
  3965. #define HTT_H2T_SYNC_COUNT_S 8
  3966. #define HTT_H2T_SYNC_COUNT_GET(_var) \
  3967. (((_var) & HTT_H2T_SYNC_COUNT_M) >> \
  3968. HTT_H2T_SYNC_COUNT_S)
  3969. #define HTT_H2T_SYNC_COUNT_SET(_var, _val) \
  3970. do { \
  3971. HTT_CHECK_SET_VAL(HTT_H2T_SYNC_COUNT, _val); \
  3972. ((_var) |= ((_val) << HTT_H2T_SYNC_COUNT_S)); \
  3973. } while (0)
  3974. /**
  3975. * @brief host -> target HTT aggregation configuration
  3976. *
  3977. * MSG_TYPE => HTT_H2T_MSG_TYPE_AGGR_CFG
  3978. */
  3979. #define HTT_AGGR_CFG_MSG_SZ 4
  3980. #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M 0xff00
  3981. #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S 8
  3982. #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M 0x1f0000
  3983. #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S 16
  3984. #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_GET(_var) \
  3985. (((_var) & HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M) >> \
  3986. HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S)
  3987. #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_SET(_var, _val) \
  3988. do { \
  3989. HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM, _val); \
  3990. ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S)); \
  3991. } while (0)
  3992. #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_GET(_var) \
  3993. (((_var) & HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M) >> \
  3994. HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S)
  3995. #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \
  3996. do { \
  3997. HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM, _val); \
  3998. ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S)); \
  3999. } while (0)
  4000. /**
  4001. * @brief host -> target HTT configure max amsdu info per vdev
  4002. *
  4003. * MSG_TYPE => HTT_H2T_MSG_TYPE_AGGR_CFG_EX
  4004. *
  4005. * @details
  4006. * The HTT AGGR CFG EX tells the target to configure max_amsdu info per vdev
  4007. *
  4008. * |31 21|20 16|15 8|7 0|
  4009. * |-----------------------------------------------------------|
  4010. * | reserved | vdev id | max amsdu | msg type |
  4011. * |-----------------------------------------------------------|
  4012. * Header fields:
  4013. * - MSG_TYPE
  4014. * Bits 7:0
  4015. * Purpose: identifies this as a aggr cfg ex message
  4016. * Value: 0xa (HTT_H2T_MSG_TYPE_AGGR_CFG_EX)
  4017. * - MAX_NUM_AMSDU_SUBFRM
  4018. * Bits 15:8
  4019. * Purpose: max MSDUs per A-MSDU
  4020. * - VDEV_ID
  4021. * Bits 20:16
  4022. * Purpose: ID of the vdev to which this limit is applied
  4023. */
  4024. #define HTT_AGGR_CFG_EX_MSG_SZ 4
  4025. #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M 0xff00
  4026. #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S 8
  4027. #define HTT_AGGR_CFG_EX_VDEV_ID_M 0x1f0000
  4028. #define HTT_AGGR_CFG_EX_VDEV_ID_S 16
  4029. #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_GET(_var) \
  4030. (((_var) & HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M) >> \
  4031. HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S)
  4032. #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \
  4033. do { \
  4034. HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM, _val); \
  4035. ((_var) |= ((_val) << HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S)); \
  4036. } while (0)
  4037. #define HTT_AGGR_CFG_EX_VDEV_ID_GET(_var) \
  4038. (((_var) & HTT_AGGR_CFG_EX_VDEV_ID_M) >> \
  4039. HTT_AGGR_CFG_EX_VDEV_ID_S)
  4040. #define HTT_AGGR_CFG_EX_VDEV_ID_SET(_var, _val) \
  4041. do { \
  4042. HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_VDEV_ID, _val); \
  4043. ((_var) |= ((_val) << HTT_AGGR_CFG_EX_VDEV_ID_S)); \
  4044. } while (0)
  4045. /**
  4046. * @brief HTT WDI_IPA Config Message
  4047. *
  4048. * MSG_TYPE => HTT_H2T_MSG_TYPE_WDI_IPA_CFG
  4049. *
  4050. * @details
  4051. * The HTT WDI_IPA config message is created/sent by host at driver
  4052. * init time. It contains information about data structures used on
  4053. * WDI_IPA TX and RX path.
  4054. * TX CE ring is used for pushing packet metadata from IPA uC
  4055. * to WLAN FW
  4056. * TX Completion ring is used for generating TX completions from
  4057. * WLAN FW to IPA uC
  4058. * RX Indication ring is used for indicating RX packets from FW
  4059. * to IPA uC
  4060. * RX Ring2 is used as either completion ring or as second
  4061. * indication ring. when Ring2 is used as completion ring, IPA uC
  4062. * puts completed RX packet meta data to Ring2. when Ring2 is used
  4063. * as second indication ring, RX packets for LTE-WLAN aggregation are
  4064. * indicated in Ring2, other RX packets (e.g. hotspot related) are
  4065. * indicated in RX Indication ring. Please see WDI_IPA specification
  4066. * for more details.
  4067. * |31 24|23 16|15 8|7 0|
  4068. * |----------------+----------------+----------------+----------------|
  4069. * | tx pkt pool size | Rsvd | msg_type |
  4070. * |-------------------------------------------------------------------|
  4071. * | tx comp ring base (bits 31:0) |
  4072. #if HTT_PADDR64
  4073. * | tx comp ring base (bits 63:32) |
  4074. #endif
  4075. * |-------------------------------------------------------------------|
  4076. * | tx comp ring size |
  4077. * |-------------------------------------------------------------------|
  4078. * | tx comp WR_IDX physical address (bits 31:0) |
  4079. #if HTT_PADDR64
  4080. * | tx comp WR_IDX physical address (bits 63:32) |
  4081. #endif
  4082. * |-------------------------------------------------------------------|
  4083. * | tx CE WR_IDX physical address (bits 31:0) |
  4084. #if HTT_PADDR64
  4085. * | tx CE WR_IDX physical address (bits 63:32) |
  4086. #endif
  4087. * |-------------------------------------------------------------------|
  4088. * | rx indication ring base (bits 31:0) |
  4089. #if HTT_PADDR64
  4090. * | rx indication ring base (bits 63:32) |
  4091. #endif
  4092. * |-------------------------------------------------------------------|
  4093. * | rx indication ring size |
  4094. * |-------------------------------------------------------------------|
  4095. * | rx ind RD_IDX physical address (bits 31:0) |
  4096. #if HTT_PADDR64
  4097. * | rx ind RD_IDX physical address (bits 63:32) |
  4098. #endif
  4099. * |-------------------------------------------------------------------|
  4100. * | rx ind WR_IDX physical address (bits 31:0) |
  4101. #if HTT_PADDR64
  4102. * | rx ind WR_IDX physical address (bits 63:32) |
  4103. #endif
  4104. * |-------------------------------------------------------------------|
  4105. * |-------------------------------------------------------------------|
  4106. * | rx ring2 base (bits 31:0) |
  4107. #if HTT_PADDR64
  4108. * | rx ring2 base (bits 63:32) |
  4109. #endif
  4110. * |-------------------------------------------------------------------|
  4111. * | rx ring2 size |
  4112. * |-------------------------------------------------------------------|
  4113. * | rx ring2 RD_IDX physical address (bits 31:0) |
  4114. #if HTT_PADDR64
  4115. * | rx ring2 RD_IDX physical address (bits 63:32) |
  4116. #endif
  4117. * |-------------------------------------------------------------------|
  4118. * | rx ring2 WR_IDX physical address (bits 31:0) |
  4119. #if HTT_PADDR64
  4120. * | rx ring2 WR_IDX physical address (bits 63:32) |
  4121. #endif
  4122. * |-------------------------------------------------------------------|
  4123. *
  4124. * Header fields:
  4125. * Header fields:
  4126. * - MSG_TYPE
  4127. * Bits 7:0
  4128. * Purpose: Identifies this as WDI_IPA config message
  4129. * value: = 0x8 (HTT_H2T_MSG_TYPE_WDI_IPA_CFG)
  4130. * - TX_PKT_POOL_SIZE
  4131. * Bits 15:0
  4132. * Purpose: Total number of TX packet buffer pool allocated by Host for
  4133. * WDI_IPA TX path
  4134. * For systems using 32-bit format for bus addresses:
  4135. * - TX_COMP_RING_BASE_ADDR
  4136. * Bits 31:0
  4137. * Purpose: TX Completion Ring base address in DDR
  4138. * - TX_COMP_RING_SIZE
  4139. * Bits 31:0
  4140. * Purpose: TX Completion Ring size (must be power of 2)
  4141. * - TX_COMP_WR_IDX_ADDR
  4142. * Bits 31:0
  4143. * Purpose: IPA doorbell register address OR DDR address where WIFI FW
  4144. * updates the Write Index for WDI_IPA TX completion ring
  4145. * - TX_CE_WR_IDX_ADDR
  4146. * Bits 31:0
  4147. * Purpose: DDR address where IPA uC
  4148. * updates the WR Index for TX CE ring
  4149. * (needed for fusion platforms)
  4150. * - RX_IND_RING_BASE_ADDR
  4151. * Bits 31:0
  4152. * Purpose: RX Indication Ring base address in DDR
  4153. * - RX_IND_RING_SIZE
  4154. * Bits 31:0
  4155. * Purpose: RX Indication Ring size
  4156. * - RX_IND_RD_IDX_ADDR
  4157. * Bits 31:0
  4158. * Purpose: DDR address where IPA uC updates the Read Index for WDI_IPA
  4159. * RX indication ring
  4160. * - RX_IND_WR_IDX_ADDR
  4161. * Bits 31:0
  4162. * Purpose: IPA doorbell register address OR DDR address where WIFI FW
  4163. * updates the Write Index for WDI_IPA RX indication ring
  4164. * - RX_RING2_BASE_ADDR
  4165. * Bits 31:0
  4166. * Purpose: Second RX Ring(Indication or completion)base address in DDR
  4167. * - RX_RING2_SIZE
  4168. * Bits 31:0
  4169. * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE)
  4170. * - RX_RING2_RD_IDX_ADDR
  4171. * Bits 31:0
  4172. * Purpose: If Second RX ring is Indication ring, DDR address where
  4173. * IPA uC updates the Read Index for Ring2.
  4174. * If Second RX ring is completion ring, this is NOT used
  4175. * - RX_RING2_WR_IDX_ADDR
  4176. * Bits 31:0
  4177. * Purpose: If Second RX ring is Indication ring, DDR address where
  4178. * WIFI FW updates the Write Index for WDI_IPA RX ring2
  4179. * If second RX ring is completion ring, DDR address where
  4180. * IPA uC updates the Write Index for Ring 2.
  4181. * For systems using 64-bit format for bus addresses:
  4182. * - TX_COMP_RING_BASE_ADDR_LO
  4183. * Bits 31:0
  4184. * Purpose: Lower 4 bytes of TX Completion Ring base physical address in DDR
  4185. * - TX_COMP_RING_BASE_ADDR_HI
  4186. * Bits 31:0
  4187. * Purpose: Higher 4 bytes of TX Completion Ring base physical address in DDR
  4188. * - TX_COMP_RING_SIZE
  4189. * Bits 31:0
  4190. * Purpose: TX Completion Ring size (must be power of 2)
  4191. * - TX_COMP_WR_IDX_ADDR_LO
  4192. * Bits 31:0
  4193. * Purpose: Lower 4 bytes of IPA doorbell register address OR
  4194. * Lower 4 bytes of DDR address where WIFI FW
  4195. * updates the Write Index for WDI_IPA TX completion ring
  4196. * - TX_COMP_WR_IDX_ADDR_HI
  4197. * Bits 31:0
  4198. * Purpose: Higher 4 bytes of IPA doorbell register address OR
  4199. * Higher 4 bytes of DDR address where WIFI FW
  4200. * updates the Write Index for WDI_IPA TX completion ring
  4201. * - TX_CE_WR_IDX_ADDR_LO
  4202. * Bits 31:0
  4203. * Purpose: Lower 4 bytes of DDR address where IPA uC
  4204. * updates the WR Index for TX CE ring
  4205. * (needed for fusion platforms)
  4206. * - TX_CE_WR_IDX_ADDR_HI
  4207. * Bits 31:0
  4208. * Purpose: Higher 4 bytes of DDR address where IPA uC
  4209. * updates the WR Index for TX CE ring
  4210. * (needed for fusion platforms)
  4211. * - RX_IND_RING_BASE_ADDR_LO
  4212. * Bits 31:0
  4213. * Purpose: Lower 4 bytes of RX Indication Ring base address in DDR
  4214. * - RX_IND_RING_BASE_ADDR_HI
  4215. * Bits 31:0
  4216. * Purpose: Higher 4 bytes of RX Indication Ring base address in DDR
  4217. * - RX_IND_RING_SIZE
  4218. * Bits 31:0
  4219. * Purpose: RX Indication Ring size
  4220. * - RX_IND_RD_IDX_ADDR_LO
  4221. * Bits 31:0
  4222. * Purpose: Lower 4 bytes of DDR address where IPA uC updates the Read Index
  4223. * for WDI_IPA RX indication ring
  4224. * - RX_IND_RD_IDX_ADDR_HI
  4225. * Bits 31:0
  4226. * Purpose: Higher 4 bytes of DDR address where IPA uC updates the Read Index
  4227. * for WDI_IPA RX indication ring
  4228. * - RX_IND_WR_IDX_ADDR_LO
  4229. * Bits 31:0
  4230. * Purpose: Lower 4 bytes of IPA doorbell register address OR
  4231. * Lower 4 bytes of DDR address where WIFI FW
  4232. * updates the Write Index for WDI_IPA RX indication ring
  4233. * - RX_IND_WR_IDX_ADDR_HI
  4234. * Bits 31:0
  4235. * Purpose: Higher 4 bytes of IPA doorbell register address OR
  4236. * Higher 4 bytes of DDR address where WIFI FW
  4237. * updates the Write Index for WDI_IPA RX indication ring
  4238. * - RX_RING2_BASE_ADDR_LO
  4239. * Bits 31:0
  4240. * Purpose: Lower 4 bytes of Second RX Ring(Indication OR completion)base address in DDR
  4241. * - RX_RING2_BASE_ADDR_HI
  4242. * Bits 31:0
  4243. * Purpose: Higher 4 bytes of Second RX Ring(Indication OR completion)base address in DDR
  4244. * - RX_RING2_SIZE
  4245. * Bits 31:0
  4246. * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE)
  4247. * - RX_RING2_RD_IDX_ADDR_LO
  4248. * Bits 31:0
  4249. * Purpose: If Second RX ring is Indication ring, lower 4 bytes of
  4250. * DDR address where IPA uC updates the Read Index for Ring2.
  4251. * If Second RX ring is completion ring, this is NOT used
  4252. * - RX_RING2_RD_IDX_ADDR_HI
  4253. * Bits 31:0
  4254. * Purpose: If Second RX ring is Indication ring, higher 4 bytes of
  4255. * DDR address where IPA uC updates the Read Index for Ring2.
  4256. * If Second RX ring is completion ring, this is NOT used
  4257. * - RX_RING2_WR_IDX_ADDR_LO
  4258. * Bits 31:0
  4259. * Purpose: If Second RX ring is Indication ring, lower 4 bytes of
  4260. * DDR address where WIFI FW updates the Write Index
  4261. * for WDI_IPA RX ring2
  4262. * If second RX ring is completion ring, lower 4 bytes of
  4263. * DDR address where IPA uC updates the Write Index for Ring 2.
  4264. * - RX_RING2_WR_IDX_ADDR_HI
  4265. * Bits 31:0
  4266. * Purpose: If Second RX ring is Indication ring, higher 4 bytes of
  4267. * DDR address where WIFI FW updates the Write Index
  4268. * for WDI_IPA RX ring2
  4269. * If second RX ring is completion ring, higher 4 bytes of
  4270. * DDR address where IPA uC updates the Write Index for Ring 2.
  4271. */
  4272. #if HTT_PADDR64
  4273. #define HTT_WDI_IPA_CFG_SZ 88 /* bytes */
  4274. #else
  4275. #define HTT_WDI_IPA_CFG_SZ 52 /* bytes */
  4276. #endif
  4277. #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M 0xffff0000
  4278. #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S 16
  4279. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M 0xffffffff
  4280. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S 0
  4281. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M 0xffffffff
  4282. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S 0
  4283. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M 0xffffffff
  4284. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S 0
  4285. #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M 0xffffffff
  4286. #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S 0
  4287. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M 0xffffffff
  4288. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S 0
  4289. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M 0xffffffff
  4290. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S 0
  4291. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M 0xffffffff
  4292. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S 0
  4293. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M 0xffffffff
  4294. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S 0
  4295. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M 0xffffffff
  4296. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S 0
  4297. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M 0xffffffff
  4298. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S 0
  4299. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M 0xffffffff
  4300. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S 0
  4301. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M 0xffffffff
  4302. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S 0
  4303. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M 0xffffffff
  4304. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S 0
  4305. #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M 0xffffffff
  4306. #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S 0
  4307. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M 0xffffffff
  4308. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S 0
  4309. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M 0xffffffff
  4310. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S 0
  4311. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M 0xffffffff
  4312. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S 0
  4313. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M 0xffffffff
  4314. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S 0
  4315. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M 0xffffffff
  4316. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S 0
  4317. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M 0xffffffff
  4318. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S 0
  4319. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M 0xffffffff
  4320. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S 0
  4321. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M 0xffffffff
  4322. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S 0
  4323. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M 0xffffffff
  4324. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S 0
  4325. #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_M 0xffffffff
  4326. #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_S 0
  4327. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M 0xffffffff
  4328. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S 0
  4329. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M 0xffffffff
  4330. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S 0
  4331. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M 0xffffffff
  4332. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S 0
  4333. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M 0xffffffff
  4334. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S 0
  4335. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M 0xffffffff
  4336. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S 0
  4337. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M 0xffffffff
  4338. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S 0
  4339. #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_GET(_var) \
  4340. (((_var) & HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M) >> HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S)
  4341. #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_SET(_var, _val) \
  4342. do { \
  4343. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE, _val); \
  4344. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S)); \
  4345. } while (0)
  4346. /* for systems using 32-bit format for bus addr */
  4347. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_GET(_var) \
  4348. (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S)
  4349. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_SET(_var, _val) \
  4350. do { \
  4351. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR, _val); \
  4352. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S)); \
  4353. } while (0)
  4354. /* for systems using 64-bit format for bus addr */
  4355. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_GET(_var) \
  4356. (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S)
  4357. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_SET(_var, _val) \
  4358. do { \
  4359. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI, _val); \
  4360. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S)); \
  4361. } while (0)
  4362. /* for systems using 64-bit format for bus addr */
  4363. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_GET(_var) \
  4364. (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S)
  4365. #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_SET(_var, _val) \
  4366. do { \
  4367. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO, _val); \
  4368. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S)); \
  4369. } while (0)
  4370. #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_GET(_var) \
  4371. (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S)
  4372. #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_SET(_var, _val) \
  4373. do { \
  4374. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE, _val); \
  4375. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S)); \
  4376. } while (0)
  4377. /* for systems using 32-bit format for bus addr */
  4378. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_GET(_var) \
  4379. (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S)
  4380. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_SET(_var, _val) \
  4381. do { \
  4382. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR, _val); \
  4383. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S)); \
  4384. } while (0)
  4385. /* for systems using 64-bit format for bus addr */
  4386. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_GET(_var) \
  4387. (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S)
  4388. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_SET(_var, _val) \
  4389. do { \
  4390. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI, _val); \
  4391. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S)); \
  4392. } while (0)
  4393. /* for systems using 64-bit format for bus addr */
  4394. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_GET(_var) \
  4395. (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S)
  4396. #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_SET(_var, _val) \
  4397. do { \
  4398. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO, _val); \
  4399. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S)); \
  4400. } while (0)
  4401. /* for systems using 32-bit format for bus addr */
  4402. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_GET(_var) \
  4403. (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S)
  4404. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_SET(_var, _val) \
  4405. do { \
  4406. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR, _val); \
  4407. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S)); \
  4408. } while (0)
  4409. /* for systems using 64-bit format for bus addr */
  4410. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_GET(_var) \
  4411. (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S)
  4412. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_SET(_var, _val) \
  4413. do { \
  4414. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI, _val); \
  4415. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S)); \
  4416. } while (0)
  4417. /* for systems using 64-bit format for bus addr */
  4418. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_GET(_var) \
  4419. (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S)
  4420. #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_SET(_var, _val) \
  4421. do { \
  4422. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO, _val); \
  4423. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S)); \
  4424. } while (0)
  4425. /* for systems using 32-bit format for bus addr */
  4426. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_GET(_var) \
  4427. (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S)
  4428. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_SET(_var, _val) \
  4429. do { \
  4430. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR, _val); \
  4431. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S)); \
  4432. } while (0)
  4433. /* for systems using 64-bit format for bus addr */
  4434. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_GET(_var) \
  4435. (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S)
  4436. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_SET(_var, _val) \
  4437. do { \
  4438. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI, _val); \
  4439. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S)); \
  4440. } while (0)
  4441. /* for systems using 64-bit format for bus addr */
  4442. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_GET(_var) \
  4443. (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S)
  4444. #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_SET(_var, _val) \
  4445. do { \
  4446. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO, _val); \
  4447. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S)); \
  4448. } while (0)
  4449. #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_GET(_var) \
  4450. (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S)
  4451. #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_SET(_var, _val) \
  4452. do { \
  4453. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_SIZE, _val); \
  4454. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S)); \
  4455. } while (0)
  4456. /* for systems using 32-bit format for bus addr */
  4457. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_GET(_var) \
  4458. (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S)
  4459. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_SET(_var, _val) \
  4460. do { \
  4461. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR, _val); \
  4462. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S)); \
  4463. } while (0)
  4464. /* for systems using 64-bit format for bus addr */
  4465. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_GET(_var) \
  4466. (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S)
  4467. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_SET(_var, _val) \
  4468. do { \
  4469. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI, _val); \
  4470. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S)); \
  4471. } while (0)
  4472. /* for systems using 64-bit format for bus addr */
  4473. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_GET(_var) \
  4474. (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S)
  4475. #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_SET(_var, _val) \
  4476. do { \
  4477. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO, _val); \
  4478. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S)); \
  4479. } while (0)
  4480. /* for systems using 32-bit format for bus addr */
  4481. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_GET(_var) \
  4482. (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S)
  4483. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_SET(_var, _val) \
  4484. do { \
  4485. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR, _val); \
  4486. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S)); \
  4487. } while (0)
  4488. /* for systems using 64-bit format for bus addr */
  4489. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_GET(_var) \
  4490. (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S)
  4491. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_SET(_var, _val) \
  4492. do { \
  4493. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI, _val); \
  4494. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S)); \
  4495. } while (0)
  4496. /* for systems using 64-bit format for bus addr */
  4497. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_GET(_var) \
  4498. (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S)
  4499. #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_SET(_var, _val) \
  4500. do { \
  4501. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO, _val); \
  4502. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S)); \
  4503. } while (0)
  4504. /* for systems using 32-bit format for bus addr */
  4505. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_GET(_var) \
  4506. (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S)
  4507. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_SET(_var, _val) \
  4508. do { \
  4509. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR, _val); \
  4510. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S)); \
  4511. } while (0)
  4512. /* for systems using 64-bit format for bus addr */
  4513. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_GET(_var) \
  4514. (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S)
  4515. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_SET(_var, _val) \
  4516. do { \
  4517. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI, _val); \
  4518. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S)); \
  4519. } while (0)
  4520. /* for systems using 64-bit format for bus addr */
  4521. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_GET(_var) \
  4522. (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S)
  4523. #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_SET(_var, _val) \
  4524. do { \
  4525. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO, _val); \
  4526. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S)); \
  4527. } while (0)
  4528. #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_GET(_var) \
  4529. (((_var) & HTT_WDI_IPA_CFG_RX_RING2_SIZE_M) >> HTT_WDI_IPA_CFG_RX_RING2_SIZE_S)
  4530. #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_SET(_var, _val) \
  4531. do { \
  4532. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_SIZE, _val); \
  4533. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_SIZE_S)); \
  4534. } while (0)
  4535. /* for systems using 32-bit format for bus addr */
  4536. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_GET(_var) \
  4537. (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S)
  4538. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_SET(_var, _val) \
  4539. do { \
  4540. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR, _val); \
  4541. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S)); \
  4542. } while (0)
  4543. /* for systems using 64-bit format for bus addr */
  4544. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_GET(_var) \
  4545. (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S)
  4546. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_SET(_var, _val) \
  4547. do { \
  4548. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI, _val); \
  4549. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S)); \
  4550. } while (0)
  4551. /* for systems using 64-bit format for bus addr */
  4552. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_GET(_var) \
  4553. (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S)
  4554. #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_SET(_var, _val) \
  4555. do { \
  4556. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO, _val); \
  4557. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S)); \
  4558. } while (0)
  4559. /* for systems using 32-bit format for bus addr */
  4560. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_GET(_var) \
  4561. (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S)
  4562. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_SET(_var, _val) \
  4563. do { \
  4564. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR, _val); \
  4565. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S)); \
  4566. } while (0)
  4567. /* for systems using 64-bit format for bus addr */
  4568. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_GET(_var) \
  4569. (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S)
  4570. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_SET(_var, _val) \
  4571. do { \
  4572. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI, _val); \
  4573. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S)); \
  4574. } while (0)
  4575. /* for systems using 64-bit format for bus addr */
  4576. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_GET(_var) \
  4577. (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S)
  4578. #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_SET(_var, _val) \
  4579. do { \
  4580. HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO, _val); \
  4581. ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S)); \
  4582. } while (0)
  4583. /*
  4584. * TEMPLATE_HTT_WDI_IPA_CONFIG_T:
  4585. * This macro defines a htt_wdi_ipa_configXXX_t in which any physical
  4586. * addresses are stored in a XXX-bit field.
  4587. * This macro is used to define both htt_wdi_ipa_config32_t and
  4588. * htt_wdi_ipa_config64_t structs.
  4589. */
  4590. #define TEMPLATE_HTT_WDI_IPA_CONFIG_T(_paddr_bits_, \
  4591. _paddr__tx_comp_ring_base_addr_, \
  4592. _paddr__tx_comp_wr_idx_addr_, \
  4593. _paddr__tx_ce_wr_idx_addr_, \
  4594. _paddr__rx_ind_ring_base_addr_, \
  4595. _paddr__rx_ind_rd_idx_addr_, \
  4596. _paddr__rx_ind_wr_idx_addr_, \
  4597. _paddr__rx_ring2_base_addr_,\
  4598. _paddr__rx_ring2_rd_idx_addr_,\
  4599. _paddr__rx_ring2_wr_idx_addr_) \
  4600. PREPACK struct htt_wdi_ipa_cfg ## _paddr_bits_ ## _t \
  4601. { \
  4602. /* DWORD 0: flags and meta-data */ \
  4603. A_UINT32 \
  4604. msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_CFG */ \
  4605. reserved: 8, \
  4606. tx_pkt_pool_size: 16;\
  4607. /* DWORD 1 */\
  4608. _paddr__tx_comp_ring_base_addr_;\
  4609. /* DWORD 2 (or 3)*/\
  4610. A_UINT32 tx_comp_ring_size;\
  4611. /* DWORD 3 (or 4)*/\
  4612. _paddr__tx_comp_wr_idx_addr_;\
  4613. /* DWORD 4 (or 6)*/\
  4614. _paddr__tx_ce_wr_idx_addr_;\
  4615. /* DWORD 5 (or 8)*/\
  4616. _paddr__rx_ind_ring_base_addr_;\
  4617. /* DWORD 6 (or 10)*/\
  4618. A_UINT32 rx_ind_ring_size;\
  4619. /* DWORD 7 (or 11)*/\
  4620. _paddr__rx_ind_rd_idx_addr_;\
  4621. /* DWORD 8 (or 13)*/\
  4622. _paddr__rx_ind_wr_idx_addr_;\
  4623. /* DWORD 9 (or 15)*/\
  4624. _paddr__rx_ring2_base_addr_;\
  4625. /* DWORD 10 (or 17) */\
  4626. A_UINT32 rx_ring2_size;\
  4627. /* DWORD 11 (or 18) */\
  4628. _paddr__rx_ring2_rd_idx_addr_;\
  4629. /* DWORD 12 (or 20) */\
  4630. _paddr__rx_ring2_wr_idx_addr_;\
  4631. } POSTPACK
  4632. /* define a htt_wdi_ipa_config32_t type */
  4633. TEMPLATE_HTT_WDI_IPA_CONFIG_T(32, HTT_VAR_PADDR32(tx_comp_ring_base_addr), HTT_VAR_PADDR32(tx_comp_wr_idx_addr), HTT_VAR_PADDR32(tx_ce_wr_idx_addr), HTT_VAR_PADDR32(rx_ind_ring_base_addr), HTT_VAR_PADDR32(rx_ind_rd_idx_addr),HTT_VAR_PADDR32(rx_ind_wr_idx_addr), HTT_VAR_PADDR32(rx_ring2_base_addr), HTT_VAR_PADDR32(rx_ring2_rd_idx_addr), HTT_VAR_PADDR32(rx_ring2_wr_idx_addr));
  4634. /* define a htt_wdi_ipa_config64_t type */
  4635. TEMPLATE_HTT_WDI_IPA_CONFIG_T(64, HTT_VAR_PADDR64_LE(tx_comp_ring_base_addr), HTT_VAR_PADDR64_LE(tx_comp_wr_idx_addr), HTT_VAR_PADDR64_LE(tx_ce_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_ring_base_addr), HTT_VAR_PADDR64_LE(rx_ind_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_base_addr), HTT_VAR_PADDR64_LE(rx_ring2_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_wr_idx_addr));
  4636. #if HTT_PADDR64
  4637. #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg64_t
  4638. #else
  4639. #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg32_t
  4640. #endif
  4641. enum htt_wdi_ipa_op_code {
  4642. HTT_WDI_IPA_OPCODE_TX_SUSPEND = 0,
  4643. HTT_WDI_IPA_OPCODE_TX_RESUME = 1,
  4644. HTT_WDI_IPA_OPCODE_RX_SUSPEND = 2,
  4645. HTT_WDI_IPA_OPCODE_RX_RESUME = 3,
  4646. HTT_WDI_IPA_OPCODE_DBG_STATS = 4,
  4647. HTT_WDI_IPA_OPCODE_GET_SHARING_STATS = 5,
  4648. HTT_WDI_IPA_OPCODE_SET_QUOTA = 6,
  4649. HTT_WDI_IPA_OPCODE_IND_QUOTA = 7,
  4650. /* keep this last */
  4651. HTT_WDI_IPA_OPCODE_MAX
  4652. };
  4653. /**
  4654. * @brief HTT WDI_IPA Operation Request Message
  4655. *
  4656. * MSG_TYPE => HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ
  4657. *
  4658. * @details
  4659. * HTT WDI_IPA Operation Request message is sent by host
  4660. * to either suspend or resume WDI_IPA TX or RX path.
  4661. * |31 24|23 16|15 8|7 0|
  4662. * |----------------+----------------+----------------+----------------|
  4663. * | op_code | Rsvd | msg_type |
  4664. * |-------------------------------------------------------------------|
  4665. *
  4666. * Header fields:
  4667. * - MSG_TYPE
  4668. * Bits 7:0
  4669. * Purpose: Identifies this as WDI_IPA Operation Request message
  4670. * value: = 0x9 (HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ)
  4671. * - OP_CODE
  4672. * Bits 31:16
  4673. * Purpose: Identifies operation host is requesting (e.g. TX suspend)
  4674. * value: = enum htt_wdi_ipa_op_code
  4675. */
  4676. PREPACK struct htt_wdi_ipa_op_request_t
  4677. {
  4678. /* DWORD 0: flags and meta-data */
  4679. A_UINT32
  4680. msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST */
  4681. reserved: 8,
  4682. op_code: 16;
  4683. } POSTPACK;
  4684. #define HTT_WDI_IPA_OP_REQUEST_SZ 4 /* bytes */
  4685. #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_M 0xffff0000
  4686. #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_S 16
  4687. #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_GET(_var) \
  4688. (((_var) & HTT_WDI_IPA_OP_REQUEST_OP_CODE_M) >> HTT_WDI_IPA_OP_REQUEST_OP_CODE_S)
  4689. #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_SET(_var, _val) \
  4690. do { \
  4691. HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_REQUEST_OP_CODE, _val); \
  4692. ((_var) |= ((_val) << HTT_WDI_IPA_OP_REQUEST_OP_CODE_S)); \
  4693. } while (0)
  4694. /*
  4695. * @brief host -> target HTT_MSI_SETUP message
  4696. *
  4697. * MSG_TYPE => HTT_H2T_MSG_TYPE_MSI_SETUP
  4698. *
  4699. * @details
  4700. * After target is booted up, host can send MSI setup message so that
  4701. * target sets up HW registers based on setup message.
  4702. *
  4703. * The message would appear as follows:
  4704. * |31 24|23 16|15|14 8|7 0|
  4705. * |---------------+-----------------+-----------------+-----------------|
  4706. * | reserved | msi_type | pdev_id | msg_type |
  4707. * |---------------------------------------------------------------------|
  4708. * | msi_addr_lo |
  4709. * |---------------------------------------------------------------------|
  4710. * | msi_addr_hi |
  4711. * |---------------------------------------------------------------------|
  4712. * | msi_data |
  4713. * |---------------------------------------------------------------------|
  4714. *
  4715. * The message is interpreted as follows:
  4716. * dword0 - b'0:7 - msg_type: This will be set to
  4717. * 0x1f (HTT_H2T_MSG_TYPE_MSI_SETUP)
  4718. * b'8:15 - pdev_id:
  4719. * 0 (for rings at SOC/UMAC level),
  4720. * 1/2/3 mac id (for rings at LMAC level)
  4721. * b'16:23 - msi_type: identify which msi registers need to be setup
  4722. * more details can be got from enum htt_msi_setup_type
  4723. * b'24:31 - reserved
  4724. * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
  4725. * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
  4726. * dword10 - b'0:31 - ring_msi_data: MSI data configured by host
  4727. */
  4728. PREPACK struct htt_msi_setup_t {
  4729. A_UINT32 msg_type: 8,
  4730. pdev_id: 8,
  4731. msi_type: 8,
  4732. reserved: 8;
  4733. A_UINT32 msi_addr_lo;
  4734. A_UINT32 msi_addr_hi;
  4735. A_UINT32 msi_data;
  4736. } POSTPACK;
  4737. enum htt_msi_setup_type {
  4738. HTT_PPDU_END_MSI_SETUP_TYPE,
  4739. /* Insert new types here*/
  4740. };
  4741. #define HTT_MSI_SETUP_SZ (sizeof(struct htt_msi_setup_t))
  4742. #define HTT_MSI_SETUP_PDEV_ID_M 0x0000ff00
  4743. #define HTT_MSI_SETUP_PDEV_ID_S 8
  4744. #define HTT_MSI_SETUP_PDEV_ID_GET(_var) \
  4745. (((_var) & HTT_MSI_SETUP_PDEV_ID_M) >> \
  4746. HTT_MSI_SETUP_PDEV_ID_S)
  4747. #define HTT_MSI_SETUP_PDEV_ID_SET(_var, _val) \
  4748. do { \
  4749. HTT_CHECK_SET_VAL(HTT_MSI_SETUP_PDEV_ID, _val); \
  4750. ((_var) |= ((_val) << HTT_MSI_SETUP_PDEV_ID_S)); \
  4751. } while (0)
  4752. #define HTT_MSI_SETUP_MSI_TYPE_M 0x00ff0000
  4753. #define HTT_MSI_SETUP_MSI_TYPE_S 16
  4754. #define HTT_MSI_SETUP_MSI_TYPE_GET(_var) \
  4755. (((_var) & HTT_MSI_SETUP_MSI_TYPE_M) >> \
  4756. HTT_MSI_SETUP_MSI_TYPE_S)
  4757. #define HTT_MSI_SETUP_MSI_TYPE_SET(_var, _val) \
  4758. do { \
  4759. HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_TYPE, _val); \
  4760. ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_TYPE_S)); \
  4761. } while (0)
  4762. #define HTT_MSI_SETUP_MSI_ADDR_LO_M 0xffffffff
  4763. #define HTT_MSI_SETUP_MSI_ADDR_LO_S 0
  4764. #define HTT_MSI_SETUP_MSI_ADDR_LO_GET(_var) \
  4765. (((_var) & HTT_MSI_SETUP_MSI_ADDR_LO_M) >> \
  4766. HTT_MSI_SETUP_MSI_ADDR_LO_S)
  4767. #define HTT_MSI_SETUP_MSI_ADDR_LO_SET(_var, _val) \
  4768. do { \
  4769. HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_ADDR_LO, _val); \
  4770. ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_ADDR_LO_S)); \
  4771. } while (0)
  4772. #define HTT_MSI_SETUP_MSI_ADDR_HI_M 0xffffffff
  4773. #define HTT_MSI_SETUP_MSI_ADDR_HI_S 0
  4774. #define HTT_MSI_SETUP_MSI_ADDR_HI_GET(_var) \
  4775. (((_var) & HTT_MSI_SETUP_MSI_ADDR_HI_M) >> \
  4776. HTT_MSI_SETUP_MSI_ADDR_HI_S)
  4777. #define HTT_MSI_SETUP_MSI_ADDR_HI_SET(_var, _val) \
  4778. do { \
  4779. HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_ADDR_HI, _val); \
  4780. ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_ADDR_HI_S)); \
  4781. } while (0)
  4782. #define HTT_MSI_SETUP_MSI_DATA_M 0xffffffff
  4783. #define HTT_MSI_SETUP_MSI_DATA_S 0
  4784. #define HTT_MSI_SETUP_MSI_DATA_GET(_var) \
  4785. (((_var) & HTT_MSI_SETUP_MSI_DATA_M) >> \
  4786. HTT_MSI_SETUP_MSI_DATA_S)
  4787. #define HTT_MSI_SETUP_MSI_DATA_SET(_var, _val) \
  4788. do { \
  4789. HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_DATA, _val); \
  4790. ((_var) |= ((_val) << HTT_MSI_SETUP_MSI_DATA_S)); \
  4791. } while (0)
  4792. /*
  4793. * @brief host -> target HTT_SRING_SETUP message
  4794. *
  4795. * MSG_TYPE => HTT_H2T_MSG_TYPE_SRING_SETUP
  4796. *
  4797. * @details
  4798. * After target is booted up, Host can send SRING setup message for
  4799. * each host facing LMAC SRING. Target setups up HW registers based
  4800. * on setup message and confirms back to Host if response_required is set.
  4801. * Host should wait for confirmation message before sending new SRING
  4802. * setup message
  4803. *
  4804. * The message would appear as follows:
  4805. * |31 24|23 21|20|19|18 16|15|14 8|7 0|
  4806. * |--------------- +-----------------+-----------------+-----------------|
  4807. * | ring_type | ring_id | pdev_id | msg_type |
  4808. * |----------------------------------------------------------------------|
  4809. * | ring_base_addr_lo |
  4810. * |----------------------------------------------------------------------|
  4811. * | ring_base_addr_hi |
  4812. * |----------------------------------------------------------------------|
  4813. * |ring_misc_cfg_flag|ring_entry_size| ring_size |
  4814. * |----------------------------------------------------------------------|
  4815. * | ring_head_offset32_remote_addr_lo |
  4816. * |----------------------------------------------------------------------|
  4817. * | ring_head_offset32_remote_addr_hi |
  4818. * |----------------------------------------------------------------------|
  4819. * | ring_tail_offset32_remote_addr_lo |
  4820. * |----------------------------------------------------------------------|
  4821. * | ring_tail_offset32_remote_addr_hi |
  4822. * |----------------------------------------------------------------------|
  4823. * | ring_msi_addr_lo |
  4824. * |----------------------------------------------------------------------|
  4825. * | ring_msi_addr_hi |
  4826. * |----------------------------------------------------------------------|
  4827. * | ring_msi_data |
  4828. * |----------------------------------------------------------------------|
  4829. * | intr_timer_th |IM| intr_batch_counter_th |
  4830. * |----------------------------------------------------------------------|
  4831. * | reserved |ID|RR| PTCF| intr_low_threshold |
  4832. * |----------------------------------------------------------------------|
  4833. * | reserved |IPA drop thres hi|IPA drop thres lo|
  4834. * |----------------------------------------------------------------------|
  4835. * Where
  4836. * IM = sw_intr_mode
  4837. * RR = response_required
  4838. * PTCF = prefetch_timer_cfg
  4839. * IP = IPA drop flag
  4840. *
  4841. * The message is interpreted as follows:
  4842. * dword0 - b'0:7 - msg_type: This will be set to
  4843. * 0xb (HTT_H2T_MSG_TYPE_SRING_SETUP)
  4844. * b'8:15 - pdev_id:
  4845. * 0 (for rings at SOC/UMAC level),
  4846. * 1/2/3 mac id (for rings at LMAC level)
  4847. * b'16:23 - ring_id: identify which ring is to setup,
  4848. * more details can be got from enum htt_srng_ring_id
  4849. * b'24:31 - ring_type: identify type of host rings,
  4850. * more details can be got from enum htt_srng_ring_type
  4851. * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address
  4852. * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address
  4853. * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words
  4854. * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
  4855. * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
  4856. * SW_TO_HW_RING.
  4857. * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
  4858. * dword4 - b'0:31 - ring_head_offset32_remote_addr_lo:
  4859. * Lower 32 bits of memory address of the remote variable
  4860. * storing the 4-byte word offset that identifies the head
  4861. * element within the ring.
  4862. * (The head offset variable has type A_UINT32.)
  4863. * Valid for HW_TO_SW and SW_TO_SW rings.
  4864. * dword5 - b'0:31 - ring_head_offset32_remote_addr_hi:
  4865. * Upper 32 bits of memory address of the remote variable
  4866. * storing the 4-byte word offset that identifies the head
  4867. * element within the ring.
  4868. * (The head offset variable has type A_UINT32.)
  4869. * Valid for HW_TO_SW and SW_TO_SW rings.
  4870. * dword6 - b'0:31 - ring_tail_offset32_remote_addr_lo:
  4871. * Lower 32 bits of memory address of the remote variable
  4872. * storing the 4-byte word offset that identifies the tail
  4873. * element within the ring.
  4874. * (The tail offset variable has type A_UINT32.)
  4875. * Valid for HW_TO_SW and SW_TO_SW rings.
  4876. * dword7 - b'0:31 - ring_tail_offset32_remote_addr_hi:
  4877. * Upper 32 bits of memory address of the remote variable
  4878. * storing the 4-byte word offset that identifies the tail
  4879. * element within the ring.
  4880. * (The tail offset variable has type A_UINT32.)
  4881. * Valid for HW_TO_SW and SW_TO_SW rings.
  4882. * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
  4883. * valid only for HW_TO_SW_RING and SW_TO_HW_RING
  4884. * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
  4885. * valid only for HW_TO_SW_RING and SW_TO_HW_RING
  4886. * dword10 - b'0:31 - ring_msi_data: MSI data
  4887. * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
  4888. * valid only for HW_TO_SW_RING and SW_TO_HW_RING
  4889. * dword11 - b'0:14 - intr_batch_counter_th:
  4890. * batch counter threshold is in units of 4-byte words.
  4891. * HW internally maintains and increments batch count.
  4892. * (see SRING spec for detail description).
  4893. * When batch count reaches threshold value, an interrupt
  4894. * is generated by HW.
  4895. * b'15 - sw_intr_mode:
  4896. * This configuration shall be static.
  4897. * Only programmed at power up.
  4898. * 0: generate pulse style sw interrupts
  4899. * 1: generate level style sw interrupts
  4900. * b'16:31 - intr_timer_th:
  4901. * The timer init value when timer is idle or is
  4902. * initialized to start downcounting.
  4903. * In 8us units (to cover a range of 0 to 524 ms)
  4904. * dword12 - b'0:15 - intr_low_threshold:
  4905. * Used only by Consumer ring to generate ring_sw_int_p.
  4906. * Ring entries low threshold water mark, that is used
  4907. * in combination with the interrupt timer as well as
  4908. * the the clearing of the level interrupt.
  4909. * b'16:18 - prefetch_timer_cfg:
  4910. * Used only by Consumer ring to set timer mode to
  4911. * support Application prefetch handling.
  4912. * The external tail offset/pointer will be updated
  4913. * at following intervals:
  4914. * 3'b000: (Prefetch feature disabled; used only for debug)
  4915. * 3'b001: 1 usec
  4916. * 3'b010: 4 usec
  4917. * 3'b011: 8 usec (default)
  4918. * 3'b100: 16 usec
  4919. * Others: Reserved
  4920. * b'19 - response_required:
  4921. * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
  4922. * b'20 - ipa_drop_flag:
  4923. Indicates that host will config ipa drop threshold percentage
  4924. * b'21:31 - reserved: reserved for future use
  4925. * dword13 - b'0:7 - ipa drop low threshold percentage:
  4926. * b'8:15 - ipa drop high threshold percentage:
  4927. * b'16:31 - Reserved
  4928. */
  4929. PREPACK struct htt_sring_setup_t {
  4930. A_UINT32 msg_type: 8,
  4931. pdev_id: 8,
  4932. ring_id: 8,
  4933. ring_type: 8;
  4934. A_UINT32 ring_base_addr_lo;
  4935. A_UINT32 ring_base_addr_hi;
  4936. A_UINT32 ring_size: 16,
  4937. ring_entry_size: 8,
  4938. ring_misc_cfg_flag: 8;
  4939. A_UINT32 ring_head_offset32_remote_addr_lo;
  4940. A_UINT32 ring_head_offset32_remote_addr_hi;
  4941. A_UINT32 ring_tail_offset32_remote_addr_lo;
  4942. A_UINT32 ring_tail_offset32_remote_addr_hi;
  4943. A_UINT32 ring_msi_addr_lo;
  4944. A_UINT32 ring_msi_addr_hi;
  4945. A_UINT32 ring_msi_data;
  4946. A_UINT32 intr_batch_counter_th: 15,
  4947. sw_intr_mode: 1,
  4948. intr_timer_th: 16;
  4949. A_UINT32 intr_low_threshold: 16,
  4950. prefetch_timer_cfg: 3,
  4951. response_required: 1,
  4952. ipa_drop_flag: 1,
  4953. reserved1: 11;
  4954. A_UINT32 ipa_drop_low_threshold: 8,
  4955. ipa_drop_high_threshold: 8,
  4956. reserved: 16;
  4957. } POSTPACK;
  4958. enum htt_srng_ring_type {
  4959. HTT_HW_TO_SW_RING = 0,
  4960. HTT_SW_TO_HW_RING,
  4961. HTT_SW_TO_SW_RING,
  4962. /* Insert new ring types above this line */
  4963. };
  4964. enum htt_srng_ring_id {
  4965. HTT_RXDMA_HOST_BUF_RING = 0, /* Used by FW to feed remote buffers and update remote packets */
  4966. HTT_RXDMA_MONITOR_STATUS_RING, /* For getting all PPDU/MPDU/MSDU status deescriptors on host for monitor VAP or packet log purposes */
  4967. HTT_RXDMA_MONITOR_BUF_RING, /* For feeding free host buffers to RxDMA for monitor traffic upload */
  4968. HTT_RXDMA_MONITOR_DESC_RING, /* For providing free LINK_DESC to RXDMA for monitor traffic upload */
  4969. HTT_RXDMA_MONITOR_DEST_RING, /* Per MPDU indication to host for monitor traffic upload */
  4970. HTT_HOST1_TO_FW_RXBUF_RING, /* (mobile only) used by host to provide remote RX buffers */
  4971. HTT_HOST2_TO_FW_RXBUF_RING, /* (mobile only) second ring used by host to provide remote RX buffers */
  4972. HTT_RXDMA_NON_MONITOR_DEST_RING, /* Per MDPU indication to host for non-monitor RxDMA traffic upload */
  4973. HTT_RXDMA_HOST_BUF_RING2, /* Second ring used by FW to feed removed buffers and update removed packets */
  4974. HTT_TX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */
  4975. HTT_TX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */
  4976. HTT_RX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */
  4977. HTT_RX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */
  4978. HTT_LPASS_TO_FW_RXBUF_RING, /* new LPASS to FW refill ring to recycle rx buffers */
  4979. HTT_HOST3_TO_FW_RXBUF_RING, /* used by host for EasyMesh feature */
  4980. HTT_HOST4_TO_FW_RXBUF_RING, /* fourth ring used by host to provide buffers for MGMT packets */
  4981. /* Add Other SRING which can't be directly configured by host software above this line */
  4982. };
  4983. #define HTT_SRING_SETUP_SZ (sizeof(struct htt_sring_setup_t))
  4984. #define HTT_SRING_SETUP_PDEV_ID_M 0x0000ff00
  4985. #define HTT_SRING_SETUP_PDEV_ID_S 8
  4986. #define HTT_SRING_SETUP_PDEV_ID_GET(_var) \
  4987. (((_var) & HTT_SRING_SETUP_PDEV_ID_M) >> \
  4988. HTT_SRING_SETUP_PDEV_ID_S)
  4989. #define HTT_SRING_SETUP_PDEV_ID_SET(_var, _val) \
  4990. do { \
  4991. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PDEV_ID, _val); \
  4992. ((_var) |= ((_val) << HTT_SRING_SETUP_PDEV_ID_S)); \
  4993. } while (0)
  4994. #define HTT_SRING_SETUP_RING_ID_M 0x00ff0000
  4995. #define HTT_SRING_SETUP_RING_ID_S 16
  4996. #define HTT_SRING_SETUP_RING_ID_GET(_var) \
  4997. (((_var) & HTT_SRING_SETUP_RING_ID_M) >> \
  4998. HTT_SRING_SETUP_RING_ID_S)
  4999. #define HTT_SRING_SETUP_RING_ID_SET(_var, _val) \
  5000. do { \
  5001. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_ID, _val); \
  5002. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_ID_S)); \
  5003. } while (0)
  5004. #define HTT_SRING_SETUP_RING_TYPE_M 0xff000000
  5005. #define HTT_SRING_SETUP_RING_TYPE_S 24
  5006. #define HTT_SRING_SETUP_RING_TYPE_GET(_var) \
  5007. (((_var) & HTT_SRING_SETUP_RING_TYPE_M) >> \
  5008. HTT_SRING_SETUP_RING_TYPE_S)
  5009. #define HTT_SRING_SETUP_RING_TYPE_SET(_var, _val) \
  5010. do { \
  5011. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_TYPE, _val); \
  5012. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_TYPE_S)); \
  5013. } while (0)
  5014. #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_M 0xffffffff
  5015. #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_S 0
  5016. #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_GET(_var) \
  5017. (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_LO_M) >> \
  5018. HTT_SRING_SETUP_RING_BASE_ADDR_LO_S)
  5019. #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_SET(_var, _val) \
  5020. do { \
  5021. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_LO, _val); \
  5022. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_LO_S)); \
  5023. } while (0)
  5024. #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_M 0xffffffff
  5025. #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_S 0
  5026. #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_GET(_var) \
  5027. (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_HI_M) >> \
  5028. HTT_SRING_SETUP_RING_BASE_ADDR_HI_S)
  5029. #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_SET(_var, _val) \
  5030. do { \
  5031. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_HI, _val); \
  5032. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_HI_S)); \
  5033. } while (0)
  5034. #define HTT_SRING_SETUP_RING_SIZE_M 0x0000ffff
  5035. #define HTT_SRING_SETUP_RING_SIZE_S 0
  5036. #define HTT_SRING_SETUP_RING_SIZE_GET(_var) \
  5037. (((_var) & HTT_SRING_SETUP_RING_SIZE_M) >> \
  5038. HTT_SRING_SETUP_RING_SIZE_S)
  5039. #define HTT_SRING_SETUP_RING_SIZE_SET(_var, _val) \
  5040. do { \
  5041. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_SIZE, _val); \
  5042. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_SIZE_S)); \
  5043. } while (0)
  5044. #define HTT_SRING_SETUP_ENTRY_SIZE_M 0x00ff0000
  5045. #define HTT_SRING_SETUP_ENTRY_SIZE_S 16
  5046. #define HTT_SRING_SETUP_ENTRY_SIZE_GET(_var) \
  5047. (((_var) & HTT_SRING_SETUP_ENTRY_SIZE_M) >> \
  5048. HTT_SRING_SETUP_ENTRY_SIZE_S)
  5049. #define HTT_SRING_SETUP_ENTRY_SIZE_SET(_var, _val) \
  5050. do { \
  5051. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_ENTRY_SIZE, _val); \
  5052. ((_var) |= ((_val) << HTT_SRING_SETUP_ENTRY_SIZE_S)); \
  5053. } while (0)
  5054. #define HTT_SRING_SETUP_MISC_CFG_FLAG_M 0xff000000
  5055. #define HTT_SRING_SETUP_MISC_CFG_FLAG_S 24
  5056. #define HTT_SRING_SETUP_MISC_CFG_FLAG_GET(_var) \
  5057. (((_var) & HTT_SRING_SETUP_MISC_CFG_FLAG_M) >> \
  5058. HTT_SRING_SETUP_MISC_CFG_FLAG_S)
  5059. #define HTT_SRING_SETUP_MISC_CFG_FLAG_SET(_var, _val) \
  5060. do { \
  5061. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_MISC_CFG_FLAG, _val); \
  5062. ((_var) |= ((_val) << HTT_SRING_SETUP_MISC_CFG_FLAG_S)); \
  5063. } while (0)
  5064. /* This control bit is applicable to only Producer, which updates Ring ID field
  5065. * of each descriptor before pushing into the ring.
  5066. * 0: updates ring_id(default)
  5067. * 1: ring_id updating disabled */
  5068. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M 0x01000000
  5069. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S 24
  5070. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_GET(_var) \
  5071. (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M) >> \
  5072. HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S)
  5073. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_SET(_var, _val) \
  5074. do { \
  5075. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE, _val); \
  5076. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S)); \
  5077. } while (0)
  5078. /* This control bit is applicable to only Producer, which updates Loopcnt field
  5079. * of each descriptor before pushing into the ring.
  5080. * 0: updates Loopcnt(default)
  5081. * 1: Loopcnt updating disabled */
  5082. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M 0x02000000
  5083. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S 25
  5084. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_GET(_var) \
  5085. (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M) >> \
  5086. HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S)
  5087. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_SET(_var, _val) \
  5088. do { \
  5089. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE, _val); \
  5090. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S)); \
  5091. } while (0)
  5092. /* Secured access enable/disable bit. SRNG drives value of this register bit
  5093. * into security_id port of GXI/AXI. */
  5094. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M 0x04000000
  5095. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S 26
  5096. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_GET(_var) \
  5097. (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M) >> \
  5098. HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S)
  5099. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_SET(_var, _val) \
  5100. do { \
  5101. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY, _val); \
  5102. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S)); \
  5103. } while (0)
  5104. /* During MSI write operation, SRNG drives value of this register bit into
  5105. * swap bit of GXI/AXI. */
  5106. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M 0x08000000
  5107. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S 27
  5108. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_GET(_var) \
  5109. (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M) >> \
  5110. HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S)
  5111. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_SET(_var, _val) \
  5112. do { \
  5113. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP, _val); \
  5114. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S)); \
  5115. } while (0)
  5116. /* During Pointer write operation, SRNG drives value of this register bit into
  5117. * swap bit of GXI/AXI. */
  5118. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M 0x10000000
  5119. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S 28
  5120. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_GET(_var) \
  5121. (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M) >> \
  5122. HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S)
  5123. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_SET(_var, _val) \
  5124. do { \
  5125. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP, _val); \
  5126. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S)); \
  5127. } while (0)
  5128. /* During any data or TLV write operation, SRNG drives value of this register
  5129. * bit into swap bit of GXI/AXI. */
  5130. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M 0x20000000
  5131. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S 29
  5132. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_GET(_var) \
  5133. (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M) >> \
  5134. HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S)
  5135. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_SET(_var, _val) \
  5136. do { \
  5137. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP, _val); \
  5138. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S)); \
  5139. } while (0)
  5140. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RESERVED1 0x40000000
  5141. #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RESERVED2 0x80000000
  5142. #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff
  5143. #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S 0
  5144. #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \
  5145. (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \
  5146. HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S)
  5147. #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \
  5148. do { \
  5149. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \
  5150. ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \
  5151. } while (0)
  5152. #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff
  5153. #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S 0
  5154. #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \
  5155. (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \
  5156. HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S)
  5157. #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \
  5158. do { \
  5159. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \
  5160. ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \
  5161. } while (0)
  5162. #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff
  5163. #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S 0
  5164. #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \
  5165. (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \
  5166. HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S)
  5167. #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \
  5168. do { \
  5169. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \
  5170. ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \
  5171. } while (0)
  5172. #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff
  5173. #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S 0
  5174. #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \
  5175. (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \
  5176. HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S)
  5177. #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \
  5178. do { \
  5179. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \
  5180. ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \
  5181. } while (0)
  5182. #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_M 0xffffffff
  5183. #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_S 0
  5184. #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_GET(_var) \
  5185. (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_LO_M) >> \
  5186. HTT_SRING_SETUP_RING_MSI_ADDR_LO_S)
  5187. #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_SET(_var, _val) \
  5188. do { \
  5189. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_LO, _val); \
  5190. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_LO_S)); \
  5191. } while (0)
  5192. #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_M 0xffffffff
  5193. #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_S 0
  5194. #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_GET(_var) \
  5195. (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_HI_M) >> \
  5196. HTT_SRING_SETUP_RING_MSI_ADDR_HI_S)
  5197. #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_SET(_var, _val) \
  5198. do { \
  5199. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_HI, _val); \
  5200. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_HI_S)); \
  5201. } while (0)
  5202. #define HTT_SRING_SETUP_RING_MSI_DATA_M 0xffffffff
  5203. #define HTT_SRING_SETUP_RING_MSI_DATA_S 0
  5204. #define HTT_SRING_SETUP_RING_MSI_DATA_GET(_var) \
  5205. (((_var) & HTT_SRING_SETUP_RING_MSI_DATA_M) >> \
  5206. HTT_SRING_SETUP_RING_MSI_DATA_S)
  5207. #define HTT_SRING_SETUP_RING_MSI_DATA_SET(_var, _val) \
  5208. do { \
  5209. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_DATA, _val); \
  5210. ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_DATA_S)); \
  5211. } while (0)
  5212. #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M 0x00007fff
  5213. #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S 0
  5214. #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_GET(_var) \
  5215. (((_var) & HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M) >> \
  5216. HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S)
  5217. #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_SET(_var, _val) \
  5218. do { \
  5219. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH, _val); \
  5220. ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S)); \
  5221. } while (0)
  5222. #define HTT_SRING_SETUP_SW_INTR_MODE_M 0x00008000
  5223. #define HTT_SRING_SETUP_SW_INTR_MODE_S 15
  5224. #define HTT_SRING_SETUP_SW_INTR_MODE_GET(_var) \
  5225. (((_var) & HTT_SRING_SETUP_SW_INTR_MODE_M) >> \
  5226. HTT_SRING_SETUP_SW_INTR_MODE_S)
  5227. #define HTT_SRING_SETUP_SW_INTR_MODE_SET(_var, _val) \
  5228. do { \
  5229. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_SW_INTR_MODE, _val); \
  5230. ((_var) |= ((_val) << HTT_SRING_SETUP_SW_INTR_MODE_S)); \
  5231. } while (0)
  5232. #define HTT_SRING_SETUP_INTR_TIMER_TH_M 0xffff0000
  5233. #define HTT_SRING_SETUP_INTR_TIMER_TH_S 16
  5234. #define HTT_SRING_SETUP_INTR_TIMER_TH_GET(_var) \
  5235. (((_var) & HTT_SRING_SETUP_INTR_TIMER_TH_M) >> \
  5236. HTT_SRING_SETUP_INTR_TIMER_TH_S)
  5237. #define HTT_SRING_SETUP_INTR_TIMER_TH_SET(_var, _val) \
  5238. do { \
  5239. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_TIMER_TH, _val); \
  5240. ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_TIMER_TH_S)); \
  5241. } while (0)
  5242. #define HTT_SRING_SETUP_INTR_LOW_TH_M 0x0000ffff
  5243. #define HTT_SRING_SETUP_INTR_LOW_TH_S 0
  5244. #define HTT_SRING_SETUP_INTR_LOW_TH_GET(_var) \
  5245. (((_var) & HTT_SRING_SETUP_INTR_LOW_TH_M) >> \
  5246. HTT_SRING_SETUP_INTR_LOW_TH_S)
  5247. #define HTT_SRING_SETUP_INTR_LOW_TH_SET(_var, _val) \
  5248. do { \
  5249. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_LOW_TH, _val); \
  5250. ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_LOW_TH_S)); \
  5251. } while (0)
  5252. #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M 0x00070000
  5253. #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S 16
  5254. #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_GET(_var) \
  5255. (((_var) & HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M) >> \
  5256. HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S)
  5257. #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_SET(_var, _val) \
  5258. do { \
  5259. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PREFETCH_TIMER_CFG, _val); \
  5260. ((_var) |= ((_val) << HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S)); \
  5261. } while (0)
  5262. #define HTT_SRING_SETUP_RESPONSE_REQUIRED_M 0x00080000
  5263. #define HTT_SRING_SETUP_RESPONSE_REQUIRED_S 19
  5264. #define HTT_SRING_SETUP_RESPONSE_REQUIRED_GET(_var) \
  5265. (((_var) & HTT_SRING_SETUP_RESPONSE_REQUIRED_M) >> \
  5266. HTT_SRING_SETUP_RESPONSE_REQUIRED_S)
  5267. #define HTT_SRING_SETUP_RESPONSE_REQUIRED_SET(_var, _val) \
  5268. do { \
  5269. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RESPONSE_REQUIRED, _val); \
  5270. ((_var) |= ((_val) << HTT_SRING_SETUP_RESPONSE_REQUIRED_S)); \
  5271. } while (0)
  5272. /**
  5273. * @brief host -> target RX ring selection config message
  5274. *
  5275. * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
  5276. *
  5277. * @details
  5278. * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
  5279. * configure RXDMA rings.
  5280. * The configuration is per ring based and includes both packet subtypes
  5281. * and PPDU/MPDU TLVs.
  5282. *
  5283. * The message would appear as follows:
  5284. *
  5285. * |31 29|28|27|26|25|24|23|22|21 19|18 16|15 | 11| 10|9 8|7 0|
  5286. * |-----+--+--+--+--+--+-----------------+----+---+---+---+---------------|
  5287. * |rsvd1|ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type |
  5288. * |--------------------------+-----+-----+--------------------------------|
  5289. * | rsvd2 |RX|RXHDL| CLD | CLC | CLM | ring_buffer_size |
  5290. * |-----------------------------------------------------------------------|
  5291. * | packet_type_enable_flags_0 |
  5292. * |-----------------------------------------------------------------------|
  5293. * | packet_type_enable_flags_1 |
  5294. * |-----------------------------------------------------------------------|
  5295. * | packet_type_enable_flags_2 |
  5296. * |-----------------------------------------------------------------------|
  5297. * | packet_type_enable_flags_3 |
  5298. * |-----------------------------------------------------------------------|
  5299. * | tlv_filter_in_flags |
  5300. * |--------------------------------------+--------------------------------|
  5301. * | rx_header_offset | rx_packet_offset |
  5302. * |--------------------------------------+--------------------------------|
  5303. * | rx_mpdu_start_offset | rx_mpdu_end_offset |
  5304. * |--------------------------------------+--------------------------------|
  5305. * | rx_msdu_start_offset | rx_msdu_end_offset |
  5306. * |--------------------------------------+--------------------------------|
  5307. * | rsvd3 | rx_attention_offset |
  5308. * |-----------------------------------------------------------------------|
  5309. * | rsvd4 | mo| fp| rx_drop_threshold |
  5310. * | |ndp|ndp| |
  5311. * |-----------------------------------------------------------------------|
  5312. * Where:
  5313. * PS = pkt_swap
  5314. * SS = status_swap
  5315. * OV = rx_offsets_valid
  5316. * DT = drop_thresh_valid
  5317. * ED = packet type enable data flags fields present / valid
  5318. * CLM = config_length_mgmt
  5319. * CLC = config_length_ctrl
  5320. * CLD = config_length_data
  5321. * RXHDL = rx_hdr_len
  5322. * RX = rxpcu_filter_enable_flag
  5323. * The message is interpreted as follows:
  5324. * dword0 - b'0:7 - msg_type: This will be set to
  5325. * 0xc (HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG)
  5326. * b'8:15 - pdev_id:
  5327. * 0 (for rings at SOC/UMAC level),
  5328. * 1/2/3 mac id (for rings at LMAC level)
  5329. * b'16:23 - ring_id : Identify the ring to configure.
  5330. * More details can be got from enum htt_srng_ring_id
  5331. * b'24 - status_swap (SS): 1 is to swap status TLV - refer to
  5332. * BUF_RING_CFG_0 defs within HW .h files,
  5333. * e.g. wmac_top_reg_seq_hwioreg.h
  5334. * b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to
  5335. * BUF_RING_CFG_0 defs within HW .h files,
  5336. * e.g. wmac_top_reg_seq_hwioreg.h
  5337. * b'26 - rx_offset_valid (OV): flag to indicate rx offsets
  5338. * configuration fields are valid
  5339. * b'27 - drop_thresh_valid (DT): flag to indicate if the
  5340. * rx_drop_threshold field is valid
  5341. * b'28 - rx_mon_global_en: Enable/Disable global register
  5342. * configuration in Rx monitor module.
  5343. * b'29 - packet_type_enable_data: flag to indicate whether
  5344. * newer packet_type_enable_data_flags_* are valid or not
  5345. * If not set, will use pkt_type_enable_flags for both status
  5346. * and full pkt buffer configuration.
  5347. * b'30:31 - rsvd1: reserved for future use
  5348. * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring,
  5349. * in byte units.
  5350. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
  5351. * b'16:18 - config_length_mgmt (MGMT):
  5352. * Represents the length of mpdu bytes for mgmt pkt.
  5353. * valid values:
  5354. * 001 - 64bytes
  5355. * 010 - 128bytes
  5356. * 100 - 256bytes
  5357. * 111 - Full mpdu bytes
  5358. * b'19:21 - config_length_ctrl (CTRL):
  5359. * Represents the length of mpdu bytes for ctrl pkt.
  5360. * valid values:
  5361. * 001 - 64bytes
  5362. * 010 - 128bytes
  5363. * 100 - 256bytes
  5364. * 111 - Full mpdu bytes
  5365. * b'22:24 - config_length_data (DATA):
  5366. * Represents the length of mpdu bytes for data pkt.
  5367. * valid values:
  5368. * 001 - 64bytes
  5369. * 010 - 128bytes
  5370. * 100 - 256bytes
  5371. * 111 - Full mpdu bytes
  5372. * b'25:26 - rx_hdr_len:
  5373. * Specifies the number of bytes of recvd packet to copy
  5374. * into the rx_hdr tlv.
  5375. * supported values for now by host:
  5376. * 01 - 64bytes
  5377. * 10 - 128bytes
  5378. * 11 - 256bytes
  5379. * default - 128 bytes
  5380. * b'27 - rxpcu_filter_enable_flag
  5381. * For Scan Radio Host CPU utilization is very high.
  5382. * In order to reduce CPU utilization we need to filter out
  5383. * certain configured MAC frames.
  5384. * To filter out configured MAC address frames, RxPCU should
  5385. * be zero which means allow all frames for MD at RxOLE
  5386. * host wil fiter out frames.
  5387. * RxPCU (Filter IN) -> RxOLE (Filter In/Filter Out)
  5388. * b'28:31 - rsvd2: Reserved for future use
  5389. * dword2 - b'0:31 - packet_type_enable_flags_0:
  5390. * Enable MGMT packet from 0b0000 to 0b1001
  5391. * bits from low to high: FP, MD, MO - 3 bits
  5392. * FP: Filter_Pass
  5393. * MD: Monitor_Direct
  5394. * MO: Monitor_Other
  5395. * 10 mgmt subtypes * 3 bits -> 30 bits
  5396. * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
  5397. * dword3 - b'0:31 - packet_type_enable_flags_1:
  5398. * Enable MGMT packet from 0b1010 to 0b1111
  5399. * bits from low to high: FP, MD, MO - 3 bits
  5400. * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
  5401. * dword4 - b'0:31 - packet_type_enable_flags_2:
  5402. * Enable CTRL packet from 0b0000 to 0b1001
  5403. * bits from low to high: FP, MD, MO - 3 bits
  5404. * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
  5405. * dword5 - b'0:31 - packet_type_enable_flags_3:
  5406. * Enable CTRL packet from 0b1010 to 0b1111,
  5407. * MCAST_DATA, UCAST_DATA, NULL_DATA
  5408. * bits from low to high: FP, MD, MO - 3 bits
  5409. * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
  5410. * dword6 - b'0:31 - tlv_filter_in_flags:
  5411. * Filter in Attention/MPDU/PPDU/Header/User tlvs
  5412. * Refer to CFG_TLV_FILTER_IN_FLAG defs
  5413. * dword7 - b'0:15 - rx_packet_offset: rx_packet_offset in byte units
  5414. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
  5415. * A value of 0 will be considered as ignore this config.
  5416. * Refer to BUF_RING_CFG_1 defs within HW .h files,
  5417. * e.g. wmac_top_reg_seq_hwioreg.h
  5418. * - b'16:31 - rx_header_offset: rx_header_offset in byte units
  5419. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
  5420. * A value of 0 will be considered as ignore this config.
  5421. * Refer to BUF_RING_CFG_1 defs within HW .h files,
  5422. * e.g. wmac_top_reg_seq_hwioreg.h
  5423. * dword8 - b'0:15 - rx_mpdu_end_offset: rx_mpdu_end_offset in byte units
  5424. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
  5425. * A value of 0 will be considered as ignore this config.
  5426. * Refer to BUF_RING_CFG_2 defs within HW .h files,
  5427. * e.g. wmac_top_reg_seq_hwioreg.h
  5428. * - b'16:31 - rx_mpdu_start_offset: rx_mpdu_start_offset in byte units
  5429. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
  5430. * A value of 0 will be considered as ignore this config.
  5431. * Refer to BUF_RING_CFG_2 defs within HW .h files,
  5432. * e.g. wmac_top_reg_seq_hwioreg.h
  5433. * dword9 - b'0:15 - rx_msdu_end_offset: rx_msdu_end_offset in byte units
  5434. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
  5435. * A value of 0 will be considered as ignore this config.
  5436. * Refer to BUF_RING_CFG_3 defs within HW .h files,
  5437. * e.g. wmac_top_reg_seq_hwioreg.h
  5438. * - b'16:31 - rx_msdu_start_offset: rx_msdu_start_offset in byte units
  5439. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
  5440. * A value of 0 will be considered as ignore this config.
  5441. * Refer to BUF_RING_CFG_3 defs within HW .h files,
  5442. * e.g. wmac_top_reg_seq_hwioreg.h
  5443. * dword10- b'0:15 - rx_attention_offset: rx_attention_offset in byte units
  5444. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
  5445. * A value of 0 will be considered as ignore this config.
  5446. * Refer to BUF_RING_CFG_4 defs within HW .h files,
  5447. * e.g. wmac_top_reg_seq_hwioreg.h
  5448. * - b'16:31 - rsvd3 for future use
  5449. * dword11- b'9:0 - rx_drop_threshold: Threshold configured in monitor mode
  5450. * to source rings. Consumer drops packets if the available
  5451. * words in the ring falls below the configured threshold
  5452. * value.
  5453. * - b'10 - fp_ndp: Flag to indicate FP NDP status tlv is subscribed
  5454. * by host. 1 -> subscribed
  5455. * - b'11 - mo_ndp: Flag to indicate MO NDP status tlv is subscribed
  5456. * by host. 1 -> subscribed
  5457. * - b'12 - fp_phy_err: Flag to indicate FP PHY status tlv is
  5458. * subscribed by host. 1 -> subscribed
  5459. * - b'13:14 - fp_phy_err_buf_src: This indicates the source ring
  5460. * selection for the FP PHY ERR status tlv.
  5461. * 0 - wbm2rxdma_buf_source_ring
  5462. * 1 - fw2rxdma_buf_source_ring
  5463. * 2 - sw2rxdma_buf_source_ring
  5464. * 3 - no_buffer_ring
  5465. * - b'15:16 - fp_phy_err_buf_dest: This indicates the destination ring
  5466. * selection for the FP PHY ERR status tlv.
  5467. * 0 - rxdma_release_ring
  5468. * 1 - rxdma2fw_ring
  5469. * 2 - rxdma2sw_ring
  5470. * 3 - rxdma2reo_ring
  5471. * - b'17:19 - pkt_type_en_msdu_or_mpdu_logging
  5472. * b'17 - Enables MSDU/MPDU logging for frames of MGMT type
  5473. * b'18 - Enables MSDU/MPDU logging for frames of CTRL type
  5474. * b'19 - Enables MSDU/MPDU logging for frames of DATA type
  5475. * - b'20 - dma_mpdu_mgmt: 1: MPDU level logging
  5476. * 0: MSDU level logging
  5477. * - b'21 - dma_mpdu_ctrl: 1: MPDU level logging
  5478. * 0: MSDU level logging
  5479. * - b'22 - dma_mpdu_data: 1: MPDU level logging
  5480. * 0: MSDU level logging
  5481. * - b'23 - word_mask_compaction: enable/disable word mask for
  5482. * mpdu/msdu start/end tlvs
  5483. * - b'24 - rbm_override_enable: enabling/disabling return buffer
  5484. * manager override
  5485. * - b'25:28 - rbm_override_val: return buffer manager override value
  5486. * dword12- b'0:31 - phy_err_mask: This field is to select the fp phy errors
  5487. * which have to be posted to host from phy.
  5488. * Corresponding to errors defined in
  5489. * phyrx_abort_request_reason enums 0 to 31.
  5490. * Refer to RXPCU register definition header files for the
  5491. * phyrx_abort_request_reason enum definition.
  5492. * dword13- b'0:31 - phy_err_mask_cont: This field is to select the fp phy
  5493. * errors which have to be posted to host from phy.
  5494. * Corresponding to errors defined in
  5495. * phyrx_abort_request_reason enums 32 to 63.
  5496. * Refer to RXPCU register definition header files for the
  5497. * phyrx_abort_request_reason enum definition.
  5498. * dword14- b'0:15 - rx_mpdu_start_word_mask: word mask for rx mpdu start,
  5499. * applicable if word mask enabled
  5500. * - b'16:18 - rx_mpdu_end_word_mask: word mask value for rx mpdu end,
  5501. * applicable if word mask enabled
  5502. * - b'19:31 - rsvd7
  5503. * dword15- b'0:16 - rx_msdu_end_word_mask
  5504. * - b'17:31 - rsvd5
  5505. * dword17- b'0 - en_rx_tlv_pkt_offset:
  5506. * 0: RX_PKT TLV logging at offset 0 for the subsequent
  5507. * buffer
  5508. * 1: RX_PKT TLV logging at specified offset for the
  5509. * subsequent buffer
  5510. * b`15:1 - rx_pkt_tlv_offset: Qword offset for rx_packet TLVs.
  5511. * dword18- b'0:19 - rx_mpdu_start_wmask_v2 - wmask address for rx mpdu start
  5512. * b'20-27 - rx_mpdu_end_wmask_v2 - wmask addr for rx mpdu end tlv addr
  5513. * b'28-31 - reserved
  5514. * dword19- b'0-19 - rx_msdu_end_wmask_v2
  5515. * b'20-31 - reserved
  5516. * dword20- b'0:19 - rx_ppdu_end_user_stats_wmask_v2
  5517. * offset for ppdu_end_user_stats tlv
  5518. * b'20-31 - reserved
  5519. * dword21- b'0-31 - packet_type_enable_fpmo_flags_0 - filter bmap for each
  5520. * mode mgmt/ctrl type/subtype for fpmo mode
  5521. * dword22- b'0-31 - packet_type_enable_fpmo_flags_1 - filter bmap for each
  5522. * mode ctrl/data type/subtype for fpmo mode
  5523. * dword23- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full
  5524. * pkt buffer each mode MGMT type/subtype
  5525. * dword24- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full
  5526. * pkt buffer each mode MGMT type/subtype
  5527. * dword25- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full
  5528. * pkt buffer each mode CTRL type/subtype
  5529. * dword26- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full
  5530. * pkt buffer each mode CTRL/DATA type/subtype
  5531. * dword27- b'0-31 - packet_type_enable_data_fpmo_flags_0 - filter bmap for
  5532. * full pkt buffer each mode mgmt/ctrl type/subtype for
  5533. * fpmo mode
  5534. * dword28- b'0-31 - packet_type_enable_data_fpmo_flags_1 - filter bmap for
  5535. * full pkt buffer each mode ctrl/data type/subtype for
  5536. * fpmo mode
  5537. */
  5538. PREPACK struct htt_rx_ring_selection_cfg_t {
  5539. A_UINT32 msg_type: 8,
  5540. pdev_id: 8,
  5541. ring_id: 8,
  5542. status_swap: 1,
  5543. pkt_swap: 1,
  5544. rx_offsets_valid: 1,
  5545. drop_thresh_valid: 1,
  5546. rx_mon_global_en: 1,
  5547. packet_type_enable_data: 1,
  5548. rsvd1: 2;
  5549. A_UINT32 ring_buffer_size: 16,
  5550. config_length_mgmt:3,
  5551. config_length_ctrl:3,
  5552. config_length_data:3,
  5553. rx_hdr_len: 2,
  5554. rxpcu_filter_enable_flag:1,
  5555. rsvd2: 4;
  5556. A_UINT32 packet_type_enable_flags_0;
  5557. A_UINT32 packet_type_enable_flags_1;
  5558. A_UINT32 packet_type_enable_flags_2;
  5559. A_UINT32 packet_type_enable_flags_3;
  5560. A_UINT32 tlv_filter_in_flags;
  5561. A_UINT32 rx_packet_offset: 16,
  5562. rx_header_offset: 16;
  5563. A_UINT32 rx_mpdu_end_offset: 16,
  5564. rx_mpdu_start_offset: 16;
  5565. A_UINT32 rx_msdu_end_offset: 16,
  5566. rx_msdu_start_offset: 16;
  5567. A_UINT32 rx_attn_offset: 16,
  5568. rsvd3: 16;
  5569. A_UINT32 rx_drop_threshold: 10,
  5570. fp_ndp: 1,
  5571. mo_ndp: 1,
  5572. fp_phy_err: 1,
  5573. fp_phy_err_buf_src: 2,
  5574. fp_phy_err_buf_dest: 2,
  5575. pkt_type_enable_msdu_or_mpdu_logging:3,
  5576. dma_mpdu_mgmt: 1,
  5577. dma_mpdu_ctrl: 1,
  5578. dma_mpdu_data: 1,
  5579. word_mask_compaction_enable:1,
  5580. rbm_override_enable: 1,
  5581. rbm_override_val: 4,
  5582. rsvd4: 3;
  5583. A_UINT32 phy_err_mask;
  5584. A_UINT32 phy_err_mask_cont;
  5585. A_UINT32 rx_mpdu_start_word_mask:16,
  5586. rx_mpdu_end_word_mask: 3,
  5587. rsvd7: 13;
  5588. A_UINT32 rx_msdu_end_word_mask: 17,
  5589. rsvd5: 15;
  5590. A_UINT32 en_rx_tlv_pkt_offset: 1,
  5591. rx_pkt_tlv_offset: 15,
  5592. rsvd6: 16;
  5593. A_UINT32 rx_mpdu_start_word_mask_v2: 20,
  5594. rx_mpdu_end_word_mask_v2: 8,
  5595. rsvd8: 4;
  5596. A_UINT32 rx_msdu_end_word_mask_v2: 20,
  5597. rsvd9: 12;
  5598. A_UINT32 rx_ppdu_end_usr_stats_word_mask_v2: 20,
  5599. rsvd10: 12;
  5600. A_UINT32 packet_type_enable_fpmo_flags0;
  5601. A_UINT32 packet_type_enable_fpmo_flags1;
  5602. A_UINT32 packet_type_enable_data_flags_0;
  5603. A_UINT32 packet_type_enable_data_flags_1;
  5604. A_UINT32 packet_type_enable_data_flags_2;
  5605. A_UINT32 packet_type_enable_data_flags_3;
  5606. A_UINT32 packet_type_enable_data_fpmo_flags0;
  5607. A_UINT32 packet_type_enable_data_fpmo_flags1;
  5608. } POSTPACK;
  5609. #define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t))
  5610. #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_M 0x0000ff00
  5611. #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_S 8
  5612. #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_GET(_var) \
  5613. (((_var) & HTT_RX_RING_SELECTION_CFG_PDEV_ID_M) >> \
  5614. HTT_RX_RING_SELECTION_CFG_PDEV_ID_S)
  5615. #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_SET(_var, _val) \
  5616. do { \
  5617. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PDEV_ID, _val); \
  5618. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PDEV_ID_S)); \
  5619. } while (0)
  5620. #define HTT_RX_RING_SELECTION_CFG_RING_ID_M 0x00ff0000
  5621. #define HTT_RX_RING_SELECTION_CFG_RING_ID_S 16
  5622. #define HTT_RX_RING_SELECTION_CFG_RING_ID_GET(_var) \
  5623. (((_var) & HTT_RX_RING_SELECTION_CFG_RING_ID_M) >> \
  5624. HTT_RX_RING_SELECTION_CFG_RING_ID_S)
  5625. #define HTT_RX_RING_SELECTION_CFG_RING_ID_SET(_var, _val) \
  5626. do { \
  5627. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_ID, _val); \
  5628. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_ID_S)); \
  5629. } while (0)
  5630. #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M 0x01000000
  5631. #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S 24
  5632. #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_GET(_var) \
  5633. (((_var) & HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M) >> \
  5634. HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S)
  5635. #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SET(_var, _val) \
  5636. do { \
  5637. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP, _val); \
  5638. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S)); \
  5639. } while (0)
  5640. #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M 0x02000000
  5641. #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S 25
  5642. #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_GET(_var) \
  5643. (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M) >> \
  5644. HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S)
  5645. #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SET(_var, _val) \
  5646. do { \
  5647. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP, _val); \
  5648. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S)); \
  5649. } while (0)
  5650. #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M 0x04000000
  5651. #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S 26
  5652. #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_GET(_var) \
  5653. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M) >> \
  5654. HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S)
  5655. #define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_SET(_var, _val) \
  5656. do { \
  5657. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID, _val); \
  5658. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S)); \
  5659. } while (0)
  5660. #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_M 0x08000000
  5661. #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S 27
  5662. #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_GET(_var) \
  5663. (((_var) & HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_M) >> \
  5664. HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S)
  5665. #define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_SET(_var, _val) \
  5666. do { \
  5667. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID, _val); \
  5668. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S)); \
  5669. } while (0)
  5670. #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_M 0x10000000
  5671. #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S 28
  5672. #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_GET(_var) \
  5673. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_M) >> \
  5674. HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S)
  5675. #define HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_SET(_var, _val) \
  5676. do { \
  5677. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN, _val); \
  5678. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S)); \
  5679. } while (0)
  5680. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_M 0x20000000
  5681. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S 29
  5682. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_GET(_var) \
  5683. (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_M) >> \
  5684. HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S)
  5685. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_SET(_var, _val) \
  5686. do { \
  5687. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA, _val); \
  5688. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S)); \
  5689. } while (0)
  5690. #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M 0x0000ffff
  5691. #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S 0
  5692. #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \
  5693. (((_var) & HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M) >> \
  5694. HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S)
  5695. #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_SET(_var, _val) \
  5696. do { \
  5697. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE, _val); \
  5698. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S)); \
  5699. } while (0)
  5700. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_M 0x00070000
  5701. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S 16
  5702. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_GET(_var) \
  5703. (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_M) >> \
  5704. HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S)
  5705. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_SET(_var, _val) \
  5706. do { \
  5707. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT, _val); \
  5708. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_MGMT_S)); \
  5709. } while (0)
  5710. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_M 0x00380000
  5711. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S 19
  5712. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_GET(_var) \
  5713. (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_M) >> \
  5714. HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S)
  5715. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_SET(_var, _val) \
  5716. do { \
  5717. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL, _val); \
  5718. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_CTRL_S)); \
  5719. } while (0)
  5720. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_M 0x01C00000
  5721. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S 22
  5722. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_GET(_var) \
  5723. (((_var) & HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_M) >> \
  5724. HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S)
  5725. #define HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_SET(_var, _val) \
  5726. do { \
  5727. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA, _val); \
  5728. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_CONFIG_LENGTH_DATA_S)); \
  5729. } while (0)
  5730. #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M 0x06000000
  5731. #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S 25
  5732. #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_GET(_var) \
  5733. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M) >> \
  5734. HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S)
  5735. #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_SET(_var, _val) \
  5736. do { \
  5737. HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN, _val); \
  5738. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S));\
  5739. } while(0)
  5740. #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M 0x08000000
  5741. #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S 27
  5742. #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_GET(_var) \
  5743. (((_var) & HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M) >> \
  5744. HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S)
  5745. #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_SET(_var, _val) \
  5746. do { \
  5747. HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER, _val); \
  5748. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S));\
  5749. } while(0)
  5750. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M 0xffffffff
  5751. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S 0
  5752. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_GET(_var) \
  5753. (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M) >> \
  5754. HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S)
  5755. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_SET(_var, _val) \
  5756. do { \
  5757. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0, _val); \
  5758. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S)); \
  5759. } while (0)
  5760. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M 0xffffffff
  5761. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S 0
  5762. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_GET(_var) \
  5763. (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M) >> \
  5764. HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S)
  5765. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_SET(_var, _val) \
  5766. do { \
  5767. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1, _val); \
  5768. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S)); \
  5769. } while (0)
  5770. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M 0xffffffff
  5771. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S 0
  5772. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_GET(_var) \
  5773. (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M) >> \
  5774. HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S)
  5775. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_SET(_var, _val) \
  5776. do { \
  5777. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2, _val); \
  5778. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S)); \
  5779. } while (0)
  5780. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M 0xffffffff
  5781. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S 0
  5782. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_GET(_var) \
  5783. (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M) >> \
  5784. HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S)
  5785. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_SET(_var, _val) \
  5786. do { \
  5787. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3, _val); \
  5788. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S)); \
  5789. } while (0)
  5790. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M 0xffffffff
  5791. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S 0
  5792. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_GET(_var) \
  5793. (((_var) & HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M) >> \
  5794. HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S)
  5795. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_SET(_var, _val) \
  5796. do { \
  5797. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG, _val); \
  5798. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S)); \
  5799. } while (0)
  5800. #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M 0x0000ffff
  5801. #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S 0
  5802. #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_GET(_var) \
  5803. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M) >> \
  5804. HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S)
  5805. #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_SET(_var, _val) \
  5806. do { \
  5807. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET, _val); \
  5808. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S)); \
  5809. } while (0)
  5810. #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M 0xffff0000
  5811. #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S 16
  5812. #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_GET(_var) \
  5813. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M) >> \
  5814. HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S)
  5815. #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_SET(_var, _val) \
  5816. do { \
  5817. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET, _val); \
  5818. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S)); \
  5819. } while (0)
  5820. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M 0x0000ffff
  5821. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S 0
  5822. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_GET(_var) \
  5823. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M) >> \
  5824. HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S)
  5825. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_SET(_var, _val) \
  5826. do { \
  5827. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET, _val); \
  5828. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S)); \
  5829. } while (0)
  5830. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M 0xffff0000
  5831. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S 16
  5832. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_GET(_var) \
  5833. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M) >> \
  5834. HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S)
  5835. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_SET(_var, _val) \
  5836. do { \
  5837. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET, _val); \
  5838. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S)); \
  5839. } while (0)
  5840. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M 0x0000ffff
  5841. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S 0
  5842. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_GET(_var) \
  5843. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M) >> \
  5844. HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S)
  5845. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_SET(_var, _val) \
  5846. do { \
  5847. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET, _val); \
  5848. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S)); \
  5849. } while (0)
  5850. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M 0xffff0000
  5851. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S 16
  5852. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_GET(_var) \
  5853. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M) >> \
  5854. HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S)
  5855. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_SET(_var, _val) \
  5856. do { \
  5857. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET, _val); \
  5858. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S)); \
  5859. } while (0)
  5860. #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M 0x0000ffff
  5861. #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S 0
  5862. #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_GET(_var) \
  5863. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M) >> \
  5864. HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S)
  5865. #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_SET(_var, _val) \
  5866. do { \
  5867. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET, _val); \
  5868. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S)); \
  5869. } while (0)
  5870. #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_M 0x000003ff
  5871. #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S 0
  5872. #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_GET(_var) \
  5873. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_M) >> \
  5874. HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S)
  5875. #define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_SET(_var, _val) \
  5876. do { \
  5877. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD, _val); \
  5878. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S)); \
  5879. } while (0)
  5880. #define HTT_RX_RING_SELECTION_CFG_FP_NDP_M 0x00000400
  5881. #define HTT_RX_RING_SELECTION_CFG_FP_NDP_S 10
  5882. #define HTT_RX_RING_SELECTION_CFG_FP_NDP_GET(_var) \
  5883. (((_var) & HTT_RX_RING_SELECTION_CFG_FP_NDP_M) >> \
  5884. HTT_RX_RING_SELECTION_CFG_FP_NDP_S)
  5885. #define HTT_RX_RING_SELECTION_CFG_FP_NDP_SET(_var, _val) \
  5886. do { \
  5887. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_NDP, _val); \
  5888. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_NDP_S)); \
  5889. } while (0)
  5890. #define HTT_RX_RING_SELECTION_CFG_MO_NDP_M 0x00000800
  5891. #define HTT_RX_RING_SELECTION_CFG_MO_NDP_S 11
  5892. #define HTT_RX_RING_SELECTION_CFG_MO_NDP_GET(_var) \
  5893. (((_var) & HTT_RX_RING_SELECTION_CFG_MO_NDP_M) >> \
  5894. HTT_RX_RING_SELECTION_CFG_MO_NDP_S)
  5895. #define HTT_RX_RING_SELECTION_CFG_MO_NDP_SET(_var, _val) \
  5896. do { \
  5897. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_MO_NDP, _val); \
  5898. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_MO_NDP_S)); \
  5899. } while (0)
  5900. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_M 0x00001000
  5901. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S 12
  5902. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_GET(_var) \
  5903. (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_M) >> \
  5904. HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S)
  5905. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_SET(_var, _val) \
  5906. do { \
  5907. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR, _val); \
  5908. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S)); \
  5909. } while (0)
  5910. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_M 0x00006000
  5911. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S 13
  5912. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_GET(_var) \
  5913. (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_M) >> \
  5914. HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S)
  5915. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_SET(_var, _val) \
  5916. do { \
  5917. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC, _val); \
  5918. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S)); \
  5919. } while (0)
  5920. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_M 0x00018000
  5921. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S 15
  5922. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_GET(_var) \
  5923. (((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_M) >> \
  5924. HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S)
  5925. #define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_SET(_var, _val) \
  5926. do { \
  5927. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST, _val); \
  5928. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S)); \
  5929. } while (0)
  5930. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_M 0x000E0000
  5931. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S 17
  5932. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_GET(_var) \
  5933. (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_M) >> \
  5934. HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S)
  5935. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_SET(_var, _val) \
  5936. do { \
  5937. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING, _val); \
  5938. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_MSDU_MPDU_LOGGING_S)); \
  5939. } while (0)
  5940. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_M 0x00100000
  5941. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S 20
  5942. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_GET(_var) \
  5943. (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_M) >> \
  5944. HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S)
  5945. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_SET(_var, _val) \
  5946. do { \
  5947. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT, _val); \
  5948. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_MGMT_S)); \
  5949. } while (0)
  5950. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_M 0x00200000
  5951. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S 21
  5952. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_GET(_var) \
  5953. (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_M) >> \
  5954. HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S)
  5955. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_SET(_var, _val) \
  5956. do { \
  5957. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL, _val); \
  5958. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_CTRL_S)); \
  5959. } while (0)
  5960. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_M 0x00400000
  5961. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S 22
  5962. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_GET(_var) \
  5963. (((_var) & HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_M) >> \
  5964. HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S)
  5965. #define HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_SET(_var, _val) \
  5966. do { \
  5967. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA, _val); \
  5968. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DMA_MPDU_DATA_S)); \
  5969. } while (0)
  5970. #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_M 0x00800000
  5971. #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S 23
  5972. #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_GET(_var) \
  5973. (((_var) & HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_M) >> \
  5974. HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S)
  5975. #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_SET(_var, _val) \
  5976. do { \
  5977. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE, _val); \
  5978. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_S)); \
  5979. } while (0)
  5980. #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_M 0x01000000
  5981. #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S 24
  5982. #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_GET(_var) \
  5983. (((_var) & HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_M) >> \
  5984. HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S)
  5985. #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_SET(_var, _val) \
  5986. do { \
  5987. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE, _val);\
  5988. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_ENABLE_S)); \
  5989. } while (0)
  5990. #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_M 0x1E000000
  5991. #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S 25
  5992. #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_GET(_var) \
  5993. (((_var) & HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_M) >> \
  5994. HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S)
  5995. #define HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_SET(_var, _val) \
  5996. do { \
  5997. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE, _val);\
  5998. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RBM_OVERRIDE_VALUE_S));\
  5999. } while (0)
  6000. #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_M 0xffffffff
  6001. #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S 0
  6002. #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_GET(_var) \
  6003. (((_var) & HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_M) >> \
  6004. HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S)
  6005. #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_SET(_var, _val) \
  6006. do { \
  6007. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK, _val); \
  6008. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S)); \
  6009. } while (0)
  6010. #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_M 0xffffffff
  6011. #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S 0
  6012. #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_GET(_var) \
  6013. (((_var) & HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_M) >> \
  6014. HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S)
  6015. #define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_SET(_var, _val) \
  6016. do { \
  6017. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT, _val); \
  6018. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S)); \
  6019. } while (0)
  6020. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_M 0x0000FFFF
  6021. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S 0
  6022. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_GET(_var) \
  6023. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_M)>> \
  6024. HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S)
  6025. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_SET(_var, _val) \
  6026. do { \
  6027. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK, _val);\
  6028. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_S)); \
  6029. } while (0)
  6030. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M 0x00070000
  6031. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S 16
  6032. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_GET(_var) \
  6033. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_M)>> \
  6034. HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S)
  6035. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_SET(_var, _val) \
  6036. do { \
  6037. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK, _val);\
  6038. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_S)); \
  6039. } while (0)
  6040. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_M 0x0001FFFF
  6041. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S 0
  6042. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_GET(_var) \
  6043. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_M)>> \
  6044. HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S)
  6045. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_SET(_var, _val) \
  6046. do { \
  6047. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK, _val);\
  6048. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_S)); \
  6049. } while (0)
  6050. #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_M 0x00000001
  6051. #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S 0
  6052. #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_GET(_var) \
  6053. (((_var) & HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_M)>> \
  6054. HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S)
  6055. #define HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_SET(_var, _val) \
  6056. do { \
  6057. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET, _val); \
  6058. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_ENABLE_RX_PKT_TLV_OFFSET_S)); \
  6059. } while (0)
  6060. #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_M 0x0000FFFE
  6061. #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S 1
  6062. #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_GET(_var) \
  6063. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_M)>> \
  6064. HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S)
  6065. #define HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_SET(_var, _val) \
  6066. do { \
  6067. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET, _val); \
  6068. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PKT_TLV_OFFSET_S)); \
  6069. } while (0)
  6070. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_M 0x000FFFFF
  6071. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S 0
  6072. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_GET(_var) \
  6073. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_M)>> \
  6074. HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S)
  6075. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_SET(_var, _val) \
  6076. do { \
  6077. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2, _val);\
  6078. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_V2_S)); \
  6079. } while (0)
  6080. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_M 0x0FF00000
  6081. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S 20
  6082. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_GET(_var) \
  6083. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_M)>> \
  6084. HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S)
  6085. #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_SET(_var, _val) \
  6086. do { \
  6087. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2, _val);\
  6088. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_V2_S)); \
  6089. } while (0)
  6090. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_M 0x000FFFFF
  6091. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S 0
  6092. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_GET(_var) \
  6093. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_M)>> \
  6094. HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S)
  6095. #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_SET(_var, _val) \
  6096. do { \
  6097. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2, _val);\
  6098. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_V2_S)); \
  6099. } while (0)
  6100. #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_M 0x000FFFFF
  6101. #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S 0
  6102. #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_GET(_var) \
  6103. (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_M)>> \
  6104. HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S)
  6105. #define HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_SET(_var, _val) \
  6106. do { \
  6107. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2, _val);\
  6108. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PPDU_END_USR_STATS_WORD_MASK_V2_S)); \
  6109. } while (0)
  6110. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_M 0xFFFFFFFF
  6111. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S 0
  6112. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_GET(_var) \
  6113. (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_M)>> \
  6114. HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S)
  6115. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_SET(_var, _val) \
  6116. do { \
  6117. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0, _val); \
  6118. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS0_S)); \
  6119. } while (0)
  6120. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_M 0xFFFFFFFF
  6121. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S 0
  6122. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_GET(_var) \
  6123. (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_M)>> \
  6124. HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S)
  6125. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_SET(_var, _val) \
  6126. do { \
  6127. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1, _val); \
  6128. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S)); \
  6129. } while (0)
  6130. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_M 0xffffffff
  6131. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_S 0
  6132. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_GET(_var) \
  6133. (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_M) >> \
  6134. HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_S)
  6135. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_SET(_var, _val) \
  6136. do { \
  6137. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0, _val); \
  6138. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_S)); \
  6139. } while (0)
  6140. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_M 0xffffffff
  6141. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_S 0
  6142. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_GET(_var) \
  6143. (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_M) >> \
  6144. HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_S)
  6145. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_SET(_var, _val) \
  6146. do { \
  6147. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1, _val); \
  6148. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_S)); \
  6149. } while (0)
  6150. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_M 0xffffffff
  6151. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_S 0
  6152. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_GET(_var) \
  6153. (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_M) >> \
  6154. HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_S)
  6155. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_SET(_var, _val) \
  6156. do { \
  6157. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2, _val); \
  6158. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_S)); \
  6159. } while (0)
  6160. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_M 0xffffffff
  6161. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_S 0
  6162. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_GET(_var) \
  6163. (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_M) >> \
  6164. HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_S)
  6165. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_SET(_var, _val) \
  6166. do { \
  6167. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3, _val); \
  6168. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_S)); \
  6169. } while (0)
  6170. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_M 0xFFFFFFFF
  6171. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_S 0
  6172. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_GET(_var) \
  6173. (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_M)>> \
  6174. HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_S)
  6175. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_SET(_var, _val) \
  6176. do { \
  6177. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0, _val); \
  6178. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_S)); \
  6179. } while (0)
  6180. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_M 0xFFFFFFFF
  6181. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_S 0
  6182. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_GET(_var) \
  6183. (((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_M)>> \
  6184. HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_S)
  6185. #define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_SET(_var, _val) \
  6186. do { \
  6187. HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1, _val); \
  6188. ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_S)); \
  6189. } while (0)
  6190. /*
  6191. * Subtype based MGMT frames enable bits.
  6192. * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other
  6193. */
  6194. /* association request */
  6195. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_M 0x00000001
  6196. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_S 0
  6197. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_M 0x00000002
  6198. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_S 1
  6199. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_M 0x00000004
  6200. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_S 2
  6201. /* association response */
  6202. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_M 0x00000008
  6203. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_S 3
  6204. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_M 0x00000010
  6205. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_S 4
  6206. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_M 0x00000020
  6207. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_S 5
  6208. /* Reassociation request */
  6209. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_M 0x00000040
  6210. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_S 6
  6211. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_M 0x00000080
  6212. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_S 7
  6213. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_M 0x00000100
  6214. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_S 8
  6215. /* Reassociation response */
  6216. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_M 0x00000200
  6217. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_S 9
  6218. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_M 0x00000400
  6219. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_S 10
  6220. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_M 0x00000800
  6221. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_S 11
  6222. /* Probe request */
  6223. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_M 0x00001000
  6224. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_S 12
  6225. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_M 0x00002000
  6226. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_S 13
  6227. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_M 0x00004000
  6228. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_S 14
  6229. /* Probe response */
  6230. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_M 0x00008000
  6231. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_S 15
  6232. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_M 0x00010000
  6233. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_S 16
  6234. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_M 0x00020000
  6235. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_S 17
  6236. /* Timing Advertisement */
  6237. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_M 0x00040000
  6238. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_S 18
  6239. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_M 0x00080000
  6240. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_S 19
  6241. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_M 0x00100000
  6242. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_S 20
  6243. /* Reserved */
  6244. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_M 0x00200000
  6245. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_S 21
  6246. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_M 0x00400000
  6247. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_S 22
  6248. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_M 0x00800000
  6249. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_S 23
  6250. /* Beacon */
  6251. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_M 0x01000000
  6252. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_S 24
  6253. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_M 0x02000000
  6254. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_S 25
  6255. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_M 0x04000000
  6256. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_S 26
  6257. /* ATIM */
  6258. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_M 0x08000000
  6259. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_S 27
  6260. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_M 0x10000000
  6261. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_S 28
  6262. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_M 0x20000000
  6263. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_S 29
  6264. /* Disassociation */
  6265. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_M 0x00000001
  6266. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_S 0
  6267. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_M 0x00000002
  6268. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_S 1
  6269. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_M 0x00000004
  6270. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_S 2
  6271. /* Authentication */
  6272. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_M 0x00000008
  6273. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_S 3
  6274. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_M 0x00000010
  6275. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_S 4
  6276. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_M 0x00000020
  6277. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_S 5
  6278. /* Deauthentication */
  6279. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_M 0x00000040
  6280. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_S 6
  6281. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_M 0x00000080
  6282. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_S 7
  6283. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_M 0x00000100
  6284. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_S 8
  6285. /* Action */
  6286. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_M 0x00000200
  6287. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_S 9
  6288. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_M 0x00000400
  6289. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_S 10
  6290. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_M 0x00000800
  6291. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_S 11
  6292. /* Action No Ack */
  6293. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_M 0x00001000
  6294. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_S 12
  6295. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_M 0x00002000
  6296. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_S 13
  6297. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_M 0x00004000
  6298. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_S 14
  6299. /* Reserved */
  6300. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_M 0x00008000
  6301. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_S 15
  6302. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_M 0x00010000
  6303. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_S 16
  6304. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_M 0x00020000
  6305. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_S 17
  6306. /*
  6307. * Subtype based CTRL frames enable bits.
  6308. * FP: Filter_Pass, MD: Monitor_Direct, MO: Monitor_Other
  6309. */
  6310. /* Reserved */
  6311. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_M 0x00000001
  6312. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_S 0
  6313. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_M 0x00000002
  6314. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_S 1
  6315. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_M 0x00000004
  6316. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_S 2
  6317. /* Reserved */
  6318. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_M 0x00000008
  6319. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_S 3
  6320. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_M 0x00000010
  6321. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_S 4
  6322. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_M 0x00000020
  6323. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_S 5
  6324. /* Reserved */
  6325. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_M 0x00000040
  6326. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_S 6
  6327. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_M 0x00000080
  6328. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_S 7
  6329. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_M 0x00000100
  6330. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_S 8
  6331. /* Reserved */
  6332. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_M 0x00000200
  6333. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_S 9
  6334. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_M 0x00000400
  6335. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_S 10
  6336. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_M 0x00000800
  6337. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_S 11
  6338. /* Reserved */
  6339. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_M 0x00001000
  6340. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_S 12
  6341. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_M 0x00002000
  6342. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_S 13
  6343. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_M 0x00004000
  6344. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_S 14
  6345. /* Reserved */
  6346. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_M 0x00008000
  6347. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_S 15
  6348. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_M 0x00010000
  6349. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_S 16
  6350. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_M 0x00020000
  6351. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_S 17
  6352. /* Reserved */
  6353. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_M 0x00040000
  6354. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_S 18
  6355. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_M 0x00080000
  6356. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_S 19
  6357. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_M 0x00100000
  6358. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_S 20
  6359. /* Control Wrapper */
  6360. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_M 0x00200000
  6361. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_S 21
  6362. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_M 0x00400000
  6363. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_S 22
  6364. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_M 0x00800000
  6365. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_S 23
  6366. /* Block Ack Request */
  6367. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_M 0x01000000
  6368. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_S 24
  6369. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_M 0x02000000
  6370. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_S 25
  6371. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_M 0x04000000
  6372. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_S 26
  6373. /* Block Ack*/
  6374. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_M 0x08000000
  6375. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_S 27
  6376. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_M 0x10000000
  6377. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_S 28
  6378. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_M 0x20000000
  6379. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_S 29
  6380. /* PS-POLL */
  6381. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_M 0x00000001
  6382. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_S 0
  6383. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_M 0x00000002
  6384. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_S 1
  6385. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_M 0x00000004
  6386. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_S 2
  6387. /* RTS */
  6388. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_M 0x00000008
  6389. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_S 3
  6390. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_M 0x00000010
  6391. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_S 4
  6392. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_M 0x00000020
  6393. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_S 5
  6394. /* CTS */
  6395. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_M 0x00000040
  6396. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_S 6
  6397. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_M 0x00000080
  6398. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_S 7
  6399. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_M 0x00000100
  6400. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_S 8
  6401. /* ACK */
  6402. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_M 0x00000200
  6403. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_S 9
  6404. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_M 0x00000400
  6405. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_S 10
  6406. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_M 0x00000800
  6407. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_S 11
  6408. /* CF-END */
  6409. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_M 0x00001000
  6410. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_S 12
  6411. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_M 0x00002000
  6412. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_S 13
  6413. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_M 0x00004000
  6414. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_S 14
  6415. /* CF-END + CF-ACK */
  6416. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_M 0x00008000
  6417. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_S 15
  6418. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_M 0x00010000
  6419. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_S 16
  6420. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_M 0x00020000
  6421. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_S 17
  6422. /* Multicast data */
  6423. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_M 0x00040000
  6424. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_S 18
  6425. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_M 0x00080000
  6426. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_S 19
  6427. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_M 0x00100000
  6428. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_S 20
  6429. /* Unicast data */
  6430. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_M 0x00200000
  6431. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_S 21
  6432. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_M 0x00400000
  6433. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_S 22
  6434. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_M 0x00800000
  6435. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_S 23
  6436. /* NULL data */
  6437. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_M 0x01000000
  6438. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_S 24
  6439. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_M 0x02000000
  6440. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_S 25
  6441. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_M 0x04000000
  6442. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_S 26
  6443. /* FPMO mode flags */
  6444. /* MGMT */
  6445. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0000_M 0x00000001
  6446. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0000_S 0
  6447. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0001_M 0x00000002
  6448. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0001_S 1
  6449. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0010_M 0x00000004
  6450. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0010_S 2
  6451. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0011_M 0x00000008
  6452. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0011_S 3
  6453. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0100_M 0x00000010
  6454. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0100_S 4
  6455. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0101_M 0x00000020
  6456. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0101_S 5
  6457. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0110_M 0x00000040
  6458. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0110_S 6
  6459. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0111_M 0x00000080
  6460. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_0111_S 7
  6461. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1000_M 0x00000100
  6462. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1000_S 8
  6463. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1001_M 0x00000200
  6464. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1001_S 9
  6465. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1010_M 0x00000400
  6466. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1010_S 10
  6467. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1011_M 0x00000800
  6468. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1011_S 11
  6469. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1100_M 0x00001000
  6470. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1100_S 12
  6471. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1101_M 0x00002000
  6472. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1101_S 13
  6473. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1110_M 0x00004000
  6474. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1110_S 14
  6475. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1111_M 0x00008000
  6476. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_MGMT_1111_S 15
  6477. /* CTRL */
  6478. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0000_M 0x00010000
  6479. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0000_S 16
  6480. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0001_M 0x00020000
  6481. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0001_S 17
  6482. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0010_M 0x00040000
  6483. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0010_S 18
  6484. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0011_M 0x00080000
  6485. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0011_S 19
  6486. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0100_M 0x00100000
  6487. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0100_S 20
  6488. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0101_M 0x00200000
  6489. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0101_S 21
  6490. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0110_M 0x00400000
  6491. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0110_S 22
  6492. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0111_M 0x00800000
  6493. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_0111_S 23
  6494. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1000_M 0x01000000
  6495. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1000_S 24
  6496. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1001_M 0x02000000
  6497. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1001_S 25
  6498. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1010_M 0x04000000
  6499. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1010_S 26
  6500. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1011_M 0x08000000
  6501. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1011_S 27
  6502. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1100_M 0x10000000
  6503. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1100_S 28
  6504. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1101_M 0x20000000
  6505. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1101_S 29
  6506. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1110_M 0x40000000
  6507. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1110_S 30
  6508. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1111_M 0x80000000
  6509. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FPMO_CTRL_1111_S 31
  6510. /* DATA */
  6511. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_MCAST_M 0x00000001
  6512. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_MCAST_S 0
  6513. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_UCAST_M 0x00000002
  6514. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_UCAST_S 1
  6515. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_NULL_M 0x00000004
  6516. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_NULL_S 2
  6517. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_DATA_M 0x00000008
  6518. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_DATA_S 3
  6519. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_TB_M 0x00000010
  6520. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FPMO_DATA_QOS_NULL_TB_S 4
  6521. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET(word, httsym, value) \
  6522. do { \
  6523. HTT_CHECK_SET_VAL(httsym, value); \
  6524. (word) |= (value) << httsym##_S; \
  6525. } while (0)
  6526. #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET(word, httsym) \
  6527. (((word) & httsym##_M) >> httsym##_S)
  6528. #define htt_rx_ring_pkt_enable_subtype_set( \
  6529. word, flag, mode, type, subtype, val) \
  6530. HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET( \
  6531. word, HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype, val)
  6532. #define htt_rx_ring_pkt_enable_subtype_get( \
  6533. word, flag, mode, type, subtype) \
  6534. HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET( \
  6535. word, HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype)
  6536. /* Definition to filter in TLVs */
  6537. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_M 0x00000001
  6538. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_S 0
  6539. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_M 0x00000002
  6540. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_S 1
  6541. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_M 0x00000004
  6542. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_S 2
  6543. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_M 0x00000008
  6544. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_S 3
  6545. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_M 0x00000010
  6546. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_S 4
  6547. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_M 0x00000020
  6548. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_S 5
  6549. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_M 0x00000040
  6550. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_S 6
  6551. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_M 0x00000080
  6552. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_S 7
  6553. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_M 0x00000100
  6554. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_S 8
  6555. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_M 0x00000200
  6556. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_S 9
  6557. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_M 0x00000400
  6558. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_S 10
  6559. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_M 0x00000800
  6560. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_S 11
  6561. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_M 0x00001000
  6562. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_S 12
  6563. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_USER_INFO_M 0x00002000
  6564. #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_USER_INFO_S 13
  6565. #define HTT_RX_RING_TLV_ENABLE_SET(word, httsym, enable) \
  6566. do { \
  6567. HTT_CHECK_SET_VAL(httsym, enable); \
  6568. (word) |= (enable) << httsym##_S; \
  6569. } while (0)
  6570. #define HTT_RX_RING_TLV_ENABLE_GET(word, httsym) \
  6571. (((word) & httsym##_M) >> httsym##_S)
  6572. #define htt_rx_ring_tlv_filter_in_enable_set(word, tlv, enable) \
  6573. HTT_RX_RING_TLV_ENABLE_SET( \
  6574. word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv, enable)
  6575. #define htt_rx_ring_tlv_filter_in_enable_get(word, tlv) \
  6576. HTT_RX_RING_TLV_ENABLE_GET( \
  6577. word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv)
  6578. /**
  6579. * @brief host -> target TX monitor config message
  6580. *
  6581. * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_MONITOR_CFG
  6582. *
  6583. * @details
  6584. * HTT_H2T_MSG_TYPE_TX_MONITOR_CFG message is sent by host to
  6585. * configure RXDMA rings.
  6586. * The configuration is per ring based and includes both packet types
  6587. * and PPDU/MPDU TLVs.
  6588. *
  6589. * The message would appear as follows:
  6590. *
  6591. * |31 28|27|26|25|24|23 22|21|20|19|18 16|15|14|13|12|11|10|9|8|7|6|5|4|3|2 0|
  6592. * |-----+--+--+--+--+-----+--+--+--+-----+--+--+--+--+--+--+-+-+-+-+-+-+-+----|
  6593. * |rsvd1|MF|TM|PS|SS| ring_id | pdev_id | msg_type |
  6594. * |--------------+--------+--------+-----+------------------------------------|
  6595. * | rsvd2 | DATA | CTRL | MGMT| ring_buffer_size |
  6596. * |-----------------------------------------+--+--+--+--+--+-+-+-+-+-+-+-+----|
  6597. * | | M| M| M| M| M|M|M|M|M|M|M|M| |
  6598. * | | S| S| S| P| P|P|S|S|S|P|P|P| |
  6599. * | | E| E| E| E| E|E|S|S|S|S|S|S| |
  6600. * | rsvd3 | D| C| M| D| C|M|D|C|M|D|C|M| E |
  6601. * |---------------------------------------------------------------------------|
  6602. * | tlv_filter_mask_in0 |
  6603. * |---------------------------------------------------------------------------|
  6604. * | tlv_filter_mask_in1 |
  6605. * |---------------------------------------------------------------------------|
  6606. * | tlv_filter_mask_in2 |
  6607. * |---------------------------------------------------------------------------|
  6608. * | tlv_filter_mask_in3 |
  6609. * |--------------------+-----------------+---------------------+--------------|
  6610. * | tx_msdu_start_wm | tx_queue_ext_wm | tx_peer_entry_wm |tx_fes_stup_wm|
  6611. * |---------------------------------------------------------------------------|
  6612. * | pcu_ppdu_setup_word_mask |
  6613. * |-----------------------+--+--+--+-----+---------------------+--------------|
  6614. * | rsvd4 | D| C| M| PT | rxpcu_usrsetp_wm |tx_mpdu_srt_wm|
  6615. * |---------------------------------------------------------------------------|
  6616. *
  6617. * Where:
  6618. * MF = MAC address filtering enable
  6619. * TM = tx monitor global enable
  6620. * PS = pkt_swap
  6621. * SS = status_swap
  6622. * The message is interpreted as follows:
  6623. * dword0 - b'0:7 - msg_type: This will be set to
  6624. * 0x1b (HTT_H2T_MSG_TYPE_TX_MONITOR_CFG)
  6625. * b'8:15 - pdev_id:
  6626. * 0 (for rings at SOC level),
  6627. * 1/2/3 mac id (for rings at LMAC level)
  6628. * b'16:23 - ring_id : Identify the ring to configure.
  6629. * More details can be got from enum htt_srng_ring_id
  6630. * b'24 - status_swap (SS): 1 is to swap status TLV - refer to
  6631. * BUF_RING_CFG_0 defs within HW .h files,
  6632. * e.g. wmac_top_reg_seq_hwioreg.h
  6633. * b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to
  6634. * BUF_RING_CFG_0 defs within HW .h files,
  6635. * e.g. wmac_top_reg_seq_hwioreg.h
  6636. * b'26 - tx_mon_global_en: Enable/Disable global register
  6637. * configuration in Tx monitor module.
  6638. * b'27 - mac_addr_filter_en:
  6639. * Enable/Disable Mac Address based filter.
  6640. * b'28:31 - rsvd1: reserved for future use
  6641. * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring,
  6642. * in byte units.
  6643. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
  6644. * b'16:18 - config_length_mgmt(MGMT) for MGMT: Each bit set represent
  6645. * 64, 128, 256.
  6646. * If all 3 bits are set config length is > 256.
  6647. * if val is '0', then ignore this field.
  6648. * b'19:21 - config_length_ctrl(CTRL) for CTRL: Each bit set represent
  6649. * 64, 128, 256.
  6650. * If all 3 bits are set config length is > 256.
  6651. * if val is '0', then ignore this field.
  6652. * b'22:24 - config_length_data(DATA) for DATA: Each bit set represent
  6653. * 64, 128, 256.
  6654. * If all 3 bits are set config length is > 256.
  6655. * If val is '0', then ignore this field.
  6656. * - b'25:31 - rsvd2: Reserved for future use
  6657. * dword2 - b'0:2 - packet_type_enable_flags(E): MGMT, CTRL, DATA
  6658. * b'3 - filter_in_tx_mpdu_start_mgmt(MPSM):
  6659. * If packet_type_enable_flags is '1' for MGMT type,
  6660. * monitor will ignore this bit and allow this TLV.
  6661. * If packet_type_enable_flags is '0' for MGMT type,
  6662. * monitor will use this bit to enable/disable logging
  6663. * of this TLV.
  6664. * b'4 - filter_in_tx_mpdu_start_ctrl(MPSC)
  6665. * If packet_type_enable_flags is '1' for CTRL type,
  6666. * monitor will ignore this bit and allow this TLV.
  6667. * If packet_type_enable_flags is '0' for CTRL type,
  6668. * monitor will use this bit to enable/disable logging
  6669. * of this TLV.
  6670. * b'5 - filter_in_tx_mpdu_start_data(MPSD)
  6671. * If packet_type_enable_flags is '1' for DATA type,
  6672. * monitor will ignore this bit and allow this TLV.
  6673. * If packet_type_enable_flags is '0' for DATA type,
  6674. * monitor will use this bit to enable/disable logging
  6675. * of this TLV.
  6676. * b'6 - filter_in_tx_msdu_start_mgmt(MSSM)
  6677. * If packet_type_enable_flags is '1' for MGMT type,
  6678. * monitor will ignore this bit and allow this TLV.
  6679. * If packet_type_enable_flags is '0' for MGMT type,
  6680. * monitor will use this bit to enable/disable logging
  6681. * of this TLV.
  6682. * b'7 - filter_in_tx_msdu_start_ctrl(MSSC)
  6683. * If packet_type_enable_flags is '1' for CTRL type,
  6684. * monitor will ignore this bit and allow this TLV.
  6685. * If packet_type_enable_flags is '0' for CTRL type,
  6686. * monitor will use this bit to enable/disable logging
  6687. * of this TLV.
  6688. * b'8 - filter_in_tx_msdu_start_data(MSSD)
  6689. * If packet_type_enable_flags is '1' for DATA type,
  6690. * monitor will ignore this bit and allow this TLV.
  6691. * If packet_type_enable_flags is '0' for DATA type,
  6692. * monitor will use this bit to enable/disable logging
  6693. * of this TLV.
  6694. * b'9 - filter_in_tx_mpdu_end_mgmt(MPEM)
  6695. * If packet_type_enable_flags is '1' for MGMT type,
  6696. * monitor will ignore this bit and allow this TLV.
  6697. * If packet_type_enable_flags is '0' for MGMT type,
  6698. * monitor will use this bit to enable/disable logging
  6699. * of this TLV.
  6700. * If filter_in_TX_MPDU_START = 1 it is recommended
  6701. * to set this bit.
  6702. * b'10 - filter_in_tx_mpdu_end_ctrl(MPEC)
  6703. * If packet_type_enable_flags is '1' for CTRL type,
  6704. * monitor will ignore this bit and allow this TLV.
  6705. * If packet_type_enable_flags is '0' for CTRL type,
  6706. * monitor will use this bit to enable/disable logging
  6707. * of this TLV.
  6708. * If filter_in_TX_MPDU_START = 1 it is recommended
  6709. * to set this bit.
  6710. * b'11 - filter_in_tx_mpdu_end_data(MPED)
  6711. * If packet_type_enable_flags is '1' for DATA type,
  6712. * monitor will ignore this bit and allow this TLV.
  6713. * If packet_type_enable_flags is '0' for DATA type,
  6714. * monitor will use this bit to enable/disable logging
  6715. * of this TLV.
  6716. * If filter_in_TX_MPDU_START = 1 it is recommended
  6717. * to set this bit.
  6718. * b'12 - filter_in_tx_msdu_end_mgmt(MSEM)
  6719. * If packet_type_enable_flags is '1' for MGMT type,
  6720. * monitor will ignore this bit and allow this TLV.
  6721. * If packet_type_enable_flags is '0' for MGMT type,
  6722. * monitor will use this bit to enable/disable logging
  6723. * of this TLV.
  6724. * If filter_in_TX_MSDU_START = 1 it is recommended
  6725. * to set this bit.
  6726. * b'13 - filter_in_tx_msdu_end_ctrl(MSEC)
  6727. * If packet_type_enable_flags is '1' for CTRL type,
  6728. * monitor will ignore this bit and allow this TLV.
  6729. * If packet_type_enable_flags is '0' for CTRL type,
  6730. * monitor will use this bit to enable/disable logging
  6731. * of this TLV.
  6732. * If filter_in_TX_MSDU_START = 1 it is recommended
  6733. * to set this bit.
  6734. * b'14 - filter_in_tx_msdu_end_data(MSED)
  6735. * If packet_type_enable_flags is '1' for DATA type,
  6736. * monitor will ignore this bit and allow this TLV.
  6737. * If packet_type_enable_flags is '0' for DATA type,
  6738. * monitor will use this bit to enable/disable logging
  6739. * of this TLV.
  6740. * If filter_in_TX_MSDU_START = 1 it is recommended
  6741. * to set this bit.
  6742. * b'15:31 - rsvd3: Reserved for future use
  6743. * dword3 - b'0:31 - tlv_filter_mask_in0:
  6744. * dword4 - b'0:31 - tlv_filter_mask_in1:
  6745. * dword5 - b'0:31 - tlv_filter_mask_in2:
  6746. * dword6 - b'0:31 - tlv_filter_mask_in3:
  6747. * dword7 - b'0:7 - tx_fes_setup_word_mask:
  6748. * - b'8:15 - tx_peer_entry_word_mask:
  6749. * - b'16:23 - tx_queue_ext_word_mask:
  6750. * - b'24:31 - tx_msdu_start_word_mask:
  6751. * dword8 - b'0:31 - pcu_ppdu_setup_word_mask:
  6752. * dword9 - b'0:7 - tx_mpdu_start_word_mask:
  6753. * - b'8:15 - rxpcu_user_setup_word_mask:
  6754. * - b'16:18 - pkt_type_enable_msdu_or_mpdu_logging (PT):
  6755. * MGMT, CTRL, DATA
  6756. * - b'19 - dma_mpdu_mgmt(M): For MGMT
  6757. * 0 -> MSDU level logging is enabled
  6758. * (valid only if bit is set in
  6759. * pkt_type_enable_msdu_or_mpdu_logging)
  6760. * 1 -> MPDU level logging is enabled
  6761. * (valid only if bit is set in
  6762. * pkt_type_enable_msdu_or_mpdu_logging)
  6763. * - b'20 - dma_mpdu_ctrl(C) : For CTRL
  6764. * 0 -> MSDU level logging is enabled
  6765. * (valid only if bit is set in
  6766. * pkt_type_enable_msdu_or_mpdu_logging)
  6767. * 1 -> MPDU level logging is enabled
  6768. * (valid only if bit is set in
  6769. * pkt_type_enable_msdu_or_mpdu_logging)
  6770. * - b'21 - dma_mpdu_data(D) : For DATA
  6771. * 0 -> MSDU level logging is enabled
  6772. * (valid only if bit is set in
  6773. * pkt_type_enable_msdu_or_mpdu_logging)
  6774. * 1 -> MPDU level logging is enabled
  6775. * (valid only if bit is set in
  6776. * pkt_type_enable_msdu_or_mpdu_logging)
  6777. * - b'22:31 - rsvd4 for future use
  6778. */
  6779. PREPACK struct htt_tx_monitor_cfg_t {
  6780. A_UINT32 msg_type: 8,
  6781. pdev_id: 8,
  6782. ring_id: 8,
  6783. status_swap: 1,
  6784. pkt_swap: 1,
  6785. tx_mon_global_en: 1,
  6786. mac_addr_filter_en: 1,
  6787. rsvd1: 4;
  6788. A_UINT32 ring_buffer_size: 16,
  6789. config_length_mgmt: 3,
  6790. config_length_ctrl: 3,
  6791. config_length_data: 3,
  6792. rsvd2: 7;
  6793. A_UINT32 pkt_type_enable_flags: 3,
  6794. filter_in_tx_mpdu_start_mgmt: 1,
  6795. filter_in_tx_mpdu_start_ctrl: 1,
  6796. filter_in_tx_mpdu_start_data: 1,
  6797. filter_in_tx_msdu_start_mgmt: 1,
  6798. filter_in_tx_msdu_start_ctrl: 1,
  6799. filter_in_tx_msdu_start_data: 1,
  6800. filter_in_tx_mpdu_end_mgmt: 1,
  6801. filter_in_tx_mpdu_end_ctrl: 1,
  6802. filter_in_tx_mpdu_end_data: 1,
  6803. filter_in_tx_msdu_end_mgmt: 1,
  6804. filter_in_tx_msdu_end_ctrl: 1,
  6805. filter_in_tx_msdu_end_data: 1,
  6806. word_mask_compaction_enable: 1,
  6807. rsvd3: 16;
  6808. A_UINT32 tlv_filter_mask_in0;
  6809. A_UINT32 tlv_filter_mask_in1;
  6810. A_UINT32 tlv_filter_mask_in2;
  6811. A_UINT32 tlv_filter_mask_in3;
  6812. A_UINT32 tx_fes_setup_word_mask: 8,
  6813. tx_peer_entry_word_mask: 8,
  6814. tx_queue_ext_word_mask: 8,
  6815. tx_msdu_start_word_mask: 8;
  6816. A_UINT32 pcu_ppdu_setup_word_mask;
  6817. A_UINT32 tx_mpdu_start_word_mask: 8,
  6818. rxpcu_user_setup_word_mask: 8,
  6819. pkt_type_enable_msdu_or_mpdu_logging: 3,
  6820. dma_mpdu_mgmt: 1,
  6821. dma_mpdu_ctrl: 1,
  6822. dma_mpdu_data: 1,
  6823. rsvd4: 10;
  6824. A_UINT32 tx_queue_ext_v2_word_mask: 12,
  6825. tx_peer_entry_v2_word_mask: 12,
  6826. rsvd5: 8;
  6827. A_UINT32 fes_status_end_word_mask: 16,
  6828. response_end_status_word_mask: 16;
  6829. A_UINT32 fes_status_prot_word_mask: 11,
  6830. rsvd6: 21;
  6831. } POSTPACK;
  6832. #define HTT_TX_MONITOR_CFG_SZ (sizeof(struct htt_tx_monitor_cfg_t))
  6833. #define HTT_TX_MONITOR_CFG_PDEV_ID_M 0x0000ff00
  6834. #define HTT_TX_MONITOR_CFG_PDEV_ID_S 8
  6835. #define HTT_TX_MONITOR_CFG_PDEV_ID_GET(_var) \
  6836. (((_var) & HTT_TX_MONITOR_CFG_PDEV_ID_M) >> \
  6837. HTT_TX_MONITOR_CFG_PDEV_ID_S)
  6838. #define HTT_TX_MONITOR_CFG_PDEV_ID_SET(_var, _val) \
  6839. do { \
  6840. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PDEV_ID, _val); \
  6841. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PDEV_ID_S)); \
  6842. } while (0)
  6843. #define HTT_TX_MONITOR_CFG_RING_ID_M 0x00ff0000
  6844. #define HTT_TX_MONITOR_CFG_RING_ID_S 16
  6845. #define HTT_TX_MONITOR_CFG_RING_ID_GET(_var) \
  6846. (((_var) & HTT_TX_MONITOR_CFG_RING_ID_M) >> \
  6847. HTT_TX_MONITOR_CFG_RING_ID_S)
  6848. #define HTT_TX_MONITOR_CFG_RING_ID_SET(_var, _val) \
  6849. do { \
  6850. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RING_ID, _val); \
  6851. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RING_ID_S)); \
  6852. } while (0)
  6853. #define HTT_TX_MONITOR_CFG_STATUS_SWAP_M 0x01000000
  6854. #define HTT_TX_MONITOR_CFG_STATUS_SWAP_S 24
  6855. #define HTT_TX_MONITOR_CFG_STATUS_TLV_GET(_var) \
  6856. (((_var) & HTT_TX_MONITOR_CFG_STATUS_SWAP_M) >> \
  6857. HTT_TX_MONITOR_CFG_STATUS_SWAP_S)
  6858. #define HTT_TX_MONITOR_CFG_STATUS_TLV_SET(_var, _val) \
  6859. do { \
  6860. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_STATUS_SWAP, _val); \
  6861. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_STATUS_SWAP_S)); \
  6862. } while (0)
  6863. #define HTT_TX_MONITOR_CFG_PKT_SWAP_M 0x02000000
  6864. #define HTT_TX_MONITOR_CFG_PKT_SWAP_S 25
  6865. #define HTT_TX_MONITOR_CFG_PKT_TLV_GET(_var) \
  6866. (((_var) & HTT_TX_MONITOR_CFG_PKT_SWAP_M) >> \
  6867. HTT_TX_MONITOR_CFG_PKT_SWAP_S)
  6868. #define HTT_TX_MONITOR_CFG_PKT_TLV_SET(_var, _val) \
  6869. do { \
  6870. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_SWAP, _val); \
  6871. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_SWAP_S)); \
  6872. } while (0)
  6873. #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_M 0x04000000
  6874. #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S 26
  6875. #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_GET(_var) \
  6876. (((_var) & HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_M) >> \
  6877. HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S)
  6878. #define HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_SET(_var, _val) \
  6879. do { \
  6880. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN, _val); \
  6881. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MON_GLOBAL_EN_S)); \
  6882. } while (0)
  6883. #define HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_M 0x08000000
  6884. #define HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_S 27
  6885. #define HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_GET(_var) \
  6886. (((_var) & HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_M) >> \
  6887. HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_S)
  6888. #define HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_SET(_var, _val) \
  6889. do { \
  6890. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN, _val); \
  6891. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_S)); \
  6892. } while (0)
  6893. #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M 0x0000ffff
  6894. #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S 0
  6895. #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_GET(_var) \
  6896. (((_var) & HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M) >> \
  6897. HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S)
  6898. #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_SET(_var, _val) \
  6899. do { \
  6900. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE, _val); \
  6901. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S)); \
  6902. } while (0)
  6903. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_M 0x00070000
  6904. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S 16
  6905. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_GET(_var) \
  6906. (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_M) >> \
  6907. HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S)
  6908. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_SET(_var, _val) \
  6909. do { \
  6910. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT, _val); \
  6911. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S)); \
  6912. } while (0)
  6913. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_M 0x00380000
  6914. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S 19
  6915. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_GET(_var) \
  6916. (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_M) >> \
  6917. HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S)
  6918. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_SET(_var, _val) \
  6919. do { \
  6920. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL, _val); \
  6921. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S)); \
  6922. } while (0)
  6923. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_M 0x01C00000
  6924. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S 22
  6925. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_GET(_var) \
  6926. (((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_M) >> \
  6927. HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S)
  6928. #define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_SET(_var, _val) \
  6929. do { \
  6930. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA, _val); \
  6931. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S)); \
  6932. } while (0)
  6933. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_M 0x00000007
  6934. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S 0
  6935. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_GET(_var) \
  6936. (((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_M) >> \
  6937. HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S)
  6938. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_SET(_var, _val) \
  6939. do { \
  6940. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS, _val); \
  6941. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S)); \
  6942. } while (0)
  6943. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_M 0x00000008
  6944. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S 3
  6945. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_GET(_var) \
  6946. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_M) >> \
  6947. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S)
  6948. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_SET(_var, _val) \
  6949. do { \
  6950. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT, _val); \
  6951. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_MGMT_S)); \
  6952. } while (0)
  6953. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_M 0x00000010
  6954. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S 4
  6955. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_GET(_var) \
  6956. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_M) >> \
  6957. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S)
  6958. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_SET(_var, _val) \
  6959. do { \
  6960. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL, _val); \
  6961. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_CTRL_S)); \
  6962. } while (0)
  6963. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_M 0x00000020
  6964. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S 5
  6965. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_GET(_var) \
  6966. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_M) >> \
  6967. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S)
  6968. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_SET(_var, _val) \
  6969. do { \
  6970. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA, _val); \
  6971. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_START_DATA_S)); \
  6972. } while (0)
  6973. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_M 0x00000040
  6974. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S 6
  6975. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_GET(_var) \
  6976. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_M) >> \
  6977. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S)
  6978. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_SET(_var, _val) \
  6979. do { \
  6980. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT, _val); \
  6981. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_MGMT_S)); \
  6982. } while (0)
  6983. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_M 0x00000080
  6984. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S 7
  6985. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_GET(_var) \
  6986. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_M) >> \
  6987. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S)
  6988. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_SET(_var, _val) \
  6989. do { \
  6990. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL, _val); \
  6991. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_CTRL_S)); \
  6992. } while (0)
  6993. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_M 0x00000100
  6994. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S 8
  6995. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_GET(_var) \
  6996. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_M) >> \
  6997. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S)
  6998. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_SET(_var, _val) \
  6999. do { \
  7000. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA, _val); \
  7001. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_START_DATA_S)); \
  7002. } while (0)
  7003. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_M 0x00000200
  7004. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S 9
  7005. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_GET(_var) \
  7006. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_M) >> \
  7007. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S)
  7008. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_SET(_var, _val) \
  7009. do { \
  7010. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT, _val); \
  7011. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_MGMT_S)); \
  7012. } while (0)
  7013. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_M 0x00000400
  7014. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S 10
  7015. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_GET(_var) \
  7016. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_M) >> \
  7017. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S)
  7018. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_SET(_var, _val) \
  7019. do { \
  7020. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL, _val); \
  7021. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_CTRL_S)); \
  7022. } while (0)
  7023. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_M 0x00000800
  7024. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S 11
  7025. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_GET(_var) \
  7026. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_M) >> \
  7027. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S)
  7028. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_SET(_var, _val) \
  7029. do { \
  7030. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA, _val); \
  7031. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MPDU_END_DATA_S)); \
  7032. } while (0)
  7033. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_M 0x00001000
  7034. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S 12
  7035. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_GET(_var) \
  7036. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_M) >> \
  7037. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S)
  7038. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_SET(_var, _val) \
  7039. do { \
  7040. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT, _val); \
  7041. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_MGMT_S)); \
  7042. } while (0)
  7043. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_M 0x00002000
  7044. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S 13
  7045. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_GET(_var) \
  7046. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_M) >> \
  7047. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S)
  7048. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_SET(_var, _val) \
  7049. do { \
  7050. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL, _val); \
  7051. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_CTRL_S)); \
  7052. } while (0)
  7053. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_M 0x00004000
  7054. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S 14
  7055. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_GET(_var) \
  7056. (((_var) & HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_M) >> \
  7057. HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S)
  7058. #define HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_SET(_var, _val) \
  7059. do { \
  7060. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA, _val); \
  7061. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S)); \
  7062. } while (0)
  7063. #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M 0x00008000
  7064. #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S 15
  7065. #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_GET(_var) \
  7066. (((_var) & HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M) >> \
  7067. HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S)
  7068. #define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_SET(_var, _val) \
  7069. do { \
  7070. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE, _val); \
  7071. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S)); \
  7072. } while (0)
  7073. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M 0xffffffff
  7074. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S 0
  7075. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_GET(_var) \
  7076. (((_var) & HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M) >> \
  7077. HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S)
  7078. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_SET(_var, _val) \
  7079. do { \
  7080. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TLV_FILTER_MASK, _val); \
  7081. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S)); \
  7082. } while (0)
  7083. #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_M 0x000000ff
  7084. #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S 0
  7085. #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_GET(_var) \
  7086. (((_var) & HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_M) >> \
  7087. HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S)
  7088. #define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_SET(_var, _val) \
  7089. do { \
  7090. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK, _val); \
  7091. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S)); \
  7092. } while (0)
  7093. #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_M 0x0000ff00
  7094. #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S 8
  7095. #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_GET(_var) \
  7096. (((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_M) >> \
  7097. HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S)
  7098. #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_SET(_var, _val) \
  7099. do { \
  7100. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK, _val); \
  7101. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S)); \
  7102. } while (0)
  7103. #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_M 0x00ff0000
  7104. #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S 16
  7105. #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_GET(_var) \
  7106. (((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_M) >> \
  7107. HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S)
  7108. #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_SET(_var, _val) \
  7109. do { \
  7110. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK, _val); \
  7111. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S)); \
  7112. } while (0)
  7113. #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_M 0xff000000
  7114. #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S 24
  7115. #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_GET(_var) \
  7116. (((_var) & HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_M) >> \
  7117. HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S)
  7118. #define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_SET(_var, _val) \
  7119. do { \
  7120. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK, _val); \
  7121. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S)); \
  7122. } while (0)
  7123. #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_M 0xffffffff
  7124. #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S 0
  7125. #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_GET(_var) \
  7126. (((_var) & HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_M) >> \
  7127. HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S)
  7128. #define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_SET(_var, _val) \
  7129. do { \
  7130. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK, _val); \
  7131. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S)); \
  7132. } while (0)
  7133. #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_M 0x000000ff
  7134. #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S 0
  7135. #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_GET(_var) \
  7136. (((_var) & HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_M) >> \
  7137. HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S)
  7138. #define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_SET(_var, _val) \
  7139. do { \
  7140. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK, _val); \
  7141. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S)); \
  7142. } while (0)
  7143. #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_M 0x0000ff00
  7144. #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S 8
  7145. #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_GET(_var) \
  7146. (((_var) & HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_M) >> \
  7147. HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S)
  7148. #define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_SET(_var, _val) \
  7149. do { \
  7150. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK, _val); \
  7151. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S)); \
  7152. } while (0)
  7153. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_M 0x00070000
  7154. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S 16
  7155. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_GET(_var) \
  7156. (((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_M) >> \
  7157. HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S)
  7158. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_SET(_var, _val) \
  7159. do { \
  7160. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK, _val); \
  7161. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S)); \
  7162. } while (0)
  7163. #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_M 0x00080000
  7164. #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S 19
  7165. #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_GET(_var) \
  7166. (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_M) >> \
  7167. HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S)
  7168. #define HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_SET(_var, _val) \
  7169. do { \
  7170. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT, _val); \
  7171. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_MGMT_S)); \
  7172. } while (0)
  7173. #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_M 0x00100000
  7174. #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S 20
  7175. #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_GET(_var) \
  7176. (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_M) >> \
  7177. HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S)
  7178. #define HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_SET(_var, _val) \
  7179. do { \
  7180. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL, _val); \
  7181. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_CTRL_S)); \
  7182. } while (0)
  7183. #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_M 0x00200000
  7184. #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S 21
  7185. #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_GET(_var) \
  7186. (((_var) & HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_M) >> \
  7187. HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S)
  7188. #define HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_SET(_var, _val) \
  7189. do { \
  7190. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_DMA_MPDU_DATA, _val); \
  7191. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S)); \
  7192. } while (0)
  7193. #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M 0x00000fff
  7194. #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S 0
  7195. #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_GET(_var) \
  7196. (((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M) >> \
  7197. HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S)
  7198. #define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_SET(_var, _val) \
  7199. do { \
  7200. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK, _val); \
  7201. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S)); \
  7202. } while (0)
  7203. #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M 0x00fff000
  7204. #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S 12
  7205. #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_GET(_var) \
  7206. (((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M) >> \
  7207. HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S)
  7208. #define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_SET(_var, _val) \
  7209. do { \
  7210. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK, _val); \
  7211. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S)); \
  7212. } while (0)
  7213. #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M 0x0000ffff
  7214. #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S 0
  7215. #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_GET(_var) \
  7216. (((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M) >> \
  7217. HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S)
  7218. #define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_SET(_var, _val) \
  7219. do { \
  7220. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK, _val); \
  7221. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S)); \
  7222. } while (0)
  7223. #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M 0xffff0000
  7224. #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S 16
  7225. #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_GET(_var) \
  7226. (((_var) & HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M) >> \
  7227. HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S)
  7228. #define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_SET(_var, _val) \
  7229. do { \
  7230. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK, _val); \
  7231. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S)); \
  7232. } while (0)
  7233. #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M 0x000007ff
  7234. #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S 0
  7235. #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_GET(_var) \
  7236. (((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M) >> \
  7237. HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)
  7238. #define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_SET(_var, _val) \
  7239. do { \
  7240. HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK, _val); \
  7241. ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)); \
  7242. } while (0)
  7243. /*
  7244. * pkt_type_enable_flags
  7245. */
  7246. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_MGMT_M 0x00000001
  7247. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_MGMT_S 0
  7248. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_CTRL_M 0x00000002
  7249. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_CTRL_S 1
  7250. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_DATA_M 0x00000004
  7251. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_DATA_S 2
  7252. /*
  7253. * PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING
  7254. */
  7255. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MGMT_M 0x00010000
  7256. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_MGMT_S 16
  7257. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_CTRL_M 0x00020000
  7258. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_CTRL_S 17
  7259. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_DATA_M 0x00040000
  7260. #define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_MSDU_OR_MPDU_LOGGING_DATA_S 18
  7261. #define HTT_TX_MONITOR_CFG_PKT_TYPE_SET(word, httsym, value) \
  7262. do { \
  7263. HTT_CHECK_SET_VAL(httsym, value); \
  7264. (word) |= (value) << httsym##_S; \
  7265. } while (0)
  7266. #define HTT_TX_MONITOR_CFG_PKT_TYPE_GET(word, httsym) \
  7267. (((word) & httsym##_M) >> httsym##_S)
  7268. /* mode -> ENABLE_FLAGS, ENABLE_MSDU_OR_MPDU_LOGGING
  7269. * type -> MGMT, CTRL, DATA*/
  7270. #define htt_tx_ring_pkt_type_set( \
  7271. word, mode, type, val) \
  7272. HTT_TX_MONITOR_CFG_PKT_TYPE_SET( \
  7273. word, HTT_TX_MONITOR_CFG_PKT_TYPE_##mode##_##type, val)
  7274. #define htt_tx_ring_pkt_type_get( \
  7275. word, mode, type) \
  7276. HTT_TX_MONITOR_CFG_PKT_TYPE_GET( \
  7277. word, HTT_TX_MONITOR_CFG_PKT_TYPE_##mode##_##type)
  7278. /* Definition to filter in TLVs */
  7279. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_M 0x00000001
  7280. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_S 0
  7281. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_PEER_ENTRY_M 0x00000002
  7282. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_PEER_ENTRY_S 1
  7283. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_QUEUE_EXTENSION_M 0x00000004
  7284. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_QUEUE_EXTENSION_S 2
  7285. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_END_M 0x00000008
  7286. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_END_S 3
  7287. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_FETCHED_M 0x00000010
  7288. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_FETCHED_S 4
  7289. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_DATA_SYNC_M 0x00000020
  7290. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_DATA_SYNC_S 5
  7291. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_PCU_PPDU_SETUP_INIT_M 0x00000040
  7292. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_PCU_PPDU_SETUP_INIT_S 6
  7293. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_FW2SW_MON_M 0x00000080
  7294. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_FW2SW_MON_S 7
  7295. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LOOPBACK_SETUP_M 0x00000100
  7296. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LOOPBACK_SETUP_S 8
  7297. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_CRITICAL_TLV_REFERENCE_M 0x00000200
  7298. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_CRITICAL_TLV_REFERENCE_S 9
  7299. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_NDP_PREAMBLE_DONE_M 0x00000400
  7300. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_NDP_PREAMBLE_DONE_S 10
  7301. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_RAW_OR_NATIVE_FRAME_SETUP_M 0x00000800
  7302. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_RAW_OR_NATIVE_FRAME_SETUP_S 11
  7303. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TXPCU_USER_SETUP_M 0x00001000
  7304. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TXPCU_USER_SETUP_S 12
  7305. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_M 0x00002000
  7306. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_S 13
  7307. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_COMPLETE_M 0x00004000
  7308. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_COMPLETE_S 14
  7309. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_COEX_TX_REQ_M 0x00008000
  7310. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_COEX_TX_REQ_S 15
  7311. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_M 0x00010000
  7312. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_S 16
  7313. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_EXT_M 0x00020000
  7314. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_EXT_S 17
  7315. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_WUR_DATA_M 0x00040000
  7316. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_WUR_DATA_S 18
  7317. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TQM_MPDU_GLOBAL_START_M 0x00080000
  7318. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TQM_MPDU_GLOBAL_START_S 19
  7319. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_COMPLETE_M 0x00100000
  7320. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_COMPLETE_S 20
  7321. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCHEDULER_END_M 0x00200000
  7322. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCHEDULER_END_S 21
  7323. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_WAIT_INSTR_TX_PATH_M 0x00400000
  7324. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_WAIT_INSTR_TX_PATH_S 22
  7325. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_M 0x00800000
  7326. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_S 23
  7327. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PUNC_M 0x01000000
  7328. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PUNC_S 24
  7329. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PER_BW_M 0x02000000
  7330. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PER_BW_S 25
  7331. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_M 0x04000000
  7332. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_S 26
  7333. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PUNC_M 0x08000000
  7334. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PUNC_S 27
  7335. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PER_BW_M 0x10000000
  7336. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PER_BW_S 28
  7337. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MPDU_QUEUE_OVERVIEW_M 0x20000000
  7338. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MPDU_QUEUE_OVERVIEW_S 29
  7339. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_COMMON_M 0x40000000
  7340. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_COMMON_S 30
  7341. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_PER_USER_M 0x80000000
  7342. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_PER_USER_S 31
  7343. #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_SET(word, httsym, enable) \
  7344. do { \
  7345. HTT_CHECK_SET_VAL(httsym, enable); \
  7346. (word) |= (enable) << httsym##_S; \
  7347. } while (0)
  7348. #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_GET(word, httsym) \
  7349. (((word) & httsym##_M) >> httsym##_S)
  7350. #define htt_tx_monitor_tlv_filter_in0_enable_set(word, tlv, enable) \
  7351. HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_SET( \
  7352. word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_##tlv, enable)
  7353. #define htt_tx_monitor_tlv_filter_in0_enable_get(word, tlv) \
  7354. HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_GET( \
  7355. word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_##tlv)
  7356. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_RESPONSE_REQUIRED_INFO_M 0x00000001
  7357. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_RESPONSE_REQUIRED_INFO_S 0
  7358. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_START_STATUS_M 0x00000002
  7359. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_START_STATUS_S 1
  7360. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_END_STATUS_M 0x00000004
  7361. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_END_STATUS_S 2
  7362. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_M 0x00000008
  7363. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_S 3
  7364. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_END_M 0x00000010
  7365. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_END_S 4
  7366. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PPDU_M 0x00000020
  7367. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PPDU_S 5
  7368. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_PPDU_M 0x00000040
  7369. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_PPDU_S 6
  7370. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_ACK_OR_BA_M 0x00000080
  7371. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_ACK_OR_BA_S 7
  7372. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_1K_BA_M 0x00000100
  7373. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_1K_BA_S 8
  7374. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PROT_M 0x00000200
  7375. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PROT_S 9
  7376. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_PROT_M 0x00000400
  7377. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_PROT_S 10
  7378. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_RESPONSE_M 0x00000800
  7379. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_RESPONSE_S 11
  7380. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_BITMAP_ACK_M 0x00001000
  7381. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_BITMAP_ACK_S 12
  7382. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_1K_BITMAP_ACK_M 0x00002000
  7383. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_1K_BITMAP_ACK_S 13
  7384. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_COEX_TX_STATUS_M 0x00004000
  7385. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_COEX_TX_STATUS_S 14
  7386. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_M 0x00008000
  7387. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_S 15
  7388. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_PART2_M 0x00010000
  7389. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_PART2_S 16
  7390. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_OFDMA_TRIGGER_DETAILS_M 0x00020000
  7391. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_OFDMA_TRIGGER_DETAILS_S 17
  7392. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_TRIGGER_INFO_M 0x00040000
  7393. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_TRIGGER_INFO_S 18
  7394. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TX_REQUEST_M 0x00080000
  7395. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TX_REQUEST_S 19
  7396. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_RESPONSE_M 0x00100000
  7397. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_RESPONSE_S 20
  7398. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TRIG_RESPONSE_M 0x00200000
  7399. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TRIG_RESPONSE_S 21
  7400. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TRIGGER_RESPONSE_TX_DONE_M 0x00400000
  7401. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TRIGGER_RESPONSE_TX_DONE_S 22
  7402. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PROT_TX_END_M 0x00800000
  7403. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PROT_TX_END_S 23
  7404. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PPDU_TX_END_M 0x01000000
  7405. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PPDU_TX_END_S 24
  7406. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_R2R_STATUS_END_M 0x02000000
  7407. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_R2R_STATUS_END_S 25
  7408. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_FLUSH_REQ_M 0x04000000
  7409. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_FLUSH_REQ_S 26
  7410. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_PHY_DESC_M 0x08000000
  7411. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_PHY_DESC_S 27
  7412. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_COMMON_M 0x10000000
  7413. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_COMMON_S 28
  7414. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_PER_USER_M 0x20000000
  7415. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_PER_USER_S 29
  7416. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_A_M 0x40000000
  7417. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_A_S 30
  7418. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_B_M 0x80000000
  7419. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_L_SIG_B_S 31
  7420. #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_SET(word, httsym, enable) \
  7421. do { \
  7422. HTT_CHECK_SET_VAL(httsym, enable); \
  7423. (word) |= (enable) << httsym##_S; \
  7424. } while (0)
  7425. #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_GET(word, httsym) \
  7426. (((word) & httsym##_M) >> httsym##_S)
  7427. #define htt_tx_monitor_tlv_filter_in1_enable_set(word, tlv, enable) \
  7428. HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_SET( \
  7429. word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_##tlv, enable)
  7430. #define htt_tx_monitor_tlv_filter_in1_enable_get(word, tlv) \
  7431. HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_GET( \
  7432. word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_##tlv)
  7433. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HT_SIG_M 0x00000001
  7434. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HT_SIG_S 0
  7435. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_A_M 0x00000002
  7436. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_A_S 1
  7437. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU20_M 0x00000004
  7438. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU20_S 2
  7439. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU40_M 0x00000008
  7440. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU40_S 3
  7441. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU80_M 0x00000010
  7442. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU80_S 4
  7443. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU160_M 0x00000020
  7444. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU160_S 5
  7445. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU20_M 0x00000040
  7446. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU20_S 6
  7447. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU40_M 0x00000080
  7448. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU40_S 7
  7449. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU80_M 0x00000100
  7450. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU80_S 8
  7451. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU160_M 0x00000200
  7452. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU160_S 9
  7453. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_SERVICE_M 0x00000400
  7454. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_SERVICE_S 10
  7455. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_SU_M 0x00000800
  7456. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_SU_S 11
  7457. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_DL_M 0x00001000
  7458. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_DL_S 12
  7459. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_UL_M 0x00002000
  7460. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_UL_S 13
  7461. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B1_MU_M 0x00004000
  7462. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B1_MU_S 14
  7463. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_MU_M 0x00008000
  7464. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_MU_S 15
  7465. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_OFDMA_M 0x00010000
  7466. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_OFDMA_S 16
  7467. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_MU_M 0x00020000
  7468. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_MU_S 17
  7469. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_M 0x00040000
  7470. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_S 18
  7471. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_TB_M 0x00080000
  7472. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_TB_S 19
  7473. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_SU_M 0x00100000
  7474. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_SU_S 20
  7475. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_MU_MIMO_M 0x00200000
  7476. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_MU_MIMO_S 21
  7477. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_OFDMA_M 0x00400000
  7478. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_OFDMA_S 22
  7479. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_PHYTX_PPDU_HEADER_INFO_REQUEST_M 0x00800000
  7480. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_PHYTX_PPDU_HEADER_INFO_REQUEST_S 23
  7481. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_UPDATE_TX_MPDU_COUNT_M 0x01000000
  7482. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_UPDATE_TX_MPDU_COUNT_S 24
  7483. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_MPDU_M 0x02000000
  7484. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_MPDU_S 25
  7485. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_1K_MPDU_M 0x04000000
  7486. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_1K_MPDU_S 26
  7487. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_BUFFER_STATUS_M 0x08000000
  7488. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_BUFFER_STATUS_S 27
  7489. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_USER_BUFFER_STATUS_M 0x10000000
  7490. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXPCU_USER_BUFFER_STATUS_S 28
  7491. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXDMA_STOP_REQUEST_M 0x20000000
  7492. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TXDMA_STOP_REQUEST_S 29
  7493. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EXPECTED_RESPONSE_M 0x40000000
  7494. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EXPECTED_RESPONSE_S 30
  7495. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_MPDU_COUNT_TRANSFER_END_M 0x80000000
  7496. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_MPDU_COUNT_TRANSFER_END_S 31
  7497. #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_SET(word, httsym, enable) \
  7498. do { \
  7499. HTT_CHECK_SET_VAL(httsym, enable); \
  7500. (word) |= (enable) << httsym##_S; \
  7501. } while (0)
  7502. #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_GET(word, httsym) \
  7503. (((word) & httsym##_M) >> httsym##_S)
  7504. #define htt_tx_monitor_tlv_filter_in2_enable_set(word, tlv, enable) \
  7505. HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_SET( \
  7506. word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_##tlv, enable)
  7507. #define htt_tx_monitor_tlv_filter_in2_enable_get(word, tlv) \
  7508. HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_GET( \
  7509. word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_##tlv)
  7510. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_TRIG_INFO_M 0x00000001
  7511. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_TRIG_INFO_S 0
  7512. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_TX_SETUP_CLEAR_M 0x00000002
  7513. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_TX_SETUP_CLEAR_S 1
  7514. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_FRAME_BITMAP_REQ_M 0x00000004
  7515. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_FRAME_BITMAP_REQ_S 2
  7516. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PHY_SLEEP_M 0x00000008
  7517. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PHY_SLEEP_S 3
  7518. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PREAMBLE_DONE_M 0x00000010
  7519. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PREAMBLE_DONE_S 4
  7520. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_DEBUG32_M 0x00000020
  7521. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_DEBUG32_S 5
  7522. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_M 0x00000040
  7523. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_S 6
  7524. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_NO_ACK_REPORT_M 0x00000080
  7525. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_NO_ACK_REPORT_S 7
  7526. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_ACK_REPORT_M 0x00000100
  7527. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_ACK_REPORT_S 8
  7528. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_COEX_RX_STATUS_M 0x00000200
  7529. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_COEX_RX_STATUS_S 9
  7530. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_START_PARAM_M 0x00000400
  7531. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_START_PARAM_S 10
  7532. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_CBF_INFO_M 0x00000800
  7533. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_CBF_INFO_S 11
  7534. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_EARLY_RX_INDICATION_M 0x00001000
  7535. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_EARLY_RX_INDICATION_S 12
  7536. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_7_0_M 0x00002000
  7537. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_7_0_S 13
  7538. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_15_8_M 0x00004000
  7539. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_15_8_S 14
  7540. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_23_16_M 0x00008000
  7541. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_23_16_S 15
  7542. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_31_24_M 0x00010000
  7543. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_31_24_S 16
  7544. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_36_32_M 0x00020000
  7545. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_36_32_S 17
  7546. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PM_INFO_M 0x00040000
  7547. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PM_INFO_S 18
  7548. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PREAMBLE_M 0x00080000
  7549. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PREAMBLE_S 19
  7550. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_OTHERS_M 0x00100000
  7551. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_OTHERS_S 20
  7552. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_MACTX_PRE_PHY_DESC_M 0x00200000
  7553. #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_MACTX_PRE_PHY_DESC_S 21
  7554. #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_SET(word, httsym, enable) \
  7555. do { \
  7556. HTT_CHECK_SET_VAL(httsym, enable); \
  7557. (word) |= (enable) << httsym##_S; \
  7558. } while (0)
  7559. #define HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_GET(word, httsym) \
  7560. (((word) & httsym##_M) >> httsym##_S)
  7561. #define htt_tx_monitor_tlv_filter_in3_enable_set(word, tlv, enable) \
  7562. HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_SET( \
  7563. word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_##tlv, enable)
  7564. #define htt_tx_monitor_tlv_filter_in3_enable_get(word, tlv) \
  7565. HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_GET( \
  7566. word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_##tlv)
  7567. /**
  7568. * @brief host --> target Receive Flow Steering configuration message definition
  7569. *
  7570. * MSG_TYPE => HTT_H2T_MSG_TYPE_RFS_CONFIG
  7571. *
  7572. * host --> target Receive Flow Steering configuration message definition.
  7573. * Host must send this message before sending HTT_H2T_MSG_TYPE_RX_RING_CFG.
  7574. * The reason for this is we want RFS to be configured and ready before MAC
  7575. * remote ring is enabled via HTT_H2T_MSG_TYPE_RX_RING_CFG.
  7576. *
  7577. * |31 24|23 16|15 9|8|7 0|
  7578. * |----------------+----------------+----------------+----------------|
  7579. * | reserved |E| msg type |
  7580. * |-------------------------------------------------------------------|
  7581. * Where E = RFS enable flag
  7582. *
  7583. * The RFS_CONFIG message consists of a single 4-byte word.
  7584. *
  7585. * Header fields:
  7586. * - MSG_TYPE
  7587. * Bits 7:0
  7588. * Purpose: identifies this as a RFS config msg
  7589. * Value: 0xf (HTT_H2T_MSG_TYPE_RFS_CONFIG)
  7590. * - RFS_CONFIG
  7591. * Bit 8
  7592. * Purpose: Tells target whether to enable (1) or disable (0)
  7593. * flow steering feature when sending rx indication messages to host
  7594. */
  7595. #define HTT_H2T_RFS_CONFIG_M 0x100
  7596. #define HTT_H2T_RFS_CONFIG_S 8
  7597. #define HTT_RX_RFS_CONFIG_GET(_var) \
  7598. (((_var) & HTT_H2T_RFS_CONFIG_M) >> \
  7599. HTT_H2T_RFS_CONFIG_S)
  7600. #define HTT_RX_RFS_CONFIG_SET(_var, _val) \
  7601. do { \
  7602. HTT_CHECK_SET_VAL(HTT_H2T_RFS_CONFIG, _val); \
  7603. ((_var) |= ((_val) << HTT_H2T_RFS_CONFIG_S)); \
  7604. } while (0)
  7605. #define HTT_RFS_CFG_REQ_BYTES 4
  7606. /**
  7607. * @brief host -> target FW extended statistics request
  7608. *
  7609. * MSG_TYPE => HTT_H2T_MSG_TYPE_EXT_STATS_REQ
  7610. *
  7611. * @details
  7612. * The following field definitions describe the format of the HTT host
  7613. * to target FW extended stats retrieve message.
  7614. * The message specifies the type of stats the host wants to retrieve.
  7615. *
  7616. * |31 24|23 16|15 8|7 0|
  7617. * |-----------------------------------------------------------|
  7618. * | reserved | stats type | pdev_mask | msg type |
  7619. * |-----------------------------------------------------------|
  7620. * | config param [0] |
  7621. * |-----------------------------------------------------------|
  7622. * | config param [1] |
  7623. * |-----------------------------------------------------------|
  7624. * | config param [2] |
  7625. * |-----------------------------------------------------------|
  7626. * | config param [3] |
  7627. * |-----------------------------------------------------------|
  7628. * | reserved |
  7629. * |-----------------------------------------------------------|
  7630. * | cookie LSBs |
  7631. * |-----------------------------------------------------------|
  7632. * | cookie MSBs |
  7633. * |-----------------------------------------------------------|
  7634. * Header fields:
  7635. * - MSG_TYPE
  7636. * Bits 7:0
  7637. * Purpose: identifies this is a extended stats upload request message
  7638. * Value: 0x10 (HTT_H2T_MSG_TYPE_EXT_STATS_REQ)
  7639. * - PDEV_MASK
  7640. * Bits 8:15
  7641. * Purpose: identifies the mask of PDEVs to retrieve stats from
  7642. * Value: This is a overloaded field, refer to usage and interpretation of
  7643. * PDEV in interface document.
  7644. * Bit 8 : Reserved for SOC stats
  7645. * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
  7646. * Indicates MACID_MASK in DBS
  7647. * - STATS_TYPE
  7648. * Bits 23:16
  7649. * Purpose: identifies which FW statistics to upload
  7650. * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
  7651. * - Reserved
  7652. * Bits 31:24
  7653. * - CONFIG_PARAM [0]
  7654. * Bits 31:0
  7655. * Purpose: give an opaque configuration value to the specified stats type
  7656. * Value: stats-type specific configuration value
  7657. * Refer to htt_stats.h for interpretation for each stats sub_type
  7658. * - CONFIG_PARAM [1]
  7659. * Bits 31:0
  7660. * Purpose: give an opaque configuration value to the specified stats type
  7661. * Value: stats-type specific configuration value
  7662. * Refer to htt_stats.h for interpretation for each stats sub_type
  7663. * - CONFIG_PARAM [2]
  7664. * Bits 31:0
  7665. * Purpose: give an opaque configuration value to the specified stats type
  7666. * Value: stats-type specific configuration value
  7667. * Refer to htt_stats.h for interpretation for each stats sub_type
  7668. * - CONFIG_PARAM [3]
  7669. * Bits 31:0
  7670. * Purpose: give an opaque configuration value to the specified stats type
  7671. * Value: stats-type specific configuration value
  7672. * Refer to htt_stats.h for interpretation for each stats sub_type
  7673. * - Reserved [31:0] for future use.
  7674. * - COOKIE_LSBS
  7675. * Bits 31:0
  7676. * Purpose: Provide a mechanism to match a target->host stats confirmation
  7677. * message with its preceding host->target stats request message.
  7678. * Value: LSBs of the opaque cookie specified by the host-side requestor
  7679. * - COOKIE_MSBS
  7680. * Bits 31:0
  7681. * Purpose: Provide a mechanism to match a target->host stats confirmation
  7682. * message with its preceding host->target stats request message.
  7683. * Value: MSBs of the opaque cookie specified by the host-side requestor
  7684. */
  7685. #define HTT_H2T_EXT_STATS_REQ_MSG_SZ 32 /* bytes */
  7686. #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_M 0x0000ff00
  7687. #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S 8
  7688. #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_M 0x00ff0000
  7689. #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S 16
  7690. #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_M 0xffffffff
  7691. #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S 0
  7692. #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_GET(_var) \
  7693. (((_var) & HTT_H2T_EXT_STATS_REQ_PDEV_MASK_M) >> \
  7694. HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S)
  7695. #define HTT_H2T_EXT_STATS_REQ_PDEV_MASK_SET(_var, _val) \
  7696. do { \
  7697. HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_PDEV_MASK, _val); \
  7698. ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_PDEV_MASK_S)); \
  7699. } while (0)
  7700. #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_GET(_var) \
  7701. (((_var) & HTT_H2T_EXT_STATS_REQ_STATS_TYPE_M) >> \
  7702. HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S)
  7703. #define HTT_H2T_EXT_STATS_REQ_STATS_TYPE_SET(_var, _val) \
  7704. do { \
  7705. HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_STATS_TYPE, _val); \
  7706. ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_STATS_TYPE_S)); \
  7707. } while (0)
  7708. #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_GET(_var) \
  7709. (((_var) & HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_M) >> \
  7710. HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S)
  7711. #define HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_SET(_var, _val) \
  7712. do { \
  7713. HTT_CHECK_SET_VAL(HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM, _val); \
  7714. ((_var) |= ((_val) << HTT_H2T_EXT_STATS_REQ_CONFIG_PARAM_S)); \
  7715. } while (0)
  7716. /**
  7717. * @brief host -> target FW streaming statistics request
  7718. *
  7719. * MSG_TYPE => HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ
  7720. *
  7721. * @details
  7722. * The following field definitions describe the format of the HTT host
  7723. * to target message that requests the target to start or stop producing
  7724. * ongoing stats of the specified type.
  7725. *
  7726. * |31|30 |23 16|15 8|7 0|
  7727. * |-----------------------------------------------------------|
  7728. * |EN| reserved | stats type | reserved | msg type |
  7729. * |-----------------------------------------------------------|
  7730. * | config param [0] |
  7731. * |-----------------------------------------------------------|
  7732. * | config param [1] |
  7733. * |-----------------------------------------------------------|
  7734. * | config param [2] |
  7735. * |-----------------------------------------------------------|
  7736. * | config param [3] |
  7737. * |-----------------------------------------------------------|
  7738. * Where:
  7739. * - EN is an enable/disable flag
  7740. * Header fields:
  7741. * - MSG_TYPE
  7742. * Bits 7:0
  7743. * Purpose: identifies this is a streaming stats upload request message
  7744. * Value: 0x20 (HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ)
  7745. * - STATS_TYPE
  7746. * Bits 23:16
  7747. * Purpose: identifies which FW statistics to upload
  7748. * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
  7749. * Only the htt_dbg_ext_stats_type values identified as streaming
  7750. * stats are valid to specify in this STEAMING_STATS_REQ message.
  7751. * - ENABLE
  7752. * Bit 31
  7753. * Purpose: enable/disable the target's ongoing stats of the specified type
  7754. * Value:
  7755. * 0 - disable ongoing production of the specified stats type
  7756. * 1 - enable ongoing production of the specified stats type
  7757. * - CONFIG_PARAM [0]
  7758. * Bits 31:0
  7759. * Purpose: give an opaque configuration value to the specified stats type
  7760. * Value: stats-type specific configuration value
  7761. * Refer to htt_stats.h for interpretation for each stats sub_type
  7762. * - CONFIG_PARAM [1]
  7763. * Bits 31:0
  7764. * Purpose: give an opaque configuration value to the specified stats type
  7765. * Value: stats-type specific configuration value
  7766. * Refer to htt_stats.h for interpretation for each stats sub_type
  7767. * - CONFIG_PARAM [2]
  7768. * Bits 31:0
  7769. * Purpose: give an opaque configuration value to the specified stats type
  7770. * Value: stats-type specific configuration value
  7771. * Refer to htt_stats.h for interpretation for each stats sub_type
  7772. * - CONFIG_PARAM [3]
  7773. * Bits 31:0
  7774. * Purpose: give an opaque configuration value to the specified stats type
  7775. * Value: stats-type specific configuration value
  7776. * Refer to htt_stats.h for interpretation for each stats sub_type
  7777. */
  7778. #define HTT_H2T_STREAMING_STATS_REQ_MSG_SZ 20 /* bytes */
  7779. #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_M 0x00ff0000
  7780. #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S 16
  7781. #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_M 0x80000000
  7782. #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_S 31
  7783. #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_GET(_var) \
  7784. (((_var) & HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_M) >> \
  7785. HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S)
  7786. #define HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_SET(_var, _val) \
  7787. do { \
  7788. HTT_CHECK_SET_VAL(HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE, _val); \
  7789. ((_var) |= ((_val) << HTT_H2T_STREAMING_STATS_REQ_STATS_TYPE_S)); \
  7790. } while (0)
  7791. #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_GET(_var) \
  7792. (((_var) & HTT_H2T_STREAMING_STATS_REQ_ENABLE_M) >> \
  7793. HTT_H2T_STREAMING_STATS_REQ_ENABLE_S)
  7794. #define HTT_H2T_STREAMING_STATS_REQ_ENABLE_SET(_var, _val) \
  7795. do { \
  7796. HTT_CHECK_SET_VAL(HTT_H2T_STREAMING_STATS_REQ_ENABLE, _val); \
  7797. ((_var) |= ((_val) << HTT_H2T_STREAMING_STATS_REQ_ENABLE_S)); \
  7798. } while (0)
  7799. /**
  7800. * @brief host -> target FW PPDU_STATS request message
  7801. *
  7802. * MSG_TYPE => HTT_H2T_MSG_TYPE_PPDU_STATS_CFG
  7803. *
  7804. * @details
  7805. * The following field definitions describe the format of the HTT host
  7806. * to target FW for PPDU_STATS_CFG msg.
  7807. * The message allows the host to configure the PPDU_STATS_IND messages
  7808. * produced by the target.
  7809. *
  7810. * |31 24|23 16|15 8|7 0|
  7811. * |-----------------------------------------------------------|
  7812. * | REQ bit mask | pdev_mask | msg type |
  7813. * |-----------------------------------------------------------|
  7814. * Header fields:
  7815. * - MSG_TYPE
  7816. * Bits 7:0
  7817. * Purpose: identifies this is a req to configure ppdu_stats_ind from target
  7818. * Value: 0x11 (HTT_H2T_MSG_TYPE_PPDU_STATS_CFG)
  7819. * - PDEV_MASK
  7820. * Bits 8:15
  7821. * Purpose: identifies which pdevs this PPDU stats configuration applies to
  7822. * Value: This is a overloaded field, refer to usage and interpretation of
  7823. * PDEV in interface document.
  7824. * Bit 8 : Reserved for SOC stats
  7825. * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
  7826. * Indicates MACID_MASK in DBS
  7827. * - REQ_TLV_BIT_MASK
  7828. * Bits 16:31
  7829. * Purpose: each set bit indicates the corresponding PPDU stats TLV type
  7830. * needs to be included in the target's PPDU_STATS_IND messages.
  7831. * Value: refer htt_ppdu_stats_tlv_tag_t
  7832. *
  7833. */
  7834. #define HTT_H2T_PPDU_STATS_CFG_MSG_SZ 4 /* bytes */
  7835. #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_M 0x0000ff00
  7836. #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S 8
  7837. #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_M 0xffff0000
  7838. #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S 16
  7839. #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_GET(_var) \
  7840. (((_var) & HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_M) >> \
  7841. HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S)
  7842. #define HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_SET(_var, _val) \
  7843. do { \
  7844. HTT_CHECK_SET_VAL(HTT_H2T_PPDU_STATS_CFG_PDEV_MASK, _val); \
  7845. ((_var) |= ((_val) << HTT_H2T_PPDU_STATS_CFG_PDEV_MASK_S)); \
  7846. } while (0)
  7847. #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_GET(_var) \
  7848. (((_var) & HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_M) >> \
  7849. HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S)
  7850. #define HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_SET(_var, _val) \
  7851. do { \
  7852. HTT_CHECK_SET_VAL(HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK, _val); \
  7853. ((_var) |= ((_val) << HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S)); \
  7854. } while (0)
  7855. /**
  7856. * @brief Host-->target HTT RX FSE setup message
  7857. *
  7858. * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG
  7859. *
  7860. * @details
  7861. * Through this message, the host will provide details of the flow tables
  7862. * in host DDR along with hash keys.
  7863. * This message can be sent per SOC or per PDEV, which is differentiated
  7864. * by pdev id values.
  7865. * The host will allocate flow search table and sends table size,
  7866. * physical DMA address of flow table, and hash keys to firmware to
  7867. * program into the RXOLE FSE HW block.
  7868. *
  7869. * The following field definitions describe the format of the RX FSE setup
  7870. * message sent from the host to target
  7871. *
  7872. * Header fields:
  7873. * dword0 - b'7:0 - msg_type: This will be set to
  7874. * 0x12 (HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG)
  7875. * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
  7876. * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that
  7877. * pdev's LMAC ring.
  7878. * b'31:16 - reserved : Reserved for future use
  7879. * dword1 - b'19:0 - number of records: This field indicates the number of
  7880. * entries in the flow table. For example: 8k number of
  7881. * records is equivalent to
  7882. * 8 * 1024 * sizeof(RX_FLOW_SEARCH_ENTRY_STRUCT)
  7883. * b'27:20 - max search: This field specifies the skid length to FSE
  7884. * parser HW module whenever match is not found at the
  7885. * exact index pointed by hash.
  7886. * b'29:28 - ip_da_sa: This indicates which IPV4-IPV6 RFC to be used.
  7887. * Refer htt_ip_da_sa_prefix below for more details.
  7888. * b'31:30 - reserved: Reserved for future use
  7889. * dword2 - b'31:0 - base address lo: Lower 4 bytes base address of flow
  7890. * table allocated by host in DDR
  7891. * dword3 - b'31:0 - base address hi: Higher 4 bytes of base address of flow
  7892. * table allocated by host in DDR
  7893. * dword4:13 - b'31:0 - Toeplitz: 315 bits of Toeplitz keys for flow table
  7894. * entry hashing
  7895. *
  7896. *
  7897. * |31 30|29 28|27|26|25 20|19 16|15 8|7 0|
  7898. * |---------------------------------------------------------------|
  7899. * | reserved | pdev_id | MSG_TYPE |
  7900. * |---------------------------------------------------------------|
  7901. * |resvd|IPDSA| max_search | Number of records |
  7902. * |---------------------------------------------------------------|
  7903. * | base address lo |
  7904. * |---------------------------------------------------------------|
  7905. * | base address high |
  7906. * |---------------------------------------------------------------|
  7907. * | toeplitz key 31_0 |
  7908. * |---------------------------------------------------------------|
  7909. * | toeplitz key 63_32 |
  7910. * |---------------------------------------------------------------|
  7911. * | toeplitz key 95_64 |
  7912. * |---------------------------------------------------------------|
  7913. * | toeplitz key 127_96 |
  7914. * |---------------------------------------------------------------|
  7915. * | toeplitz key 159_128 |
  7916. * |---------------------------------------------------------------|
  7917. * | toeplitz key 191_160 |
  7918. * |---------------------------------------------------------------|
  7919. * | toeplitz key 223_192 |
  7920. * |---------------------------------------------------------------|
  7921. * | toeplitz key 255_224 |
  7922. * |---------------------------------------------------------------|
  7923. * | toeplitz key 287_256 |
  7924. * |---------------------------------------------------------------|
  7925. * | reserved | toeplitz key 314_288(26:0 bits) |
  7926. * |---------------------------------------------------------------|
  7927. * where:
  7928. * IPDSA = ip_da_sa
  7929. */
  7930. /**
  7931. * @brief: htt_ip_da_sa_prefix
  7932. * 0x0 -> Prefix is 0x20010db8_00000000_00000000
  7933. * IPv6 addresses beginning with 0x20010db8 are reserved for
  7934. * documentation per RFC3849
  7935. * 0x1 -> Prefix is 0x00000000_00000000_0000ffff RFC4291 IPv4-mapped IPv6
  7936. * 0x2 -> Prefix is 0x0 RFC4291 IPv4-compatible IPv6
  7937. * 0x3 -> Prefix is 0x0064ff9b_00000000_00000000 RFC6052 well-known prefix
  7938. */
  7939. enum htt_ip_da_sa_prefix {
  7940. HTT_RX_IPV6_20010db8,
  7941. HTT_RX_IPV4_MAPPED_IPV6,
  7942. HTT_RX_IPV4_COMPATIBLE_IPV6,
  7943. HTT_RX_IPV6_64FF9B,
  7944. };
  7945. /**
  7946. * @brief Host-->target HTT RX FISA configure and enable
  7947. *
  7948. * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FISA_CFG
  7949. *
  7950. * @details
  7951. * The host will send this command down to configure and enable the FISA
  7952. * operational params.
  7953. * Configure RXOLE_RXOLE_R0_FISA_CTRL and RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH
  7954. * register.
  7955. * Should configure both the MACs.
  7956. *
  7957. * dword0 - b'7:0 - msg_type:
  7958. * This will be set to 0x15 (HTT_H2T_MSG_TYPE_RX_FISA_CFG)
  7959. * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
  7960. * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that
  7961. * pdev's LMAC ring.
  7962. * b'31:16 - reserved : Reserved for future use
  7963. *
  7964. * dword1 - b'0 - enable: Global FISA Enable, 0-FISA Disable, 1-Enable
  7965. * b'1 - IPSEC_SKIP_SEARCH: Flow search will be skipped for IP_SEC
  7966. * packets. 1 flow search will be skipped
  7967. * b'2 - NON_TCP_SKIP_SEARCH: Flow search will be skipped for Non
  7968. * tcp,udp packets
  7969. * b'3 - ADD_IPV4_FIXED_HDR_LEN: Add IPV4 Fixed HDR to length
  7970. * calculation
  7971. * b'4 - ADD_IPV6_FIXED_HDR_LEN: Add IPV6 Fixed HDR to length
  7972. * calculation
  7973. * b'5 - ADD_TCP_FIXED_HDR_LEN: Add TCP Fixed HDR to length
  7974. * calculation
  7975. * b'6 - ADD_UDP_HDR_LEN: Add UDP HDR to length calculation
  7976. * b'7 - CHKSUM_CUM_IP_LEN_EN: IPV4 hdr Checksum over cumulative IP
  7977. * length
  7978. * 0 L4 checksum will be provided in the RX_MSDU_END tlv
  7979. * 1 IPV4 hdr checksum after adjusting for cumulative IP
  7980. * length
  7981. * b'8 - DISABLE_TID_CHECK: 1- Disable TID check for MPDU Sequence
  7982. * num jump
  7983. * b'9 - DISABLE_TA_CHECK: 1- Disable TA check for MPDU Sequence
  7984. * num jump
  7985. * b'10 - DISABLE_QOS_CHECK: 1- Disable checking if qos/nonqos
  7986. * data type switch has happened for MPDU Sequence num jump
  7987. * b'11 - DISABLE_RAW_CHECK: 1- Disable checking for raw packet type
  7988. * for MPDU Sequence num jump
  7989. * b'12 - DISABLE_DECRYPT_ERR_CHECK: 1- Disable fisa cache commands
  7990. * for decrypt errors
  7991. * b'13 - DISABLE_MSDU_DROP_CHECK: 1- Ignore checking of msdu drop
  7992. * while aggregating a msdu
  7993. * b'17:14 - LIMIT, Aggregtion limit for number of MSDUs.
  7994. * The aggregation is done until (number of MSDUs aggregated
  7995. * < LIMIT + 1)
  7996. * b'31:18 - Reserved
  7997. *
  7998. * fisa_control_value - 32bit value FW can write to register
  7999. *
  8000. * dword2 - b'31:0 - FISA_TIMEOUT_THRESH, Timeout threshold for aggregation
  8001. * Threshold value for FISA timeout (units are microseconds).
  8002. * When the global timestamp exceeds this threshold, FISA
  8003. * aggregation will be restarted.
  8004. * A value of 0 means timeout is disabled.
  8005. * Compare the threshold register with timestamp field in
  8006. * flow entry to generate timeout for the flow.
  8007. *
  8008. * |31 18 |17 16|15 8|7 0|
  8009. * |-------------------------------------------------------------|
  8010. * | reserved | pdev_mask | msg type |
  8011. * |-------------------------------------------------------------|
  8012. * | reserved | FISA_CTRL |
  8013. * |-------------------------------------------------------------|
  8014. * | FISA_TIMEOUT_THRESH |
  8015. * |-------------------------------------------------------------|
  8016. */
  8017. PREPACK struct htt_h2t_msg_type_fisa_config_t {
  8018. A_UINT32 msg_type:8,
  8019. pdev_id:8,
  8020. reserved0:16;
  8021. /**
  8022. * @brief fisa_control - RXOLE_RXOLE_R0_FISA_CTRL FISA control register
  8023. * [17:0]
  8024. */
  8025. union {
  8026. /*
  8027. * fisa_control_bits structure is deprecated.
  8028. * Please use fisa_control_bits_v2 going forward.
  8029. */
  8030. struct {
  8031. A_UINT32 fisa_enable: 1,
  8032. ipsec_skip_search: 1,
  8033. nontcp_skip_search: 1,
  8034. add_ipv4_fixed_hdr_len: 1,
  8035. add_ipv6_fixed_hdr_len: 1,
  8036. add_tcp_fixed_hdr_len: 1,
  8037. add_udp_hdr_len: 1,
  8038. chksum_cum_ip_len_en: 1,
  8039. disable_tid_check: 1,
  8040. disable_ta_check: 1,
  8041. disable_qos_check: 1,
  8042. disable_raw_check: 1,
  8043. disable_decrypt_err_check: 1,
  8044. disable_msdu_drop_check: 1,
  8045. fisa_aggr_limit: 4,
  8046. reserved: 14;
  8047. } fisa_control_bits;
  8048. struct {
  8049. A_UINT32 fisa_enable: 1,
  8050. fisa_aggr_limit: 6,
  8051. reserved: 25;
  8052. } fisa_control_bits_v2;
  8053. A_UINT32 fisa_control_value;
  8054. } u_fisa_control;
  8055. /**
  8056. * @brief fisa_timeout_threshold - RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH FISA
  8057. * timeout threshold for aggregation. Unit in usec.
  8058. * [31:0]
  8059. */
  8060. A_UINT32 fisa_timeout_threshold;
  8061. } POSTPACK;
  8062. /* DWord 0: pdev-ID */
  8063. #define HTT_RX_FISA_CONFIG_PDEV_ID_M 0x0000ff00
  8064. #define HTT_RX_FISA_CONFIG_PDEV_ID_S 8
  8065. #define HTT_RX_FISA_CONFIG_PDEV_ID_GET(_var) \
  8066. (((_var) & HTT_RX_FISA_CONFIG_PDEV_ID_M) >> \
  8067. HTT_RX_FISA_CONFIG_PDEV_ID_S)
  8068. #define HTT_RX_FISA_CONFIG_PDEV_ID_SET(_var, _val) \
  8069. do { \
  8070. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_PDEV_ID, _val); \
  8071. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_PDEV_ID_S)); \
  8072. } while (0)
  8073. /* Dword 1: fisa_control_value fisa config */
  8074. #define HTT_RX_FISA_CONFIG_FISA_ENABLE_M 0x00000001
  8075. #define HTT_RX_FISA_CONFIG_FISA_ENABLE_S 0
  8076. #define HTT_RX_FISA_CONFIG_FISA_ENABLE_GET(_var) \
  8077. (((_var) & HTT_RX_FISA_CONFIG_FISA_ENABLE_M) >> \
  8078. HTT_RX_FISA_CONFIG_FISA_ENABLE_S)
  8079. #define HTT_RX_FISA_CONFIG_FISA_ENABLE_SET(_var, _val) \
  8080. do { \
  8081. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_ENABLE, _val); \
  8082. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_ENABLE_S)); \
  8083. } while (0)
  8084. /* Dword 1: fisa_control_value ipsec_skip_search */
  8085. #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M 0x00000002
  8086. #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S 1
  8087. #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_GET(_var) \
  8088. (((_var) & HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M) >> \
  8089. HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S)
  8090. #define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_SET(_var, _val) \
  8091. do { \
  8092. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH, _val); \
  8093. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S)); \
  8094. } while (0)
  8095. /* Dword 1: fisa_control_value non_tcp_skip_search */
  8096. #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M 0x00000004
  8097. #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S 2
  8098. #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_GET(_var) \
  8099. (((_var) & HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M) >> \
  8100. HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S)
  8101. #define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_SET(_var, _val) \
  8102. do { \
  8103. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH, _val); \
  8104. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S)); \
  8105. } while (0)
  8106. /* Dword 1: fisa_control_value add_ipv4_fixed_hdr */
  8107. #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M 0x00000008
  8108. #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S 3
  8109. #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_GET(_var) \
  8110. (((_var) & HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M) >> \
  8111. HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S)
  8112. #define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_SET(_var, _val) \
  8113. do { \
  8114. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN, _val); \
  8115. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S)); \
  8116. } while (0)
  8117. /* Dword 1: fisa_control_value add_ipv6_fixed_hdr */
  8118. #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M 0x00000010
  8119. #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S 4
  8120. #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_GET(_var) \
  8121. (((_var) & HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M) >> \
  8122. HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S)
  8123. #define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_SET(_var, _val) \
  8124. do { \
  8125. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN, _val); \
  8126. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S)); \
  8127. } while (0)
  8128. /* Dword 1: fisa_control_value tcp_fixed_hdr_len */
  8129. #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M 0x00000020
  8130. #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S 5
  8131. #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_GET(_var) \
  8132. (((_var) & HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M) >> \
  8133. HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S)
  8134. #define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_SET(_var, _val) \
  8135. do { \
  8136. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN, _val); \
  8137. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S)); \
  8138. } while (0)
  8139. /* Dword 1: fisa_control_value add_udp_hdr_len */
  8140. #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M 0x00000040
  8141. #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S 6
  8142. #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_GET(_var) \
  8143. (((_var) & HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M) >> \
  8144. HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S)
  8145. #define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_SET(_var, _val) \
  8146. do { \
  8147. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN, _val); \
  8148. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S)); \
  8149. } while (0)
  8150. /* Dword 1: fisa_control_value chksum_cum_ip_len_en */
  8151. #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M 0x00000080
  8152. #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S 7
  8153. #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_GET(_var) \
  8154. (((_var) & HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M) >> \
  8155. HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S)
  8156. #define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_SET(_var, _val) \
  8157. do { \
  8158. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN, _val); \
  8159. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S)); \
  8160. } while (0)
  8161. /* Dword 1: fisa_control_value disable_tid_check */
  8162. #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M 0x00000100
  8163. #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S 8
  8164. #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_GET(_var) \
  8165. (((_var) & HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M) >> \
  8166. HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S)
  8167. #define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_SET(_var, _val) \
  8168. do { \
  8169. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK, _val); \
  8170. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S)); \
  8171. } while (0)
  8172. /* Dword 1: fisa_control_value disable_ta_check */
  8173. #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M 0x00000200
  8174. #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S 9
  8175. #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_GET(_var) \
  8176. (((_var) & HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M) >> \
  8177. HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S)
  8178. #define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_SET(_var, _val) \
  8179. do { \
  8180. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK, _val); \
  8181. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S)); \
  8182. } while (0)
  8183. /* Dword 1: fisa_control_value disable_qos_check */
  8184. #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M 0x00000400
  8185. #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S 10
  8186. #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_GET(_var) \
  8187. (((_var) & HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M) >> \
  8188. HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S)
  8189. #define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_SET(_var, _val) \
  8190. do { \
  8191. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK, _val); \
  8192. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S)); \
  8193. } while (0)
  8194. /* Dword 1: fisa_control_value disable_raw_check */
  8195. #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M 0x00000800
  8196. #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S 11
  8197. #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_GET(_var) \
  8198. (((_var) & HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M) >> \
  8199. HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S)
  8200. #define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_SET(_var, _val) \
  8201. do { \
  8202. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK, _val); \
  8203. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S)); \
  8204. } while (0)
  8205. /* Dword 1: fisa_control_value disable_decrypt_err_check */
  8206. #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M 0x00001000
  8207. #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S 12
  8208. #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_GET(_var) \
  8209. (((_var) & HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M) >> \
  8210. HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S)
  8211. #define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_SET(_var, _val) \
  8212. do { \
  8213. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK, _val); \
  8214. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S)); \
  8215. } while (0)
  8216. /* Dword 1: fisa_control_value disable_msdu_drop_check */
  8217. #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M 0x00002000
  8218. #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S 13
  8219. #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_GET(_var) \
  8220. (((_var) & HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M) >> \
  8221. HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S)
  8222. #define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_SET(_var, _val) \
  8223. do { \
  8224. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK, _val); \
  8225. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S)); \
  8226. } while (0)
  8227. /* Dword 1: fisa_control_value fisa_aggr_limit */
  8228. #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M 0x0003c000
  8229. #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S 14
  8230. #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_GET(_var) \
  8231. (((_var) & HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M) >> \
  8232. HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S)
  8233. #define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_SET(_var, _val) \
  8234. do { \
  8235. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT, _val); \
  8236. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S)); \
  8237. } while (0)
  8238. /* Dword 1: fisa_control_value fisa config */
  8239. #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_M 0x00000001
  8240. #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S 0
  8241. #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_GET(_var) \
  8242. (((_var) & HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_M) >> \
  8243. HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S)
  8244. #define HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_SET(_var, _val) \
  8245. do { \
  8246. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_V2_ENABLE, _val); \
  8247. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_V2_ENABLE_S)); \
  8248. } while (0)
  8249. /* Dword 1: fisa_control_value fisa_aggr_limit */
  8250. #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M 0x0000007e
  8251. #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S 1
  8252. #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_GET(_var) \
  8253. (((_var) & HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M) >> \
  8254. HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S)
  8255. #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_SET(_var, _val) \
  8256. do { \
  8257. HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT, _val); \
  8258. ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S)); \
  8259. } while (0)
  8260. PREPACK struct htt_h2t_msg_rx_fse_setup_t {
  8261. A_UINT32 msg_type:8, /* HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG */
  8262. pdev_id:8,
  8263. reserved0:16;
  8264. A_UINT32 num_records:20,
  8265. max_search:8,
  8266. ip_da_sa:2, /* htt_ip_da_sa_prefix enumeration */
  8267. reserved1:2;
  8268. A_UINT32 base_addr_lo;
  8269. A_UINT32 base_addr_hi;
  8270. A_UINT32 toeplitz31_0;
  8271. A_UINT32 toeplitz63_32;
  8272. A_UINT32 toeplitz95_64;
  8273. A_UINT32 toeplitz127_96;
  8274. A_UINT32 toeplitz159_128;
  8275. A_UINT32 toeplitz191_160;
  8276. A_UINT32 toeplitz223_192;
  8277. A_UINT32 toeplitz255_224;
  8278. A_UINT32 toeplitz287_256;
  8279. A_UINT32 toeplitz314_288:27,
  8280. reserved2:5;
  8281. } POSTPACK;
  8282. #define HTT_RX_FSE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_fse_setup_t))
  8283. #define HTT_RX_FSE_OPERATION_SZ (sizeof(struct htt_h2t_msg_rx_fse_operation_t))
  8284. #define HTT_RX_FISA_CONFIG_SZ (sizeof(struct htt_h2t_msg_type_fisa_config_t))
  8285. #define HTT_RX_FSE_SETUP_HASH_314_288_M 0x07ffffff
  8286. #define HTT_RX_FSE_SETUP_HASH_314_288_S 0
  8287. /* DWORD 0: Pdev ID */
  8288. #define HTT_RX_FSE_SETUP_PDEV_ID_M 0x0000ff00
  8289. #define HTT_RX_FSE_SETUP_PDEV_ID_S 8
  8290. #define HTT_RX_FSE_SETUP_PDEV_ID_GET(_var) \
  8291. (((_var) & HTT_RX_FSE_SETUP_PDEV_ID_M) >> \
  8292. HTT_RX_FSE_SETUP_PDEV_ID_S)
  8293. #define HTT_RX_FSE_SETUP_PDEV_ID_SET(_var, _val) \
  8294. do { \
  8295. HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_PDEV_ID, _val); \
  8296. ((_var) |= ((_val) << HTT_RX_FSE_SETUP_PDEV_ID_S)); \
  8297. } while (0)
  8298. /* DWORD 1:num of records */
  8299. #define HTT_RX_FSE_SETUP_NUM_REC_M 0x000fffff
  8300. #define HTT_RX_FSE_SETUP_NUM_REC_S 0
  8301. #define HTT_RX_FSE_SETUP_NUM_REC_GET(_var) \
  8302. (((_var) & HTT_RX_FSE_SETUP_NUM_REC_M) >> \
  8303. HTT_RX_FSE_SETUP_NUM_REC_S)
  8304. #define HTT_RX_FSE_SETUP_NUM_REC_SET(_var, _val) \
  8305. do { \
  8306. HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_NUM_REC, _val); \
  8307. ((_var) |= ((_val) << HTT_RX_FSE_SETUP_NUM_REC_S)); \
  8308. } while (0)
  8309. /* DWORD 1:max_search */
  8310. #define HTT_RX_FSE_SETUP_MAX_SEARCH_M 0x0ff00000
  8311. #define HTT_RX_FSE_SETUP_MAX_SEARCH_S 20
  8312. #define HTT_RX_FSE_SETUP_MAX_SEARCH_GET(_var) \
  8313. (((_var) & HTT_RX_FSE_SETUP_MAX_SEARCH_M) >> \
  8314. HTT_RX_FSE_SETUP_MAX_SEARCH_S)
  8315. #define HTT_RX_FSE_SETUP_MAX_SEARCH_SET(_var, _val) \
  8316. do { \
  8317. HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_MAX_SEARCH, _val); \
  8318. ((_var) |= ((_val) << HTT_RX_FSE_SETUP_MAX_SEARCH_S)); \
  8319. } while (0)
  8320. /* DWORD 1:ip_da_sa prefix */
  8321. #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M 0x30000000
  8322. #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S 28
  8323. #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_GET(_var) \
  8324. (((_var) & HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M) >> \
  8325. HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S)
  8326. #define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_SET(_var, _val) \
  8327. do { \
  8328. HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX, _val); \
  8329. ((_var) |= ((_val) << HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S)); \
  8330. } while (0)
  8331. /* DWORD 2: Base Address LO */
  8332. #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_M 0xffffffff
  8333. #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_S 0
  8334. #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_GET(_var) \
  8335. (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_LO_M) >> \
  8336. HTT_RX_FSE_SETUP_BASE_ADDR_LO_S)
  8337. #define HTT_RX_FSE_SETUP_BASE_ADDR_LO_SET(_var, _val) \
  8338. do { \
  8339. HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_LO, _val); \
  8340. ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_LO_S)); \
  8341. } while (0)
  8342. /* DWORD 3: Base Address High */
  8343. #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_M 0xffffffff
  8344. #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_S 0
  8345. #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_GET(_var) \
  8346. (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_HI_M) >> \
  8347. HTT_RX_FSE_SETUP_BASE_ADDR_HI_S)
  8348. #define HTT_RX_FSE_SETUP_BASE_ADDR_HI_SET(_var, _val) \
  8349. do { \
  8350. HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_HI, _val); \
  8351. ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_HI_S)); \
  8352. } while (0)
  8353. /* DWORD 4-12: Hash Value */
  8354. #define HTT_RX_FSE_SETUP_HASH_VALUE_M 0xffffffff
  8355. #define HTT_RX_FSE_SETUP_HASH_VALUE_S 0
  8356. #define HTT_RX_FSE_SETUP_HASH_VALUE_GET(_var) \
  8357. (((_var) & HTT_RX_FSE_SETUP_HASH_VALUE_M) >> \
  8358. HTT_RX_FSE_SETUP_HASH_VALUE_S)
  8359. #define HTT_RX_FSE_SETUP_HASH_VALUE_SET(_var, _val) \
  8360. do { \
  8361. HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_VALUE, _val); \
  8362. ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_VALUE_S)); \
  8363. } while (0)
  8364. /* DWORD 13: Hash Value 314:288 bits */
  8365. #define HTT_RX_FSE_SETUP_HASH_314_288_GET(_var) \
  8366. (((_var) & HTT_RX_FSE_SETUP_HASH_314_288_M) >> \
  8367. HTT_RX_FSE_SETUP_HASH_314_288_S)
  8368. #define HTT_RX_FSE_SETUP_HASH_314_288_SET(_var, _val) \
  8369. do { \
  8370. HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_314_288, _val); \
  8371. ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_314_288_S)); \
  8372. } while (0)
  8373. /**
  8374. * @brief Host-->target HTT RX FSE operation message
  8375. *
  8376. * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG
  8377. *
  8378. * @details
  8379. * The host will send this Flow Search Engine (FSE) operation message for
  8380. * every flow add/delete operation.
  8381. * The FSE operation includes FSE full cache invalidation or individual entry
  8382. * invalidation.
  8383. * This message can be sent per SOC or per PDEV which is differentiated
  8384. * by pdev id values.
  8385. *
  8386. * |31 16|15 8|7 1|0|
  8387. * |-------------------------------------------------------------|
  8388. * | reserved | pdev_id | MSG_TYPE |
  8389. * |-------------------------------------------------------------|
  8390. * | reserved | operation |I|
  8391. * |-------------------------------------------------------------|
  8392. * | ip_src_addr_31_0 |
  8393. * |-------------------------------------------------------------|
  8394. * | ip_src_addr_63_32 |
  8395. * |-------------------------------------------------------------|
  8396. * | ip_src_addr_95_64 |
  8397. * |-------------------------------------------------------------|
  8398. * | ip_src_addr_127_96 |
  8399. * |-------------------------------------------------------------|
  8400. * | ip_dst_addr_31_0 |
  8401. * |-------------------------------------------------------------|
  8402. * | ip_dst_addr_63_32 |
  8403. * |-------------------------------------------------------------|
  8404. * | ip_dst_addr_95_64 |
  8405. * |-------------------------------------------------------------|
  8406. * | ip_dst_addr_127_96 |
  8407. * |-------------------------------------------------------------|
  8408. * | l4_dst_port | l4_src_port |
  8409. * | (32-bit SPI incase of IPsec) |
  8410. * |-------------------------------------------------------------|
  8411. * | reserved | l4_proto |
  8412. * |-------------------------------------------------------------|
  8413. *
  8414. * where I is 1-bit ipsec_valid.
  8415. *
  8416. * The following field definitions describe the format of the RX FSE operation
  8417. * message sent from the host to target for every add/delete flow entry to flow
  8418. * table.
  8419. *
  8420. * Header fields:
  8421. * dword0 - b'7:0 - msg_type: This will be set to
  8422. * 0x13 (HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG)
  8423. * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
  8424. * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the
  8425. * specified pdev's LMAC ring.
  8426. * b'31:16 - reserved : Reserved for future use
  8427. * dword1 - b'0 - ipsec_valid: This indicates protocol IP or IPsec
  8428. * (Internet Protocol Security).
  8429. * IPsec describes the framework for providing security at
  8430. * IP layer. IPsec is defined for both versions of IP:
  8431. * IPV4 and IPV6.
  8432. * Please refer to htt_rx_flow_proto enumeration below for
  8433. * more info.
  8434. * ipsec_valid = 1 for IPSEC packets
  8435. * ipsec_valid = 0 for IP Packets
  8436. * b'7:1 - operation: This indicates types of FSE operation.
  8437. * Refer to htt_rx_fse_operation enumeration:
  8438. * 0 - No Cache Invalidation required
  8439. * 1 - Cache invalidate only one entry given by IP
  8440. * src/dest address at DWORD[2:9]
  8441. * 2 - Complete FSE Cache Invalidation
  8442. * 3 - FSE Disable
  8443. * 4 - FSE Enable
  8444. * b'31:8 - reserved: Reserved for future use
  8445. * dword2:9-b'31:0 - IP src/dest: IPV4/IPV6 source and destination address
  8446. * for per flow addition/deletion
  8447. * For IPV4 src/dest addresses, the first A_UINT32 is used
  8448. * and the subsequent 3 A_UINT32 will be padding bytes.
  8449. * For IPV6 src/dest Addresses, all A_UINT32 are used.
  8450. * dword10 -b'31:0 - L4 src port (15:0): 16-bit Source Port numbers range
  8451. * from 0 to 65535 but only 0 to 1023 are designated as
  8452. * well-known ports. Refer to [RFC1700] for more details.
  8453. * This field is valid only if
  8454. * (valid_ip_proto(l4_proto) && (ipsec_valid == 0))
  8455. * - L4 dest port (31:16): 16-bit Destination Port numbers
  8456. * range from 0 to 65535 but only 0 to 1023 are designated
  8457. * as well-known ports. Refer to [RFC1700] for more details.
  8458. * This field is valid only if
  8459. * (valid_ip_proto(l4_proto) && (ipsec_valid == 0))
  8460. * - SPI (31:0): Security Parameters Index is an
  8461. * identification tag added to the header while using IPsec
  8462. * for tunneling the IP traffici.
  8463. * Valid only if IPSec_valid bit (in DWORD1) is set to 1.
  8464. * dword11 -b'7:0 - l4_proto: This carries L4 protocol numbers, which are
  8465. * Assigned Internet Protocol Numbers.
  8466. * l4_proto numbers for standard protocol like UDP/TCP
  8467. * protocol at l4 layer, e.g. l4_proto = 6 for TCP,
  8468. * l4_proto = 17 for UDP etc.
  8469. * b'31:8 - reserved: Reserved for future use.
  8470. *
  8471. */
  8472. PREPACK struct htt_h2t_msg_rx_fse_operation_t {
  8473. A_UINT32 msg_type:8,
  8474. pdev_id:8,
  8475. reserved0:16;
  8476. A_UINT32 ipsec_valid:1,
  8477. operation:7,
  8478. reserved1:24;
  8479. A_UINT32 ip_src_addr_31_0;
  8480. A_UINT32 ip_src_addr_63_32;
  8481. A_UINT32 ip_src_addr_95_64;
  8482. A_UINT32 ip_src_addr_127_96;
  8483. A_UINT32 ip_dest_addr_31_0;
  8484. A_UINT32 ip_dest_addr_63_32;
  8485. A_UINT32 ip_dest_addr_95_64;
  8486. A_UINT32 ip_dest_addr_127_96;
  8487. union {
  8488. A_UINT32 spi;
  8489. struct {
  8490. A_UINT32 l4_src_port:16,
  8491. l4_dest_port:16;
  8492. } ip;
  8493. } u;
  8494. A_UINT32 l4_proto:8,
  8495. reserved:24;
  8496. } POSTPACK;
  8497. /**
  8498. * @brief Host-->target HTT RX Full monitor mode register configuration message
  8499. *
  8500. * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE
  8501. *
  8502. * @details
  8503. * The host will send this Full monitor mode register configuration message.
  8504. * This message can be sent per SOC or per PDEV which is differentiated
  8505. * by pdev id values.
  8506. *
  8507. * |31 16|15 11|10 8|7 3|2|1|0|
  8508. * |-------------------------------------------------------------|
  8509. * | reserved | pdev_id | MSG_TYPE |
  8510. * |-------------------------------------------------------------|
  8511. * | reserved |Release Ring |N|Z|E|
  8512. * |-------------------------------------------------------------|
  8513. *
  8514. * where E is 1-bit full monitor mode enable/disable.
  8515. * Z is 1-bit additional descriptor for zero mpdu enable/disable
  8516. * N is 1-bit additional descriptor for non zero mdpu enable/disable
  8517. *
  8518. * The following field definitions describe the format of the full monitor
  8519. * mode configuration message sent from the host to target for each pdev.
  8520. *
  8521. * Header fields:
  8522. * dword0 - b'7:0 - msg_type: This will be set to
  8523. * 0x17 (HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE)
  8524. * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
  8525. * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the
  8526. * specified pdev's LMAC ring.
  8527. * b'31:16 - reserved : Reserved for future use.
  8528. * dword1 - b'0 - full_monitor_mode enable: This indicates that the full
  8529. * monitor mode rxdma register is to be enabled or disabled.
  8530. * b'1 - addnl_descs_zero_mpdus_end: This indicates that the
  8531. * additional descriptors at ppdu end for zero mpdus
  8532. * enabled or disabled.
  8533. * b'2 - addnl_descs_non_zero_mpdus_end: This indicates that the
  8534. * additional descriptors at ppdu end for non zero mpdus
  8535. * enabled or disabled.
  8536. * b'10:3 - release_ring: This indicates the destination ring
  8537. * selection for the descriptor at the end of PPDU
  8538. * 0 - REO ring select
  8539. * 1 - FW ring select
  8540. * 2 - SW ring select
  8541. * 3 - Release ring select
  8542. * Refer to htt_rx_full_mon_release_ring.
  8543. * b'31:11 - reserved for future use
  8544. */
  8545. PREPACK struct htt_h2t_msg_rx_full_monitor_mode_t {
  8546. A_UINT32 msg_type:8,
  8547. pdev_id:8,
  8548. reserved0:16;
  8549. A_UINT32 full_monitor_mode_enable:1,
  8550. addnl_descs_zero_mpdus_end:1,
  8551. addnl_descs_non_zero_mpdus_end:1,
  8552. release_ring:8,
  8553. reserved1:21;
  8554. } POSTPACK;
  8555. /**
  8556. * Enumeration for full monitor mode destination ring select
  8557. * 0 - REO destination ring select
  8558. * 1 - FW destination ring select
  8559. * 2 - SW destination ring select
  8560. * 3 - Release destination ring select
  8561. */
  8562. enum htt_rx_full_mon_release_ring {
  8563. HTT_RX_MON_RING_REO,
  8564. HTT_RX_MON_RING_FW,
  8565. HTT_RX_MON_RING_SW,
  8566. HTT_RX_MON_RING_RELEASE,
  8567. };
  8568. #define HTT_RX_FULL_MONITOR_MODE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_full_monitor_mode_t))
  8569. /* DWORD 0: Pdev ID */
  8570. #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M 0x0000ff00
  8571. #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S 8
  8572. #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_GET(_var) \
  8573. (((_var) & HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M) >> \
  8574. HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S)
  8575. #define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_SET(_var, _val) \
  8576. do { \
  8577. HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID, _val); \
  8578. ((_var) |= ((_val) << HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S)); \
  8579. } while (0)
  8580. /* DWORD 1:ENABLE */
  8581. #define HTT_RX_FULL_MONITOR_MODE_ENABLE_M 0x00000001
  8582. #define HTT_RX_FULL_MONITOR_MODE_ENABLE_S 0
  8583. #define HTT_RX_FULL_MONITOR_MODE_ENABLE_SET(word, enable) \
  8584. do { \
  8585. HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ENABLE, enable); \
  8586. (word) |= ((enable) << HTT_RX_FULL_MONITOR_MODE_ENABLE_S); \
  8587. } while (0)
  8588. #define HTT_RX_FULL_MONITOR_MODE_ENABLE_GET(word) \
  8589. (((word) & HTT_RX_FULL_MONITOR_MODE_ENABLE_M) >> HTT_RX_FULL_MONITOR_MODE_ENABLE_S)
  8590. /* DWORD 1:ZERO_MPDU */
  8591. #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M 0x00000002
  8592. #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S 1
  8593. #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_SET(word, zerompdu) \
  8594. do { \
  8595. HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU, zerompdu); \
  8596. (word) |= ((zerompdu) << HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S); \
  8597. } while (0)
  8598. #define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_GET(word) \
  8599. (((word) & HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S)
  8600. /* DWORD 1:NON_ZERO_MPDU */
  8601. #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M 0x00000004
  8602. #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S 2
  8603. #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_SET(word, nonzerompdu) \
  8604. do { \
  8605. HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU, nonzerompdu); \
  8606. (word) |= ((nonzerompdu) << HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S); \
  8607. } while (0)
  8608. #define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_GET(word) \
  8609. (((word) & HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S)
  8610. /* DWORD 1:RELEASE_RINGS */
  8611. #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M 0x000007f8
  8612. #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S 3
  8613. #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_SET(word, releaserings) \
  8614. do { \
  8615. HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS, releaserings); \
  8616. (word) |= ((releaserings) << HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S); \
  8617. } while (0)
  8618. #define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_GET(word) \
  8619. (((word) & HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M) >> HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S)
  8620. /**
  8621. * Enumeration for IP Protocol or IPSEC Protocol
  8622. * IPsec describes the framework for providing security at IP layer.
  8623. * IPsec is defined for both versions of IP: IPV4 and IPV6.
  8624. */
  8625. enum htt_rx_flow_proto {
  8626. HTT_RX_FLOW_IP_PROTO,
  8627. HTT_RX_FLOW_IPSEC_PROTO,
  8628. };
  8629. /**
  8630. * Enumeration for FSE Cache Invalidation
  8631. * 0 - No Cache Invalidation required
  8632. * 1 - Cache invalidate only one entry given by IP src/dest address at DWORD2:9
  8633. * 2 - Complete FSE Cache Invalidation
  8634. * 3 - FSE Disable
  8635. * 4 - FSE Enable
  8636. */
  8637. enum htt_rx_fse_operation {
  8638. HTT_RX_FSE_CACHE_INVALIDATE_NONE,
  8639. HTT_RX_FSE_CACHE_INVALIDATE_ENTRY,
  8640. HTT_RX_FSE_CACHE_INVALIDATE_FULL,
  8641. HTT_RX_FSE_DISABLE,
  8642. HTT_RX_FSE_ENABLE,
  8643. };
  8644. /* DWORD 0: Pdev ID */
  8645. #define HTT_RX_FSE_OPERATION_PDEV_ID_M 0x0000ff00
  8646. #define HTT_RX_FSE_OPERATION_PDEV_ID_S 8
  8647. #define HTT_RX_FSE_OPERATION_PDEV_ID_GET(_var) \
  8648. (((_var) & HTT_RX_FSE_OPERATION_PDEV_ID_M) >> \
  8649. HTT_RX_FSE_OPERATION_PDEV_ID_S)
  8650. #define HTT_RX_FSE_OPERATION_PDEV_ID_SET(_var, _val) \
  8651. do { \
  8652. HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_PDEV_ID, _val); \
  8653. ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_PDEV_ID_S)); \
  8654. } while (0)
  8655. /* DWORD 1:IP PROTO or IPSEC */
  8656. #define HTT_RX_FSE_IPSEC_VALID_M 0x00000001
  8657. #define HTT_RX_FSE_IPSEC_VALID_S 0
  8658. #define HTT_RX_FSE_IPSEC_VALID_SET(word, ipsec_valid) \
  8659. do { \
  8660. HTT_CHECK_SET_VAL(HTT_RX_FSE_IPSEC_VALID, ipsec_valid); \
  8661. (word) |= ((ipsec_valid) << HTT_RX_FSE_IPSEC_VALID_S); \
  8662. } while (0)
  8663. #define HTT_RX_FSE_IPSEC_VALID_GET(word) \
  8664. (((word) & HTT_RX_FSE_IPSEC_VALID_M) >> HTT_RX_FSE_IPSEC_VALID_S)
  8665. /* DWORD 1:FSE Operation */
  8666. #define HTT_RX_FSE_OPERATION_M 0x000000fe
  8667. #define HTT_RX_FSE_OPERATION_S 1
  8668. #define HTT_RX_FSE_OPERATION_SET(word, op_val) \
  8669. do { \
  8670. HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION, op_val); \
  8671. (word) |= ((op_val) << HTT_RX_FSE_OPERATION_S); \
  8672. } while (0)
  8673. #define HTT_RX_FSE_OPERATION_GET(word) \
  8674. (((word) & HTT_RX_FSE_OPERATION_M) >> HTT_RX_FSE_OPERATION_S)
  8675. /* DWORD 2-9:IP Address */
  8676. #define HTT_RX_FSE_OPERATION_IP_ADDR_M 0xffffffff
  8677. #define HTT_RX_FSE_OPERATION_IP_ADDR_S 0
  8678. #define HTT_RX_FSE_OPERATION_IP_ADDR_GET(_var) \
  8679. (((_var) & HTT_RX_FSE_OPERATION_IP_ADDR_M) >> \
  8680. HTT_RX_FSE_OPERATION_IP_ADDR_S)
  8681. #define HTT_RX_FSE_OPERATION_IP_ADDR_SET(_var, _val) \
  8682. do { \
  8683. HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_IP_ADDR, _val); \
  8684. ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_IP_ADDR_S)); \
  8685. } while (0)
  8686. /* DWORD 10:Source Port Number */
  8687. #define HTT_RX_FSE_SOURCEPORT_M 0x0000ffff
  8688. #define HTT_RX_FSE_SOURCEPORT_S 0
  8689. #define HTT_RX_FSE_SOURCEPORT_SET(word, sport) \
  8690. do { \
  8691. HTT_CHECK_SET_VAL(HTT_RX_FSE_SOURCEPORT, sport); \
  8692. (word) |= ((sport) << HTT_RX_FSE_SOURCEPORT_S); \
  8693. } while (0)
  8694. #define HTT_RX_FSE_SOURCEPORT_GET(word) \
  8695. (((word) & HTT_RX_FSE_SOURCEPORT_M) >> HTT_RX_FSE_SOURCEPORT_S)
  8696. /* DWORD 11:Destination Port Number */
  8697. #define HTT_RX_FSE_DESTPORT_M 0xffff0000
  8698. #define HTT_RX_FSE_DESTPORT_S 16
  8699. #define HTT_RX_FSE_DESTPORT_SET(word, dport) \
  8700. do { \
  8701. HTT_CHECK_SET_VAL(HTT_RX_FSE_DESTPORT, dport); \
  8702. (word) |= ((dport) << HTT_RX_FSE_DESTPORT_S); \
  8703. } while (0)
  8704. #define HTT_RX_FSE_DESTPORT_GET(word) \
  8705. (((word) & HTT_RX_FSE_DESTPORT_M) >> HTT_RX_FSE_DESTPORT_S)
  8706. /* DWORD 10-11:SPI (In case of IPSEC) */
  8707. #define HTT_RX_FSE_OPERATION_SPI_M 0xffffffff
  8708. #define HTT_RX_FSE_OPERATION_SPI_S 0
  8709. #define HTT_RX_FSE_OPERATION_SPI_GET(_var) \
  8710. (((_var) & HTT_RX_FSE_OPERATION_SPI_ADDR_M) >> \
  8711. HTT_RX_FSE_OPERATION_SPI_ADDR_S)
  8712. #define HTT_RX_FSE_OPERATION_SPI_SET(_var, _val) \
  8713. do { \
  8714. HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_SPI, _val); \
  8715. ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_SPI_S)); \
  8716. } while (0)
  8717. /* DWORD 12:L4 PROTO */
  8718. #define HTT_RX_FSE_L4_PROTO_M 0x000000ff
  8719. #define HTT_RX_FSE_L4_PROTO_S 0
  8720. #define HTT_RX_FSE_L4_PROTO_SET(word, proto_val) \
  8721. do { \
  8722. HTT_CHECK_SET_VAL(HTT_RX_FSE_L4_PROTO, proto_val); \
  8723. (word) |= ((proto_val) << HTT_RX_FSE_L4_PROTO_S); \
  8724. } while (0)
  8725. #define HTT_RX_FSE_L4_PROTO_GET(word) \
  8726. (((word) & HTT_RX_FSE_L4_PROTO_M) >> HTT_RX_FSE_L4_PROTO_S)
  8727. /**
  8728. * @brief host --> target Receive to configure the RxOLE 3-tuple Hash
  8729. *
  8730. * MSG_TYPE => HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG
  8731. *
  8732. * |31 24|23 |15 8|7 3|2|1|0|
  8733. * |----------------+----------------+----------------+----------------|
  8734. * | reserved | pdev_id | msg_type |
  8735. * |---------------------------------+----------------+----------------|
  8736. * | reserved |G|E|F|
  8737. * |---------------------------------+----------------+----------------|
  8738. * Where E = Configure the target to provide the 3-tuple hash value in
  8739. * toeplitz_hash_2_or_4 field of rx_msdu_start tlv
  8740. * F = Configure the target to provide the 3-tuple hash value in
  8741. * flow_id_toeplitz field of rx_msdu_start tlv
  8742. * G = Configure the target to provide the 3-tuple based flow
  8743. * classification search
  8744. *
  8745. * The following field definitions describe the format of the 3 tuple hash value
  8746. * message sent from the host to target as part of initialization sequence.
  8747. *
  8748. * Header fields:
  8749. * dword0 - b'7:0 - msg_type: This will be set to
  8750. * 0x16 (HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG)
  8751. * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
  8752. * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the
  8753. * specified pdev's LMAC ring.
  8754. * b'31:16 - reserved : Reserved for future use
  8755. * dword1 - b'0 - flow_id_toeplitz_field_enable
  8756. * b'1 - toeplitz_hash_2_or_4_field_enable
  8757. * b'2 - flow_classification_3_tuple_field_enable
  8758. * b'31:3 - reserved : Reserved for future use
  8759. * ---------+------+----------------------------------------------------------
  8760. * bit1 | bit0 | Functionality
  8761. * ---------+------+----------------------------------------------------------
  8762. * 0 | 1 | Configure the target to provide the 3 tuple hash value
  8763. * | | in flow_id_toeplitz field
  8764. * ---------+------+----------------------------------------------------------
  8765. * 1 | 0 | Configure the target to provide the 3 tuple hash value
  8766. * | | in toeplitz_hash_2_or_4 field
  8767. * ---------+------+----------------------------------------------------------
  8768. * 1 | 1 | Configure the target to provide the 3 tuple hash value
  8769. * | | in both flow_id_toeplitz & toeplitz_hash_2_or_4 field
  8770. * ---------+------+----------------------------------------------------------
  8771. * 0 | 0 | Configure the target to provide the 5 tuple hash value
  8772. * | | in flow_id_toeplitz field 2 or 4 tuple has value in
  8773. * | | toeplitz_hash_2_or_4 field
  8774. *----------------------------------------------------------------------------
  8775. */
  8776. PREPACK struct htt_h2t_msg_rx_3_tuple_hash_cfg_t {
  8777. A_UINT32 msg_type :8,
  8778. pdev_id :8,
  8779. reserved0 :16;
  8780. A_UINT32 flow_id_toeplitz_field_enable :1,
  8781. toeplitz_hash_2_or_4_field_enable :1,
  8782. flow_classification_3_tuple_field_enable :1,
  8783. reserved1 :29;
  8784. } POSTPACK;
  8785. /* DWORD0 : pdev_id configuration Macros */
  8786. #define HTT_H2T_3_TUPLE_HASH_PDEV_ID_M 0xff00
  8787. #define HTT_H2T_3_TUPLE_HASH_PDEV_ID_S 8
  8788. #define HTT_RX_3_TUPLE_HASH_PDEV_ID_GET(_var) \
  8789. (((_var) & HTT_H2T_3_TUPLE_HASH_PDEV_ID_M) >> \
  8790. HTT_H2T_3_TUPLE_HASH_PDEV_ID_S)
  8791. #define HTT_RX_3_TUPLE_HASH_PDEV_ID_SET(_var, _val) \
  8792. do { \
  8793. HTT_CHECK_SET_VAL(HTT_H2T_3_TUPLE_HASH_PDEV_ID, _val); \
  8794. ((_var) |= ((_val) << HTT_H2T_3_TUPLE_HASH_PDEV_ID_S)); \
  8795. } while (0)
  8796. /* DWORD1: rx 3 tuple hash value reception field configuration Macros */
  8797. #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_M 0x00000001
  8798. #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S 0
  8799. #define HTT_FLOW_ID_TOEPLITZ_FIELD_CONFIG_GET(_var) \
  8800. (((_var) & HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_M) >> \
  8801. HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S)
  8802. #define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_SET(_var, _val) \
  8803. do { \
  8804. HTT_CHECK_SET_VAL(HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG, _val); \
  8805. ((_var) |= ((_val) << HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S)); \
  8806. } while (0)
  8807. #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_M 0x00000002
  8808. #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S 1
  8809. #define HTT_TOEPLITZ_2_OR_4_FIELD_CONFIG_GET(_var) \
  8810. (((_var) & HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_M) >> \
  8811. HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S)
  8812. #define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_SET(_var, _val) \
  8813. do { \
  8814. HTT_CHECK_SET_VAL(HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG, _val); \
  8815. ((_var) |= ((_val) << HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S)); \
  8816. } while (0)
  8817. #define HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_M 0x00000004
  8818. #define HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_S 2
  8819. #define HTT_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_GET(_var) \
  8820. (((_var) & HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_M) >> \
  8821. HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_S)
  8822. #define HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_SET(_var, _val) \
  8823. do { \
  8824. HTT_CHECK_SET_VAL(HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE, _val); \
  8825. ((_var) |= ((_val) << HTT_H2T_FLOW_CLASSIFY_3_TUPLE_FIELD_ENABLE_S)); \
  8826. } while (0)
  8827. #define HTT_3_TUPLE_HASH_CFG_REQ_BYTES 8
  8828. /**
  8829. * @brief host --> target Host PA Address Size
  8830. *
  8831. * MSG_TYPE => HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE
  8832. *
  8833. * @details
  8834. * The HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE message is sent by the host to
  8835. * provide the physical start address and size of each of the memory
  8836. * areas within host DDR that the target FW may need to access.
  8837. *
  8838. * For example, the host can use this message to allow the target FW
  8839. * to set up access to the host's pools of TQM link descriptors.
  8840. * The message would appear as follows:
  8841. *
  8842. * |31 24|23 16|15 8|7 0|
  8843. * |----------------+----------------+----------------+----------------|
  8844. * | reserved | num_entries | msg_type |
  8845. * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-|
  8846. * | mem area 0 size |
  8847. * |----------------+----------------+----------------+----------------|
  8848. * | mem area 0 physical_address_lo |
  8849. * |----------------+----------------+----------------+----------------|
  8850. * | mem area 0 physical_address_hi |
  8851. * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-|
  8852. * | mem area 1 size |
  8853. * |----------------+----------------+----------------+----------------|
  8854. * | mem area 1 physical_address_lo |
  8855. * |----------------+----------------+----------------+----------------|
  8856. * | mem area 1 physical_address_hi |
  8857. * |----------------+----------------+----------------+----------------|
  8858. * ...
  8859. * |-=-=-=-=-=-=-=-=+-=-=-=-=-=-=-=-=+=-=-=-=-=-=-=-=-+=-=-=-=-=-=-=-=-|
  8860. * | mem area N size |
  8861. * |----------------+----------------+----------------+----------------|
  8862. * | mem area N physical_address_lo |
  8863. * |----------------+----------------+----------------+----------------|
  8864. * | mem area N physical_address_hi |
  8865. * |----------------+----------------+----------------+----------------|
  8866. *
  8867. * The message is interpreted as follows:
  8868. * dword0 - b'0:7 - msg_type: This will be set to
  8869. * 0x18 (HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE)
  8870. * b'8:15 - number_entries: Indicated the number of host memory
  8871. * areas specified within the remainder of the message
  8872. * b'16:31 - reserved.
  8873. * dword1 - b'0:31 - memory area 0 size in bytes
  8874. * dword2 - b'0:31 - memory area 0 physical address, lower 32 bits
  8875. * dword3 - b'0:31 - memory area 0 physical address, upper 32 bits
  8876. * and similar for memory area 1 through memory area N.
  8877. */
  8878. PREPACK struct htt_h2t_host_paddr_size {
  8879. A_UINT32 msg_type: 8,
  8880. num_entries: 8,
  8881. reserved: 16;
  8882. } POSTPACK;
  8883. PREPACK struct htt_h2t_host_paddr_size_entry_t {
  8884. A_UINT32 size;
  8885. A_UINT32 physical_address_lo;
  8886. A_UINT32 physical_address_hi;
  8887. } POSTPACK;
  8888. #define HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE \
  8889. (sizeof(struct htt_h2t_host_paddr_size_entry_t))
  8890. #define HTT_H2T_HOST_PADDR_SIZE_ENTRY_DWORDS \
  8891. (HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE >> 2)
  8892. #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_M 0x0000FF00
  8893. #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S 8
  8894. #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_GET(_var) \
  8895. (((_var) & HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_M) >> \
  8896. HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S)
  8897. #define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_SET(_var, _val) \
  8898. do { \
  8899. HTT_CHECK_SET_VAL(HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES, _val); \
  8900. ((_var) |= ((_val) << HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S)); \
  8901. } while (0)
  8902. /**
  8903. * @brief host --> target Host RXDMA RXOLE PPE register configuration
  8904. *
  8905. * MSG_TYPE => HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG
  8906. *
  8907. * @details
  8908. * The HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG message is sent by the host to
  8909. * provide the PPE DS register confiuration for RXOLE and RXDMA.
  8910. *
  8911. * The message would appear as follows:
  8912. *
  8913. * |31 19|18 |17 |16 |15 |14 |13 9|8|7 0|
  8914. * |---------------------------------+---+---+----------+-+-----------|
  8915. * | reserved |IFO|DNO|DRO|IBO|MIO| RDI |O| msg_type |
  8916. * |---------------------+---+---+---+---+---+----------+-+-----------|
  8917. *
  8918. *
  8919. * The message is interpreted as follows:
  8920. * dword0 - b'0:7 - msg_type: This will be set to
  8921. * 0x19 (HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG)
  8922. * b'8 - override bit to drive MSDUs to PPE ring
  8923. * b'9:13 - REO destination ring indication
  8924. * b'14 - Multi buffer msdu override enable bit
  8925. * b'15 - Intra BSS override
  8926. * b'16 - Decap raw override
  8927. * b'17 - Decap Native wifi override
  8928. * b'18 - IP frag override
  8929. * b'19:31 - reserved
  8930. */
  8931. PREPACK struct htt_h2t_msg_type_rxdma_rxole_ppe_cfg_t {
  8932. A_UINT32 msg_type: 8, /* HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG */
  8933. override: 1,
  8934. reo_destination_indication: 5,
  8935. multi_buffer_msdu_override_en: 1,
  8936. intra_bss_override: 1,
  8937. decap_raw_override: 1,
  8938. decap_nwifi_override: 1,
  8939. ip_frag_override: 1,
  8940. reserved: 13;
  8941. } POSTPACK;
  8942. /* DWORD 0: Override */
  8943. #define HTT_PPE_CFG_OVERRIDE_M 0x00000100
  8944. #define HTT_PPE_CFG_OVERRIDE_S 8
  8945. #define HTT_PPE_CFG_OVERRIDE_GET(_var) \
  8946. (((_var) & HTT_PPE_CFG_OVERRIDE_M) >> \
  8947. HTT_PPE_CFG_OVERRIDE_S)
  8948. #define HTT_PPE_CFG_OVERRIDE_SET(_var, _val) \
  8949. do { \
  8950. HTT_CHECK_SET_VAL(HTT_PPE_CFG_OVERRIDE, _val); \
  8951. ((_var) |= ((_val) << HTT_PPE_CFG_OVERRIDE_S)); \
  8952. } while (0)
  8953. /* DWORD 0: REO Destination Indication*/
  8954. #define HTT_PPE_CFG_REO_DEST_IND_M 0x00003E00
  8955. #define HTT_PPE_CFG_REO_DEST_IND_S 9
  8956. #define HTT_PPE_CFG_REO_DEST_IND_GET(_var) \
  8957. (((_var) & HTT_PPE_CFG_REO_DEST_IND_M) >> \
  8958. HTT_PPE_CFG_REO_DEST_IND_S)
  8959. #define HTT_PPE_CFG_REO_DEST_IND_SET(_var, _val) \
  8960. do { \
  8961. HTT_CHECK_SET_VAL(HTT_PPE_CFG_REO_DEST_IND, _val); \
  8962. ((_var) |= ((_val) << HTT_PPE_CFG_REO_DEST_IND_S)); \
  8963. } while (0)
  8964. /* DWORD 0: Multi buffer MSDU override */
  8965. #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_M 0x00004000
  8966. #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S 14
  8967. #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_GET(_var) \
  8968. (((_var) & HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_M) >> \
  8969. HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S)
  8970. #define HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_SET(_var, _val) \
  8971. do { \
  8972. HTT_CHECK_SET_VAL(HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN, _val); \
  8973. ((_var) |= ((_val) << HTT_PPE_CFG_MULTI_BUF_MSDU_OVERRIDE_EN_S)); \
  8974. } while (0)
  8975. /* DWORD 0: Intra BSS override */
  8976. #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_M 0x00008000
  8977. #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S 15
  8978. #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_GET(_var) \
  8979. (((_var) & HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_M) >> \
  8980. HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S)
  8981. #define HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_SET(_var, _val) \
  8982. do { \
  8983. HTT_CHECK_SET_VAL(HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN, _val); \
  8984. ((_var) |= ((_val) << HTT_PPE_CFG_INTRA_BSS_OVERRIDE_EN_S)); \
  8985. } while (0)
  8986. /* DWORD 0: Decap RAW override */
  8987. #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_M 0x00010000
  8988. #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S 16
  8989. #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_GET(_var) \
  8990. (((_var) & HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_M) >> \
  8991. HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S)
  8992. #define HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_SET(_var, _val) \
  8993. do { \
  8994. HTT_CHECK_SET_VAL(HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN, _val); \
  8995. ((_var) |= ((_val) << HTT_PPE_CFG_DECAP_RAW_OVERRIDE_EN_S)); \
  8996. } while (0)
  8997. /* DWORD 0: Decap NWIFI override */
  8998. #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_M 0x00020000
  8999. #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S 17
  9000. #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_GET(_var) \
  9001. (((_var) & HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_M) >> \
  9002. HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S)
  9003. #define HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_SET(_var, _val) \
  9004. do { \
  9005. HTT_CHECK_SET_VAL(HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN, _val); \
  9006. ((_var) |= ((_val) << HTT_PPE_CFG_DECAP_NWIFI_OVERRIDE_EN_S)); \
  9007. } while (0)
  9008. /* DWORD 0: IP frag override */
  9009. #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_M 0x00040000
  9010. #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S 18
  9011. #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_GET(_var) \
  9012. (((_var) & HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_M) >> \
  9013. HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S)
  9014. #define HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_SET(_var, _val) \
  9015. do { \
  9016. HTT_CHECK_SET_VAL(HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN, _val); \
  9017. ((_var) |= ((_val) << HTT_PPE_CFG_IP_FRAG_OVERRIDE_EN_S)); \
  9018. } while (0)
  9019. /*
  9020. * MSG_TYPE => HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG
  9021. *
  9022. * @details
  9023. * The following field definitions describe the format of the HTT host
  9024. * to target FW VDEV TX RX stats retrieve message.
  9025. * The message specifies the type of stats the host wants to retrieve.
  9026. *
  9027. * |31 27|26 25|24 17|16|15 8|7 0|
  9028. * |-----------------------------------------------------------|
  9029. * | rsvd | R | Periodic Int| E| pdev_id | msg type |
  9030. * |-----------------------------------------------------------|
  9031. * | vdev_id lower bitmask |
  9032. * |-----------------------------------------------------------|
  9033. * | vdev_id upper bitmask |
  9034. * |-----------------------------------------------------------|
  9035. * Header fields:
  9036. * Where:
  9037. * dword0 - b'7:0 - msg_type: This will be set to
  9038. * 0x1a (HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG)
  9039. * b'15:8 - pdev id
  9040. * b'16(E) - Enable/Disable the vdev HW stats
  9041. * b'17:24(PI) - Periodic Interval, units = 8 ms, e.g. 125 -> 1000 ms
  9042. * b'25:26(R) - Reset stats bits
  9043. * 0: don't reset stats
  9044. * 1: reset stats once
  9045. * 2: reset stats at the start of each periodic interval
  9046. * b'27:31 - reserved for future use
  9047. * dword1 - b'0:31 - vdev_id lower bitmask
  9048. * dword2 - b'0:31 - vdev_id upper bitmask
  9049. */
  9050. PREPACK struct htt_h2t_vdevs_txrx_stats_cfg {
  9051. A_UINT32 msg_type :8,
  9052. pdev_id :8,
  9053. enable :1,
  9054. periodic_interval :8,
  9055. reset_stats_bits :2,
  9056. reserved0 :5;
  9057. A_UINT32 vdev_id_lower_bitmask;
  9058. A_UINT32 vdev_id_upper_bitmask;
  9059. } POSTPACK;
  9060. #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_M 0xFF00
  9061. #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S 8
  9062. #define HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_GET(_var) \
  9063. (((_var) & HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_M) >> \
  9064. HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S)
  9065. #define HTT_RX_VDEVS_TXRX_STATS_PDEV_ID_SET(_var, _val) \
  9066. do { \
  9067. HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID, _val); \
  9068. ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_PDEV_ID_S)); \
  9069. } while (0)
  9070. #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_M 0x10000
  9071. #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S 16
  9072. #define HTT_H2T_VDEVS_TXRX_STATS_ENABLE_GET(_var) \
  9073. (((_var) & HTT_H2T_VDEVS_TXRX_STATS_ENABLE_M) >> \
  9074. HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S)
  9075. #define HTT_RX_VDEVS_TXRX_STATS_ENABLE_SET(_var, _val) \
  9076. do { \
  9077. HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_ENABLE, _val); \
  9078. ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_ENABLE_S)); \
  9079. } while (0)
  9080. #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_M 0x1FE0000
  9081. #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S 17
  9082. #define HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_GET(_var) \
  9083. (((_var) & HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_M) >> \
  9084. HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S)
  9085. #define HTT_RX_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_SET(_var, _val) \
  9086. do { \
  9087. HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL, _val); \
  9088. ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_PERIODIC_INTERVAL_S)); \
  9089. } while (0)
  9090. #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_M 0x6000000
  9091. #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S 25
  9092. #define HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_GET(_var) \
  9093. (((_var) & HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_M) >> \
  9094. HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S)
  9095. #define HTT_RX_VDEVS_TXRX_STATS_RESET_STATS_BITS_SET(_var, _val) \
  9096. do { \
  9097. HTT_CHECK_SET_VAL(HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS, _val); \
  9098. ((_var) |= ((_val) << HTT_H2T_VDEVS_TXRX_STATS_RESET_STATS_BITS_S)); \
  9099. } while (0)
  9100. /*
  9101. * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ
  9102. *
  9103. * @details
  9104. * The SAWF_DEF_QUEUES_MAP_REQ message is sent by the host to link
  9105. * the default MSDU queues for one of the TIDs within the specified peer
  9106. * to the specified service class.
  9107. * The TID is indirectly specified - each service class is associated
  9108. * with a TID. All default MSDU queues for this peer-TID will be
  9109. * linked to the service class in question.
  9110. *
  9111. * |31 16|15 8|7 0|
  9112. * |------------------------------+--------------+--------------|
  9113. * | peer ID | svc class ID | msg type |
  9114. * |------------------------------------------------------------|
  9115. * Header fields:
  9116. * dword0 - b'7:0 - msg_type: This will be set to
  9117. * 0x1c (HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ)
  9118. * b'15:8 - service class ID
  9119. * b'31:16 - peer ID
  9120. */
  9121. PREPACK struct htt_h2t_sawf_def_queues_map_req {
  9122. A_UINT32 msg_type :8,
  9123. svc_class_id :8,
  9124. peer_id :16;
  9125. } POSTPACK;
  9126. #define HTT_SAWF_DEF_QUEUES_MAP_REQ_BYTES 4
  9127. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_M 0x0000FF00
  9128. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S 8
  9129. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_GET(_var) \
  9130. (((_var) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_M) >> \
  9131. HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S)
  9132. #define HTT_RX_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_SET(_var, _val) \
  9133. do { \
  9134. HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID, _val); \
  9135. ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_SVC_CLASS_ID_S));\
  9136. } while (0)
  9137. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_M 0xFFFF0000
  9138. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S 16
  9139. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_GET(_var) \
  9140. (((_var) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_M) >> \
  9141. HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S)
  9142. #define HTT_RX_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_SET(_var, _val) \
  9143. do { \
  9144. HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID, _val); \
  9145. ((_var) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ_PEER_ID_S)); \
  9146. } while (0)
  9147. /*
  9148. * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ
  9149. *
  9150. * @details
  9151. * The SAWF_DEF_QUEUES_UNMAP_REQ message is sent by the host to
  9152. * remove the linkage of the specified peer-TID's MSDU queues to
  9153. * service classes.
  9154. *
  9155. * |31 16|15 8|7 0|
  9156. * |------------------------------+--------------+--------------|
  9157. * | peer ID | svc class ID | msg type |
  9158. * |------------------------------------------------------------|
  9159. * Header fields:
  9160. * dword0 - b'7:0 - msg_type: This will be set to
  9161. * 0x1d (HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ)
  9162. * b'15:8 - service class ID
  9163. * b'31:16 - peer ID
  9164. * A HTT_H2T_SAWF_DEF_QUEUES_UNMAP_PEER_ID_WILDCARD
  9165. * value for peer ID indicates that the target should
  9166. * apply the UNMAP_REQ to all peers.
  9167. */
  9168. #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_PEER_ID_WILDCARD 0xff
  9169. PREPACK struct htt_h2t_sawf_def_queues_unmap_req {
  9170. A_UINT32 msg_type :8,
  9171. svc_class_id :8,
  9172. peer_id :16;
  9173. } POSTPACK;
  9174. #define HTT_SAWF_DEF_QUEUES_UNMAP_REQ_BYTES 4
  9175. #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M 0x0000FF00
  9176. #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S 8
  9177. #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_GET(word0) \
  9178. (((word0) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_M) >> \
  9179. HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S)
  9180. #define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_SET(word0, _val) \
  9181. do { \
  9182. HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID, _val); \
  9183. ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_SVC_CLASS_ID_S)); \
  9184. } while (0)
  9185. #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M 0xFFFF0000
  9186. #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S 16
  9187. #define HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_GET(word0) \
  9188. (((word0) & HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_M) >> \
  9189. HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S)
  9190. #define HTT_RX_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_SET(word0, _val) \
  9191. do { \
  9192. HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID, _val); \
  9193. ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ_PEER_ID_S)); \
  9194. } while (0)
  9195. /*
  9196. * MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ
  9197. *
  9198. * @details
  9199. * The SAWF_DEF_QUEUES_MAP_REPORT_REQ message is sent by the host to
  9200. * request the target to report what service class the default MSDU queues
  9201. * of the specified TIDs within the peer are linked to.
  9202. * The target will respond with a SAWF_DEF_QUEUES_MAP_REPORT_CONF message
  9203. * to report what service class (if any) the default MSDU queues for
  9204. * each of the specified TIDs are linked to.
  9205. *
  9206. * |31 16|15 8|7 1| 0|
  9207. * |------------------------------+--------------+--------------|
  9208. * | peer ID | TID mask | msg type |
  9209. * |------------------------------------------------------------|
  9210. * | reserved |ETO|
  9211. * |------------------------------------------------------------|
  9212. * Header fields:
  9213. * dword0 - b'7:0 - msg_type: This will be set to
  9214. * 0x1e (HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ)
  9215. * b'15:8 - TID mask
  9216. * b'31:16 - peer ID
  9217. * dword1 - b'0 - "Existing Tids Only" flag
  9218. * If this flag is set, the DEF_QUEUES_MAP_REPORT_CONF
  9219. * message generated by this REQ will only show the
  9220. * mapping for TIDs that actually exist in the target's
  9221. * peer object.
  9222. * Any TIDs that are covered by a MAP_REQ but which
  9223. * do not actually exist will be shown as being
  9224. * unmapped (i.e. svc class ID 0xff).
  9225. * If this flag is cleared, the MAP_REPORT_CONF message
  9226. * will consider not only the mapping of TIDs currently
  9227. * existing in the peer, but also the mapping that will
  9228. * be applied for any TID objects created within this
  9229. * peer in the future.
  9230. * b'31:1 - reserved for future use
  9231. */
  9232. PREPACK struct htt_h2t_sawf_def_queues_map_report_req {
  9233. A_UINT32 msg_type :8,
  9234. tid_mask :8,
  9235. peer_id :16;
  9236. A_UINT32 existing_tids_only:1,
  9237. reserved :31;
  9238. } POSTPACK;
  9239. #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_REQ_BYTES 8
  9240. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M 0x0000FF00
  9241. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S 8
  9242. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_GET(word0) \
  9243. (((word0) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_M) >> \
  9244. HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S)
  9245. #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_SET(word0, _val) \
  9246. do { \
  9247. HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK, _val); \
  9248. ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_TID_MASK_S));\
  9249. } while (0)
  9250. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M 0xFFFF0000
  9251. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S 16
  9252. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_GET(word0) \
  9253. (((word0) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_M) >> \
  9254. HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S)
  9255. #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_SET(word0, _val) \
  9256. do { \
  9257. HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID, _val); \
  9258. ((word0) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_PEER_ID_S)); \
  9259. } while (0)
  9260. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_M 0x00000001
  9261. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S 0
  9262. #define HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_GET(word1) \
  9263. (((word1) & HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_M) >> \
  9264. HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S)
  9265. #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_SET(word1, _val) \
  9266. do { \
  9267. HTT_CHECK_SET_VAL(HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY, _val); \
  9268. ((word1) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S)); \
  9269. } while (0)
  9270. /**
  9271. * @brief Format of shared memory between Host and Target
  9272. * for UMAC recovery feature messaging.
  9273. * @details
  9274. * This is shared memory between Host and Target allocated
  9275. * and used in chips where UMAC recovery feature is supported.
  9276. * This shared memory is allocated per SOC level by Host since each
  9277. * SOC's target Q6FW needs to communicate independently to the Host
  9278. * through its own shared memory.
  9279. * If target sets a bit in t2h_msg (provided it's valid bit offset)
  9280. * then host interprets it as a new message from target.
  9281. * Host clears that particular read bit in t2h_msg after each read
  9282. * operation. It is vice versa for h2t_msg. At any given point
  9283. * of time there is expected to be only one bit set
  9284. * either in t2h_msg or h2t_msg (referring to valid bit offset).
  9285. *
  9286. * The message is interpreted as follows:
  9287. * dword0 - b'0:31 - magic_num: Magic number for the shared memory region
  9288. * added for debuggability purpose.
  9289. * dword1 - b'0 - do_pre_reset
  9290. * b'1 - do_post_reset_start
  9291. * b'2 - do_post_reset_complete
  9292. * b'3 - initiate_umac_recovery
  9293. * b'4 - initiate_target_recovery_sync_using_umac
  9294. * b'5:31 - rsvd_t2h
  9295. * dword2 - b'0 - pre_reset_done
  9296. * b'1 - post_reset_start_done
  9297. * b'2 - post_reset_complete_done
  9298. * b'3 - start_pre_reset (deprecated)
  9299. * b'4:31 - rsvd_h2t
  9300. */
  9301. PREPACK typedef struct {
  9302. /** Magic number added for debuggability. */
  9303. A_UINT32 magic_num;
  9304. union {
  9305. /*
  9306. * BIT [0] :- T2H msg to do pre-reset
  9307. * BIT [1] :- T2H msg to do post-reset start
  9308. * BIT [2] :- T2H msg to do post-reset complete
  9309. * BIT [3] :- T2H msg to indicate to Host that
  9310. * a trigger request for MLO UMAC Recovery
  9311. * is received for UMAC hang.
  9312. * BIT [4] :- T2H msg to indicate to Host that
  9313. * a trigger request for MLO UMAC Recovery
  9314. * is received for Mode-1 Target Recovery.
  9315. * BIT [31 : 5] :- reserved
  9316. */
  9317. A_UINT32 t2h_msg;
  9318. struct {
  9319. A_UINT32
  9320. do_pre_reset: 1, /* BIT [0] */
  9321. do_post_reset_start: 1, /* BIT [1] */
  9322. do_post_reset_complete: 1, /* BIT [2] */
  9323. initiate_umac_recovery: 1, /* BIT [3] */
  9324. initiate_target_recovery_sync_using_umac: 1, /* BIT [4] */
  9325. rsvd_t2h: 27; /* BIT [31:5] */
  9326. };
  9327. };
  9328. union {
  9329. /*
  9330. * BIT [0] :- H2T msg to send pre-reset done
  9331. * BIT [1] :- H2T msg to send post-reset start done
  9332. * BIT [2] :- H2T msg to send post-reset complete done
  9333. * BIT [3] :- H2T msg to start pre-reset. This is deprecated.
  9334. * BIT [31 : 4] :- reserved
  9335. */
  9336. A_UINT32 h2t_msg;
  9337. struct {
  9338. A_UINT32 pre_reset_done : 1, /* BIT [0] */
  9339. post_reset_start_done : 1, /* BIT [1] */
  9340. post_reset_complete_done : 1, /* BIT [2] */
  9341. start_pre_reset : 1, /* BIT [3] */
  9342. rsvd_h2t : 28; /* BIT [31 : 4] */
  9343. };
  9344. };
  9345. } POSTPACK htt_umac_hang_recovery_msg_shmem_t;
  9346. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_BYTES \
  9347. (sizeof(htt_umac_hang_recovery_msg_shmem_t))
  9348. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DWORDS \
  9349. (HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_BYTES >> 2)
  9350. /* dword1 - b'0 - do_pre_reset */
  9351. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_M 0x00000001
  9352. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S 0
  9353. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_GET(word1) \
  9354. (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_M) >> \
  9355. HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S)
  9356. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_SET(word1, _val) \
  9357. do { \
  9358. HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET, _val); \
  9359. ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S));\
  9360. } while (0)
  9361. /* dword1 - b'1 - do_post_reset_start */
  9362. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_M 0x00000002
  9363. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S 1
  9364. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_GET(word1) \
  9365. (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_M) >> \
  9366. HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S)
  9367. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_SET(word1, _val) \
  9368. do { \
  9369. HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START, _val); \
  9370. ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S));\
  9371. } while (0)
  9372. /* dword1 - b'2 - do_post_reset_complete */
  9373. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_M 0x00000004
  9374. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S 2
  9375. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_GET(word1) \
  9376. (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_M) >> \
  9377. HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S)
  9378. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_SET(word1, _val) \
  9379. do { \
  9380. HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE, _val); \
  9381. ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S));\
  9382. } while (0)
  9383. /* dword1 - b'3 - initiate_umac_recovery */
  9384. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M 0x00000008
  9385. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S 3
  9386. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_GET(word1) \
  9387. (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \
  9388. HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S)
  9389. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_SET(word1, _val) \
  9390. do { \
  9391. HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY, _val); \
  9392. ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S));\
  9393. } while (0)
  9394. /* dword1 - b'4 - initiate_target_recovery_sync_using_umac */
  9395. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M 0x00000010
  9396. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S 4
  9397. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_GET(word1) \
  9398. (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M) >> \
  9399. HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S)
  9400. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_SET(word1, _val) \
  9401. do { \
  9402. HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC, _val); \
  9403. ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S));\
  9404. } while (0)
  9405. /* dword2 - b'0 - pre_reset_done */
  9406. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M 0x00000001
  9407. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S 0
  9408. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_GET(word2) \
  9409. (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M) >> \
  9410. HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S)
  9411. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_SET(word2, _val) \
  9412. do { \
  9413. HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE, _val); \
  9414. ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S));\
  9415. } while (0)
  9416. /* dword2 - b'1 - post_reset_start_done */
  9417. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_M 0x00000002
  9418. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S 1
  9419. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_GET(word2) \
  9420. (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_M) >> \
  9421. HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S)
  9422. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_SET(word2, _val) \
  9423. do { \
  9424. HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE, _val); \
  9425. ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S));\
  9426. } while (0)
  9427. /* dword2 - b'2 - post_reset_complete_done */
  9428. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_M 0x00000004
  9429. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S 2
  9430. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_GET(word2) \
  9431. (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_M) >> \
  9432. HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S)
  9433. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_SET(word2, _val) \
  9434. do { \
  9435. HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE, _val); \
  9436. ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S));\
  9437. } while (0)
  9438. /* dword2 - b'3 - start_pre_reset */
  9439. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_M 0x00000008
  9440. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S 3
  9441. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_GET(word2) \
  9442. (((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_M) >> \
  9443. HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S)
  9444. #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_SET(word2, _val) \
  9445. do { \
  9446. HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET, _val); \
  9447. ((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_START_PRE_RESET_S));\
  9448. } while (0)
  9449. /**
  9450. * @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message
  9451. *
  9452. * @details
  9453. * The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message is sent
  9454. * by the host to provide prerequisite info to target for the UMAC hang
  9455. * recovery feature.
  9456. * The info sent in this H2T message are T2H message method, H2T message
  9457. * method, T2H MSI interrupt number and physical start address, size of
  9458. * the shared memory (refers to the shared memory dedicated for messaging
  9459. * between host and target when the DUT is in UMAC hang recovery mode).
  9460. * This H2T message is expected to be only sent if the WMI service bit
  9461. * WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target.
  9462. *
  9463. * |31 16|15 12|11 8|7 0|
  9464. * |-------------------------------+--------------+--------------+------------|
  9465. * | reserved |h2t msg method|t2h msg method| msg_type |
  9466. * |--------------------------------------------------------------------------|
  9467. * | t2h msi interrupt number |
  9468. * |--------------------------------------------------------------------------|
  9469. * | shared memory area size |
  9470. * |--------------------------------------------------------------------------|
  9471. * | shared memory area physical address low |
  9472. * |--------------------------------------------------------------------------|
  9473. * | shared memory area physical address high |
  9474. * |--------------------------------------------------------------------------|
  9475. *
  9476. * The message is interpreted as follows:
  9477. * dword0 - b'0:7 - msg_type
  9478. * (HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP)
  9479. * b'8:11 - t2h_msg_method: indicates method to be used for
  9480. * T2H communication in UMAC hang recovery mode.
  9481. * Value zero indicates MSI interrupt (default method).
  9482. * Refer to htt_umac_hang_recovery_msg_method enum.
  9483. * b'12:15 - h2t_msg_method: indicates method to be used for
  9484. * H2T communication in UMAC hang recovery mode.
  9485. * Value zero indicates polling by target for this h2t msg
  9486. * during UMAC hang recovery mode.
  9487. * Refer to htt_umac_hang_recovery_msg_method enum.
  9488. * b'16:31 - reserved.
  9489. * dword1 - b'0:31 - t2h_msi_data: MSI data to be used for
  9490. * T2H communication in UMAC hang recovery mode.
  9491. * dword2 - b'0:31 - size: size of shared memory dedicated for messaging
  9492. * only when in UMAC hang recovery mode.
  9493. * This refers to size in bytes.
  9494. * dword3 - b'0:31 - physical_address_lo: lower 32 bit physical address
  9495. * of the shared memory dedicated for messaging only when
  9496. * in UMAC hang recovery mode.
  9497. * dword4 - b'0:31 - physical_address_hi: higher 32 bit physical address
  9498. * of the shared memory dedicated for messaging only when
  9499. * in UMAC hang recovery mode.
  9500. */
  9501. /* t2h_msg_method and h2t_msg_method */
  9502. enum htt_umac_hang_recovery_msg_method {
  9503. htt_umac_hang_recovery_msg_t2h_msi_and_h2t_polling = 0,
  9504. };
  9505. PREPACK typedef struct {
  9506. A_UINT32 msg_type : 8,
  9507. t2h_msg_method : 4,
  9508. h2t_msg_method : 4,
  9509. reserved : 16;
  9510. A_UINT32 t2h_msi_data;
  9511. /* size bytes and physical address of shared memory. */
  9512. struct htt_h2t_host_paddr_size_entry_t msg_shared_mem;
  9513. } POSTPACK htt_h2t_umac_hang_recovery_prerequisite_setup_t;
  9514. #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_BYTES \
  9515. (sizeof(htt_h2t_umac_hang_recovery_prerequisite_setup_t))
  9516. #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_DWORDS \
  9517. (HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_BYTES >> 2)
  9518. #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_M 0x00000F00
  9519. #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S 8
  9520. #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_GET(word0) \
  9521. (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_M) >> \
  9522. HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S)
  9523. #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_SET(word0, _val) \
  9524. do { \
  9525. HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD, _val); \
  9526. ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S));\
  9527. } while (0)
  9528. #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_M 0x0000F000
  9529. #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S 12
  9530. #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_GET(word0) \
  9531. (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_M) >> \
  9532. HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S)
  9533. #define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_SET(word0, _val) \
  9534. do { \
  9535. HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD, _val); \
  9536. ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S));\
  9537. } while (0)
  9538. /**
  9539. * @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET message
  9540. *
  9541. * @details
  9542. * The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET is a SOC level
  9543. * HTT message sent by the host to indicate that the target needs to start the
  9544. * UMAC hang recovery feature from the point of pre-reset routine.
  9545. * The purpose of this H2T message is to have host synchronize and trigger
  9546. * UMAC recovery across all targets.
  9547. * The info sent in this H2T message is the flag to indicate whether the
  9548. * target needs to execute UMAC-recovery in context of the Initiator or
  9549. * Non-Initiator.
  9550. * This H2T message is expected to be sent as response to the
  9551. * initiate_umac_recovery indication from the Initiator target attached to
  9552. * this same host.
  9553. * This H2T message is expected to be only sent if the WMI service bit
  9554. * WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target
  9555. * and HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP was sent
  9556. * beforehand.
  9557. *
  9558. * |31 10|9|8|7 0|
  9559. * |-----------------------------------------------------------|
  9560. * | reserved |U|I| msg_type |
  9561. * |-----------------------------------------------------------|
  9562. * Where:
  9563. * I = is_initiator
  9564. * U = is_umac_hang
  9565. *
  9566. * The message is interpreted as follows:
  9567. * dword0 - b'0:7 - msg_type
  9568. * (HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET)
  9569. * b'8 - is_initiator: indicates whether the target needs to
  9570. * execute the UMAC-recovery in context of the Initiator or
  9571. * Non-Initiator.
  9572. * The value zero indicates this target is Non-Initiator.
  9573. * b'9 - is_umac_hang: indicates whether MLO UMAC recovery
  9574. * executed in context of UMAC hang or Target recovery.
  9575. * b'10:31 - reserved.
  9576. */
  9577. PREPACK typedef struct {
  9578. A_UINT32 msg_type : 8,
  9579. is_initiator : 1,
  9580. is_umac_hang : 1,
  9581. reserved : 22;
  9582. } POSTPACK htt_h2t_umac_hang_recovery_start_pre_reset_t;
  9583. #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES \
  9584. (sizeof(htt_h2t_umac_hang_recovery_start_pre_reset_t))
  9585. #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_DWORDS \
  9586. (HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES >> 2)
  9587. #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_M 0x00000100
  9588. #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S 8
  9589. #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_GET(word0) \
  9590. (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_M) >> \
  9591. HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S)
  9592. #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_SET(word0, _val) \
  9593. do { \
  9594. HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR, _val); \
  9595. ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S));\
  9596. } while (0)
  9597. #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M 0x00000200
  9598. #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S 9
  9599. #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_GET(word0) \
  9600. (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M) >> \
  9601. HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S)
  9602. #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_SET(word0, _val) \
  9603. do { \
  9604. HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG, _val); \
  9605. ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S));\
  9606. } while (0)
  9607. /*
  9608. * @brief host -> target HTT RX_CCE_SUPER_RULE_SETUP message
  9609. *
  9610. * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP
  9611. *
  9612. * @details
  9613. * Host sends RX_CCE_SUPER_RULE setup message to target, in order to request,
  9614. * install or uninstall rx cce super rules to match certain kind of packets
  9615. * with specific parameters. Target sets up HW registers based on setup message
  9616. * and always confirms back to Host.
  9617. *
  9618. * The message would appear as follows:
  9619. * |31 24|23 16|15 8|7 0|
  9620. * |-----------------+-----------------+-----------------+-----------------|
  9621. * | reserved | operation | pdev_id | msg_type |
  9622. * |-----------------------------------------------------------------------|
  9623. * | cce_super_rule_param[0] |
  9624. * |-----------------------------------------------------------------------|
  9625. * | cce_super_rule_param[1] |
  9626. * |-----------------------------------------------------------------------|
  9627. *
  9628. * The message is interpreted as follows:
  9629. * dword0 - b'0:7 - msg_type: This will be set to
  9630. * 0x23 (HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP)
  9631. * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is for
  9632. * b'16:23 - operation: Identify operation to be taken,
  9633. * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST
  9634. * 1: HTT_RX_CCE_SUPER_RULE_INSTALL
  9635. * 2: HTT_RX_CCE_SUPER_RULE_RELEASE
  9636. * b'24:31 - reserved
  9637. * dword1~10 - cce_super_rule_param[0]:
  9638. * contains parameters used to setup RX_CCE_SUPER_RULE_0
  9639. * dword11~20 - cce_super_rule_param[1]:
  9640. * contains parameters used to setup RX_CCE_SUPER_RULE_1
  9641. *
  9642. * Each cce_super_rule_param structure would appear as follows:
  9643. * |31 24|23 16|15 8|7 0|
  9644. * |-----------------+-----------------+-----------------+-----------------|
  9645. * |src_ipv6_addr[3] |src_ipv6_addr[2] |src_ipv6_addr[1] |src_ipv6_addr[0] |
  9646. * |/src_ipv4_addr[3]|/src_ipv4_addr[2]|/src_ipv4_addr[1]|/src_ipv4_addr[0]|
  9647. * |-----------------------------------------------------------------------|
  9648. * |src_ipv6_addr[7] |src_ipv6_addr[6] |src_ipv6_addr[5] |src_ipv6_addr[4] |
  9649. * |-----------------------------------------------------------------------|
  9650. * |src_ipv6_addr[11]|src_ipv6_addr[10]|src_ipv6_addr[9] |src_ipv6_addr[8] |
  9651. * |-----------------------------------------------------------------------|
  9652. * |src_ipv6_addr[15]|src_ipv6_addr[14]|src_ipv6_addr[13]|src_ipv6_addr[12]|
  9653. * |-----------------------------------------------------------------------|
  9654. * |dst_ipv6_addr[3] |dst_ipv6_addr[2] |dst_ipv6_addr[1] |dst_ipv6_addr[0] |
  9655. * |/dst_ipv4_addr[3]|/dst_ipv4_addr[2]|/dst_ipv4_addr[1]|/dst_ipv4_addr[0]|
  9656. * |-----------------------------------------------------------------------|
  9657. * |dst_ipv6_addr[7] |dst_ipv6_addr[6] |dst_ipv6_addr[5] |dst_ipv6_addr[4] |
  9658. * |-----------------------------------------------------------------------|
  9659. * |dst_ipv6_addr[11]|dst_ipv6_addr[10]|dst_ipv6_addr[9] |dst_ipv6_addr[8] |
  9660. * |-----------------------------------------------------------------------|
  9661. * |dst_ipv6_addr[15]|dst_ipv6_addr[14]|dst_ipv6_addr[13]|dst_ipv6_addr[12]|
  9662. * |-----------------------------------------------------------------------|
  9663. * | is_valid | l4_type | l3_type |
  9664. * |-----------------------------------------------------------------------|
  9665. * | l4_dst_port | l4_src_port |
  9666. * |-----------------------------------------------------------------------|
  9667. *
  9668. * The cce_super_rule_param[0] structure is interpreted as follows:
  9669. * dword1 - b'0:7 - src_ipv6_addr[0]: b'120:127 of source ipv6 address
  9670. * (or src_ipv4_addr[0]: b'24:31 of source ipv4 address,
  9671. * in case of ipv4)
  9672. * b'8:15 - src_ipv6_addr[1]: b'112:119 of source ipv6 address
  9673. * (or src_ipv4_addr[1]: b'16:23 of source ipv4 address,
  9674. * in case of ipv4)
  9675. * b'16:23 - src_ipv6_addr[2]: b'104:111 of source ipv6 address
  9676. * (or src_ipv4_addr[2]: b'8:15 of source ipv4 address,
  9677. * in case of ipv4)
  9678. * b'24:31 - src_ipv6_addr[3]: b'96:103 of source ipv6 address
  9679. * (or src_ipv4_addr[3]: b'0:7 of source ipv4 address,
  9680. * in case of ipv4)
  9681. * dword2 - b'0:7 - src_ipv6_addr[4]: b'88:95 of source ipv6 address
  9682. * b'8:15 - src_ipv6_addr[5]: b'80:87 of source ipv6 address
  9683. * b'16:23 - src_ipv6_addr[6]: b'72:79 of source ipv6 address
  9684. * b'24:31 - src_ipv6_addr[7]: b'64:71 of source ipv6 address
  9685. * dword3 - b'0:7 - src_ipv6_addr[8]: b'56:63 of source ipv6 address
  9686. * b'8:15 - src_ipv6_addr[9]: b'48:55 of source ipv6 address
  9687. * b'16:23 - src_ipv6_addr[10]: b'40:47 of source ipv6 address
  9688. * b'24:31 - src_ipv6_addr[11]: b'32:39 of source ipv6 address
  9689. * dword4 - b'0:7 - src_ipv6_addr[12]: b'24:31 of source ipv6 address
  9690. * b'8:15 - src_ipv6_addr[13]: b'16:23 of source ipv6 address
  9691. * b'16:23 - src_ipv6_addr[14]: b'8:15 of source ipv6 address
  9692. * b'24:31 - src_ipv6_addr[15]: b'0:7 of source ipv6 address
  9693. * dword5 - b'0:7 - dst_ipv6_addr[0]: b'120:127 of destination ipv6 address
  9694. * (or dst_ipv4_addr[0]: b'24:31 of destination
  9695. * ipv4 address, in case of ipv4)
  9696. * b'8:15 - dst_ipv6_addr[1]: b'112:119 of destination ipv6 address
  9697. * (or dst_ipv4_addr[1]: b'16:23 of destination
  9698. * ipv4 address, in case of ipv4)
  9699. * b'16:23 - dst_ipv6_addr[2]: b'104:111 of destination ipv6 address
  9700. * (or dst_ipv4_addr[2]: b'8:15 of destination
  9701. * ipv4 address, in case of ipv4)
  9702. * b'24:31 - dst_ipv6_addr[3]: b'96:103 of destination ipv6 address
  9703. * (or dst_ipv4_addr[3]: b'0:7 of destination
  9704. * ipv4 address, in case of ipv4)
  9705. * dword6 - b'0:7 - dst_ipv6_addr[4]: b'88:95 of destination ipv6 address
  9706. * b'8:15 - dst_ipv6_addr[5]: b'80:87 of destination ipv6 address
  9707. * b'16:23 - dst_ipv6_addr[6]: b'72:79 of destination ipv6 address
  9708. * b'24:31 - dst_ipv6_addr[7]: b'64:71 of destination ipv6 address
  9709. * dword7 - b'0:7 - dst_ipv6_addr[8]: b'56:63 of destination ipv6 address
  9710. * b'8:15 - dst_ipv6_addr[9]: b'48:55 of destination ipv6 address
  9711. * b'16:23 - dst_ipv6_addr[10]: b'40:47 of destination ipv6 address
  9712. * b'24:31 - dst_ipv6_addr[11]: b'32:39 of destination ipv6 address
  9713. * dword8 - b'0:7 - dst_ipv6_addr[12]: b'24:31 of destination ipv6 address
  9714. * b'8:15 - dst_ipv6_addr[13]: b'16:23 of destination ipv6 address
  9715. * b'16:23 - dst_ipv6_addr[14]: b'8:15 of destination ipv6 address
  9716. * b'24:31 - dst_ipv6_addr[15]: b'0:7 of destination ipv6 address
  9717. * dword9 - b'0:15 - l3_type: type of L3 protocol, indicating L3 protocol used
  9718. * 0x0008: ipv4
  9719. * 0xdd86: ipv6
  9720. * b'16:23 - l4_type: type of L4 protocol, indicating L4 protocol used
  9721. * 6: TCP
  9722. * 17: UDP
  9723. * b'24:31 - is_valid: indicate whether this parameter is valid
  9724. * 0: invalid
  9725. * 1: valid
  9726. * dword10 - b'0:15 - l4_src_port: TCP/UDP source port field
  9727. * b'16:31 - l4_dst_port: TCP/UDP destination port field
  9728. *
  9729. * The cce_super_rule_param[1] structure is similar.
  9730. */
  9731. #define HTT_RX_CCE_SUPER_RULE_SETUP_NUM 2
  9732. enum htt_rx_cce_super_rule_setup_operation {
  9733. HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST = 0,
  9734. HTT_RX_CCE_SUPER_RULE_INSTALL,
  9735. HTT_RX_CCE_SUPER_RULE_RELEASE,
  9736. /* All operation should be before this */
  9737. HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_OPERATION,
  9738. };
  9739. typedef struct {
  9740. union {
  9741. A_UINT8 src_ipv4_addr[4];
  9742. A_UINT8 src_ipv6_addr[16];
  9743. };
  9744. union {
  9745. A_UINT8 dst_ipv4_addr[4];
  9746. A_UINT8 dst_ipv6_addr[16];
  9747. };
  9748. A_UINT32 l3_type: 16,
  9749. l4_type: 8,
  9750. is_valid: 8;
  9751. A_UINT32 l4_src_port: 16,
  9752. l4_dst_port: 16;
  9753. } htt_rx_cce_super_rule_param_t;
  9754. PREPACK struct htt_rx_cce_super_rule_setup_t {
  9755. A_UINT32 msg_type: 8,
  9756. pdev_id: 8,
  9757. operation: 8,
  9758. reserved: 8;
  9759. htt_rx_cce_super_rule_param_t
  9760. cce_super_rule_param[HTT_RX_CCE_SUPER_RULE_SETUP_NUM];
  9761. } POSTPACK;
  9762. #define HTT_RX_CCE_SUPER_RULE_SETUP_SZ \
  9763. (sizeof(struct htt_rx_cce_super_rule_setup_t))
  9764. #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M 0x0000ff00
  9765. #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S 8
  9766. #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_GET(_var) \
  9767. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M) >> \
  9768. HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S)
  9769. #define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_SET(_var, _val) \
  9770. do { \
  9771. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID, _val); \
  9772. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S)); \
  9773. } while (0)
  9774. #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000
  9775. #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S 16
  9776. #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_GET(_var) \
  9777. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M) >> \
  9778. HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S)
  9779. #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_SET(_var, _val) \
  9780. do { \
  9781. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION, _val); \
  9782. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S)); \
  9783. } while (0)
  9784. #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M 0x0000ffff
  9785. #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S 0
  9786. #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_GET(_var) \
  9787. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M) >> \
  9788. HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S)
  9789. #define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_SET(_var, _val) \
  9790. do { \
  9791. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE, _val); \
  9792. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S)); \
  9793. } while (0)
  9794. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M 0x00ff0000
  9795. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S 16
  9796. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_GET(_var) \
  9797. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M) >> \
  9798. HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S)
  9799. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_SET(_var, _val) \
  9800. do { \
  9801. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE, _val); \
  9802. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S)); \
  9803. } while (0)
  9804. #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M 0xff000000
  9805. #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S 24
  9806. #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_GET(_var) \
  9807. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M) >> \
  9808. HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S)
  9809. #define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_SET(_var, _val) \
  9810. do { \
  9811. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID, _val); \
  9812. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S)); \
  9813. } while (0)
  9814. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M 0x0000ffff
  9815. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S 0
  9816. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_GET(_var) \
  9817. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M) >> \
  9818. HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)
  9819. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_SET(_var, _val) \
  9820. do { \
  9821. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT, _val); \
  9822. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)); \
  9823. } while (0)
  9824. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M 0xffff0000
  9825. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S 16
  9826. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_GET(_var) \
  9827. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M) >> \
  9828. HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S)
  9829. #define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_SET(_var, _val) \
  9830. do { \
  9831. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT, _val); \
  9832. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S)); \
  9833. } while (0)
  9834. #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_GET(_ptr, _array) \
  9835. do { \
  9836. A_MEMCPY(_array, _ptr, 4); \
  9837. } while (0)
  9838. #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_SET(_ptr, _array) \
  9839. do { \
  9840. A_MEMCPY(_ptr, _array, 4); \
  9841. } while (0)
  9842. #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_GET(_ptr, _array) \
  9843. do { \
  9844. A_MEMCPY(_array, _ptr, 16); \
  9845. } while (0)
  9846. #define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_SET(_ptr, _array) \
  9847. do { \
  9848. A_MEMCPY(_ptr, _array, 16); \
  9849. } while (0)
  9850. /*
  9851. * @brief host -> target HTT TX_LCE_SUPER_RULE_SETUP message
  9852. *
  9853. * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP
  9854. *
  9855. * @details
  9856. * Host sends TX_SUPER_RULE setup message to target, in order to request,
  9857. * install, or uninstall tx super rules to match certain kind of packets
  9858. * with specific parameters. Target sets up HW registers based on setup
  9859. * message and always confirms back to host (by sending a T2H
  9860. * TX_LCE_SUPER_RULE_SETUP_DONE message).
  9861. *
  9862. * The message would appear as follows:
  9863. * |31 24|23 16|15 8|7 0|
  9864. * |-----------------+-----------------+-----------------+-----------------|
  9865. * | reserved | operation | pdev_id | msg_type |
  9866. * |-----------------------------------------------------------------------|
  9867. * | tx_super_rule_param[0] |
  9868. * |-----------------------------------------------------------------------|
  9869. * | tx_super_rule_param[1] |
  9870. * |-----------------------------------------------------------------------|
  9871. * | tx_super_rule_param[2] |
  9872. * |-----------------------------------------------------------------------|
  9873. *
  9874. * The message is interpreted as follows:
  9875. * dword0 - b'0:7 - msg_type: This will be set to
  9876. * 0x26 (HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP)
  9877. * b'8:15 - pdev_id: Identify which pdev TX_SUPER_RULE is for
  9878. * b'16:23 - operation: Identify operation to be taken,
  9879. * 0: HTT_TX_LCE_SUPER_RULE_INSTALL
  9880. * 1: HTT_TX_LCE_SUPER_RULE_RELEASE
  9881. * b'24:31 - reserved
  9882. * dword1~10 - tx_super_rule_param[0]:
  9883. * contains parameters used to setup TX_SUPER_RULE_0
  9884. * dword11~20 - tx_super_rule_param[1]:
  9885. * contains parameters used to setup TX_SUPER_RULE_1
  9886. * dword21~30 - tx_super_rule_param[2]:
  9887. * contains parameters used to setup TX_SUPER_RULE_2
  9888. *
  9889. * Each tx_super_rule_param structure would appear as follows:
  9890. * |31 24|23 16|15 8|7 0|
  9891. * |-----------------+-----------------+-----------------+-----------------|
  9892. * |src_ipv6_addr[3] |src_ipv6_addr[2] |src_ipv6_addr[1] |src_ipv6_addr[0] |
  9893. * |/src_ipv4_addr[3]|/src_ipv4_addr[2]|/src_ipv4_addr[1]|/src_ipv4_addr[0]|
  9894. * |-----------------------------------------------------------------------|
  9895. * |src_ipv6_addr[7] |src_ipv6_addr[6] |src_ipv6_addr[5] |src_ipv6_addr[4] |
  9896. * |-----------------------------------------------------------------------|
  9897. * |src_ipv6_addr[11]|src_ipv6_addr[10]|src_ipv6_addr[9] |src_ipv6_addr[8] |
  9898. * |-----------------------------------------------------------------------|
  9899. * |src_ipv6_addr[15]|src_ipv6_addr[14]|src_ipv6_addr[13]|src_ipv6_addr[12]|
  9900. * |-----------------------------------------------------------------------|
  9901. * |dst_ipv6_addr[3] |dst_ipv6_addr[2] |dst_ipv6_addr[1] |dst_ipv6_addr[0] |
  9902. * |/dst_ipv4_addr[3]|/dst_ipv4_addr[2]|/dst_ipv4_addr[1]|/dst_ipv4_addr[0]|
  9903. * |-----------------------------------------------------------------------|
  9904. * |dst_ipv6_addr[7] |dst_ipv6_addr[6] |dst_ipv6_addr[5] |dst_ipv6_addr[4] |
  9905. * |-----------------------------------------------------------------------|
  9906. * |dst_ipv6_addr[11]|dst_ipv6_addr[10]|dst_ipv6_addr[9] |dst_ipv6_addr[8] |
  9907. * |-----------------------------------------------------------------------|
  9908. * |dst_ipv6_addr[15]|dst_ipv6_addr[14]|dst_ipv6_addr[13]|dst_ipv6_addr[12]|
  9909. * |-----------------------------------------------------------------------|
  9910. * | is_valid | l4_type | l3_type |
  9911. * |-----------------------------------------------------------------------|
  9912. * | l4_dst_port | l4_src_port |
  9913. * |-----------------------------------------------------------------------|
  9914. * Where l3_type is 802.3 EtherType, l4_type is IANA IP protocol type.
  9915. *
  9916. * The tx_super_rule_param[1] structure is similar.
  9917. * The tx_super_rule_param[2] structure is similar.
  9918. */
  9919. #define HTT_TX_LCE_SUPER_RULE_SETUP_NUM 3
  9920. enum htt_tx_lce_super_rule_setup_operation {
  9921. HTT_TX_LCE_SUPER_RULE_INSTALL = 0,
  9922. HTT_TX_LCE_SUPER_RULE_RELEASE,
  9923. /* All operation should be before this */
  9924. HTT_TX_LCE_SUPER_RULE_SETUP_INVALID_OPERATION,
  9925. };
  9926. typedef struct {
  9927. union {
  9928. A_UINT8 src_ipv4_addr[4];
  9929. A_UINT8 src_ipv6_addr[16];
  9930. };
  9931. union {
  9932. A_UINT8 dst_ipv4_addr[4];
  9933. A_UINT8 dst_ipv6_addr[16];
  9934. };
  9935. A_UINT32 l3_type: 16,
  9936. l4_type: 8,
  9937. is_valid: 8;
  9938. A_UINT32 l4_src_port: 16,
  9939. l4_dst_port: 16;
  9940. } htt_tx_lce_super_rule_param_t;
  9941. PREPACK struct htt_tx_lce_super_rule_setup_t {
  9942. A_UINT32 msg_type: 8,
  9943. pdev_id: 8,
  9944. operation: 8, /* htt_tx_lce_super_rule_setup_operation */
  9945. reserved: 8;
  9946. htt_tx_lce_super_rule_param_t
  9947. lce_super_rule_param[HTT_TX_LCE_SUPER_RULE_SETUP_NUM];
  9948. } POSTPACK;
  9949. #define HTT_TX_LCE_SUPER_RULE_SETUP_SZ (sizeof(struct htt_tx_lce_super_rule_setup_t))
  9950. #define HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_M 0x0000ff00
  9951. #define HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_S 8
  9952. #define HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_GET(_var) \
  9953. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_M) >> \
  9954. HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_S)
  9955. #define HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_SET(_var, _val) \
  9956. do { \
  9957. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID, _val); \
  9958. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_PDEV_ID_S)); \
  9959. } while (0)
  9960. #define HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000
  9961. #define HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_S 16
  9962. #define HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_GET(_var) \
  9963. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_M) >> \
  9964. HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_S)
  9965. #define HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_SET(_var, _val) \
  9966. do { \
  9967. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION, _val); \
  9968. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_OPERATION_S)); \
  9969. } while (0)
  9970. #define HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_M 0x0000ffff
  9971. #define HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_S 0
  9972. #define HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_GET(_var) \
  9973. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_M) >> \
  9974. HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_S)
  9975. #define HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_SET(_var, _val) \
  9976. do { \
  9977. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE, _val); \
  9978. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_L3_TYPE_S)); \
  9979. } while (0)
  9980. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_M 0x00ff0000
  9981. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_S 16
  9982. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_GET(_var) \
  9983. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_M) >> \
  9984. HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_S)
  9985. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_SET(_var, _val) \
  9986. do { \
  9987. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE, _val); \
  9988. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_L4_TYPE_S)); \
  9989. } while (0)
  9990. #define HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_M 0xff000000
  9991. #define HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_S 24
  9992. #define HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_GET(_var) \
  9993. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_M) >> \
  9994. HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_S)
  9995. #define HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_SET(_var, _val) \
  9996. do { \
  9997. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID, _val); \
  9998. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_IS_VALID_S)); \
  9999. } while (0)
  10000. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_M 0x0000ffff
  10001. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_S 0
  10002. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_GET(_var) \
  10003. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_M) >> \
  10004. HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)
  10005. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_SET(_var, _val) \
  10006. do { \
  10007. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT, _val); \
  10008. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)); \
  10009. } while (0)
  10010. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_M 0xffff0000
  10011. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_S 16
  10012. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_GET(_var) \
  10013. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_M) >> \
  10014. HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_S)
  10015. #define HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_SET(_var, _val) \
  10016. do { \
  10017. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT, _val); \
  10018. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_L4_DST_PORT_S)); \
  10019. } while (0)
  10020. #define HTT_TX_LCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_GET(_ptr, _array) \
  10021. do { \
  10022. A_MEMCPY(_array, _ptr, 4); \
  10023. } while (0)
  10024. #define HTT_TX_LCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_SET(_ptr, _array) \
  10025. do { \
  10026. A_MEMCPY(_ptr, _array, 4); \
  10027. } while (0)
  10028. #define HTT_TX_LCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_GET(_ptr, _array) \
  10029. do { \
  10030. A_MEMCPY(_array, _ptr, 16); \
  10031. } while (0)
  10032. #define HTT_TX_LCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_SET(_ptr, _array) \
  10033. do { \
  10034. A_MEMCPY(_ptr, _array, 16); \
  10035. } while (0)
  10036. /**
  10037. * htt_h2t_primary_link_peer_status_type -
  10038. * Unique number for each status or reasons
  10039. * The status reasons can go up to 255 max
  10040. */
  10041. enum htt_h2t_primary_link_peer_status_type {
  10042. /* Host Primary Link Peer migration Success */
  10043. HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_OK = 0,
  10044. /* keep this last */
  10045. /* Host Primary Link Peer migration Fail */
  10046. HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_FAIL = 254,
  10047. HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_NUM_STATUS = 255
  10048. };
  10049. /**
  10050. * @brief host -> Primary peer migration completion message from host
  10051. *
  10052. * MSG_TYPE => HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP
  10053. *
  10054. * @details
  10055. * HTT_H2T_MSG_TYPE_PRIMARY_PEER_MIGRATE_RESP message is sent by host to
  10056. * target Confirming that primary link peer migration has completed,
  10057. * in response to a HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND
  10058. * message from the target.
  10059. *
  10060. * The message would appear as follows:
  10061. *
  10062. * |31 25|24|23 16|15 12|11 8|7 0|
  10063. * |----------------------------+----------+---------+--------------|
  10064. * | vdev ID | pdev ID | chip ID | msg type |
  10065. * |----------------------------+----------+---------+--------------|
  10066. * | ML peer ID | SW peer ID |
  10067. * |------------+--+------------+--------------------+--------------|
  10068. * | reserved |SV| src_info | status |
  10069. * |------------+--+---------------------------------+--------------|
  10070. * Where:
  10071. * SV = src_info_valid flag
  10072. *
  10073. * The message is interpreted as follows:
  10074. * dword0 - b'0:7 - msg_type: This will be set to 0x24
  10075. * (HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP)
  10076. * b'8:11 - chip_id: Indicate which chip has been chosen as primary
  10077. * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen
  10078. * as primary
  10079. * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen
  10080. * as primary
  10081. *
  10082. * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer
  10083. * chosen as primary
  10084. * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the
  10085. * primary peer belongs.
  10086. * dword2 - b'0:7 - status: Indicates the status of Rx/TCL migration
  10087. * b'8:23 - src_info: Indicates New Virtual port number through
  10088. * which Rx Pipe connects to the correct PPE.
  10089. * b'24 - src_info_valid: Indicates src_info is valid.
  10090. */
  10091. typedef struct {
  10092. A_UINT32 msg_type: 8, /* bits 7:0 */
  10093. chip_id: 4, /* bits 11:8 */
  10094. pdev_id: 4, /* bits 15:12 */
  10095. vdev_id: 16; /* bits 31:16 */
  10096. A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */
  10097. ml_peer_id: 16; /* bits 31:16 */
  10098. A_UINT32 status: 8, /* bits 7:0 */
  10099. src_info: 16, /* bits 23:8 */
  10100. src_info_valid: 1, /* bit 24 */
  10101. reserved: 7; /* bits 31:25 */
  10102. } htt_h2t_primary_link_peer_migrate_resp_t;
  10103. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00
  10104. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8
  10105. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \
  10106. (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \
  10107. HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S)
  10108. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \
  10109. do { \
  10110. HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \
  10111. ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\
  10112. } while (0)
  10113. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000
  10114. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12
  10115. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \
  10116. (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \
  10117. HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S)
  10118. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \
  10119. do { \
  10120. HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \
  10121. ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\
  10122. } while (0)
  10123. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000
  10124. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16
  10125. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \
  10126. (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \
  10127. HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S)
  10128. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \
  10129. do { \
  10130. HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \
  10131. ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\
  10132. } while (0)
  10133. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF
  10134. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0
  10135. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \
  10136. (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \
  10137. HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S)
  10138. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \
  10139. do { \
  10140. HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \
  10141. ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\
  10142. } while (0)
  10143. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000
  10144. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16
  10145. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \
  10146. (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \
  10147. HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S)
  10148. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \
  10149. do { \
  10150. HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \
  10151. ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\
  10152. } while (0)
  10153. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M 0x000000FF
  10154. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S 0
  10155. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_GET(_var) \
  10156. (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M) >> \
  10157. HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S)
  10158. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_SET(_var, _val) \
  10159. do { \
  10160. HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS, _val); \
  10161. ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S));\
  10162. } while (0)
  10163. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M 0x00FFFF00
  10164. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S 8
  10165. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_GET(_var) \
  10166. (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M) >> \
  10167. HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S)
  10168. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_SET(_var, _val) \
  10169. do { \
  10170. HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO, _val); \
  10171. ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S));\
  10172. } while (0)
  10173. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M 0x01000000
  10174. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S 24
  10175. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_GET(_var) \
  10176. (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M) >> \
  10177. HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S)
  10178. #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_SET(_var, _val) \
  10179. do { \
  10180. HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID, _val); \
  10181. ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S));\
  10182. } while (0)
  10183. /**
  10184. * @brief host -> tgt msg to configure params for PPDU tx latency stats report
  10185. *
  10186. * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG
  10187. *
  10188. * @details
  10189. * HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG message is sent by the host to
  10190. * configure the parameters needed for FW to report PPDU tx latency stats
  10191. * for latency prediction in user space.
  10192. *
  10193. * The message would appear as follows:
  10194. * |31 28|27 12|11|10 8|7 0|
  10195. * |-----------+-------------------+--+-------+--------------|
  10196. * |granularity| periodic interval | E|vdev ID| msg type |
  10197. * |-----------+-------------------+--+-------+--------------|
  10198. * Where: E = enable
  10199. *
  10200. * The message is interpreted as follows:
  10201. * dword0 - b'0:7 - msg_type: This will be set to 0x25
  10202. * (HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG)
  10203. * b'8:10 - vdev_id: Indicate which vdev is configuration is for
  10204. * b'11 - enable: Indicate this message is to enable/disable
  10205. * PPDU latency report from FW
  10206. * b'12:27 - periodic_interval: Indicate the report interval in MS
  10207. * b'28:31 - granularity: Indicate the granularity of the latency
  10208. * stats report, in ms
  10209. */
  10210. /* HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG */
  10211. PREPACK struct htt_h2t_tx_latency_stats_cfg {
  10212. A_UINT32 msg_type :8,
  10213. vdev_id :3,
  10214. enable :1,
  10215. periodic_interval :16,
  10216. granularity :4;
  10217. } POSTPACK;
  10218. #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M 0x00000700
  10219. #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S 8
  10220. #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_GET(_var) \
  10221. (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M) >> \
  10222. HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)
  10223. #define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_SET(_var, _val) \
  10224. do { \
  10225. HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID, _val); \
  10226. ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)); \
  10227. } while (0)
  10228. #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M 0x00000800
  10229. #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S 11
  10230. #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_GET(_var) \
  10231. (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M) >> \
  10232. HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)
  10233. #define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_SET(_var, _val) \
  10234. do { \
  10235. HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE, _val); \
  10236. ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)); \
  10237. } while (0)
  10238. #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M 0x0FFFF000
  10239. #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S 12
  10240. #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_GET(_var) \
  10241. (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M) >> \
  10242. HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)
  10243. #define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_SET(_var, _val) \
  10244. do { \
  10245. HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL, _val); \
  10246. ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)); \
  10247. } while (0)
  10248. #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M 0xF0000000
  10249. #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S 28
  10250. #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_GET(_var) \
  10251. (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M) >> \
  10252. HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)
  10253. #define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_SET(_var, _val) \
  10254. do { \
  10255. HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY, _val); \
  10256. ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)); \
  10257. } while (0)
  10258. /**
  10259. * @brief host -> tgt msg to reconfigure params for a MSDU queue
  10260. *
  10261. * MSG_TYPE => HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ
  10262. *
  10263. * @details
  10264. * HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ message is sent by the host to
  10265. * update the configuration of the identified MSDU.
  10266. * This message supports the following MSDU queue reconfigurations:
  10267. * 1. Deactivating or reactivating the MSDU queue.
  10268. * 2. Moving the MSDU queue from its current service class to a
  10269. * different service class.
  10270. * The new service class needs to be within the same TID as the
  10271. * current service class.
  10272. * This msg overlaps with the HTT_H2T_SAWF_DEF_QUEUES_[MAP,UNMAP]_REQ
  10273. * messages, but those only apply to the default MSDU queues within
  10274. * a peer-TID, while this message applies only to a single MSDU queue,
  10275. * and that MSDU queue can be a user-defined queue or a default queue.
  10276. * Also, the concurrent combination of reconfigurations 1+2 is supported.
  10277. *
  10278. * The message format is as follows:
  10279. * |31 24|23 9|8|7 0|
  10280. * |--------------------------------------------------------------|
  10281. * | tgt_opaque_msduq_id | msg type |
  10282. * |--------------------------------------------------------------|
  10283. * | request_cookie | reserved |D| svc_class_id |
  10284. * |--------------------------------------------------------------|
  10285. * Where: D = deactivate flag
  10286. *
  10287. * The message is interpreted as follows:
  10288. * dword0 - b'0:7 - msg_type: This will be set to 0x27
  10289. * (HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ)
  10290. * b'8:31 - tgt_opaque_msduq_id: tx flow number that uniquely
  10291. * identifies the MSDU queue
  10292. * dword1 - b'0:7 - svc_class_id: ID of the SAWF service class to which
  10293. * the MSDU queue should be associated.
  10294. * On reactivate requests, svc_class_id may be set to the
  10295. * same service class ID as before the deactivate or it may
  10296. * be set to a different service class ID.
  10297. * b'8:8 - deactivate: Whether the MSDU queue should be deactivated
  10298. * or reactivated (refer to HTT_MSDUQ_DEACTIVATE_E)
  10299. * b'9:23 - reserved
  10300. * b'31:24 - request_cookie: Identifier for FW to use in the
  10301. * completion indication (T2H SDWF_MSDU_CFG_IND) to call
  10302. * out this specific request. The host shall avoid using
  10303. * a value of 0xFF (COOKIE_INVALID) here, so that a
  10304. * 0xFF / COOKIE_INVALID value can be used in any T2H
  10305. * SDWF_MSDUQ_CFG_IND messages that the target sends
  10306. * autonomously rather than in response to a H2T
  10307. * SDWF_MSDUQ_RECFG_REQ.
  10308. */
  10309. /* HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ */
  10310. typedef enum {
  10311. HTT_MSDUQ_REACTIVATE = 0,
  10312. HTT_MSDUQ_DEACTIVATE = 1,
  10313. } HTT_MSDUQ_DEACTIVATE_E;
  10314. PREPACK struct htt_h2t_sdwf_msduq_recfg_req {
  10315. A_UINT32 msg_type :8, /* bits 7:0 */
  10316. tgt_opaque_msduq_id :24; /* bits 31:8 */
  10317. A_UINT32 svc_class_id :8, /* bits 7:0 */
  10318. deactivate :1, /* bits 8:8 */
  10319. reserved :15, /* bits 23:9 */
  10320. request_cookie :8; /* bits 31:24 */
  10321. } POSTPACK;
  10322. #define HTT_MSDUQ_CFG_REG_COOKIE_INVALID 0xFF
  10323. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_M 0xFFFFFF00
  10324. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_S 8
  10325. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_GET(_var) \
  10326. (((_var) & HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_M) >> \
  10327. HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_S)
  10328. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_SET(_var, _val) \
  10329. do { \
  10330. HTT_CHECK_SET_VAL(HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID, _val); \
  10331. ((_var) |= ((_val) << HTT_H2T_SDWF_MSDUQ_RECFG_REQ_TGT_OPAQUE_MSDUQ_ID_S)); \
  10332. } while (0)
  10333. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_M 0x000000FF
  10334. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_S 0
  10335. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_GET(_var) \
  10336. (((_var) & HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_M) >> \
  10337. HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_S)
  10338. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_SET(_var, _val) \
  10339. do { \
  10340. HTT_CHECK_SET_VAL(HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID, _val); \
  10341. ((_var) |= ((_val) << HTT_H2T_SDWF_MSDUQ_RECFG_REQ_SVC_CLASS_ID_S)); \
  10342. } while (0)
  10343. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_M 0x00000100
  10344. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_S 8
  10345. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_GET(_var) \
  10346. (((_var) & HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_M) >> \
  10347. HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_S)
  10348. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_SET(_var, _val) \
  10349. do { \
  10350. HTT_CHECK_SET_VAL(HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE, _val); \
  10351. ((_var) |= ((_val) << HTT_H2T_SDWF_MSDUQ_RECFG_REQ_DEACTIVATE_S)); \
  10352. } while (0)
  10353. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_M 0xFF000000
  10354. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_S 24
  10355. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_GET(_var) \
  10356. (((_var) & HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_M) >> \
  10357. HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_S)
  10358. #define HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_SET(_var, _val) \
  10359. do { \
  10360. HTT_CHECK_SET_VAL(HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE, _val); \
  10361. ((_var) |= ((_val) << HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_S)); \
  10362. } while (0)
  10363. /*=== target -> host messages ===============================================*/
  10364. enum htt_t2h_msg_type {
  10365. HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0,
  10366. HTT_T2H_MSG_TYPE_RX_IND = 0x1,
  10367. HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2,
  10368. HTT_T2H_MSG_TYPE_PEER_MAP = 0x3,
  10369. HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
  10370. HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5,
  10371. HTT_T2H_MSG_TYPE_RX_DELBA = 0x6,
  10372. HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
  10373. HTT_T2H_MSG_TYPE_PKTLOG = 0x8,
  10374. HTT_T2H_MSG_TYPE_STATS_CONF = 0x9,
  10375. HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
  10376. HTT_T2H_MSG_TYPE_SEC_IND = 0xb,
  10377. DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* no longer used */
  10378. HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
  10379. HTT_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
  10380. /* only used for HL, add HTT MSG for HTT CREDIT update */
  10381. HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
  10382. HTT_T2H_MSG_TYPE_RX_PN_IND = 0x10,
  10383. HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
  10384. HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12,
  10385. /* 0x13 is reserved for RX_RING_LOW_IND (RX Full reordering related) */
  10386. HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14,
  10387. HTT_T2H_MSG_TYPE_CHAN_CHANGE = 0x15,
  10388. HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16,
  10389. HTT_T2H_MSG_TYPE_RATE_REPORT = 0x17,
  10390. HTT_T2H_MSG_TYPE_FLOW_POOL_MAP = 0x18,
  10391. HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP = 0x19,
  10392. HTT_T2H_MSG_TYPE_SRING_SETUP_DONE = 0x1a,
  10393. HTT_T2H_MSG_TYPE_MAP_FLOW_INFO = 0x1b,
  10394. HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
  10395. HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
  10396. HTT_T2H_MSG_TYPE_PEER_MAP_V2 = 0x1e,
  10397. HTT_T2H_MSG_TYPE_PEER_UNMAP_V2 = 0x1f,
  10398. HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND = 0x20,
  10399. HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE = 0x21,
  10400. HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND = 0x22,
  10401. HTT_T2H_MSG_TYPE_PEER_STATS_IND = 0x23,
  10402. HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
  10403. /* TX_OFFLOAD_DELIVER_IND:
  10404. * Forward the target's locally-generated packets to the host,
  10405. * to provide to the monitor mode interface.
  10406. */
  10407. HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND = 0x25,
  10408. HTT_T2H_MSG_TYPE_CHAN_CALDATA = 0x26,
  10409. HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND = 0x27,
  10410. HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28,
  10411. HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP = 0x29,
  10412. HTT_T2H_MSG_TYPE_MLO_RX_PEER_UNMAP = 0x2a,
  10413. HTT_T2H_MSG_TYPE_PEER_MAP_V3 = 0x2b,
  10414. HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND = 0x2c,
  10415. HTT_T2H_MSG_TYPE_SAWF_DEF_QUEUES_MAP_REPORT_CONF = 0x2d,
  10416. HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF = 0x2d, /* alias */
  10417. HTT_T2H_MSG_TYPE_SAWF_MSDUQ_INFO_IND = 0x2e,
  10418. HTT_T2H_SAWF_MSDUQ_INFO_IND = 0x2e, /* alias */
  10419. HTT_T2H_MSG_TYPE_STREAMING_STATS_IND = 0x2f,
  10420. HTT_T2H_PPDU_ID_FMT_IND = 0x30,
  10421. HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN = 0x31,
  10422. HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32,
  10423. HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33,
  10424. HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, /* DEPRECATED */
  10425. HTT_T2H_MSG_TYPE_RX_DATA_IND = 0x35,
  10426. HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36,
  10427. HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37,
  10428. HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38,
  10429. HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT = 0x39,
  10430. HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND = 0x3a,
  10431. HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE = 0x3b,
  10432. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND = 0x3c,
  10433. HTT_T2H_MSG_TYPE_TEST,
  10434. /* keep this last */
  10435. HTT_T2H_NUM_MSGS
  10436. };
  10437. /*
  10438. * HTT target to host message type -
  10439. * stored in bits 7:0 of the first word of the message
  10440. */
  10441. #define HTT_T2H_MSG_TYPE_M 0xff
  10442. #define HTT_T2H_MSG_TYPE_S 0
  10443. #define HTT_T2H_MSG_TYPE_SET(word, msg_type) \
  10444. do { \
  10445. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE, msg_type); \
  10446. (word) |= ((msg_type) << HTT_T2H_MSG_TYPE_S); \
  10447. } while (0)
  10448. #define HTT_T2H_MSG_TYPE_GET(word) \
  10449. (((word) & HTT_T2H_MSG_TYPE_M) >> HTT_T2H_MSG_TYPE_S)
  10450. /**
  10451. * @brief target -> host version number confirmation message definition
  10452. *
  10453. * MSG_TYPE => HTT_T2H_MSG_TYPE_VERSION_CONF
  10454. *
  10455. * |31 24|23 16|15 8|7 0|
  10456. * |----------------+----------------+----------------+----------------|
  10457. * | reserved | major number | minor number | msg type |
  10458. * |-------------------------------------------------------------------|
  10459. * : option request TLV (optional) |
  10460. * :...................................................................:
  10461. *
  10462. * The VER_CONF message may consist of a single 4-byte word, or may be
  10463. * extended with TLVs that specify HTT options selected by the target.
  10464. * The following option TLVs may be appended to the VER_CONF message:
  10465. * - LL_BUS_ADDR_SIZE
  10466. * - HL_SUPPRESS_TX_COMPL_IND
  10467. * - MAX_TX_QUEUE_GROUPS
  10468. * These TLVs may appear in an arbitrary order. Any number of these TLVs
  10469. * may be appended to the VER_CONF message (but only one TLV of each type).
  10470. *
  10471. * Header fields:
  10472. * - MSG_TYPE
  10473. * Bits 7:0
  10474. * Purpose: identifies this as a version number confirmation message
  10475. * Value: 0x0 (HTT_T2H_MSG_TYPE_VERSION_CONF)
  10476. * - VER_MINOR
  10477. * Bits 15:8
  10478. * Purpose: Specify the minor number of the HTT message library version
  10479. * in use by the target firmware.
  10480. * The minor number specifies the specific revision within a range
  10481. * of fundamentally compatible HTT message definition revisions.
  10482. * Compatible revisions involve adding new messages or perhaps
  10483. * adding new fields to existing messages, in a backwards-compatible
  10484. * manner.
  10485. * Incompatible revisions involve changing the message type values,
  10486. * or redefining existing messages.
  10487. * Value: minor number
  10488. * - VER_MAJOR
  10489. * Bits 15:8
  10490. * Purpose: Specify the major number of the HTT message library version
  10491. * in use by the target firmware.
  10492. * The major number specifies the family of minor revisions that are
  10493. * fundamentally compatible with each other, but not with prior or
  10494. * later families.
  10495. * Value: major number
  10496. */
  10497. #define HTT_VER_CONF_MINOR_M 0x0000ff00
  10498. #define HTT_VER_CONF_MINOR_S 8
  10499. #define HTT_VER_CONF_MAJOR_M 0x00ff0000
  10500. #define HTT_VER_CONF_MAJOR_S 16
  10501. #define HTT_VER_CONF_MINOR_SET(word, value) \
  10502. do { \
  10503. HTT_CHECK_SET_VAL(HTT_VER_CONF_MINOR, value); \
  10504. (word) |= (value) << HTT_VER_CONF_MINOR_S; \
  10505. } while (0)
  10506. #define HTT_VER_CONF_MINOR_GET(word) \
  10507. (((word) & HTT_VER_CONF_MINOR_M) >> HTT_VER_CONF_MINOR_S)
  10508. #define HTT_VER_CONF_MAJOR_SET(word, value) \
  10509. do { \
  10510. HTT_CHECK_SET_VAL(HTT_VER_CONF_MAJOR, value); \
  10511. (word) |= (value) << HTT_VER_CONF_MAJOR_S; \
  10512. } while (0)
  10513. #define HTT_VER_CONF_MAJOR_GET(word) \
  10514. (((word) & HTT_VER_CONF_MAJOR_M) >> HTT_VER_CONF_MAJOR_S)
  10515. #define HTT_VER_CONF_BYTES 4
  10516. /**
  10517. * @brief - target -> host HTT Rx In order indication message
  10518. *
  10519. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND
  10520. *
  10521. * @details
  10522. *
  10523. * |31 24|23 |15|14|13|12|11|10|9|8|7|6|5|4 0|
  10524. * |----------------+-------------------+---------------------+---------------|
  10525. * | peer ID | P| F| O| ext TID | msg type |
  10526. * |--------------------------------------------------------------------------|
  10527. * | MSDU count | Reserved | vdev id |
  10528. * |--------------------------------------------------------------------------|
  10529. * | MSDU 0 bus address (bits 31:0) |
  10530. #if HTT_PADDR64
  10531. * | MSDU 0 bus address (bits 63:32) |
  10532. #endif
  10533. * |--------------------------------------------------------------------------|
  10534. * | MSDU info | MSDU 0 FW Desc | MSDU 0 Length |
  10535. * |--------------------------------------------------------------------------|
  10536. * | MSDU 1 bus address (bits 31:0) |
  10537. #if HTT_PADDR64
  10538. * | MSDU 1 bus address (bits 63:32) |
  10539. #endif
  10540. * |--------------------------------------------------------------------------|
  10541. * | MSDU info | MSDU 1 FW Desc | MSDU 1 Length |
  10542. * |--------------------------------------------------------------------------|
  10543. */
  10544. /** @brief - MSDU info byte for TCP_CHECKSUM_OFFLOAD use
  10545. *
  10546. * @details
  10547. * bits
  10548. * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
  10549. * |-----+----+-------+--------+--------+---------+---------+-----------|
  10550. * | reserved | is IP | is UDP | is TCP | is IPv6 |IP chksum| TCP/UDP |
  10551. * | | frag | | | | fail |chksum fail|
  10552. * |-----+----+-------+--------+--------+---------+---------+-----------|
  10553. * (see fw_rx_msdu_info def in wal_rx_desc.h)
  10554. */
  10555. struct htt_rx_in_ord_paddr_ind_hdr_t
  10556. {
  10557. A_UINT32 /* word 0 */
  10558. msg_type: 8,
  10559. ext_tid: 5,
  10560. offload: 1,
  10561. frag: 1,
  10562. pktlog: 1, /* tell host whether to store MSDUs referenced in this message in pktlog */
  10563. peer_id: 16;
  10564. A_UINT32 /* word 1 */
  10565. vap_id: 8,
  10566. /* NOTE:
  10567. * This reserved_1 field is not truly reserved - certain targets use
  10568. * this field internally to store debug information, and do not zero
  10569. * out the contents of the field before uploading the message to the
  10570. * host. Thus, any host-target communication supported by this field
  10571. * is limited to using values that are never used by the debug
  10572. * information stored by certain targets in the reserved_1 field.
  10573. * In particular, the targets in question don't use the value 0x3
  10574. * within bits 7:6 of this field (i.e. bits 15:14 of the A_UINT32),
  10575. * so this previously-unused value within these bits is available to
  10576. * use as the host / target PKT_CAPTURE_MODE flag.
  10577. */
  10578. reserved_1: 8, /* reserved_1a: 6, pkt_capture_mode: 2, */
  10579. /* if pkt_capture_mode == 0x3, host should
  10580. * send rx frames to monitor mode interface
  10581. */
  10582. msdu_cnt: 16;
  10583. };
  10584. struct htt_rx_in_ord_paddr_ind_msdu32_t
  10585. {
  10586. A_UINT32 dma_addr;
  10587. A_UINT32
  10588. length: 16,
  10589. fw_desc: 8,
  10590. msdu_info:8;
  10591. };
  10592. struct htt_rx_in_ord_paddr_ind_msdu64_t
  10593. {
  10594. A_UINT32 dma_addr_lo;
  10595. A_UINT32 dma_addr_hi;
  10596. A_UINT32
  10597. length: 16,
  10598. fw_desc: 8,
  10599. msdu_info:8;
  10600. };
  10601. #if HTT_PADDR64
  10602. #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu64_t
  10603. #else
  10604. #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu32_t
  10605. #endif
  10606. #define HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES (sizeof(struct htt_rx_in_ord_paddr_ind_hdr_t))
  10607. #define HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS (HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES >> 2)
  10608. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTE_OFFSET HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES
  10609. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORD_OFFSET HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS
  10610. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 (sizeof(struct htt_rx_in_ord_paddr_ind_msdu64_t))
  10611. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_64 (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 >> 2)
  10612. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 (sizeof(struct htt_rx_in_ord_paddr_ind_msdu32_t))
  10613. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_32 (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 >> 2)
  10614. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES (sizeof(struct htt_rx_in_ord_paddr_ind_msdu_t))
  10615. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES >> 2)
  10616. #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M 0x00001f00
  10617. #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S 8
  10618. #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M 0x00002000
  10619. #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S 13
  10620. #define HTT_RX_IN_ORD_PADDR_IND_FRAG_M 0x00004000
  10621. #define HTT_RX_IN_ORD_PADDR_IND_FRAG_S 14
  10622. #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_M 0x00008000
  10623. #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S 15
  10624. #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M 0xffff0000
  10625. #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S 16
  10626. #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M 0x000000ff
  10627. #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S 0
  10628. #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_M 0x0000c000
  10629. #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S 14
  10630. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M 0xffff0000
  10631. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S 16
  10632. /* for systems using 64-bit format for bus addresses */
  10633. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M 0xffffffff
  10634. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S 0
  10635. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M 0xffffffff
  10636. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S 0
  10637. /* for systems using 32-bit format for bus addresses */
  10638. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_M 0xffffffff
  10639. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_S 0
  10640. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M 0x0000ffff
  10641. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S 0
  10642. #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M 0x00ff0000
  10643. #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S 16
  10644. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M 0xff000000
  10645. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S 24
  10646. #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_SET(word, value) \
  10647. do { \
  10648. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_EXT_TID, value); \
  10649. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S; \
  10650. } while (0)
  10651. #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_GET(word) \
  10652. (((word) & HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M) >> HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S)
  10653. #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_SET(word, value) \
  10654. do { \
  10655. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PEER_ID, value); \
  10656. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S; \
  10657. } while (0)
  10658. #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_GET(word) \
  10659. (((word) & HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S)
  10660. #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_SET(word, value) \
  10661. do { \
  10662. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_VAP_ID, value); \
  10663. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S; \
  10664. } while (0)
  10665. #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_GET(word) \
  10666. (((word) & HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S)
  10667. /*
  10668. * If the PKT_CAPTURE_MODE flags value is MONITOR (0x3), the host should
  10669. * deliver the rx frames to the monitor mode interface.
  10670. * The HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR_SET macro
  10671. * sets the PKT_CAPTURE_MODE flags value to MONITOR, and the
  10672. * HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET macro
  10673. * checks whether the PKT_CAPTURE_MODE flags value is MONITOR.
  10674. */
  10675. #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR 0x3
  10676. #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR_SET(word) \
  10677. do { \
  10678. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE, HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR); \
  10679. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S; \
  10680. } while (0)
  10681. #define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET(word) \
  10682. ((((word) & HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_M) >> HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S) == \
  10683. HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR)
  10684. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_SET(word, value) \
  10685. do { \
  10686. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT, value); \
  10687. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S; \
  10688. } while (0)
  10689. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_GET(word) \
  10690. (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S)
  10691. /* for systems using 64-bit format for bus addresses */
  10692. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_SET(word, value) \
  10693. do { \
  10694. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_HI, value); \
  10695. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S; \
  10696. } while (0)
  10697. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_GET(word) \
  10698. (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S)
  10699. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_SET(word, value) \
  10700. do { \
  10701. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_LO, value); \
  10702. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S; \
  10703. } while (0)
  10704. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_GET(word) \
  10705. (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S)
  10706. /* for systems using 32-bit format for bus addresses */
  10707. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_SET(word, value) \
  10708. do { \
  10709. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR, value); \
  10710. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_S; \
  10711. } while (0)
  10712. #define HTT_RX_IN_ORD_PADDR_IND_PADDR_GET(word) \
  10713. (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_S)
  10714. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_SET(word, value) \
  10715. do { \
  10716. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN, value); \
  10717. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S; \
  10718. } while (0)
  10719. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_GET(word) \
  10720. (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S)
  10721. #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_SET(word, value) \
  10722. do { \
  10723. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_FW_DESC, value); \
  10724. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S; \
  10725. } while (0)
  10726. #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_GET(word) \
  10727. (((word) & HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M) >> HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S)
  10728. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_SET(word, value) \
  10729. do { \
  10730. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO, value); \
  10731. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S; \
  10732. } while (0)
  10733. #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_GET(word) \
  10734. (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S)
  10735. #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_SET(word, value) \
  10736. do { \
  10737. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_OFFLOAD, value); \
  10738. (word) |= (value) << HTT_RX_IN_ORD_IND_OFFLOAD_S; \
  10739. } while (0)
  10740. #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_GET(word) \
  10741. (((word) & HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M) >> HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S)
  10742. #define HTT_RX_IN_ORD_PADDR_IND_FRAG_SET(word, value) \
  10743. do { \
  10744. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_FRAG, value); \
  10745. (word) |= (value) << HTT_RX_IN_ORD_IND_FRAG_S; \
  10746. } while (0)
  10747. #define HTT_RX_IN_ORD_PADDR_IND_FRAG_GET(word) \
  10748. (((word) & HTT_RX_IN_ORD_PADDR_IND_FRAG_M) >> HTT_RX_IN_ORD_PADDR_IND_FRAG_S)
  10749. #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_SET(word, value) \
  10750. do { \
  10751. HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKTLOG, value); \
  10752. (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S; \
  10753. } while (0)
  10754. #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_GET(word) \
  10755. (((word) & HTT_RX_IN_ORD_PADDR_IND_PKTLOG_M) >> HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S)
  10756. /* definitions used within target -> host rx indication message */
  10757. PREPACK struct htt_rx_ind_hdr_prefix_t
  10758. {
  10759. A_UINT32 /* word 0 */
  10760. msg_type: 8,
  10761. ext_tid: 5,
  10762. release_valid: 1,
  10763. flush_valid: 1,
  10764. reserved0: 1,
  10765. peer_id: 16;
  10766. A_UINT32 /* word 1 */
  10767. flush_start_seq_num: 6,
  10768. flush_end_seq_num: 6,
  10769. release_start_seq_num: 6,
  10770. release_end_seq_num: 6,
  10771. num_mpdu_ranges: 8;
  10772. } POSTPACK;
  10773. #define HTT_RX_IND_HDR_PREFIX_BYTES (sizeof(struct htt_rx_ind_hdr_prefix_t))
  10774. #define HTT_RX_IND_HDR_PREFIX_SIZE32 (HTT_RX_IND_HDR_PREFIX_BYTES >> 2)
  10775. #define HTT_TGT_RSSI_INVALID 0x80
  10776. PREPACK struct htt_rx_ppdu_desc_t
  10777. {
  10778. #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI_CMB 0
  10779. #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_SUBMICROSEC 0
  10780. #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR_CODE 0
  10781. #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR 0
  10782. #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE 0
  10783. #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE_SEL 0
  10784. #define HTT_RX_IND_PPDU_OFFSET_WORD_END_VALID 0
  10785. #define HTT_RX_IND_PPDU_OFFSET_WORD_START_VALID 0
  10786. A_UINT32 /* word 0 */
  10787. rssi_cmb: 8,
  10788. timestamp_submicrosec: 8,
  10789. phy_err_code: 8,
  10790. phy_err: 1,
  10791. legacy_rate: 4,
  10792. legacy_rate_sel: 1,
  10793. end_valid: 1,
  10794. start_valid: 1;
  10795. #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI0 1
  10796. union {
  10797. A_UINT32 /* word 1 */
  10798. rssi0_pri20: 8,
  10799. rssi0_ext20: 8,
  10800. rssi0_ext40: 8,
  10801. rssi0_ext80: 8;
  10802. A_UINT32 rssi0; /* access all 20/40/80 per-bandwidth RSSIs together */
  10803. } u0;
  10804. #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI1 2
  10805. union {
  10806. A_UINT32 /* word 2 */
  10807. rssi1_pri20: 8,
  10808. rssi1_ext20: 8,
  10809. rssi1_ext40: 8,
  10810. rssi1_ext80: 8;
  10811. A_UINT32 rssi1; /* access all 20/40/80 per-bandwidth RSSIs together */
  10812. } u1;
  10813. #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI2 3
  10814. union {
  10815. A_UINT32 /* word 3 */
  10816. rssi2_pri20: 8,
  10817. rssi2_ext20: 8,
  10818. rssi2_ext40: 8,
  10819. rssi2_ext80: 8;
  10820. A_UINT32 rssi2; /* access all 20/40/80 per-bandwidth RSSIs together */
  10821. } u2;
  10822. #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI3 4
  10823. union {
  10824. A_UINT32 /* word 4 */
  10825. rssi3_pri20: 8,
  10826. rssi3_ext20: 8,
  10827. rssi3_ext40: 8,
  10828. rssi3_ext80: 8;
  10829. A_UINT32 rssi3; /* access all 20/40/80 per-bandwidth RSSIs together */
  10830. } u3;
  10831. #define HTT_RX_IND_PPDU_OFFSET_WORD_TSF32 5
  10832. A_UINT32 tsf32; /* word 5 */
  10833. #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_MICROSEC 6
  10834. A_UINT32 timestamp_microsec; /* word 6 */
  10835. #define HTT_RX_IND_PPDU_OFFSET_WORD_PREAMBLE_TYPE 7
  10836. #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A1 7
  10837. A_UINT32 /* word 7 */
  10838. vht_sig_a1: 24,
  10839. preamble_type: 8;
  10840. #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A2 8
  10841. #define HTT_RX_IND_PPDU_OFFSET_WORD_SA_ANT_MATRIX 8
  10842. A_UINT32 /* word 8 */
  10843. vht_sig_a2: 24,
  10844. /* sa_ant_matrix
  10845. * For cases where a single rx chain has options to be connected to
  10846. * different rx antennas, show which rx antennas were in use during
  10847. * receipt of a given PPDU.
  10848. * This sa_ant_matrix provides a bitmask of the antennas used while
  10849. * receiving this frame.
  10850. */
  10851. sa_ant_matrix: 8;
  10852. } POSTPACK;
  10853. #define HTT_RX_PPDU_DESC_BYTES (sizeof(struct htt_rx_ppdu_desc_t))
  10854. #define HTT_RX_PPDU_DESC_SIZE32 (HTT_RX_PPDU_DESC_BYTES >> 2)
  10855. PREPACK struct htt_rx_ind_hdr_suffix_t
  10856. {
  10857. A_UINT32 /* word 0 */
  10858. fw_rx_desc_bytes: 16,
  10859. reserved0: 16;
  10860. } POSTPACK;
  10861. #define HTT_RX_IND_HDR_SUFFIX_BYTES (sizeof(struct htt_rx_ind_hdr_suffix_t))
  10862. #define HTT_RX_IND_HDR_SUFFIX_SIZE32 (HTT_RX_IND_HDR_SUFFIX_BYTES >> 2)
  10863. PREPACK struct htt_rx_ind_hdr_t
  10864. {
  10865. struct htt_rx_ind_hdr_prefix_t prefix;
  10866. struct htt_rx_ppdu_desc_t rx_ppdu_desc;
  10867. struct htt_rx_ind_hdr_suffix_t suffix;
  10868. } POSTPACK;
  10869. #define HTT_RX_IND_HDR_BYTES (sizeof(struct htt_rx_ind_hdr_t))
  10870. #define HTT_RX_IND_HDR_SIZE32 (HTT_RX_IND_HDR_BYTES >> 2)
  10871. /* confirm that HTT_RX_IND_HDR_BYTES is a multiple of 4 */
  10872. A_COMPILE_TIME_ASSERT(HTT_RX_IND_hdr_size_quantum,
  10873. (HTT_RX_IND_HDR_BYTES & 0x3) == 0);
  10874. /*
  10875. * HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET:
  10876. * the offset into the HTT rx indication message at which the
  10877. * FW rx PPDU descriptor resides
  10878. */
  10879. #define HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET HTT_RX_IND_HDR_PREFIX_BYTES
  10880. /*
  10881. * HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET:
  10882. * the offset into the HTT rx indication message at which the
  10883. * header suffix (FW rx MSDU byte count) resides
  10884. */
  10885. #define HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET \
  10886. (HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET + HTT_RX_PPDU_DESC_BYTES)
  10887. /*
  10888. * HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET:
  10889. * the offset into the HTT rx indication message at which the per-MSDU
  10890. * information starts
  10891. * Bytes 0-7 are the message header; bytes 8-11 contain the length of the
  10892. * per-MSDU information portion of the message. The per-MSDU info itself
  10893. * starts at byte 12.
  10894. */
  10895. #define HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET HTT_RX_IND_HDR_BYTES
  10896. /**
  10897. * @brief target -> host rx indication message definition
  10898. *
  10899. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_IND
  10900. *
  10901. * @details
  10902. * The following field definitions describe the format of the rx indication
  10903. * message sent from the target to the host.
  10904. * The message consists of three major sections:
  10905. * 1. a fixed-length header
  10906. * 2. a variable-length list of firmware rx MSDU descriptors
  10907. * 3. one or more 4-octet MPDU range information elements
  10908. * The fixed length header itself has two sub-sections
  10909. * 1. the message meta-information, including identification of the
  10910. * sender and type of the received data, and a 4-octet flush/release IE
  10911. * 2. the firmware rx PPDU descriptor
  10912. *
  10913. * The format of the message is depicted below.
  10914. * in this depiction, the following abbreviations are used for information
  10915. * elements within the message:
  10916. * - SV - start valid: this flag is set if the FW rx PPDU descriptor
  10917. * elements associated with the PPDU start are valid.
  10918. * Specifically, the following fields are valid only if SV is set:
  10919. * RSSI (all variants), L, legacy rate, preamble type, service,
  10920. * VHT-SIG-A
  10921. * - EV - end valid: this flag is set if the FW rx PPDU descriptor
  10922. * elements associated with the PPDU end are valid.
  10923. * Specifically, the following fields are valid only if EV is set:
  10924. * P, PHY err code, TSF, microsec / sub-microsec timestamp
  10925. * - L - Legacy rate selector - if legacy rates are used, this flag
  10926. * indicates whether the rate is from a CCK (L == 1) or OFDM
  10927. * (L == 0) PHY.
  10928. * - P - PHY error flag - boolean indication of whether the rx frame had
  10929. * a PHY error
  10930. *
  10931. * |31 24|23 18|17|16|15|14|13|12|11|10|9|8|7|6|5|4 0|
  10932. * |----------------+-------------------+---------------------+---------------|
  10933. * | peer ID | |RV|FV| ext TID | msg type |
  10934. * |--------------------------------------------------------------------------|
  10935. * | num | release | release | flush | flush |
  10936. * | MPDU | end | start | end | start |
  10937. * | ranges | seq num | seq num | seq num | seq num |
  10938. * |==========================================================================|
  10939. * |S|E|L| legacy |P| PHY err code | sub-microsec | combined |
  10940. * |V|V| | rate | | | timestamp | RSSI |
  10941. * |--------------------------------------------------------------------------|
  10942. * | RSSI rx0 ext80 | RSSI rx0 ext40 | RSSI rx0 ext20 | RSSI rx0 pri20|
  10943. * |--------------------------------------------------------------------------|
  10944. * | RSSI rx1 ext80 | RSSI rx1 ext40 | RSSI rx1 ext20 | RSSI rx1 pri20|
  10945. * |--------------------------------------------------------------------------|
  10946. * | RSSI rx2 ext80 | RSSI rx2 ext40 | RSSI rx2 ext20 | RSSI rx2 pri20|
  10947. * |--------------------------------------------------------------------------|
  10948. * | RSSI rx3 ext80 | RSSI rx3 ext40 | RSSI rx3 ext20 | RSSI rx3 pri20|
  10949. * |--------------------------------------------------------------------------|
  10950. * | TSF LSBs |
  10951. * |--------------------------------------------------------------------------|
  10952. * | microsec timestamp |
  10953. * |--------------------------------------------------------------------------|
  10954. * | preamble type | HT-SIG / VHT-SIG-A1 |
  10955. * |--------------------------------------------------------------------------|
  10956. * | service | HT-SIG / VHT-SIG-A2 |
  10957. * |==========================================================================|
  10958. * | reserved | FW rx desc bytes |
  10959. * |--------------------------------------------------------------------------|
  10960. * | MSDU Rx | MSDU Rx | MSDU Rx | MSDU Rx |
  10961. * | desc B3 | desc B2 | desc B1 | desc B0 |
  10962. * |--------------------------------------------------------------------------|
  10963. * : : :
  10964. * |--------------------------------------------------------------------------|
  10965. * | alignment | MSDU Rx |
  10966. * | padding | desc Bn |
  10967. * |--------------------------------------------------------------------------|
  10968. * | reserved | MPDU range status | MPDU count |
  10969. * |--------------------------------------------------------------------------|
  10970. * : reserved : MPDU range status : MPDU count :
  10971. * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - :
  10972. *
  10973. * Header fields:
  10974. * - MSG_TYPE
  10975. * Bits 7:0
  10976. * Purpose: identifies this as an rx indication message
  10977. * Value: 0x1 (HTT_T2H_MSG_TYPE_RX_IND)
  10978. * - EXT_TID
  10979. * Bits 12:8
  10980. * Purpose: identify the traffic ID of the rx data, including
  10981. * special "extended" TID values for multicast, broadcast, and
  10982. * non-QoS data frames
  10983. * Value: 0-15 for regular TIDs, or >= 16 for bcast/mcast/non-QoS
  10984. * - FLUSH_VALID (FV)
  10985. * Bit 13
  10986. * Purpose: indicate whether the flush IE (start/end sequence numbers)
  10987. * is valid
  10988. * Value:
  10989. * 1 -> flush IE is valid and needs to be processed
  10990. * 0 -> flush IE is not valid and should be ignored
  10991. * - REL_VALID (RV)
  10992. * Bit 13
  10993. * Purpose: indicate whether the release IE (start/end sequence numbers)
  10994. * is valid
  10995. * Value:
  10996. * 1 -> release IE is valid and needs to be processed
  10997. * 0 -> release IE is not valid and should be ignored
  10998. * - PEER_ID
  10999. * Bits 31:16
  11000. * Purpose: Identify, by ID, which peer sent the rx data
  11001. * Value: ID of the peer who sent the rx data
  11002. * - FLUSH_SEQ_NUM_START
  11003. * Bits 5:0
  11004. * Purpose: Indicate the start of a series of MPDUs to flush
  11005. * Not all MPDUs within this series are necessarily valid - the host
  11006. * must check each sequence number within this range to see if the
  11007. * corresponding MPDU is actually present.
  11008. * This field is only valid if the FV bit is set.
  11009. * Value:
  11010. * The sequence number for the first MPDUs to check to flush.
  11011. * The sequence number is masked by 0x3f.
  11012. * - FLUSH_SEQ_NUM_END
  11013. * Bits 11:6
  11014. * Purpose: Indicate the end of a series of MPDUs to flush
  11015. * Value:
  11016. * The sequence number one larger than the sequence number of the
  11017. * last MPDU to check to flush.
  11018. * The sequence number is masked by 0x3f.
  11019. * Not all MPDUs within this series are necessarily valid - the host
  11020. * must check each sequence number within this range to see if the
  11021. * corresponding MPDU is actually present.
  11022. * This field is only valid if the FV bit is set.
  11023. * - REL_SEQ_NUM_START
  11024. * Bits 17:12
  11025. * Purpose: Indicate the start of a series of MPDUs to release.
  11026. * All MPDUs within this series are present and valid - the host
  11027. * need not check each sequence number within this range to see if
  11028. * the corresponding MPDU is actually present.
  11029. * This field is only valid if the RV bit is set.
  11030. * Value:
  11031. * The sequence number for the first MPDUs to check to release.
  11032. * The sequence number is masked by 0x3f.
  11033. * - REL_SEQ_NUM_END
  11034. * Bits 23:18
  11035. * Purpose: Indicate the end of a series of MPDUs to release.
  11036. * Value:
  11037. * The sequence number one larger than the sequence number of the
  11038. * last MPDU to check to release.
  11039. * The sequence number is masked by 0x3f.
  11040. * All MPDUs within this series are present and valid - the host
  11041. * need not check each sequence number within this range to see if
  11042. * the corresponding MPDU is actually present.
  11043. * This field is only valid if the RV bit is set.
  11044. * - NUM_MPDU_RANGES
  11045. * Bits 31:24
  11046. * Purpose: Indicate how many ranges of MPDUs are present.
  11047. * Each MPDU range consists of a series of contiguous MPDUs within the
  11048. * rx frame sequence which all have the same MPDU status.
  11049. * Value: 1-63 (typically a small number, like 1-3)
  11050. *
  11051. * Rx PPDU descriptor fields:
  11052. * - RSSI_CMB
  11053. * Bits 7:0
  11054. * Purpose: Combined RSSI from all active rx chains, across the active
  11055. * bandwidth.
  11056. * Value: RSSI dB units w.r.t. noise floor
  11057. * - TIMESTAMP_SUBMICROSEC
  11058. * Bits 15:8
  11059. * Purpose: high-resolution timestamp
  11060. * Value:
  11061. * Sub-microsecond time of PPDU reception.
  11062. * This timestamp ranges from [0,MAC clock MHz).
  11063. * This timestamp can be used in conjunction with TIMESTAMP_MICROSEC
  11064. * to form a high-resolution, large range rx timestamp.
  11065. * - PHY_ERR_CODE
  11066. * Bits 23:16
  11067. * Purpose:
  11068. * If the rx frame processing resulted in a PHY error, indicate what
  11069. * type of rx PHY error occurred.
  11070. * Value:
  11071. * This field is valid if the "P" (PHY_ERR) flag is set.
  11072. * TBD: document/specify the values for this field
  11073. * - PHY_ERR
  11074. * Bit 24
  11075. * Purpose: indicate whether the rx PPDU had a PHY error
  11076. * Value: 0 -> no rx PHY error, 1 -> rx PHY error encountered
  11077. * - LEGACY_RATE
  11078. * Bits 28:25
  11079. * Purpose:
  11080. * If the rx frame used a legacy rate rather than a HT or VHT rate,
  11081. * specify which rate was used.
  11082. * Value:
  11083. * The LEGACY_RATE field's value depends on the "L" (LEGACY_RATE_SEL)
  11084. * flag.
  11085. * If LEGACY_RATE_SEL is 0:
  11086. * 0x8: OFDM 48 Mbps
  11087. * 0x9: OFDM 24 Mbps
  11088. * 0xA: OFDM 12 Mbps
  11089. * 0xB: OFDM 6 Mbps
  11090. * 0xC: OFDM 54 Mbps
  11091. * 0xD: OFDM 36 Mbps
  11092. * 0xE: OFDM 18 Mbps
  11093. * 0xF: OFDM 9 Mbps
  11094. * If LEGACY_RATE_SEL is 1:
  11095. * 0x8: CCK 11 Mbps long preamble
  11096. * 0x9: CCK 5.5 Mbps long preamble
  11097. * 0xA: CCK 2 Mbps long preamble
  11098. * 0xB: CCK 1 Mbps long preamble
  11099. * 0xC: CCK 11 Mbps short preamble
  11100. * 0xD: CCK 5.5 Mbps short preamble
  11101. * 0xE: CCK 2 Mbps short preamble
  11102. * - LEGACY_RATE_SEL
  11103. * Bit 29
  11104. * Purpose: if rx used a legacy rate, specify whether it was OFDM or CCK
  11105. * Value:
  11106. * This field is valid if the PREAMBLE_TYPE field indicates the rx
  11107. * used a legacy rate.
  11108. * 0 -> OFDM, 1 -> CCK
  11109. * - END_VALID
  11110. * Bit 30
  11111. * Purpose: Indicate whether the FW rx PPDU desc fields associated with
  11112. * the start of the PPDU are valid. Specifically, the following
  11113. * fields are only valid if END_VALID is set:
  11114. * PHY_ERR, PHY_ERR_CODE, TSF32, TIMESTAMP_MICROSEC,
  11115. * TIMESTAMP_SUBMICROSEC
  11116. * Value:
  11117. * 0 -> rx PPDU desc end fields are not valid
  11118. * 1 -> rx PPDU desc end fields are valid
  11119. * - START_VALID
  11120. * Bit 31
  11121. * Purpose: Indicate whether the FW rx PPDU desc fields associated with
  11122. * the end of the PPDU are valid. Specifically, the following
  11123. * fields are only valid if START_VALID is set:
  11124. * RSSI, LEGACY_RATE_SEL, LEGACY_RATE, PREAMBLE_TYPE, SERVICE,
  11125. * VHT-SIG-A
  11126. * Value:
  11127. * 0 -> rx PPDU desc start fields are not valid
  11128. * 1 -> rx PPDU desc start fields are valid
  11129. * - RSSI0_PRI20
  11130. * Bits 7:0
  11131. * Purpose: RSSI from chain 0 on the primary 20 MHz channel
  11132. * Value: RSSI dB units w.r.t. noise floor
  11133. *
  11134. * - RSSI0_EXT20
  11135. * Bits 7:0
  11136. * Purpose: RSSI from chain 0 on the bonded extension 20 MHz channel
  11137. * (if the rx bandwidth was >= 40 MHz)
  11138. * Value: RSSI dB units w.r.t. noise floor
  11139. * - RSSI0_EXT40
  11140. * Bits 7:0
  11141. * Purpose: RSSI from chain 0 on the bonded extension 40 MHz channel
  11142. * (if the rx bandwidth was >= 80 MHz)
  11143. * Value: RSSI dB units w.r.t. noise floor
  11144. * - RSSI0_EXT80
  11145. * Bits 7:0
  11146. * Purpose: RSSI from chain 0 on the bonded extension 80 MHz channel
  11147. * (if the rx bandwidth was >= 160 MHz)
  11148. * Value: RSSI dB units w.r.t. noise floor
  11149. *
  11150. * - RSSI1_PRI20
  11151. * Bits 7:0
  11152. * Purpose: RSSI from chain 1 on the primary 20 MHz channel
  11153. * Value: RSSI dB units w.r.t. noise floor
  11154. * - RSSI1_EXT20
  11155. * Bits 7:0
  11156. * Purpose: RSSI from chain 1 on the bonded extension 20 MHz channel
  11157. * (if the rx bandwidth was >= 40 MHz)
  11158. * Value: RSSI dB units w.r.t. noise floor
  11159. * - RSSI1_EXT40
  11160. * Bits 7:0
  11161. * Purpose: RSSI from chain 1 on the bonded extension 40 MHz channel
  11162. * (if the rx bandwidth was >= 80 MHz)
  11163. * Value: RSSI dB units w.r.t. noise floor
  11164. * - RSSI1_EXT80
  11165. * Bits 7:0
  11166. * Purpose: RSSI from chain 1 on the bonded extension 80 MHz channel
  11167. * (if the rx bandwidth was >= 160 MHz)
  11168. * Value: RSSI dB units w.r.t. noise floor
  11169. *
  11170. * - RSSI2_PRI20
  11171. * Bits 7:0
  11172. * Purpose: RSSI from chain 2 on the primary 20 MHz channel
  11173. * Value: RSSI dB units w.r.t. noise floor
  11174. * - RSSI2_EXT20
  11175. * Bits 7:0
  11176. * Purpose: RSSI from chain 2 on the bonded extension 20 MHz channel
  11177. * (if the rx bandwidth was >= 40 MHz)
  11178. * Value: RSSI dB units w.r.t. noise floor
  11179. * - RSSI2_EXT40
  11180. * Bits 7:0
  11181. * Purpose: RSSI from chain 2 on the bonded extension 40 MHz channel
  11182. * (if the rx bandwidth was >= 80 MHz)
  11183. * Value: RSSI dB units w.r.t. noise floor
  11184. * - RSSI2_EXT80
  11185. * Bits 7:0
  11186. * Purpose: RSSI from chain 2 on the bonded extension 80 MHz channel
  11187. * (if the rx bandwidth was >= 160 MHz)
  11188. * Value: RSSI dB units w.r.t. noise floor
  11189. *
  11190. * - RSSI3_PRI20
  11191. * Bits 7:0
  11192. * Purpose: RSSI from chain 3 on the primary 20 MHz channel
  11193. * Value: RSSI dB units w.r.t. noise floor
  11194. * - RSSI3_EXT20
  11195. * Bits 7:0
  11196. * Purpose: RSSI from chain 3 on the bonded extension 20 MHz channel
  11197. * (if the rx bandwidth was >= 40 MHz)
  11198. * Value: RSSI dB units w.r.t. noise floor
  11199. * - RSSI3_EXT40
  11200. * Bits 7:0
  11201. * Purpose: RSSI from chain 3 on the bonded extension 40 MHz channel
  11202. * (if the rx bandwidth was >= 80 MHz)
  11203. * Value: RSSI dB units w.r.t. noise floor
  11204. * - RSSI3_EXT80
  11205. * Bits 7:0
  11206. * Purpose: RSSI from chain 3 on the bonded extension 80 MHz channel
  11207. * (if the rx bandwidth was >= 160 MHz)
  11208. * Value: RSSI dB units w.r.t. noise floor
  11209. *
  11210. * - TSF32
  11211. * Bits 31:0
  11212. * Purpose: specify the time the rx PPDU was received, in TSF units
  11213. * Value: 32 LSBs of the TSF
  11214. * - TIMESTAMP_MICROSEC
  11215. * Bits 31:0
  11216. * Purpose: specify the time the rx PPDU was received, in microsecond units
  11217. * Value: PPDU rx time, in microseconds
  11218. * - VHT_SIG_A1
  11219. * Bits 23:0
  11220. * Purpose: Provide the HT-SIG (initial 24 bits) or VHT-SIG-A1 field
  11221. * from the rx PPDU
  11222. * Value:
  11223. * If PREAMBLE_TYPE specifies VHT, then this field contains the
  11224. * VHT-SIG-A1 data.
  11225. * If PREAMBLE_TYPE specifies HT, then this field contains the
  11226. * first 24 bits of the HT-SIG data.
  11227. * Otherwise, this field is invalid.
  11228. * Refer to the the 802.11 protocol for the definition of the
  11229. * HT-SIG and VHT-SIG-A1 fields
  11230. * - VHT_SIG_A2
  11231. * Bits 23:0
  11232. * Purpose: Provide the HT-SIG (final 24 bits) or VHT-SIG-A2 field
  11233. * from the rx PPDU
  11234. * Value:
  11235. * If PREAMBLE_TYPE specifies VHT, then this field contains the
  11236. * VHT-SIG-A2 data.
  11237. * If PREAMBLE_TYPE specifies HT, then this field contains the
  11238. * last 24 bits of the HT-SIG data.
  11239. * Otherwise, this field is invalid.
  11240. * Refer to the the 802.11 protocol for the definition of the
  11241. * HT-SIG and VHT-SIG-A2 fields
  11242. * - PREAMBLE_TYPE
  11243. * Bits 31:24
  11244. * Purpose: indicate the PHY format of the received burst
  11245. * Value:
  11246. * 0x4: Legacy (OFDM/CCK)
  11247. * 0x8: HT
  11248. * 0x9: HT with TxBF
  11249. * 0xC: VHT
  11250. * 0xD: VHT with TxBF
  11251. * - SERVICE
  11252. * Bits 31:24
  11253. * Purpose: TBD
  11254. * Value: TBD
  11255. *
  11256. * Rx MSDU descriptor fields:
  11257. * - FW_RX_DESC_BYTES
  11258. * Bits 15:0
  11259. * Purpose: Indicate how many bytes in the Rx indication are used for
  11260. * FW Rx descriptors
  11261. *
  11262. * Payload fields:
  11263. * - MPDU_COUNT
  11264. * Bits 7:0
  11265. * Purpose: Indicate how many sequential MPDUs share the same status.
  11266. * All MPDUs within the indicated list are from the same RA-TA-TID.
  11267. * - MPDU_STATUS
  11268. * Bits 15:8
  11269. * Purpose: Indicate whether the (group of sequential) MPDU(s) were
  11270. * received successfully.
  11271. * Value:
  11272. * 0x1: success
  11273. * 0x2: FCS error
  11274. * 0x3: duplicate error
  11275. * 0x4: replay error
  11276. * 0x5: invalid peer
  11277. */
  11278. /* header fields */
  11279. #define HTT_RX_IND_EXT_TID_M 0x1f00
  11280. #define HTT_RX_IND_EXT_TID_S 8
  11281. #define HTT_RX_IND_FLUSH_VALID_M 0x2000
  11282. #define HTT_RX_IND_FLUSH_VALID_S 13
  11283. #define HTT_RX_IND_REL_VALID_M 0x4000
  11284. #define HTT_RX_IND_REL_VALID_S 14
  11285. #define HTT_RX_IND_PEER_ID_M 0xffff0000
  11286. #define HTT_RX_IND_PEER_ID_S 16
  11287. #define HTT_RX_IND_FLUSH_SEQ_NUM_START_M 0x3f
  11288. #define HTT_RX_IND_FLUSH_SEQ_NUM_START_S 0
  11289. #define HTT_RX_IND_FLUSH_SEQ_NUM_END_M 0xfc0
  11290. #define HTT_RX_IND_FLUSH_SEQ_NUM_END_S 6
  11291. #define HTT_RX_IND_REL_SEQ_NUM_START_M 0x3f000
  11292. #define HTT_RX_IND_REL_SEQ_NUM_START_S 12
  11293. #define HTT_RX_IND_REL_SEQ_NUM_END_M 0xfc0000
  11294. #define HTT_RX_IND_REL_SEQ_NUM_END_S 18
  11295. #define HTT_RX_IND_NUM_MPDU_RANGES_M 0xff000000
  11296. #define HTT_RX_IND_NUM_MPDU_RANGES_S 24
  11297. /* rx PPDU descriptor fields */
  11298. #define HTT_RX_IND_RSSI_CMB_M 0x000000ff
  11299. #define HTT_RX_IND_RSSI_CMB_S 0
  11300. #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M 0x0000ff00
  11301. #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S 8
  11302. #define HTT_RX_IND_PHY_ERR_CODE_M 0x00ff0000
  11303. #define HTT_RX_IND_PHY_ERR_CODE_S 16
  11304. #define HTT_RX_IND_PHY_ERR_M 0x01000000
  11305. #define HTT_RX_IND_PHY_ERR_S 24
  11306. #define HTT_RX_IND_LEGACY_RATE_M 0x1e000000
  11307. #define HTT_RX_IND_LEGACY_RATE_S 25
  11308. #define HTT_RX_IND_LEGACY_RATE_SEL_M 0x20000000
  11309. #define HTT_RX_IND_LEGACY_RATE_SEL_S 29
  11310. #define HTT_RX_IND_END_VALID_M 0x40000000
  11311. #define HTT_RX_IND_END_VALID_S 30
  11312. #define HTT_RX_IND_START_VALID_M 0x80000000
  11313. #define HTT_RX_IND_START_VALID_S 31
  11314. #define HTT_RX_IND_RSSI_PRI20_M 0x000000ff
  11315. #define HTT_RX_IND_RSSI_PRI20_S 0
  11316. #define HTT_RX_IND_RSSI_EXT20_M 0x0000ff00
  11317. #define HTT_RX_IND_RSSI_EXT20_S 8
  11318. #define HTT_RX_IND_RSSI_EXT40_M 0x00ff0000
  11319. #define HTT_RX_IND_RSSI_EXT40_S 16
  11320. #define HTT_RX_IND_RSSI_EXT80_M 0xff000000
  11321. #define HTT_RX_IND_RSSI_EXT80_S 24
  11322. #define HTT_RX_IND_VHT_SIG_A1_M 0x00ffffff
  11323. #define HTT_RX_IND_VHT_SIG_A1_S 0
  11324. #define HTT_RX_IND_VHT_SIG_A2_M 0x00ffffff
  11325. #define HTT_RX_IND_VHT_SIG_A2_S 0
  11326. #define HTT_RX_IND_PREAMBLE_TYPE_M 0xff000000
  11327. #define HTT_RX_IND_PREAMBLE_TYPE_S 24
  11328. #define HTT_RX_IND_SERVICE_M 0xff000000
  11329. #define HTT_RX_IND_SERVICE_S 24
  11330. #define HTT_RX_IND_SA_ANT_MATRIX_M 0xff000000
  11331. #define HTT_RX_IND_SA_ANT_MATRIX_S 24
  11332. /* rx MSDU descriptor fields */
  11333. #define HTT_RX_IND_FW_RX_DESC_BYTES_M 0xffff
  11334. #define HTT_RX_IND_FW_RX_DESC_BYTES_S 0
  11335. /* payload fields */
  11336. #define HTT_RX_IND_MPDU_COUNT_M 0xff
  11337. #define HTT_RX_IND_MPDU_COUNT_S 0
  11338. #define HTT_RX_IND_MPDU_STATUS_M 0xff00
  11339. #define HTT_RX_IND_MPDU_STATUS_S 8
  11340. #define HTT_RX_IND_EXT_TID_SET(word, value) \
  11341. do { \
  11342. HTT_CHECK_SET_VAL(HTT_RX_IND_EXT_TID, value); \
  11343. (word) |= (value) << HTT_RX_IND_EXT_TID_S; \
  11344. } while (0)
  11345. #define HTT_RX_IND_EXT_TID_GET(word) \
  11346. (((word) & HTT_RX_IND_EXT_TID_M) >> HTT_RX_IND_EXT_TID_S)
  11347. #define HTT_RX_IND_FLUSH_VALID_SET(word, value) \
  11348. do { \
  11349. HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_VALID, value); \
  11350. (word) |= (value) << HTT_RX_IND_FLUSH_VALID_S; \
  11351. } while (0)
  11352. #define HTT_RX_IND_FLUSH_VALID_GET(word) \
  11353. (((word) & HTT_RX_IND_FLUSH_VALID_M) >> HTT_RX_IND_FLUSH_VALID_S)
  11354. #define HTT_RX_IND_REL_VALID_SET(word, value) \
  11355. do { \
  11356. HTT_CHECK_SET_VAL(HTT_RX_IND_REL_VALID, value); \
  11357. (word) |= (value) << HTT_RX_IND_REL_VALID_S; \
  11358. } while (0)
  11359. #define HTT_RX_IND_REL_VALID_GET(word) \
  11360. (((word) & HTT_RX_IND_REL_VALID_M) >> HTT_RX_IND_REL_VALID_S)
  11361. #define HTT_RX_IND_PEER_ID_SET(word, value) \
  11362. do { \
  11363. HTT_CHECK_SET_VAL(HTT_RX_IND_PEER_ID, value); \
  11364. (word) |= (value) << HTT_RX_IND_PEER_ID_S; \
  11365. } while (0)
  11366. #define HTT_RX_IND_PEER_ID_GET(word) \
  11367. (((word) & HTT_RX_IND_PEER_ID_M) >> HTT_RX_IND_PEER_ID_S)
  11368. #define HTT_RX_IND_FW_RX_DESC_BYTES_SET(word, value) \
  11369. do { \
  11370. HTT_CHECK_SET_VAL(HTT_RX_IND_FW_RX_DESC_BYTES, value); \
  11371. (word) |= (value) << HTT_RX_IND_FW_RX_DESC_BYTES_S; \
  11372. } while (0)
  11373. #define HTT_RX_IND_FW_RX_DESC_BYTES_GET(word) \
  11374. (((word) & HTT_RX_IND_FW_RX_DESC_BYTES_M) >> HTT_RX_IND_FW_RX_DESC_BYTES_S)
  11375. #define HTT_RX_IND_FLUSH_SEQ_NUM_START_SET(word, value) \
  11376. do { \
  11377. HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_START, value); \
  11378. (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_START_S; \
  11379. } while (0)
  11380. #define HTT_RX_IND_FLUSH_SEQ_NUM_START_GET(word) \
  11381. (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_START_M) >> \
  11382. HTT_RX_IND_FLUSH_SEQ_NUM_START_S)
  11383. #define HTT_RX_IND_FLUSH_SEQ_NUM_END_SET(word, value) \
  11384. do { \
  11385. HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_END, value); \
  11386. (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_END_S; \
  11387. } while (0)
  11388. #define HTT_RX_IND_FLUSH_SEQ_NUM_END_GET(word) \
  11389. (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_END_M) >> \
  11390. HTT_RX_IND_FLUSH_SEQ_NUM_END_S)
  11391. #define HTT_RX_IND_REL_SEQ_NUM_START_SET(word, value) \
  11392. do { \
  11393. HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_START, value); \
  11394. (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_START_S; \
  11395. } while (0)
  11396. #define HTT_RX_IND_REL_SEQ_NUM_START_GET(word) \
  11397. (((word) & HTT_RX_IND_REL_SEQ_NUM_START_M) >> \
  11398. HTT_RX_IND_REL_SEQ_NUM_START_S)
  11399. #define HTT_RX_IND_REL_SEQ_NUM_END_SET(word, value) \
  11400. do { \
  11401. HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_END, value); \
  11402. (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_END_S; \
  11403. } while (0)
  11404. #define HTT_RX_IND_REL_SEQ_NUM_END_GET(word) \
  11405. (((word) & HTT_RX_IND_REL_SEQ_NUM_END_M) >> \
  11406. HTT_RX_IND_REL_SEQ_NUM_END_S)
  11407. #define HTT_RX_IND_NUM_MPDU_RANGES_SET(word, value) \
  11408. do { \
  11409. HTT_CHECK_SET_VAL(HTT_RX_IND_NUM_MPDU_RANGES, value); \
  11410. (word) |= (value) << HTT_RX_IND_NUM_MPDU_RANGES_S; \
  11411. } while (0)
  11412. #define HTT_RX_IND_NUM_MPDU_RANGES_GET(word) \
  11413. (((word) & HTT_RX_IND_NUM_MPDU_RANGES_M) >> \
  11414. HTT_RX_IND_NUM_MPDU_RANGES_S)
  11415. /* FW rx PPDU descriptor fields */
  11416. #define HTT_RX_IND_RSSI_CMB_SET(word, value) \
  11417. do { \
  11418. HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_CMB, value); \
  11419. (word) |= (value) << HTT_RX_IND_RSSI_CMB_S; \
  11420. } while (0)
  11421. #define HTT_RX_IND_RSSI_CMB_GET(word) \
  11422. (((word) & HTT_RX_IND_RSSI_CMB_M) >> \
  11423. HTT_RX_IND_RSSI_CMB_S)
  11424. #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_SET(word, value) \
  11425. do { \
  11426. HTT_CHECK_SET_VAL(HTT_RX_IND_TIMESTAMP_SUBMICROSEC, value); \
  11427. (word) |= (value) << HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S; \
  11428. } while (0)
  11429. #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_GET(word) \
  11430. (((word) & HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M) >> \
  11431. HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S)
  11432. #define HTT_RX_IND_PHY_ERR_CODE_SET(word, value) \
  11433. do { \
  11434. HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR_CODE, value); \
  11435. (word) |= (value) << HTT_RX_IND_PHY_ERR_CODE_S; \
  11436. } while (0)
  11437. #define HTT_RX_IND_PHY_ERR_CODE_GET(word) \
  11438. (((word) & HTT_RX_IND_PHY_ERR_CODE_M) >> \
  11439. HTT_RX_IND_PHY_ERR_CODE_S)
  11440. #define HTT_RX_IND_PHY_ERR_SET(word, value) \
  11441. do { \
  11442. HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR, value); \
  11443. (word) |= (value) << HTT_RX_IND_PHY_ERR_S; \
  11444. } while (0)
  11445. #define HTT_RX_IND_PHY_ERR_GET(word) \
  11446. (((word) & HTT_RX_IND_PHY_ERR_M) >> \
  11447. HTT_RX_IND_PHY_ERR_S)
  11448. #define HTT_RX_IND_LEGACY_RATE_SET(word, value) \
  11449. do { \
  11450. HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE, value); \
  11451. (word) |= (value) << HTT_RX_IND_LEGACY_RATE_S; \
  11452. } while (0)
  11453. #define HTT_RX_IND_LEGACY_RATE_GET(word) \
  11454. (((word) & HTT_RX_IND_LEGACY_RATE_M) >> \
  11455. HTT_RX_IND_LEGACY_RATE_S)
  11456. #define HTT_RX_IND_LEGACY_RATE_SEL_SET(word, value) \
  11457. do { \
  11458. HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE_SEL, value); \
  11459. (word) |= (value) << HTT_RX_IND_LEGACY_RATE_SEL_S; \
  11460. } while (0)
  11461. #define HTT_RX_IND_LEGACY_RATE_SEL_GET(word) \
  11462. (((word) & HTT_RX_IND_LEGACY_RATE_SEL_M) >> \
  11463. HTT_RX_IND_LEGACY_RATE_SEL_S)
  11464. #define HTT_RX_IND_END_VALID_SET(word, value) \
  11465. do { \
  11466. HTT_CHECK_SET_VAL(HTT_RX_IND_END_VALID, value); \
  11467. (word) |= (value) << HTT_RX_IND_END_VALID_S; \
  11468. } while (0)
  11469. #define HTT_RX_IND_END_VALID_GET(word) \
  11470. (((word) & HTT_RX_IND_END_VALID_M) >> \
  11471. HTT_RX_IND_END_VALID_S)
  11472. #define HTT_RX_IND_START_VALID_SET(word, value) \
  11473. do { \
  11474. HTT_CHECK_SET_VAL(HTT_RX_IND_START_VALID, value); \
  11475. (word) |= (value) << HTT_RX_IND_START_VALID_S; \
  11476. } while (0)
  11477. #define HTT_RX_IND_START_VALID_GET(word) \
  11478. (((word) & HTT_RX_IND_START_VALID_M) >> \
  11479. HTT_RX_IND_START_VALID_S)
  11480. #define HTT_RX_IND_RSSI_PRI20_SET(word, value) \
  11481. do { \
  11482. HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_PRI20, value); \
  11483. (word) |= (value) << HTT_RX_IND_RSSI_PRI20_S; \
  11484. } while (0)
  11485. #define HTT_RX_IND_RSSI_PRI20_GET(word) \
  11486. (((word) & HTT_RX_IND_RSSI_PRI20_M) >> \
  11487. HTT_RX_IND_RSSI_PRI20_S)
  11488. #define HTT_RX_IND_RSSI_EXT20_SET(word, value) \
  11489. do { \
  11490. HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT20, value); \
  11491. (word) |= (value) << HTT_RX_IND_RSSI_EXT20_S; \
  11492. } while (0)
  11493. #define HTT_RX_IND_RSSI_EXT20_GET(word) \
  11494. (((word) & HTT_RX_IND_RSSI_EXT20_M) >> \
  11495. HTT_RX_IND_RSSI_EXT20_S)
  11496. #define HTT_RX_IND_RSSI_EXT40_SET(word, value) \
  11497. do { \
  11498. HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT40, value); \
  11499. (word) |= (value) << HTT_RX_IND_RSSI_EXT40_S; \
  11500. } while (0)
  11501. #define HTT_RX_IND_RSSI_EXT40_GET(word) \
  11502. (((word) & HTT_RX_IND_RSSI_EXT40_M) >> \
  11503. HTT_RX_IND_RSSI_EXT40_S)
  11504. #define HTT_RX_IND_RSSI_EXT80_SET(word, value) \
  11505. do { \
  11506. HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT80, value); \
  11507. (word) |= (value) << HTT_RX_IND_RSSI_EXT80_S; \
  11508. } while (0)
  11509. #define HTT_RX_IND_RSSI_EXT80_GET(word) \
  11510. (((word) & HTT_RX_IND_RSSI_EXT80_M) >> \
  11511. HTT_RX_IND_RSSI_EXT80_S)
  11512. #define HTT_RX_IND_VHT_SIG_A1_SET(word, value) \
  11513. do { \
  11514. HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A1, value); \
  11515. (word) |= (value) << HTT_RX_IND_VHT_SIG_A1_S; \
  11516. } while (0)
  11517. #define HTT_RX_IND_VHT_SIG_A1_GET(word) \
  11518. (((word) & HTT_RX_IND_VHT_SIG_A1_M) >> \
  11519. HTT_RX_IND_VHT_SIG_A1_S)
  11520. #define HTT_RX_IND_VHT_SIG_A2_SET(word, value) \
  11521. do { \
  11522. HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A2, value); \
  11523. (word) |= (value) << HTT_RX_IND_VHT_SIG_A2_S; \
  11524. } while (0)
  11525. #define HTT_RX_IND_VHT_SIG_A2_GET(word) \
  11526. (((word) & HTT_RX_IND_VHT_SIG_A2_M) >> \
  11527. HTT_RX_IND_VHT_SIG_A2_S)
  11528. #define HTT_RX_IND_PREAMBLE_TYPE_SET(word, value) \
  11529. do { \
  11530. HTT_CHECK_SET_VAL(HTT_RX_IND_PREAMBLE_TYPE, value); \
  11531. (word) |= (value) << HTT_RX_IND_PREAMBLE_TYPE_S; \
  11532. } while (0)
  11533. #define HTT_RX_IND_PREAMBLE_TYPE_GET(word) \
  11534. (((word) & HTT_RX_IND_PREAMBLE_TYPE_M) >> \
  11535. HTT_RX_IND_PREAMBLE_TYPE_S)
  11536. #define HTT_RX_IND_SERVICE_SET(word, value) \
  11537. do { \
  11538. HTT_CHECK_SET_VAL(HTT_RX_IND_SERVICE, value); \
  11539. (word) |= (value) << HTT_RX_IND_SERVICE_S; \
  11540. } while (0)
  11541. #define HTT_RX_IND_SERVICE_GET(word) \
  11542. (((word) & HTT_RX_IND_SERVICE_M) >> \
  11543. HTT_RX_IND_SERVICE_S)
  11544. #define HTT_RX_IND_SA_ANT_MATRIX_SET(word, value) \
  11545. do { \
  11546. HTT_CHECK_SET_VAL(HTT_RX_IND_SA_ANT_MATRIX, value); \
  11547. (word) |= (value) << HTT_RX_IND_SA_ANT_MATRIX_S; \
  11548. } while (0)
  11549. #define HTT_RX_IND_SA_ANT_MATRIX_GET(word) \
  11550. (((word) & HTT_RX_IND_SA_ANT_MATRIX_M) >> \
  11551. HTT_RX_IND_SA_ANT_MATRIX_S)
  11552. #define HTT_RX_IND_MPDU_COUNT_SET(word, value) \
  11553. do { \
  11554. HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_COUNT, value); \
  11555. (word) |= (value) << HTT_RX_IND_MPDU_COUNT_S; \
  11556. } while (0)
  11557. #define HTT_RX_IND_MPDU_COUNT_GET(word) \
  11558. (((word) & HTT_RX_IND_MPDU_COUNT_M) >> HTT_RX_IND_MPDU_COUNT_S)
  11559. #define HTT_RX_IND_MPDU_STATUS_SET(word, value) \
  11560. do { \
  11561. HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_STATUS, value); \
  11562. (word) |= (value) << HTT_RX_IND_MPDU_STATUS_S; \
  11563. } while (0)
  11564. #define HTT_RX_IND_MPDU_STATUS_GET(word) \
  11565. (((word) & HTT_RX_IND_MPDU_STATUS_M) >> HTT_RX_IND_MPDU_STATUS_S)
  11566. #define HTT_RX_IND_HL_BYTES \
  11567. (HTT_RX_IND_HDR_BYTES + \
  11568. 4 /* single FW rx MSDU descriptor */ + \
  11569. 4 /* single MPDU range information element */)
  11570. #define HTT_RX_IND_HL_SIZE32 (HTT_RX_IND_HL_BYTES >> 2)
  11571. /* Could we use one macro entry? */
  11572. #define HTT_WORD_SET(word, field, value) \
  11573. do { \
  11574. HTT_CHECK_SET_VAL(field, value); \
  11575. (word) |= ((value) << field ## _S); \
  11576. } while (0)
  11577. #define HTT_WORD_GET(word, field) \
  11578. (((word) & field ## _M) >> field ## _S)
  11579. PREPACK struct hl_htt_rx_ind_base {
  11580. A_UINT32 rx_ind_msg[HTT_RX_IND_HL_SIZE32]; /* align with LL case rx indication message, but reduced to 5 words */
  11581. } POSTPACK;
  11582. /*
  11583. * HTT_RX_IND_HL_RX_DESC_BASE_OFFSET
  11584. * Currently, we use a resv field in hl_htt_rx_ind_base to store some
  11585. * HL host needed info; refer to fw_rx_desc_base in wal_rx_desc.h.
  11586. * The field is just after the MSDU FW rx desc, and 1 byte ahead of
  11587. * htt_rx_ind_hl_rx_desc_t.
  11588. */
  11589. #define HTT_RX_IND_HL_RX_DESC_BASE_OFFSET (HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET + 1)
  11590. struct htt_rx_ind_hl_rx_desc_t {
  11591. A_UINT8 ver;
  11592. A_UINT8 len;
  11593. struct {
  11594. A_UINT8
  11595. first_msdu: 1,
  11596. last_msdu: 1,
  11597. c3_failed: 1,
  11598. c4_failed: 1,
  11599. ipv6: 1,
  11600. tcp: 1,
  11601. udp: 1,
  11602. reserved: 1;
  11603. } flags;
  11604. /* NOTE: no reserved space - don't append any new fields here */
  11605. };
  11606. #define HTT_RX_IND_HL_RX_DESC_VER_OFFSET \
  11607. (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \
  11608. + offsetof(struct htt_rx_ind_hl_rx_desc_t, ver))
  11609. #define HTT_RX_IND_HL_RX_DESC_VER 0
  11610. #define HTT_RX_IND_HL_RX_DESC_LEN_OFFSET \
  11611. (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \
  11612. + offsetof(struct htt_rx_ind_hl_rx_desc_t, len))
  11613. #define HTT_RX_IND_HL_FLAG_OFFSET \
  11614. (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \
  11615. + offsetof(struct htt_rx_ind_hl_rx_desc_t, flags))
  11616. #define HTT_RX_IND_HL_FLAG_FIRST_MSDU (0x01 << 0)
  11617. #define HTT_RX_IND_HL_FLAG_LAST_MSDU (0x01 << 1)
  11618. #define HTT_RX_IND_HL_FLAG_C3_FAILED (0x01 << 2) /* L3 checksum failed */
  11619. #define HTT_RX_IND_HL_FLAG_C4_FAILED (0x01 << 3) /* L4 checksum failed */
  11620. #define HTT_RX_IND_HL_FLAG_IPV6 (0x01 << 4) /* is ipv6, or else ipv4 */
  11621. #define HTT_RX_IND_HL_FLAG_TCP (0x01 << 5) /* is tcp */
  11622. #define HTT_RX_IND_HL_FLAG_UDP (0x01 << 6) /* is udp */
  11623. /* This structure is used in HL, the basic descriptor information
  11624. * used by host. the structure is translated by FW from HW desc
  11625. * or generated by FW. But in HL monitor mode, the host would use
  11626. * the same structure with LL.
  11627. */
  11628. PREPACK struct hl_htt_rx_desc_base {
  11629. A_UINT32
  11630. seq_num:12,
  11631. encrypted:1,
  11632. chan_info_present:1,
  11633. resv0:2,
  11634. mcast_bcast:1,
  11635. fragment:1,
  11636. key_id_oct:8,
  11637. resv1:6;
  11638. A_UINT32
  11639. pn_31_0;
  11640. union {
  11641. struct {
  11642. A_UINT16 pn_47_32;
  11643. A_UINT16 pn_63_48;
  11644. } pn16;
  11645. A_UINT32 pn_63_32;
  11646. } u0;
  11647. A_UINT32
  11648. pn_95_64;
  11649. A_UINT32
  11650. pn_127_96;
  11651. } POSTPACK;
  11652. /*
  11653. * Channel information can optionally be appended after hl_htt_rx_desc_base.
  11654. * If so, the len field in htt_rx_ind_hl_rx_desc_t will be updated accordingly,
  11655. * and the chan_info_present flag in hl_htt_rx_desc_base will be set.
  11656. * Please see htt_chan_change_t for description of the fields.
  11657. */
  11658. PREPACK struct htt_chan_info_t
  11659. {
  11660. A_UINT32 primary_chan_center_freq_mhz: 16,
  11661. contig_chan1_center_freq_mhz: 16;
  11662. A_UINT32 contig_chan2_center_freq_mhz: 16,
  11663. phy_mode: 8,
  11664. reserved: 8;
  11665. } POSTPACK;
  11666. #define HTT_CHAN_INFO_SIZE sizeof(struct htt_chan_info_t)
  11667. #define HL_RX_DESC_SIZE (sizeof(struct hl_htt_rx_desc_base))
  11668. #define HL_RX_DESC_SIZE_DWORD (HL_RX_STD_DESC_SIZE >> 2)
  11669. #define HTT_HL_RX_DESC_MPDU_SEQ_NUM_M 0xfff
  11670. #define HTT_HL_RX_DESC_MPDU_SEQ_NUM_S 0
  11671. #define HTT_HL_RX_DESC_MPDU_ENC_M 0x1000
  11672. #define HTT_HL_RX_DESC_MPDU_ENC_S 12
  11673. #define HTT_HL_RX_DESC_CHAN_INFO_PRESENT_M 0x2000
  11674. #define HTT_HL_RX_DESC_CHAN_INFO_PRESENT_S 13
  11675. #define HTT_HL_RX_DESC_MCAST_BCAST_M 0x10000
  11676. #define HTT_HL_RX_DESC_MCAST_BCAST_S 16
  11677. #define HTT_HL_RX_DESC_FRAGMENT_M 0x20000
  11678. #define HTT_HL_RX_DESC_FRAGMENT_S 17
  11679. #define HTT_HL_RX_DESC_KEY_ID_OCT_M 0x3fc0000
  11680. #define HTT_HL_RX_DESC_KEY_ID_OCT_S 18
  11681. #define HTT_HL_RX_DESC_PN_OFFSET offsetof(struct hl_htt_rx_desc_base, pn_31_0)
  11682. #define HTT_HL_RX_DESC_PN_WORD_OFFSET (HTT_HL_RX_DESC_PN_OFFSET >> 2)
  11683. /* Channel information */
  11684. #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M 0x0000ffff
  11685. #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S 0
  11686. #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M 0xffff0000
  11687. #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S 16
  11688. #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M 0x0000ffff
  11689. #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S 0
  11690. #define HTT_CHAN_INFO_PHY_MODE_M 0x00ff0000
  11691. #define HTT_CHAN_INFO_PHY_MODE_S 16
  11692. #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_SET(word, value) \
  11693. do { \
  11694. HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ, value); \
  11695. (word) |= (value) << HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S; \
  11696. } while (0)
  11697. #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_GET(word) \
  11698. (((word) & HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M) >> HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S)
  11699. #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_SET(word, value) \
  11700. do { \
  11701. HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ, value); \
  11702. (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S; \
  11703. } while (0)
  11704. #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_GET(word) \
  11705. (((word) & HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M) >> HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S)
  11706. #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_SET(word, value) \
  11707. do { \
  11708. HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ, value); \
  11709. (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S; \
  11710. } while (0)
  11711. #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_GET(word) \
  11712. (((word) & HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M) >> HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S)
  11713. #define HTT_CHAN_INFO_PHY_MODE_SET(word, value) \
  11714. do { \
  11715. HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PHY_MODE, value); \
  11716. (word) |= (value) << HTT_CHAN_INFO_PHY_MODE_S; \
  11717. } while (0)
  11718. #define HTT_CHAN_INFO_PHY_MODE_GET(word) \
  11719. (((word) & HTT_CHAN_INFO_PHY_MODE_M) >> HTT_CHAN_INFO_PHY_MODE_S)
  11720. /*
  11721. * @brief target -> host message definition for FW offloaded pkts
  11722. *
  11723. * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND
  11724. *
  11725. * @details
  11726. * The following field definitions describe the format of the firmware
  11727. * offload deliver message sent from the target to the host.
  11728. *
  11729. * definition for struct htt_tx_offload_deliver_ind_hdr_t
  11730. *
  11731. * |31 20|19 16|15 13|12 8|7 5|4|3|2 0|
  11732. * |----------------------------+--------+-----+---------------+-----+-+-+----|
  11733. * | reserved_1 | msg type |
  11734. * |--------------------------------------------------------------------------|
  11735. * | phy_timestamp_l32 |
  11736. * |--------------------------------------------------------------------------|
  11737. * | WORD2 (see below) |
  11738. * |--------------------------------------------------------------------------|
  11739. * | seqno | framectrl |
  11740. * |--------------------------------------------------------------------------|
  11741. * | reserved_3 | vdev_id | tid_num|
  11742. * |--------------------------------------------------------------------------|
  11743. * | reserved_4 | tx_mpdu_bytes |F|STAT|
  11744. * |--------------------------------------------------------------------------|
  11745. *
  11746. * where:
  11747. * STAT = status
  11748. * F = format (802.3 vs. 802.11)
  11749. *
  11750. * definition for word 2
  11751. *
  11752. * |31 26|25| 24 |23 | 22 |21 19|18 17|16 9|8 6|5 2|1 0|
  11753. * |--------+--+----+---+----+-----+-----+---------------------+----+-----+---|
  11754. * |reserv_2|BF|LDPC|SGI|STBC| BW | NSS | RSSI |RATE| MCS |PR |
  11755. * |--------------------------------------------------------------------------|
  11756. *
  11757. * where:
  11758. * PR = preamble
  11759. * BF = beamformed
  11760. */
  11761. PREPACK struct htt_tx_offload_deliver_ind_hdr_t
  11762. {
  11763. A_UINT32 /* word 0 */
  11764. msg_type:8, /* [ 7: 0] */
  11765. reserved_1:24; /* [31: 8] */
  11766. A_UINT32 phy_timestamp_l32; /* word 1 [31:0] */
  11767. A_UINT32 /* word 2 */
  11768. /* preamble:
  11769. * 0-OFDM,
  11770. * 1-CCk,
  11771. * 2-HT,
  11772. * 3-VHT
  11773. */
  11774. preamble: 2, /* [1:0] */
  11775. /* mcs:
  11776. * In case of HT preamble interpret
  11777. * MCS along with NSS.
  11778. * Valid values for HT are 0 to 7.
  11779. * HT mcs 0 with NSS 2 is mcs 8.
  11780. * Valid values for VHT are 0 to 9.
  11781. */
  11782. mcs: 4, /* [5:2] */
  11783. /* rate:
  11784. * This is applicable only for
  11785. * CCK and OFDM preamble type
  11786. * rate 0: OFDM 48 Mbps,
  11787. * 1: OFDM 24 Mbps,
  11788. * 2: OFDM 12 Mbps
  11789. * 3: OFDM 6 Mbps
  11790. * 4: OFDM 54 Mbps
  11791. * 5: OFDM 36 Mbps
  11792. * 6: OFDM 18 Mbps
  11793. * 7: OFDM 9 Mbps
  11794. * rate 0: CCK 11 Mbps Long
  11795. * 1: CCK 5.5 Mbps Long
  11796. * 2: CCK 2 Mbps Long
  11797. * 3: CCK 1 Mbps Long
  11798. * 4: CCK 11 Mbps Short
  11799. * 5: CCK 5.5 Mbps Short
  11800. * 6: CCK 2 Mbps Short
  11801. */
  11802. rate : 3, /* [ 8: 6] */
  11803. rssi : 8, /* [16: 9] units=dBm */
  11804. nss : 2, /* [18:17] if nss 1 means 1ss and 2 means 2ss */
  11805. bw : 3, /* [21:19] (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) */
  11806. stbc : 1, /* [22] */
  11807. sgi : 1, /* [23] */
  11808. ldpc : 1, /* [24] */
  11809. beamformed: 1, /* [25] */
  11810. reserved_2: 6; /* [31:26] */
  11811. A_UINT32 /* word 3 */
  11812. framectrl:16, /* [15: 0] */
  11813. seqno:16; /* [31:16] */
  11814. A_UINT32 /* word 4 */
  11815. tid_num:5, /* [ 4: 0] actual TID number */
  11816. vdev_id:8, /* [12: 5] */
  11817. reserved_3:19; /* [31:13] */
  11818. A_UINT32 /* word 5 */
  11819. /* status:
  11820. * 0: tx_ok
  11821. * 1: retry
  11822. * 2: drop
  11823. * 3: filtered
  11824. * 4: abort
  11825. * 5: tid delete
  11826. * 6: sw abort
  11827. * 7: dropped by peer migration
  11828. */
  11829. status:3, /* [2:0] */
  11830. format:1, /* [3] 0: 802.3 format, 1: 802.11 format */
  11831. tx_mpdu_bytes:16, /* [19:4] */
  11832. /* Indicates retry count of offloaded/local generated Data tx frames */
  11833. tx_retry_cnt:6, /* [25:20] */
  11834. reserved_4:6; /* [31:26] */
  11835. } POSTPACK;
  11836. /* FW offload deliver ind message header fields */
  11837. /* DWORD one */
  11838. #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_M 0xffffffff
  11839. #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S 0
  11840. /* DWORD two */
  11841. #define HTT_FW_OFFLOAD_IND_PREAMBLE_M 0x00000003
  11842. #define HTT_FW_OFFLOAD_IND_PREAMBLE_S 0
  11843. #define HTT_FW_OFFLOAD_IND_MCS_M 0x0000003c
  11844. #define HTT_FW_OFFLOAD_IND_MCS_S 2
  11845. #define HTT_FW_OFFLOAD_IND_RATE_M 0x000001c0
  11846. #define HTT_FW_OFFLOAD_IND_RATE_S 6
  11847. #define HTT_FW_OFFLOAD_IND_RSSI_M 0x0001fe00
  11848. #define HTT_FW_OFFLOAD_IND_RSSI_S 9
  11849. #define HTT_FW_OFFLOAD_IND_NSS_M 0x00060000
  11850. #define HTT_FW_OFFLOAD_IND_NSS_S 17
  11851. #define HTT_FW_OFFLOAD_IND_BW_M 0x00380000
  11852. #define HTT_FW_OFFLOAD_IND_BW_S 19
  11853. #define HTT_FW_OFFLOAD_IND_STBC_M 0x00400000
  11854. #define HTT_FW_OFFLOAD_IND_STBC_S 22
  11855. #define HTT_FW_OFFLOAD_IND_SGI_M 0x00800000
  11856. #define HTT_FW_OFFLOAD_IND_SGI_S 23
  11857. #define HTT_FW_OFFLOAD_IND_LDPC_M 0x01000000
  11858. #define HTT_FW_OFFLOAD_IND_LDPC_S 24
  11859. #define HTT_FW_OFFLOAD_IND_BEAMFORMED_M 0x02000000
  11860. #define HTT_FW_OFFLOAD_IND_BEAMFORMED_S 25
  11861. /* DWORD three*/
  11862. #define HTT_FW_OFFLOAD_IND_FRAMECTRL_M 0x0000ffff
  11863. #define HTT_FW_OFFLOAD_IND_FRAMECTRL_S 0
  11864. #define HTT_FW_OFFLOAD_IND_SEQNO_M 0xffff0000
  11865. #define HTT_FW_OFFLOAD_IND_SEQNO_S 16
  11866. /* DWORD four */
  11867. #define HTT_FW_OFFLOAD_IND_TID_NUM_M 0x0000001f
  11868. #define HTT_FW_OFFLOAD_IND_TID_NUM_S 0
  11869. #define HTT_FW_OFFLOAD_IND_VDEV_ID_M 0x00001fe0
  11870. #define HTT_FW_OFFLOAD_IND_VDEV_ID_S 5
  11871. /* DWORD five */
  11872. #define HTT_FW_OFFLOAD_IND_STATUS_M 0x00000007
  11873. #define HTT_FW_OFFLOAD_IND_STATUS_S 0
  11874. #define HTT_FW_OFFLOAD_IND_FORMAT_M 0x00000008
  11875. #define HTT_FW_OFFLOAD_IND_FORMAT_S 3
  11876. #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_M 0x000ffff0
  11877. #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S 4
  11878. #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_M 0x03f00000
  11879. #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S 20
  11880. #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_SET(word, value) \
  11881. do { \
  11882. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32, value); \
  11883. (word) |= (value) << HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S; \
  11884. } while (0)
  11885. #define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_GET(word) \
  11886. (((word) & HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_M) >> HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S)
  11887. #define HTT_FW_OFFLOAD_IND_PREAMBLE_SET(word, value) \
  11888. do { \
  11889. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_PREAMBLE, value); \
  11890. (word) |= (value) << HTT_FW_OFFLOAD_IND_PREAMBLE_S; \
  11891. } while (0)
  11892. #define HTT_FW_OFFLOAD_IND_PREAMBLE_GET(word) \
  11893. (((word) & HTT_FW_OFFLOAD_IND_PREAMBLE_M) >> HTT_FW_OFFLOAD_IND_PREAMBLE_S)
  11894. #define HTT_FW_OFFLOAD_IND_MCS_SET(word, value) \
  11895. do { \
  11896. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_MCS, value); \
  11897. (word) |= (value) << HTT_FW_OFFLOAD_IND_MCS_S; \
  11898. } while (0)
  11899. #define HTT_FW_OFFLOAD_IND_MCS_GET(word) \
  11900. (((word) & HTT_FW_OFFLOAD_IND_MCS_M) >> HTT_FW_OFFLOAD_IND_MCS_S)
  11901. #define HTT_FW_OFFLOAD_IND_RATE_SET(word, value) \
  11902. do { \
  11903. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_RATE, value); \
  11904. (word) |= (value) << HTT_FW_OFFLOAD_IND_RATE_S; \
  11905. } while (0)
  11906. #define HTT_FW_OFFLOAD_IND_RATE_GET(word) \
  11907. (((word) & HTT_FW_OFFLOAD_IND_RATE_M) >> HTT_FW_OFFLOAD_IND_RATE_S)
  11908. #define HTT_FW_OFFLOAD_IND_RSSI_SET(word, value) \
  11909. do { \
  11910. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_RSSI, value); \
  11911. (word) |= (value) << HTT_FW_OFFLOAD_IND_RSSI_S; \
  11912. } while (0)
  11913. #define HTT_FW_OFFLOAD_IND_RSSI_GET(word) \
  11914. (((word) & HTT_FW_OFFLOAD_IND_RSSI_M) >> HTT_FW_OFFLOAD_IND_RSSI_S)
  11915. #define HTT_FW_OFFLOAD_IND_NSS_SET(word, value) \
  11916. do { \
  11917. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_NSS, value); \
  11918. (word) |= (value) << HTT_FW_OFFLOAD_IND_NSS_S; \
  11919. } while (0)
  11920. #define HTT_FW_OFFLOAD_IND_NSS_GET(word) \
  11921. (((word) & HTT_FW_OFFLOAD_IND_NSS_M) >> HTT_FW_OFFLOAD_IND_NSS_S)
  11922. #define HTT_FW_OFFLOAD_IND_BW_SET(word, value) \
  11923. do { \
  11924. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_BW, value); \
  11925. (word) |= (value) << HTT_FW_OFFLOAD_IND_BW_S; \
  11926. } while (0)
  11927. #define HTT_FW_OFFLOAD_IND_BW_GET(word) \
  11928. (((word) & HTT_FW_OFFLOAD_IND_BW_M) >> HTT_FW_OFFLOAD_IND_BW_S)
  11929. #define HTT_FW_OFFLOAD_IND_STBC_SET(word, value) \
  11930. do { \
  11931. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_STBC, value); \
  11932. (word) |= (value) << HTT_FW_OFFLOAD_IND_STBC_S; \
  11933. } while (0)
  11934. #define HTT_FW_OFFLOAD_IND_STBC_GET(word) \
  11935. (((word) & HTT_FW_OFFLOAD_IND_STBC_M) >> HTT_FW_OFFLOAD_IND_STBC_S)
  11936. #define HTT_FW_OFFLOAD_IND_SGI_SET(word, value) \
  11937. do { \
  11938. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_SGI, value); \
  11939. (word) |= (value) << HTT_FW_OFFLOAD_IND_SGI_S; \
  11940. } while (0)
  11941. #define HTT_FW_OFFLOAD_IND_SGI_GET(word) \
  11942. (((word) & HTT_FW_OFFLOAD_IND_SGI_M) >> HTT_FW_OFFLOAD_IND_SGI_S)
  11943. #define HTT_FW_OFFLOAD_IND_LDPC_SET(word, value) \
  11944. do { \
  11945. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_LDPC, value); \
  11946. (word) |= (value) << HTT_FW_OFFLOAD_IND_LDPC_S; \
  11947. } while (0)
  11948. #define HTT_FW_OFFLOAD_IND_LDPC_GET(word) \
  11949. (((word) & HTT_FW_OFFLOAD_IND_LDPC_M) >> HTT_FW_OFFLOAD_IND_LDPC_S)
  11950. #define HTT_FW_OFFLOAD_IND_BEAMFORMED_SET(word, value) \
  11951. do { \
  11952. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_BEAMFORMED, value); \
  11953. (word) |= (value) << HTT_FW_OFFLOAD_IND_BEAMFORMED_S; \
  11954. } while (0)
  11955. #define HTT_FW_OFFLOAD_IND_BEAMFORMED_GET(word) \
  11956. (((word) & HTT_FW_OFFLOAD_IND_BEAMFORMED_M) >> HTT_FW_OFFLOAD_IND_BEAMFORMED_S)
  11957. #define HTT_FW_OFFLOAD_IND_FRAMECTRL_SET(word, value) \
  11958. do { \
  11959. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_FRAMECTRL, value); \
  11960. (word) |= (value) << HTT_FW_OFFLOAD_IND_FRAMECTRL_S; \
  11961. } while (0)
  11962. #define HTT_FW_OFFLOAD_IND_FRAMECTRL_GET(word) \
  11963. (((word) & HTT_FW_OFFLOAD_IND_FRAMECTRL_M) >> HTT_FW_OFFLOAD_IND_FRAMECTRL_S)
  11964. #define HTT_FW_OFFLOAD_IND_SEQNO_SET(word, value) \
  11965. do { \
  11966. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_SEQNO, value); \
  11967. (word) |= (value) << HTT_FW_OFFLOAD_IND_SEQNO_S; \
  11968. } while (0)
  11969. #define HTT_FW_OFFLOAD_IND_SEQNO_GET(word) \
  11970. (((word) & HTT_FW_OFFLOAD_IND_SEQNO_M) >> HTT_FW_OFFLOAD_IND_SEQNO_S)
  11971. #define HTT_FW_OFFLOAD_IND_TID_NUM_SET(word, value) \
  11972. do { \
  11973. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TID_NUM, value); \
  11974. (word) |= (value) << HTT_FW_OFFLOAD_IND_TID_NUM_S; \
  11975. } while (0)
  11976. #define HTT_FW_OFFLOAD_IND_TID_NUM_GET(word) \
  11977. (((word) & HTT_FW_OFFLOAD_IND_TID_NUM_M) >> HTT_FW_OFFLOAD_IND_TID_NUM_S)
  11978. #define HTT_FW_OFFLOAD_IND_VDEV_ID_SET(word, value) \
  11979. do { \
  11980. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_VDEV_ID, value); \
  11981. (word) |= (value) << HTT_FW_OFFLOAD_IND_VDEV_ID_S; \
  11982. } while (0)
  11983. #define HTT_FW_OFFLOAD_IND_VDEV_ID_GET(word) \
  11984. (((word) & HTT_FW_OFFLOAD_IND_VDEV_ID_M) >> HTT_FW_OFFLOAD_IND_VDEV_ID_S)
  11985. #define HTT_FW_OFFLOAD_IND_STATUS_SET(word, value) \
  11986. do { \
  11987. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_STATUS, value); \
  11988. (word) |= (value) << HTT_FW_OFFLOAD_IND_STATUS_S; \
  11989. } while (0)
  11990. #define HTT_FW_OFFLOAD_IND_STATUS_GET(word) \
  11991. (((word) & HTT_FW_OFFLOAD_IND_STATUS_M) >> HTT_FW_OFFLOAD_IND_STATUS_M)
  11992. #define HTT_FW_OFFLOAD_IND_FORMAT_SET(word, value) \
  11993. do { \
  11994. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_FORMAT, value); \
  11995. (word) |= (value) << HTT_FW_OFFLOAD_IND_FORMAT_S; \
  11996. } while (0)
  11997. #define HTT_FW_OFFLOAD_IND_FORMAT_GET(word) \
  11998. (((word) & HTT_FW_OFFLOAD_IND_FORMAT_M) >> HTT_FW_OFFLOAD_IND_FORMAT_S)
  11999. #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_SET(word, value) \
  12000. do { \
  12001. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES, value); \
  12002. (word) |= (value) << HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S; \
  12003. } while (0)
  12004. #define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_GET(word) \
  12005. (((word) & HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_M) >> HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S)
  12006. #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_SET(word, value) \
  12007. do { \
  12008. HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TX_RETRY_CNT, value); \
  12009. (word) |= (value) << HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S; \
  12010. } while (0)
  12011. #define HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_GET(word) \
  12012. (((word) & HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_M) >> HTT_FW_OFFLOAD_IND_TX_RETRY_CNT_S)
  12013. /*
  12014. * @brief target -> host rx reorder flush message definition
  12015. *
  12016. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_FLUSH
  12017. *
  12018. * @details
  12019. * The following field definitions describe the format of the rx flush
  12020. * message sent from the target to the host.
  12021. * The message consists of a 4-octet header, followed by one or more
  12022. * 4-octet payload information elements.
  12023. *
  12024. * |31 24|23 8|7 0|
  12025. * |--------------------------------------------------------------|
  12026. * | TID | peer ID | msg type |
  12027. * |--------------------------------------------------------------|
  12028. * | seq num end | seq num start | MPDU status | reserved |
  12029. * |--------------------------------------------------------------|
  12030. * First DWORD:
  12031. * - MSG_TYPE
  12032. * Bits 7:0
  12033. * Purpose: identifies this as an rx flush message
  12034. * Value: 0x2 (HTT_T2H_MSG_TYPE_RX_FLUSH)
  12035. * - PEER_ID
  12036. * Bits 23:8 (only bits 18:8 actually used)
  12037. * Purpose: identify which peer's rx data is being flushed
  12038. * Value: (rx) peer ID
  12039. * - TID
  12040. * Bits 31:24 (only bits 27:24 actually used)
  12041. * Purpose: Specifies which traffic identifier's rx data is being flushed
  12042. * Value: traffic identifier
  12043. * Second DWORD:
  12044. * - MPDU_STATUS
  12045. * Bits 15:8
  12046. * Purpose:
  12047. * Indicate whether the flushed MPDUs should be discarded or processed.
  12048. * Value:
  12049. * 0x1: send the MPDUs from the rx reorder buffer to subsequent
  12050. * stages of rx processing
  12051. * other: discard the MPDUs
  12052. * It is anticipated that flush messages will always have
  12053. * MPDU status == 1, but the status flag is included for
  12054. * flexibility.
  12055. * - SEQ_NUM_START
  12056. * Bits 23:16
  12057. * Purpose:
  12058. * Indicate the start of a series of consecutive MPDUs being flushed.
  12059. * Not all MPDUs within this range are necessarily valid - the host
  12060. * must check each sequence number within this range to see if the
  12061. * corresponding MPDU is actually present.
  12062. * Value:
  12063. * The sequence number for the first MPDU in the sequence.
  12064. * This sequence number is the 6 LSBs of the 802.11 sequence number.
  12065. * - SEQ_NUM_END
  12066. * Bits 30:24
  12067. * Purpose:
  12068. * Indicate the end of a series of consecutive MPDUs being flushed.
  12069. * Value:
  12070. * The sequence number one larger than the sequence number of the
  12071. * last MPDU being flushed.
  12072. * This sequence number is the 6 LSBs of the 802.11 sequence number.
  12073. * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] inclusive
  12074. * are to be released for further rx processing.
  12075. * Not all MPDUs within this range are necessarily valid - the host
  12076. * must check each sequence number within this range to see if the
  12077. * corresponding MPDU is actually present.
  12078. */
  12079. /* first DWORD */
  12080. #define HTT_RX_FLUSH_PEER_ID_M 0xffff00
  12081. #define HTT_RX_FLUSH_PEER_ID_S 8
  12082. #define HTT_RX_FLUSH_TID_M 0xff000000
  12083. #define HTT_RX_FLUSH_TID_S 24
  12084. /* second DWORD */
  12085. #define HTT_RX_FLUSH_MPDU_STATUS_M 0x0000ff00
  12086. #define HTT_RX_FLUSH_MPDU_STATUS_S 8
  12087. #define HTT_RX_FLUSH_SEQ_NUM_START_M 0x00ff0000
  12088. #define HTT_RX_FLUSH_SEQ_NUM_START_S 16
  12089. #define HTT_RX_FLUSH_SEQ_NUM_END_M 0xff000000
  12090. #define HTT_RX_FLUSH_SEQ_NUM_END_S 24
  12091. #define HTT_RX_FLUSH_BYTES 8
  12092. #define HTT_RX_FLUSH_PEER_ID_SET(word, value) \
  12093. do { \
  12094. HTT_CHECK_SET_VAL(HTT_RX_FLUSH_PEER_ID, value); \
  12095. (word) |= (value) << HTT_RX_FLUSH_PEER_ID_S; \
  12096. } while (0)
  12097. #define HTT_RX_FLUSH_PEER_ID_GET(word) \
  12098. (((word) & HTT_RX_FLUSH_PEER_ID_M) >> HTT_RX_FLUSH_PEER_ID_S)
  12099. #define HTT_RX_FLUSH_TID_SET(word, value) \
  12100. do { \
  12101. HTT_CHECK_SET_VAL(HTT_RX_FLUSH_TID, value); \
  12102. (word) |= (value) << HTT_RX_FLUSH_TID_S; \
  12103. } while (0)
  12104. #define HTT_RX_FLUSH_TID_GET(word) \
  12105. (((word) & HTT_RX_FLUSH_TID_M) >> HTT_RX_FLUSH_TID_S)
  12106. #define HTT_RX_FLUSH_MPDU_STATUS_SET(word, value) \
  12107. do { \
  12108. HTT_CHECK_SET_VAL(HTT_RX_FLUSH_MPDU_STATUS, value); \
  12109. (word) |= (value) << HTT_RX_FLUSH_MPDU_STATUS_S; \
  12110. } while (0)
  12111. #define HTT_RX_FLUSH_MPDU_STATUS_GET(word) \
  12112. (((word) & HTT_RX_FLUSH_MPDU_STATUS_M) >> HTT_RX_FLUSH_MPDU_STATUS_S)
  12113. #define HTT_RX_FLUSH_SEQ_NUM_START_SET(word, value) \
  12114. do { \
  12115. HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_START, value); \
  12116. (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_START_S; \
  12117. } while (0)
  12118. #define HTT_RX_FLUSH_SEQ_NUM_START_GET(word) \
  12119. (((word) & HTT_RX_FLUSH_SEQ_NUM_START_M) >> HTT_RX_FLUSH_SEQ_NUM_START_S)
  12120. #define HTT_RX_FLUSH_SEQ_NUM_END_SET(word, value) \
  12121. do { \
  12122. HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_END, value); \
  12123. (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_END_S; \
  12124. } while (0)
  12125. #define HTT_RX_FLUSH_SEQ_NUM_END_GET(word) \
  12126. (((word) & HTT_RX_FLUSH_SEQ_NUM_END_M) >> HTT_RX_FLUSH_SEQ_NUM_END_S)
  12127. /*
  12128. * @brief target -> host rx pn check indication message
  12129. *
  12130. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_PN_IND
  12131. *
  12132. * @details
  12133. * The following field definitions describe the format of the Rx PN check
  12134. * indication message sent from the target to the host.
  12135. * The message consists of a 4-octet header, followed by the start and
  12136. * end sequence numbers to be released, followed by the PN IEs. Each PN
  12137. * IE is one octet containing the sequence number that failed the PN
  12138. * check.
  12139. *
  12140. * |31 24|23 8|7 0|
  12141. * |--------------------------------------------------------------|
  12142. * | TID | peer ID | msg type |
  12143. * |--------------------------------------------------------------|
  12144. * | Reserved | PN IE count | seq num end | seq num start|
  12145. * |--------------------------------------------------------------|
  12146. * l : PN IE 2 | PN IE 1 | PN IE 0 |
  12147. * |--------------------------------------------------------------|
  12148. * First DWORD:
  12149. * - MSG_TYPE
  12150. * Bits 7:0
  12151. * Purpose: Identifies this as an rx pn check indication message
  12152. * Value: 0x10 (HTT_T2H_MSG_TYPE_RX_PN_IND)
  12153. * - PEER_ID
  12154. * Bits 23:8 (only bits 18:8 actually used)
  12155. * Purpose: identify which peer
  12156. * Value: (rx) peer ID
  12157. * - TID
  12158. * Bits 31:24 (only bits 27:24 actually used)
  12159. * Purpose: identify traffic identifier
  12160. * Value: traffic identifier
  12161. * Second DWORD:
  12162. * - SEQ_NUM_START
  12163. * Bits 7:0
  12164. * Purpose:
  12165. * Indicates the starting sequence number of the MPDU in this
  12166. * series of MPDUs that went though PN check.
  12167. * Value:
  12168. * The sequence number for the first MPDU in the sequence.
  12169. * This sequence number is the 6 LSBs of the 802.11 sequence number.
  12170. * - SEQ_NUM_END
  12171. * Bits 15:8
  12172. * Purpose:
  12173. * Indicates the ending sequence number of the MPDU in this
  12174. * series of MPDUs that went though PN check.
  12175. * Value:
  12176. * The sequence number one larger then the sequence number of the last
  12177. * MPDU being flushed.
  12178. * This sequence number is the 6 LSBs of the 802.11 sequence number.
  12179. * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] have been checked
  12180. * for invalid PN numbers and are ready to be released for further processing.
  12181. * Not all MPDUs within this range are necessarily valid - the host
  12182. * must check each sequence number within this range to see if the
  12183. * corresponding MPDU is actually present.
  12184. * - PN_IE_COUNT
  12185. * Bits 23:16
  12186. * Purpose:
  12187. * Used to determine the variable number of PN information elements in this
  12188. * message
  12189. *
  12190. * PN information elements:
  12191. * - PN_IE_x-
  12192. * Purpose:
  12193. * Each PN information element contains the sequence number of the MPDU that
  12194. * has failed the target PN check.
  12195. * Value:
  12196. * Contains the 6 LSBs of the 802.11 sequence number corresponding to the MPDU
  12197. * that failed the PN check.
  12198. */
  12199. /* first DWORD */
  12200. #define HTT_RX_PN_IND_PEER_ID_M 0xffff00
  12201. #define HTT_RX_PN_IND_PEER_ID_S 8
  12202. #define HTT_RX_PN_IND_TID_M 0xff000000
  12203. #define HTT_RX_PN_IND_TID_S 24
  12204. /* second DWORD */
  12205. #define HTT_RX_PN_IND_SEQ_NUM_START_M 0x000000ff
  12206. #define HTT_RX_PN_IND_SEQ_NUM_START_S 0
  12207. #define HTT_RX_PN_IND_SEQ_NUM_END_M 0x0000ff00
  12208. #define HTT_RX_PN_IND_SEQ_NUM_END_S 8
  12209. #define HTT_RX_PN_IND_PN_IE_CNT_M 0x00ff0000
  12210. #define HTT_RX_PN_IND_PN_IE_CNT_S 16
  12211. #define HTT_RX_PN_IND_BYTES 8
  12212. #define HTT_RX_PN_IND_PEER_ID_SET(word, value) \
  12213. do { \
  12214. HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PEER_ID, value); \
  12215. (word) |= (value) << HTT_RX_PN_IND_PEER_ID_S; \
  12216. } while (0)
  12217. #define HTT_RX_PN_IND_PEER_ID_GET(word) \
  12218. (((word) & HTT_RX_PN_IND_PEER_ID_M) >> HTT_RX_PN_IND_PEER_ID_S)
  12219. #define HTT_RX_PN_IND_EXT_TID_SET(word, value) \
  12220. do { \
  12221. HTT_CHECK_SET_VAL(HTT_RX_PN_IND_TID, value); \
  12222. (word) |= (value) << HTT_RX_PN_IND_TID_S; \
  12223. } while (0)
  12224. #define HTT_RX_PN_IND_EXT_TID_GET(word) \
  12225. (((word) & HTT_RX_PN_IND_TID_M) >> HTT_RX_PN_IND_TID_S)
  12226. #define HTT_RX_PN_IND_SEQ_NUM_START_SET(word, value) \
  12227. do { \
  12228. HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_START, value); \
  12229. (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_START_S; \
  12230. } while (0)
  12231. #define HTT_RX_PN_IND_SEQ_NUM_START_GET(word) \
  12232. (((word) & HTT_RX_PN_IND_SEQ_NUM_START_M) >> HTT_RX_PN_IND_SEQ_NUM_START_S)
  12233. #define HTT_RX_PN_IND_SEQ_NUM_END_SET(word, value) \
  12234. do { \
  12235. HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_END, value); \
  12236. (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_END_S; \
  12237. } while (0)
  12238. #define HTT_RX_PN_IND_SEQ_NUM_END_GET(word) \
  12239. (((word) & HTT_RX_PN_IND_SEQ_NUM_END_M) >> HTT_RX_PN_IND_SEQ_NUM_END_S)
  12240. #define HTT_RX_PN_IND_PN_IE_CNT_SET(word, value) \
  12241. do { \
  12242. HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PN_IE_CNT, value); \
  12243. (word) |= (value) << HTT_RX_PN_IND_PN_IE_CNT_S; \
  12244. } while (0)
  12245. #define HTT_RX_PN_IND_PN_IE_CNT_GET(word) \
  12246. (((word) & HTT_RX_PN_IND_PN_IE_CNT_M) >> HTT_RX_PN_IND_PN_IE_CNT_S)
  12247. /*
  12248. * @brief target -> host rx offload deliver message for LL system
  12249. *
  12250. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND
  12251. *
  12252. * @details
  12253. * In a low latency system this message is sent whenever the offload
  12254. * manager flushes out the packets it has coalesced in its coalescing buffer.
  12255. * The DMA of the actual packets into host memory is done before sending out
  12256. * this message. This message indicates only how many MSDUs to reap. The
  12257. * peer ID, vdev ID, tid and MSDU length are copied inline into the header
  12258. * portion of the MSDU while DMA'ing into the host memory. Unlike the packets
  12259. * DMA'd by the MAC directly into host memory these packets do not contain
  12260. * the MAC descriptors in the header portion of the packet. Instead they contain
  12261. * the peer ID, vdev ID, tid and MSDU length. Also when the host receives this
  12262. * message, the packets are delivered directly to the NW stack without going
  12263. * through the regular reorder buffering and PN checking path since it has
  12264. * already been done in target.
  12265. *
  12266. * |31 24|23 16|15 8|7 0|
  12267. * |-----------------------------------------------------------------------|
  12268. * | Total MSDU count | reserved | msg type |
  12269. * |-----------------------------------------------------------------------|
  12270. *
  12271. * @brief target -> host rx offload deliver message for HL system
  12272. *
  12273. * @details
  12274. * In a high latency system this message is sent whenever the offload manager
  12275. * flushes out the packets it has coalesced in its coalescing buffer. The
  12276. * actual packets are also carried along with this message. When the host
  12277. * receives this message, it is expected to deliver these packets to the NW
  12278. * stack directly instead of routing them through the reorder buffering and
  12279. * PN checking path since it has already been done in target.
  12280. *
  12281. * |31 24|23 16|15 8|7 0|
  12282. * |-----------------------------------------------------------------------|
  12283. * | Total MSDU count | reserved | msg type |
  12284. * |-----------------------------------------------------------------------|
  12285. * | peer ID | MSDU length |
  12286. * |-----------------------------------------------------------------------|
  12287. * | MSDU payload | FW Desc | tid | vdev ID |
  12288. * |-----------------------------------------------------------------------|
  12289. * | MSDU payload contd. |
  12290. * |-----------------------------------------------------------------------|
  12291. * | peer ID | MSDU length |
  12292. * |-----------------------------------------------------------------------|
  12293. * | MSDU payload | FW Desc | tid | vdev ID |
  12294. * |-----------------------------------------------------------------------|
  12295. * | MSDU payload contd. |
  12296. * |-----------------------------------------------------------------------|
  12297. *
  12298. */
  12299. /* first DWORD */
  12300. #define HTT_RX_OFFLOAD_DELIVER_IND_HDR_BYTES 4
  12301. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_HDR_BYTES 7
  12302. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M 0xffff0000
  12303. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S 16
  12304. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M 0x0000ffff
  12305. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S 0
  12306. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M 0xffff0000
  12307. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S 16
  12308. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M 0x000000ff
  12309. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S 0
  12310. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M 0x0000ff00
  12311. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S 8
  12312. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M 0x00ff0000
  12313. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S 16
  12314. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_GET(word) \
  12315. (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S)
  12316. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_SET(word, value) \
  12317. do { \
  12318. HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT, value); \
  12319. (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S; \
  12320. } while (0)
  12321. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_GET(word) \
  12322. (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S)
  12323. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_SET(word, value) \
  12324. do { \
  12325. HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN, value); \
  12326. (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S; \
  12327. } while (0)
  12328. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_GET(word) \
  12329. (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S)
  12330. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_SET(word, value) \
  12331. do { \
  12332. HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID, value); \
  12333. (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S; \
  12334. } while (0)
  12335. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_GET(word) \
  12336. (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S)
  12337. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_SET(word, value) \
  12338. do { \
  12339. HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID, value); \
  12340. (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S; \
  12341. } while (0)
  12342. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_GET(word) \
  12343. (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S)
  12344. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_SET(word, value) \
  12345. do { \
  12346. HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID, value); \
  12347. (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S; \
  12348. } while (0)
  12349. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_GET(word) \
  12350. (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S)
  12351. #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_SET(word, value) \
  12352. do { \
  12353. HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC, value); \
  12354. (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S; \
  12355. } while (0)
  12356. /**
  12357. * @brief target -> host rx peer map/unmap message definition
  12358. *
  12359. * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP
  12360. *
  12361. * @details
  12362. * The following diagram shows the format of the rx peer map message sent
  12363. * from the target to the host. This layout assumes the target operates
  12364. * as little-endian.
  12365. *
  12366. * This message always contains a SW peer ID. The main purpose of the
  12367. * SW peer ID is to tell the host what peer ID rx packets will be tagged
  12368. * with, so that the host can use that peer ID to determine which peer
  12369. * transmitted the rx frame. This SW peer ID is sometimes also used for
  12370. * other purposes, such as identifying during tx completions which peer
  12371. * the tx frames in question were transmitted to.
  12372. *
  12373. * In certain generations of chips, the peer map message also contains
  12374. * a HW peer ID. This HW peer ID is used during rx --> tx frame forwarding
  12375. * to identify which peer the frame needs to be forwarded to (i.e. the
  12376. * peer associated with the Destination MAC Address within the packet),
  12377. * and particularly which vdev needs to transmit the frame (for cases
  12378. * of inter-vdev rx --> tx forwarding). The HW peer id here is the same
  12379. * meaning as AST_INDEX_0.
  12380. * This DA-based peer ID that is provided for certain rx frames
  12381. * (the rx frames that need to be re-transmitted as tx frames)
  12382. * is the ID that the HW uses for referring to the peer in question,
  12383. * rather than the peer ID that the SW+FW use to refer to the peer.
  12384. *
  12385. *
  12386. * |31 24|23 16|15 8|7 0|
  12387. * |-----------------------------------------------------------------------|
  12388. * | SW peer ID | VDEV ID | msg type |
  12389. * |-----------------------------------------------------------------------|
  12390. * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
  12391. * |-----------------------------------------------------------------------|
  12392. * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 |
  12393. * |-----------------------------------------------------------------------|
  12394. *
  12395. *
  12396. * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_UNMAP
  12397. *
  12398. * The following diagram shows the format of the rx peer unmap message sent
  12399. * from the target to the host.
  12400. *
  12401. * |31 24|23 16|15 8|7 0|
  12402. * |-----------------------------------------------------------------------|
  12403. * | SW peer ID | VDEV ID | msg type |
  12404. * |-----------------------------------------------------------------------|
  12405. *
  12406. * The following field definitions describe the format of the rx peer map
  12407. * and peer unmap messages sent from the target to the host.
  12408. * - MSG_TYPE
  12409. * Bits 7:0
  12410. * Purpose: identifies this as an rx peer map or peer unmap message
  12411. * Value: peer map -> 0x3 (HTT_T2H_MSG_TYPE_PEER_MAP),
  12412. * peer unmap -> 0x4 (HTT_T2H_MSG_TYPE_PEER_UNMAP)
  12413. * - VDEV_ID
  12414. * Bits 15:8
  12415. * Purpose: Indicates which virtual device the peer is associated
  12416. * with.
  12417. * Value: vdev ID (used in the host to look up the vdev object)
  12418. * - PEER_ID (a.k.a. SW_PEER_ID)
  12419. * Bits 31:16
  12420. * Purpose: The peer ID (index) that WAL is allocating (map) or
  12421. * freeing (unmap)
  12422. * Value: (rx) peer ID
  12423. * - MAC_ADDR_L32 (peer map only)
  12424. * Bits 31:0
  12425. * Purpose: Identifies which peer node the peer ID is for.
  12426. * Value: lower 4 bytes of peer node's MAC address
  12427. * - MAC_ADDR_U16 (peer map only)
  12428. * Bits 15:0
  12429. * Purpose: Identifies which peer node the peer ID is for.
  12430. * Value: upper 2 bytes of peer node's MAC address
  12431. * - HW_PEER_ID
  12432. * Bits 31:16
  12433. * Purpose: Identifies the HW peer ID corresponding to the peer MAC
  12434. * address, so for rx frames marked for rx --> tx forwarding, the
  12435. * host can determine from the HW peer ID provided as meta-data with
  12436. * the rx frame which peer the frame is supposed to be forwarded to.
  12437. * Value: ID used by the MAC HW to identify the peer
  12438. */
  12439. #define HTT_RX_PEER_MAP_VDEV_ID_M 0xff00
  12440. #define HTT_RX_PEER_MAP_VDEV_ID_S 8
  12441. #define HTT_RX_PEER_MAP_PEER_ID_M 0xffff0000
  12442. #define HTT_RX_PEER_MAP_PEER_ID_S 16
  12443. #define HTT_RX_PEER_MAP_SW_PEER_ID_M HTT_RX_PEER_MAP_PEER_ID_M /* alias */
  12444. #define HTT_RX_PEER_MAP_SW_PEER_ID_S HTT_RX_PEER_MAP_PEER_ID_S /* alias */
  12445. #define HTT_RX_PEER_MAP_MAC_ADDR_L32_M 0xffffffff
  12446. #define HTT_RX_PEER_MAP_MAC_ADDR_L32_S 0
  12447. #define HTT_RX_PEER_MAP_MAC_ADDR_U16_M 0xffff
  12448. #define HTT_RX_PEER_MAP_MAC_ADDR_U16_S 0
  12449. #define HTT_RX_PEER_MAP_HW_PEER_ID_M 0xffff0000
  12450. #define HTT_RX_PEER_MAP_HW_PEER_ID_S 16
  12451. #define HTT_RX_PEER_MAP_VAP_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET /* deprecated */
  12452. #define HTT_RX_PEER_MAP_VDEV_ID_SET(word, value) \
  12453. do { \
  12454. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_VDEV_ID, value); \
  12455. (word) |= (value) << HTT_RX_PEER_MAP_VDEV_ID_S; \
  12456. } while (0)
  12457. #define HTT_RX_PEER_MAP_VAP_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET /* deprecated */
  12458. #define HTT_RX_PEER_MAP_VDEV_ID_GET(word) \
  12459. (((word) & HTT_RX_PEER_MAP_VDEV_ID_M) >> HTT_RX_PEER_MAP_VDEV_ID_S)
  12460. #define HTT_RX_PEER_MAP_PEER_ID_SET(word, value) \
  12461. do { \
  12462. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \
  12463. (word) |= (value) << HTT_RX_PEER_MAP_PEER_ID_S; \
  12464. } while (0)
  12465. #define HTT_RX_PEER_MAP_PEER_ID_GET(word) \
  12466. (((word) & HTT_RX_PEER_MAP_PEER_ID_M) >> HTT_RX_PEER_MAP_PEER_ID_S)
  12467. #define HTT_RX_PEER_MAP_SW_PEER_ID_SET HTT_RX_PEER_MAP_PEER_ID_SET /* alias */
  12468. #define HTT_RX_PEER_MAP_SW_PEER_ID_GET HTT_RX_PEER_MAP_PEER_ID_GET /* alias */
  12469. #define HTT_RX_PEER_MAP_HW_PEER_ID_SET(word, value) \
  12470. do { \
  12471. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_HW_PEER_ID, value); \
  12472. (word) |= (value) << HTT_RX_PEER_MAP_HW_PEER_ID_S; \
  12473. } while (0)
  12474. #define HTT_RX_PEER_MAP_HW_PEER_ID_GET(word) \
  12475. (((word) & HTT_RX_PEER_MAP_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_HW_PEER_ID_S)
  12476. #define HTT_RX_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */
  12477. #define HTT_RX_PEER_MAP_HW_PEER_ID_OFFSET 8 /* bytes */
  12478. #define HTT_RX_PEER_MAP_BYTES 12
  12479. #define HTT_RX_PEER_UNMAP_PEER_ID_M HTT_RX_PEER_MAP_PEER_ID_M
  12480. #define HTT_RX_PEER_UNMAP_PEER_ID_S HTT_RX_PEER_MAP_PEER_ID_S
  12481. #define HTT_RX_PEER_UNMAP_SW_PEER_ID_M HTT_RX_PEER_MAP_SW_PEER_ID_M
  12482. #define HTT_RX_PEER_UNMAP_SW_PEER_ID_S HTT_RX_PEER_MAP_SW_PEER_ID_S
  12483. #define HTT_RX_PEER_UNMAP_PEER_ID_SET HTT_RX_PEER_MAP_PEER_ID_SET
  12484. #define HTT_RX_PEER_UNMAP_PEER_ID_GET HTT_RX_PEER_MAP_PEER_ID_GET
  12485. #define HTT_RX_PEER_UNMAP_VDEV_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET
  12486. #define HTT_RX_PEER_UNMAP_VDEV_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET
  12487. #define HTT_RX_PEER_UNMAP_BYTES 4
  12488. /**
  12489. * @brief target -> host rx peer map V2 message definition
  12490. *
  12491. * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP_V2
  12492. *
  12493. * @details
  12494. * The following diagram shows the format of the rx peer map v2 message sent
  12495. * from the target to the host. This layout assumes the target operates
  12496. * as little-endian.
  12497. *
  12498. * This message always contains a SW peer ID. The main purpose of the
  12499. * SW peer ID is to tell the host what peer ID rx packets will be tagged
  12500. * with, so that the host can use that peer ID to determine which peer
  12501. * transmitted the rx frame. This SW peer ID is sometimes also used for
  12502. * other purposes, such as identifying during tx completions which peer
  12503. * the tx frames in question were transmitted to.
  12504. *
  12505. * The peer map v2 message also contains a HW peer ID. This HW peer ID
  12506. * is used during rx --> tx frame forwarding to identify which peer the
  12507. * frame needs to be forwarded to (i.e. the peer associated with the
  12508. * Destination MAC Address within the packet), and particularly which vdev
  12509. * needs to transmit the frame (for cases of inter-vdev rx --> tx forwarding).
  12510. * This DA-based peer ID that is provided for certain rx frames
  12511. * (the rx frames that need to be re-transmitted as tx frames)
  12512. * is the ID that the HW uses for referring to the peer in question,
  12513. * rather than the peer ID that the SW+FW use to refer to the peer.
  12514. *
  12515. * The HW peer id here is the same meaning as AST_INDEX_0.
  12516. * Some chips support up to 4 AST indices per peer: AST_INDEX_0, AST_INDEX_1,
  12517. * AST_INDEX_2, and AST_INDEX_3. AST 0 is always valid; for AST 1 through
  12518. * AST 3, check the AST_VALID_MASK(3) to see if the corresponding extension
  12519. * AST is valid.
  12520. *
  12521. * |31 28|27 24|23 21|20|19 17|16|15 8|7 0|
  12522. * |-------------------------------------------------------------------------|
  12523. * | SW peer ID | VDEV ID | msg type |
  12524. * |-------------------------------------------------------------------------|
  12525. * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
  12526. * |-------------------------------------------------------------------------|
  12527. * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 |
  12528. * |-------------------------------------------------------------------------|
  12529. * | Reserved_21_31 |OA|ASTVM|NH| AST Hash Value |
  12530. * |-------------------------------------------------------------------------|
  12531. * | ASTFM3 | ASTFM2 | ASTFM1 | ASTFM0 | AST index 1 |
  12532. * |-------------------------------------------------------------------------|
  12533. * |TID valid low pri| TID valid hi pri | AST index 2 |
  12534. * |-------------------------------------------------------------------------|
  12535. * | LMAC/PMAC_RXPCU AST index | AST index 3 |
  12536. * |-------------------------------------------------------------------------|
  12537. * | Reserved_2 |
  12538. * |-------------------------------------------------------------------------|
  12539. * Where:
  12540. * NH = Next Hop
  12541. * ASTVM = AST valid mask
  12542. * OA = on-chip AST valid bit
  12543. * ASTFM = AST flow mask
  12544. *
  12545. * The following field definitions describe the format of the rx peer map v2
  12546. * messages sent from the target to the host.
  12547. * - MSG_TYPE
  12548. * Bits 7:0
  12549. * Purpose: identifies this as an rx peer map v2 message
  12550. * Value: peer map v2 -> 0x1e (HTT_T2H_MSG_TYPE_PEER_MAP_V2)
  12551. * - VDEV_ID
  12552. * Bits 15:8
  12553. * Purpose: Indicates which virtual device the peer is associated with.
  12554. * Value: vdev ID (used in the host to look up the vdev object)
  12555. * - SW_PEER_ID
  12556. * Bits 31:16
  12557. * Purpose: The peer ID (index) that WAL is allocating
  12558. * Value: (rx) peer ID
  12559. * - MAC_ADDR_L32
  12560. * Bits 31:0
  12561. * Purpose: Identifies which peer node the peer ID is for.
  12562. * Value: lower 4 bytes of peer node's MAC address
  12563. * - MAC_ADDR_U16
  12564. * Bits 15:0
  12565. * Purpose: Identifies which peer node the peer ID is for.
  12566. * Value: upper 2 bytes of peer node's MAC address
  12567. * - HW_PEER_ID / AST_INDEX_0
  12568. * Bits 31:16
  12569. * Purpose: Identifies the HW peer ID corresponding to the peer MAC
  12570. * address, so for rx frames marked for rx --> tx forwarding, the
  12571. * host can determine from the HW peer ID provided as meta-data with
  12572. * the rx frame which peer the frame is supposed to be forwarded to.
  12573. * Value: ID used by the MAC HW to identify the peer
  12574. * - AST_HASH_VALUE
  12575. * Bits 15:0
  12576. * Purpose: Indicates AST Hash value is required for the TCL AST index
  12577. * override feature.
  12578. * - NEXT_HOP
  12579. * Bit 16
  12580. * Purpose: Bit indicates that a next_hop AST entry is used for WDS
  12581. * (Wireless Distribution System).
  12582. * - AST_VALID_MASK
  12583. * Bits 19:17
  12584. * Purpose: Indicate if the AST 1 through AST 3 are valid
  12585. * - ONCHIP_AST_VALID_FLAG
  12586. * Bit 20
  12587. * Purpose: Indicate if the on-chip AST index field (ONCHIP_AST_IDX)
  12588. * is valid.
  12589. * - AST_INDEX_1
  12590. * Bits 15:0
  12591. * Purpose: indicate the second AST index for this peer
  12592. * - AST_0_FLOW_MASK
  12593. * Bits 19:16
  12594. * Purpose: identify the which flow the AST 0 entry corresponds to.
  12595. * - AST_1_FLOW_MASK
  12596. * Bits 23:20
  12597. * Purpose: identify the which flow the AST 1 entry corresponds to.
  12598. * - AST_2_FLOW_MASK
  12599. * Bits 27:24
  12600. * Purpose: identify the which flow the AST 2 entry corresponds to.
  12601. * - AST_3_FLOW_MASK
  12602. * Bits 31:28
  12603. * Purpose: identify the which flow the AST 3 entry corresponds to.
  12604. * - AST_INDEX_2
  12605. * Bits 15:0
  12606. * Purpose: indicate the third AST index for this peer
  12607. * - TID_VALID_HI_PRI
  12608. * Bits 23:16
  12609. * Purpose: identify if this peer's TIDs 0-7 support HI priority flow
  12610. * - TID_VALID_LOW_PRI
  12611. * Bits 31:24
  12612. * Purpose: identify if this peer's TIDs 0-7 support Low priority flow
  12613. * - AST_INDEX_3
  12614. * Bits 15:0
  12615. * Purpose: indicate the fourth AST index for this peer
  12616. * - ONCHIP_AST_IDX / RESERVED
  12617. * Bits 31:16
  12618. * Purpose: This field is valid only when split AST feature is enabled.
  12619. * The ONCHIP_AST_VALID_FLAG identifies whether this field is valid.
  12620. * If valid, identifies the HW peer ID corresponding to the peer MAC
  12621. * address, this ast_idx is used for LMAC modules for RXPCU.
  12622. * Value: ID used by the LMAC HW to identify the peer
  12623. */
  12624. #define HTT_RX_PEER_MAP_V2_VDEV_ID_M 0xff00
  12625. #define HTT_RX_PEER_MAP_V2_VDEV_ID_S 8
  12626. #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_M 0xffff0000
  12627. #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_S 16
  12628. #define HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_M 0xffffffff
  12629. #define HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_S 0
  12630. #define HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_M 0xffff
  12631. #define HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_S 0
  12632. #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_M 0xffff0000
  12633. #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_S 16
  12634. #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_M 0x0000ffff
  12635. #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S 0
  12636. #define HTT_RX_PEER_MAP_V2_NEXT_HOP_M 0x00010000
  12637. #define HTT_RX_PEER_MAP_V2_NEXT_HOP_S 16
  12638. #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M 0x000e0000
  12639. #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S 17
  12640. #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M 0x00100000
  12641. #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S 20
  12642. #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_M 0xffff
  12643. #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_S 0
  12644. #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M 0x000f0000
  12645. #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S 16
  12646. #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M 0x00f00000
  12647. #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S 20
  12648. #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M 0x0f000000
  12649. #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S 24
  12650. #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M 0xf0000000
  12651. #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S 28
  12652. #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_M 0xffff
  12653. #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_S 0
  12654. #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M 0x00ff0000
  12655. #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S 16
  12656. #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M 0xff000000
  12657. #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S 24
  12658. #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_M 0xffff
  12659. #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_S 0
  12660. #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M 0xffff0000
  12661. #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S 16
  12662. #define HTT_RX_PEER_MAP_V2_VDEV_ID_SET(word, value) \
  12663. do { \
  12664. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_VDEV_ID, value); \
  12665. (word) |= (value) << HTT_RX_PEER_MAP_V2_VDEV_ID_S; \
  12666. } while (0)
  12667. #define HTT_RX_PEER_MAP_V2_VDEV_ID_GET(word) \
  12668. (((word) & HTT_RX_PEER_MAP_V2_VDEV_ID_M) >> HTT_RX_PEER_MAP_V2_VDEV_ID_S)
  12669. #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_SET(word, value) \
  12670. do { \
  12671. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_SW_PEER_ID, value); \
  12672. (word) |= (value) << HTT_RX_PEER_MAP_V2_SW_PEER_ID_S; \
  12673. } while (0)
  12674. #define HTT_RX_PEER_MAP_V2_SW_PEER_ID_GET(word) \
  12675. (((word) & HTT_RX_PEER_MAP_V2_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V2_SW_PEER_ID_S)
  12676. #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_SET(word, value) \
  12677. do { \
  12678. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_HW_PEER_ID, value); \
  12679. (word) |= (value) << HTT_RX_PEER_MAP_V2_HW_PEER_ID_S; \
  12680. } while (0)
  12681. #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_GET(word) \
  12682. (((word) & HTT_RX_PEER_MAP_V2_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_V2_HW_PEER_ID_S)
  12683. #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_SET(word, value) \
  12684. do { \
  12685. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_HASH_VALUE, value); \
  12686. (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S; \
  12687. } while (0)
  12688. #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_GET(word) \
  12689. (((word) & HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_M) >> HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S)
  12690. #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_SET(word, value) \
  12691. do { \
  12692. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M, value); \
  12693. (word) |= (value) << HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S; \
  12694. } while (0)
  12695. #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_GET(word) \
  12696. (((word) & HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_M) >> HTT_RX_PEER_MAP_V2_ONCHIP_AST_HASH_VALUE_S)
  12697. #define HTT_RX_PEER_MAP_V2_NEXT_HOP_SET(word, value) \
  12698. do { \
  12699. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_NEXT_HOP, value); \
  12700. (word) |= (value) << HTT_RX_PEER_MAP_V2_NEXT_HOP_S; \
  12701. } while (0)
  12702. #define HTT_RX_PEER_MAP_V2_NEXT_HOP_GET(word) \
  12703. (((word) & HTT_RX_PEER_MAP_V2_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V2_NEXT_HOP_S)
  12704. #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_SET(word, value) \
  12705. do { \
  12706. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_VALID_MASK, value); \
  12707. (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S; \
  12708. } while (0)
  12709. #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_GET(word) \
  12710. (((word) & HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S)
  12711. #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_SET(word, value) \
  12712. do { \
  12713. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M, value); \
  12714. (word) |= (value) << HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S; \
  12715. } while (0)
  12716. #define HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_MASK_GET(word) \
  12717. (((word) & HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V2_ONCHIP_AST_VALID_FLAG_S)
  12718. #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_SET(word, value) \
  12719. do { \
  12720. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_1, value); \
  12721. (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_1_S; \
  12722. } while (0)
  12723. #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_GET(word) \
  12724. (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_1_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_1_S)
  12725. #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_SET(word, value) \
  12726. do { \
  12727. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK, value); \
  12728. (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S; \
  12729. } while (0)
  12730. #define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_GET(word) \
  12731. (((word) & HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S)
  12732. #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_SET(word, value) \
  12733. do { \
  12734. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK, value); \
  12735. (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S; \
  12736. } while (0)
  12737. #define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_GET(word) \
  12738. (((word) & HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S)
  12739. #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_SET(word, value) \
  12740. do { \
  12741. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK, value); \
  12742. (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S; \
  12743. } while (0)
  12744. #define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_GET(word) \
  12745. (((word) & HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S)
  12746. #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_SET(word, value) \
  12747. do { \
  12748. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK, value); \
  12749. (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S; \
  12750. } while (0)
  12751. #define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_GET(word) \
  12752. (((word) & HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S)
  12753. #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_SET(word, value) \
  12754. do { \
  12755. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_2, value); \
  12756. (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_2_S; \
  12757. } while (0)
  12758. #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_GET(word) \
  12759. (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_2_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_2_S)
  12760. #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_SET(word, value) \
  12761. do { \
  12762. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI, value); \
  12763. (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S; \
  12764. } while (0)
  12765. #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_GET(word) \
  12766. (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S)
  12767. #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_SET(word, value) \
  12768. do { \
  12769. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI, value); \
  12770. (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S; \
  12771. } while (0)
  12772. #define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_GET(word) \
  12773. (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S)
  12774. #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_SET(word, value) \
  12775. do { \
  12776. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_3, value); \
  12777. (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_3_S; \
  12778. } while (0)
  12779. #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_GET(word) \
  12780. (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_3_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_3_S)
  12781. #define HTT_RX_PEER_MAP_V2_MAC_ADDR_OFFSET 4 /* bytes */
  12782. #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_OFFSET 8 /* bytes */
  12783. #define HTT_RX_PEER_MAP_V2_AST_HASH_INDEX_OFFSET 12 /* bytes */
  12784. #define HTT_RX_PEER_MAP_V2_NEXT_HOP_OFFSET 12 /* bytes */
  12785. #define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_OFFSET 12 /* bytes */
  12786. #define HTT_RX_PEER_MAP_V2_AST_INDEX_1_OFFSET 16 /* bytes */
  12787. #define HTT_RX_PEER_MAP_V2_AST_X_FLOW_MASK_OFFSET 16 /* bytes */
  12788. #define HTT_RX_PEER_MAP_V2_AST_INDEX_2_OFFSET 20 /* bytes */
  12789. #define HTT_RX_PEER_MAP_V2_TID_VALID_LO_PRI_OFFSET 20 /* bytes */
  12790. #define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_OFFSET 20 /* bytes */
  12791. #define HTT_RX_PEER_MAP_V2_AST_INDEX_3_OFFSET 24 /* bytes */
  12792. #define HTT_RX_PEER_MAP_V2_BYTES 32
  12793. /**
  12794. * @brief target -> host rx peer map V3 message definition
  12795. *
  12796. * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_MAP_V3
  12797. *
  12798. * @details
  12799. * The following diagram shows the format of the rx peer map v3 message sent
  12800. * from the target to the host.
  12801. * Format inherits HTT_T2H_MSG_TYPE_PEER_MAP_V2 published above
  12802. * This layout assumes the target operates as little-endian.
  12803. *
  12804. * |31 24|23 20|19|18|17|16|15 8|7 0|
  12805. * |-----------------+--------+--+--+--+--+-----------------+-----------------|
  12806. * | SW peer ID | VDEV ID | msg type |
  12807. * |-----------------+--------------------+-----------------+-----------------|
  12808. * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
  12809. * |-----------------+--------------------+-----------------+-----------------|
  12810. * | Multicast SW peer ID | MAC addr 5 | MAC addr 4 |
  12811. * |-----------------+--------+-----------+-----------------+-----------------|
  12812. * | HTT_MSDU_IDX_ |RESERVED| CACHE_ | |
  12813. * | VALID_MASK |(4bits) | SET_NUM | HW peer ID / AST index |
  12814. * | (8bits) | | (4bits) | |
  12815. * |-----------------+--------+--+--+--+--------------------------------------|
  12816. * | RESERVED |E |O | | |
  12817. * | (13bits) |A |A |NH| on-Chip PMAC_RXPCU AST index |
  12818. * | |V |V | | |
  12819. * |-----------------+--------------------+-----------------------------------|
  12820. * | HTT_MSDU_IDX_ | RESERVED | |
  12821. * | VALID_MASK_EXT | (8bits) | EXT AST index |
  12822. * | (8bits) | | |
  12823. * |-----------------+--------------------+-----------------------------------|
  12824. * | Reserved_2 |
  12825. * |--------------------------------------------------------------------------|
  12826. * | Reserved_3 |
  12827. * |--------------------------------------------------------------------------|
  12828. *
  12829. * Where:
  12830. * EAV = EXT_AST_VALID flag, for "EXT AST index"
  12831. * OAV = ONCHIP_AST_VALID flag, for "on-Chip PMAC_RXPCU AST index"
  12832. * NH = Next Hop
  12833. * The following field definitions describe the format of the rx peer map v3
  12834. * messages sent from the target to the host.
  12835. * - MSG_TYPE
  12836. * Bits 7:0
  12837. * Purpose: identifies this as a peer map v3 message
  12838. * Value: 0x2b (HTT_T2H_MSG_TYPE_PEER_MAP_V3)
  12839. * - VDEV_ID
  12840. * Bits 15:8
  12841. * Purpose: Indicates which virtual device the peer is associated with.
  12842. * - SW_PEER_ID
  12843. * Bits 31:16
  12844. * Purpose: The peer ID (index) that WAL has allocated for this peer.
  12845. * - MAC_ADDR_L32
  12846. * Bits 31:0
  12847. * Purpose: Identifies which peer node the peer ID is for.
  12848. * Value: lower 4 bytes of peer node's MAC address
  12849. * - MAC_ADDR_U16
  12850. * Bits 15:0
  12851. * Purpose: Identifies which peer node the peer ID is for.
  12852. * Value: upper 2 bytes of peer node's MAC address
  12853. * - MULTICAST_SW_PEER_ID
  12854. * Bits 31:16
  12855. * Purpose: The multicast peer ID (index)
  12856. * Value: set to HTT_INVALID_PEER if not valid
  12857. * - HW_PEER_ID / AST_INDEX
  12858. * Bits 15:0
  12859. * Purpose: Identifies the HW peer ID corresponding to the peer MAC
  12860. * address, so for rx frames marked for rx --> tx forwarding, the
  12861. * host can determine from the HW peer ID provided as meta-data with
  12862. * the rx frame which peer the frame is supposed to be forwarded to.
  12863. * - CACHE_SET_NUM
  12864. * Bits 19:16
  12865. * Purpose: Cache Set Number for AST_INDEX
  12866. * Cache set number that should be used to cache the index based
  12867. * search results, for address and flow search.
  12868. * This value should be equal to LSB 4 bits of the hash value
  12869. * of match data, in case of search index points to an entry which
  12870. * may be used in content based search also. The value can be
  12871. * anything when the entry pointed by search index will not be
  12872. * used for content based search.
  12873. * - HTT_MSDU_IDX_VALID_MASK
  12874. * Bits 31:24
  12875. * Purpose: Shows MSDU indexes valid mask for AST_INDEX
  12876. * - ONCHIP_AST_IDX / RESERVED
  12877. * Bits 15:0
  12878. * Purpose: This field is valid only when split AST feature is enabled.
  12879. * The ONCHIP_AST_VALID flag identifies whether this field is valid.
  12880. * If valid, identifies the HW peer ID corresponding to the peer MAC
  12881. * address, this ast_idx is used for LMAC modules for RXPCU.
  12882. * - NEXT_HOP
  12883. * Bits 16
  12884. * Purpose: Flag indicates next_hop AST entry used for WDS
  12885. * (Wireless Distribution System).
  12886. * - ONCHIP_AST_VALID
  12887. * Bits 17
  12888. * Purpose: Flag indicates valid data behind of the ONCHIP_AST_IDX field
  12889. * - EXT_AST_VALID
  12890. * Bits 18
  12891. * Purpose: Flag indicates valid data behind of the EXT_AST_INDEX field
  12892. * - EXT_AST_INDEX
  12893. * Bits 15:0
  12894. * Purpose: This field describes Extended AST index
  12895. * Valid if EXT_AST_VALID flag set
  12896. * - HTT_MSDU_IDX_VALID_MASK_EXT
  12897. * Bits 31:24
  12898. * Purpose: Shows MSDU indexes valid mask for EXT_AST_INDEX
  12899. */
  12900. /* dword 0 */
  12901. #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_M 0xffff0000
  12902. #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_S 16
  12903. #define HTT_RX_PEER_MAP_V3_VDEV_ID_M 0x0000ff00
  12904. #define HTT_RX_PEER_MAP_V3_VDEV_ID_S 8
  12905. /* dword 1 */
  12906. #define HTT_RX_PEER_MAP_V3_MAC_ADDR_L32_M 0xffffffff
  12907. #define HTT_RX_PEER_MAP_V3_MAC_ADDR_L32_S 0
  12908. /* dword 2 */
  12909. #define HTT_RX_PEER_MAP_V3_MAC_ADDR_U16_M 0x0000ffff
  12910. #define HTT_RX_PEER_MAP_V3_MAC_ADDR_U16_S 0
  12911. #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_M 0xffff0000
  12912. #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S 16
  12913. /* dword 3 */
  12914. #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_M 0xff000000
  12915. #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S 24
  12916. #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_M 0x000f0000
  12917. #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S 16
  12918. #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_M 0x0000ffff
  12919. #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_S 0
  12920. /* dword 4 */
  12921. #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M 0x00040000
  12922. #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S 18
  12923. #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_M 0x00020000
  12924. #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S 17
  12925. #define HTT_RX_PEER_MAP_V3_NEXT_HOP_M 0x00010000
  12926. #define HTT_RX_PEER_MAP_V3_NEXT_HOP_S 16
  12927. #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_M 0x0000ffff
  12928. #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S 0
  12929. /* dword 5 */
  12930. #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_M 0xff000000
  12931. #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S 24
  12932. #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M 0x0000ffff
  12933. #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S 0
  12934. #define HTT_RX_PEER_MAP_V3_VDEV_ID_SET(word, value) \
  12935. do { \
  12936. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_VDEV_ID, value); \
  12937. (word) |= (value) << HTT_RX_PEER_MAP_V3_VDEV_ID_S; \
  12938. } while (0)
  12939. #define HTT_RX_PEER_MAP_V3_VDEV_ID_GET(word) \
  12940. (((word) & HTT_RX_PEER_MAP_V3_VDEV_ID_M) >> HTT_RX_PEER_MAP_V3_VDEV_ID_S)
  12941. #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_SET(word, value) \
  12942. do { \
  12943. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_SW_PEER_ID, value); \
  12944. (word) |= (value) << HTT_RX_PEER_MAP_V3_SW_PEER_ID_S; \
  12945. } while (0)
  12946. #define HTT_RX_PEER_MAP_V3_SW_PEER_ID_GET(word) \
  12947. (((word) & HTT_RX_PEER_MAP_V3_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_SW_PEER_ID_S)
  12948. #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_SET(word, value) \
  12949. do { \
  12950. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID, value); \
  12951. (word) |= (value) << HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S; \
  12952. } while (0)
  12953. #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_GET(word) \
  12954. (((word) & HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S)
  12955. #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_SET(word, value) \
  12956. do { \
  12957. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_HW_PEER_ID, value); \
  12958. (word) |= (value) << HTT_RX_PEER_MAP_V3_HW_PEER_ID_S; \
  12959. } while (0)
  12960. #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_GET(word) \
  12961. (((word) & HTT_RX_PEER_MAP_V3_HW_PEER_ID_M) >> HTT_RX_PEER_MAP_V3_HW_PEER_ID_S)
  12962. #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_SET(word, value) \
  12963. do { \
  12964. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_CACHE_SET_NUM, value); \
  12965. (word) |= (value) << HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S; \
  12966. } while (0)
  12967. #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_GET(word) \
  12968. (((word) & HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_M) >> HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S)
  12969. #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_SET(word, value) \
  12970. do { \
  12971. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST, value); \
  12972. (word) |= (value) << HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S; \
  12973. } while (0)
  12974. #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_GET(word) \
  12975. (((word) & HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_M) >> HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S)
  12976. #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_SET(word, value) \
  12977. do { \
  12978. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX, value); \
  12979. (word) |= (value) << HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S; \
  12980. } while (0)
  12981. #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_GET(word) \
  12982. (((word) & HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_M) >> HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S)
  12983. #define HTT_RX_PEER_MAP_V3_NEXT_HOP_SET(word, value) \
  12984. do { \
  12985. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_NEXT_HOP, value); \
  12986. (word) |= (value) << HTT_RX_PEER_MAP_V3_NEXT_HOP_S; \
  12987. } while (0)
  12988. #define HTT_RX_PEER_MAP_V3_NEXT_HOP_GET(word) \
  12989. (((word) & HTT_RX_PEER_MAP_V3_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V3_NEXT_HOP_S)
  12990. #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_SET(word, value) \
  12991. do { \
  12992. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG, value); \
  12993. (word) |= (value) << HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S; \
  12994. } while (0)
  12995. #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_GET(word) \
  12996. (((word) & HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S)
  12997. #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_SET(word, value) \
  12998. do { \
  12999. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG, value); \
  13000. (word) |= (value) << HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S; \
  13001. } while (0)
  13002. #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_GET(word) \
  13003. (((word) & HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S)
  13004. #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_SET(word, value) \
  13005. do { \
  13006. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_EXT_AST_IDX, value); \
  13007. (word) |= (value) << HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S; \
  13008. } while (0)
  13009. #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_GET(word) \
  13010. (((word) & HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M) >> HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S)
  13011. #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_SET(word, value) \
  13012. do { \
  13013. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST, value); \
  13014. (word) |= (value) << HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S; \
  13015. } while (0)
  13016. #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_GET(word) \
  13017. (((word) & HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_M) >> HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S)
  13018. #define HTT_RX_PEER_MAP_V3_MAC_ADDR_OFFSET 4 /* bytes */
  13019. #define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_OFFSET 8 /* bytes */
  13020. #define HTT_RX_PEER_MAP_V3_HW_PEER_ID_OFFSET 12 /* bytes */
  13021. #define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_OFFSET 12 /* bytes */
  13022. #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_OFFSET 12 /* bytes */
  13023. #define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_OFFSET 16 /* bytes */
  13024. #define HTT_RX_PEER_MAP_V3_NEXT_HOP_OFFSET 16 /* bytes */
  13025. #define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_OFFSET 16 /* bytes */
  13026. #define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_OFFSET 16 /* bytes */
  13027. #define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_OFFSET 20 /* bytes */
  13028. #define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_OFFSET 20 /* bytes */
  13029. #define HTT_RX_PEER_MAP_V3_BYTES 32
  13030. /**
  13031. * @brief target -> host rx peer unmap V2 message definition
  13032. *
  13033. * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_UNMAP_V2
  13034. *
  13035. * The following diagram shows the format of the rx peer unmap message sent
  13036. * from the target to the host.
  13037. *
  13038. * |31 24|23 16|15 8|7 0|
  13039. * |-----------------------------------------------------------------------|
  13040. * | SW peer ID | VDEV ID | msg type |
  13041. * |-----------------------------------------------------------------------|
  13042. * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
  13043. * |-----------------------------------------------------------------------|
  13044. * | Reserved_17_31 | Next Hop | MAC addr 5 | MAC addr 4 |
  13045. * |-----------------------------------------------------------------------|
  13046. * | Peer Delete Duration |
  13047. * |-----------------------------------------------------------------------|
  13048. * | Reserved_0 | WDS Free Count |
  13049. * |-----------------------------------------------------------------------|
  13050. * | Reserved_1 |
  13051. * |-----------------------------------------------------------------------|
  13052. * | Reserved_2 |
  13053. * |-----------------------------------------------------------------------|
  13054. *
  13055. *
  13056. * The following field definitions describe the format of the rx peer unmap
  13057. * messages sent from the target to the host.
  13058. * - MSG_TYPE
  13059. * Bits 7:0
  13060. * Purpose: identifies this as an rx peer unmap v2 message
  13061. * Value: peer unmap v2 -> 0x1f (HTT_T2H_MSG_TYPE_PEER_UNMAP_V2)
  13062. * - VDEV_ID
  13063. * Bits 15:8
  13064. * Purpose: Indicates which virtual device the peer is associated
  13065. * with.
  13066. * Value: vdev ID (used in the host to look up the vdev object)
  13067. * - SW_PEER_ID
  13068. * Bits 31:16
  13069. * Purpose: The peer ID (index) that WAL is freeing
  13070. * Value: (rx) peer ID
  13071. * - MAC_ADDR_L32
  13072. * Bits 31:0
  13073. * Purpose: Identifies which peer node the peer ID is for.
  13074. * Value: lower 4 bytes of peer node's MAC address
  13075. * - MAC_ADDR_U16
  13076. * Bits 15:0
  13077. * Purpose: Identifies which peer node the peer ID is for.
  13078. * Value: upper 2 bytes of peer node's MAC address
  13079. * - NEXT_HOP
  13080. * Bits 16
  13081. * Purpose: Bit indicates next_hop AST entry used for WDS
  13082. * (Wireless Distribution System).
  13083. * - PEER_DELETE_DURATION
  13084. * Bits 31:0
  13085. * Purpose: Time taken to delete peer, in msec,
  13086. * Used for monitoring / debugging PEER delete response delay
  13087. * - PEER_WDS_FREE_COUNT
  13088. * Bits 15:0
  13089. * Purpose: Count of WDS entries deleted associated to peer deleted
  13090. */
  13091. #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_M HTT_RX_PEER_MAP_V2_VDEV_ID_M
  13092. #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_S HTT_RX_PEER_MAP_V2_VDEV_ID_S
  13093. #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_M HTT_RX_PEER_MAP_V2_SW_PEER_ID_M
  13094. #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_S HTT_RX_PEER_MAP_V2_SW_PEER_ID_S
  13095. #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_L32_M HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_M
  13096. #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_L32_S HTT_RX_PEER_MAP_V2_MAC_ADDR_L32_S
  13097. #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_U16_M HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_M
  13098. #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_U16_S HTT_RX_PEER_MAP_V2_MAC_ADDR_U16_S
  13099. #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_M HTT_RX_PEER_MAP_V2_NEXT_HOP_M
  13100. #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_S HTT_RX_PEER_MAP_V2_NEXT_HOP_S
  13101. #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_M 0xffffffff
  13102. #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S 0
  13103. #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_M 0x0000ffff
  13104. #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S 0
  13105. #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_SET HTT_RX_PEER_MAP_V2_VDEV_ID_SET
  13106. #define HTT_RX_PEER_UNMAP_V2_VDEV_ID_GET HTT_RX_PEER_MAP_V2_VDEV_ID_GET
  13107. #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_SET HTT_RX_PEER_MAP_V2_SW_PEER_ID_SET
  13108. #define HTT_RX_PEER_UNMAP_V2_SW_PEER_ID_GET HTT_RX_PEER_MAP_V2_SW_PEER_ID_GET
  13109. #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_SET HTT_RX_PEER_MAP_V2_NEXT_HOP_SET
  13110. #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_GET HTT_RX_PEER_MAP_V2_NEXT_HOP_GET
  13111. #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_SET(word, value) \
  13112. do { \
  13113. HTT_CHECK_SET_VAL(HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION, value); \
  13114. (word) |= (value) << HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S; \
  13115. } while (0)
  13116. #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_GET(word) \
  13117. (((word) & HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_M) >> HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_S)
  13118. #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_SET(word, value) \
  13119. do { \
  13120. HTT_CHECK_SET_VAL(HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT, value); \
  13121. (word) |= (value) << HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S; \
  13122. } while (0)
  13123. #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_GET(word) \
  13124. (((word) & HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_M) >> HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_S)
  13125. #define HTT_RX_PEER_UNMAP_V2_MAC_ADDR_OFFSET 4 /* bytes */
  13126. #define HTT_RX_PEER_UNMAP_V2_NEXT_HOP_OFFSET 8 /* bytes */
  13127. #define HTT_RX_PEER_UNMAP_V2_PEER_DELETE_DURATION_OFFSET 12 /* bytes */
  13128. #define HTT_RX_PEER_UNMAP_V2_PEER_WDS_FREE_COUNT_OFFSET 16 /* bytes */
  13129. #define HTT_RX_PEER_UNMAP_V2_BYTES 28
  13130. /**
  13131. * @brief target -> host rx peer mlo map message definition
  13132. *
  13133. * MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP
  13134. *
  13135. * @details
  13136. * The following diagram shows the format of the rx mlo peer map message sent
  13137. * from the target to the host. This layout assumes the target operates
  13138. * as little-endian.
  13139. *
  13140. * MCC:
  13141. * One HTT_MLO_PEER_MAP is sent after PEER_ASSOC received on first LINK for both STA and SAP.
  13142. *
  13143. * WIN:
  13144. * One HTT_MLO_PEER_MAP is sent after peers are created on all the links for both AP and STA.
  13145. * It will be sent on the Assoc Link.
  13146. *
  13147. * This message always contains a MLO peer ID. The main purpose of the
  13148. * MLO peer ID is to tell the host what peer ID rx packets will be tagged
  13149. * with, so that the host can use that MLO peer ID to determine which peer
  13150. * transmitted the rx frame.
  13151. *
  13152. * |31 |29 27|26 24|23 20|19 17|16|15 8|7 0|
  13153. * |-------------------------------------------------------------------------|
  13154. * |RSVD | PRC |NUMLINK| MLO peer ID | msg type |
  13155. * |-------------------------------------------------------------------------|
  13156. * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
  13157. * |-------------------------------------------------------------------------|
  13158. * | RSVD_16_31 | MAC addr 5 | MAC addr 4 |
  13159. * |-------------------------------------------------------------------------|
  13160. * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 0 |
  13161. * |-------------------------------------------------------------------------|
  13162. * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 1 |
  13163. * |-------------------------------------------------------------------------|
  13164. * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 2 |
  13165. * |-------------------------------------------------------------------------|
  13166. * |RSVD |
  13167. * |-------------------------------------------------------------------------|
  13168. * |RSVD |
  13169. * |-------------------------------------------------------------------------|
  13170. * | htt_tlv_hdr_t |
  13171. * |-------------------------------------------------------------------------|
  13172. * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID |
  13173. * |-------------------------------------------------------------------------|
  13174. * | htt_tlv_hdr_t |
  13175. * |-------------------------------------------------------------------------|
  13176. * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID |
  13177. * |-------------------------------------------------------------------------|
  13178. * | htt_tlv_hdr_t |
  13179. * |-------------------------------------------------------------------------|
  13180. * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID |
  13181. * |-------------------------------------------------------------------------|
  13182. *
  13183. * Where:
  13184. * PRC - Primary REO CHIPID - 3 Bits Bit24,25,26
  13185. * NUMLINK - NUM_LOGICAL_LINKS - 3 Bits Bit27,28,29
  13186. * V (valid) - 1 Bit Bit17
  13187. * CHIPID - 3 Bits
  13188. * TIDMASK - 8 Bits
  13189. * CACHE_SET_NUM - 8 Bits
  13190. *
  13191. * The following field definitions describe the format of the rx MLO peer map
  13192. * messages sent from the target to the host.
  13193. * - MSG_TYPE
  13194. * Bits 7:0
  13195. * Purpose: identifies this as an rx mlo peer map message
  13196. * Value: 0x29 (HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP)
  13197. *
  13198. * - MLO_PEER_ID
  13199. * Bits 23:8
  13200. * Purpose: The MLO peer ID (index).
  13201. * For MCC, FW will allocate it. For WIN, Host will allocate it.
  13202. * Value: MLO peer ID
  13203. *
  13204. * - NUMLINK
  13205. * Bits: 26:24 (3Bits)
  13206. * Purpose: Indicate the max number of logical links supported per client.
  13207. * Value: number of logical links
  13208. *
  13209. * - PRC
  13210. * Bits: 29:27 (3Bits)
  13211. * Purpose: Indicate the Primary REO CHIPID. The ID can be used to indicate
  13212. * if there is migration of the primary chip.
  13213. * Value: Primary REO CHIPID
  13214. *
  13215. * - MAC_ADDR_L32
  13216. * Bits 31:0
  13217. * Purpose: Identifies which mlo peer node the mlo peer ID is for.
  13218. * Value: lower 4 bytes of peer node's MAC address
  13219. *
  13220. * - MAC_ADDR_U16
  13221. * Bits 15:0
  13222. * Purpose: Identifies which peer node the peer ID is for.
  13223. * Value: upper 2 bytes of peer node's MAC address
  13224. *
  13225. * - PRIMARY_TCL_AST_IDX
  13226. * Bits 15:0
  13227. * Purpose: Primary TCL AST index for this peer.
  13228. *
  13229. * - V
  13230. * 1 Bit Position 16
  13231. * Purpose: If the ast idx is valid.
  13232. *
  13233. * - CHIPID
  13234. * Bits 19:17
  13235. * Purpose: Identifies which chip id of PRIMARY_TCL_AST_IDX
  13236. *
  13237. * - TIDMASK
  13238. * Bits 27:20
  13239. * Purpose: LINK to TID mapping for PRIMARY_TCL_AST_IDX
  13240. *
  13241. * - CACHE_SET_NUM
  13242. * Bits 31:28
  13243. * Purpose: Cache Set Number for PRIMARY_TCL_AST_IDX
  13244. * Cache set number that should be used to cache the index based
  13245. * search results, for address and flow search.
  13246. * This value should be equal to LSB four bits of the hash value
  13247. * of match data, in case of search index points to an entry which
  13248. * may be used in content based search also. The value can be
  13249. * anything when the entry pointed by search index will not be
  13250. * used for content based search.
  13251. *
  13252. * - htt_tlv_hdr_t
  13253. * Purpose: Provide link specific chip,vdev and sw_peer IDs
  13254. *
  13255. * Bits 11:0
  13256. * Purpose: tag equal to MLO_PEER_MAP_TLV_STRUCT_SOC_VDEV_PEER_IDS.
  13257. *
  13258. * Bits 23:12
  13259. * Purpose: Length, Length of the value that follows the header
  13260. *
  13261. * Bits 31:28
  13262. * Purpose: Reserved.
  13263. *
  13264. *
  13265. * - SW_PEER_ID
  13266. * Bits 15:0
  13267. * Purpose: The peer ID (index) that WAL is allocating
  13268. * Value: (rx) peer ID
  13269. *
  13270. * - VDEV_ID
  13271. * Bits 23:16
  13272. * Purpose: Indicates which virtual device the peer is associated with.
  13273. * Value: vdev ID (used in the host to look up the vdev object)
  13274. *
  13275. * - CHIPID
  13276. * Bits 26:24
  13277. * Purpose: Indicates which Chip id the peer is associated with.
  13278. * Value: chip ID (Provided by Host as part of QMI exchange)
  13279. */
  13280. typedef enum {
  13281. MLO_PEER_MAP_TLV_STRUCT_SOC_VDEV_PEER_IDS,
  13282. } MLO_PEER_MAP_TLV_TAG_ID;
  13283. #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M 0x00ffff00
  13284. #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S 8
  13285. #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_M 0x07000000
  13286. #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S 24
  13287. #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M 0x38000000
  13288. #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S 27
  13289. #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_L32_M 0xffffffff
  13290. #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_L32_S 0
  13291. #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_M 0x0000ffff
  13292. #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_S 0
  13293. #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M 0x0000ffff
  13294. #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S 0
  13295. #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M 0x00010000
  13296. #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S 16
  13297. #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_M 0x000E0000
  13298. #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S 17
  13299. #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_M 0x00F00000
  13300. #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S 20
  13301. #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_M 0xF0000000
  13302. #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S 28
  13303. #define HTT_RX_MLO_PEER_MAP_TLV_TAG_M 0x00000fff
  13304. #define HTT_RX_MLO_PEER_MAP_TLV_TAG_S 0
  13305. #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_M 0x00fff000
  13306. #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S 12
  13307. #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_M 0x0000ffff
  13308. #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S 0
  13309. #define HTT_RX_MLO_PEER_MAP_VDEV_ID_M 0x00ff0000
  13310. #define HTT_RX_MLO_PEER_MAP_VDEV_ID_S 16
  13311. #define HTT_RX_MLO_PEER_MAP_CHIP_ID_M 0x07000000
  13312. #define HTT_RX_MLO_PEER_MAP_CHIP_ID_S 24
  13313. #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_SET(word, value) \
  13314. do { \
  13315. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_MLO_PEER_ID, value); \
  13316. (word) |= (value) << HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S; \
  13317. } while (0)
  13318. #define HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_GET(word) \
  13319. (((word) & HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M) >> HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S)
  13320. #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_SET(word, value) \
  13321. do { \
  13322. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS, value); \
  13323. (word) |= (value) << HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S; \
  13324. } while (0)
  13325. #define HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_GET(word) \
  13326. (((word) & HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_M) >> HTT_RX_MLO_PEER_MAP_NUM_LOGICAL_LINKS_S)
  13327. #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_SET(word, value) \
  13328. do { \
  13329. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID, value); \
  13330. (word) |= (value) << HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S; \
  13331. } while (0)
  13332. #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_GET(word) \
  13333. (((word) & HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M) >> HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S)
  13334. #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_SET(word, value) \
  13335. do { \
  13336. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX, value); \
  13337. (word) |= (value) << HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S; \
  13338. } while (0)
  13339. #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_GET(word) \
  13340. (((word) & HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S)
  13341. #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_SET(word, value) \
  13342. do { \
  13343. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG, value); \
  13344. (word) |= (value) << HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S; \
  13345. } while (0)
  13346. #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_GET(word) \
  13347. (((word) & HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M) >> HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_S)
  13348. #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_SET(word, value) \
  13349. do { \
  13350. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX, value); \
  13351. (word) |= (value) << HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S; \
  13352. } while (0)
  13353. #define HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_GET(word) \
  13354. (((word) & HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_CHIP_ID_AST_INDEX_S)
  13355. #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_SET(word, value) \
  13356. do { \
  13357. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX, value); \
  13358. (word) |= (value) << HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S; \
  13359. } while (0)
  13360. #define HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_GET(word) \
  13361. (((word) & HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_TIDMASK_AST_INDEX_S)
  13362. #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_SET(word, value) \
  13363. do { \
  13364. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX, value); \
  13365. (word) |= (value) << HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S; \
  13366. } while (0)
  13367. #define HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_GET(word) \
  13368. (((word) & HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_M) >> HTT_RX_MLO_PEER_MAP_CACHE_SET_NUM_AST_INDEX_S)
  13369. #define HTT_RX_MLO_PEER_MAP_TLV_TAG_SET(word, value) \
  13370. do { \
  13371. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TLV_TAG, value); \
  13372. (word) |= (value) << HTT_RX_MLO_PEER_MAP_TLV_TAG_S; \
  13373. } while (0)
  13374. #define HTT_RX_MLO_PEER_MAP_TLV_TAG_GET(word) \
  13375. (((word) & HTT_RX_MLO_PEER_MAP_TLV_TAG_M) >> HTT_RX_MLO_PEER_MAP_TLV_TAG_S)
  13376. #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_SET(word, value) \
  13377. do { \
  13378. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_TLV_LENGTH, value); \
  13379. (word) |= (value) << HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S; \
  13380. } while (0)
  13381. #define HTT_RX_MLO_PEER_MAP_TLV_LENGTH_GET(word) \
  13382. (((word) & HTT_RX_MLO_PEER_MAP_TLV_LENGTH_M) >> HTT_RX_MLO_PEER_MAP_TLV_LENGTH_S)
  13383. #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_SET(word, value) \
  13384. do { \
  13385. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_SW_PEER_ID, value); \
  13386. (word) |= (value) << HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S; \
  13387. } while (0)
  13388. #define HTT_RX_MLO_PEER_MAP_SW_PEER_ID_GET(word) \
  13389. (((word) & HTT_RX_MLO_PEER_MAP_SW_PEER_ID_M) >> HTT_RX_MLO_PEER_MAP_SW_PEER_ID_S)
  13390. #define HTT_RX_MLO_PEER_MAP_VDEV_ID_SET(word, value) \
  13391. do { \
  13392. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_VDEV_ID, value); \
  13393. (word) |= (value) << HTT_RX_MLO_PEER_MAP_VDEV_ID_S; \
  13394. } while (0)
  13395. #define HTT_RX_MLO_PEER_MAP_VDEV_ID_GET(word) \
  13396. (((word) & HTT_RX_MLO_PEER_MAP_VDEV_ID_M) >> HTT_RX_MLO_PEER_MAP_VDEV_ID_S)
  13397. #define HTT_RX_MLO_PEER_MAP_CHIP_ID_SET(word, value) \
  13398. do { \
  13399. HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CHIP_ID, value); \
  13400. (word) |= (value) << HTT_RX_MLO_PEER_MAP_CHIP_ID_S; \
  13401. } while (0)
  13402. #define HTT_RX_MLO_PEER_MAP_CHIP_ID_GET(word) \
  13403. (((word) & HTT_RX_MLO_PEER_MAP_CHIP_ID_M) >> HTT_RX_MLO_PEER_MAP_CHIP_ID_S)
  13404. #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */
  13405. #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_0_OFFSET 12 /* bytes */
  13406. #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_1_OFFSET 16 /* bytes */
  13407. #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_2_OFFSET 20 /* bytes */
  13408. #define HTT_RX_MLO_PEER_MAP_TLV_OFFSET 32 /* bytes */
  13409. #define HTT_RX_MLO_PEER_MAP_FIXED_BYTES 8*4 /* 8 Dwords. Does not include the TLV header and the TLV */
  13410. /* MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_RX_PEER_UNMAP
  13411. *
  13412. * The following diagram shows the format of the rx mlo peer unmap message sent
  13413. * from the target to the host.
  13414. *
  13415. * |31 24|23 16|15 8|7 0|
  13416. * |-----------------------------------------------------------------------|
  13417. * | RSVD_24_31 | MLO peer ID | msg type |
  13418. * |-----------------------------------------------------------------------|
  13419. */
  13420. #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_M HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_M
  13421. #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_S HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_S
  13422. #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_SET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_SET
  13423. #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_GET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_GET
  13424. /**
  13425. * @brief target -> host peer extended event for additional information
  13426. *
  13427. * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT
  13428. *
  13429. * @details
  13430. * The following diagram shows the format of the peer extended message sent
  13431. * from the target to the host. This layout assumes the target operates
  13432. * as little-endian.
  13433. *
  13434. * This message always contains a SW peer ID. The main purpose of the
  13435. * SW peer ID is to tell the host what peer ID logical link id will be tagged
  13436. * with, so that the host can use that peer ID to determine which link
  13437. * transmitted the rx/tx frame.
  13438. *
  13439. * This message also contains MLO logical link id assigned to peer
  13440. * with sw_peer_id if it is valid ML link peer.
  13441. *
  13442. *
  13443. * |31 28|27 24|23 20|19|18 16|15 8|7 0|
  13444. * |---------------------------------------------------------------------------|
  13445. * | VDEV_ID | SW peer ID | msg type |
  13446. * |---------------------------------------------------------------------------|
  13447. * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
  13448. * |---------------------------------------------------------------------------|
  13449. * | Reserved |V | LINK ID | MAC addr 5 | MAC addr 4 |
  13450. * |---------------------------------------------------------------------------|
  13451. * | Reserved |
  13452. * |---------------------------------------------------------------------------|
  13453. * | Reserved |
  13454. * |---------------------------------------------------------------------------|
  13455. *
  13456. * Where:
  13457. * LINK_ID (LOGICAL) - 3 Bits Bit16,17,18 of 3rd byte
  13458. * V (valid) - 1 Bit Bit19 of 3rd byte
  13459. *
  13460. * The following field definitions describe the format of the rx peer extended
  13461. * event messages sent from the target to the host.
  13462. * MSG_TYPE
  13463. * Bits 7:0
  13464. * Purpose: identifies this as an rx MLO peer extended information message
  13465. * Value: 0x39 (HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT)
  13466. * - PEER_ID (a.k.a. SW_PEER_ID)
  13467. * Bits 8:23
  13468. * Purpose: The peer ID (index) that WAL has allocated
  13469. * Value: (rx) peer ID
  13470. * - VDEV_ID
  13471. * Bits 24:31
  13472. * Purpose: Gives the vdev id of peer with peer_id as above.
  13473. * Value: VDEV ID of wal_peer
  13474. *
  13475. * - MAC_ADDR_L32
  13476. * Bits 31:0
  13477. * Purpose: Identifies which peer node the peer ID is for.
  13478. * Value: lower 4 bytes of peer node's MAC address
  13479. *
  13480. * - MAC_ADDR_U16
  13481. * Bits 15:0
  13482. * Purpose: Identifies which peer node the peer ID is for.
  13483. * Value: upper 2 bytes of peer node's MAC address
  13484. * Rest all bits are reserved for future expansion
  13485. * - LOGICAL_LINK_ID
  13486. * Bits 18:16
  13487. * Purpose: Gives the logical link id of peer with peer_id as above. This
  13488. * field should be taken alongwith LOGICAL_LINK_ID_VALID
  13489. * Value: Logical link id used by wal_peer
  13490. * - LOGICAL_LINK_ID_VALID
  13491. * Bit 19
  13492. * Purpose: Clarifies whether the logical link id of peer with peer_id as
  13493. * is valid or not
  13494. * Value: 0/1 indicating LOGICAL_LINK_ID is valid or not
  13495. */
  13496. #define HTT_RX_PEER_EXTENDED_PEER_ID_M 0x00ffff00
  13497. #define HTT_RX_PEER_EXTENDED_PEER_ID_S 8
  13498. #define HTT_RX_PEER_EXTENDED_VDEV_ID_M 0xff000000
  13499. #define HTT_RX_PEER_EXTENDED_VDEV_ID_S 24
  13500. #define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_M 0xffffffff
  13501. #define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_S 0
  13502. #define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_M 0x0000ffff
  13503. #define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_S 0
  13504. #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M 0x00070000
  13505. #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S 16
  13506. #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M 0x00080000
  13507. #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S 19
  13508. #define HTT_RX_PEER_EXTENDED_PEER_ID_SET(word, value) \
  13509. do { \
  13510. HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \
  13511. (word) |= (value) << HTT_RX_PEER_EXTENDED_PEER_ID_S; \
  13512. } while (0)
  13513. #define HTT_RX_PEER_EXTENDED_PEER_ID_GET(word) \
  13514. (((word) & HTT_RX_PEER_EXTENDED_PEER_ID_M) >> HTT_RX_PEER_EXTENDED_PEER_ID_S)
  13515. #define HTT_RX_PEER_EXTENDED_VDEV_ID_SET(word, value) \
  13516. do { \
  13517. HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_VDEV_ID, value); \
  13518. (word) |= (value) << HTT_RX_PEER_EXTENDED_VDEV_ID_S; \
  13519. } while (0)
  13520. #define HTT_RX_PEER_EXTENDED_VDEV_ID_GET(word) \
  13521. (((word) & HTT_RX_PEER_EXTENDED_VDEV_ID_M) >> HTT_RX_PEER_EXTENDED_VDEV_ID_S)
  13522. #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_SET(word, value) \
  13523. do { \
  13524. HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID, value); \
  13525. (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S; \
  13526. } while (0)
  13527. #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_GET(word) \
  13528. (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S)
  13529. #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_SET(word, value) \
  13530. do { \
  13531. HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID, value); \
  13532. (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S; \
  13533. } while (0)
  13534. #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_GET(word) \
  13535. (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S)
  13536. #define HTT_RX_PEER_EXTENDED_MAC_ADDR_OFFSET 4 /* bytes */
  13537. #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_OFFSET 8 /* bytes */
  13538. #define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_OFFSET 8 /* bytes */
  13539. #define HTT_RX_PEER_EXTENDED_EVENT_BYTES 20 /* bytes */
  13540. /**
  13541. * @brief target -> host message specifying security parameters
  13542. *
  13543. * MSG_TYPE => HTT_T2H_MSG_TYPE_SEC_IND
  13544. *
  13545. * @details
  13546. * The following diagram shows the format of the security specification
  13547. * message sent from the target to the host.
  13548. * This security specification message tells the host whether a PN check is
  13549. * necessary on rx data frames, and if so, how large the PN counter is.
  13550. * This message also tells the host about the security processing to apply
  13551. * to defragmented rx frames - specifically, whether a Message Integrity
  13552. * Check is required, and the Michael key to use.
  13553. *
  13554. * |31 24|23 16|15|14 8|7 0|
  13555. * |-----------------------------------------------------------------------|
  13556. * | peer ID | U| security type | msg type |
  13557. * |-----------------------------------------------------------------------|
  13558. * | Michael Key K0 |
  13559. * |-----------------------------------------------------------------------|
  13560. * | Michael Key K1 |
  13561. * |-----------------------------------------------------------------------|
  13562. * | WAPI RSC Low0 |
  13563. * |-----------------------------------------------------------------------|
  13564. * | WAPI RSC Low1 |
  13565. * |-----------------------------------------------------------------------|
  13566. * | WAPI RSC Hi0 |
  13567. * |-----------------------------------------------------------------------|
  13568. * | WAPI RSC Hi1 |
  13569. * |-----------------------------------------------------------------------|
  13570. *
  13571. * The following field definitions describe the format of the security
  13572. * indication message sent from the target to the host.
  13573. * - MSG_TYPE
  13574. * Bits 7:0
  13575. * Purpose: identifies this as a security specification message
  13576. * Value: 0xb (HTT_T2H_MSG_TYPE_SEC_IND)
  13577. * - SEC_TYPE
  13578. * Bits 14:8
  13579. * Purpose: specifies which type of security applies to the peer
  13580. * Value: htt_sec_type enum value
  13581. * - UNICAST
  13582. * Bit 15
  13583. * Purpose: whether this security is applied to unicast or multicast data
  13584. * Value: 1 -> unicast, 0 -> multicast
  13585. * - PEER_ID
  13586. * Bits 31:16
  13587. * Purpose: The ID number for the peer the security specification is for
  13588. * Value: peer ID
  13589. * - MICHAEL_KEY_K0
  13590. * Bits 31:0
  13591. * Purpose: 4-byte word that forms the 1st half of the TKIP Michael key
  13592. * Value: Michael Key K0 (if security type is TKIP)
  13593. * - MICHAEL_KEY_K1
  13594. * Bits 31:0
  13595. * Purpose: 4-byte word that forms the 2nd half of the TKIP Michael key
  13596. * Value: Michael Key K1 (if security type is TKIP)
  13597. * - WAPI_RSC_LOW0
  13598. * Bits 31:0
  13599. * Purpose: 4-byte word that forms the 1st quarter of the 16 byte WAPI RSC
  13600. * Value: WAPI RSC Low0 (if security type is WAPI)
  13601. * - WAPI_RSC_LOW1
  13602. * Bits 31:0
  13603. * Purpose: 4-byte word that forms the 2nd quarter of the 16 byte WAPI RSC
  13604. * Value: WAPI RSC Low1 (if security type is WAPI)
  13605. * - WAPI_RSC_HI0
  13606. * Bits 31:0
  13607. * Purpose: 4-byte word that forms the 3rd quarter of the 16 byte WAPI RSC
  13608. * Value: WAPI RSC Hi0 (if security type is WAPI)
  13609. * - WAPI_RSC_HI1
  13610. * Bits 31:0
  13611. * Purpose: 4-byte word that forms the 4th quarter of the 16 byte WAPI RSC
  13612. * Value: WAPI RSC Hi1 (if security type is WAPI)
  13613. */
  13614. #define HTT_SEC_IND_SEC_TYPE_M 0x00007f00
  13615. #define HTT_SEC_IND_SEC_TYPE_S 8
  13616. #define HTT_SEC_IND_UNICAST_M 0x00008000
  13617. #define HTT_SEC_IND_UNICAST_S 15
  13618. #define HTT_SEC_IND_PEER_ID_M 0xffff0000
  13619. #define HTT_SEC_IND_PEER_ID_S 16
  13620. #define HTT_SEC_IND_SEC_TYPE_SET(word, value) \
  13621. do { \
  13622. HTT_CHECK_SET_VAL(HTT_SEC_IND_SEC_TYPE, value); \
  13623. (word) |= (value) << HTT_SEC_IND_SEC_TYPE_S; \
  13624. } while (0)
  13625. #define HTT_SEC_IND_SEC_TYPE_GET(word) \
  13626. (((word) & HTT_SEC_IND_SEC_TYPE_M) >> HTT_SEC_IND_SEC_TYPE_S)
  13627. #define HTT_SEC_IND_UNICAST_SET(word, value) \
  13628. do { \
  13629. HTT_CHECK_SET_VAL(HTT_SEC_IND_UNICAST, value); \
  13630. (word) |= (value) << HTT_SEC_IND_UNICAST_S; \
  13631. } while (0)
  13632. #define HTT_SEC_IND_UNICAST_GET(word) \
  13633. (((word) & HTT_SEC_IND_UNICAST_M) >> HTT_SEC_IND_UNICAST_S)
  13634. #define HTT_SEC_IND_PEER_ID_SET(word, value) \
  13635. do { \
  13636. HTT_CHECK_SET_VAL(HTT_SEC_IND_PEER_ID, value); \
  13637. (word) |= (value) << HTT_SEC_IND_PEER_ID_S; \
  13638. } while (0)
  13639. #define HTT_SEC_IND_PEER_ID_GET(word) \
  13640. (((word) & HTT_SEC_IND_PEER_ID_M) >> HTT_SEC_IND_PEER_ID_S)
  13641. #define HTT_SEC_IND_BYTES 28
  13642. /**
  13643. * @brief target -> host rx ADDBA / DELBA message definitions
  13644. *
  13645. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_ADDBA
  13646. *
  13647. * @details
  13648. * The following diagram shows the format of the rx ADDBA message sent
  13649. * from the target to the host:
  13650. *
  13651. * |31 20|19 16|15 8|7 0|
  13652. * |---------------------------------------------------------------------|
  13653. * | peer ID | TID | window size | msg type |
  13654. * |---------------------------------------------------------------------|
  13655. *
  13656. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DELBA
  13657. *
  13658. * The following diagram shows the format of the rx DELBA message sent
  13659. * from the target to the host:
  13660. *
  13661. * |31 20|19 16|15 10|9 8|7 0|
  13662. * |---------------------------------------------------------------------|
  13663. * | peer ID | TID | window size | IR| msg type |
  13664. * |---------------------------------------------------------------------|
  13665. *
  13666. * The following field definitions describe the format of the rx ADDBA
  13667. * and DELBA messages sent from the target to the host.
  13668. * - MSG_TYPE
  13669. * Bits 7:0
  13670. * Purpose: identifies this as an rx ADDBA or DELBA message
  13671. * Value: ADDBA -> 0x5 (HTT_T2H_MSG_TYPE_RX_ADDBA),
  13672. * DELBA -> 0x6 (HTT_T2H_MSG_TYPE_RX_DELBA)
  13673. * - IR (initiator / recipient)
  13674. * Bits 9:8 (DELBA only)
  13675. * Purpose: specify whether the DELBA handshake was initiated by the
  13676. * local STA/AP, or by the peer STA/AP
  13677. * Value:
  13678. * 0 - unspecified
  13679. * 1 - initiator (a.k.a. originator)
  13680. * 2 - recipient (a.k.a. responder)
  13681. * 3 - unused / reserved
  13682. * - WIN_SIZE
  13683. * Bits 15:8 for ADDBA, bits 15:10 for DELBA
  13684. * Purpose: Specifies the length of the block ack window (max = 64).
  13685. * Value:
  13686. * block ack window length specified by the received ADDBA/DELBA
  13687. * management message.
  13688. * - TID
  13689. * Bits 19:16
  13690. * Purpose: Specifies which traffic identifier the ADDBA / DELBA is for.
  13691. * Value:
  13692. * TID specified by the received ADDBA or DELBA management message.
  13693. * - PEER_ID
  13694. * Bits 31:20
  13695. * Purpose: Identifies which peer sent the ADDBA / DELBA.
  13696. * Value:
  13697. * ID (hash value) used by the host for fast, direct lookup of
  13698. * host SW peer info, including rx reorder states.
  13699. */
  13700. #define HTT_RX_ADDBA_WIN_SIZE_M 0xff00
  13701. #define HTT_RX_ADDBA_WIN_SIZE_S 8
  13702. #define HTT_RX_ADDBA_TID_M 0xf0000
  13703. #define HTT_RX_ADDBA_TID_S 16
  13704. #define HTT_RX_ADDBA_PEER_ID_M 0xfff00000
  13705. #define HTT_RX_ADDBA_PEER_ID_S 20
  13706. #define HTT_RX_ADDBA_WIN_SIZE_SET(word, value) \
  13707. do { \
  13708. HTT_CHECK_SET_VAL(HTT_RX_ADDBA_WIN_SIZE, value); \
  13709. (word) |= (value) << HTT_RX_ADDBA_WIN_SIZE_S; \
  13710. } while (0)
  13711. #define HTT_RX_ADDBA_WIN_SIZE_GET(word) \
  13712. (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S)
  13713. #define HTT_RX_ADDBA_TID_SET(word, value) \
  13714. do { \
  13715. HTT_CHECK_SET_VAL(HTT_RX_ADDBA_TID, value); \
  13716. (word) |= (value) << HTT_RX_ADDBA_TID_S; \
  13717. } while (0)
  13718. #define HTT_RX_ADDBA_TID_GET(word) \
  13719. (((word) & HTT_RX_ADDBA_TID_M) >> HTT_RX_ADDBA_TID_S)
  13720. #define HTT_RX_ADDBA_PEER_ID_SET(word, value) \
  13721. do { \
  13722. HTT_CHECK_SET_VAL(HTT_RX_ADDBA_PEER_ID, value); \
  13723. (word) |= (value) << HTT_RX_ADDBA_PEER_ID_S; \
  13724. } while (0)
  13725. #define HTT_RX_ADDBA_PEER_ID_GET(word) \
  13726. (((word) & HTT_RX_ADDBA_PEER_ID_M) >> HTT_RX_ADDBA_PEER_ID_S)
  13727. #define HTT_RX_ADDBA_BYTES 4
  13728. #define HTT_RX_DELBA_INITIATOR_M 0x00000300
  13729. #define HTT_RX_DELBA_INITIATOR_S 8
  13730. #define HTT_RX_DELBA_WIN_SIZE_M 0x0000FC00
  13731. #define HTT_RX_DELBA_WIN_SIZE_S 10
  13732. #define HTT_RX_DELBA_TID_M HTT_RX_ADDBA_TID_M
  13733. #define HTT_RX_DELBA_TID_S HTT_RX_ADDBA_TID_S
  13734. #define HTT_RX_DELBA_PEER_ID_M HTT_RX_ADDBA_PEER_ID_M
  13735. #define HTT_RX_DELBA_PEER_ID_S HTT_RX_ADDBA_PEER_ID_S
  13736. #define HTT_RX_DELBA_TID_SET HTT_RX_ADDBA_TID_SET
  13737. #define HTT_RX_DELBA_TID_GET HTT_RX_ADDBA_TID_GET
  13738. #define HTT_RX_DELBA_PEER_ID_SET HTT_RX_ADDBA_PEER_ID_SET
  13739. #define HTT_RX_DELBA_PEER_ID_GET HTT_RX_ADDBA_PEER_ID_GET
  13740. #define HTT_RX_DELBA_INITIATOR_SET(word, value) \
  13741. do { \
  13742. HTT_CHECK_SET_VAL(HTT_RX_DELBA_INITIATOR, value); \
  13743. (word) |= (value) << HTT_RX_DELBA_INITIATOR_S; \
  13744. } while (0)
  13745. #define HTT_RX_DELBA_INITIATOR_GET(word) \
  13746. (((word) & HTT_RX_DELBA_INITIATOR_M) >> HTT_RX_DELBA_INITIATOR_S)
  13747. #define HTT_RX_DELBA_WIN_SIZE_SET(word, value) \
  13748. do { \
  13749. HTT_CHECK_SET_VAL(HTT_RX_DELBA_WIN_SIZE, value); \
  13750. (word) |= (value) << HTT_RX_DELBA_WIN_SIZE_S; \
  13751. } while (0)
  13752. #define HTT_RX_DELBA_WIN_SIZE_GET(word) \
  13753. (((word) & HTT_RX_DELBA_WIN_SIZE_M) >> HTT_RX_DELBA_WIN_SIZE_S)
  13754. #define HTT_RX_DELBA_BYTES 4
  13755. /**
  13756. * @brief target -> host rx ADDBA / DELBA message definitions
  13757. *
  13758. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN
  13759. *
  13760. * @details
  13761. * The following diagram shows the format of the rx ADDBA extn message sent
  13762. * from the target to the host:
  13763. *
  13764. * |31 20|19 16|15 13|12 8|7 0|
  13765. * |---------------------------------------------------------------------|
  13766. * | peer ID | TID | reserved | msg type |
  13767. * |---------------------------------------------------------------------|
  13768. * | reserved | window size |
  13769. * |---------------------------------------------------------------------|
  13770. *
  13771. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DELBA_EXTN
  13772. *
  13773. * The following diagram shows the format of the rx DELBA message sent
  13774. * from the target to the host:
  13775. *
  13776. * |31 20|19 16|15 13|12 10|9 8|7 0|
  13777. * |---------------------------------------------------------------------|
  13778. * | peer ID | TID | reserved | IR| msg type |
  13779. * |---------------------------------------------------------------------|
  13780. * | reserved | window size |
  13781. * |---------------------------------------------------------------------|
  13782. *
  13783. * The following field definitions describe the format of the rx ADDBA
  13784. * and DELBA messages sent from the target to the host.
  13785. * - MSG_TYPE
  13786. * Bits 7:0
  13787. * Purpose: identifies this as an rx ADDBA or DELBA message
  13788. * Value: ADDBA -> 0x31 (HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN),
  13789. * DELBA -> 0x32 (HTT_T2H_MSG_TYPE_RX_DELBA_EXTN)
  13790. * - IR (initiator / recipient)
  13791. * Bits 9:8 (DELBA only)
  13792. * Purpose: specify whether the DELBA handshake was initiated by the
  13793. * local STA/AP, or by the peer STA/AP
  13794. * Value:
  13795. * 0 - unspecified
  13796. * 1 - initiator (a.k.a. originator)
  13797. * 2 - recipient (a.k.a. responder)
  13798. * 3 - unused / reserved
  13799. * Value:
  13800. * block ack window length specified by the received ADDBA/DELBA
  13801. * management message.
  13802. * - TID
  13803. * Bits 19:16
  13804. * Purpose: Specifies which traffic identifier the ADDBA / DELBA is for.
  13805. * Value:
  13806. * TID specified by the received ADDBA or DELBA management message.
  13807. * - PEER_ID
  13808. * Bits 31:20
  13809. * Purpose: Identifies which peer sent the ADDBA / DELBA.
  13810. * Value:
  13811. * ID (hash value) used by the host for fast, direct lookup of
  13812. * host SW peer info, including rx reorder states.
  13813. * == DWORD 1
  13814. * - WIN_SIZE
  13815. * Bits 12:0 for ADDBA, bits 12:0 for DELBA
  13816. * Purpose: Specifies the length of the block ack window (max = 8191).
  13817. */
  13818. #define HTT_RX_ADDBA_EXTN_TID_M 0xf0000
  13819. #define HTT_RX_ADDBA_EXTN_TID_S 16
  13820. #define HTT_RX_ADDBA_EXTN_PEER_ID_M 0xfff00000
  13821. #define HTT_RX_ADDBA_EXTN_PEER_ID_S 20
  13822. /*--- Dword 0 ---*/
  13823. #define HTT_RX_ADDBA_EXTN_TID_SET(word, value) \
  13824. do { \
  13825. HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_TID, value); \
  13826. (word) |= (value) << HTT_RX_ADDBA_EXTN_TID_S; \
  13827. } while (0)
  13828. #define HTT_RX_ADDBA_EXTN_TID_GET(word) \
  13829. (((word) & HTT_RX_ADDBA_EXTN_TID_M) >> HTT_RX_ADDBA_EXTN_TID_S)
  13830. #define HTT_RX_ADDBA_EXTN_PEER_ID_SET(word, value) \
  13831. do { \
  13832. HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_PEER_ID, value); \
  13833. (word) |= (value) << HTT_RX_ADDBA_EXTN_PEER_ID_S; \
  13834. } while (0)
  13835. #define HTT_RX_ADDBA_EXTN_PEER_ID_GET(word) \
  13836. (((word) & HTT_RX_ADDBA_EXTN_PEER_ID_M) >> HTT_RX_ADDBA_EXTN_PEER_ID_S)
  13837. /*--- Dword 1 ---*/
  13838. #define HTT_RX_ADDBA_EXTN_WIN_SIZE_M 0x1fff
  13839. #define HTT_RX_ADDBA_EXTN_WIN_SIZE_S 0
  13840. #define HTT_RX_ADDBA_EXTN_WIN_SIZE_SET(word, value) \
  13841. do { \
  13842. HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_WIN_SIZE, value); \
  13843. (word) |= (value) << HTT_RX_ADDBA_EXTN_WIN_SIZE_S; \
  13844. } while (0)
  13845. #define HTT_RX_ADDBA_EXTN_WIN_SIZE_GET(word) \
  13846. (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S)
  13847. #define HTT_RX_ADDBA_EXTN_BYTES 8
  13848. #define HTT_RX_DELBA_EXTN_INITIATOR_M 0x00000300
  13849. #define HTT_RX_DELBA_EXTN_INITIATOR_S 8
  13850. #define HTT_RX_DELBA_EXTN_TID_M 0xf0000
  13851. #define HTT_RX_DELBA_EXTN_TID_S 16
  13852. #define HTT_RX_DELBA_EXTN_PEER_ID_M 0xfff00000
  13853. #define HTT_RX_DELBA_EXTN_PEER_ID_S 20
  13854. /*--- Dword 0 ---*/
  13855. #define HTT_RX_DELBA_INITIATOR_SET(word, value) \
  13856. do { \
  13857. HTT_CHECK_SET_VAL(HTT_RX_DELBA_INITIATOR, value); \
  13858. (word) |= (value) << HTT_RX_DELBA_INITIATOR_S; \
  13859. } while (0)
  13860. #define HTT_RX_DELBA_INITIATOR_GET(word) \
  13861. (((word) & HTT_RX_DELBA_INITIATOR_M) >> HTT_RX_DELBA_INITIATOR_S)
  13862. #define HTT_RX_DELBA_EXTN_TID_SET(word, value) \
  13863. do { \
  13864. HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_TID, value); \
  13865. (word) |= (value) << HTT_RX_DELBA_EXTN_TID_S; \
  13866. } while (0)
  13867. #define HTT_RX_DELBA_EXTN_TID_GET(word) \
  13868. (((word) & HTT_RX_DELBA_EXTN_TID_M) >> HTT_RX_DELBA_EXTN_TID_S)
  13869. #define HTT_RX_DELBA_EXTN_PEER_ID_SET(word, value) \
  13870. do { \
  13871. HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_PEER_ID, value); \
  13872. (word) |= (value) << HTT_RX_DELBA_EXTN_PEER_ID_S; \
  13873. } while (0)
  13874. #define HTT_RX_DELBA_EXTN_PEER_ID_GET(word) \
  13875. (((word) & HTT_RX_DELBA_EXTN_PEER_ID_M) >> HTT_RX_DELBA_EXTN_PEER_ID_S)
  13876. /*--- Dword 1 ---*/
  13877. #define HTT_RX_DELBA_EXTN_WIN_SIZE_M 0x1fff
  13878. #define HTT_RX_DELBA_EXTN_WIN_SIZE_S 0
  13879. #define HTT_RX_DELBA_EXTN_WIN_SIZE_SET(word, value) \
  13880. do { \
  13881. HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_WIN_SIZE, value); \
  13882. (word) |= (value) << HTT_RX_DELBA_EXTN_WIN_SIZE_S; \
  13883. } while (0)
  13884. #define HTT_RX_DELBA_EXTN_WIN_SIZE_GET(word) \
  13885. (((word) & HTT_RX_DELBA_EXTN_WIN_SIZE_M) >> HTT_RX_DELBA_EXTN_WIN_SIZE_S)
  13886. #define HTT_RX_DELBA_EXTN_BYTES 8
  13887. /**
  13888. * @brief tx queue group information element definition
  13889. *
  13890. * @details
  13891. * The following diagram shows the format of the tx queue group
  13892. * information element, which can be included in target --> host
  13893. * messages to specify the number of tx "credits" (tx descriptors
  13894. * for LL, or tx buffers for HL) available to a particular group
  13895. * of host-side tx queues, and which host-side tx queues belong to
  13896. * the group.
  13897. *
  13898. * |31|30 24|23 16|15|14|13 0|
  13899. * |------------------------------------------------------------------------|
  13900. * | X| reserved | tx queue grp ID | A| S| credit count |
  13901. * |------------------------------------------------------------------------|
  13902. * | vdev ID mask | AC mask |
  13903. * |------------------------------------------------------------------------|
  13904. *
  13905. * The following definitions describe the fields within the tx queue group
  13906. * information element:
  13907. * - credit_count
  13908. * Bits 13:1
  13909. * Purpose: specify how many tx credits are available to the tx queue group
  13910. * Value: An absolute or relative, positive or negative credit value
  13911. * The 'A' bit specifies whether the value is absolute or relative.
  13912. * The 'S' bit specifies whether the value is positive or negative.
  13913. * A negative value can only be relative, not absolute.
  13914. * An absolute value replaces any prior credit value the host has for
  13915. * the tx queue group in question.
  13916. * A relative value is added to the prior credit value the host has for
  13917. * the tx queue group in question.
  13918. * - sign
  13919. * Bit 14
  13920. * Purpose: specify whether the credit count is positive or negative
  13921. * Value: 0 -> positive, 1 -> negative
  13922. * - absolute
  13923. * Bit 15
  13924. * Purpose: specify whether the credit count is absolute or relative
  13925. * Value: 0 -> relative, 1 -> absolute
  13926. * - txq_group_id
  13927. * Bits 23:16
  13928. * Purpose: indicate which tx queue group's credit and/or membership are
  13929. * being specified
  13930. * Value: 0 to max_tx_queue_groups-1
  13931. * - reserved
  13932. * Bits 30:16
  13933. * Value: 0x0
  13934. * - eXtension
  13935. * Bit 31
  13936. * Purpose: specify whether another tx queue group info element follows
  13937. * Value: 0 -> no more tx queue group information elements
  13938. * 1 -> another tx queue group information element immediately follows
  13939. * - ac_mask
  13940. * Bits 15:0
  13941. * Purpose: specify which Access Categories belong to the tx queue group
  13942. * Value: bit-OR of masks for the ACs (WMM and extension) that belong to
  13943. * the tx queue group.
  13944. * The AC bit-mask values are obtained by left-shifting by the
  13945. * corresponding HTT_AC_WMM enum values, e.g. (1 << HTT_AC_WMM_BE) == 0x1
  13946. * - vdev_id_mask
  13947. * Bits 31:16
  13948. * Purpose: specify which vdev's tx queues belong to the tx queue group
  13949. * Value: bit-OR of masks based on the IDs of the vdevs whose tx queues
  13950. * belong to the tx queue group.
  13951. * For example, if vdev IDs 1 and 4 belong to a tx queue group, the
  13952. * vdev_id_mask would be (1 << 1) | (1 << 4) = 0x12
  13953. */
  13954. PREPACK struct htt_txq_group {
  13955. A_UINT32
  13956. credit_count: 14,
  13957. sign: 1,
  13958. absolute: 1,
  13959. tx_queue_group_id: 8,
  13960. reserved0: 7,
  13961. extension: 1;
  13962. A_UINT32
  13963. ac_mask: 16,
  13964. vdev_id_mask: 16;
  13965. } POSTPACK;
  13966. /* first word */
  13967. #define HTT_TXQ_GROUP_CREDIT_COUNT_S 0
  13968. #define HTT_TXQ_GROUP_CREDIT_COUNT_M 0x00003fff
  13969. #define HTT_TXQ_GROUP_SIGN_S 14
  13970. #define HTT_TXQ_GROUP_SIGN_M 0x00004000
  13971. #define HTT_TXQ_GROUP_ABS_S 15
  13972. #define HTT_TXQ_GROUP_ABS_M 0x00008000
  13973. #define HTT_TXQ_GROUP_ID_S 16
  13974. #define HTT_TXQ_GROUP_ID_M 0x00ff0000
  13975. #define HTT_TXQ_GROUP_EXT_S 31
  13976. #define HTT_TXQ_GROUP_EXT_M 0x80000000
  13977. /* second word */
  13978. #define HTT_TXQ_GROUP_AC_MASK_S 0
  13979. #define HTT_TXQ_GROUP_AC_MASK_M 0x0000ffff
  13980. #define HTT_TXQ_GROUP_VDEV_ID_MASK_S 16
  13981. #define HTT_TXQ_GROUP_VDEV_ID_MASK_M 0xffff0000
  13982. #define HTT_TXQ_GROUP_CREDIT_COUNT_SET(_info, _val) \
  13983. do { \
  13984. HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_CREDIT_COUNT, _val); \
  13985. ((_info) |= ((_val) << HTT_TXQ_GROUP_CREDIT_COUNT_S)); \
  13986. } while (0)
  13987. #define HTT_TXQ_GROUP_CREDIT_COUNT_GET(_info) \
  13988. (((_info) & HTT_TXQ_GROUP_CREDIT_COUNT_M) >> HTT_TXQ_GROUP_CREDIT_COUNT_S)
  13989. #define HTT_TXQ_GROUP_SIGN_SET(_info, _val) \
  13990. do { \
  13991. HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_SIGN, _val); \
  13992. ((_info) |= ((_val) << HTT_TXQ_GROUP_SIGN_S)); \
  13993. } while (0)
  13994. #define HTT_TXQ_GROUP_SIGN_GET(_info) \
  13995. (((_info) & HTT_TXQ_GROUP_SIGN_M) >> HTT_TXQ_GROUP_SIGN_S)
  13996. #define HTT_TXQ_GROUP_ABS_SET(_info, _val) \
  13997. do { \
  13998. HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ABS, _val); \
  13999. ((_info) |= ((_val) << HTT_TXQ_GROUP_ABS_S)); \
  14000. } while (0)
  14001. #define HTT_TXQ_GROUP_ABS_GET(_info) \
  14002. (((_info) & HTT_TXQ_GROUP_ABS_M) >> HTT_TXQ_GROUP_ABS_S)
  14003. #define HTT_TXQ_GROUP_ID_SET(_info, _val) \
  14004. do { \
  14005. HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ID, _val); \
  14006. ((_info) |= ((_val) << HTT_TXQ_GROUP_ID_S)); \
  14007. } while (0)
  14008. #define HTT_TXQ_GROUP_ID_GET(_info) \
  14009. (((_info) & HTT_TXQ_GROUP_ID_M) >> HTT_TXQ_GROUP_ID_S)
  14010. #define HTT_TXQ_GROUP_EXT_SET(_info, _val) \
  14011. do { \
  14012. HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_EXT, _val); \
  14013. ((_info) |= ((_val) << HTT_TXQ_GROUP_EXT_S)); \
  14014. } while (0)
  14015. #define HTT_TXQ_GROUP_EXT_GET(_info) \
  14016. (((_info) & HTT_TXQ_GROUP_EXT_M) >> HTT_TXQ_GROUP_EXT_S)
  14017. #define HTT_TXQ_GROUP_AC_MASK_SET(_info, _val) \
  14018. do { \
  14019. HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_AC_MASK, _val); \
  14020. ((_info) |= ((_val) << HTT_TXQ_GROUP_AC_MASK_S)); \
  14021. } while (0)
  14022. #define HTT_TXQ_GROUP_AC_MASK_GET(_info) \
  14023. (((_info) & HTT_TXQ_GROUP_AC_MASK_M) >> HTT_TXQ_GROUP_AC_MASK_S)
  14024. #define HTT_TXQ_GROUP_VDEV_ID_MASK_SET(_info, _val) \
  14025. do { \
  14026. HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_VDEV_ID_MASK, _val); \
  14027. ((_info) |= ((_val) << HTT_TXQ_GROUP_VDEV_ID_MASK_S)); \
  14028. } while (0)
  14029. #define HTT_TXQ_GROUP_VDEV_ID_MASK_GET(_info) \
  14030. (((_info) & HTT_TXQ_GROUP_VDEV_ID_MASK_M) >> HTT_TXQ_GROUP_VDEV_ID_MASK_S)
  14031. /**
  14032. * @brief target -> host TX completion indication message definition
  14033. *
  14034. * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_COMPL_IND
  14035. *
  14036. * @details
  14037. * The following diagram shows the format of the TX completion indication sent
  14038. * from the target to the host
  14039. *
  14040. * |31 30|29|28|27|26|25|24|23 16| 15 |14 11|10 8|7 0|
  14041. * |-------------------------------------------------------------------|
  14042. * header: |rsvd |A4|A3|A2|TP|A1|A0| num | t_i| tid |status| msg_type |
  14043. * |-------------------------------------------------------------------|
  14044. * payload:| MSDU1 ID | MSDU0 ID |
  14045. * |-------------------------------------------------------------------|
  14046. * : MSDU3 ID | MSDU2 ID :
  14047. * |-------------------------------------------------------------------|
  14048. * | struct htt_tx_compl_ind_append_retries |
  14049. * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
  14050. * | struct htt_tx_compl_ind_append_tx_tstamp |
  14051. * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
  14052. * | MSDU1 ACK RSSI | MSDU0 ACK RSSI |
  14053. * |-------------------------------------------------------------------|
  14054. * : MSDU3 ACK RSSI | MSDU2 ACK RSSI :
  14055. * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
  14056. * | MSDU0 tx_tsf64_low |
  14057. * |-------------------------------------------------------------------|
  14058. * | MSDU0 tx_tsf64_high |
  14059. * |-------------------------------------------------------------------|
  14060. * | MSDU1 tx_tsf64_low |
  14061. * |-------------------------------------------------------------------|
  14062. * | MSDU1 tx_tsf64_high |
  14063. * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
  14064. * | phy_timestamp |
  14065. * |-------------------------------------------------------------------|
  14066. * | rate specs (see below) |
  14067. * |-------------------------------------------------------------------|
  14068. * | seqctrl | framectrl |
  14069. * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
  14070. * Where:
  14071. * A0 = append (a.k.a. append0)
  14072. * A1 = append1
  14073. * TP = MSDU tx power presence
  14074. * A2 = append2
  14075. * A3 = append3
  14076. * A4 = append4
  14077. *
  14078. * The following field definitions describe the format of the TX completion
  14079. * indication sent from the target to the host
  14080. * Header fields:
  14081. * - msg_type
  14082. * Bits 7:0
  14083. * Purpose: identifies this as HTT TX completion indication
  14084. * Value: 0x7 (HTT_T2H_MSG_TYPE_TX_COMPL_IND)
  14085. * - status
  14086. * Bits 10:8
  14087. * Purpose: the TX completion status of payload fragmentations descriptors
  14088. * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD
  14089. * - tid
  14090. * Bits 14:11
  14091. * Purpose: the tid associated with those fragmentation descriptors. It is
  14092. * valid or not, depending on the tid_invalid bit.
  14093. * Value: 0 to 15
  14094. * - tid_invalid
  14095. * Bits 15:15
  14096. * Purpose: this bit indicates whether the tid field is valid or not
  14097. * Value: 0 indicates valid; 1 indicates invalid
  14098. * - num
  14099. * Bits 23:16
  14100. * Purpose: the number of payload in this indication
  14101. * Value: 1 to 255
  14102. * - append (a.k.a. append0)
  14103. * Bits 24:24
  14104. * Purpose: append the struct htt_tx_compl_ind_append_retries which contains
  14105. * the number of tx retries for one MSDU at the end of this message
  14106. * Value: 0 indicates no appending; 1 indicates appending
  14107. * - append1
  14108. * Bits 25:25
  14109. * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which
  14110. * contains the timestamp info for each TX msdu id in payload.
  14111. * The order of the timestamps matches the order of the MSDU IDs.
  14112. * Note that a big-endian host needs to account for the reordering
  14113. * of MSDU IDs within each 4-byte MSDU ID pair (during endianness
  14114. * conversion) when determining which tx timestamp corresponds to
  14115. * which MSDU ID.
  14116. * Value: 0 indicates no appending; 1 indicates appending
  14117. * - msdu_tx_power_presence
  14118. * Bits 26:26
  14119. * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report
  14120. * for each MSDU referenced by the TX_COMPL_IND message.
  14121. * The tx power is reported in 0.5 dBm units.
  14122. * The order of the per-MSDU tx power reports matches the order
  14123. * of the MSDU IDs.
  14124. * Note that a big-endian host needs to account for the reordering
  14125. * of MSDU IDs within each 4-byte MSDU ID pair (during endianness
  14126. * conversion) when determining which Tx Power corresponds to
  14127. * which MSDU ID.
  14128. * Value: 0 indicates MSDU tx power reports are not appended,
  14129. * 1 indicates MSDU tx power reports are appended
  14130. * - append2
  14131. * Bits 27:27
  14132. * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in
  14133. * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report
  14134. * matches the order of the MSDU IDs. Although the ACK RSSI is the
  14135. * same for all MSDUs within a single PPDU, the RSSI is duplicated
  14136. * for each MSDU, for convenience.
  14137. * The ACK RSSI values are valid when status is COMPLETE_OK (and
  14138. * this append2 bit is set).
  14139. * The ACK RSSI values are SNR in dB, i.e. are the RSSI in units of
  14140. * dB above the noise floor.
  14141. * Value: 0 indicates MSDU ACK RSSI values are not appended,
  14142. * 1 indicates MSDU ACK RSSI values are appended.
  14143. * - append3
  14144. * Bits 28:28
  14145. * Purpose: Append the struct htt_tx_compl_ind_append_tx_tsf64 which
  14146. * contains the tx tsf info based on wlan global TSF for
  14147. * each TX msdu id in payload.
  14148. * The order of the tx tsf matches the order of the MSDU IDs.
  14149. * The struct htt_tx_compl_ind_append_tx_tsf64 contains two 32-bits
  14150. * values to indicate the the lower 32 bits and higher 32 bits of
  14151. * the tx tsf.
  14152. * The tx_tsf64 here represents the time MSDU was acked and the
  14153. * tx_tsf64 has microseconds units.
  14154. * Value: 0 indicates no appending; 1 indicates appending
  14155. * - append4
  14156. * Bits 29:29
  14157. * Purpose: Indicate whether data frame control fields and fields required
  14158. * for radio tap header are appended for each MSDU in TX_COMP_IND
  14159. * message. The order of the this message matches the order of
  14160. * the MSDU IDs.
  14161. * Value: 0 indicates frame control fields and fields required for
  14162. * radio tap header values are not appended,
  14163. * 1 indicates frame control fields and fields required for
  14164. * radio tap header values are appended.
  14165. * Payload fields:
  14166. * - hmsdu_id
  14167. * Bits 15:0
  14168. * Purpose: this ID is used to track the Tx buffer in host
  14169. * Value: 0 to "size of host MSDU descriptor pool - 1"
  14170. */
  14171. PREPACK struct htt_tx_data_hdr_information {
  14172. A_UINT32 phy_timestamp_l32; /* word 0 [31:0] */
  14173. A_UINT32 /* word 1 */
  14174. /* preamble:
  14175. * 0-OFDM,
  14176. * 1-CCk,
  14177. * 2-HT,
  14178. * 3-VHT
  14179. */
  14180. preamble: 2, /* [1:0] */
  14181. /* mcs:
  14182. * In case of HT preamble interpret
  14183. * MCS along with NSS.
  14184. * Valid values for HT are 0 to 7.
  14185. * HT mcs 0 with NSS 2 is mcs 8.
  14186. * Valid values for VHT are 0 to 9.
  14187. */
  14188. mcs: 4, /* [5:2] */
  14189. /* rate:
  14190. * This is applicable only for
  14191. * CCK and OFDM preamble type
  14192. * rate 0: OFDM 48 Mbps,
  14193. * 1: OFDM 24 Mbps,
  14194. * 2: OFDM 12 Mbps
  14195. * 3: OFDM 6 Mbps
  14196. * 4: OFDM 54 Mbps
  14197. * 5: OFDM 36 Mbps
  14198. * 6: OFDM 18 Mbps
  14199. * 7: OFDM 9 Mbps
  14200. * rate 0: CCK 11 Mbps Long
  14201. * 1: CCK 5.5 Mbps Long
  14202. * 2: CCK 2 Mbps Long
  14203. * 3: CCK 1 Mbps Long
  14204. * 4: CCK 11 Mbps Short
  14205. * 5: CCK 5.5 Mbps Short
  14206. * 6: CCK 2 Mbps Short
  14207. */
  14208. rate : 3, /* [ 8: 6] */
  14209. rssi : 8, /* [16: 9] units=dBm */
  14210. nss : 2, /* [18:17] if nss 1 means 1ss and 2 means 2ss */
  14211. bw : 3, /* [21:19] (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) */
  14212. stbc : 1, /* [22] */
  14213. sgi : 1, /* [23] */
  14214. ldpc : 1, /* [24] */
  14215. beamformed: 1, /* [25] */
  14216. /* tx_retry_cnt:
  14217. * Indicates retry count of data tx frames provided by the host.
  14218. */
  14219. tx_retry_cnt: 6; /* [31:26] */
  14220. A_UINT32 /* word 2 */
  14221. framectrl:16, /* [15: 0] */
  14222. seqno:16; /* [31:16] */
  14223. } POSTPACK;
  14224. #define HTT_TX_COMPL_IND_STATUS_S 8
  14225. #define HTT_TX_COMPL_IND_STATUS_M 0x00000700
  14226. #define HTT_TX_COMPL_IND_TID_S 11
  14227. #define HTT_TX_COMPL_IND_TID_M 0x00007800
  14228. #define HTT_TX_COMPL_IND_TID_INV_S 15
  14229. #define HTT_TX_COMPL_IND_TID_INV_M 0x00008000
  14230. #define HTT_TX_COMPL_IND_NUM_S 16
  14231. #define HTT_TX_COMPL_IND_NUM_M 0x00ff0000
  14232. #define HTT_TX_COMPL_IND_APPEND_S 24
  14233. #define HTT_TX_COMPL_IND_APPEND_M 0x01000000
  14234. #define HTT_TX_COMPL_IND_APPEND1_S 25
  14235. #define HTT_TX_COMPL_IND_APPEND1_M 0x02000000
  14236. #define HTT_TX_COMPL_IND_TX_POWER_S 26
  14237. #define HTT_TX_COMPL_IND_TX_POWER_M 0x04000000
  14238. #define HTT_TX_COMPL_IND_APPEND2_S 27
  14239. #define HTT_TX_COMPL_IND_APPEND2_M 0x08000000
  14240. #define HTT_TX_COMPL_IND_APPEND3_S 28
  14241. #define HTT_TX_COMPL_IND_APPEND3_M 0x10000000
  14242. #define HTT_TX_COMPL_IND_APPEND4_S 29
  14243. #define HTT_TX_COMPL_IND_APPEND4_M 0x20000000
  14244. #define HTT_TX_COMPL_IND_STATUS_SET(_info, _val) \
  14245. do { \
  14246. HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_STATUS, _val); \
  14247. ((_info) |= ((_val) << HTT_TX_COMPL_IND_STATUS_S)); \
  14248. } while (0)
  14249. #define HTT_TX_COMPL_IND_STATUS_GET(_info) \
  14250. (((_info) & HTT_TX_COMPL_IND_STATUS_M) >> HTT_TX_COMPL_IND_STATUS_S)
  14251. #define HTT_TX_COMPL_IND_NUM_SET(_info, _val) \
  14252. do { \
  14253. HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_NUM, _val); \
  14254. ((_info) |= ((_val) << HTT_TX_COMPL_IND_NUM_S)); \
  14255. } while (0)
  14256. #define HTT_TX_COMPL_IND_NUM_GET(_info) \
  14257. (((_info) & HTT_TX_COMPL_IND_NUM_M) >> HTT_TX_COMPL_IND_NUM_S)
  14258. #define HTT_TX_COMPL_IND_TID_SET(_info, _val) \
  14259. do { \
  14260. HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID, _val); \
  14261. ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_S)); \
  14262. } while (0)
  14263. #define HTT_TX_COMPL_IND_TID_GET(_info) \
  14264. (((_info) & HTT_TX_COMPL_IND_TID_M) >> HTT_TX_COMPL_IND_TID_S)
  14265. #define HTT_TX_COMPL_IND_TID_INV_SET(_info, _val) \
  14266. do { \
  14267. HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID_INV, _val); \
  14268. ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_INV_S)); \
  14269. } while (0)
  14270. #define HTT_TX_COMPL_IND_TID_INV_GET(_info) \
  14271. (((_info) & HTT_TX_COMPL_IND_TID_INV_M) >> \
  14272. HTT_TX_COMPL_IND_TID_INV_S)
  14273. #define HTT_TX_COMPL_IND_APPEND_SET(_info, _val) \
  14274. do { \
  14275. HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND, _val); \
  14276. ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND_S)); \
  14277. } while (0)
  14278. #define HTT_TX_COMPL_IND_APPEND_GET(_info) \
  14279. (((_info) & HTT_TX_COMPL_IND_APPEND_M) >> HTT_TX_COMPL_IND_APPEND_S)
  14280. #define HTT_TX_COMPL_IND_APPEND1_SET(_info, _val) \
  14281. do { \
  14282. HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND1, _val); \
  14283. ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND1_S)); \
  14284. } while (0)
  14285. #define HTT_TX_COMPL_IND_APPEND1_GET(_info) \
  14286. (((_info) & HTT_TX_COMPL_IND_APPEND1_M) >> HTT_TX_COMPL_IND_APPEND1_S)
  14287. #define HTT_TX_COMPL_IND_TX_POWER_SET(_info, _val) \
  14288. do { \
  14289. HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TX_POWER, _val); \
  14290. ((_info) |= ((_val) << HTT_TX_COMPL_IND_TX_POWER_S)); \
  14291. } while (0)
  14292. #define HTT_TX_COMPL_IND_TX_POWER_GET(_info) \
  14293. (((_info) & HTT_TX_COMPL_IND_TX_POWER_M) >> HTT_TX_COMPL_IND_TX_POWER_S)
  14294. #define HTT_TX_COMPL_IND_APPEND2_SET(_info, _val) \
  14295. do { \
  14296. HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND2, _val); \
  14297. ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND2_S)); \
  14298. } while (0)
  14299. #define HTT_TX_COMPL_IND_APPEND2_GET(_info) \
  14300. (((_info) & HTT_TX_COMPL_IND_APPEND2_M) >> HTT_TX_COMPL_IND_APPEND2_S)
  14301. #define HTT_TX_COMPL_IND_APPEND3_SET(_info, _val) \
  14302. do { \
  14303. HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND3, _val); \
  14304. ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND3_S)); \
  14305. } while (0)
  14306. #define HTT_TX_COMPL_IND_APPEND3_GET(_info) \
  14307. (((_info) & HTT_TX_COMPL_IND_APPEND3_M) >> HTT_TX_COMPL_IND_APPEND3_S)
  14308. #define HTT_TX_COMPL_IND_APPEND4_SET(_info, _val) \
  14309. do { \
  14310. HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND4, _val); \
  14311. ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND4_S)); \
  14312. } while (0)
  14313. #define HTT_TX_COMPL_IND_APPEND4_GET(_info) \
  14314. (((_info) & HTT_TX_COMPL_IND_APPEND4_M) >> HTT_TX_COMPL_IND_APPEND4_S)
  14315. #define HTT_TX_COMPL_INV_TX_POWER 0xffff
  14316. #define HTT_TX_COMPL_CTXT_SZ sizeof(A_UINT16)
  14317. #define HTT_TX_COMPL_CTXT_NUM(_bytes) ((_bytes) >> 1)
  14318. #define HTT_TX_COMPL_INV_MSDU_ID 0xffff
  14319. #define HTT_TX_COMPL_IND_STAT_OK 0
  14320. /* DISCARD:
  14321. * current meaning:
  14322. * MSDUs were queued for transmission but filtered by HW or SW
  14323. * without any over the air attempts
  14324. * legacy meaning (HL Rome):
  14325. * MSDUs were discarded by the target FW without any over the air
  14326. * attempts due to lack of space
  14327. */
  14328. #define HTT_TX_COMPL_IND_STAT_DISCARD 1
  14329. /* NO_ACK:
  14330. * MSDUs were transmitted (repeatedly) but no ACK was received from the peer
  14331. */
  14332. #define HTT_TX_COMPL_IND_STAT_NO_ACK 2
  14333. /* POSTPONE:
  14334. * temporarily-undeliverable MSDUs were deleted to free up space, but should
  14335. * be downloaded again later (in the appropriate order), when they are
  14336. * deliverable.
  14337. */
  14338. #define HTT_TX_COMPL_IND_STAT_POSTPONE 3
  14339. /*
  14340. * The PEER_DEL tx completion status is used for HL cases
  14341. * where the peer the frame is for has been deleted.
  14342. * The host has already discarded its copy of the frame, but
  14343. * it still needs the tx completion to restore its credit.
  14344. */
  14345. #define HTT_TX_COMPL_IND_STAT_PEER_DEL 4
  14346. /* DROP: MSDUs dropped due to lack of space (congestion control) */
  14347. #define HTT_TX_COMPL_IND_STAT_DROP 5
  14348. #define HTT_TX_COMPL_IND_STAT_HOST_INSPECT 6
  14349. #define HTT_TX_COMPL_IND_APPEND_SET_MORE_RETRY(f) ((f) |= 0x1)
  14350. #define HTT_TX_COMPL_IND_APPEND_CLR_MORE_RETRY(f) ((f) &= (~0x1))
  14351. PREPACK struct htt_tx_compl_ind_base {
  14352. A_UINT32 hdr;
  14353. A_UINT16 payload[1/*or more*/];
  14354. } POSTPACK;
  14355. PREPACK struct htt_tx_compl_ind_append_retries {
  14356. A_UINT16 msdu_id;
  14357. A_UINT8 tx_retries;
  14358. A_UINT8 flag; /* Bit 0, 1: another append_retries struct is appended
  14359. 0: this is the last append_retries struct */
  14360. } POSTPACK;
  14361. PREPACK struct htt_tx_compl_ind_append_tx_tstamp {
  14362. A_UINT32 timestamp[1/*or more*/];
  14363. } POSTPACK;
  14364. PREPACK struct htt_tx_compl_ind_append_tx_tsf64 {
  14365. A_UINT32 tx_tsf64_low;
  14366. A_UINT32 tx_tsf64_high;
  14367. } POSTPACK;
  14368. /* htt_tx_data_hdr_information payload extension fields: */
  14369. /* DWORD zero */
  14370. #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_M 0xffffffff
  14371. #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S 0
  14372. /* DWORD one */
  14373. #define HTT_FW_TX_DATA_HDR_PREAMBLE_M 0x00000003
  14374. #define HTT_FW_TX_DATA_HDR_PREAMBLE_S 0
  14375. #define HTT_FW_TX_DATA_HDR_MCS_M 0x0000003c
  14376. #define HTT_FW_TX_DATA_HDR_MCS_S 2
  14377. #define HTT_FW_TX_DATA_HDR_RATE_M 0x000001c0
  14378. #define HTT_FW_TX_DATA_HDR_RATE_S 6
  14379. #define HTT_FW_TX_DATA_HDR_RSSI_M 0x0001fe00
  14380. #define HTT_FW_TX_DATA_HDR_RSSI_S 9
  14381. #define HTT_FW_TX_DATA_HDR_NSS_M 0x00060000
  14382. #define HTT_FW_TX_DATA_HDR_NSS_S 17
  14383. #define HTT_FW_TX_DATA_HDR_BW_M 0x00380000
  14384. #define HTT_FW_TX_DATA_HDR_BW_S 19
  14385. #define HTT_FW_TX_DATA_HDR_STBC_M 0x00400000
  14386. #define HTT_FW_TX_DATA_HDR_STBC_S 22
  14387. #define HTT_FW_TX_DATA_HDR_SGI_M 0x00800000
  14388. #define HTT_FW_TX_DATA_HDR_SGI_S 23
  14389. #define HTT_FW_TX_DATA_HDR_LDPC_M 0x01000000
  14390. #define HTT_FW_TX_DATA_HDR_LDPC_S 24
  14391. #define HTT_FW_TX_DATA_HDR_BEAMFORMED_M 0x02000000
  14392. #define HTT_FW_TX_DATA_HDR_BEAMFORMED_S 25
  14393. #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_M 0xfc000000
  14394. #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S 26
  14395. /* DWORD two */
  14396. #define HTT_FW_TX_DATA_HDR_FRAMECTRL_M 0x0000ffff
  14397. #define HTT_FW_TX_DATA_HDR_FRAMECTRL_S 0
  14398. #define HTT_FW_TX_DATA_HDR_SEQNO_M 0xffff0000
  14399. #define HTT_FW_TX_DATA_HDR_SEQNO_S 16
  14400. #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_SET(word, value) \
  14401. do { \
  14402. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32, value); \
  14403. (word) |= (value) << HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S; \
  14404. } while (0)
  14405. #define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_GET(word) \
  14406. (((word) & HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_M) >> HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S)
  14407. #define HTT_FW_TX_DATA_HDR_PREAMBLE_SET(word, value) \
  14408. do { \
  14409. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_PREAMBLE, value); \
  14410. (word) |= (value) << HTT_FW_TX_DATA_HDR_PREAMBLE_S; \
  14411. } while (0)
  14412. #define HTT_FW_TX_DATA_HDR_PREAMBLE_GET(word) \
  14413. (((word) & HTT_FW_TX_DATA_HDR_PREAMBLE_M) >> HTT_FW_TX_DATA_HDR_PREAMBLE_S)
  14414. #define HTT_FW_TX_DATA_HDR_MCS_SET(word, value) \
  14415. do { \
  14416. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_MCS, value); \
  14417. (word) |= (value) << HTT_FW_TX_DATA_HDR_MCS_S; \
  14418. } while (0)
  14419. #define HTT_FW_TX_DATA_HDR_MCS_GET(word) \
  14420. (((word) & HTT_FW_TX_DATA_HDR_MCS_M) >> HTT_FW_TX_DATA_HDR_MCS_S)
  14421. #define HTT_FW_TX_DATA_HDR_RATE_SET(word, value) \
  14422. do { \
  14423. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_RATE, value); \
  14424. (word) |= (value) << HTT_FW_TX_DATA_HDR_RATE_S; \
  14425. } while (0)
  14426. #define HTT_FW_TX_DATA_HDR_RATE_GET(word) \
  14427. (((word) & HTT_FW_TX_DATA_HDR_RATE_M) >> HTT_FW_TX_DATA_HDR_RATE_S)
  14428. #define HTT_FW_TX_DATA_HDR_RSSI_SET(word, value) \
  14429. do { \
  14430. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_RSSI, value); \
  14431. (word) |= (value) << HTT_FW_TX_DATA_HDR_RSSI_S; \
  14432. } while (0)
  14433. #define HTT_FW_TX_DATA_HDR_RSSI_GET(word) \
  14434. (((word) & HTT_FW_TX_DATA_HDR_RSSI_M) >> HTT_FW_TX_DATA_HDR_RSSI_S)
  14435. #define HTT_FW_TX_DATA_HDR_NSS_SET(word, value) \
  14436. do { \
  14437. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_NSS, value); \
  14438. (word) |= (value) << HTT_FW_TX_DATA_HDR_NSS_S; \
  14439. } while (0)
  14440. #define HTT_FW_TX_DATA_HDR_NSS_GET(word) \
  14441. (((word) & HTT_FW_TX_DATA_HDR_NSS_M) >> HTT_FW_TX_DATA_HDR_NSS_S)
  14442. #define HTT_FW_TX_DATA_HDR_BW_SET(word, value) \
  14443. do { \
  14444. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_BW, value); \
  14445. (word) |= (value) << HTT_FW_TX_DATA_HDR_BW_S; \
  14446. } while (0)
  14447. #define HTT_FW_TX_DATA_HDR_BW_GET(word) \
  14448. (((word) & HTT_FW_TX_DATA_HDR_BW_M) >> HTT_FW_TX_DATA_HDR_BW_S)
  14449. #define HTT_FW_TX_DATA_HDR_STBC_SET(word, value) \
  14450. do { \
  14451. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_STBC, value); \
  14452. (word) |= (value) << HTT_FW_TX_DATA_HDR_STBC_S; \
  14453. } while (0)
  14454. #define HTT_FW_TX_DATA_HDR_STBC_GET(word) \
  14455. (((word) & HTT_FW_TX_DATA_HDR_STBC_M) >> HTT_FW_TX_DATA_HDR_STBC_S)
  14456. #define HTT_FW_TX_DATA_HDR_SGI_SET(word, value) \
  14457. do { \
  14458. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_SGI, value); \
  14459. (word) |= (value) << HTT_FW_TX_DATA_HDR_SGI_S; \
  14460. } while (0)
  14461. #define HTT_FW_TX_DATA_HDR_SGI_GET(word) \
  14462. (((word) & HTT_FW_TX_DATA_HDR_SGI_M) >> HTT_FW_TX_DATA_HDR_SGI_S)
  14463. #define HTT_FW_TX_DATA_HDR_LDPC_SET(word, value) \
  14464. do { \
  14465. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_LDPC, value); \
  14466. (word) |= (value) << HTT_FW_TX_DATA_HDR_LDPC_S; \
  14467. } while (0)
  14468. #define HTT_FW_TX_DATA_HDR_LDPC_GET(word) \
  14469. (((word) & HTT_FW_TX_DATA_HDR_LDPC_M) >> HTT_FW_TX_DATA_HDR_LDPC_S)
  14470. #define HTT_FW_TX_DATA_HDR_BEAMFORMED_SET(word, value) \
  14471. do { \
  14472. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_BEAMFORMED, value); \
  14473. (word) |= (value) << HTT_FW_TX_DATA_HDR_BEAMFORMED_S; \
  14474. } while (0)
  14475. #define HTT_FW_TX_DATA_HDR_BEAMFORMED_GET(word) \
  14476. (((word) & HTT_FW_TX_DATA_HDR_BEAMFORMED_M) >> HTT_FW_TX_DATA_HDR_BEAMFORMED_S)
  14477. #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_SET(word, value) \
  14478. do { \
  14479. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_TX_RETRY_CNT, value); \
  14480. (word) |= (value) << HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S; \
  14481. } while (0)
  14482. #define HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_GET(word) \
  14483. (((word) & HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_M) >> HTT_FW_TX_DATA_HDR_TX_RETRY_CNT_S)
  14484. #define HTT_FW_TX_DATA_HDR_FRAMECTRL_SET(word, value) \
  14485. do { \
  14486. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_FRAMECTRL, value); \
  14487. (word) |= (value) << HTT_FW_TX_DATA_HDR_FRAMECTRL_S; \
  14488. } while (0)
  14489. #define HTT_FW_TX_DATA_HDR_FRAMECTRL_GET(word) \
  14490. (((word) & HTT_FW_TX_DATA_HDR_FRAMECTRL_M) >> HTT_FW_TX_DATA_HDR_FRAMECTRL_S)
  14491. #define HTT_FW_TX_DATA_HDR_SEQNO_SET(word, value) \
  14492. do { \
  14493. HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_SEQNO, value); \
  14494. (word) |= (value) << HTT_FW_TX_DATA_HDR_SEQNO_S; \
  14495. } while (0)
  14496. #define HTT_FW_TX_DATA_HDR_SEQNO_GET(word) \
  14497. (((word) & HTT_FW_TX_DATA_HDR_SEQNO_M) >> HTT_FW_TX_DATA_HDR_SEQNO_S)
  14498. /**
  14499. * @brief target -> host software UMAC TX completion indication message
  14500. *
  14501. * MSG_TYPE => HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND
  14502. *
  14503. * @details
  14504. * The following diagram shows the format of the soft UMAC TX completion
  14505. * indication sent from the target to the host
  14506. *
  14507. * |31 30|29|28|27|26 20|19 17|16|15 12|11|10| 9|8|7 4|3 1|0|
  14508. * |-------------------------------------+----------------+------------|
  14509. * hdr: | rsvd | msdu_cnt | msg_type |
  14510. * pyld: |===================================================================|
  14511. * MSDU 0| buf addr low (bits 31:0) |
  14512. * |-----------------------------------------------+------+------------|
  14513. * | SW buffer cookie | RS | buf addr hi|
  14514. * |--------+--+--+-------------+--------+---------+------+------------|
  14515. * | rsvd0 | M| V| tx count | TID | SW peer ID |
  14516. * |--------+--+--+-------------+--------+----------------------+------|
  14517. * | frametype | TQM status number | RELR |
  14518. * |-----+-----+-----------------------------------+--+-+-+-----+------|
  14519. * |rsvd1| buffer timestamp | A|L|F| ACK RSSI |
  14520. * |-----+--+-------------------------+--+------+-----+--+-+-----+---+-|
  14521. * | rsvd2 | tones in RU |OF|tx MCS|txSGI|LC|S|PKTYP|BW |I|
  14522. * |--------+-------------------------+--+------+-----+--+-+-----+---+-|
  14523. * | PPDU transmission TSF |
  14524. * |-------------------------------------------------------------------|
  14525. * | rsvd3 |
  14526. * |===================================================================|
  14527. * MSDU 1| buf addr low (bits 31:0) |
  14528. * : ... :
  14529. * | rsvd3 |
  14530. * |===================================================================|
  14531. * etc.
  14532. *
  14533. * Where:
  14534. * RS = release source
  14535. * V = valid
  14536. * M = multicast
  14537. * RELR = release reason
  14538. * F = first MSDU
  14539. * L = last MSDU
  14540. * A = MSDU is part of A-MSDU
  14541. * I = rate info valid
  14542. * PKTYP = packet type
  14543. * S = STBC
  14544. * LC = LDPC
  14545. * OF = OFDMA transmission
  14546. */
  14547. typedef enum {
  14548. /* 0 (REASON_FRAME_ACKED):
  14549. * Corresponds to tqm_release_reason = <enum 0 tqm_rr_frame_acked>;
  14550. * frame is removed because an ACK of BA for it was received.
  14551. */
  14552. HTT_TX_MSDU_RELEASE_REASON_FRAME_ACKED,
  14553. /* 1 (REASON_REMOVE_CMD_FW):
  14554. * Corresponds to tqm_release_reason = <enum 1 tqm_rr_rem_cmd_rem>;
  14555. * frame is removed because a remove command of type "Remove_mpdus"
  14556. * initiated by SW.
  14557. */
  14558. HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_FW,
  14559. /* 2 (REASON_REMOVE_CMD_TX):
  14560. * Corresponds to tqm_release_reason = <enum 2 tqm_rr_rem_cmd_tx>;
  14561. * frame is removed because a remove command of type
  14562. * "Remove_transmitted_mpdus" initiated by SW.
  14563. */
  14564. HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_TX,
  14565. /* 3 (REASON_REMOVE_CMD_NOTX):
  14566. * Corresponds to tqm_release_reason = <enum 3 tqm_rr_rem_cmd_notx>;
  14567. * frame is removed because a remove command of type
  14568. * "Remove_untransmitted_mpdus" initiated by SW.
  14569. */
  14570. HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_NOTX,
  14571. /* 4 (REASON_REMOVE_CMD_AGED):
  14572. * Corresponds to tqm_release_reason = <enum 4 tqm_rr_rem_cmd_aged>;
  14573. * frame is removed because a remove command of type "Remove_aged_mpdus"
  14574. * or "Remove_aged_msdus" initiated by SW.
  14575. */
  14576. HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_AGED,
  14577. /* 5 (RELEASE_FW_REASON1):
  14578. * Corresponds to tqm_release_reason = <enum 5 tqm_fw_reason1>;
  14579. * frame is removed because a remove command where fw indicated that
  14580. * remove reason is fw_reason1.
  14581. */
  14582. HTT_TX_MSDU_RELEASE_FW_REASON1,
  14583. /* 6 (RELEASE_FW_REASON2):
  14584. * Corresponds to tqm_release_reason = <enum 6 tqm_fw_reason2>;
  14585. * frame is removed because a remove command where fw indicated that
  14586. * remove reason is fw_reason1.
  14587. */
  14588. HTT_TX_MSDU_RELEASE_FW_REASON2,
  14589. /* 7 (RELEASE_FW_REASON3):
  14590. * Corresponds to tqm_release_reason = <enum 7 tqm_fw_reason3>;
  14591. * frame is removed because a remove command where fw indicated that
  14592. * remove reason is fw_reason1.
  14593. */
  14594. HTT_TX_MSDU_RELEASE_FW_REASON3,
  14595. /* 8 (REASON_REMOVE_CMD_DISABLEQ):
  14596. * Corresponds to tqm_release_reason = <enum 8 tqm_rr_rem_cmd_disable_queue>
  14597. * frame is removed because a remove command of type
  14598. * "remove_mpdus_and_disable_queue" or "remove_msdus_and_disable_flow"
  14599. * initiated by SW.
  14600. */
  14601. HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_DISABLEQ,
  14602. /* 9 (REASON_DROP_MISC):
  14603. * Corresponds to sw_release_reason = Packet dropped by FW due to
  14604. * any discard reason that is not categorized as MSDU TTL expired.
  14605. * Examples: TXDE ENQ layer dropped the packet due to peer delete,
  14606. * tid delete, no resource credit available.
  14607. */
  14608. HTT_TX_MSDU_RELEASE_REASON_DROP_MISC,
  14609. /* 10 (REASON_DROP_TTL):
  14610. * Corresponds to sw_release_reason = Packet dropped by FW due to
  14611. * discard reason that frame is not transmitted due to MSDU TTL expired.
  14612. */
  14613. HTT_TX_MSDU_RELEASE_REASON_DROP_TTL,
  14614. /* 11 - available for use */
  14615. /* 12 - available for use */
  14616. /* 13 - available for use */
  14617. /* 14 - available for use */
  14618. /* 15 - available for use */
  14619. HTT_TX_MSDU_RELEASE_REASON_MAX = 16
  14620. } htt_t2h_tx_msdu_release_reason_e;
  14621. typedef enum {
  14622. /* 0 (RELEASE_SOURCE_FW):
  14623. * MSDU released by FW even before the frame was queued to TQM-L HW.
  14624. */
  14625. HTT_TX_MSDU_RELEASE_SOURCE_FW,
  14626. /* 1 (RELEASE_SOURCE_TQM_LITE):
  14627. * MSDU released by TQM-L HW.
  14628. */
  14629. HTT_TX_MSDU_RELEASE_SOURCE_TQM_LITE,
  14630. HTT_TX_MSDU_RELEASE_SOURCE_MAX = 8
  14631. } htt_t2h_tx_msdu_release_source_e;
  14632. struct htt_t2h_tx_buffer_addr_info { /* 2 words */
  14633. A_UINT32 buffer_addr_31_0 : 32; /* [31:0] */
  14634. A_UINT32 buffer_addr_39_32 : 8, /* [7:0] */
  14635. /* release_source:
  14636. * holds a htt_t2h_tx_msdu_release_source_e enum value
  14637. */
  14638. release_source : 3, /* [10:8] */
  14639. sw_buffer_cookie : 21; /* [31:11] */
  14640. /* NOTE:
  14641. * To preserve backwards compatibility,
  14642. * no new fields can be added in this struct.
  14643. */
  14644. };
  14645. /* member definitions of htt_t2h_tx_buffer_addr_info */
  14646. #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M 0xFFFFFFFF
  14647. #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S 0
  14648. #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_SET(word, value) \
  14649. do { \
  14650. HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0, value); \
  14651. (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S; \
  14652. } while (0)
  14653. #define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_GET(word) \
  14654. (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S)
  14655. #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M 0x000000FF
  14656. #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S 0
  14657. #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_SET(word, value) \
  14658. do { \
  14659. HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32, value); \
  14660. (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S; \
  14661. } while (0)
  14662. #define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_GET(word) \
  14663. (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S)
  14664. #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M 0x00000700
  14665. #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S 8
  14666. #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_SET(word, value) \
  14667. do { \
  14668. HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE, value); \
  14669. (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S; \
  14670. } while (0)
  14671. #define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_GET(word) \
  14672. (((word) & HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M) >> HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S)
  14673. #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M 0xFFFFF800
  14674. #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S 11
  14675. #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_SET(word, value) \
  14676. do { \
  14677. HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE, value); \
  14678. (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S; \
  14679. } while (0)
  14680. #define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_GET(word) \
  14681. (((word) & HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M) >> HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S)
  14682. struct htt_t2h_tx_rate_stats_info { /* 2 words */
  14683. /* word 0 */
  14684. A_UINT32
  14685. /* tx_rate_stats_info_valid:
  14686. * Indicates if the tx rate stats below are valid.
  14687. */
  14688. tx_rate_stats_info_valid : 1, /* [0] */
  14689. /* transmit_bw:
  14690. * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW.
  14691. * Indicates the BW of the upcoming transmission that shall likely
  14692. * start in about 3 -4 us on the medium:
  14693. * <enum 0 transmit_bw_20_MHz>
  14694. * <enum 1 transmit_bw_40_MHz>
  14695. * <enum 2 transmit_bw_80_MHz>
  14696. * <enum 3 transmit_bw_160_MHz>
  14697. * <enum 4 transmit_bw_320_MHz>
  14698. */
  14699. transmit_bw : 3, /* [3:1] */
  14700. /* transmit_pkt_type:
  14701. * same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW.
  14702. * Field filled in by PDG.
  14703. * Not valid when in SW transmit mode
  14704. * The packet type
  14705. * <enum_type PKT_TYPE_ENUM>
  14706. * Type: enum Definition Name: PKT_TYPE_ENUM
  14707. * enum number enum name Description
  14708. * ------------------------------------
  14709. * 0 dot11a 802.11a PPDU type
  14710. * 1 dot11b 802.11b PPDU type
  14711. * 2 dot11n_mm 802.11n Mixed Mode PPDU type
  14712. * 3 dot11ac 802.11ac PPDU type
  14713. * 4 dot11ax 802.11ax PPDU type
  14714. * 5 dot11ba 802.11ba (WUR) PPDU type
  14715. * 6 dot11be 802.11be PPDU type
  14716. * 7 dot11az 802.11az (ranging) PPDU type
  14717. */
  14718. transmit_pkt_type : 4, /* [7:4] */
  14719. /* transmit_stbc:
  14720. * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW.
  14721. * Field filled in by PDG.
  14722. * Not valid when in SW transmit mode
  14723. * When set, STBC transmission rate was used.
  14724. */
  14725. transmit_stbc : 1, /* [8] */
  14726. /* transmit_ldpc:
  14727. * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW.
  14728. * Field filled in by PDG.
  14729. * Not valid when in SW transmit mode
  14730. * When set, use LDPC transmission rates
  14731. */
  14732. transmit_ldpc : 1, /* [9] */
  14733. /* transmit_sgi:
  14734. * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW.
  14735. * Field filled in by PDG.
  14736. * Not valid when in SW transmit mode
  14737. * <enum 0 0_8_us_sgi > Legacy normal GI. Can also be used for HE
  14738. * <enum 1 0_4_us_sgi > Legacy short GI. Can also be used for HE
  14739. * <enum 2 1_6_us_sgi > HE related GI
  14740. * <enum 3 3_2_us_sgi > HE related GI
  14741. * <legal 0 - 3>
  14742. */
  14743. transmit_sgi : 2, /* [11:10] */
  14744. /* transmit_mcs:
  14745. * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW.
  14746. * Field filled in by PDG.
  14747. * Not valid when in SW transmit mode
  14748. *
  14749. * For details, refer to MCS_TYPE description
  14750. * <legal all>
  14751. * Pkt_type Related definition of MCS_TYPE
  14752. * dot11b This field is the rate:
  14753. * 0: CCK 11 Mbps Long
  14754. * 1: CCK 5.5 Mbps Long
  14755. * 2: CCK 2 Mbps Long
  14756. * 3: CCK 1 Mbps Long
  14757. * 4: CCK 11 Mbps Short
  14758. * 5: CCK 5.5 Mbps Short
  14759. * 6: CCK 2 Mbps Short
  14760. * NOTE: The numbering here is NOT the same as the as MAC gives
  14761. * in the "rate" field in the SIG given to the PHY.
  14762. * The MAC will do an internal translation.
  14763. *
  14764. * Dot11a This field is the rate:
  14765. * 0: OFDM 48 Mbps
  14766. * 1: OFDM 24 Mbps
  14767. * 2: OFDM 12 Mbps
  14768. * 3: OFDM 6 Mbps
  14769. * 4: OFDM 54 Mbps
  14770. * 5: OFDM 36 Mbps
  14771. * 6: OFDM 18 Mbps
  14772. * 7: OFDM 9 Mbps
  14773. * NOTE: The numbering here is NOT the same as the as MAC gives
  14774. * in the "rate" field in the SIG given to the PHY.
  14775. * The MAC will do an internal translation.
  14776. *
  14777. * Dot11n_mm (mixed mode) This field represends the MCS.
  14778. * 0: HT MCS 0 (BPSK 1/2)
  14779. * 1: HT MCS 1 (QPSK 1/2)
  14780. * 2: HT MCS 2 (QPSK 3/4)
  14781. * 3: HT MCS 3 (16-QAM 1/2)
  14782. * 4: HT MCS 4 (16-QAM 3/4)
  14783. * 5: HT MCS 5 (64-QAM 2/3)
  14784. * 6: HT MCS 6 (64-QAM 3/4)
  14785. * 7: HT MCS 7 (64-QAM 5/6)
  14786. * NOTE: To get higher MCS's use the nss field to indicate the
  14787. * number of spatial streams.
  14788. *
  14789. * Dot11ac This field represends the MCS.
  14790. * 0: VHT MCS 0 (BPSK 1/2)
  14791. * 1: VHT MCS 1 (QPSK 1/2)
  14792. * 2: VHT MCS 2 (QPSK 3/4)
  14793. * 3: VHT MCS 3 (16-QAM 1/2)
  14794. * 4: VHT MCS 4 (16-QAM 3/4)
  14795. * 5: VHT MCS 5 (64-QAM 2/3)
  14796. * 6: VHT MCS 6 (64-QAM 3/4)
  14797. * 7: VHT MCS 7 (64-QAM 5/6)
  14798. * 8: VHT MCS 8 (256-QAM 3/4)
  14799. * 9: VHT MCS 9 (256-QAM 5/6)
  14800. * 10: VHT MCS 10 (1024-QAM 3/4)
  14801. * 11: VHT MCS 11 (1024-QAM 5/6)
  14802. * NOTE: There are several illegal VHT rates due to fractional
  14803. * number of bits per symbol.
  14804. * Below are the illegal rates for 4 streams and lower:
  14805. * 20 MHz, 1 stream, MCS 9
  14806. * 20 MHz, 2 stream, MCS 9
  14807. * 20 MHz, 4 stream, MCS 9
  14808. * 80 MHz, 3 stream, MCS 6
  14809. * 160 MHz, 3 stream, MCS 9 (Unsupported)
  14810. * 160 MHz, 4 stream, MCS 7 (Unsupported)
  14811. *
  14812. * dot11ax This field represends the MCS.
  14813. * 0: HE MCS 0 (BPSK 1/2)
  14814. * 1: HE MCS 1 (QPSK 1/2)
  14815. * 2: HE MCS 2 (QPSK 3/4)
  14816. * 3: HE MCS 3 (16-QAM 1/2)
  14817. * 4: HE MCS 4 (16-QAM 3/4)
  14818. * 5: HE MCS 5 (64-QAM 2/3)
  14819. * 6: HE MCS 6 (64-QAM 3/4)
  14820. * 7: HE MCS 7 (64-QAM 5/6)
  14821. * 8: HE MCS 8 (256-QAM 3/4)
  14822. * 9: HE MCS 9 (256-QAM 5/6)
  14823. * 10: HE MCS 10 (1024-QAM 3/4)
  14824. * 11: HE MCS 11 (1024-QAM 5/6)
  14825. * 12: HE MCS 12 (4096-QAM 3/4)
  14826. * 13: HE MCS 13 (4096-QAM 5/6)
  14827. *
  14828. * dot11ba This field is the rate:
  14829. * 0: LDR
  14830. * 1: HDR
  14831. * 2: Exclusive rate
  14832. */
  14833. transmit_mcs : 4, /* [15:12] */
  14834. /* ofdma_transmission:
  14835. * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW.
  14836. * Field filled in by PDG.
  14837. * Set when the transmission was an OFDMA transmission (DL or UL).
  14838. * <legal all>
  14839. */
  14840. ofdma_transmission : 1, /* [16] */
  14841. /* tones_in_ru:
  14842. * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW.
  14843. * Field filled in by PDG.
  14844. * Not valid when in SW transmit mode
  14845. * The number of tones in the RU used.
  14846. * <legal all>
  14847. */
  14848. tones_in_ru : 12, /* [28:17] */
  14849. rsvd2 : 3; /* [31:29] */
  14850. /* word 1 */
  14851. /* ppdu_transmission_tsf:
  14852. * Based on a HWSCH configuration register setting,
  14853. * this field either contains:
  14854. * Lower 32 bits of the TSF, snapshot of this value when transmission
  14855. * of the PPDU containing the frame finished.
  14856. * OR
  14857. * Lower 32 bits of the TSF, snapshot of this value when transmission
  14858. * of the PPDU containing the frame started.
  14859. * <legal all>
  14860. */
  14861. A_UINT32 ppdu_transmission_tsf;
  14862. /* NOTE:
  14863. * To preserve backwards compatibility,
  14864. * no new fields can be added in this struct.
  14865. */
  14866. };
  14867. /* member definitions of htt_t2h_tx_rate_stats_info */
  14868. #define HTT_TX_RATE_STATS_INFO_VALID_M 0x00000001
  14869. #define HTT_TX_RATE_STATS_INFO_VALID_S 0
  14870. #define HTT_TX_RATE_STATS_INFO_VALID_SET(word, value) \
  14871. do { \
  14872. HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_VALID, value); \
  14873. (word) |= (value) << HTT_TX_RATE_STATS_INFO_VALID_S; \
  14874. } while (0)
  14875. #define HTT_TX_RATE_STATS_INFO_VALID_GET(word) \
  14876. (((word) & HTT_TX_RATE_STATS_INFO_VALID_M) >> HTT_TX_RATE_STATS_INFO_VALID_S)
  14877. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M 0x0000000E
  14878. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S 1
  14879. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_SET(word, value) \
  14880. do { \
  14881. HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_BW, value); \
  14882. (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S; \
  14883. } while (0)
  14884. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_GET(word) \
  14885. (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S)
  14886. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M 0x000000F0
  14887. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S 4
  14888. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_SET(word, value) \
  14889. do { \
  14890. HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE, value); \
  14891. (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S; \
  14892. } while (0)
  14893. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_GET(word) \
  14894. (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S)
  14895. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M 0x00000100
  14896. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S 8
  14897. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_SET(word, value) \
  14898. do { \
  14899. HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC, value); \
  14900. (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S; \
  14901. } while (0)
  14902. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_GET(word) \
  14903. (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S)
  14904. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M 0x00000200
  14905. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S 9
  14906. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_SET(word, value) \
  14907. do { \
  14908. HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC, value); \
  14909. (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S; \
  14910. } while (0)
  14911. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_GET(word) \
  14912. (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S)
  14913. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M 0x00000C00
  14914. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S 10
  14915. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_SET(word, value) \
  14916. do { \
  14917. HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI, value); \
  14918. (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S; \
  14919. } while (0)
  14920. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_GET(word) \
  14921. (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S)
  14922. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M 0x0000F000
  14923. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S 12
  14924. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_SET(word, value) \
  14925. do { \
  14926. HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS, value); \
  14927. (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S; \
  14928. } while (0)
  14929. #define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_GET(word) \
  14930. (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S)
  14931. #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M 0x00010000
  14932. #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S 16
  14933. #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_SET(word, value) \
  14934. do { \
  14935. HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION, value); \
  14936. (word) |= (value) << HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S; \
  14937. } while (0)
  14938. #define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_GET(word) \
  14939. (((word) & HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M) >> HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S)
  14940. #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M 0x1FFE0000
  14941. #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S 17
  14942. #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_SET(word, value) \
  14943. do { \
  14944. HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TONES_IN_RU, value); \
  14945. (word) |= (value) << HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S; \
  14946. } while (0)
  14947. #define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_GET(word) \
  14948. (((word) & HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M) >> HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S)
  14949. #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M 0xFFFFFFFF
  14950. #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S 0
  14951. #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_SET(word, value) \
  14952. do { \
  14953. HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF, value); \
  14954. (word) |= (value) << HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S; \
  14955. } while (0)
  14956. #define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_GET(word) \
  14957. (((word) & HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M) >> HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S)
  14958. struct htt_t2h_tx_msdu_info { /* 8 words */
  14959. /* words 0 + 1 */
  14960. struct htt_t2h_tx_buffer_addr_info addr_info;
  14961. /* word 2 */
  14962. A_UINT32
  14963. sw_peer_id : 16,
  14964. tid : 4,
  14965. transmit_cnt : 7,
  14966. valid : 1,
  14967. mcast : 1,
  14968. rsvd0 : 3;
  14969. /* word 3 */
  14970. A_UINT32
  14971. release_reason : 4, /* Refer to htt_t2h_tx_msdu_release_reason_e */
  14972. tqm_status_number : 24,
  14973. frame_type : 4; /* holds htt_tx_wbm_status_frame_type value */
  14974. /* word 4 */
  14975. A_UINT32
  14976. /* ack_frame_rssi:
  14977. * If this frame is removed as the result of the
  14978. * reception of an ACK or BA, this field indicates
  14979. * the RSSI of the received ACK or BA frame.
  14980. * When the frame is removed as result of a direct
  14981. * remove command from the SW, this field is set
  14982. * to 0x0 (which is never a valid value when real
  14983. * RSSI is available).
  14984. * Units: dB w.r.t noise floor
  14985. */
  14986. ack_frame_rssi : 8,
  14987. first_msdu : 1,
  14988. last_msdu : 1,
  14989. msdu_part_of_amsdu : 1,
  14990. buffer_timestamp : 19, /* units = TU = 1024 microseconds */
  14991. rsvd1 : 2;
  14992. /* words 5 + 6 */
  14993. struct htt_t2h_tx_rate_stats_info tx_rate_stats;
  14994. /* word 7 */
  14995. /* rsvd3:
  14996. * backup reserved field to add new parameters if [rsvd0, rsvd1, rsvd2]
  14997. * is not sufficient
  14998. */
  14999. A_UINT32 rsvd3;
  15000. /* NOTE:
  15001. * To preserve backwards compatibility,
  15002. * no new fields can be added in this struct.
  15003. */
  15004. };
  15005. /* member definitions of htt_t2h_tx_msdu_info */
  15006. #define HTT_TX_MSDU_INFO_SW_PEER_ID_M 0x0000FFFF
  15007. #define HTT_TX_MSDU_INFO_SW_PEER_ID_S 0
  15008. #define HTT_TX_MSDU_INFO_SW_PEER_ID_SET(word, value) \
  15009. do { \
  15010. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_SW_PEER_ID, value); \
  15011. (word) |= (value) << HTT_TX_MSDU_INFO_SW_PEER_ID_S; \
  15012. } while (0)
  15013. #define HTT_TX_MSDU_INFO_SW_PEER_ID_GET(word) \
  15014. (((word) & HTT_TX_MSDU_INFO_SW_PEER_ID_M) >> HTT_TX_MSDU_INFO_SW_PEER_ID_S)
  15015. #define HTT_TX_MSDU_INFO_TID_M 0x000F0000
  15016. #define HTT_TX_MSDU_INFO_TID_S 16
  15017. #define HTT_TX_MSDU_INFO_TID_SET(word, value) \
  15018. do { \
  15019. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TID, value); \
  15020. (word) |= (value) << HTT_TX_MSDU_INFO_TID_S; \
  15021. } while (0)
  15022. #define HTT_TX_MSDU_INFO_TID_GET(word) \
  15023. (((word) & HTT_TX_MSDU_INFO_TID_M) >> HTT_TX_MSDU_INFO_TID_S)
  15024. #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_M 0x07F00000
  15025. #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_S 20
  15026. #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_SET(word, value) \
  15027. do { \
  15028. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TRANSMIT_CNT, value); \
  15029. (word) |= (value) << HTT_TX_MSDU_INFO_TRANSMIT_CNT_S; \
  15030. } while (0)
  15031. #define HTT_TX_MSDU_INFO_TRANSMIT_CNT_GET(word) \
  15032. (((word) & HTT_TX_MSDU_INFO_TRANSMIT_CNT_M) >> HTT_TX_MSDU_INFO_TRANSMIT_CNT_S)
  15033. #define HTT_TX_MSDU_INFO_VALID_M 0x08000000
  15034. #define HTT_TX_MSDU_INFO_VALID_S 27
  15035. #define HTT_TX_MSDU_INFO_VALID_SET(word, value) \
  15036. do { \
  15037. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_VALID, value); \
  15038. (word) |= (value) << HTT_TX_MSDU_INFO_VALID_S; \
  15039. } while (0)
  15040. #define HTT_TX_MSDU_INFO_VALID_GET(word) \
  15041. (((word) & HTT_TX_MSDU_INFO_VALID_M) >> HTT_TX_MSDU_INFO_VALID_S)
  15042. #define HTT_TX_MSDU_INFO_MCAST_M 0x10000000
  15043. #define HTT_TX_MSDU_INFO_MCAST_S 28
  15044. #define HTT_TX_MSDU_INFO_MCAST_SET(word, value) \
  15045. do { \
  15046. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MCAST, value); \
  15047. (word) |= (value) << HTT_TX_MSDU_INFO_MCAST_S; \
  15048. } while (0)
  15049. #define HTT_TX_MSDU_INFO_MCAST_GET(word) \
  15050. (((word) & HTT_TX_MSDU_INFO_MCAST_M) >> HTT_TX_MSDU_INFO_MCAST_S)
  15051. #define HTT_TX_MSDU_INFO_RELEASE_REASON_M 0x0000000F
  15052. #define HTT_TX_MSDU_INFO_RELEASE_REASON_S 0
  15053. #define HTT_TX_MSDU_INFO_RELEASE_REASON_SET(word, value) \
  15054. do { \
  15055. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_RELEASE_REASON, value); \
  15056. (word) |= (value) << HTT_TX_MSDU_INFO_RELEASE_REASON_S; \
  15057. } while (0)
  15058. #define HTT_TX_MSDU_INFO_RELEASE_REASON_GET(word) \
  15059. (((word) & HTT_TX_MSDU_INFO_RELEASE_REASON_M) >> HTT_TX_MSDU_INFO_RELEASE_REASON_S)
  15060. #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M 0x0FFFFFF0
  15061. #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S 4
  15062. #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_SET(word, value) \
  15063. do { \
  15064. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER, value); \
  15065. (word) |= (value) << HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S; \
  15066. } while (0)
  15067. #define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_GET(word) \
  15068. (((word) & HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M) >> HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S)
  15069. #define HTT_TX_MSDU_INFO_FRAME_TYPE_M 0xF0000000
  15070. #define HTT_TX_MSDU_INFO_FRAME_TYPE_S 28
  15071. #define HTT_TX_MSDU_INFO_FRAME_TYPE_SET(word, value) \
  15072. do { \
  15073. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FRAME_TYPE, value); \
  15074. (word) |= (value) << HTT_TX_MSDU_INFO_FRAME_TYPE_S; \
  15075. } while (0)
  15076. #define HTT_TX_MSDU_INFO_FRAME_TYPE_GET(word) \
  15077. (((word) & HTT_TX_MSDU_INFO_FRAME_TYPE_M) >> HTT_TX_MSDU_INFO_FRAME_TYPE_S)
  15078. #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M 0x000000FF
  15079. #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S 0
  15080. #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_SET(word, value) \
  15081. do { \
  15082. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_ACK_FRAME_RSSI, value); \
  15083. (word) |= (value) << HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S; \
  15084. } while (0)
  15085. #define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_GET(word) \
  15086. (((word) & HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M) >> HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S)
  15087. #define HTT_TX_MSDU_INFO_FIRST_MSDU_M 0x00000100
  15088. #define HTT_TX_MSDU_INFO_FIRST_MSDU_S 8
  15089. #define HTT_TX_MSDU_INFO_FIRST_MSDU_SET(word, value) \
  15090. do { \
  15091. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FIRST_MSDU, value); \
  15092. (word) |= (value) << HTT_TX_MSDU_INFO_FIRST_MSDU_S; \
  15093. } while (0)
  15094. #define HTT_TX_MSDU_INFO_FIRST_MSDU_GET(word) \
  15095. (((word) & HTT_TX_MSDU_INFO_FIRST_MSDU_M) >> HTT_TX_MSDU_INFO_FIRST_MSDU_S)
  15096. #define HTT_TX_MSDU_INFO_LAST_MSDU_M 0x00000200
  15097. #define HTT_TX_MSDU_INFO_LAST_MSDU_S 9
  15098. #define HTT_TX_MSDU_INFO_LAST_MSDU_SET(word, value) \
  15099. do { \
  15100. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_LAST_MSDU, value); \
  15101. (word) |= (value) << HTT_TX_MSDU_INFO_LAST_MSDU_S; \
  15102. } while (0)
  15103. #define HTT_TX_MSDU_INFO_LAST_MSDU_GET(word) \
  15104. (((word) & HTT_TX_MSDU_INFO_LAST_MSDU_M) >> HTT_TX_MSDU_INFO_LAST_MSDU_S)
  15105. #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M 0x00000400
  15106. #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S 10
  15107. #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_SET(word, value) \
  15108. do { \
  15109. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU, value); \
  15110. (word) |= (value) << HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S; \
  15111. } while (0)
  15112. #define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_GET(word) \
  15113. (((word) & HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M) >> HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S)
  15114. #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M 0x3FFFF800
  15115. #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S 11
  15116. #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_SET(word, value) \
  15117. do { \
  15118. HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP, value); \
  15119. (word) |= (value) << HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S; \
  15120. } while (0)
  15121. #define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_GET(word) \
  15122. (((word) & HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M) >> HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S)
  15123. struct htt_t2h_soft_umac_tx_compl_ind {
  15124. A_UINT32 msg_type : 8, /* HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND */
  15125. msdu_cnt : 8, /* min: 0, max: 255 */
  15126. rsvd0 : 16;
  15127. /* NOTE:
  15128. * To preserve backwards compatibility,
  15129. * no new fields can be added in this struct.
  15130. */
  15131. /*
  15132. * append here:
  15133. * struct htt_t2h_tx_msdu_info payload[1(or more)]
  15134. * for all the msdu's that are part of this completion.
  15135. */
  15136. };
  15137. /* member definitions of htt_t2h_soft_umac_tx_compl_ind */
  15138. #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M 0x0000FF00
  15139. #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S 8
  15140. #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_SET(word, value) \
  15141. do { \
  15142. HTT_CHECK_SET_VAL(HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT, value); \
  15143. (word) |= (value) << HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S; \
  15144. } while (0)
  15145. #define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_GET(word) \
  15146. (((word) & HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M) >> HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S)
  15147. /**
  15148. * @brief target -> host rate-control update indication message
  15149. *
  15150. * DEPRECATED (DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND)
  15151. *
  15152. * @details
  15153. * The following diagram shows the format of the RC Update message
  15154. * sent from the target to the host, while processing the tx-completion
  15155. * of a transmitted PPDU.
  15156. *
  15157. * |31 24|23 16|15 8|7 0|
  15158. * |-------------------------------------------------------------|
  15159. * | peer ID | vdev ID | msg_type |
  15160. * |-------------------------------------------------------------|
  15161. * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
  15162. * |-------------------------------------------------------------|
  15163. * | reserved | num elems | MAC addr 5 | MAC addr 4 |
  15164. * |-------------------------------------------------------------|
  15165. * | : |
  15166. * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) :
  15167. * | : |
  15168. * |-------------------------------------------------------------|
  15169. * | : |
  15170. * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) :
  15171. * | : |
  15172. * |-------------------------------------------------------------|
  15173. * : :
  15174. * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  15175. *
  15176. */
  15177. typedef struct {
  15178. A_UINT32 rate_code; /* rate code, bw, chain mask sgi */
  15179. A_UINT32 rate_code_flags;
  15180. A_UINT32 flags; /* Encodes information such as excessive
  15181. retransmission, aggregate, some info
  15182. from .11 frame control,
  15183. STBC, LDPC, (SGI and Tx Chain Mask
  15184. are encoded in ptx_rc->flags field),
  15185. AMPDU truncation (BT/time based etc.),
  15186. RTS/CTS attempt */
  15187. A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */
  15188. A_UINT32 num_retries; /* Total # of transmission attempt for this rate */
  15189. A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */
  15190. A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */
  15191. A_UINT32 time_stamp ; /* ACK timestamp (helps determine age) */
  15192. A_UINT32 is_probe; /* Valid if probing. Else, 0 */
  15193. } HTT_RC_TX_DONE_PARAMS;
  15194. #define HTT_RC_UPDATE_CTXT_SZ (sizeof(HTT_RC_TX_DONE_PARAMS)) /* bytes */
  15195. #define HTT_RC_UPDATE_HDR_SZ (12) /* bytes */
  15196. #define HTT_RC_UPDATE_MAC_ADDR_OFFSET (4) /* bytes */
  15197. #define HTT_RC_UPDATE_MAC_ADDR_LENGTH IEEE80211_ADDR_LEN /* bytes */
  15198. #define HTT_RC_UPDATE_VDEVID_S 8
  15199. #define HTT_RC_UPDATE_VDEVID_M 0xff00
  15200. #define HTT_RC_UPDATE_PEERID_S 16
  15201. #define HTT_RC_UPDATE_PEERID_M 0xffff0000
  15202. #define HTT_RC_UPDATE_NUM_ELEMS_S 16
  15203. #define HTT_RC_UPDATE_NUM_ELEMS_M 0x00ff0000
  15204. #define HTT_RC_UPDATE_VDEVID_SET(_info, _val) \
  15205. do { \
  15206. HTT_CHECK_SET_VAL(HTT_RC_UPDATE_VDEVID, _val); \
  15207. ((_info) |= ((_val) << HTT_RC_UPDATE_VDEVID_S)); \
  15208. } while (0)
  15209. #define HTT_RC_UPDATE_VDEVID_GET(_info) \
  15210. (((_info) & HTT_RC_UPDATE_VDEVID_M) >> HTT_RC_UPDATE_VDEVID_S)
  15211. #define HTT_RC_UPDATE_PEERID_SET(_info, _val) \
  15212. do { \
  15213. HTT_CHECK_SET_VAL(HTT_RC_UPDATE_PEERID, _val); \
  15214. ((_info) |= ((_val) << HTT_RC_UPDATE_PEERID_S)); \
  15215. } while (0)
  15216. #define HTT_RC_UPDATE_PEERID_GET(_info) \
  15217. (((_info) & HTT_RC_UPDATE_PEERID_M) >> HTT_RC_UPDATE_PEERID_S)
  15218. #define HTT_RC_UPDATE_NUM_ELEMS_SET(_info, _val) \
  15219. do { \
  15220. HTT_CHECK_SET_VAL(HTT_RC_UPDATE_NUM_ELEMS, _val); \
  15221. ((_info) |= ((_val) << HTT_RC_UPDATE_NUM_ELEMS_S)); \
  15222. } while (0)
  15223. #define HTT_RC_UPDATE_NUM_ELEMS_GET(_info) \
  15224. (((_info) & HTT_RC_UPDATE_NUM_ELEMS_M) >> HTT_RC_UPDATE_NUM_ELEMS_S)
  15225. /**
  15226. * @brief target -> host rx fragment indication message definition
  15227. *
  15228. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_FRAG_IND
  15229. *
  15230. * @details
  15231. * The following field definitions describe the format of the rx fragment
  15232. * indication message sent from the target to the host.
  15233. * The rx fragment indication message shares the format of the
  15234. * rx indication message, but not all fields from the rx indication message
  15235. * are relevant to the rx fragment indication message.
  15236. *
  15237. *
  15238. * |31 24|23 18|17|16|15|14|13|12|11|10|9|8|7|6|5|4 0|
  15239. * |-----------+-------------------+---------------------+-------------|
  15240. * | peer ID | |FV| ext TID | msg type |
  15241. * |-------------------------------------------------------------------|
  15242. * | | flush | flush |
  15243. * | | end | start |
  15244. * | | seq num | seq num |
  15245. * |-------------------------------------------------------------------|
  15246. * | reserved | FW rx desc bytes |
  15247. * |-------------------------------------------------------------------|
  15248. * | | FW MSDU Rx |
  15249. * | | desc B0 |
  15250. * |-------------------------------------------------------------------|
  15251. * Header fields:
  15252. * - MSG_TYPE
  15253. * Bits 7:0
  15254. * Purpose: identifies this as an rx fragment indication message
  15255. * Value: 0xa (HTT_T2H_MSG_TYPE_RX_FRAG_IND)
  15256. * - EXT_TID
  15257. * Bits 12:8
  15258. * Purpose: identify the traffic ID of the rx data, including
  15259. * special "extended" TID values for multicast, broadcast, and
  15260. * non-QoS data frames
  15261. * Value: 0-15 for regular TIDs, or >= 16 for bcast/mcast/non-QoS
  15262. * - FLUSH_VALID (FV)
  15263. * Bit 13
  15264. * Purpose: indicate whether the flush IE (start/end sequence numbers)
  15265. * is valid
  15266. * Value:
  15267. * 1 -> flush IE is valid and needs to be processed
  15268. * 0 -> flush IE is not valid and should be ignored
  15269. * - PEER_ID
  15270. * Bits 31:16
  15271. * Purpose: Identify, by ID, which peer sent the rx data
  15272. * Value: ID of the peer who sent the rx data
  15273. * - FLUSH_SEQ_NUM_START
  15274. * Bits 5:0
  15275. * Purpose: Indicate the start of a series of MPDUs to flush
  15276. * Not all MPDUs within this series are necessarily valid - the host
  15277. * must check each sequence number within this range to see if the
  15278. * corresponding MPDU is actually present.
  15279. * This field is only valid if the FV bit is set.
  15280. * Value:
  15281. * The sequence number for the first MPDUs to check to flush.
  15282. * The sequence number is masked by 0x3f.
  15283. * - FLUSH_SEQ_NUM_END
  15284. * Bits 11:6
  15285. * Purpose: Indicate the end of a series of MPDUs to flush
  15286. * Value:
  15287. * The sequence number one larger than the sequence number of the
  15288. * last MPDU to check to flush.
  15289. * The sequence number is masked by 0x3f.
  15290. * Not all MPDUs within this series are necessarily valid - the host
  15291. * must check each sequence number within this range to see if the
  15292. * corresponding MPDU is actually present.
  15293. * This field is only valid if the FV bit is set.
  15294. * Rx descriptor fields:
  15295. * - FW_RX_DESC_BYTES
  15296. * Bits 15:0
  15297. * Purpose: Indicate how many bytes in the Rx indication are used for
  15298. * FW Rx descriptors
  15299. * Value: 1
  15300. */
  15301. #define HTT_RX_FRAG_IND_HDR_PREFIX_SIZE32 2
  15302. #define HTT_RX_FRAG_IND_FW_DESC_BYTE_OFFSET 12
  15303. #define HTT_RX_FRAG_IND_EXT_TID_SET HTT_RX_IND_EXT_TID_SET
  15304. #define HTT_RX_FRAG_IND_EXT_TID_GET HTT_RX_IND_EXT_TID_GET
  15305. #define HTT_RX_FRAG_IND_PEER_ID_SET HTT_RX_IND_PEER_ID_SET
  15306. #define HTT_RX_FRAG_IND_PEER_ID_GET HTT_RX_IND_PEER_ID_GET
  15307. #define HTT_RX_FRAG_IND_FLUSH_VALID_SET HTT_RX_IND_FLUSH_VALID_SET
  15308. #define HTT_RX_FRAG_IND_FLUSH_VALID_GET HTT_RX_IND_FLUSH_VALID_GET
  15309. #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_SET \
  15310. HTT_RX_IND_FLUSH_SEQ_NUM_START_SET
  15311. #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_GET \
  15312. HTT_RX_IND_FLUSH_SEQ_NUM_START_GET
  15313. #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_SET \
  15314. HTT_RX_IND_FLUSH_SEQ_NUM_END_SET
  15315. #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_GET \
  15316. HTT_RX_IND_FLUSH_SEQ_NUM_END_GET
  15317. #define HTT_RX_FRAG_IND_FW_RX_DESC_BYTES_GET HTT_RX_IND_FW_RX_DESC_BYTES_GET
  15318. #define HTT_RX_FRAG_IND_BYTES \
  15319. (4 /* msg hdr */ + \
  15320. 4 /* flush spec */ + \
  15321. 4 /* (unused) FW rx desc bytes spec */ + \
  15322. 4 /* FW rx desc */)
  15323. /**
  15324. * @brief target -> host test message definition
  15325. *
  15326. * MSG_TYPE => HTT_T2H_MSG_TYPE_TEST
  15327. *
  15328. * @details
  15329. * The following field definitions describe the format of the test
  15330. * message sent from the target to the host.
  15331. * The message consists of a 4-octet header, followed by a variable
  15332. * number of 32-bit integer values, followed by a variable number
  15333. * of 8-bit character values.
  15334. *
  15335. * |31 16|15 8|7 0|
  15336. * |-----------------------------------------------------------|
  15337. * | num chars | num ints | msg type |
  15338. * |-----------------------------------------------------------|
  15339. * | int 0 |
  15340. * |-----------------------------------------------------------|
  15341. * | int 1 |
  15342. * |-----------------------------------------------------------|
  15343. * | ... |
  15344. * |-----------------------------------------------------------|
  15345. * | char 3 | char 2 | char 1 | char 0 |
  15346. * |-----------------------------------------------------------|
  15347. * | | | ... | char 4 |
  15348. * |-----------------------------------------------------------|
  15349. * - MSG_TYPE
  15350. * Bits 7:0
  15351. * Purpose: identifies this as a test message
  15352. * Value: HTT_MSG_TYPE_TEST
  15353. * - NUM_INTS
  15354. * Bits 15:8
  15355. * Purpose: indicate how many 32-bit integers follow the message header
  15356. * - NUM_CHARS
  15357. * Bits 31:16
  15358. * Purpose: indicate how many 8-bit characters follow the series of integers
  15359. */
  15360. #define HTT_RX_TEST_NUM_INTS_M 0xff00
  15361. #define HTT_RX_TEST_NUM_INTS_S 8
  15362. #define HTT_RX_TEST_NUM_CHARS_M 0xffff0000
  15363. #define HTT_RX_TEST_NUM_CHARS_S 16
  15364. #define HTT_RX_TEST_NUM_INTS_SET(word, value) \
  15365. do { \
  15366. HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_INTS, value); \
  15367. (word) |= (value) << HTT_RX_TEST_NUM_INTS_S; \
  15368. } while (0)
  15369. #define HTT_RX_TEST_NUM_INTS_GET(word) \
  15370. (((word) & HTT_RX_TEST_NUM_INTS_M) >> HTT_RX_TEST_NUM_INTS_S)
  15371. #define HTT_RX_TEST_NUM_CHARS_SET(word, value) \
  15372. do { \
  15373. HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_CHARS, value); \
  15374. (word) |= (value) << HTT_RX_TEST_NUM_CHARS_S; \
  15375. } while (0)
  15376. #define HTT_RX_TEST_NUM_CHARS_GET(word) \
  15377. (((word) & HTT_RX_TEST_NUM_CHARS_M) >> HTT_RX_TEST_NUM_CHARS_S)
  15378. /**
  15379. * @brief target -> host packet log message
  15380. *
  15381. * MSG_TYPE => HTT_T2H_MSG_TYPE_PKTLOG
  15382. *
  15383. * @details
  15384. * The following field definitions describe the format of the packet log
  15385. * message sent from the target to the host.
  15386. * The message consists of a 4-octet header,followed by a variable number
  15387. * of 32-bit character values.
  15388. *
  15389. * |31 16|15 12|11 10|9 8|7 0|
  15390. * |------------------------------------------------------------------|
  15391. * | payload_size | rsvd |pdev_id|mac_id| msg type |
  15392. * |------------------------------------------------------------------|
  15393. * | payload |
  15394. * |------------------------------------------------------------------|
  15395. * - MSG_TYPE
  15396. * Bits 7:0
  15397. * Purpose: identifies this as a pktlog message
  15398. * Value: 0x8 (HTT_T2H_MSG_TYPE_PKTLOG)
  15399. * - mac_id
  15400. * Bits 9:8
  15401. * Purpose: identifies which MAC/PHY instance generated this pktlog info
  15402. * Value: 0-3
  15403. * - pdev_id
  15404. * Bits 11:10
  15405. * Purpose: pdev_id
  15406. * Value: 0-3
  15407. * 0 (for rings at SOC level),
  15408. * 1/2/3 PDEV -> 0/1/2
  15409. * - payload_size
  15410. * Bits 31:16
  15411. * Purpose: explicitly specify the payload size
  15412. * Value: payload size in bytes (payload size is a multiple of 4 bytes)
  15413. */
  15414. PREPACK struct htt_pktlog_msg {
  15415. A_UINT32 header;
  15416. A_UINT32 payload[1/* or more */];
  15417. } POSTPACK;
  15418. #define HTT_T2H_PKTLOG_MAC_ID_M 0x00000300
  15419. #define HTT_T2H_PKTLOG_MAC_ID_S 8
  15420. #define HTT_T2H_PKTLOG_PDEV_ID_M 0x00000C00
  15421. #define HTT_T2H_PKTLOG_PDEV_ID_S 10
  15422. #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_M 0xFFFF0000
  15423. #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_S 16
  15424. #define HTT_T2H_PKTLOG_MAC_ID_SET(word, value) \
  15425. do { \
  15426. HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_MAC_ID, value); \
  15427. (word) |= (value) << HTT_T2H_PKTLOG_MAC_ID_S; \
  15428. } while (0)
  15429. #define HTT_T2H_PKTLOG_MAC_ID_GET(word) \
  15430. (((word) & HTT_T2H_PKTLOG_MAC_ID_M) >> \
  15431. HTT_T2H_PKTLOG_MAC_ID_S)
  15432. #define HTT_T2H_PKTLOG_PDEV_ID_SET(word, value) \
  15433. do { \
  15434. HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_PDEV_ID, value); \
  15435. (word) |= (value) << HTT_T2H_PKTLOG_PDEV_ID_S; \
  15436. } while (0)
  15437. #define HTT_T2H_PKTLOG_PDEV_ID_GET(word) \
  15438. (((word) & HTT_T2H_PKTLOG_PDEV_ID_M) >> \
  15439. HTT_T2H_PKTLOG_PDEV_ID_S)
  15440. #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_SET(word, value) \
  15441. do { \
  15442. HTT_CHECK_SET_VAL(HTT_T2H_PKTLOG_PAYLOAD_SIZE, value); \
  15443. (word) |= (value) << HTT_T2H_PKTLOG_PAYLOAD_SIZE_S; \
  15444. } while (0)
  15445. #define HTT_T2H_PKTLOG_PAYLOAD_SIZE_GET(word) \
  15446. (((word) & HTT_T2H_PKTLOG_PAYLOAD_SIZE_M) >> \
  15447. HTT_T2H_PKTLOG_PAYLOAD_SIZE_S)
  15448. /*
  15449. * Rx reorder statistics
  15450. * NB: all the fields must be defined in 4 octets size.
  15451. */
  15452. struct rx_reorder_stats {
  15453. /* Non QoS MPDUs received */
  15454. A_UINT32 deliver_non_qos;
  15455. /* MPDUs received in-order */
  15456. A_UINT32 deliver_in_order;
  15457. /* Flush due to reorder timer expired */
  15458. A_UINT32 deliver_flush_timeout;
  15459. /* Flush due to move out of window */
  15460. A_UINT32 deliver_flush_oow;
  15461. /* Flush due to DELBA */
  15462. A_UINT32 deliver_flush_delba;
  15463. /* MPDUs dropped due to FCS error */
  15464. A_UINT32 fcs_error;
  15465. /* MPDUs dropped due to monitor mode non-data packet */
  15466. A_UINT32 mgmt_ctrl;
  15467. /* Unicast-data MPDUs dropped due to invalid peer */
  15468. A_UINT32 invalid_peer;
  15469. /* MPDUs dropped due to duplication (non aggregation) */
  15470. A_UINT32 dup_non_aggr;
  15471. /* MPDUs dropped due to processed before */
  15472. A_UINT32 dup_past;
  15473. /* MPDUs dropped due to duplicate in reorder queue */
  15474. A_UINT32 dup_in_reorder;
  15475. /* Reorder timeout happened */
  15476. A_UINT32 reorder_timeout;
  15477. /* invalid bar ssn */
  15478. A_UINT32 invalid_bar_ssn;
  15479. /* reorder reset due to bar ssn */
  15480. A_UINT32 ssn_reset;
  15481. /* Flush due to delete peer */
  15482. A_UINT32 deliver_flush_delpeer;
  15483. /* Flush due to offload*/
  15484. A_UINT32 deliver_flush_offload;
  15485. /* Flush due to out of buffer*/
  15486. A_UINT32 deliver_flush_oob;
  15487. /* MPDUs dropped due to PN check fail */
  15488. A_UINT32 pn_fail;
  15489. /* MPDUs dropped due to unable to allocate memory */
  15490. A_UINT32 store_fail;
  15491. /* Number of times the tid pool alloc succeeded */
  15492. A_UINT32 tid_pool_alloc_succ;
  15493. /* Number of times the MPDU pool alloc succeeded */
  15494. A_UINT32 mpdu_pool_alloc_succ;
  15495. /* Number of times the MSDU pool alloc succeeded */
  15496. A_UINT32 msdu_pool_alloc_succ;
  15497. /* Number of times the tid pool alloc failed */
  15498. A_UINT32 tid_pool_alloc_fail;
  15499. /* Number of times the MPDU pool alloc failed */
  15500. A_UINT32 mpdu_pool_alloc_fail;
  15501. /* Number of times the MSDU pool alloc failed */
  15502. A_UINT32 msdu_pool_alloc_fail;
  15503. /* Number of times the tid pool freed */
  15504. A_UINT32 tid_pool_free;
  15505. /* Number of times the MPDU pool freed */
  15506. A_UINT32 mpdu_pool_free;
  15507. /* Number of times the MSDU pool freed */
  15508. A_UINT32 msdu_pool_free;
  15509. /* number of MSDUs undelivered to HTT and queued to Data Rx MSDU free list*/
  15510. A_UINT32 msdu_queued;
  15511. /* Number of MSDUs released from Data Rx MSDU list to MAC ring */
  15512. A_UINT32 msdu_recycled;
  15513. /* Number of MPDUs with invalid peer but A2 found in AST */
  15514. A_UINT32 invalid_peer_a2_in_ast;
  15515. /* Number of MPDUs with invalid peer but A3 found in AST */
  15516. A_UINT32 invalid_peer_a3_in_ast;
  15517. /* Number of MPDUs with invalid peer, Broadcast or Multicast frame */
  15518. A_UINT32 invalid_peer_bmc_mpdus;
  15519. /* Number of MSDUs with err attention word */
  15520. A_UINT32 rxdesc_err_att;
  15521. /* Number of MSDUs with flag of peer_idx_invalid */
  15522. A_UINT32 rxdesc_err_peer_idx_inv;
  15523. /* Number of MSDUs with flag of peer_idx_timeout */
  15524. A_UINT32 rxdesc_err_peer_idx_to;
  15525. /* Number of MSDUs with flag of overflow */
  15526. A_UINT32 rxdesc_err_ov;
  15527. /* Number of MSDUs with flag of msdu_length_err */
  15528. A_UINT32 rxdesc_err_msdu_len;
  15529. /* Number of MSDUs with flag of mpdu_length_err */
  15530. A_UINT32 rxdesc_err_mpdu_len;
  15531. /* Number of MSDUs with flag of tkip_mic_err */
  15532. A_UINT32 rxdesc_err_tkip_mic;
  15533. /* Number of MSDUs with flag of decrypt_err */
  15534. A_UINT32 rxdesc_err_decrypt;
  15535. /* Number of MSDUs with flag of fcs_err */
  15536. A_UINT32 rxdesc_err_fcs;
  15537. /* Number of Unicast (bc_mc bit is not set in attention word)
  15538. * frames with invalid peer handler
  15539. */
  15540. A_UINT32 rxdesc_uc_msdus_inv_peer;
  15541. /* Number of unicast frame directly (direct bit is set in attention word)
  15542. * to DUT with invalid peer handler
  15543. */
  15544. A_UINT32 rxdesc_direct_msdus_inv_peer;
  15545. /* Number of Broadcast/Multicast (bc_mc bit set in attention word)
  15546. * frames with invalid peer handler
  15547. */
  15548. A_UINT32 rxdesc_bmc_msdus_inv_peer;
  15549. /* Number of MSDUs dropped due to no first MSDU flag */
  15550. A_UINT32 rxdesc_no_1st_msdu;
  15551. /* Number of MSDUs dropped due to ring overflow */
  15552. A_UINT32 msdu_drop_ring_ov;
  15553. /* Number of MSDUs dropped due to FC mismatch */
  15554. A_UINT32 msdu_drop_fc_mismatch;
  15555. /* Number of MSDUs dropped due to mgt frame in Remote ring */
  15556. A_UINT32 msdu_drop_mgmt_remote_ring;
  15557. /* Number of MSDUs dropped due to errors not reported in attention word */
  15558. A_UINT32 msdu_drop_misc;
  15559. /* Number of MSDUs go to offload before reorder */
  15560. A_UINT32 offload_msdu_wal;
  15561. /* Number of data frame dropped by offload after reorder */
  15562. A_UINT32 offload_msdu_reorder;
  15563. /* Number of MPDUs with sequence number in the past and within the BA window */
  15564. A_UINT32 dup_past_within_window;
  15565. /* Number of MPDUs with sequence number in the past and outside the BA window */
  15566. A_UINT32 dup_past_outside_window;
  15567. /* Number of MSDUs with decrypt/MIC error */
  15568. A_UINT32 rxdesc_err_decrypt_mic;
  15569. /* Number of data MSDUs received on both local and remote rings */
  15570. A_UINT32 data_msdus_on_both_rings;
  15571. /* MPDUs never filled */
  15572. A_UINT32 holes_not_filled;
  15573. };
  15574. /*
  15575. * Rx Remote buffer statistics
  15576. * NB: all the fields must be defined in 4 octets size.
  15577. */
  15578. struct rx_remote_buffer_mgmt_stats {
  15579. /* Total number of MSDUs reaped for Rx processing */
  15580. A_UINT32 remote_reaped;
  15581. /* MSDUs recycled within firmware */
  15582. A_UINT32 remote_recycled;
  15583. /* MSDUs stored by Data Rx */
  15584. A_UINT32 data_rx_msdus_stored;
  15585. /* Number of HTT indications from WAL Rx MSDU */
  15586. A_UINT32 wal_rx_ind;
  15587. /* Number of unconsumed HTT indications from WAL Rx MSDU */
  15588. A_UINT32 wal_rx_ind_unconsumed;
  15589. /* Number of HTT indications from Data Rx MSDU */
  15590. A_UINT32 data_rx_ind;
  15591. /* Number of unconsumed HTT indications from Data Rx MSDU */
  15592. A_UINT32 data_rx_ind_unconsumed;
  15593. /* Number of HTT indications from ATHBUF */
  15594. A_UINT32 athbuf_rx_ind;
  15595. /* Number of remote buffers requested for refill */
  15596. A_UINT32 refill_buf_req;
  15597. /* Number of remote buffers filled by the host */
  15598. A_UINT32 refill_buf_rsp;
  15599. /* Number of times MAC hw_index = f/w write_index */
  15600. A_INT32 mac_no_bufs;
  15601. /* Number of times f/w write_index = f/w read_index for MAC Rx ring */
  15602. A_INT32 fw_indices_equal;
  15603. /* Number of times f/w finds no buffers to post */
  15604. A_INT32 host_no_bufs;
  15605. };
  15606. /*
  15607. * TXBF MU/SU packets and NDPA statistics
  15608. * NB: all the fields must be defined in 4 octets size.
  15609. */
  15610. struct rx_txbf_musu_ndpa_pkts_stats {
  15611. A_UINT32 number_mu_pkts; /* number of TXBF MU packets received */
  15612. A_UINT32 number_su_pkts; /* number of TXBF SU packets received */
  15613. A_UINT32 txbf_directed_ndpa_count; /* number of TXBF directed NDPA */
  15614. A_UINT32 txbf_ndpa_retry_count; /* number of TXBF retried NDPA */
  15615. A_UINT32 txbf_total_ndpa_count; /* total number of TXBF NDPA */
  15616. A_UINT32 reserved[3]; /* must be set to 0x0 */
  15617. };
  15618. /*
  15619. * htt_dbg_stats_status -
  15620. * present - The requested stats have been delivered in full.
  15621. * This indicates that either the stats information was contained
  15622. * in its entirety within this message, or else this message
  15623. * completes the delivery of the requested stats info that was
  15624. * partially delivered through earlier STATS_CONF messages.
  15625. * partial - The requested stats have been delivered in part.
  15626. * One or more subsequent STATS_CONF messages with the same
  15627. * cookie value will be sent to deliver the remainder of the
  15628. * information.
  15629. * error - The requested stats could not be delivered, for example due
  15630. * to a shortage of memory to construct a message holding the
  15631. * requested stats.
  15632. * invalid - The requested stat type is either not recognized, or the
  15633. * target is configured to not gather the stats type in question.
  15634. * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  15635. * series_done - This special value indicates that no further stats info
  15636. * elements are present within a series of stats info elems
  15637. * (within a stats upload confirmation message).
  15638. */
  15639. enum htt_dbg_stats_status {
  15640. HTT_DBG_STATS_STATUS_PRESENT = 0,
  15641. HTT_DBG_STATS_STATUS_PARTIAL = 1,
  15642. HTT_DBG_STATS_STATUS_ERROR = 2,
  15643. HTT_DBG_STATS_STATUS_INVALID = 3,
  15644. HTT_DBG_STATS_STATUS_SERIES_DONE = 7
  15645. };
  15646. /**
  15647. * @brief target -> host statistics upload
  15648. *
  15649. * MSG_TYPE => HTT_T2H_MSG_TYPE_STATS_CONF
  15650. *
  15651. * @details
  15652. * The following field definitions describe the format of the HTT target
  15653. * to host stats upload confirmation message.
  15654. * The message contains a cookie echoed from the HTT host->target stats
  15655. * upload request, which identifies which request the confirmation is
  15656. * for, and a series of tag-length-value stats information elements.
  15657. * The tag-length header for each stats info element also includes a
  15658. * status field, to indicate whether the request for the stat type in
  15659. * question was fully met, partially met, unable to be met, or invalid
  15660. * (if the stat type in question is disabled in the target).
  15661. * A special value of all 1's in this status field is used to indicate
  15662. * the end of the series of stats info elements.
  15663. *
  15664. *
  15665. * |31 16|15 8|7 5|4 0|
  15666. * |------------------------------------------------------------|
  15667. * | reserved | msg type |
  15668. * |------------------------------------------------------------|
  15669. * | cookie LSBs |
  15670. * |------------------------------------------------------------|
  15671. * | cookie MSBs |
  15672. * |------------------------------------------------------------|
  15673. * | stats entry length | reserved | S |stat type|
  15674. * |------------------------------------------------------------|
  15675. * | |
  15676. * | type-specific stats info |
  15677. * | |
  15678. * |------------------------------------------------------------|
  15679. * | stats entry length | reserved | S |stat type|
  15680. * |------------------------------------------------------------|
  15681. * | |
  15682. * | type-specific stats info |
  15683. * | |
  15684. * |------------------------------------------------------------|
  15685. * | n/a | reserved | 111 | n/a |
  15686. * |------------------------------------------------------------|
  15687. * Header fields:
  15688. * - MSG_TYPE
  15689. * Bits 7:0
  15690. * Purpose: identifies this is a statistics upload confirmation message
  15691. * Value: 0x9 (HTT_T2H_MSG_TYPE_STATS_CONF)
  15692. * - COOKIE_LSBS
  15693. * Bits 31:0
  15694. * Purpose: Provide a mechanism to match a target->host stats confirmation
  15695. * message with its preceding host->target stats request message.
  15696. * Value: LSBs of the opaque cookie specified by the host-side requestor
  15697. * - COOKIE_MSBS
  15698. * Bits 31:0
  15699. * Purpose: Provide a mechanism to match a target->host stats confirmation
  15700. * message with its preceding host->target stats request message.
  15701. * Value: MSBs of the opaque cookie specified by the host-side requestor
  15702. *
  15703. * Stats Information Element tag-length header fields:
  15704. * - STAT_TYPE
  15705. * Bits 4:0
  15706. * Purpose: identifies the type of statistics info held in the
  15707. * following information element
  15708. * Value: htt_dbg_stats_type
  15709. * - STATUS
  15710. * Bits 7:5
  15711. * Purpose: indicate whether the requested stats are present
  15712. * Value: htt_dbg_stats_status, including a special value (0x7) to mark
  15713. * the completion of the stats entry series
  15714. * - LENGTH
  15715. * Bits 31:16
  15716. * Purpose: indicate the stats information size
  15717. * Value: This field specifies the number of bytes of stats information
  15718. * that follows the element tag-length header.
  15719. * It is expected but not required that this length is a multiple of
  15720. * 4 bytes. Even if the length is not an integer multiple of 4, the
  15721. * subsequent stats entry header will begin on a 4-byte aligned
  15722. * boundary.
  15723. */
  15724. #define HTT_T2H_STATS_COOKIE_SIZE 8
  15725. #define HTT_T2H_STATS_CONF_TAIL_SIZE 4
  15726. #define HTT_T2H_STATS_CONF_HDR_SIZE 4
  15727. #define HTT_T2H_STATS_CONF_TLV_HDR_SIZE 4
  15728. #define HTT_T2H_STATS_CONF_TLV_TYPE_M 0x0000001f
  15729. #define HTT_T2H_STATS_CONF_TLV_TYPE_S 0
  15730. #define HTT_T2H_STATS_CONF_TLV_STATUS_M 0x000000e0
  15731. #define HTT_T2H_STATS_CONF_TLV_STATUS_S 5
  15732. #define HTT_T2H_STATS_CONF_TLV_LENGTH_M 0xffff0000
  15733. #define HTT_T2H_STATS_CONF_TLV_LENGTH_S 16
  15734. #define HTT_T2H_STATS_CONF_TLV_TYPE_SET(word, value) \
  15735. do { \
  15736. HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_TYPE, value); \
  15737. (word) |= (value) << HTT_T2H_STATS_CONF_TLV_TYPE_S; \
  15738. } while (0)
  15739. #define HTT_T2H_STATS_CONF_TLV_TYPE_GET(word) \
  15740. (((word) & HTT_T2H_STATS_CONF_TLV_TYPE_M) >> \
  15741. HTT_T2H_STATS_CONF_TLV_TYPE_S)
  15742. #define HTT_T2H_STATS_CONF_TLV_STATUS_SET(word, value) \
  15743. do { \
  15744. HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_STATUS, value); \
  15745. (word) |= (value) << HTT_T2H_STATS_CONF_TLV_STATUS_S; \
  15746. } while (0)
  15747. #define HTT_T2H_STATS_CONF_TLV_STATUS_GET(word) \
  15748. (((word) & HTT_T2H_STATS_CONF_TLV_STATUS_M) >> \
  15749. HTT_T2H_STATS_CONF_TLV_STATUS_S)
  15750. #define HTT_T2H_STATS_CONF_TLV_LENGTH_SET(word, value) \
  15751. do { \
  15752. HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_LENGTH, value); \
  15753. (word) |= (value) << HTT_T2H_STATS_CONF_TLV_LENGTH_S; \
  15754. } while (0)
  15755. #define HTT_T2H_STATS_CONF_TLV_LENGTH_GET(word) \
  15756. (((word) & HTT_T2H_STATS_CONF_TLV_LENGTH_M) >> \
  15757. HTT_T2H_STATS_CONF_TLV_LENGTH_S)
  15758. #define HL_HTT_FW_RX_DESC_RSVD_SIZE 18
  15759. #define HTT_MAX_AGGR 64
  15760. #define HTT_HL_MAX_AGGR 18
  15761. /**
  15762. * @brief host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank
  15763. *
  15764. * MSG_TYPE => HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG
  15765. *
  15766. * @details
  15767. * The following field definitions describe the format of the HTT host
  15768. * to target frag_desc/msdu_ext bank configuration message.
  15769. * The message contains the based address and the min and max id of the
  15770. * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and
  15771. * MSDU_EXT/FRAG_DESC.
  15772. * HTT will use id in HTT descriptor instead sending the frag_desc_ptr.
  15773. * In peregrine the firmware will use fragment_desc_ptr but in WIFI2.0
  15774. * the hardware does the mapping/translation.
  15775. *
  15776. * Total banks that can be configured is configured to 16.
  15777. *
  15778. * This should be called before any TX has be initiated by the HTT
  15779. *
  15780. * |31 16|15 8|7 5|4 0|
  15781. * |------------------------------------------------------------|
  15782. * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type |
  15783. * |------------------------------------------------------------|
  15784. * | BANK0_BASE_ADDRESS (bits 31:0) |
  15785. #if HTT_PADDR64
  15786. * | BANK0_BASE_ADDRESS (bits 63:32) |
  15787. #endif
  15788. * |------------------------------------------------------------|
  15789. * | ... |
  15790. * |------------------------------------------------------------|
  15791. * | BANK15_BASE_ADDRESS (bits 31:0) |
  15792. #if HTT_PADDR64
  15793. * | BANK15_BASE_ADDRESS (bits 63:32) |
  15794. #endif
  15795. * |------------------------------------------------------------|
  15796. * | BANK0_MAX_ID | BANK0_MIN_ID |
  15797. * |------------------------------------------------------------|
  15798. * | ... |
  15799. * |------------------------------------------------------------|
  15800. * | BANK15_MAX_ID | BANK15_MIN_ID |
  15801. * |------------------------------------------------------------|
  15802. * Header fields:
  15803. * - MSG_TYPE
  15804. * Bits 7:0
  15805. * Value: 0x6 (HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG)
  15806. * for systems with 64-bit format for bus addresses:
  15807. * - BANKx_BASE_ADDRESS_LO
  15808. * Bits 31:0
  15809. * Purpose: Provide a mechanism to specify the base address of the
  15810. * MSDU_EXT bank physical/bus address.
  15811. * Value: lower 4 bytes of MSDU_EXT bank physical / bus address
  15812. * - BANKx_BASE_ADDRESS_HI
  15813. * Bits 31:0
  15814. * Purpose: Provide a mechanism to specify the base address of the
  15815. * MSDU_EXT bank physical/bus address.
  15816. * Value: higher 4 bytes of MSDU_EXT bank physical / bus address
  15817. * for systems with 32-bit format for bus addresses:
  15818. * - BANKx_BASE_ADDRESS
  15819. * Bits 31:0
  15820. * Purpose: Provide a mechanism to specify the base address of the
  15821. * MSDU_EXT bank physical/bus address.
  15822. * Value: MSDU_EXT bank physical / bus address
  15823. * - BANKx_MIN_ID
  15824. * Bits 15:0
  15825. * Purpose: Provide a mechanism to specify the min index that needs to
  15826. * mapped.
  15827. * - BANKx_MAX_ID
  15828. * Bits 31:16
  15829. * Purpose: Provide a mechanism to specify the max index that needs to
  15830. * mapped.
  15831. *
  15832. */
  15833. /** @todo Compress the fields to fit MAX HTT Message size, until then configure to a
  15834. * safe value.
  15835. * @note MAX supported banks is 16.
  15836. */
  15837. #define HTT_TX_MSDU_EXT_BANK_MAX 4
  15838. #define HTT_H2T_FRAG_DESC_BANK_PDEVID_M 0x300
  15839. #define HTT_H2T_FRAG_DESC_BANK_PDEVID_S 8
  15840. #define HTT_H2T_FRAG_DESC_BANK_SWAP_M 0x400
  15841. #define HTT_H2T_FRAG_DESC_BANK_SWAP_S 10
  15842. #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M 0xff0000
  15843. #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S 16
  15844. #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M 0xff000000
  15845. #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S 24
  15846. #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M 0xffff
  15847. #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S 0
  15848. #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M 0xffff0000
  15849. #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S 16
  15850. #define HTT_H2T_FRAG_DESC_BANK_PDEVID_SET(word, value) \
  15851. do { \
  15852. HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_PDEVID, value); \
  15853. (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_PDEVID_S); \
  15854. } while (0)
  15855. #define HTT_H2T_FRAG_DESC_BANK_PDEVID_GET(word) \
  15856. (((word) & HTT_H2T_FRAG_DESC_BANK_PDEVID_M) >> HTT_H2T_FRAG_DESC_BANK_PDEVID_S)
  15857. #define HTT_H2T_FRAG_DESC_BANK_SWAP_SET(word, value) \
  15858. do { \
  15859. HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_SWAP, value); \
  15860. (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_SWAP_S); \
  15861. } while (0)
  15862. #define HTT_H2T_FRAG_DESC_BANK_SWAP_GET(word) \
  15863. (((word) & HTT_H2T_FRAG_DESC_BANK_SWAP_M) >> HTT_H2T_FRAG_DESC_BANK_SWAP_S)
  15864. #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_SET(word, value) \
  15865. do { \
  15866. HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_NUM_BANKS, value); \
  15867. (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S); \
  15868. } while (0)
  15869. #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_GET(word) \
  15870. (((word) & HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M) >> HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S)
  15871. #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_SET(word, value) \
  15872. do { \
  15873. HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_DESC_SIZE, value); \
  15874. (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S); \
  15875. } while (0)
  15876. #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_GET(word) \
  15877. (((word) & HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M) >> HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S)
  15878. #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_SET(word, value) \
  15879. do { \
  15880. HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MIN_IDX, value); \
  15881. (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S); \
  15882. } while (0)
  15883. #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_GET(word) \
  15884. (((word) & HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M) >> HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S)
  15885. #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_SET(word, value) \
  15886. do { \
  15887. HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MAX_IDX, value); \
  15888. (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S); \
  15889. } while (0)
  15890. #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_GET(word) \
  15891. (((word) & HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M) >> HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S)
  15892. /*
  15893. * TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T:
  15894. * This macro defines a htt_tx_frag_descXXX_bank_cfg_t in which any physical
  15895. * addresses are stored in a XXX-bit field.
  15896. * This macro is used to define both htt_tx_frag_desc32_bank_cfg_t and
  15897. * htt_tx_frag_desc64_bank_cfg_t structs.
  15898. */
  15899. #define TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T( \
  15900. _paddr_bits_, \
  15901. _paddr__bank_base_address_) \
  15902. PREPACK struct htt_tx_frag_desc ## _paddr_bits_ ## _bank_cfg_t { \
  15903. /** word 0 \
  15904. * msg_type: 8, \
  15905. * pdev_id: 2, \
  15906. * swap: 1, \
  15907. * reserved0: 5, \
  15908. * num_banks: 8, \
  15909. * desc_size: 8; \
  15910. */ \
  15911. A_UINT32 word0; \
  15912. /* \
  15913. * If bank_base_address is 64 bits, the upper / lower halves are stored \
  15914. * in little-endian order (bytes 0-3 in the first A_UINT32, bytes 4-7 in \
  15915. * the second A_UINT32). \
  15916. */ \
  15917. _paddr__bank_base_address_[HTT_TX_MSDU_EXT_BANK_MAX]; \
  15918. A_UINT32 bank_info[HTT_TX_MSDU_EXT_BANK_MAX]; \
  15919. } POSTPACK
  15920. /* define htt_tx_frag_desc32_bank_cfg_t */
  15921. TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(32, HTT_VAR_PADDR32(bank_base_address));
  15922. /* define htt_tx_frag_desc64_bank_cfg_t */
  15923. TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(64, HTT_VAR_PADDR64_LE(bank_base_address));
  15924. /*
  15925. * Make htt_tx_frag_desc_bank_cfg_t be an alias for either
  15926. * htt_tx_frag_desc32_bank_cfg_t or htt_tx_frag_desc64_bank_cfg_t
  15927. */
  15928. #if HTT_PADDR64
  15929. #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc64_bank_cfg_t
  15930. #else
  15931. #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc32_bank_cfg_t
  15932. #endif
  15933. /**
  15934. * @brief target -> host HTT TX Credit total count update message definition
  15935. *
  15936. * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND
  15937. *
  15938. *|31 16|15|14 9| 8 |7 0 |
  15939. *|---------------------+--+----------+-------+----------|
  15940. *|cur htt credit delta | Q| reserved | sign | msg type |
  15941. *|------------------------------------------------------|
  15942. *
  15943. * Header fields:
  15944. * - MSG_TYPE
  15945. * Bits 7:0
  15946. * Purpose: identifies this as a htt tx credit delta update message
  15947. * Value: 0xf (HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND)
  15948. * - SIGN
  15949. * Bits 8
  15950. * identifies whether credit delta is positive or negative
  15951. * Value:
  15952. * - 0x0: credit delta is positive, rebalance in some buffers
  15953. * - 0x1: credit delta is negative, rebalance out some buffers
  15954. * - reserved
  15955. * Bits 14:9
  15956. * Value: 0x0
  15957. * - TXQ_GRP
  15958. * Bit 15
  15959. * Purpose: indicates whether any tx queue group information elements
  15960. * are appended to the tx credit update message
  15961. * Value: 0 -> no tx queue group information element is present
  15962. * 1 -> a tx queue group information element immediately follows
  15963. * - DELTA_COUNT
  15964. * Bits 31:16
  15965. * Purpose: Specify current htt credit delta absolute count
  15966. */
  15967. #define HTT_TX_CREDIT_SIGN_BIT_M 0x00000100
  15968. #define HTT_TX_CREDIT_SIGN_BIT_S 8
  15969. #define HTT_TX_CREDIT_TXQ_GRP_M 0x00008000
  15970. #define HTT_TX_CREDIT_TXQ_GRP_S 15
  15971. #define HTT_TX_CREDIT_DELTA_ABS_M 0xffff0000
  15972. #define HTT_TX_CREDIT_DELTA_ABS_S 16
  15973. #define HTT_TX_CREDIT_SIGN_BIT_SET(word, value) \
  15974. do { \
  15975. HTT_CHECK_SET_VAL(HTT_TX_CREDIT_SIGN_BIT, value); \
  15976. (word) |= (value) << HTT_TX_CREDIT_SIGN_BIT_S; \
  15977. } while (0)
  15978. #define HTT_TX_CREDIT_SIGN_BIT_GET(word) \
  15979. (((word) & HTT_TX_CREDIT_SIGN_BIT_M) >> HTT_TX_CREDIT_SIGN_BIT_S)
  15980. #define HTT_TX_CREDIT_TXQ_GRP_SET(word, value) \
  15981. do { \
  15982. HTT_CHECK_SET_VAL(HTT_TX_CREDIT_TXQ_GRP, value); \
  15983. (word) |= (value) << HTT_TX_CREDIT_TXQ_GRP_S; \
  15984. } while (0)
  15985. #define HTT_TX_CREDIT_TXQ_GRP_GET(word) \
  15986. (((word) & HTT_TX_CREDIT_TXQ_GRP_M) >> HTT_TX_CREDIT_TXQ_GRP_S)
  15987. #define HTT_TX_CREDIT_DELTA_ABS_SET(word, value) \
  15988. do { \
  15989. HTT_CHECK_SET_VAL(HTT_TX_CREDIT_DELTA_ABS, value); \
  15990. (word) |= (value) << HTT_TX_CREDIT_DELTA_ABS_S; \
  15991. } while (0)
  15992. #define HTT_TX_CREDIT_DELTA_ABS_GET(word) \
  15993. (((word) & HTT_TX_CREDIT_DELTA_ABS_M) >> HTT_TX_CREDIT_DELTA_ABS_S)
  15994. #define HTT_TX_CREDIT_MSG_BYTES 4
  15995. #define HTT_TX_CREDIT_SIGN_BIT_POSITIVE 0x0
  15996. #define HTT_TX_CREDIT_SIGN_BIT_NEGATIVE 0x1
  15997. /**
  15998. * @brief HTT WDI_IPA Operation Response Message
  15999. *
  16000. * MSG_TYPE => HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE
  16001. *
  16002. * @details
  16003. * HTT WDI_IPA Operation Response message is sent by target
  16004. * to host confirming suspend or resume operation.
  16005. * |31 24|23 16|15 8|7 0|
  16006. * |----------------+----------------+----------------+----------------|
  16007. * | op_code | Rsvd | msg_type |
  16008. * |-------------------------------------------------------------------|
  16009. * | Rsvd | Response len |
  16010. * |-------------------------------------------------------------------|
  16011. * | |
  16012. * | Response-type specific info |
  16013. * | |
  16014. * | |
  16015. * |-------------------------------------------------------------------|
  16016. * Header fields:
  16017. * - MSG_TYPE
  16018. * Bits 7:0
  16019. * Purpose: Identifies this as WDI_IPA Operation Response message
  16020. * value: = 0x14 (HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE)
  16021. * - OP_CODE
  16022. * Bits 31:16
  16023. * Purpose: Identifies the operation target is responding to (e.g. TX suspend)
  16024. * value: = enum htt_wdi_ipa_op_code
  16025. * - RSP_LEN
  16026. * Bits 16:0
  16027. * Purpose: length for the response-type specific info
  16028. * value: = length in bytes for response-type specific info
  16029. * For example, if OP_CODE == HTT_WDI_IPA_OPCODE_DBG_STATS, the
  16030. * length value will be sizeof(struct wlan_wdi_ipa_dbg_stats_t).
  16031. */
  16032. PREPACK struct htt_wdi_ipa_op_response_t
  16033. {
  16034. /* DWORD 0: flags and meta-data */
  16035. A_UINT32
  16036. msg_type: 8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */
  16037. reserved1: 8,
  16038. op_code: 16;
  16039. A_UINT32
  16040. rsp_len: 16,
  16041. reserved2: 16;
  16042. } POSTPACK;
  16043. #define HTT_WDI_IPA_OP_RESPONSE_SZ 8 /* bytes */
  16044. #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M 0xffff0000
  16045. #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S 16
  16046. #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M 0x0000ffff
  16047. #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S 0
  16048. #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_GET(_var) \
  16049. (((_var) & HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M) >> HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S)
  16050. #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_SET(_var, _val) \
  16051. do { \
  16052. HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_OP_CODE, _val); \
  16053. ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S)); \
  16054. } while (0)
  16055. #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_GET(_var) \
  16056. (((_var) & HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M) >> HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S)
  16057. #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_SET(_var, _val) \
  16058. do { \
  16059. HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_RSP_LEN, _val); \
  16060. ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S)); \
  16061. } while (0)
  16062. enum htt_phy_mode {
  16063. htt_phy_mode_11a = 0,
  16064. htt_phy_mode_11g = 1,
  16065. htt_phy_mode_11b = 2,
  16066. htt_phy_mode_11g_only = 3,
  16067. htt_phy_mode_11na_ht20 = 4,
  16068. htt_phy_mode_11ng_ht20 = 5,
  16069. htt_phy_mode_11na_ht40 = 6,
  16070. htt_phy_mode_11ng_ht40 = 7,
  16071. htt_phy_mode_11ac_vht20 = 8,
  16072. htt_phy_mode_11ac_vht40 = 9,
  16073. htt_phy_mode_11ac_vht80 = 10,
  16074. htt_phy_mode_11ac_vht20_2g = 11,
  16075. htt_phy_mode_11ac_vht40_2g = 12,
  16076. htt_phy_mode_11ac_vht80_2g = 13,
  16077. htt_phy_mode_11ac_vht80_80 = 14, /* 80+80 */
  16078. htt_phy_mode_11ac_vht160 = 15,
  16079. htt_phy_mode_max,
  16080. };
  16081. /**
  16082. * @brief target -> host HTT channel change indication
  16083. *
  16084. * MSG_TYPE => HTT_T2H_MSG_TYPE_CHAN_CHANGE
  16085. *
  16086. * @details
  16087. * Specify when a channel change occurs.
  16088. * This allows the host to precisely determine which rx frames arrived
  16089. * on the old channel and which rx frames arrived on the new channel.
  16090. *
  16091. *|31 |7 0 |
  16092. *|-------------------------------------------+----------|
  16093. *| reserved | msg type |
  16094. *|------------------------------------------------------|
  16095. *| primary_chan_center_freq_mhz |
  16096. *|------------------------------------------------------|
  16097. *| contiguous_chan1_center_freq_mhz |
  16098. *|------------------------------------------------------|
  16099. *| contiguous_chan2_center_freq_mhz |
  16100. *|------------------------------------------------------|
  16101. *| phy_mode |
  16102. *|------------------------------------------------------|
  16103. *
  16104. * Header fields:
  16105. * - MSG_TYPE
  16106. * Bits 7:0
  16107. * Purpose: identifies this as a htt channel change indication message
  16108. * Value: 0x15 (HTT_T2H_MSG_TYPE_CHAN_CHANGE)
  16109. * - PRIMARY_CHAN_CENTER_FREQ_MHZ
  16110. * Bits 31:0
  16111. * Purpose: identify the (center of the) new 20 MHz primary channel
  16112. * Value: center frequency of the 20 MHz primary channel, in MHz units
  16113. * - CONTIG_CHAN1_CENTER_FREQ_MHZ
  16114. * Bits 31:0
  16115. * Purpose: identify the (center of the) contiguous frequency range
  16116. * comprising the new channel.
  16117. * For example, if the new channel is a 80 MHz channel extending
  16118. * 60 MHz beyond the primary channel, this field would be 30 larger
  16119. * than the primary channel center frequency field.
  16120. * Value: center frequency of the contiguous frequency range comprising
  16121. * the full channel in MHz units
  16122. * (80+80 channels also use the CONTIG_CHAN2 field)
  16123. * - CONTIG_CHAN2_CENTER_FREQ_MHZ
  16124. * Bits 31:0
  16125. * Purpose: Identify the (center of the) 80 MHz extension frequency range
  16126. * within a VHT 80+80 channel.
  16127. * This field is only relevant for VHT 80+80 channels.
  16128. * Value: center frequency of the 80 MHz extension channel in a VHT 80+80
  16129. * channel (arbitrary value for cases besides VHT 80+80)
  16130. * - PHY_MODE
  16131. * Bits 31:0
  16132. * Purpose: specify the PHY channel's type (legacy vs. HT vs. VHT), width,
  16133. * and band
  16134. * Value: htt_phy_mode enum value
  16135. */
  16136. PREPACK struct htt_chan_change_t
  16137. {
  16138. /* DWORD 0: flags and meta-data */
  16139. A_UINT32
  16140. msg_type: 8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */
  16141. reserved1: 24;
  16142. A_UINT32 primary_chan_center_freq_mhz;
  16143. A_UINT32 contig_chan1_center_freq_mhz;
  16144. A_UINT32 contig_chan2_center_freq_mhz;
  16145. A_UINT32 phy_mode;
  16146. } POSTPACK;
  16147. /*
  16148. * Due to historical / backwards-compatibility reasons, maintain the
  16149. * below htt_chan_change_msg struct definition, which needs to be
  16150. * consistent with the above htt_chan_change_t struct definition
  16151. * (aside from the htt_chan_change_t definition including the msg_type
  16152. * dword within the message, and the htt_chan_change_msg only containing
  16153. * the payload of the message that follows the msg_type dword).
  16154. */
  16155. PREPACK struct htt_chan_change_msg {
  16156. A_UINT32 chan_mhz; /* frequency in mhz */
  16157. A_UINT32 band_center_freq1; /* Center frequency 1 in MHz */
  16158. A_UINT32 band_center_freq2; /* Center frequency 2 in MHz - valid only for 11acvht 80plus80 mode*/
  16159. A_UINT32 chan_mode; /* WLAN_PHY_MODE of the channel defined in wlan_defs.h */
  16160. } POSTPACK;
  16161. #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M 0xffffffff
  16162. #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S 0
  16163. #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M 0xffffffff
  16164. #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S 0
  16165. #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M 0xffffffff
  16166. #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S 0
  16167. #define HTT_CHAN_CHANGE_PHY_MODE_M 0xffffffff
  16168. #define HTT_CHAN_CHANGE_PHY_MODE_S 0
  16169. #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_SET(word, value) \
  16170. do { \
  16171. HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ, value);\
  16172. (word) |= (value) << HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S; \
  16173. } while (0)
  16174. #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_GET(word) \
  16175. (((word) & HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M) \
  16176. >> HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S)
  16177. #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_SET(word, value) \
  16178. do { \
  16179. HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ, value);\
  16180. (word) |= (value) << HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S; \
  16181. } while (0)
  16182. #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_GET(word) \
  16183. (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M) \
  16184. >> HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S)
  16185. #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_SET(word, value) \
  16186. do { \
  16187. HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ, value);\
  16188. (word) |= (value) << HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S; \
  16189. } while (0)
  16190. #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_GET(word) \
  16191. (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M) \
  16192. >> HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S)
  16193. #define HTT_CHAN_CHANGE_PHY_MODE_SET(word, value) \
  16194. do { \
  16195. HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PHY_MODE, value);\
  16196. (word) |= (value) << HTT_CHAN_CHANGE_PHY_MODE_S; \
  16197. } while (0)
  16198. #define HTT_CHAN_CHANGE_PHY_MODE_GET(word) \
  16199. (((word) & HTT_CHAN_CHANGE_PHY_MODE_M) \
  16200. >> HTT_CHAN_CHANGE_PHY_MODE_S)
  16201. #define HTT_CHAN_CHANGE_BYTES sizeof(struct htt_chan_change_t)
  16202. /**
  16203. * @brief rx offload packet error message
  16204. *
  16205. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR
  16206. *
  16207. * @details
  16208. * HTT_RX_OFLD_PKT_ERR message is sent by target to host to indicate err
  16209. * of target payload like mic err.
  16210. *
  16211. * |31 24|23 16|15 8|7 0|
  16212. * |----------------+----------------+----------------+----------------|
  16213. * | tid | vdev_id | msg_sub_type | msg_type |
  16214. * |-------------------------------------------------------------------|
  16215. * : (sub-type dependent content) :
  16216. * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -:
  16217. * Header fields:
  16218. * - msg_type
  16219. * Bits 7:0
  16220. * Purpose: Identifies this as HTT_RX_OFLD_PKT_ERR message
  16221. * value: 0x16 (HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR)
  16222. * - msg_sub_type
  16223. * Bits 15:8
  16224. * Purpose: Identifies which type of rx error is reported by this message
  16225. * value: htt_rx_ofld_pkt_err_type
  16226. * - vdev_id
  16227. * Bits 23:16
  16228. * Purpose: Identifies which vdev received the erroneous rx frame
  16229. * value:
  16230. * - tid
  16231. * Bits 31:24
  16232. * Purpose: Identifies the traffic type of the rx frame
  16233. * value:
  16234. *
  16235. * - The payload fields used if the sub-type == MIC error are shown below.
  16236. * Note - MIC err is per MSDU, while PN is per MPDU.
  16237. * The FW will discard the whole MPDU if any MSDU within the MPDU is marked
  16238. * with MIC err in A-MSDU case, so FW will send only one HTT message
  16239. * with the PN of this MPDU attached to indicate MIC err for one MPDU
  16240. * instead of sending separate HTT messages for each wrong MSDU within
  16241. * the MPDU.
  16242. *
  16243. * |31 24|23 16|15 8|7 0|
  16244. * |----------------+----------------+----------------+----------------|
  16245. * | Rsvd | key_id | peer_id |
  16246. * |-------------------------------------------------------------------|
  16247. * | receiver MAC addr 31:0 |
  16248. * |-------------------------------------------------------------------|
  16249. * | Rsvd | receiver MAC addr 47:32 |
  16250. * |-------------------------------------------------------------------|
  16251. * | transmitter MAC addr 31:0 |
  16252. * |-------------------------------------------------------------------|
  16253. * | Rsvd | transmitter MAC addr 47:32 |
  16254. * |-------------------------------------------------------------------|
  16255. * | PN 31:0 |
  16256. * |-------------------------------------------------------------------|
  16257. * | Rsvd | PN 47:32 |
  16258. * |-------------------------------------------------------------------|
  16259. * - peer_id
  16260. * Bits 15:0
  16261. * Purpose: identifies which peer is frame is from
  16262. * value:
  16263. * - key_id
  16264. * Bits 23:16
  16265. * Purpose: identifies key_id of rx frame
  16266. * value:
  16267. * - RA_31_0 (receiver MAC addr 31:0)
  16268. * Bits 31:0
  16269. * Purpose: identifies by MAC address which vdev received the frame
  16270. * value: MAC address lower 4 bytes
  16271. * - RA_47_32 (receiver MAC addr 47:32)
  16272. * Bits 15:0
  16273. * Purpose: identifies by MAC address which vdev received the frame
  16274. * value: MAC address upper 2 bytes
  16275. * - TA_31_0 (transmitter MAC addr 31:0)
  16276. * Bits 31:0
  16277. * Purpose: identifies by MAC address which peer transmitted the frame
  16278. * value: MAC address lower 4 bytes
  16279. * - TA_47_32 (transmitter MAC addr 47:32)
  16280. * Bits 15:0
  16281. * Purpose: identifies by MAC address which peer transmitted the frame
  16282. * value: MAC address upper 2 bytes
  16283. * - PN_31_0
  16284. * Bits 31:0
  16285. * Purpose: Identifies pn of rx frame
  16286. * value: PN lower 4 bytes
  16287. * - PN_47_32
  16288. * Bits 15:0
  16289. * Purpose: Identifies pn of rx frame
  16290. * value:
  16291. * TKIP or CCMP: PN upper 2 bytes
  16292. * WAPI: PN bytes 6:5 (bytes 15:7 not included in this message)
  16293. */
  16294. enum htt_rx_ofld_pkt_err_type {
  16295. HTT_RX_OFLD_PKT_ERR_TYPE_NONE = 0,
  16296. HTT_RX_OFLD_PKT_ERR_TYPE_MIC_ERR,
  16297. };
  16298. /* definition for HTT_RX_OFLD_PKT_ERR msg hdr */
  16299. #define HTT_RX_OFLD_PKT_ERR_HDR_BYTES 4
  16300. #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M 0x0000ff00
  16301. #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S 8
  16302. #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_M 0x00ff0000
  16303. #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_S 16
  16304. #define HTT_RX_OFLD_PKT_ERR_TID_M 0xff000000
  16305. #define HTT_RX_OFLD_PKT_ERR_TID_S 24
  16306. #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_GET(_var) \
  16307. (((_var) & HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M) \
  16308. >> HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S)
  16309. #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_SET(_var, _val) \
  16310. do { \
  16311. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE, _val); \
  16312. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S)); \
  16313. } while (0)
  16314. #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_GET(_var) \
  16315. (((_var) & HTT_RX_OFLD_PKT_ERR_VDEV_ID_M) >> HTT_RX_OFLD_PKT_ERR_VDEV_ID_S)
  16316. #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_SET(_var, _val) \
  16317. do { \
  16318. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_VDEV_ID, _val); \
  16319. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_VDEV_ID_S)); \
  16320. } while (0)
  16321. #define HTT_RX_OFLD_PKT_ERR_TID_GET(_var) \
  16322. (((_var) & HTT_RX_OFLD_PKT_ERR_TID_M) >> HTT_RX_OFLD_PKT_ERR_TID_S)
  16323. #define HTT_RX_OFLD_PKT_ERR_TID_SET(_var, _val) \
  16324. do { \
  16325. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_TID, _val); \
  16326. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_TID_S)); \
  16327. } while (0)
  16328. /* definition for HTT_RX_OFLD_PKT_ERR_MIC_ERR msg sub-type payload */
  16329. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_BYTES 28
  16330. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M 0x0000ffff
  16331. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S 0
  16332. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M 0x00ff0000
  16333. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S 16
  16334. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M 0xffffffff
  16335. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S 0
  16336. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M 0x0000ffff
  16337. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S 0
  16338. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M 0xffffffff
  16339. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S 0
  16340. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M 0x0000ffff
  16341. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S 0
  16342. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M 0xffffffff
  16343. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S 0
  16344. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M 0x0000ffff
  16345. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S 0
  16346. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_GET(_var) \
  16347. (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M) >> \
  16348. HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S)
  16349. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_SET(_var, _val) \
  16350. do { \
  16351. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID, _val); \
  16352. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S)); \
  16353. } while (0)
  16354. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_GET(_var) \
  16355. (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M) >> \
  16356. HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S)
  16357. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_SET(_var, _val) \
  16358. do { \
  16359. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID, _val); \
  16360. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S)); \
  16361. } while (0)
  16362. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_GET(_var) \
  16363. (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M) >> \
  16364. HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S)
  16365. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_SET(_var, _val) \
  16366. do { \
  16367. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0, _val); \
  16368. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S)); \
  16369. } while (0)
  16370. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_GET(_var) \
  16371. (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M) >> \
  16372. HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S)
  16373. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_SET(_var, _val) \
  16374. do { \
  16375. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32, _val); \
  16376. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S)); \
  16377. } while (0)
  16378. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_GET(_var) \
  16379. (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M) >> \
  16380. HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S)
  16381. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_SET(_var, _val) \
  16382. do { \
  16383. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0, _val); \
  16384. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S)); \
  16385. } while (0)
  16386. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_GET(_var) \
  16387. (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M) >> \
  16388. HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S)
  16389. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_SET(_var, _val) \
  16390. do { \
  16391. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32, _val); \
  16392. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S)); \
  16393. } while (0)
  16394. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_GET(_var) \
  16395. (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M) >> \
  16396. HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S)
  16397. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_SET(_var, _val) \
  16398. do { \
  16399. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0, _val); \
  16400. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S)); \
  16401. } while (0)
  16402. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_GET(_var) \
  16403. (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M) >> \
  16404. HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S)
  16405. #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_SET(_var, _val) \
  16406. do { \
  16407. HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32, _val); \
  16408. ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S)); \
  16409. } while (0)
  16410. /**
  16411. * @brief target -> host peer rate report message
  16412. *
  16413. * MSG_TYPE => HTT_T2H_MSG_TYPE_RATE_REPORT
  16414. *
  16415. * @details
  16416. * HTT_T2H_MSG_TYPE_RATE_REPORT message is sent by target to host to indicate the
  16417. * justified rate of all the peers.
  16418. *
  16419. * |31 24|23 16|15 8|7 0|
  16420. * |----------------+----------------+----------------+----------------|
  16421. * | peer_count | | msg_type |
  16422. * |-------------------------------------------------------------------|
  16423. * : Payload (variant number of peer rate report) :
  16424. * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -:
  16425. * Header fields:
  16426. * - msg_type
  16427. * Bits 7:0
  16428. * Purpose: Identifies this as HTT_T2H_MSG_TYPE_RATE_REPORT message.
  16429. * value: 0x17 (HTT_T2H_MSG_TYPE_RATE_REPORT)
  16430. * - reserved
  16431. * Bits 15:8
  16432. * Purpose:
  16433. * value:
  16434. * - peer_count
  16435. * Bits 31:16
  16436. * Purpose: Specify how many peer rate report elements are present in the payload.
  16437. * value:
  16438. *
  16439. * Payload:
  16440. * There are variant number of peer rate report follow the first 32 bits.
  16441. * The peer rate report is defined as follows.
  16442. *
  16443. * |31 20|19 16|15 0|
  16444. * |-----------------------+---------+---------------------------------|-
  16445. * | reserved | phy | peer_id | \
  16446. * |-------------------------------------------------------------------| -> report #0
  16447. * | rate | /
  16448. * |-----------------------+---------+---------------------------------|-
  16449. * | reserved | phy | peer_id | \
  16450. * |-------------------------------------------------------------------| -> report #1
  16451. * | rate | /
  16452. * |-----------------------+---------+---------------------------------|-
  16453. * | reserved | phy | peer_id | \
  16454. * |-------------------------------------------------------------------| -> report #2
  16455. * | rate | /
  16456. * |-------------------------------------------------------------------|-
  16457. * : :
  16458. * : :
  16459. * : :
  16460. * :-------------------------------------------------------------------:
  16461. *
  16462. * - peer_id
  16463. * Bits 15:0
  16464. * Purpose: identify the peer
  16465. * value:
  16466. * - phy
  16467. * Bits 19:16
  16468. * Purpose: identify which phy is in use
  16469. * value: 0=11b, 1=11a/g, 2=11n, 3=11ac.
  16470. * Please see enum htt_peer_report_phy_type for detail.
  16471. * - reserved
  16472. * Bits 31:20
  16473. * Purpose:
  16474. * value:
  16475. * - rate
  16476. * Bits 31:0
  16477. * Purpose: represent the justified rate of the peer specified by peer_id
  16478. * value:
  16479. */
  16480. enum htt_peer_rate_report_phy_type {
  16481. HTT_PEER_RATE_REPORT_11B = 0,
  16482. HTT_PEER_RATE_REPORT_11A_G,
  16483. HTT_PEER_RATE_REPORT_11N,
  16484. HTT_PEER_RATE_REPORT_11AC,
  16485. };
  16486. #define HTT_PEER_RATE_REPORT_SIZE 8
  16487. #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M 0xffff0000
  16488. #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S 16
  16489. #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_M 0x0000ffff
  16490. #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_S 0
  16491. #define HTT_PEER_RATE_REPORT_MSG_PHY_M 0x000f0000
  16492. #define HTT_PEER_RATE_REPORT_MSG_PHY_S 16
  16493. #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_GET(_var) \
  16494. (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M) \
  16495. >> HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S)
  16496. #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_SET(_var, _val) \
  16497. do { \
  16498. HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_COUNT, _val); \
  16499. ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S)); \
  16500. } while (0)
  16501. #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_GET(_var) \
  16502. (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_ID_M) \
  16503. >> HTT_PEER_RATE_REPORT_MSG_PEER_ID_S)
  16504. #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_SET(_var, _val) \
  16505. do { \
  16506. HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_ID, _val); \
  16507. ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_ID_S)); \
  16508. } while (0)
  16509. #define HTT_PEER_RATE_REPORT_MSG_PHY_GET(_var) \
  16510. (((_var) & HTT_PEER_RATE_REPORT_MSG_PHY_M) \
  16511. >> HTT_PEER_RATE_REPORT_MSG_PHY_S)
  16512. #define HTT_PEER_RATE_REPORT_MSG_PHY_SET(_var, _val) \
  16513. do { \
  16514. HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PHY, _val); \
  16515. ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PHY_S)); \
  16516. } while (0)
  16517. /**
  16518. * @brief target -> host flow pool map message
  16519. *
  16520. * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_MAP
  16521. *
  16522. * @details
  16523. * HTT_T2H_MSG_TYPE_FLOW_POOL_MAP message is sent by the target when setting up
  16524. * a flow of descriptors.
  16525. *
  16526. * This message is in TLV format and indicates the parameters to be setup a
  16527. * flow in the host. Each entry indicates that a particular flow ID is ready to
  16528. * receive descriptors from a specified pool.
  16529. *
  16530. * The message would appear as follows:
  16531. *
  16532. * |31 24|23 16|15 8|7 0|
  16533. * |----------------+----------------+----------------+----------------|
  16534. * header | reserved | num_flows | msg_type |
  16535. * |-------------------------------------------------------------------|
  16536. * | |
  16537. * : payload :
  16538. * | |
  16539. * |-------------------------------------------------------------------|
  16540. *
  16541. * The header field is one DWORD long and is interpreted as follows:
  16542. * b'0:7 - msg_type: Set to 0x18 (HTT_T2H_MSG_TYPE_FLOW_POOL_MAP)
  16543. * b'8-15 - num_flows: This will indicate the number of flows being setup in
  16544. * this message
  16545. * b'16-31 - reserved: These bits are reserved for future use
  16546. *
  16547. * Payload:
  16548. * The payload would contain multiple objects of the following structure. Each
  16549. * object represents a flow.
  16550. *
  16551. * |31 24|23 16|15 8|7 0|
  16552. * |----------------+----------------+----------------+----------------|
  16553. * header | reserved | num_flows | msg_type |
  16554. * |-------------------------------------------------------------------|
  16555. * payload0| flow_type |
  16556. * |-------------------------------------------------------------------|
  16557. * | flow_id |
  16558. * |-------------------------------------------------------------------|
  16559. * | reserved0 | flow_pool_id |
  16560. * |-------------------------------------------------------------------|
  16561. * | reserved1 | flow_pool_size |
  16562. * |-------------------------------------------------------------------|
  16563. * | reserved2 |
  16564. * |-------------------------------------------------------------------|
  16565. * payload1| flow_type |
  16566. * |-------------------------------------------------------------------|
  16567. * | flow_id |
  16568. * |-------------------------------------------------------------------|
  16569. * | reserved0 | flow_pool_id |
  16570. * |-------------------------------------------------------------------|
  16571. * | reserved1 | flow_pool_size |
  16572. * |-------------------------------------------------------------------|
  16573. * | reserved2 |
  16574. * |-------------------------------------------------------------------|
  16575. * | . |
  16576. * | . |
  16577. * | . |
  16578. * |-------------------------------------------------------------------|
  16579. *
  16580. * Each payload is 5 DWORDS long and is interpreted as follows:
  16581. * dword0 - b'0:31 - flow_type: This indicates the type of the entity to which
  16582. * this flow is associated. It can be VDEV, peer,
  16583. * or tid (AC). Based on enum htt_flow_type.
  16584. *
  16585. * dword1 - b'0:31 - flow_id: Identifier for the flow corresponding to this
  16586. * object. For flow_type vdev it is set to the
  16587. * vdevid, for peer it is peerid and for tid, it is
  16588. * tid_num.
  16589. *
  16590. * dword2 - b'0:15 - flow_pool_id: Identifier of the descriptor-pool being used
  16591. * in the host for this flow
  16592. * b'16:31 - reserved0: This field in reserved for the future. In case
  16593. * we have a hierarchical implementation (HCM) of
  16594. * pools, it can be used to indicate the ID of the
  16595. * parent-pool.
  16596. *
  16597. * dword3 - b'0:15 - flow_pool_size: Size of the pool in number of descriptors.
  16598. * Descriptors for this flow will be
  16599. * allocated from this pool in the host.
  16600. * b'16:31 - reserved1: This field in reserved for the future. In case
  16601. * we have a hierarchical implementation of pools,
  16602. * it can be used to indicate the max number of
  16603. * descriptors in the pool. The b'0:15 can be used
  16604. * to indicate min number of descriptors in the
  16605. * HCM scheme.
  16606. *
  16607. * dword4 - b'0:31 - reserved2: This field in reserved for the future. In case
  16608. * we have a hierarchical implementation of pools,
  16609. * b'0:15 can be used to indicate the
  16610. * priority-based borrowing (PBB) threshold of
  16611. * the flow's pool. The b'16:31 are still left
  16612. * reserved.
  16613. */
  16614. enum htt_flow_type {
  16615. FLOW_TYPE_VDEV = 0,
  16616. /* Insert new flow types above this line */
  16617. };
  16618. PREPACK struct htt_flow_pool_map_payload_t {
  16619. A_UINT32 flow_type;
  16620. A_UINT32 flow_id;
  16621. A_UINT32 flow_pool_id:16,
  16622. reserved0:16;
  16623. A_UINT32 flow_pool_size:16,
  16624. reserved1:16;
  16625. A_UINT32 reserved2;
  16626. } POSTPACK;
  16627. #define HTT_FLOW_POOL_MAP_HEADER_SZ (sizeof(A_UINT32))
  16628. #define HTT_FLOW_POOL_MAP_PAYLOAD_SZ \
  16629. (sizeof(struct htt_flow_pool_map_payload_t))
  16630. #define HTT_FLOW_POOL_MAP_NUM_FLOWS_M 0x0000ff00
  16631. #define HTT_FLOW_POOL_MAP_NUM_FLOWS_S 8
  16632. #define HTT_FLOW_POOL_MAP_FLOW_TYPE_M 0xffffffff
  16633. #define HTT_FLOW_POOL_MAP_FLOW_TYPE_S 0
  16634. #define HTT_FLOW_POOL_MAP_FLOW_ID_M 0xffffffff
  16635. #define HTT_FLOW_POOL_MAP_FLOW_ID_S 0
  16636. #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M 0x0000ffff
  16637. #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S 0
  16638. #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M 0x0000ffff
  16639. #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S 0
  16640. #define HTT_FLOW_POOL_MAP_NUM_FLOWS_GET(_var) \
  16641. (((_var) & HTT_FLOW_POOL_MAP_NUM_FLOWS_M) >> HTT_FLOW_POOL_MAP_NUM_FLOWS_S)
  16642. #define HTT_FLOW_POOL_MAP_FLOW_TYPE_GET(_var) \
  16643. (((_var) & HTT_FLOW_POOL_MAP_FLOW_TYPE_M) >> HTT_FLOW_POOL_MAP_FLOW_TYPE_S)
  16644. #define HTT_FLOW_POOL_MAP_FLOW_ID_GET(_var) \
  16645. (((_var) & HTT_FLOW_POOL_MAP_FLOW_ID_M) >> HTT_FLOW_POOL_MAP_FLOW_ID_S)
  16646. #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_GET(_var) \
  16647. (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M) >> \
  16648. HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S)
  16649. #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_GET(_var) \
  16650. (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M) >> \
  16651. HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S)
  16652. #define HTT_FLOW_POOL_MAP_NUM_FLOWS_SET(_var, _val) \
  16653. do { \
  16654. HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_NUM_FLOWS, _val); \
  16655. ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_NUM_FLOWS_S)); \
  16656. } while (0)
  16657. #define HTT_FLOW_POOL_MAP_FLOW_TYPE_SET(_var, _val) \
  16658. do { \
  16659. HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_TYPE, _val); \
  16660. ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_TYPE_S)); \
  16661. } while (0)
  16662. #define HTT_FLOW_POOL_MAP_FLOW_ID_SET(_var, _val) \
  16663. do { \
  16664. HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_ID, _val); \
  16665. ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_ID_S)); \
  16666. } while (0)
  16667. #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_SET(_var, _val) \
  16668. do { \
  16669. HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_ID, _val); \
  16670. ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S)); \
  16671. } while (0)
  16672. #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_SET(_var, _val) \
  16673. do { \
  16674. HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE, _val); \
  16675. ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S)); \
  16676. } while (0)
  16677. /**
  16678. * @brief target -> host flow pool unmap message
  16679. *
  16680. * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP
  16681. *
  16682. * @details
  16683. * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP message is sent by the target when tearing
  16684. * down a flow of descriptors.
  16685. * This message indicates that for the flow (whose ID is provided) is wanting
  16686. * to stop receiving descriptors. This flow ID corresponds to the ID of the
  16687. * pool of descriptors from where descriptors are being allocated for this
  16688. * flow. When a flow (and its pool) are unmapped, all the child-pools will also
  16689. * be unmapped by the host.
  16690. *
  16691. * The message would appear as follows:
  16692. *
  16693. * |31 24|23 16|15 8|7 0|
  16694. * |----------------+----------------+----------------+----------------|
  16695. * | reserved0 | msg_type |
  16696. * |-------------------------------------------------------------------|
  16697. * | flow_type |
  16698. * |-------------------------------------------------------------------|
  16699. * | flow_id |
  16700. * |-------------------------------------------------------------------|
  16701. * | reserved1 | flow_pool_id |
  16702. * |-------------------------------------------------------------------|
  16703. *
  16704. * The message is interpreted as follows:
  16705. * dword0 - b'0:7 - msg_type: This will be set to 0x19
  16706. * (HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP)
  16707. * b'8:31 - reserved0: Reserved for future use
  16708. *
  16709. * dword1 - b'0:31 - flow_type: This indicates the type of the entity to which
  16710. * this flow is associated. It can be VDEV, peer,
  16711. * or tid (AC). Based on enum htt_flow_type.
  16712. *
  16713. * dword2 - b'0:31 - flow_id: Identifier for the flow corresponding to this
  16714. * object. For flow_type vdev it is set to the
  16715. * vdevid, for peer it is peerid and for tid, it is
  16716. * tid_num.
  16717. *
  16718. * dword3 - b'0:15 - flow_pool_id: Identifier of the descriptor-pool being
  16719. * used in the host for this flow
  16720. * b'16:31 - reserved0: This field in reserved for the future.
  16721. *
  16722. */
  16723. PREPACK struct htt_flow_pool_unmap_t {
  16724. A_UINT32 msg_type:8,
  16725. reserved0:24;
  16726. A_UINT32 flow_type;
  16727. A_UINT32 flow_id;
  16728. A_UINT32 flow_pool_id:16,
  16729. reserved1:16;
  16730. } POSTPACK;
  16731. #define HTT_FLOW_POOL_UNMAP_SZ (sizeof(struct htt_flow_pool_unmap_t))
  16732. #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M 0xffffffff
  16733. #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S 0
  16734. #define HTT_FLOW_POOL_UNMAP_FLOW_ID_M 0xffffffff
  16735. #define HTT_FLOW_POOL_UNMAP_FLOW_ID_S 0
  16736. #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M 0x0000ffff
  16737. #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S 0
  16738. #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_GET(_var) \
  16739. (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M) >> \
  16740. HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S)
  16741. #define HTT_FLOW_POOL_UNMAP_FLOW_ID_GET(_var) \
  16742. (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_ID_M) >> HTT_FLOW_POOL_UNMAP_FLOW_ID_S)
  16743. #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_GET(_var) \
  16744. (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M) >> \
  16745. HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S)
  16746. #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_SET(_var, _val) \
  16747. do { \
  16748. HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_TYPE, _val); \
  16749. ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S)); \
  16750. } while (0)
  16751. #define HTT_FLOW_POOL_UNMAP_FLOW_ID_SET(_var, _val) \
  16752. do { \
  16753. HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_ID, _val); \
  16754. ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_ID_S)); \
  16755. } while (0)
  16756. #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_SET(_var, _val) \
  16757. do { \
  16758. HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID, _val); \
  16759. ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S)); \
  16760. } while (0)
  16761. /**
  16762. * @brief target -> host SRING setup done message
  16763. *
  16764. * MSG_TYPE => HTT_T2H_MSG_TYPE_SRING_SETUP_DONE
  16765. *
  16766. * @details
  16767. * HTT_T2H_MSG_TYPE_SRING_SETUP_DONE message is sent by the target when
  16768. * SRNG ring setup is done
  16769. *
  16770. * This message indicates whether the last setup operation is successful.
  16771. * It will be sent to host when host set respose_required bit in
  16772. * HTT_H2T_MSG_TYPE_SRING_SETUP.
  16773. * The message would appear as follows:
  16774. *
  16775. * |31 24|23 16|15 8|7 0|
  16776. * |--------------- +----------------+----------------+----------------|
  16777. * | setup_status | ring_id | pdev_id | msg_type |
  16778. * |-------------------------------------------------------------------|
  16779. *
  16780. * The message is interpreted as follows:
  16781. * dword0 - b'0:7 - msg_type: This will be set to 0x1a
  16782. * (HTT_T2H_MSG_TYPE_SRING_SETUP_DONE)
  16783. * b'8:15 - pdev_id:
  16784. * 0 (for rings at SOC/UMAC level),
  16785. * 1/2/3 mac id (for rings at LMAC level)
  16786. * b'16:23 - ring_id: Identify the ring which is set up
  16787. * More details can be got from enum htt_srng_ring_id
  16788. * b'24:31 - setup_status: Indicate status of setup operation
  16789. * Refer to htt_ring_setup_status
  16790. */
  16791. PREPACK struct htt_sring_setup_done_t {
  16792. A_UINT32 msg_type: 8,
  16793. pdev_id: 8,
  16794. ring_id: 8,
  16795. setup_status: 8;
  16796. } POSTPACK;
  16797. enum htt_ring_setup_status {
  16798. htt_ring_setup_status_ok = 0,
  16799. htt_ring_setup_status_error,
  16800. };
  16801. #define HTT_SRING_SETUP_DONE_SZ (sizeof(struct htt_sring_setup_done_t))
  16802. #define HTT_SRING_SETUP_DONE_PDEV_ID_M 0x0000ff00
  16803. #define HTT_SRING_SETUP_DONE_PDEV_ID_S 8
  16804. #define HTT_SRING_SETUP_DONE_PDEV_ID_GET(_var) \
  16805. (((_var) & HTT_SRING_SETUP_DONE_PDEV_ID_M) >> \
  16806. HTT_SRING_SETUP_DONE_PDEV_ID_S)
  16807. #define HTT_SRING_SETUP_DONE_PDEV_ID_SET(_var, _val) \
  16808. do { \
  16809. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_PDEV_ID, _val); \
  16810. ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_PDEV_ID_S)); \
  16811. } while (0)
  16812. #define HTT_SRING_SETUP_DONE_RING_ID_M 0x00ff0000
  16813. #define HTT_SRING_SETUP_DONE_RING_ID_S 16
  16814. #define HTT_SRING_SETUP_DONE_RING_ID_GET(_var) \
  16815. (((_var) & HTT_SRING_SETUP_DONE_RING_ID_M) >> \
  16816. HTT_SRING_SETUP_DONE_RING_ID_S)
  16817. #define HTT_SRING_SETUP_DONE_RING_ID_SET(_var, _val) \
  16818. do { \
  16819. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_RING_ID, _val); \
  16820. ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_RING_ID_S)); \
  16821. } while (0)
  16822. #define HTT_SRING_SETUP_DONE_STATUS_M 0xff000000
  16823. #define HTT_SRING_SETUP_DONE_STATUS_S 24
  16824. #define HTT_SRING_SETUP_DONE_STATUS_GET(_var) \
  16825. (((_var) & HTT_SRING_SETUP_DONE_STATUS_M) >> \
  16826. HTT_SRING_SETUP_DONE_STATUS_S)
  16827. #define HTT_SRING_SETUP_DONE_STATUS_SET(_var, _val) \
  16828. do { \
  16829. HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_STATUS, _val); \
  16830. ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_STATUS_S)); \
  16831. } while (0)
  16832. /**
  16833. * @brief target -> flow map flow info
  16834. *
  16835. * MSG_TYPE => HTT_T2H_MSG_TYPE_MAP_FLOW_INFO
  16836. *
  16837. * @details
  16838. * HTT TX map flow entry with tqm flow pointer
  16839. * Sent from firmware to host to add tqm flow pointer in corresponding
  16840. * flow search entry. Flow metadata is replayed back to host as part of this
  16841. * struct to enable host to find the specific flow search entry
  16842. *
  16843. * The message would appear as follows:
  16844. *
  16845. * |31 28|27 18|17 14|13 8|7 0|
  16846. * |-------+------------------------------------------+----------------|
  16847. * | rsvd0 | fse_hsh_idx | msg_type |
  16848. * |-------------------------------------------------------------------|
  16849. * | rsvd1 | tid | peer_id |
  16850. * |-------------------------------------------------------------------|
  16851. * | tqm_flow_pntr_lo |
  16852. * |-------------------------------------------------------------------|
  16853. * | tqm_flow_pntr_hi |
  16854. * |-------------------------------------------------------------------|
  16855. * | fse_meta_data |
  16856. * |-------------------------------------------------------------------|
  16857. *
  16858. * The message is interpreted as follows:
  16859. *
  16860. * dword0 - b'0:7 - msg_type: This will be set to 0x1b
  16861. * (HTT_T2H_MSG_TYPE_MAP_FLOW_INFO)
  16862. *
  16863. * dword0 - b'8:27 - fse_hsh_idx: Flow search table index provided by host
  16864. * for this flow entry
  16865. *
  16866. * dword0 - b'28:31 - rsvd0: Reserved for future use
  16867. *
  16868. * dword1 - b'0:13 - peer_id: Software peer id given by host during association
  16869. *
  16870. * dword1 - b'14:17 - tid
  16871. *
  16872. * dword1 - b'18:31 - rsvd1: Reserved for future use
  16873. *
  16874. * dword2 - b'0:31 - tqm_flow_pntr_lo: Lower 32 bits of TQM flow pointer
  16875. *
  16876. * dword3 - b'0:31 - tqm_flow_pntr_hi: Higher 32 bits of TQM flow pointer
  16877. *
  16878. * dword4 - b'0:31 - fse_meta_data: Replay back TX flow search metadata
  16879. * given by host
  16880. */
  16881. PREPACK struct htt_tx_map_flow_info {
  16882. A_UINT32
  16883. msg_type: 8,
  16884. fse_hsh_idx: 20,
  16885. rsvd0: 4;
  16886. A_UINT32
  16887. peer_id: 14,
  16888. tid: 4,
  16889. rsvd1: 14;
  16890. A_UINT32 tqm_flow_pntr_lo;
  16891. A_UINT32 tqm_flow_pntr_hi;
  16892. struct htt_tx_flow_metadata fse_meta_data;
  16893. } POSTPACK;
  16894. /* DWORD 0 */
  16895. #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_M 0x0fffff00
  16896. #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S 8
  16897. /* DWORD 1 */
  16898. #define HTT_TX_MAP_FLOW_INFO_PEER_ID_M 0x00003fff
  16899. #define HTT_TX_MAP_FLOW_INFO_PEER_ID_S 0
  16900. #define HTT_TX_MAP_FLOW_INFO_TID_M 0x0003c000
  16901. #define HTT_TX_MAP_FLOW_INFO_TID_S 14
  16902. /* DWORD 0 */
  16903. #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_GET(_var) \
  16904. (((_var) & HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_M) >> \
  16905. HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S)
  16906. #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_SET(_var, _val) \
  16907. do { \
  16908. HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX, _val); \
  16909. ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S)); \
  16910. } while (0)
  16911. /* DWORD 1 */
  16912. #define HTT_TX_MAP_FLOW_INFO_PEER_ID_GET(_var) \
  16913. (((_var) & HTT_TX_MAP_FLOW_INFO_PEER_ID_M) >> \
  16914. HTT_TX_MAP_FLOW_INFO_PEER_ID_S)
  16915. #define HTT_TX_MAP_FLOW_INFO_PEER_ID_SET(_var, _val) \
  16916. do { \
  16917. HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_PEER_ID_IDX, _val); \
  16918. ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_PEER_ID_S)); \
  16919. } while (0)
  16920. #define HTT_TX_MAP_FLOW_INFO_TID_GET(_var) \
  16921. (((_var) & HTT_TX_MAP_FLOW_INFO_TID_M) >> \
  16922. HTT_TX_MAP_FLOW_INFO_TID_S)
  16923. #define HTT_TX_MAP_FLOW_INFO_TID_SET(_var, _val) \
  16924. do { \
  16925. HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_TID_IDX, _val); \
  16926. ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_TID_S)); \
  16927. } while (0)
  16928. /*
  16929. * htt_dbg_ext_stats_status -
  16930. * present - The requested stats have been delivered in full.
  16931. * This indicates that either the stats information was contained
  16932. * in its entirety within this message, or else this message
  16933. * completes the delivery of the requested stats info that was
  16934. * partially delivered through earlier STATS_CONF messages.
  16935. * partial - The requested stats have been delivered in part.
  16936. * One or more subsequent STATS_CONF messages with the same
  16937. * cookie value will be sent to deliver the remainder of the
  16938. * information.
  16939. * error - The requested stats could not be delivered, for example due
  16940. * to a shortage of memory to construct a message holding the
  16941. * requested stats.
  16942. * invalid - The requested stat type is either not recognized, or the
  16943. * target is configured to not gather the stats type in question.
  16944. */
  16945. enum htt_dbg_ext_stats_status {
  16946. HTT_DBG_EXT_STATS_STATUS_PRESENT = 0,
  16947. HTT_DBG_EXT_STATS_STATUS_PARTIAL = 1,
  16948. HTT_DBG_EXT_STATS_STATUS_ERROR = 2,
  16949. HTT_DBG_EXT_STATS_STATUS_INVALID = 3,
  16950. };
  16951. /**
  16952. * @brief target -> host ppdu stats upload
  16953. *
  16954. * MSG_TYPE => HTT_T2H_MSG_TYPE_PPDU_STATS_IND
  16955. *
  16956. * @details
  16957. * The following field definitions describe the format of the HTT target
  16958. * to host ppdu stats indication message.
  16959. *
  16960. *
  16961. * |31 24|23 16|15 12|11 10|9 8|7 0 |
  16962. * |-----------------------------+-------+-------+--------+---------------|
  16963. * | payload_size | rsvd |pdev_id|mac_id | msg type |
  16964. * |-------------+---------------+-------+-------+--------+---------------|
  16965. * | tgt_private | ppdu_id |
  16966. * |-------------+--------------------------------------------------------|
  16967. * | Timestamp in us |
  16968. * |----------------------------------------------------------------------|
  16969. * | reserved |
  16970. * |----------------------------------------------------------------------|
  16971. * | type-specific stats info |
  16972. * | (see htt_ppdu_stats.h) |
  16973. * |----------------------------------------------------------------------|
  16974. * Header fields:
  16975. * - MSG_TYPE
  16976. * Bits 7:0
  16977. * Purpose: Identifies this is a PPDU STATS indication
  16978. * message.
  16979. * Value: 0x1d (HTT_T2H_MSG_TYPE_PPDU_STATS_IND)
  16980. * - mac_id
  16981. * Bits 9:8
  16982. * Purpose: mac_id of this ppdu_id
  16983. * Value: 0-3
  16984. * - pdev_id
  16985. * Bits 11:10
  16986. * Purpose: pdev_id of this ppdu_id
  16987. * Value: 0-3
  16988. * 0 (for rings at SOC level),
  16989. * 1/2/3 PDEV -> 0/1/2
  16990. * - payload_size
  16991. * Bits 31:16
  16992. * Purpose: total tlv size
  16993. * Value: payload_size in bytes
  16994. */
  16995. #define HTT_T2H_PPDU_STATS_IND_HDR_SIZE 16
  16996. #define HTT_T2H_PPDU_STATS_MAC_ID_M 0x00000300
  16997. #define HTT_T2H_PPDU_STATS_MAC_ID_S 8
  16998. #define HTT_T2H_PPDU_STATS_PDEV_ID_M 0x00000C00
  16999. #define HTT_T2H_PPDU_STATS_PDEV_ID_S 10
  17000. #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M 0xFFFF0000
  17001. #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S 16
  17002. #define HTT_T2H_PPDU_STATS_PPDU_ID_M 0x00FFFFFF
  17003. #define HTT_T2H_PPDU_STATS_PPDU_ID_S 0
  17004. /* bits 31:24 are used by the target for internal purposes */
  17005. #define HTT_T2H_PPDU_STATS_MAC_ID_SET(word, value) \
  17006. do { \
  17007. HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_MAC_ID, value); \
  17008. (word) |= (value) << HTT_T2H_PPDU_STATS_MAC_ID_S; \
  17009. } while (0)
  17010. #define HTT_T2H_PPDU_STATS_MAC_ID_GET(word) \
  17011. (((word) & HTT_T2H_PPDU_STATS_MAC_ID_M) >> \
  17012. HTT_T2H_PPDU_STATS_MAC_ID_S)
  17013. #define HTT_T2H_PPDU_STATS_PDEV_ID_SET(word, value) \
  17014. do { \
  17015. HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PDEV_ID, value); \
  17016. (word) |= (value) << HTT_T2H_PPDU_STATS_PDEV_ID_S; \
  17017. } while (0)
  17018. #define HTT_T2H_PPDU_STATS_PDEV_ID_GET(word) \
  17019. (((word) & HTT_T2H_PPDU_STATS_PDEV_ID_M) >> \
  17020. HTT_T2H_PPDU_STATS_PDEV_ID_S)
  17021. #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_SET(word, value) \
  17022. do { \
  17023. HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PAYLOAD_SIZE, value); \
  17024. (word) |= (value) << HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S; \
  17025. } while (0)
  17026. #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_GET(word) \
  17027. (((word) & HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M) >> \
  17028. HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S)
  17029. #define HTT_T2H_PPDU_STATS_PPDU_ID_SET(word, value) \
  17030. do { \
  17031. /*HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value);*/ \
  17032. (word) |= (value) << HTT_T2H_PPDU_STATS_PPDU_ID_S; \
  17033. } while (0)
  17034. #define HTT_T2H_PPDU_STATS_PPDU_ID_GET(word) \
  17035. (((word) & HTT_T2H_PPDU_STATS_PPDU_ID_M) >> \
  17036. HTT_T2H_PPDU_STATS_PPDU_ID_S)
  17037. /* htt_t2h_ppdu_stats_ind_hdr_t
  17038. * This struct contains the fields within the header of the
  17039. * HTT_T2H_PPDU_STATS_IND message, preceding the type-specific
  17040. * stats info.
  17041. * This struct assumes little-endian layout, and thus is only
  17042. * suitable for use within processors known to be little-endian
  17043. * (such as the target).
  17044. * In contrast, the above macros provide endian-portable methods
  17045. * to get and set the bitfields within this PPDU_STATS_IND header.
  17046. */
  17047. typedef struct {
  17048. A_UINT32 msg_type: 8, /* bits 7:0 */
  17049. mac_id: 2, /* bits 9:8 */
  17050. pdev_id: 2, /* bits 11:10 */
  17051. reserved1: 4, /* bits 15:12 */
  17052. payload_size: 16; /* bits 31:16 */
  17053. A_UINT32 ppdu_id;
  17054. A_UINT32 timestamp_us;
  17055. A_UINT32 reserved2;
  17056. } htt_t2h_ppdu_stats_ind_hdr_t;
  17057. /**
  17058. * @brief target -> host extended statistics upload
  17059. *
  17060. * MSG_TYPE => HTT_T2H_MSG_TYPE_EXT_STATS_CONF
  17061. *
  17062. * @details
  17063. * The following field definitions describe the format of the HTT target
  17064. * to host stats upload confirmation message.
  17065. * The message contains a cookie echoed from the HTT host->target stats
  17066. * upload request, which identifies which request the confirmation is
  17067. * for, and a single stats can span over multiple HTT stats indication
  17068. * due to the HTT message size limitation so every HTT ext stats indication
  17069. * will have tag-length-value stats information elements.
  17070. * The tag-length header for each HTT stats IND message also includes a
  17071. * status field, to indicate whether the request for the stat type in
  17072. * question was fully met, partially met, unable to be met, or invalid
  17073. * (if the stat type in question is disabled in the target).
  17074. * A Done bit 1's indicate the end of the of stats info elements.
  17075. *
  17076. *
  17077. * |31 16|15 12|11|10 8|7 5|4 0|
  17078. * |--------------------------------------------------------------|
  17079. * | reserved | msg type |
  17080. * |--------------------------------------------------------------|
  17081. * | cookie LSBs |
  17082. * |--------------------------------------------------------------|
  17083. * | cookie MSBs |
  17084. * |--------------------------------------------------------------|
  17085. * | stats entry length | rsvd | D| S | stat type |
  17086. * |--------------------------------------------------------------|
  17087. * | type-specific stats info |
  17088. * | (see htt_stats.h) |
  17089. * |--------------------------------------------------------------|
  17090. * Header fields:
  17091. * - MSG_TYPE
  17092. * Bits 7:0
  17093. * Purpose: Identifies this is a extended statistics upload confirmation
  17094. * message.
  17095. * Value: 0x1c (HTT_T2H_MSG_TYPE_EXT_STATS_CONF)
  17096. * - COOKIE_LSBS
  17097. * Bits 31:0
  17098. * Purpose: Provide a mechanism to match a target->host stats confirmation
  17099. * message with its preceding host->target stats request message.
  17100. * Value: LSBs of the opaque cookie specified by the host-side requestor
  17101. * - COOKIE_MSBS
  17102. * Bits 31:0
  17103. * Purpose: Provide a mechanism to match a target->host stats confirmation
  17104. * message with its preceding host->target stats request message.
  17105. * Value: MSBs of the opaque cookie specified by the host-side requestor
  17106. *
  17107. * Stats Information Element tag-length header fields:
  17108. * - STAT_TYPE
  17109. * Bits 7:0
  17110. * Purpose: identifies the type of statistics info held in the
  17111. * following information element
  17112. * Value: htt_dbg_ext_stats_type
  17113. * - STATUS
  17114. * Bits 10:8
  17115. * Purpose: indicate whether the requested stats are present
  17116. * Value: htt_dbg_ext_stats_status
  17117. * - DONE
  17118. * Bits 11
  17119. * Purpose:
  17120. * Indicates the completion of the stats entry, this will be the last
  17121. * stats conf HTT segment for the requested stats type.
  17122. * Value:
  17123. * 0 -> the stats retrieval is ongoing
  17124. * 1 -> the stats retrieval is complete
  17125. * - LENGTH
  17126. * Bits 31:16
  17127. * Purpose: indicate the stats information size
  17128. * Value: This field specifies the number of bytes of stats information
  17129. * that follows the element tag-length header.
  17130. * It is expected but not required that this length is a multiple of
  17131. * 4 bytes.
  17132. */
  17133. #define HTT_T2H_EXT_STATS_COOKIE_SIZE 8
  17134. #define HTT_T2H_EXT_STATS_CONF_HDR_SIZE 4
  17135. #define HTT_T2H_EXT_STATS_CONF_TLV_HDR_SIZE 4
  17136. #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_M 0x000000ff
  17137. #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S 0
  17138. #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_M 0x00000700
  17139. #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S 8
  17140. #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_M 0x00000800
  17141. #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_S 11
  17142. #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_M 0xffff0000
  17143. #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S 16
  17144. #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_SET(word, value) \
  17145. do { \
  17146. HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_TYPE, value); \
  17147. (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S; \
  17148. } while (0)
  17149. #define HTT_T2H_EXT_STATS_CONF_TLV_TYPE_GET(word) \
  17150. (((word) & HTT_T2H_EXT_STATS_CONF_TLV_TYPE_M) >> \
  17151. HTT_T2H_EXT_STATS_CONF_TLV_TYPE_S)
  17152. #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_SET(word, value) \
  17153. do { \
  17154. HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_STATUS, value); \
  17155. (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S; \
  17156. } while (0)
  17157. #define HTT_T2H_EXT_STATS_CONF_TLV_STATUS_GET(word) \
  17158. (((word) & HTT_T2H_EXT_STATS_CONF_TLV_STATUS_M) >> \
  17159. HTT_T2H_EXT_STATS_CONF_TLV_STATUS_S)
  17160. #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_SET(word, value) \
  17161. do { \
  17162. HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_DONE, value); \
  17163. (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_DONE_S; \
  17164. } while (0)
  17165. #define HTT_T2H_EXT_STATS_CONF_TLV_DONE_GET(word) \
  17166. (((word) & HTT_T2H_EXT_STATS_CONF_TLV_DONE_M) >> \
  17167. HTT_T2H_EXT_STATS_CONF_TLV_DONE_S)
  17168. #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_SET(word, value) \
  17169. do { \
  17170. HTT_CHECK_SET_VAL(HTT_T2H_EXT_STATS_CONF_TLV_LENGTH, value); \
  17171. (word) |= (value) << HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S; \
  17172. } while (0)
  17173. #define HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_GET(word) \
  17174. (((word) & HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_M) >> \
  17175. HTT_T2H_EXT_STATS_CONF_TLV_LENGTH_S)
  17176. /**
  17177. * @brief target -> host streaming statistics upload
  17178. *
  17179. * MSG_TYPE => HTT_T2H_MSG_TYPE_STREAMING_STATS_IND
  17180. *
  17181. * @details
  17182. * The following field definitions describe the format of the HTT target
  17183. * to host streaming stats upload indication message.
  17184. * The host can use a STREAMING_STATS_REQ message to enable the target to
  17185. * produce an ongoing series of STREAMING_STATS_IND messages, and can also
  17186. * use the STREAMING_STATS_REQ message to halt the target's production of
  17187. * STREAMING_STATS_IND messages.
  17188. * The STREAMING_STATS_IND message contains a payload of TLVs containing
  17189. * the stats enabled by the host's STREAMING_STATS_REQ message.
  17190. *
  17191. * |31 8|7 0|
  17192. * |--------------------------------------------------------------|
  17193. * | reserved | msg type |
  17194. * |--------------------------------------------------------------|
  17195. * | type-specific stats info |
  17196. * | (see htt_stats.h) |
  17197. * |--------------------------------------------------------------|
  17198. * Header fields:
  17199. * - MSG_TYPE
  17200. * Bits 7:0
  17201. * Purpose: Identifies this as a streaming statistics upload indication
  17202. * message.
  17203. * Value: 0x2f (HTT_T2H_MSG_TYPE_STREAMING_STATS_IND)
  17204. */
  17205. #define HTT_T2H_STREAMING_STATS_IND_HDR_SIZE 4
  17206. typedef enum {
  17207. HTT_PEER_TYPE_DEFAULT = 0, /* Generic/Non-BSS/Self Peer */
  17208. HTT_PEER_TYPE_BSS = 1, /* Peer is BSS Peer entry */
  17209. HTT_PEER_TYPE_TDLS = 2, /* Peer is a TDLS Peer */
  17210. HTT_PEER_TYPE_OCB = 3, /* Peer is a OCB Peer */
  17211. HTT_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */
  17212. HTT_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */
  17213. /* Reserved from 128 - 255 for target internal use.*/
  17214. HTT_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */
  17215. } HTT_PEER_TYPE;
  17216. /** macro to convert MAC address from char array to HTT word format */
  17217. #define HTT_CHAR_ARRAY_TO_MAC_ADDR(c_macaddr, phtt_mac_addr) do { \
  17218. (phtt_mac_addr)->mac_addr31to0 = \
  17219. (((c_macaddr)[0] << 0) | \
  17220. ((c_macaddr)[1] << 8) | \
  17221. ((c_macaddr)[2] << 16) | \
  17222. ((c_macaddr)[3] << 24)); \
  17223. (phtt_mac_addr)->mac_addr47to32 = ((c_macaddr)[4] | ((c_macaddr)[5] << 8));\
  17224. } while (0)
  17225. /**
  17226. * @brief target -> host monitor mac header indication message
  17227. *
  17228. * MSG_TYPE => HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND
  17229. *
  17230. * @details
  17231. * The following diagram shows the format of the monitor mac header message
  17232. * sent from the target to the host.
  17233. * This message is primarily sent when promiscuous rx mode is enabled.
  17234. * One message is sent per rx PPDU.
  17235. *
  17236. * |31 24|23 16|15 8|7 0|
  17237. * |-------------------------------------------------------------|
  17238. * | peer_id | reserved0 | msg_type |
  17239. * |-------------------------------------------------------------|
  17240. * | reserved1 | num_mpdu |
  17241. * |-------------------------------------------------------------|
  17242. * | struct hw_rx_desc |
  17243. * | (see wal_rx_desc.h) |
  17244. * |-------------------------------------------------------------|
  17245. * | struct ieee80211_frame_addr4 |
  17246. * | (see ieee80211_defs.h) |
  17247. * |-------------------------------------------------------------|
  17248. * | struct ieee80211_frame_addr4 |
  17249. * | (see ieee80211_defs.h) |
  17250. * |-------------------------------------------------------------|
  17251. * | ...... |
  17252. * |-------------------------------------------------------------|
  17253. *
  17254. * Header fields:
  17255. * - msg_type
  17256. * Bits 7:0
  17257. * Purpose: Identifies this is a monitor mac header indication message.
  17258. * Value: 0x20 (HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND)
  17259. * - peer_id
  17260. * Bits 31:16
  17261. * Purpose: Software peer id given by host during association,
  17262. * During promiscuous mode, the peer ID will be invalid (0xFF)
  17263. * for rx PPDUs received from unassociated peers.
  17264. * Value: peer ID (for associated peers) or 0xFF (for unassociated peers)
  17265. * - num_mpdu
  17266. * Bits 15:0
  17267. * Purpose: The number of MPDU frame headers (struct ieee80211_frame_addr4)
  17268. * delivered within the message.
  17269. * Value: 1 to 32
  17270. * num_mpdu is limited to a maximum value of 32, due to buffer
  17271. * size limits. For PPDUs with more than 32 MPDUs, only the
  17272. * ieee80211_frame_addr4 headers from the first 32 MPDUs within
  17273. * the PPDU will be provided.
  17274. */
  17275. #define HTT_T2H_MONITOR_MAC_HEADER_IND_HDR_SIZE 8
  17276. #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_M 0xFFFF0000
  17277. #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S 16
  17278. #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_M 0x0000FFFF
  17279. #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S 0
  17280. #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_SET(word, value) \
  17281. do { \
  17282. HTT_CHECK_SET_VAL(HTT_T2H_MONITOR_MAC_HEADER_PEER_ID, value); \
  17283. (word) |= (value) << HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S; \
  17284. } while (0)
  17285. #define HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_GET(word) \
  17286. (((word) & HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_M) >> \
  17287. HTT_T2H_MONITOR_MAC_HEADER_PEER_ID_S)
  17288. #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_SET(word, value) \
  17289. do { \
  17290. HTT_CHECK_SET_VAL(HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU, value); \
  17291. (word) |= (value) << HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S; \
  17292. } while (0)
  17293. #define HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_GET(word) \
  17294. (((word) & HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_M) >> \
  17295. HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S)
  17296. /**
  17297. * @brief target -> host flow pool resize Message
  17298. *
  17299. * MSG_TYPE => HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE
  17300. *
  17301. * @details
  17302. * HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE message is sent by the target when
  17303. * the flow pool associated with the specified ID is resized
  17304. *
  17305. * The message would appear as follows:
  17306. *
  17307. * |31 16|15 8|7 0|
  17308. * |---------------------------------+----------------+----------------|
  17309. * | reserved0 | Msg type |
  17310. * |-------------------------------------------------------------------|
  17311. * | flow pool new size | flow pool ID |
  17312. * |-------------------------------------------------------------------|
  17313. *
  17314. * The message is interpreted as follows:
  17315. * b'0:7 - msg_type: This will be set to 0x21
  17316. * (HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE)
  17317. *
  17318. * b'0:15 - flow pool ID: Existing flow pool ID
  17319. *
  17320. * b'16:31 - flow pool new size: new pool size for existing flow pool ID
  17321. *
  17322. */
  17323. PREPACK struct htt_flow_pool_resize_t {
  17324. A_UINT32 msg_type:8,
  17325. reserved0:24;
  17326. A_UINT32 flow_pool_id:16,
  17327. flow_pool_new_size:16;
  17328. } POSTPACK;
  17329. #define HTT_FLOW_POOL_RESIZE_SZ (sizeof(struct htt_flow_pool_resize_t))
  17330. #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_M 0x0000ffff
  17331. #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S 0
  17332. #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_M 0xffff0000
  17333. #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S 16
  17334. #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_GET(_var) \
  17335. (((_var) & HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_M) >> \
  17336. HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S)
  17337. #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_SET(_var, _val) \
  17338. do { \
  17339. HTT_CHECK_SET_VAL(HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID, _val); \
  17340. ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S)); \
  17341. } while (0)
  17342. #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_GET(_var) \
  17343. (((_var) & HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_M) >> \
  17344. HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S)
  17345. #define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_SET(_var, _val) \
  17346. do { \
  17347. HTT_CHECK_SET_VAL(HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE, _val); \
  17348. ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S)); \
  17349. } while (0)
  17350. #define HTT_CFR_CAPTURE_MAGIC_PATTERN 0xCCCCCCCC
  17351. #define HTT_CFR_CAPTURE_READ_INDEX_OFFSET 0 /* bytes */
  17352. #define HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES 4
  17353. #define HTT_CFR_CAPTURE_WRITE_INDEX_OFFSET /* bytes */ \
  17354. (HTT_CFR_CAPTURE_READ_INDEX_OFFSET + HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES)
  17355. #define HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES 4
  17356. #define HTT_CFR_CAPTURE_SIZEOF_MAGIC_PATTERN_BYTES 4
  17357. /*
  17358. * The read and write indices point to the data within the host buffer.
  17359. * Because the first 4 bytes of the host buffer is used for the read index and
  17360. * the next 4 bytes for the write index, the data itself starts at offset 8.
  17361. * The read index and write index are the byte offsets from the base of the
  17362. * meta-data buffer, and thus have a minimum value of 8 rather than 0.
  17363. * Refer the ASCII text picture below.
  17364. */
  17365. #define HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX \
  17366. (HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES + \
  17367. HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES)
  17368. /*
  17369. ***************************************************************************
  17370. *
  17371. * Layout when CFR capture message type is 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1'
  17372. *
  17373. ***************************************************************************
  17374. *
  17375. * The memory allocated by WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID is used
  17376. * in the below format. The HTT message 'htt_cfr_dump_compl_ind' is sent by
  17377. * FW to Host whenever a CFR capture (CFR data1 or CFR data2 etc.,) is
  17378. * written into the Host memory region mentioned below.
  17379. *
  17380. * Read index is updated by the Host. At any point of time, the read index will
  17381. * indicate the index that will next be read by the Host. The read index is
  17382. * in units of bytes offset from the base of the meta-data buffer.
  17383. *
  17384. * Write index is updated by the FW. At any point of time, the write index will
  17385. * indicate from where the FW can start writing any new data. The write index is
  17386. * in units of bytes offset from the base of the meta-data buffer.
  17387. *
  17388. * If the Host is not fast enough in reading the CFR data, any new capture data
  17389. * would be dropped if there is no space left to write the new captures.
  17390. *
  17391. * The last 4 bytes of the memory region will have the magic pattern
  17392. * HTT_CFR_CAPTURE_MAGIC_PATTERN. This can be used to ensure that the FW does
  17393. * not overrun the host buffer.
  17394. *
  17395. * ,--------------------. read and write indices store the
  17396. * | | byte offset from the base of the
  17397. * | ,--------+--------. meta-data buffer to the next
  17398. * | | | | location within the data buffer
  17399. * | | v v that will be read / written
  17400. * ************************************************************************
  17401. * * Read * Write * * Magic *
  17402. * * index * index * CFR data1 ...... CFR data N * pattern *
  17403. * * (4 bytes) * (4 bytes) * * (4 bytes)*
  17404. * ************************************************************************
  17405. * |<---------- data buffer ---------->|
  17406. *
  17407. * |<----------------- meta-data buffer allocated in Host ----------------|
  17408. *
  17409. * Note:
  17410. * - Considering the 4 bytes needed to store the Read index (R) and the
  17411. * Write index (W), the initial value is as follows:
  17412. * R = W = HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX
  17413. * - Buffer empty condition:
  17414. * R = W
  17415. *
  17416. * Regarding CFR data format:
  17417. * --------------------------
  17418. *
  17419. * Each CFR tone is stored in HW as 16-bits with the following format:
  17420. * {bits[15:12], bits[11:6], bits[5:0]} =
  17421. * {unsigned exponent (4 bits),
  17422. * signed mantissa_real (6 bits),
  17423. * signed mantissa_imag (6 bits)}
  17424. *
  17425. * CFR_real = mantissa_real * 2^(exponent-5)
  17426. * CFR_imag = mantissa_imag * 2^(exponent-5)
  17427. *
  17428. *
  17429. * The CFR data is written to the 16-bit unsigned output array (buff) in
  17430. * ascending tone order. For example, the Legacy20 CFR is output as follows:
  17431. *
  17432. * buff[0]: [CFR_exp[-26], CFR_mant_real[-26], CFR_mant_imag[-26]]
  17433. * buff[1]: [CFR_exp[-25], CFR_mant_real[-25], CFR_mant_imag[-25]]
  17434. * .
  17435. * .
  17436. * .
  17437. * buff[N-2]: [CFR_exp[25], CFR_mant_real[25], CFR_mant_imag[25]]
  17438. * buff[N-1]: [CFR_exp[26], CFR_mant_real[26], CFR_mant_imag[26]]
  17439. */
  17440. /* Bandwidth of peer CFR captures */
  17441. typedef enum {
  17442. HTT_PEER_CFR_CAPTURE_BW_20MHZ = 0,
  17443. HTT_PEER_CFR_CAPTURE_BW_40MHZ = 1,
  17444. HTT_PEER_CFR_CAPTURE_BW_80MHZ = 2,
  17445. HTT_PEER_CFR_CAPTURE_BW_160MHZ = 3,
  17446. HTT_PEER_CFR_CAPTURE_BW_80_80MHZ = 4,
  17447. HTT_PEER_CFR_CAPTURE_BW_MAX,
  17448. } HTT_PEER_CFR_CAPTURE_BW;
  17449. /* Mode of the peer CFR captures. The type of RX frame for which the CFR
  17450. * was captured
  17451. */
  17452. typedef enum {
  17453. HTT_PEER_CFR_CAPTURE_MODE_LEGACY = 0,
  17454. HTT_PEER_CFR_CAPTURE_MODE_DUP_LEGACY = 1,
  17455. HTT_PEER_CFR_CAPTURE_MODE_HT = 2,
  17456. HTT_PEER_CFR_CAPTURE_MODE_VHT = 3,
  17457. HTT_PEER_CFR_CAPTURE_MODE_MAX,
  17458. } HTT_PEER_CFR_CAPTURE_MODE;
  17459. typedef enum {
  17460. /* This message type is currently used for the below purpose:
  17461. *
  17462. * - capture_method = WMI_PEER_CFR_CAPTURE_METHOD_NULL_FRAME in the
  17463. * wmi_peer_cfr_capture_cmd.
  17464. * If payload_present bit is set to 0 then the associated memory region
  17465. * gets allocated through WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID.
  17466. * If payload_present bit is set to 1 then CFR dump is part of the HTT
  17467. * message; the CFR dump will be present at the end of the message,
  17468. * after the chan_phy_mode.
  17469. */
  17470. HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 = 0x1,
  17471. /* Always keep this last */
  17472. HTT_PEER_CFR_CAPTURE_MSG_TYPE_MAX,
  17473. } HTT_PEER_CFR_CAPTURE_MSG_TYPE;
  17474. /**
  17475. * @brief target -> host CFR dump completion indication message definition
  17476. * htt_cfr_dump_compl_ind when the version is HTT_PEER_CFR_CAPTURE_MSG_TYPE_1.
  17477. *
  17478. * MSG_TYPE => HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND
  17479. *
  17480. * @details
  17481. * The following diagram shows the format of the Channel Frequency Response
  17482. * (CFR) dump completion indication. This inidcation is sent to the Host when
  17483. * the channel capture of a peer is copied by Firmware into the Host memory
  17484. *
  17485. * **************************************************************************
  17486. *
  17487. * Message format when the CFR capture message type is
  17488. * 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1'
  17489. *
  17490. * **************************************************************************
  17491. *
  17492. * |31 16|15 |8|7 0|
  17493. * |----------------------------------------------------------------|
  17494. * header: | reserved |P| msg_type |
  17495. * word 0 | | | |
  17496. * |----------------------------------------------------------------|
  17497. * payload: | cfr_capture_msg_type |
  17498. * word 1 | |
  17499. * |----------------------------------------------------------------|
  17500. * | vdev_id | captype | chbw | sts | mode | capbw |S| req_id |
  17501. * word 2 | | | | | | | | |
  17502. * |----------------------------------------------------------------|
  17503. * | mac_addr31to0 |
  17504. * word 3 | |
  17505. * |----------------------------------------------------------------|
  17506. * | unused / reserved | mac_addr47to32 |
  17507. * word 4 | | |
  17508. * |----------------------------------------------------------------|
  17509. * | index |
  17510. * word 5 | |
  17511. * |----------------------------------------------------------------|
  17512. * | length |
  17513. * word 6 | |
  17514. * |----------------------------------------------------------------|
  17515. * | timestamp |
  17516. * word 7 | |
  17517. * |----------------------------------------------------------------|
  17518. * | counter |
  17519. * word 8 | |
  17520. * |----------------------------------------------------------------|
  17521. * | chan_mhz |
  17522. * word 9 | |
  17523. * |----------------------------------------------------------------|
  17524. * | band_center_freq1 |
  17525. * word 10 | |
  17526. * |----------------------------------------------------------------|
  17527. * | band_center_freq2 |
  17528. * word 11 | |
  17529. * |----------------------------------------------------------------|
  17530. * | chan_phy_mode |
  17531. * word 12 | |
  17532. * |----------------------------------------------------------------|
  17533. * where,
  17534. * P - payload present bit (payload_present explained below)
  17535. * req_id - memory request id (mem_req_id explained below)
  17536. * S - status field (status explained below)
  17537. * capbw - capture bandwidth (capture_bw explained below)
  17538. * mode - mode of capture (mode explained below)
  17539. * sts - space time streams (sts_count explained below)
  17540. * chbw - channel bandwidth (channel_bw explained below)
  17541. * captype - capture type (cap_type explained below)
  17542. *
  17543. * The following field definitions describe the format of the CFR dump
  17544. * completion indication sent from the target to the host
  17545. *
  17546. * Header fields:
  17547. *
  17548. * Word 0
  17549. * - msg_type
  17550. * Bits 7:0
  17551. * Purpose: Identifies this as CFR TX completion indication
  17552. * Value: 0x22 (HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND)
  17553. * - payload_present
  17554. * Bit 8
  17555. * Purpose: Identifies how CFR data is sent to host
  17556. * Value: 0 - If CFR Payload is written to host memory
  17557. * 1 - If CFR Payload is sent as part of HTT message
  17558. * (This is the requirement for SDIO/USB where it is
  17559. * not possible to write CFR data to host memory)
  17560. * - reserved
  17561. * Bits 31:9
  17562. * Purpose: Reserved
  17563. * Value: 0
  17564. *
  17565. * Payload fields:
  17566. *
  17567. * Word 1
  17568. * - cfr_capture_msg_type
  17569. * Bits 31:0
  17570. * Purpose: Contains the type of the message HTT_PEER_CFR_CAPTURE_MSG_TYPE
  17571. * to specify the format used for the remainder of the message
  17572. * Value: HTT_PEER_CFR_CAPTURE_MSG_TYPE_1
  17573. * (currently only MSG_TYPE_1 is defined)
  17574. *
  17575. * Word 2
  17576. * - mem_req_id
  17577. * Bits 6:0
  17578. * Purpose: Contain the mem request id of the region where the CFR capture
  17579. * has been stored - of type WMI_HOST_MEM_REQ_ID
  17580. * Value: WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID (if payload_present is 1,
  17581. this value is invalid)
  17582. * - status
  17583. * Bit 7
  17584. * Purpose: Boolean value carrying the status of the CFR capture of the peer
  17585. * Value: 1 (True) - Successful; 0 (False) - Not successful
  17586. * - capture_bw
  17587. * Bits 10:8
  17588. * Purpose: Carry the bandwidth of the CFR capture
  17589. * Value: Bandwidth of the CFR capture of type HTT_PEER_CFR_CAPTURE_BW
  17590. * - mode
  17591. * Bits 13:11
  17592. * Purpose: Carry the mode of the rx frame for which the CFR was captured
  17593. * Value: Mode of the CFR capture of type HTT_PEER_CFR_CAPTURE_MODE
  17594. * - sts_count
  17595. * Bits 16:14
  17596. * Purpose: Carry the number of space time streams
  17597. * Value: Number of space time streams
  17598. * - channel_bw
  17599. * Bits 19:17
  17600. * Purpose: Carry the bandwidth of the channel of the vdev performing the
  17601. * measurement
  17602. * Value: Bandwidth of the channel (of type HTT_PEER_CFR_CAPTURE_BW)
  17603. * - cap_type
  17604. * Bits 23:20
  17605. * Purpose: Carry the type of the capture
  17606. * Value: Capture type (of type WMI_PEER_CFR_CAPTURE_METHOD)
  17607. * - vdev_id
  17608. * Bits 31:24
  17609. * Purpose: Carry the virtual device id
  17610. * Value: vdev ID
  17611. *
  17612. * Word 3
  17613. * - mac_addr31to0
  17614. * Bits 31:0
  17615. * Purpose: Contain the bits 31:0 of the peer MAC address
  17616. * Value: Bits 31:0 of the peer MAC address
  17617. *
  17618. * Word 4
  17619. * - mac_addr47to32
  17620. * Bits 15:0
  17621. * Purpose: Contain the bits 47:32 of the peer MAC address
  17622. * Value: Bits 47:32 of the peer MAC address
  17623. *
  17624. * Word 5
  17625. * - index
  17626. * Bits 31:0
  17627. * Purpose: Contain the index at which this CFR dump was written in the Host
  17628. * allocated memory. This index is the number of bytes from the base address.
  17629. * Value: Index position
  17630. *
  17631. * Word 6
  17632. * - length
  17633. * Bits 31:0
  17634. * Purpose: Carry the length of the CFR capture of the peer, in bytes
  17635. * Value: Length of the CFR capture of the peer
  17636. *
  17637. * Word 7
  17638. * - timestamp
  17639. * Bits 31:0
  17640. * Purpose: Carry the time at which the CFR was captured in the hardware. The
  17641. * clock used for this timestamp is private to the target and not visible to
  17642. * the host i.e., Host can interpret only the relative timestamp deltas from
  17643. * one message to the next, but can't interpret the absolute timestamp from a
  17644. * single message.
  17645. * Value: Timestamp in microseconds
  17646. *
  17647. * Word 8
  17648. * - counter
  17649. * Bits 31:0
  17650. * Purpose: Carry the count of the current CFR capture from FW. This is
  17651. * helpful to identify any drops in FW in any scenario (e.g., lack of space
  17652. * in host memory)
  17653. * Value: Count of the current CFR capture
  17654. *
  17655. * Word 9
  17656. * - chan_mhz
  17657. * Bits 31:0
  17658. * Purpose: Carry the primary 20 MHz channel frequency in MHz of the VDEV
  17659. * Value: Primary 20 channel frequency
  17660. *
  17661. * Word 10
  17662. * - band_center_freq1
  17663. * Bits 31:0
  17664. * Purpose: Carry the center frequency 1 in MHz of the VDEV
  17665. * Value: Center frequency 1 in MHz
  17666. *
  17667. * Word 11
  17668. * - band_center_freq2
  17669. * Bits 31:0
  17670. * Purpose: Carry the center frequency 2 in MHz. valid only for 11acvht of
  17671. * the VDEV
  17672. * 80plus80 mode
  17673. * Value: Center frequency 2 in MHz
  17674. *
  17675. * Word 12
  17676. * - chan_phy_mode
  17677. * Bits 31:0
  17678. * Purpose: Carry the phy mode of the channel, of the VDEV
  17679. * Value: WLAN_PHY_MODE of the channel defined in wlan_defs.h
  17680. */
  17681. PREPACK struct htt_cfr_dump_ind_type_1 {
  17682. A_UINT32 mem_req_id:7,
  17683. status:1,
  17684. capture_bw:3,
  17685. mode:3,
  17686. sts_count:3,
  17687. channel_bw:3,
  17688. cap_type:4,
  17689. vdev_id:8;
  17690. htt_mac_addr addr;
  17691. A_UINT32 index;
  17692. A_UINT32 length;
  17693. A_UINT32 timestamp;
  17694. A_UINT32 counter;
  17695. struct htt_chan_change_msg chan;
  17696. } POSTPACK;
  17697. PREPACK struct htt_cfr_dump_compl_ind {
  17698. A_UINT32 msg_type; /* HTT_PEER_CFR_CAPTURE_MSG_TYPE */
  17699. union {
  17700. /* Message format when msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 */
  17701. struct htt_cfr_dump_ind_type_1 htt_cfr_dump_compl_ind_type_1;
  17702. /* If there is a need to change the memory layout and its associated
  17703. * HTT indication format, a new CFR capture message type can be
  17704. * introduced and added into this union.
  17705. */
  17706. };
  17707. } POSTPACK;
  17708. /*
  17709. * Get / set macros for the bit fields within WORD-1 of htt_cfr_dump_compl_ind,
  17710. * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1
  17711. */
  17712. #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_M 0x00000100
  17713. #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S 8
  17714. #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_SET(word, value) \
  17715. do { \
  17716. HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID, value); \
  17717. (word) |= (value) << HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S; \
  17718. } while(0)
  17719. #define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_GET(word) \
  17720. (((word) & HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_M) >> \
  17721. HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S)
  17722. /*
  17723. * Get / set macros for the bit fields within WORD-2 of htt_cfr_dump_compl_ind,
  17724. * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1
  17725. */
  17726. #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M 0X0000007F
  17727. #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S 0
  17728. #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_M 0X00000080
  17729. #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_S 7
  17730. #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M 0X00000700
  17731. #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S 8
  17732. #define HTT_T2H_CFR_DUMP_TYPE1_MODE_M 0X00003800
  17733. #define HTT_T2H_CFR_DUMP_TYPE1_MODE_S 11
  17734. #define HTT_T2H_CFR_DUMP_TYPE1_STS_M 0X0001C000
  17735. #define HTT_T2H_CFR_DUMP_TYPE1_STS_S 14
  17736. #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M 0X000E0000
  17737. #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S 17
  17738. #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M 0X00F00000
  17739. #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S 20
  17740. #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M 0XFF000000
  17741. #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S 24
  17742. #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_SET(word, value) \
  17743. do { \
  17744. HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID, value); \
  17745. (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S; \
  17746. } while (0)
  17747. #define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_GET(word) \
  17748. (((word) & HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M) >> \
  17749. HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S)
  17750. #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_SET(word, value) \
  17751. do { \
  17752. HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STATUS, value); \
  17753. (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STATUS_S; \
  17754. } while (0)
  17755. #define HTT_T2H_CFR_DUMP_TYPE1_STATUS_GET(word) \
  17756. (((word) & HTT_T2H_CFR_DUMP_TYPE1_STATUS_M) >> \
  17757. HTT_T2H_CFR_DUMP_TYPE1_STATUS_S)
  17758. #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_SET(word, value) \
  17759. do { \
  17760. HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_BW, value); \
  17761. (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S; \
  17762. } while (0)
  17763. #define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_GET(word) \
  17764. (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M) >> \
  17765. HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S)
  17766. #define HTT_T2H_CFR_DUMP_TYPE1_MODE_SET(word, value) \
  17767. do { \
  17768. HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MODE, value); \
  17769. (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MODE_S; \
  17770. } while (0)
  17771. #define HTT_T2H_CFR_DUMP_TYPE1_MODE_GET(word) \
  17772. (((word) & HTT_T2H_CFR_DUMP_TYPE1_MODE_M) >> \
  17773. HTT_T2H_CFR_DUMP_TYPE1_MODE_S)
  17774. #define HTT_T2H_CFR_DUMP_TYPE1_STS_SET(word, value) \
  17775. do { \
  17776. HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STS, value); \
  17777. (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STS_S; \
  17778. } while (0)
  17779. #define HTT_T2H_CFR_DUMP_TYPE1_STS_GET(word) \
  17780. (((word) & HTT_T2H_CFR_DUMP_TYPE1_STS_M) >> \
  17781. HTT_T2H_CFR_DUMP_TYPE1_STS_S)
  17782. #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_SET(word, value) \
  17783. do { \
  17784. HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW, value); \
  17785. (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S; \
  17786. } while (0)
  17787. #define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_GET(word) \
  17788. (((word) & HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M) >> \
  17789. HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S)
  17790. #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_SET(word, value) \
  17791. do { \
  17792. HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE, value); \
  17793. (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S; \
  17794. } while (0)
  17795. #define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_GET(word) \
  17796. (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M) >> \
  17797. HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S)
  17798. #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_SET(word, value) \
  17799. do { \
  17800. HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID, value); \
  17801. (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S; \
  17802. } while (0)
  17803. #define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_GET(word) \
  17804. (((word) & HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M) >> \
  17805. HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S)
  17806. /**
  17807. * @brief target -> host peer (PPDU) stats message
  17808. *
  17809. * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_STATS_IND
  17810. *
  17811. * @details
  17812. * This message is generated by FW when FW is sending stats to host
  17813. * about one or more PPDUs that the FW has transmitted to one or more peers.
  17814. * This message is sent autonomously by the target rather than upon request
  17815. * by the host.
  17816. * The following field definitions describe the format of the HTT target
  17817. * to host peer stats indication message.
  17818. *
  17819. * The HTT_T2H PPDU_STATS_IND message has a header followed by one
  17820. * or more PPDU stats records.
  17821. * Each PPDU stats record uses a htt_tx_ppdu_stats_info TLV.
  17822. * If the details of N PPDUS are sent in one PEER_STATS_IND message,
  17823. * then the message would start with the
  17824. * header, followed by N htt_tx_ppdu_stats_info structures, as depicted
  17825. * below.
  17826. *
  17827. * |31 16|15|14|13 11|10 9|8|7 0|
  17828. * |-------------------------------------------------------------|
  17829. * | reserved |MSG_TYPE |
  17830. * |-------------------------------------------------------------|
  17831. * rec 0 | TLV header |
  17832. * rec 0 |-------------------------------------------------------------|
  17833. * rec 0 | ppdu successful bytes |
  17834. * rec 0 |-------------------------------------------------------------|
  17835. * rec 0 | ppdu retry bytes |
  17836. * rec 0 |-------------------------------------------------------------|
  17837. * rec 0 | ppdu failed bytes |
  17838. * rec 0 |-------------------------------------------------------------|
  17839. * rec 0 | peer id | S|SG| BW | BA |A|rate code|
  17840. * rec 0 |-------------------------------------------------------------|
  17841. * rec 0 | retried MSDUs | successful MSDUs |
  17842. * rec 0 |-------------------------------------------------------------|
  17843. * rec 0 | TX duration | failed MSDUs |
  17844. * rec 0 |-------------------------------------------------------------|
  17845. * ...
  17846. * |-------------------------------------------------------------|
  17847. * rec N | TLV header |
  17848. * rec N |-------------------------------------------------------------|
  17849. * rec N | ppdu successful bytes |
  17850. * rec N |-------------------------------------------------------------|
  17851. * rec N | ppdu retry bytes |
  17852. * rec N |-------------------------------------------------------------|
  17853. * rec N | ppdu failed bytes |
  17854. * rec N |-------------------------------------------------------------|
  17855. * rec N | peer id | S|SG| BW | BA |A|rate code|
  17856. * rec N |-------------------------------------------------------------|
  17857. * rec N | retried MSDUs | successful MSDUs |
  17858. * rec N |-------------------------------------------------------------|
  17859. * rec N | TX duration | failed MSDUs |
  17860. * rec N |-------------------------------------------------------------|
  17861. *
  17862. * where:
  17863. * A = is A-MPDU flag
  17864. * BA = block-ack failure flags
  17865. * BW = bandwidth spec
  17866. * SG = SGI enabled spec
  17867. * S = skipped rate ctrl
  17868. * One htt_tx_ppdu_stats_info instance will have stats for one PPDU
  17869. *
  17870. * Header
  17871. * ------
  17872. * dword0 - b'0:7 - msg_type : 0x23 (HTT_T2H_MSG_TYPE_PEER_STATS_IND)
  17873. * dword0 - b'8:31 - reserved : Reserved for future use
  17874. *
  17875. * payload include below peer_stats information
  17876. * --------------------------------------------
  17877. * @TLV : HTT_PPDU_STATS_INFO_TLV
  17878. * @tx_success_bytes : total successful bytes in the PPDU.
  17879. * @tx_retry_bytes : total retried bytes in the PPDU.
  17880. * @tx_failed_bytes : total failed bytes in the PPDU.
  17881. * @tx_ratecode : rate code used for the PPDU.
  17882. * @is_ampdu : Indicates PPDU is AMPDU or not.
  17883. * @ba_ack_failed : BA/ACK failed for this PPDU
  17884. * b00 -> BA received
  17885. * b01 -> BA failed once
  17886. * b10 -> BA failed twice, when HW retry is enabled.
  17887. * @bw : BW
  17888. * b00 -> 20 MHz
  17889. * b01 -> 40 MHz
  17890. * b10 -> 80 MHz
  17891. * b11 -> 160 MHz (or 80+80)
  17892. * @sg : SGI enabled
  17893. * @s : skipped ratectrl
  17894. * @peer_id : peer id
  17895. * @tx_success_msdus : successful MSDUs
  17896. * @tx_retry_msdus : retried MSDUs
  17897. * @tx_failed_msdus : MSDUs dropped in FW after max retry
  17898. * @tx_duration : Tx duration for the PPDU (microsecond units)
  17899. */
  17900. /**
  17901. * @brief target -> host backpressure event
  17902. *
  17903. * MSG_TYPE => HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND
  17904. *
  17905. * @details
  17906. * HTT_T2H_MSG_TYPE_BKPRESSURE_EVENTID message is sent by the target when
  17907. * continuous backpressure is seen in the LMAC/ UMAC rings software rings.
  17908. * This message will only be sent if the backpressure condition has existed
  17909. * continuously for an initial period (100 ms).
  17910. * Repeat messages with updated information will be sent after each
  17911. * subsequent period (100 ms) as long as the backpressure remains unabated.
  17912. * This message indicates the ring id along with current head and tail index
  17913. * locations (i.e. write and read indices).
  17914. * The backpressure time indicates the time in ms for which continuous
  17915. * backpressure has been observed in the ring.
  17916. *
  17917. * The message format is as follows:
  17918. *
  17919. * |31 24|23 16|15 8|7 0|
  17920. * |----------------+----------------+----------------+----------------|
  17921. * | ring_id | ring_type | pdev_id | msg_type |
  17922. * |-------------------------------------------------------------------|
  17923. * | tail_idx | head_idx |
  17924. * |-------------------------------------------------------------------|
  17925. * | backpressure_time_ms |
  17926. * |-------------------------------------------------------------------|
  17927. *
  17928. * The message is interpreted as follows:
  17929. * dword0 - b'0:7 - msg_type: This will be set to 0x24
  17930. * (HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND)
  17931. * b'8:15 - pdev_id: 0 indicates msg is for UMAC ring.
  17932. * 1, 2, 3 indicates pdev_id 0,1,2 and
  17933. * the msg is for LMAC ring.
  17934. * b'16:23 - ring_type: Refer to enum htt_backpressure_ring_type.
  17935. * b'24:31 - ring_id: Refer enum htt_backpressure_umac_ring_id/
  17936. * htt_backpressure_lmac_ring_id. This represents
  17937. * the ring id for which continuous backpressure
  17938. * is seen
  17939. *
  17940. * dword1 - b'0:15 - head_idx: This indicates the current head index of
  17941. * the ring indicated by the ring_id
  17942. *
  17943. * dword1 - b'16:31 - tail_idx: This indicates the current tail index of
  17944. * the ring indicated by the ring id
  17945. *
  17946. * dword2 - b'0:31 - backpressure_time_ms: Indicates how long continuous
  17947. * backpressure has been seen in the ring
  17948. * indicated by the ring_id.
  17949. * Units = milliseconds
  17950. */
  17951. #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_M 0x0000ff00
  17952. #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_S 8
  17953. #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_M 0x00ff0000
  17954. #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_S 16
  17955. #define HTT_T2H_RX_BKPRESSURE_RINGID_M 0xff000000
  17956. #define HTT_T2H_RX_BKPRESSURE_RINGID_S 24
  17957. #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_M 0x0000ffff
  17958. #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S 0
  17959. #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_M 0xffff0000
  17960. #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S 16
  17961. #define HTT_T2H_RX_BKPRESSURE_TIME_MS_M 0xffffffff
  17962. #define HTT_T2H_RX_BKPRESSURE_TIME_MS_S 0
  17963. #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_SET(word, value) \
  17964. do { \
  17965. HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_PDEV_ID, value); \
  17966. (word) |= (value) << HTT_T2H_RX_BKPRESSURE_PDEV_ID_S; \
  17967. } while (0)
  17968. #define HTT_T2H_RX_BKPRESSURE_PDEV_ID_GET(word) \
  17969. (((word) & HTT_T2H_RX_BKPRESSURE_PDEV_ID_M) >> \
  17970. HTT_T2H_RX_BKPRESSURE_PDEV_ID_S)
  17971. #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_SET(word, value) \
  17972. do { \
  17973. HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_RING_TYPE, value); \
  17974. (word) |= (value) << HTT_T2H_RX_BKPRESSURE_RING_TYPE_S; \
  17975. } while (0)
  17976. #define HTT_T2H_RX_BKPRESSURE_RING_TYPE_GET(word) \
  17977. (((word) & HTT_T2H_RX_BKPRESSURE_RING_TYPE_M) >> \
  17978. HTT_T2H_RX_BKPRESSURE_RING_TYPE_S)
  17979. #define HTT_T2H_RX_BKPRESSURE_RINGID_SET(word, value) \
  17980. do { \
  17981. HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_RINGID, value); \
  17982. (word) |= (value) << HTT_T2H_RX_BKPRESSURE_RINGID_S; \
  17983. } while (0)
  17984. #define HTT_T2H_RX_BKPRESSURE_RINGID_GET(word) \
  17985. (((word) & HTT_T2H_RX_BKPRESSURE_RINGID_M) >> \
  17986. HTT_T2H_RX_BKPRESSURE_RINGID_S)
  17987. #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_SET(word, value) \
  17988. do { \
  17989. HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_HEAD_IDX, value); \
  17990. (word) |= (value) << HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S; \
  17991. } while (0)
  17992. #define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_GET(word) \
  17993. (((word) & HTT_T2H_RX_BKPRESSURE_HEAD_IDX_M) >> \
  17994. HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S)
  17995. #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_SET(word, value) \
  17996. do { \
  17997. HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_TAIL_IDX, value); \
  17998. (word) |= (value) << HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S; \
  17999. } while (0)
  18000. #define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_GET(word) \
  18001. (((word) & HTT_T2H_RX_BKPRESSURE_TAIL_IDX_M) >> \
  18002. HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S)
  18003. #define HTT_T2H_RX_BKPRESSURE_TIME_MS_SET(word, value) \
  18004. do { \
  18005. HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_TIME_MS, value); \
  18006. (word) |= (value) << HTT_T2H_RX_BKPRESSURE_TIME_MS_S; \
  18007. } while (0)
  18008. #define HTT_T2H_RX_BKPRESSURE_TIME_MS_GET(word) \
  18009. (((word) & HTT_T2H_RX_BKPRESSURE_TIME_MS_M) >> \
  18010. HTT_T2H_RX_BKPRESSURE_TIME_MS_S)
  18011. enum htt_backpressure_ring_type {
  18012. HTT_SW_RING_TYPE_UMAC,
  18013. HTT_SW_RING_TYPE_LMAC,
  18014. HTT_SW_RING_TYPE_MAX,
  18015. };
  18016. /* Ring id for which the message is sent to host */
  18017. enum htt_backpressure_umac_ringid {
  18018. HTT_SW_RING_IDX_REO_REO2SW1_RING,
  18019. HTT_SW_RING_IDX_REO_REO2SW2_RING,
  18020. HTT_SW_RING_IDX_REO_REO2SW3_RING,
  18021. HTT_SW_RING_IDX_REO_REO2SW4_RING,
  18022. HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING,
  18023. HTT_SW_RING_IDX_REO_REO2TCL_RING,
  18024. HTT_SW_RING_IDX_REO_REO2FW_RING,
  18025. HTT_SW_RING_IDX_REO_REO_RELEASE_RING,
  18026. HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING,
  18027. HTT_SW_RING_IDX_TCL_TCL2TQM_RING,
  18028. HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING,
  18029. HTT_SW_RING_IDX_WBM_REO_RELEASE_RING,
  18030. HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING,
  18031. HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING,
  18032. HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING,
  18033. HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING,
  18034. HTT_SW_RING_IDX_REO_REO_CMD_RING,
  18035. HTT_SW_RING_IDX_REO_REO_STATUS_RING,
  18036. HTT_SW_UMAC_RING_IDX_MAX,
  18037. };
  18038. enum htt_backpressure_lmac_ringid {
  18039. HTT_SW_RING_IDX_FW2RXDMA_BUF_RING,
  18040. HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING,
  18041. HTT_SW_RING_IDX_FW2RXDMA_LINK_RING,
  18042. HTT_SW_RING_IDX_SW2RXDMA_BUF_RING,
  18043. HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING,
  18044. HTT_SW_RING_IDX_RXDMA2FW_RING,
  18045. HTT_SW_RING_IDX_RXDMA2SW_RING,
  18046. HTT_SW_RING_IDX_RXDMA2RELEASE_RING,
  18047. HTT_SW_RING_IDX_RXDMA2REO_RING,
  18048. HTT_SW_RING_IDX_MONITOR_STATUS_RING,
  18049. HTT_SW_RING_IDX_MONITOR_BUF_RING,
  18050. HTT_SW_RING_IDX_MONITOR_DESC_RING,
  18051. HTT_SW_RING_IDX_MONITOR_DEST_RING,
  18052. HTT_SW_LMAC_RING_IDX_MAX,
  18053. };
  18054. PREPACK struct htt_t2h_msg_bkpressure_event_ind_t {
  18055. A_UINT32 msg_type: 8, /* HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND */
  18056. pdev_id: 8,
  18057. ring_type: 8, /* htt_backpressure_ring_type */
  18058. /*
  18059. * ring_id holds an enum value from either
  18060. * htt_backpressure_umac_ringid or
  18061. * htt_backpressure_lmac_ringid, based on
  18062. * the ring_type setting.
  18063. */
  18064. ring_id: 8;
  18065. A_UINT16 head_idx;
  18066. A_UINT16 tail_idx;
  18067. A_UINT32 backpressure_time_ms; /* Time in milliseconds for which backpressure is seen continuously */
  18068. } POSTPACK;
  18069. /*
  18070. * Defines two 32 bit words that can be used by the target to indicate a per
  18071. * user RU allocation and rate information.
  18072. *
  18073. * This information is currently provided in the "sw_response_reference_ptr"
  18074. * (word 0) and "sw_response_reference_ptr_ext" (word 1) fields of the
  18075. * "rx_ppdu_end_user_stats" TLV.
  18076. *
  18077. * VALID:
  18078. * The consumer of these words must explicitly check the valid bit,
  18079. * and only attempt interpretation of any of the remaining fields if
  18080. * the valid bit is set to 1.
  18081. *
  18082. * VERSION:
  18083. * The consumer of these words must also explicitly check the version bit,
  18084. * and only use the V0 definition if the VERSION field is set to 0.
  18085. *
  18086. * Version 1 is currently undefined, with the exception of the VALID and
  18087. * VERSION fields.
  18088. *
  18089. * Version 0:
  18090. *
  18091. * The fields below are duplicated per BW.
  18092. *
  18093. * The consumer must determine which BW field to use, based on the UL OFDMA
  18094. * PPDU BW indicated by HW.
  18095. *
  18096. * RU_START: RU26 start index for the user.
  18097. * Note that this is always using the RU26 index, regardless
  18098. * of the actual RU assigned to the user
  18099. * (i.e. the second RU52 is RU_START 2, RU_SIZE
  18100. * HTT_UL_OFDMA_V0_RU_SIZE_RU_52)
  18101. *
  18102. * For example, 20MHz (the value in the top row is RU_START)
  18103. *
  18104. * RU Size 0 (26): |0|1|2|3|4|5|6|7|8|
  18105. * RU Size 1 (52): | | | | | |
  18106. * RU Size 2 (106): | | | |
  18107. * RU Size 3 (242): | |
  18108. *
  18109. * RU_SIZE: Indicates the RU size, as defined by enum
  18110. * htt_ul_ofdma_user_info_ru_size.
  18111. *
  18112. * LDPC: LDPC enabled (if 0, BCC is used)
  18113. *
  18114. * DCM: DCM enabled
  18115. *
  18116. * |31 | 30|29 23|22 19|18 16|15 9| 8 | 7 |6 3|2 0|
  18117. * |---------------------------------+--------------------------------|
  18118. * |Ver|Valid| FW internal |
  18119. * |---------------------------------+--------------------------------|
  18120. * | reserved |Trig Type|RU SIZE| RU START |DCM|LDPC|MCS |NSS|
  18121. * |---------------------------------+--------------------------------|
  18122. */
  18123. enum htt_ul_ofdma_user_info_ru_size {
  18124. HTT_UL_OFDMA_V0_RU_SIZE_RU_26,
  18125. HTT_UL_OFDMA_V0_RU_SIZE_RU_52,
  18126. HTT_UL_OFDMA_V0_RU_SIZE_RU_106,
  18127. HTT_UL_OFDMA_V0_RU_SIZE_RU_242,
  18128. HTT_UL_OFDMA_V0_RU_SIZE_RU_484,
  18129. HTT_UL_OFDMA_V0_RU_SIZE_RU_996,
  18130. HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2
  18131. };
  18132. /* htt_up_ofdma_user_info_v0 provides an abstract view of the info */
  18133. struct htt_ul_ofdma_user_info_v0 {
  18134. A_UINT32 word0;
  18135. A_UINT32 word1;
  18136. };
  18137. #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 \
  18138. A_UINT32 w0_fw_rsvd:29; \
  18139. A_UINT32 w0_manual_ulofdma_trig:1; \
  18140. A_UINT32 w0_valid:1; \
  18141. A_UINT32 w0_version:1;
  18142. struct htt_ul_ofdma_user_info_v0_bitmap_w0 {
  18143. HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0
  18144. };
  18145. #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1 \
  18146. A_UINT32 w1_nss:3; \
  18147. A_UINT32 w1_mcs:4; \
  18148. A_UINT32 w1_ldpc:1; \
  18149. A_UINT32 w1_dcm:1; \
  18150. A_UINT32 w1_ru_start:7; \
  18151. A_UINT32 w1_ru_size:3; \
  18152. A_UINT32 w1_trig_type:4; \
  18153. A_UINT32 w1_unused:9;
  18154. struct htt_ul_ofdma_user_info_v0_bitmap_w1 {
  18155. HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1
  18156. };
  18157. #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 \
  18158. A_UINT32 w0_fw_rsvd:27; \
  18159. A_UINT32 w0_sub_version:3; /* set to a value of "0" on WKK/Beryllium targets (future expansion) */ \
  18160. A_UINT32 w0_valid:1; /* field aligns with V0 definition */ \
  18161. A_UINT32 w0_version:1; /* set to a value of "1" to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */
  18162. struct htt_ul_ofdma_user_info_v1_bitmap_w0 {
  18163. HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0
  18164. };
  18165. #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 \
  18166. A_UINT32 w1_unused_0_to_18:19; /* Guaranteed to be set to 0, can be used for future expansion without bumping version again. */ \
  18167. A_UINT32 w1_trig_type:4; \
  18168. A_UINT32 w1_unused_23_to_31:9; /* Guaranteed to be set to 0, can be used for future expansion without bumping version again. */
  18169. struct htt_ul_ofdma_user_info_v1_bitmap_w1 {
  18170. HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1
  18171. };
  18172. /* htt_ul_ofdma_user_info_v0_bitmap shows what bitfields are within the info */
  18173. PREPACK struct htt_ul_ofdma_user_info_v0_bitmap {
  18174. union {
  18175. A_UINT32 word0;
  18176. struct {
  18177. HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0
  18178. };
  18179. };
  18180. union {
  18181. A_UINT32 word1;
  18182. struct {
  18183. HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1
  18184. };
  18185. };
  18186. } POSTPACK;
  18187. /*
  18188. * htt_ul_ofdma_user_info_v1_bitmap bits are aligned to
  18189. * htt_ul_ofdma_user_info_v0_bitmap, based on the w0_version
  18190. * this should be picked.
  18191. */
  18192. PREPACK struct htt_ul_ofdma_user_info_v1_bitmap {
  18193. union {
  18194. A_UINT32 word0;
  18195. struct {
  18196. HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0
  18197. };
  18198. };
  18199. union {
  18200. A_UINT32 word1;
  18201. struct {
  18202. HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1
  18203. };
  18204. };
  18205. } POSTPACK;
  18206. enum HTT_UL_OFDMA_TRIG_TYPE {
  18207. HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BASIC = 0,
  18208. HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BFRP,
  18209. HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_BAR,
  18210. HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_RTS_CTS,
  18211. HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BSR,
  18212. };
  18213. #define HTT_UL_OFDMA_USER_INFO_V0_SZ (sizeof(struct htt_ul_ofdma_user_info_v0))
  18214. #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff
  18215. #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0
  18216. #define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_M 0x20000000
  18217. #define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_S 29
  18218. #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000
  18219. #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30
  18220. #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M 0x80000000
  18221. #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S 31
  18222. #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M 0x00000007
  18223. #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S 0
  18224. #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M 0x00000078
  18225. #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S 3
  18226. #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M 0x00000080
  18227. #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S 7
  18228. #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M 0x00000100
  18229. #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S 8
  18230. #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M 0x0000fe00
  18231. #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S 9
  18232. #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M 0x00070000
  18233. #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S 16
  18234. #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M 0x00780000
  18235. #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S 19
  18236. #define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_M 0xff800000
  18237. #define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_S 23
  18238. /*--- word 0 ---*/
  18239. #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_GET(word) \
  18240. (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)
  18241. #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_SET(word, _val) \
  18242. do { \
  18243. HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL, _val); \
  18244. ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)); \
  18245. } while (0)
  18246. #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_GET(word) \
  18247. (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)
  18248. #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_SET(word, _val) \
  18249. do { \
  18250. HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VALID, _val); \
  18251. ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)); \
  18252. } while (0)
  18253. #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_GET(word) \
  18254. (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)
  18255. #define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_SET(word, _val) \
  18256. do { \
  18257. HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VER, _val); \
  18258. ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)); \
  18259. } while (0)
  18260. /*--- word 1 ---*/
  18261. #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_GET(word) \
  18262. (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)
  18263. #define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_SET(word, _val) \
  18264. do { \
  18265. HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_NSS, _val); \
  18266. ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)); \
  18267. } while (0)
  18268. #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_GET(word) \
  18269. (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)
  18270. #define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_SET(word, _val) \
  18271. do { \
  18272. HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_MCS, _val); \
  18273. ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)); \
  18274. } while (0)
  18275. #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_GET(word) \
  18276. (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)
  18277. #define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_SET(word, _val) \
  18278. do { \
  18279. HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC, _val); \
  18280. ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)); \
  18281. } while (0)
  18282. #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_GET(word) \
  18283. (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)
  18284. #define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_SET(word, _val) \
  18285. do { \
  18286. HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_DCM, _val); \
  18287. ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)); \
  18288. } while (0)
  18289. #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_GET(word) \
  18290. (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)
  18291. #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_SET(word, _val) \
  18292. do { \
  18293. HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START, _val); \
  18294. ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)); \
  18295. } while (0)
  18296. #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_GET(word) \
  18297. (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)
  18298. #define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_SET(word, _val) \
  18299. do { \
  18300. HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE, _val); \
  18301. ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)); \
  18302. } while (0)
  18303. #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_GET(word) \
  18304. (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S)
  18305. #define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_SET(word, _val) \
  18306. do { \
  18307. HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP, _val); \
  18308. ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP_S)); \
  18309. } while (0)
  18310. /**
  18311. * @brief target -> host channel calibration data message
  18312. *
  18313. * MSG_TYPE => HTT_T2H_MSG_TYPE_CHAN_CALDATA
  18314. *
  18315. * @brief host -> target channel calibration data message
  18316. *
  18317. * MSG_TYPE => HTT_H2T_MSG_TYPE_CHAN_CALDATA
  18318. *
  18319. * @details
  18320. * The following field definitions describe the format of the channel
  18321. * calibration data message sent from the target to the host when
  18322. * MSG_TYPE is HTT_T2H_MSG_TYPE_CHAN_CALDATA, and sent from the host
  18323. * to the target when MSG_TYPE is HTT_H2T_MSG_TYPE_CHAN_CALDATA.
  18324. * The message is defined as htt_chan_caldata_msg followed by a variable
  18325. * number of 32-bit character values.
  18326. *
  18327. * |31 21|20|19 16|15 13| 12|11 8|7 0|
  18328. * |------------------------------------------------------------------|
  18329. * | rsv | A| frag | rsv |ck_v| sub_type| msg type |
  18330. * |------------------------------------------------------------------|
  18331. * | payload size | mhz |
  18332. * |------------------------------------------------------------------|
  18333. * | center frequency 2 | center frequency 1 |
  18334. * |------------------------------------------------------------------|
  18335. * | check sum |
  18336. * |------------------------------------------------------------------|
  18337. * | payload |
  18338. * |------------------------------------------------------------------|
  18339. * message info field:
  18340. * - MSG_TYPE
  18341. * Bits 7:0
  18342. * Purpose: identifies this as a channel calibration data message
  18343. * Value: 0x25 (HTT_T2H_MSG_TYPE_CHAN_CALDATA)
  18344. * 0x14 (HTT_H2T_MSG_TYPE_CHAN_CALDATA)
  18345. * - SUB_TYPE
  18346. * Bits 11:8
  18347. * Purpose: T2H: indicates whether target is providing chan cal data
  18348. * to the host to store, or requesting that the host
  18349. * download previously-stored data.
  18350. * H2T: indicates whether the host is providing the requested
  18351. * channel cal data, or if it is rejecting the data
  18352. * request because it does not have the requested data.
  18353. * Value: see HTT_T2H_MSG_CHAN_CALDATA_xxx defs
  18354. * - CHKSUM_VALID
  18355. * Bit 12
  18356. * Purpose: indicates if the checksum field is valid
  18357. * value:
  18358. * - FRAG
  18359. * Bit 19:16
  18360. * Purpose: indicates the fragment index for message
  18361. * value: 0 for first fragment, 1 for second fragment, ...
  18362. * - APPEND
  18363. * Bit 20
  18364. * Purpose: indicates if this is the last fragment
  18365. * value: 0 = final fragment, 1 = more fragments will be appended
  18366. *
  18367. * channel and payload size field
  18368. * - MHZ
  18369. * Bits 15:0
  18370. * Purpose: indicates the channel primary frequency
  18371. * Value:
  18372. * - PAYLOAD_SIZE
  18373. * Bits 31:16
  18374. * Purpose: indicates the bytes of calibration data in payload
  18375. * Value:
  18376. *
  18377. * center frequency field
  18378. * - CENTER FREQUENCY 1
  18379. * Bits 15:0
  18380. * Purpose: indicates the channel center frequency
  18381. * Value: channel center frequency, in MHz units
  18382. * - CENTER FREQUENCY 2
  18383. * Bits 31:16
  18384. * Purpose: indicates the secondary channel center frequency,
  18385. * only for 11acvht 80plus80 mode
  18386. * Value: secondary channel center frequency, in MHz units, if applicable
  18387. *
  18388. * checksum field
  18389. * - CHECK_SUM
  18390. * Bits 31:0
  18391. * Purpose: check the payload data, it is just for this fragment.
  18392. * This is intended for the target to check that the channel
  18393. * calibration data returned by the host is the unmodified data
  18394. * that was previously provided to the host by the target.
  18395. * value: checksum of fragment payload
  18396. */
  18397. PREPACK struct htt_chan_caldata_msg {
  18398. /* DWORD 0: message info */
  18399. A_UINT32
  18400. msg_type: 8,
  18401. sub_type: 4 ,
  18402. chksum_valid: 1, /** 1:valid, 0:invalid */
  18403. reserved1: 3,
  18404. frag_idx: 4, /** fragment index for calibration data */
  18405. appending: 1, /** 0: no fragment appending,
  18406. * 1: extra fragment appending */
  18407. reserved2: 11;
  18408. /* DWORD 1: channel and payload size */
  18409. A_UINT32
  18410. mhz: 16, /** primary 20 MHz channel frequency in mhz */
  18411. payload_size: 16; /** unit: bytes */
  18412. /* DWORD 2: center frequency */
  18413. A_UINT32
  18414. band_center_freq1: 16, /** Center frequency 1 in MHz */
  18415. band_center_freq2: 16; /** Center frequency 2 in MHz,
  18416. * valid only for 11acvht 80plus80 mode */
  18417. /* DWORD 3: check sum */
  18418. A_UINT32 chksum;
  18419. /* variable length for calibration data */
  18420. A_UINT32 payload[1/* or more */];
  18421. } POSTPACK;
  18422. /* T2H SUBTYPE */
  18423. #define HTT_T2H_MSG_CHAN_CALDATA_REQ 0
  18424. #define HTT_T2H_MSG_CHAN_CALDATA_UPLOAD 1
  18425. /* H2T SUBTYPE */
  18426. #define HTT_H2T_MSG_CHAN_CALDATA_REJ 0
  18427. #define HTT_H2T_MSG_CHAN_CALDATA_DOWNLOAD 1
  18428. #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_S 8
  18429. #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_M 0x00000f00
  18430. #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_GET(_var) \
  18431. (((_var) & HTT_CHAN_CALDATA_MSG_SUB_TYPE_M) >> HTT_CHAN_CALDATA_MSG_SUB_TYPE_S)
  18432. #define HTT_CHAN_CALDATA_MSG_SUB_TYPE_SET(_var, _val) \
  18433. do { \
  18434. HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_SUB_TYPE, _val); \
  18435. ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_SUB_TYPE_S)); \
  18436. } while (0)
  18437. #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_S 12
  18438. #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_M 0x00001000
  18439. #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_GET(_var) \
  18440. (((_var) & HTT_CHAN_CALDATA_MSG_CHKSUM_V_M) >> HTT_CHAN_CALDATA_MSG_CHKSUM_V_S)
  18441. #define HTT_CHAN_CALDATA_MSG_CHKSUM_V_SET(_var, _val) \
  18442. do { \
  18443. HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_CHKSUM_V, _val); \
  18444. ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_CHKSUM_V_S)); \
  18445. } while (0)
  18446. #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_S 16
  18447. #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_M 0x000f0000
  18448. #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_GET(_var) \
  18449. (((_var) & HTT_CHAN_CALDATA_MSG_FRAG_IDX_M) >> HTT_CHAN_CALDATA_MSG_FRAG_IDX_S)
  18450. #define HTT_CHAN_CALDATA_MSG_FRAG_IDX_SET(_var, _val) \
  18451. do { \
  18452. HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FRAG_IDX, _val); \
  18453. ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FRAG_IDX_S)); \
  18454. } while (0)
  18455. #define HTT_CHAN_CALDATA_MSG_APPENDING_S 20
  18456. #define HTT_CHAN_CALDATA_MSG_APPENDING_M 0x00100000
  18457. #define HTT_CHAN_CALDATA_MSG_APPENDING_GET(_var) \
  18458. (((_var) & HTT_CHAN_CALDATA_MSG_APPENDING_M) >> HTT_CHAN_CALDATA_MSG_APPENDING_S)
  18459. #define HTT_CHAN_CALDATA_MSG_APPENDING_SET(_var, _val) \
  18460. do { \
  18461. HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_APPENDING, _val); \
  18462. ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_APPENDING_S)); \
  18463. } while (0)
  18464. #define HTT_CHAN_CALDATA_MSG_MHZ_S 0
  18465. #define HTT_CHAN_CALDATA_MSG_MHZ_M 0x0000ffff
  18466. #define HTT_CHAN_CALDATA_MSG_MHZ_GET(_var) \
  18467. (((_var) & HTT_CHAN_CALDATA_MSG_MHZ_M) >> HTT_CHAN_CALDATA_MSG_MHZ_S)
  18468. #define HTT_CHAN_CALDATA_MSG_MHZ_SET(_var, _val) \
  18469. do { \
  18470. HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_MHZ, _val); \
  18471. ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_MHZ_S)); \
  18472. } while (0)
  18473. #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_S 16
  18474. #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_M 0xffff0000
  18475. #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_GET(_var) \
  18476. (((_var) & HTT_CHAN_CALDATA_MSG_PLD_SIZE_M) >> HTT_CHAN_CALDATA_MSG_PLD_SIZE_S)
  18477. #define HTT_CHAN_CALDATA_MSG_PLD_SIZE_SET(_var, _val) \
  18478. do { \
  18479. HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_PLD_SIZE, _val); \
  18480. ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_PLD_SIZE_S)); \
  18481. } while (0)
  18482. #define HTT_CHAN_CALDATA_MSG_FREQ1_S 0
  18483. #define HTT_CHAN_CALDATA_MSG_FREQ1_M 0x0000ffff
  18484. #define HTT_CHAN_CALDATA_MSG_FREQ1_GET(_var) \
  18485. (((_var) & HTT_CHAN_CALDATA_MSG_FREQ1_M) >> HTT_CHAN_CALDATA_MSG_FREQ1_S)
  18486. #define HTT_CHAN_CALDATA_MSG_FREQ1_SET(_var, _val) \
  18487. do { \
  18488. HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FREQ1, _val); \
  18489. ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FREQ1_S)); \
  18490. } while (0)
  18491. #define HTT_CHAN_CALDATA_MSG_FREQ2_S 16
  18492. #define HTT_CHAN_CALDATA_MSG_FREQ2_M 0xffff0000
  18493. #define HTT_CHAN_CALDATA_MSG_FREQ2_GET(_var) \
  18494. (((_var) & HTT_CHAN_CALDATA_MSG_FREQ2_M) >> HTT_CHAN_CALDATA_MSG_FREQ2_S)
  18495. #define HTT_CHAN_CALDATA_MSG_FREQ2_SET(_var, _val) \
  18496. do { \
  18497. HTT_CHECK_SET_VAL(HTT_CHAN_CALDATA_MSG_FREQ2, _val); \
  18498. ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FREQ2_S)); \
  18499. } while (0)
  18500. /**
  18501. * @brief target -> host FSE CMEM based send
  18502. *
  18503. * MSG_TYPE => HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND
  18504. *
  18505. * @details
  18506. * HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND message is sent by the target when
  18507. * FSE placement in CMEM is enabled.
  18508. *
  18509. * This message sends the non-secure CMEM base address.
  18510. * It will be sent to host in response to message
  18511. * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG.
  18512. * The message would appear as follows:
  18513. *
  18514. * |31 24|23 16|15 8|7 0|
  18515. * |----------------+----------------+----------------+----------------|
  18516. * | reserved | num_entries | msg_type |
  18517. * |----------------+----------------+----------------+----------------|
  18518. * | base_address_lo |
  18519. * |----------------+----------------+----------------+----------------|
  18520. * | base_address_hi |
  18521. * |-------------------------------------------------------------------|
  18522. *
  18523. * The message is interpreted as follows:
  18524. * dword0 - b'0:7 - msg_type: This will be set to 0x27
  18525. * (HTT_T2H_MSG_TYPE_FSE_CMEM_BASE_SEND)
  18526. * b'8:15 - number_entries: Indicated the number of entries
  18527. * programmed.
  18528. * b'16:31 - reserved.
  18529. * dword1 - b'0:31 - base_address_lo: Indicate lower 32 bits of
  18530. * CMEM base address
  18531. * dword2 - b'0:31 - base_address_hi: Indicate upper 32 bits of
  18532. * CMEM base address
  18533. */
  18534. PREPACK struct htt_cmem_base_send_t {
  18535. A_UINT32 msg_type: 8,
  18536. num_entries: 8,
  18537. reserved: 16;
  18538. A_UINT32 base_address_lo;
  18539. A_UINT32 base_address_hi;
  18540. } POSTPACK;
  18541. #define HTT_CMEM_BASE_SEND_SIZE (sizeof(struct htt_cmem_base_send_t))
  18542. #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_M 0x0000FF00
  18543. #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_S 8
  18544. #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_GET(_var) \
  18545. (((_var) & HTT_CMEM_BASE_SEND_NUM_ENTRIES_M) >> \
  18546. HTT_CMEM_BASE_SEND_NUM_ENTRIES_S)
  18547. #define HTT_CMEM_BASE_SEND_NUM_ENTRIES_SET(_var, _val) \
  18548. do { \
  18549. HTT_CHECK_SET_VAL(HTT_CMEM_BASE_SEND_NUM_ENTRIES, _val); \
  18550. ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_PDEV_ID_S)); \
  18551. } while (0)
  18552. /**
  18553. * @brief - HTT PPDU ID format
  18554. *
  18555. * @details
  18556. * The following field definitions describe the format of the PPDU ID.
  18557. * The PPDU ID is truncated to 24 bits for TLVs from TQM.
  18558. *
  18559. * |31 30|29 24| 23|22 21|20 19|18 17|16 12|11 0|
  18560. * +--------------------------------------------------------------------------
  18561. * |rsvd |seq_cmd_type|tqm_cmd|rsvd |seq_idx|mac_id| hwq_ id | sch id |
  18562. * +--------------------------------------------------------------------------
  18563. *
  18564. * sch id :Schedule command id
  18565. * Bits [11 : 0] : monotonically increasing counter to track the
  18566. * PPDU posted to a specific transmit queue.
  18567. *
  18568. * hwq_id: Hardware Queue ID.
  18569. * Bits [16 : 12] : Indicates the queue id in the hardware transmit queue.
  18570. *
  18571. * mac_id: MAC ID
  18572. * Bits [18 : 17] : LMAC ID obtained from the whal_mac_struct
  18573. *
  18574. * seq_idx: Sequence index.
  18575. * Bits [21 : 19] : Sequence index indicates all the PPDU belonging to
  18576. * a particular TXOP.
  18577. *
  18578. * tqm_cmd: HWSCH/TQM flag.
  18579. * Bit [23] : Always set to 0.
  18580. *
  18581. * seq_cmd_type: Sequence command type.
  18582. * Bit [29 : 24] : Indicates the frame type for the current sequence.
  18583. * Refer to enum HTT_STATS_FTYPE for values.
  18584. */
  18585. PREPACK struct htt_ppdu_id {
  18586. A_UINT32
  18587. sch_id: 12,
  18588. hwq_id: 5,
  18589. mac_id: 2,
  18590. seq_idx: 2,
  18591. reserved1: 2,
  18592. tqm_cmd: 1,
  18593. seq_cmd_type: 6,
  18594. reserved2: 2;
  18595. } POSTPACK;
  18596. #define HTT_PPDU_ID_SCH_ID_S 0
  18597. #define HTT_PPDU_ID_SCH_ID_M 0x00000fff
  18598. #define HTT_PPDU_ID_SCH_ID_GET(_var) \
  18599. (((_var) & HTT_PPDU_ID_SCH_ID_M) >> HTT_PPDU_ID_SCH_ID_S)
  18600. #define HTT_PPDU_ID_SCH_ID_SET(_var, _val) \
  18601. do { \
  18602. HTT_CHECK_SET_VAL(HTT_PPDU_ID_SCH_ID, _val); \
  18603. ((_var) |= ((_val) << HTT_PPDU_ID_SCH_ID_S)); \
  18604. } while (0)
  18605. #define HTT_PPDU_ID_HWQ_ID_S 12
  18606. #define HTT_PPDU_ID_HWQ_ID_M 0x0001f000
  18607. #define HTT_PPDU_ID_HWQ_ID_GET(_var) \
  18608. (((_var) & HTT_PPDU_ID_HWQ_ID_M) >> HTT_PPDU_ID_HWQ_ID_S)
  18609. #define HTT_PPDU_ID_HWQ_ID_SET(_var, _val) \
  18610. do { \
  18611. HTT_CHECK_SET_VAL(HTT_PPDU_ID_HWQ_ID, _val); \
  18612. ((_var) |= ((_val) << HTT_PPDU_ID_HWQ_ID_S)); \
  18613. } while (0)
  18614. #define HTT_PPDU_ID_MAC_ID_S 17
  18615. #define HTT_PPDU_ID_MAC_ID_M 0x00060000
  18616. #define HTT_PPDU_ID_MAC_ID_GET(_var) \
  18617. (((_var) & HTT_PPDU_ID_MAC_ID_M) >> HTT_PPDU_ID_MAC_ID_S)
  18618. #define HTT_PPDU_ID_MAC_ID_SET(_var, _val) \
  18619. do { \
  18620. HTT_CHECK_SET_VAL(HTT_PPDU_ID_MAC_ID, _val); \
  18621. ((_var) |= ((_val) << HTT_PPDU_ID_MAC_ID_S)); \
  18622. } while (0)
  18623. #define HTT_PPDU_ID_SEQ_IDX_S 19
  18624. #define HTT_PPDU_ID_SEQ_IDX_M 0x00180000
  18625. #define HTT_PPDU_ID_SEQ_IDX_GET(_var) \
  18626. (((_var) & HTT_PPDU_ID_SEQ_IDX_M) >> HTT_PPDU_ID_SEQ_IDX_S)
  18627. #define HTT_PPDU_ID_SEQ_IDX_SET(_var, _val) \
  18628. do { \
  18629. HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_IDX, _val); \
  18630. ((_var) |= ((_val) << HTT_PPDU_ID_SEQ_IDX_S)); \
  18631. } while (0)
  18632. #define HTT_PPDU_ID_TQM_CMD_S 23
  18633. #define HTT_PPDU_ID_TQM_CMD_M 0x00800000
  18634. #define HTT_PPDU_ID_TQM_CMD_GET(_var) \
  18635. (((_var) & HTT_PPDU_ID_TQM_CMD_M) >> HTT_PPDU_ID_TQM_CMD_S)
  18636. #define HTT_PPDU_ID_TQM_CMD_SET(_var, _val) \
  18637. do { \
  18638. HTT_CHECK_SET_VAL(HTT_PPDU_ID_TQM_CMD, _val); \
  18639. ((_var) |= ((_val) << HTT_PPDU_ID_TQM_CMD_S)); \
  18640. } while (0)
  18641. #define HTT_PPDU_ID_SEQ_CMD_TYPE_S 24
  18642. #define HTT_PPDU_ID_SEQ_CMD_TYPE_M 0x3f000000
  18643. #define HTT_PPDU_ID_SEQ_CMD_TYPE_GET(_var) \
  18644. (((_var) & HTT_PPDU_ID_SEQ_CMD_TYPE_M) >> HTT_PPDU_ID_SEQ_CMD_TYPE_S)
  18645. #define HTT_PPDU_ID_SEQ_CMD_TYPE_SET(_var, _val) \
  18646. do { \
  18647. HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_CMD_TYPE, _val); \
  18648. ((_var) |= ((_val) << HTT_PPDU_ID_SEQ_CMD_TYPE_S)); \
  18649. } while (0)
  18650. /**
  18651. * @brief target -> RX PEER METADATA V0 format
  18652. * Host will know the peer metadata version from the wmi_service_ready_ext2
  18653. * message from target, and will confirm to the target which peer metadata
  18654. * version to use in the wmi_init message.
  18655. *
  18656. * The following diagram shows the format of the RX PEER METADATA.
  18657. *
  18658. * |31 24|23 16|15 8|7 0|
  18659. * |-----------------------------------------------------------------------|
  18660. * | Reserved | VDEV ID | PEER ID |
  18661. * |-----------------------------------------------------------------------|
  18662. */
  18663. PREPACK struct htt_rx_peer_metadata_v0 {
  18664. A_UINT32
  18665. peer_id: 16,
  18666. vdev_id: 8,
  18667. reserved1: 8;
  18668. } POSTPACK;
  18669. #define HTT_RX_PEER_META_DATA_V0_PEER_ID_S 0
  18670. #define HTT_RX_PEER_META_DATA_V0_PEER_ID_M 0x0000ffff
  18671. #define HTT_RX_PEER_META_DATA_V0_PEER_ID_GET(_var) \
  18672. (((_var) & HTT_RX_PEER_META_DATA_V0_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V0_PEER_ID_S)
  18673. #define HTT_RX_PEER_META_DATA_V0_PEER_ID_SET(_var, _val) \
  18674. do { \
  18675. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V0_PEER_ID, _val); \
  18676. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V0_PEER_ID_S)); \
  18677. } while (0)
  18678. #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_S 16
  18679. #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_M 0x00ff0000
  18680. #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_GET(_var) \
  18681. (((_var) & HTT_RX_PEER_META_DATA_V0_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V0_VDEV_ID_S)
  18682. #define HTT_RX_PEER_META_DATA_V0_VDEV_ID_SET(_var, _val) \
  18683. do { \
  18684. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V0_VDEV_ID, _val); \
  18685. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V0_VDEV_ID_S)); \
  18686. } while (0)
  18687. /**
  18688. * @brief target -> RX PEER METADATA V1 format
  18689. * Host will know the peer metadata version from the wmi_service_ready_ext2
  18690. * message from target, and will confirm to the target which peer metadata
  18691. * version to use in the wmi_init message.
  18692. *
  18693. * The following diagram shows the format of the RX PEER METADATA V1 format.
  18694. *
  18695. * |31 29|28 26|25 24|23 16|15 14| 13 |12 0|
  18696. * |---------------------------------------------------------------------------|
  18697. * |Rsvd2|CHIP ID|LMAC ID|VDEV ID|logical_link_id|ML PEER|SW PEER ID/ML PEER ID|
  18698. * |---------------------------------------------------------------------------|
  18699. */
  18700. PREPACK struct htt_rx_peer_metadata_v1 {
  18701. A_UINT32
  18702. peer_id: 13,
  18703. ml_peer_valid: 1,
  18704. logical_link_id: 2,
  18705. vdev_id: 8,
  18706. lmac_id: 2,
  18707. chip_id: 3,
  18708. reserved2: 3;
  18709. } POSTPACK;
  18710. #define HTT_RX_PEER_META_DATA_V1_PEER_ID_S 0
  18711. #define HTT_RX_PEER_META_DATA_V1_PEER_ID_M 0x00001fff
  18712. #define HTT_RX_PEER_META_DATA_V1_PEER_ID_GET(_var) \
  18713. (((_var) & HTT_RX_PEER_META_DATA_V1_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1_PEER_ID_S)
  18714. #define HTT_RX_PEER_META_DATA_V1_PEER_ID_SET(_var, _val) \
  18715. do { \
  18716. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_PEER_ID, _val); \
  18717. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_PEER_ID_S)); \
  18718. } while (0)
  18719. #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S 13
  18720. #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_M 0x00002000
  18721. #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_GET(_var) \
  18722. (((_var) & HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S)
  18723. #define HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_SET(_var, _val) \
  18724. do { \
  18725. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID, _val); \
  18726. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S)); \
  18727. } while (0)
  18728. #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_S 16
  18729. #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_M 0x00ff0000
  18730. #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_GET(_var) \
  18731. (((_var) & HTT_RX_PEER_META_DATA_V1_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1_VDEV_ID_S)
  18732. #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S 14
  18733. #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M 0x0000c000
  18734. #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_GET(_var) \
  18735. (((_var) & HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S)
  18736. #define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_SET(_var, _val) \
  18737. do { \
  18738. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID, _val); \
  18739. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S)); \
  18740. } while (0)
  18741. #define HTT_RX_PEER_META_DATA_V1_VDEV_ID_SET(_var, _val) \
  18742. do { \
  18743. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_VDEV_ID, _val); \
  18744. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_VDEV_ID_S)); \
  18745. } while (0)
  18746. #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_S 24
  18747. #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_M 0x03000000
  18748. #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_GET(_var) \
  18749. (((_var) & HTT_RX_PEER_META_DATA_V1_LMAC_ID_M) >> HTT_RX_PEER_META_DATA_V1_LMAC_ID_S)
  18750. #define HTT_RX_PEER_META_DATA_V1_LMAC_ID_SET(_var, _val) \
  18751. do { \
  18752. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_LMAC_ID, _val); \
  18753. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_LMAC_ID_S)); \
  18754. } while (0)
  18755. #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_S 26
  18756. #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_M 0x1c000000
  18757. #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_GET(_var) \
  18758. (((_var) & HTT_RX_PEER_META_DATA_V1_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1_CHIP_ID_S)
  18759. #define HTT_RX_PEER_META_DATA_V1_CHIP_ID_SET(_var, _val) \
  18760. do { \
  18761. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_CHIP_ID, _val); \
  18762. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_CHIP_ID_S)); \
  18763. } while (0)
  18764. /**
  18765. * @brief target -> RX PEER METADATA V1A format
  18766. * Host will know the peer metadata version from the wmi_service_ready_ext2
  18767. * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service,
  18768. * and will confirm to the target which peer metadata version to use in the
  18769. * wmi_init message.
  18770. *
  18771. * The following diagram shows the format of the RX PEER METADATA V1A format.
  18772. *
  18773. * |31 29|28 26|25 22|21 14| 13 |12 0|
  18774. * |-------------------------------------------------------------------|
  18775. * |Rsvd2|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID|
  18776. * |-------------------------------------------------------------------|
  18777. */
  18778. PREPACK struct htt_rx_peer_metadata_v1a {
  18779. A_UINT32
  18780. peer_id: 13,
  18781. ml_peer_valid: 1,
  18782. vdev_id: 8,
  18783. logical_link_id: 4,
  18784. chip_id: 3,
  18785. qdata_refill: 1,
  18786. reserved2: 2;
  18787. } POSTPACK;
  18788. #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S 0
  18789. #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_M 0x00001fff
  18790. #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_GET(_var) \
  18791. (((_var) & HTT_RX_PEER_META_DATA_V1A_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1A_PEER_ID_S)
  18792. #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_SET(_var, _val) \
  18793. do { \
  18794. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_PEER_ID, _val); \
  18795. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PEER_ID_S)); \
  18796. } while (0)
  18797. #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S 13
  18798. #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M 0x00002000
  18799. #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_GET(_var) \
  18800. (((_var) & HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S)
  18801. #define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_SET(_var, _val) \
  18802. do { \
  18803. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID, _val); \
  18804. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S)); \
  18805. } while (0)
  18806. #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S 14
  18807. #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M 0x003fc000
  18808. #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_GET(_var) \
  18809. (((_var) & HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S)
  18810. #define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_SET(_var, _val) \
  18811. do { \
  18812. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_VDEV_ID, _val); \
  18813. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S)); \
  18814. } while (0)
  18815. #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S 22
  18816. #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M 0x03C00000
  18817. #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_GET(_var) \
  18818. (((_var) & HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S)
  18819. #define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_SET(_var, _val) \
  18820. do { \
  18821. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID, _val); \
  18822. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S)); \
  18823. } while (0)
  18824. #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S 26
  18825. #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M 0x1c000000
  18826. #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_GET(_var) \
  18827. (((_var) & HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S)
  18828. #define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_SET(_var, _val) \
  18829. do { \
  18830. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_CHIP_ID, _val); \
  18831. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S)); \
  18832. } while (0)
  18833. #define HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_S 29
  18834. #define HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_M 0x20000000
  18835. #define HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_GET(_var) \
  18836. (((_var) & HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_M) >> HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_S)
  18837. #define HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_SET(_var, _val) \
  18838. do { \
  18839. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL, _val); \
  18840. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_S)); \
  18841. } while (0)
  18842. /**
  18843. * @brief target -> RX PEER METADATA V1B format
  18844. * Host will know the peer metadata version from the wmi_service_ready_ext2
  18845. * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service,
  18846. * and will confirm to the target which peer metadata version to use in the
  18847. * wmi_init message.
  18848. *
  18849. * The following diagram shows the format of the RX PEER METADATA V1B format.
  18850. *
  18851. * |31 29|28 26|25 22|21 14| 13 |12 0|
  18852. * |--------------------------------------------------------------|
  18853. * |Rsvd2|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID|
  18854. * |--------------------------------------------------------------|
  18855. */
  18856. PREPACK struct htt_rx_peer_metadata_v1b {
  18857. A_UINT32
  18858. peer_id: 13,
  18859. ml_peer_valid: 1,
  18860. vdev_id: 8,
  18861. hw_link_id: 4,
  18862. chip_id: 3,
  18863. reserved2: 3;
  18864. } POSTPACK;
  18865. #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_S 0
  18866. #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_M 0x00001fff
  18867. #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_GET(_var) \
  18868. (((_var) & HTT_RX_PEER_META_DATA_V1B_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1B_PEER_ID_S)
  18869. #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_SET(_var, _val) \
  18870. do { \
  18871. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_PEER_ID, _val); \
  18872. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_PEER_ID_S)); \
  18873. } while (0)
  18874. #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S 13
  18875. #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M 0x00002000
  18876. #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_GET(_var) \
  18877. (((_var) & HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S)
  18878. #define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_SET(_var, _val) \
  18879. do { \
  18880. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID, _val); \
  18881. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S)); \
  18882. } while (0)
  18883. #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S 14
  18884. #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M 0x003fc000
  18885. #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_GET(_var) \
  18886. (((_var) & HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S)
  18887. #define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_SET(_var, _val) \
  18888. do { \
  18889. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_VDEV_ID, _val); \
  18890. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S)); \
  18891. } while (0)
  18892. #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S 22
  18893. #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M 0x03C00000
  18894. #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_GET(_var) \
  18895. (((_var) & HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S)
  18896. #define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_SET(_var, _val) \
  18897. do { \
  18898. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID, _val); \
  18899. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S)); \
  18900. } while (0)
  18901. #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S 26
  18902. #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M 0x1c000000
  18903. #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_GET(_var) \
  18904. (((_var) & HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)
  18905. #define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_SET(_var, _val) \
  18906. do { \
  18907. HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_CHIP_ID, _val); \
  18908. ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \
  18909. } while (0)
  18910. /* generic variables for masks and shifts for various fields */
  18911. extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S;
  18912. extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_M;
  18913. extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_S;
  18914. extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_M;
  18915. /* generic function pointers to get/set values from rx peer metadata v0/v1/v1a/v1b */
  18916. extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_ID_GET) (A_UINT32 var);
  18917. extern void (*HTT_RX_PEER_META_DATA_PEER_ID_SET) (A_UINT32 *var, A_UINT32 val);
  18918. extern A_UINT32 (*HTT_RX_PEER_META_DATA_VDEV_ID_GET) (A_UINT32 var);
  18919. extern void (*HTT_RX_PEER_META_DATA_VDEV_ID_SET) (A_UINT32 *var, A_UINT32 val);
  18920. extern A_UINT32 (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_GET) (A_UINT32 var);
  18921. extern void (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_SET) (A_UINT32 *var, A_UINT32 val);
  18922. extern A_UINT32 (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_GET) (A_UINT32 var);
  18923. extern void (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val);
  18924. extern A_UINT32 (*HTT_RX_PEER_META_DATA_LMAC_ID_GET) (A_UINT32 var);
  18925. extern void (*HTT_RX_PEER_META_DATA_LMAC_ID_SET) (A_UINT32 *var, A_UINT32 val);
  18926. extern A_UINT32 (*HTT_RX_PEER_META_DATA_CHIP_ID_GET) (A_UINT32 var);
  18927. extern void (*HTT_RX_PEER_META_DATA_CHIP_ID_SET) (A_UINT32 *var, A_UINT32 val);
  18928. extern A_UINT32 (*HTT_RX_PEER_META_DATA_HW_LINK_ID_GET) (A_UINT32 var);
  18929. extern void (*HTT_RX_PEER_META_DATA_HW_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val);
  18930. extern A_UINT32 (*HTT_RX_PEER_META_DATA_QDATA_REFILL_GET) (A_UINT32 var);
  18931. extern void (*HTT_RX_PEER_META_DATA_QDATA_REFILL_SET) (A_UINT32 *var, A_UINT32 val);
  18932. /*
  18933. * In some systems, the host SW wants to specify priorities between
  18934. * different MSDU / flow queues within the same peer-TID.
  18935. * The below enums are used for the host to identify to the target
  18936. * which MSDU queue's priority it wants to adjust.
  18937. */
  18938. /*
  18939. * The MSDUQ index describe index of TCL HW, where each index is
  18940. * used for queuing particular types of MSDUs.
  18941. * The different MSDU queue types are defined in HTT_MSDU_QTYPE.
  18942. */
  18943. enum HTT_MSDUQ_INDEX {
  18944. HTT_MSDUQ_INDEX_NON_UDP, /* NON UDP MSDUQ index */
  18945. HTT_MSDUQ_INDEX_UDP, /* UDP MSDUQ index */
  18946. HTT_MSDUQ_INDEX_CUSTOM_PRIO_0, /* Latency priority 0 index */
  18947. HTT_MSDUQ_INDEX_CUSTOM_PRIO_1, /* Latency priority 1 index */
  18948. HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_0, /* High num TID cases/ MLO dedicate link cases */
  18949. HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_1, /* High num TID cases/ MLO dedicate link cases */
  18950. HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_2, /* High num TID cases/ MLO dedicate link cases */
  18951. HTT_MSDUQ_INDEX_CUSTOM_EXT_PRIO_3, /* High num TID cases/ MLO dedicate link cases */
  18952. HTT_MSDUQ_MAX_INDEX,
  18953. };
  18954. /* MSDU qtype definition */
  18955. enum HTT_MSDU_QTYPE {
  18956. /*
  18957. * The LATENCY_CRIT_0 and LATENCY_CRIT_1 queue types don't have a fixed
  18958. * relative priority. Instead, the relative priority of CRIT_0 versus
  18959. * CRIT_1 is controlled by the FW, through the configuration parameters
  18960. * it applies to the queues.
  18961. */
  18962. HTT_MSDU_QTYPE_LATENCY_CRIT_0, /* Specified MSDUQ index used for latency critical 0 */
  18963. HTT_MSDU_QTYPE_LATENCY_CRIT_1, /* Specified MSDUQ index used for latency critical 1 */
  18964. HTT_MSDU_QTYPE_UDP, /* Specifies MSDUQ index used for UDP flow */
  18965. HTT_MSDU_QTYPE_NON_UDP, /* Specifies MSDUQ index used for non-udp flow */
  18966. HTT_MSDU_QTYPE_HOL, /* Specified MSDUQ index used for Head of Line */
  18967. HTT_MSDU_QTYPE_USER_SPECIFIED, /* Specifies MSDUQ index used for advertising changeable flow type */
  18968. HTT_MSDU_QTYPE_HI_PRIO, /* Specifies MSDUQ index used for high priority flow type */
  18969. HTT_MSDU_QTYPE_LO_PRIO, /* Specifies MSDUQ index used for low priority flow type */
  18970. /* New MSDU_QTYPE should be added above this line */
  18971. /*
  18972. * Below QTYPE_MAX will increase if additional QTYPEs are defined
  18973. * in the future. Hence HTT_MSDU_QTYPE_MAX can't be used in
  18974. * any host/target message definitions. The QTYPE_MAX value can
  18975. * only be used internally within the host or within the target.
  18976. * If host or target find a qtype value is >= HTT_MSDU_QTYPE_MAX
  18977. * it must regard the unexpected value as a default qtype value,
  18978. * or ignore it.
  18979. */
  18980. HTT_MSDU_QTYPE_MAX,
  18981. HTT_MSDU_QTYPE_NOT_IN_USE = 255, /* corresponding MSDU index is not in use */
  18982. };
  18983. enum HTT_MSDUQ_LEGACY_FLOW_INDEX {
  18984. HTT_MSDUQ_LEGACY_HI_PRI_FLOW_INDEX = 0,
  18985. HTT_MSDUQ_LEGACY_LO_PRI_FLOW_INDEX = 1,
  18986. HTT_MSDUQ_LEGACY_UDP_FLOW_INDEX = 2,
  18987. HTT_MSDUQ_LEGACY_NON_UDP_FLOW_INDEX = 3,
  18988. };
  18989. /**
  18990. * @brief target -> host mlo timestamp offset indication
  18991. *
  18992. * MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND
  18993. *
  18994. * @details
  18995. * The following field definitions describe the format of the HTT target
  18996. * to host mlo timestamp offset indication message.
  18997. *
  18998. *
  18999. * |31 16|15 12|11 10|9 8|7 0 |
  19000. * |----------------------------------------------------------------------|
  19001. * | mac_clk_freq_mhz | rsvd |chip_id|pdev_id| msg type |
  19002. * |----------------------------------------------------------------------|
  19003. * | Sync time stamp lo in us |
  19004. * |----------------------------------------------------------------------|
  19005. * | Sync time stamp hi in us |
  19006. * |----------------------------------------------------------------------|
  19007. * | mlo time stamp offset lo in us |
  19008. * |----------------------------------------------------------------------|
  19009. * | mlo time stamp offset hi in us |
  19010. * |----------------------------------------------------------------------|
  19011. * | mlo time stamp offset clocks in clock ticks |
  19012. * |----------------------------------------------------------------------|
  19013. * |31 26|25 16|15 0 |
  19014. * |rsvd2 | mlo time stamp | mlo time stamp compensation in us |
  19015. * | | compensation in clks | |
  19016. * |----------------------------------------------------------------------|
  19017. * |31 22|21 0 |
  19018. * | rsvd 3 | mlo time stamp comp timer period |
  19019. * |----------------------------------------------------------------------|
  19020. * The message is interpreted as follows:
  19021. *
  19022. * dword0 - b'0:7 - msg_type: This will be set to
  19023. * HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND
  19024. * value: 0x28
  19025. *
  19026. * dword0 - b'9:8 - pdev_id
  19027. *
  19028. * dword0 - b'11:10 - chip_id
  19029. *
  19030. * dword0 - b'15:12 - rsvd1: Reserved for future use
  19031. *
  19032. * dword0 - b'31:16 - mac clock frequency of the mac HW block in MHz
  19033. *
  19034. * dword1 - b'31:0 - lower 32 bits of the WLAN global time stamp (in us) at
  19035. * which last sync interrupt was received
  19036. *
  19037. * dword2 - b'31:0 - upper 32 bits of the WLAN global time stamp (in us) at
  19038. * which last sync interrupt was received
  19039. *
  19040. * dword3 - b'31:0 - lower 32 bits of the MLO time stamp offset in us
  19041. *
  19042. * dword4 - b'31:0 - upper 32 bits of the MLO time stamp offset in us
  19043. *
  19044. * dword5 - b'31:0 - MLO time stamp offset in clock ticks for sub us
  19045. *
  19046. * dword6 - b'15:0 - MLO time stamp compensation applied in us
  19047. *
  19048. * dword6 - b'25:16 - MLO time stamp compensation applied in clock ticks
  19049. * for sub us resolution
  19050. *
  19051. * dword6 - b'31:26 - rsvd2: Reserved for future use
  19052. *
  19053. * dword7 - b'21:0 - period of MLO compensation timer at which compensation
  19054. * is applied, in us
  19055. *
  19056. * dword7 - b'31:22 - rsvd3: Reserved for future use
  19057. */
  19058. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_M 0x000000FF
  19059. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S 0
  19060. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_M 0x00000300
  19061. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S 8
  19062. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_M 0x00000C00
  19063. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S 10
  19064. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_M 0xFFFF0000
  19065. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S 16
  19066. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_M 0x0000FFFF
  19067. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S 0
  19068. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_M 0x03FF0000
  19069. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S 16
  19070. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_M 0x003FFFFF
  19071. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S 0
  19072. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_GET(_var) \
  19073. (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S)
  19074. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_SET(_var, _val) \
  19075. do { \
  19076. HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE, _val); \
  19077. ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MSG_TYPE_S)); \
  19078. } while (0)
  19079. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_GET(_var) \
  19080. (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S)
  19081. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_SET(_var, _val) \
  19082. do { \
  19083. HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID, _val); \
  19084. ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_PDEV_ID_S)); \
  19085. } while (0)
  19086. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_GET(_var) \
  19087. (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_M) >> HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S)
  19088. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_SET(_var, _val) \
  19089. do { \
  19090. HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID, _val); \
  19091. ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_CHIP_ID_S)); \
  19092. } while (0)
  19093. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_GET(_var) \
  19094. (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_M) >> \
  19095. HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S)
  19096. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_SET(_var, _val) \
  19097. do { \
  19098. HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ, _val); \
  19099. ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MAC_CLK_FREQ_MHZ_S)); \
  19100. } while (0)
  19101. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_GET(_var) \
  19102. (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_M) >> \
  19103. HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S)
  19104. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_SET(_var, _val) \
  19105. do { \
  19106. HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US, _val); \
  19107. ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_US_S)); \
  19108. } while (0)
  19109. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_GET(_var) \
  19110. (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_M) >> \
  19111. HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S)
  19112. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_SET(_var, _val) \
  19113. do { \
  19114. HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS, _val); \
  19115. ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_CLKS_S)); \
  19116. } while (0)
  19117. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_GET(_var) \
  19118. (((_var) & HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_M) >> \
  19119. HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S)
  19120. #define HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_SET(_var, _val) \
  19121. do { \
  19122. HTT_CHECK_SET_VAL(HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US, _val); \
  19123. ((_var) |= ((_val) << HTT_T2H_MLO_TIMESTAMP_OFFSET_MLO_TIMESTAMP_COMP_PERIOD_US_S)); \
  19124. } while (0)
  19125. typedef struct {
  19126. A_UINT32 msg_type: 8, /* bits 7:0 */
  19127. pdev_id: 2, /* bits 9:8 */
  19128. chip_id: 2, /* bits 11:10 */
  19129. reserved1: 4, /* bits 15:12 */
  19130. mac_clk_freq_mhz: 16; /* bits 31:16 */
  19131. A_UINT32 sync_timestamp_lo_us;
  19132. A_UINT32 sync_timestamp_hi_us;
  19133. A_UINT32 mlo_timestamp_offset_lo_us;
  19134. A_UINT32 mlo_timestamp_offset_hi_us;
  19135. A_UINT32 mlo_timestamp_offset_clks;
  19136. A_UINT32 mlo_timestamp_comp_us: 16, /* bits 15:0 */
  19137. mlo_timestamp_comp_clks: 10, /* bits 25:16 */
  19138. reserved2: 6; /* bits 31:26 */
  19139. A_UINT32 mlo_timestamp_comp_timer_period_us: 22, /* bits 21:0 */
  19140. reserved3: 10; /* bits 31:22 */
  19141. } htt_t2h_mlo_offset_ind_t;
  19142. /*
  19143. * @brief target -> host VDEV TX RX STATS
  19144. *
  19145. * MSG_TYPE => HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND
  19146. *
  19147. * @details
  19148. * HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND message is sent by the target
  19149. * every periodic interval programmed in HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG.
  19150. * After the host sends an initial HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG,
  19151. * this HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND message will be sent
  19152. * periodically by target even in the absence of any further HTT request
  19153. * messages from host.
  19154. *
  19155. * The message is formatted as follows:
  19156. *
  19157. * |31 16|15 8|7 0|
  19158. * |---------------------------------+----------------+----------------|
  19159. * | payload_size | pdev_id | msg_type |
  19160. * |---------------------------------+----------------+----------------|
  19161. * | reserved0 |
  19162. * |-------------------------------------------------------------------|
  19163. * | reserved1 |
  19164. * |-------------------------------------------------------------------|
  19165. * | reserved2 |
  19166. * |-------------------------------------------------------------------|
  19167. * | |
  19168. * | VDEV specific Tx Rx stats info |
  19169. * | |
  19170. * |-------------------------------------------------------------------|
  19171. *
  19172. * The message is interpreted as follows:
  19173. * dword0 - b'0:7 - msg_type: This will be set to 0x2c
  19174. * (HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND)
  19175. * b'8:15 - pdev_id
  19176. * b'16:31 - size in bytes of the payload that follows the 16-byte
  19177. * message header fields (msg_type through reserved2)
  19178. * dword1 - b'0:31 - reserved0.
  19179. * dword2 - b'0:31 - reserved1.
  19180. * dword3 - b'0:31 - reserved2.
  19181. */
  19182. typedef struct {
  19183. A_UINT32 msg_type: 8,
  19184. pdev_id: 8,
  19185. payload_size: 16;
  19186. A_UINT32 reserved0;
  19187. A_UINT32 reserved1;
  19188. A_UINT32 reserved2;
  19189. } htt_t2h_vdevs_txrx_stats_periodic_hdr_t;
  19190. #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_HDR_SIZE 16
  19191. #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_M 0x0000FF00
  19192. #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S 8
  19193. #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \
  19194. (((_var) & HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S)
  19195. #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \
  19196. do { \
  19197. HTT_CHECK_SET_VAL(HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID, _val); \
  19198. ((_var) |= ((_val) << HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PDEV_ID_S)); \
  19199. } while (0)
  19200. #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_M 0xFFFF0000
  19201. #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S 16
  19202. #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_GET(_var) \
  19203. (((_var) & HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_M) >> HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S)
  19204. #define HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_SET(_var, _val) \
  19205. do { \
  19206. HTT_CHECK_SET_VAL(HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE, _val); \
  19207. ((_var) |= ((_val) << HTT_T2H_VDEVS_TXRX_STATS_PERIODIC_IND_PAYLOAD_SIZE_S)); \
  19208. } while (0)
  19209. /* SOC related stats */
  19210. typedef struct {
  19211. htt_tlv_hdr_t tlv_hdr;
  19212. /* When TQM is not able to find the peers during Tx, then it drops the packets
  19213. * This can be due to either the peer is deleted or deletion is ongoing
  19214. * */
  19215. A_UINT32 inv_peers_msdu_drop_count_lo;
  19216. A_UINT32 inv_peers_msdu_drop_count_hi;
  19217. } htt_stats_soc_txrx_stats_common_tlv;
  19218. /* preserve old name alias for new name consistent with the tag name */
  19219. typedef htt_stats_soc_txrx_stats_common_tlv htt_t2h_soc_txrx_stats_common_tlv;
  19220. /* VDEV HW Tx/Rx stats */
  19221. typedef struct {
  19222. htt_tlv_hdr_t tlv_hdr;
  19223. A_UINT32 vdev_id;
  19224. /* Rx msdu byte cnt */
  19225. A_UINT32 rx_msdu_byte_cnt_lo;
  19226. A_UINT32 rx_msdu_byte_cnt_hi;
  19227. /* Rx msdu cnt */
  19228. A_UINT32 rx_msdu_cnt_lo;
  19229. A_UINT32 rx_msdu_cnt_hi;
  19230. /* tx msdu byte cnt */
  19231. A_UINT32 tx_msdu_byte_cnt_lo;
  19232. A_UINT32 tx_msdu_byte_cnt_hi;
  19233. /* tx msdu cnt */
  19234. A_UINT32 tx_msdu_cnt_lo;
  19235. A_UINT32 tx_msdu_cnt_hi;
  19236. /* tx excessive retry discarded msdu cnt */
  19237. A_UINT32 tx_msdu_excessive_retry_discard_cnt_lo;
  19238. A_UINT32 tx_msdu_excessive_retry_discard_cnt_hi;
  19239. /* TX congestion ctrl msdu drop cnt */
  19240. A_UINT32 tx_msdu_cong_ctrl_drop_cnt_lo;
  19241. A_UINT32 tx_msdu_cong_ctrl_drop_cnt_hi;
  19242. /* discarded tx msdus cnt coz of time to live expiry */
  19243. A_UINT32 tx_msdu_ttl_expire_drop_cnt_lo;
  19244. A_UINT32 tx_msdu_ttl_expire_drop_cnt_hi;
  19245. /* tx excessive retry discarded msdu byte cnt */
  19246. A_UINT32 tx_msdu_excessive_retry_discard_byte_cnt_lo;
  19247. A_UINT32 tx_msdu_excessive_retry_discard_byte_cnt_hi;
  19248. /* TX congestion ctrl msdu drop byte cnt */
  19249. A_UINT32 tx_msdu_cong_ctrl_drop_byte_cnt_lo;
  19250. A_UINT32 tx_msdu_cong_ctrl_drop_byte_cnt_hi;
  19251. /* discarded tx msdus byte cnt coz of time to live expiry */
  19252. A_UINT32 tx_msdu_ttl_expire_drop_byte_cnt_lo;
  19253. A_UINT32 tx_msdu_ttl_expire_drop_byte_cnt_hi;
  19254. /* TQM bypass frame cnt */
  19255. A_UINT32 tqm_bypass_frame_cnt_lo;
  19256. A_UINT32 tqm_bypass_frame_cnt_hi;
  19257. /* TQM bypass byte cnt */
  19258. A_UINT32 tqm_bypass_byte_cnt_lo;
  19259. A_UINT32 tqm_bypass_byte_cnt_hi;
  19260. } htt_stats_vdev_txrx_stats_hw_stats_tlv;
  19261. /* preserve old name alias for new name consistent with the tag name */
  19262. typedef htt_stats_vdev_txrx_stats_hw_stats_tlv
  19263. htt_t2h_vdev_txrx_stats_hw_stats_tlv;
  19264. /*
  19265. * MSG_TYPE => HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF
  19266. *
  19267. * @details
  19268. * The SAWF_DEF_QUEUES_MAP_REPORT_CONF message is sent by the target in
  19269. * response to a SAWF_DEF_QUEUES_MAP_REPORT_REQ from the host.
  19270. * The SAWF_DEF_QUEUES_MAP_REPORT_CONF will show which service class
  19271. * the default MSDU queues of each of the specified TIDs for the peer
  19272. * specified in the SAWF_DEF_QUEUES_MAP_REPORT_REQ message are linked to.
  19273. * If the default MSDU queues of a given TID within the peer are not linked
  19274. * to a service class, the svc_class_id field for that TID will have a
  19275. * 0xff HTT_SAWF_SVC_CLASS_INVALID_ID value to indicate the default MSDU
  19276. * queues for that TID are not mapped to any service class.
  19277. *
  19278. * |31 16|15 8|7 0|
  19279. * |------------------------------+--------------+--------------|
  19280. * | peer ID | reserved | msg type |
  19281. * |------------------------------+--------------+------+-------|
  19282. * | reserved | svc class ID | TID |
  19283. * |------------------------------------------------------------|
  19284. * ...
  19285. * |------------------------------------------------------------|
  19286. * | reserved | svc class ID | TID |
  19287. * |------------------------------------------------------------|
  19288. * Header fields:
  19289. * dword0 - b'7:0 - msg_type: This will be set to
  19290. * 0x2d (HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF)
  19291. * b'31:16 - peer ID
  19292. * dword1 - b'7:0 - TID
  19293. * b'15:8 - svc class ID
  19294. * (dword2, etc. same format as dword1)
  19295. */
  19296. #define HTT_SAWF_SVC_CLASS_INVALID_ID 0xff
  19297. PREPACK struct htt_t2h_sawf_def_queues_map_report_conf {
  19298. A_UINT32 msg_type :8,
  19299. reserved0 :8,
  19300. peer_id :16;
  19301. struct {
  19302. A_UINT32 tid :8,
  19303. svc_class_id :8,
  19304. reserved1 :16;
  19305. } tid_reports[1/*or more*/];
  19306. } POSTPACK;
  19307. #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_CONF_HDR_BYTES 4 /* msg_type, peer_id */
  19308. #define HTT_SAWF_DEF_QUEUES_MAP_REPORT_CONF_ELEM_BYTES 4 /* TID, svc_class_id */
  19309. #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_M 0xFFFF0000
  19310. #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S 16
  19311. #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_GET(_var) \
  19312. (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_M) >> \
  19313. HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S)
  19314. #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_SET(_var, _val) \
  19315. do { \
  19316. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID, _val); \
  19317. ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_PEER_ID_S)); \
  19318. } while (0)
  19319. #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_M 0x000000FF
  19320. #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S 0
  19321. #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_GET(_var) \
  19322. (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_M) >> \
  19323. HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S)
  19324. #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_SET(_var, _val) \
  19325. do { \
  19326. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID, _val); \
  19327. ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_TID_S)); \
  19328. } while (0)
  19329. #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_M 0x0000FF00
  19330. #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S 8
  19331. #define HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_GET(_var) \
  19332. (((_var) & HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_M) >> \
  19333. HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S)
  19334. #define HTT_RX_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_SET(_var, _val) \
  19335. do { \
  19336. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID, _val); \
  19337. ((_var) |= ((_val) << HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF_SVC_CLASS_ID_S)); \
  19338. } while (0)
  19339. /*
  19340. * MSG_TYPE => HTT_T2H_SAWF_MSDUQ_INFO_IND
  19341. *
  19342. * @details
  19343. * When SAWF is enabled and a flow is mapped to a policy during the traffic
  19344. * flow if the flow is seen the associated service class is conveyed to the
  19345. * target via TCL Data Command. Target on the other hand internally creates the
  19346. * MSDUQ. Once the target creates the MSDUQ the target sends the information
  19347. * of the newly created MSDUQ and some other identifiers to uniquely identity
  19348. * the newly created MSDUQ
  19349. *
  19350. * |31 27| 24|23 16|15|14 11|10|9 8|7 4|3 0|
  19351. * |------------------------------+------------------------+--------------|
  19352. * | peer ID | HTT qtype | msg type |
  19353. * |---------------------------------+--------------+--+---+-------+------|
  19354. * | reserved |AST list index|FO|WC | HLOS | remap|
  19355. * | | | | | TID | TID |
  19356. * |---------------------+------------------------------------------------|
  19357. * | reserved1 | tgt_opaque_id |
  19358. * |---------------------+------------------------------------------------|
  19359. *
  19360. * Header fields:
  19361. *
  19362. * dword0 - b'7:0 - msg_type: This will be set to
  19363. * 0x2e (HTT_T2H_SAWF_MSDUQ_INFO_IND)
  19364. * b'15:8 - HTT qtype
  19365. * b'31:16 - peer ID
  19366. *
  19367. * dword1 - b'3:0 - remap TID, as assigned in firmware
  19368. * b'7:4 - HLOS TID, as sent by host in TCL Data Command
  19369. * hlos_tid : Common to Lithium and Beryllium
  19370. * b'9:8 - who_classify_info_sel (WC), as sent by host in
  19371. * TCL Data Command : Beryllium
  19372. * b10 - flow_override (FO), as sent by host in
  19373. * TCL Data Command: Beryllium
  19374. * b11:14 - ast_list_idx
  19375. * Array index into the list of extension AST entries
  19376. * (not the actual AST 16-bit index).
  19377. * The ast_list_idx is one-based, with the following
  19378. * range of values:
  19379. * - legacy targets supporting 16 user-defined
  19380. * MSDU queues: 1-2
  19381. * - legacy targets supporting 48 user-defined
  19382. * MSDU queues: 1-6
  19383. * - new targets: 0 (peer_id is used instead)
  19384. * Note that since ast_list_idx is one-based,
  19385. * the host will need to subtract 1 to use it as an
  19386. * index into a list of extension AST entries.
  19387. * b15:31 - reserved
  19388. *
  19389. * dword2 - b'23:0 - tgt_opaque_id Opaque Tx flow number which is a
  19390. * unique MSDUQ id in firmware
  19391. * b'24:31 - reserved1
  19392. */
  19393. PREPACK struct htt_t2h_sawf_msduq_event {
  19394. A_UINT32 msg_type : 8,
  19395. htt_qtype : 8,
  19396. peer_id :16;
  19397. A_UINT32 remap_tid : 4,
  19398. hlos_tid : 4,
  19399. who_classify_info_sel : 2,
  19400. flow_override : 1,
  19401. ast_list_idx : 4,
  19402. reserved :17;
  19403. A_UINT32 tgt_opaque_id :24,
  19404. reserved1 : 8;
  19405. } POSTPACK;
  19406. #define HTT_SAWF_MSDUQ_INFO_SIZE (sizeof(struct htt_t2h_sawf_msduq_event))
  19407. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_M 0x0000FF00
  19408. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S 8
  19409. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_GET(_var) \
  19410. (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_M) >> \
  19411. HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S)
  19412. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_SET(_var, _val) \
  19413. do { \
  19414. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE, _val); \
  19415. ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_QTYPE_S));\
  19416. } while (0)
  19417. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_M 0xFFFF0000
  19418. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S 16
  19419. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_GET(_var) \
  19420. (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_M) >> \
  19421. HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S)
  19422. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_SET(_var, _val) \
  19423. do { \
  19424. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID, _val); \
  19425. ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_PEER_ID_S)); \
  19426. } while (0)
  19427. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_M 0x0000000F
  19428. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S 0
  19429. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_GET(_var) \
  19430. (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_M) >> \
  19431. HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S)
  19432. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_SET(_var, _val) \
  19433. do { \
  19434. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID, _val); \
  19435. ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_REMAP_TID_S)); \
  19436. } while (0)
  19437. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_M 0x000000F0
  19438. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S 4
  19439. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_GET(_var) \
  19440. (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_M) >> \
  19441. HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S)
  19442. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_SET(_var, _val) \
  19443. do { \
  19444. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID, _val); \
  19445. ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_HLOS_TID_S)); \
  19446. } while (0)
  19447. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_M 0x00000300
  19448. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S 8
  19449. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_GET(_var) \
  19450. (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_M) >> \
  19451. HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S)
  19452. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_SET(_var, _val) \
  19453. do { \
  19454. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL, _val); \
  19455. ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_WHO_CLASS_INFO_SEL_S)); \
  19456. } while (0)
  19457. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_M 0x00000400
  19458. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S 10
  19459. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_GET(_var) \
  19460. (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_M) >> \
  19461. HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S)
  19462. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_SET(_var, _val) \
  19463. do { \
  19464. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE, _val); \
  19465. ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_FLOW_OVERRIDE_S)); \
  19466. } while (0)
  19467. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_M 0x00007800
  19468. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S 11
  19469. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_GET(_var) \
  19470. (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_M) >> \
  19471. HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S)
  19472. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_SET(_var, _val) \
  19473. do { \
  19474. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX, _val); \
  19475. ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_AST_LIST_IDX_S)); \
  19476. } while (0)
  19477. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_M 0x00FFFFFF
  19478. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S 0
  19479. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_GET(_var) \
  19480. (((_var) & HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_M) >> \
  19481. HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S)
  19482. #define HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_SET(_var, _val) \
  19483. do { \
  19484. HTT_CHECK_SET_VAL(HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID, _val); \
  19485. ((_var) |= ((_val) << HTT_T2H_SAWF_MSDUQ_INFO_HTT_TGT_OPAQUE_ID_S)); \
  19486. } while (0)
  19487. /**
  19488. * @brief target -> PPDU id format indication
  19489. *
  19490. * MSG_TYPE => HTT_T2H_PPDU_ID_FMT_IND
  19491. *
  19492. * @details
  19493. * The following field definitions describe the format of the HTT target
  19494. * to host PPDU ID format indication message.
  19495. * hwsch_cmd_id :- A number per ring, increases by one with each HWSCH command.
  19496. * ring_id :- HWSCH ring id in which this PPDU was enqueued.
  19497. * seq_idx :- Sequence control index of this PPDU.
  19498. * link_id :- HW link ID of the link in which the PPDU was enqueued.
  19499. * seq_cmd_type:- WHAL_TXSEND_FTYPE (SU Data, MU Data, SGEN frames etc.)
  19500. * tqm_cmd:-
  19501. *
  19502. * |31 27|26 22|21 17| 16 |15 11|10 8|7 6|5 1| 0 |
  19503. * |--------------------------------------------------+------------------------|
  19504. * | rsvd0 | msg type |
  19505. * |-----+----------+----------+---------+-----+----------+----------+---------|
  19506. * |rsvd2|ring_id OF|ring_id NB|ring_id V|rsvd1|cmd_id OF |cmd_id NB |cmd_id V |
  19507. * |-----+----------+----------+---------+-----+----------+----------+---------|
  19508. * |rsvd4|link_id OF|link_id NB|link_id V|rsvd3|seq_idx OF|seq_idx NB|seq_idx V|
  19509. * |-----+----------+----------+---------+-----+----------+----------+---------|
  19510. * |rsvd6|tqm_cmd OF|tqm_cmd NB|tqm_cmd V|rsvd5|seq_cmd OF|seq_cmd NB|seq_cmd V|
  19511. * |-----+----------+----------+---------+-----+----------+----------+---------|
  19512. * |rsvd8| crc OF | crc NB | crc V |rsvd7|mac_id OF |mac_id NB |mac_id V |
  19513. * |-----+----------+----------+---------+-----+----------+----------+---------|
  19514. * Where: OF = bit offset, NB = number of bits, V = valid
  19515. * The message is interpreted as follows:
  19516. *
  19517. * dword0 - b'7:0 - msg_type: This will be set to
  19518. * HTT_T2H_PPDU_ID_FMT_IND
  19519. * value: 0x30
  19520. *
  19521. * dword0 - b'31:8 - reserved
  19522. *
  19523. * dword1 - b'0:0 - field to indicate whether hwsch_cmd_id is valid or not
  19524. *
  19525. * dword1 - b'5:1 - number of bits in hwsch_cmd_id
  19526. *
  19527. * dword1 - b'10:6 - offset of hwsch_cmd_id (in number of bits)
  19528. *
  19529. * dword1 - b'15:11 - reserved for future use
  19530. *
  19531. * dword1 - b'16:16 - field to indicate whether ring_id is valid or not
  19532. *
  19533. * dword1 - b'21:17 - number of bits in ring_id
  19534. *
  19535. * dword1 - b'26:22 - offset of ring_id (in number of bits)
  19536. *
  19537. * dword1 - b'31:27 - reserved for future use
  19538. *
  19539. * dword2 - b'0:0 - field to indicate whether sequence index is valid or not
  19540. *
  19541. * dword2 - b'5:1 - number of bits in sequence index
  19542. *
  19543. * dword2 - b'10:6 - offset of sequence index (in number of bits)
  19544. *
  19545. * dword2 - b'15:11 - reserved for future use
  19546. *
  19547. * dword2 - b'16:16 - field to indicate whether link_id is valid or not
  19548. *
  19549. * dword2 - b'21:17 - number of bits in link_id
  19550. *
  19551. * dword2 - b'26:22 - offset of link_id (in number of bits)
  19552. *
  19553. * dword2 - b'31:27 - reserved for future use
  19554. *
  19555. * dword3 - b'0:0 - field to indicate whether seq_cmd_type is valid or not
  19556. *
  19557. * dword3 - b'5:1 - number of bits in seq_cmd_type
  19558. *
  19559. * dword3 - b'10:6 - offset of seq_cmd_type (in number of bits)
  19560. *
  19561. * dword3 - b'15:11 - reserved for future use
  19562. *
  19563. * dword3 - b'16:16 - field to indicate whether tqm_cmd is valid or not
  19564. *
  19565. * dword3 - b'21:17 - number of bits in tqm_cmd
  19566. *
  19567. * dword3 - b'26:22 - offset of tqm_cmd (in number of bits)
  19568. *
  19569. * dword3 - b'31:27 - reserved for future use
  19570. *
  19571. * dword4 - b'0:0 - field to indicate whether mac_id is valid or not
  19572. *
  19573. * dword4 - b'5:1 - number of bits in mac_id
  19574. *
  19575. * dword4 - b'10:6 - offset of mac_id (in number of bits)
  19576. *
  19577. * dword4 - b'15:11 - reserved for future use
  19578. *
  19579. * dword4 - b'16:16 - field to indicate whether crc is valid or not
  19580. *
  19581. * dword4 - b'21:17 - number of bits in crc
  19582. *
  19583. * dword4 - b'26:22 - offset of crc (in number of bits)
  19584. *
  19585. * dword4 - b'31:27 - reserved for future use
  19586. *
  19587. */
  19588. #define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M 0x00000001
  19589. #define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S 0
  19590. #define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M 0x0000003E
  19591. #define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S 1
  19592. #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M 0x000007C0
  19593. #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S 6
  19594. #define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M 0x00010000
  19595. #define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S 16
  19596. #define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M 0x003E0000
  19597. #define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S 17
  19598. #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M 0x07C00000
  19599. #define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S 22
  19600. /* macros for accessing lower 16 bits in dword */
  19601. #define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0(word, value) \
  19602. do { \
  19603. HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS15_0, value); \
  19604. (word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S; \
  19605. } while (0)
  19606. #define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS15_0(word) \
  19607. (((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S)
  19608. #define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0(word, value) \
  19609. do { \
  19610. HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS15_0, value); \
  19611. (word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S; \
  19612. } while (0)
  19613. #define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS15_0(word) \
  19614. (((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S)
  19615. #define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0(word, value) \
  19616. do { \
  19617. HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0, value); \
  19618. (word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S; \
  19619. } while (0)
  19620. #define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS15_0(word) \
  19621. (((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S)
  19622. /* macros for accessing upper 16 bits in dword */
  19623. #define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16(word, value) \
  19624. do { \
  19625. HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS31_16, value); \
  19626. (word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S; \
  19627. } while (0)
  19628. #define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS31_16(word) \
  19629. (((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S)
  19630. #define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16(word, value) \
  19631. do { \
  19632. HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS31_16, value); \
  19633. (word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S; \
  19634. } while (0)
  19635. #define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS31_16(word) \
  19636. (((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S)
  19637. #define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16(word, value) \
  19638. do { \
  19639. HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16, value); \
  19640. (word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S; \
  19641. } while (0)
  19642. #define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS31_16(word) \
  19643. (((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S)
  19644. #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_VALID_SET \
  19645. HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
  19646. #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_BITS_SET \
  19647. HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
  19648. #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET_SET \
  19649. HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
  19650. #define HTT_PPDU_ID_FMT_IND_RING_ID_VALID_SET \
  19651. HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
  19652. #define HTT_PPDU_ID_FMT_IND_RING_ID_BITS_SET \
  19653. HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
  19654. #define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET_SET \
  19655. HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
  19656. #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_VALID_SET \
  19657. HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
  19658. #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_BITS_SET \
  19659. HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
  19660. #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET_SET \
  19661. HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
  19662. #define HTT_PPDU_ID_FMT_IND_LINK_ID_VALID_SET \
  19663. HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
  19664. #define HTT_PPDU_ID_FMT_IND_LINK_ID_BITS_SET \
  19665. HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
  19666. #define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET_SET \
  19667. HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
  19668. #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_VALID_SET \
  19669. HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
  19670. #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_BITS_SET \
  19671. HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
  19672. #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET_SET \
  19673. HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
  19674. #define HTT_PPDU_ID_FMT_IND_TQM_CMD_VALID_SET \
  19675. HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
  19676. #define HTT_PPDU_ID_FMT_IND_TQM_CMD_BITS_SET \
  19677. HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
  19678. #define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET_SET \
  19679. HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
  19680. #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_VALID_SET \
  19681. HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
  19682. #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_BITS_SET \
  19683. HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
  19684. #define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_OFFSET_SET \
  19685. HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
  19686. #define HTT_PPDU_ID_FMT_IND_CRC_VALID_SET \
  19687. HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
  19688. #define HTT_PPDU_ID_FMT_IND_CRC_BITS_SET \
  19689. HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
  19690. #define HTT_PPDU_ID_FMT_IND_CRC_OFFSET_SET \
  19691. HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
  19692. /* offsets in number dwords */
  19693. #define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET 1
  19694. #define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET 1
  19695. #define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET 2
  19696. #define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET 2
  19697. #define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET 3
  19698. #define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET 3
  19699. #define HTT_PPDU_ID_FMT_IND_MAC_ID_OFFSET 4
  19700. #define HTT_PPDU_ID_FMT_IND_CRC_OFFSET 4
  19701. typedef struct {
  19702. A_UINT32 msg_type: 8, /* bits 7:0 */
  19703. rsvd0: 24;/* bits 31:8 */
  19704. A_UINT32 hwsch_cmd_id_valid: 1, /* bits 0:0 */
  19705. hwsch_cmd_id_bits: 5, /* bits 5:1 */
  19706. hwsch_cmd_id_offset: 5, /* bits 10:6 */
  19707. rsvd1: 5, /* bits 15:11 */
  19708. ring_id_valid: 1, /* bits 16:16 */
  19709. ring_id_bits: 5, /* bits 21:17 */
  19710. ring_id_offset: 5, /* bits 26:22 */
  19711. rsvd2: 5; /* bits 31:27 */
  19712. A_UINT32 seq_idx_valid: 1, /* bits 0:0 */
  19713. seq_idx_bits: 5, /* bits 5:1 */
  19714. seq_idx_offset: 5, /* bits 10:6 */
  19715. rsvd3: 5, /* bits 15:11 */
  19716. link_id_valid: 1, /* bits 16:16 */
  19717. link_id_bits: 5, /* bits 21:17 */
  19718. link_id_offset: 5, /* bits 26:22 */
  19719. rsvd4: 5; /* bits 31:27 */
  19720. A_UINT32 seq_cmd_type_valid: 1, /* bits 0:0 */
  19721. seq_cmd_type_bits: 5, /* bits 5:1 */
  19722. seq_cmd_type_offset: 5, /* bits 10:6 */
  19723. rsvd5: 5, /* bits 15:11 */
  19724. tqm_cmd_valid: 1, /* bits 16:16 */
  19725. tqm_cmd_bits: 5, /* bits 21:17 */
  19726. tqm_cmd_offset: 5, /* bits 26:12 */
  19727. rsvd6: 5; /* bits 31:27 */
  19728. A_UINT32 mac_id_valid: 1, /* bits 0:0 */
  19729. mac_id_bits: 5, /* bits 5:1 */
  19730. mac_id_offset: 5, /* bits 10:6 */
  19731. rsvd8: 5, /* bits 15:11 */
  19732. crc_valid: 1, /* bits 16:16 */
  19733. crc_bits: 5, /* bits 21:17 */
  19734. crc_offset: 5, /* bits 26:12 */
  19735. rsvd9: 5; /* bits 31:27 */
  19736. } htt_t2h_ppdu_id_fmt_ind_t;
  19737. /**
  19738. * @brief target -> host RX_CCE_SUPER_RULE setup done message
  19739. *
  19740. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE
  19741. *
  19742. * @details
  19743. * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE message is sent by the target
  19744. * when RX_CCE_SUPER_RULE setup is done
  19745. *
  19746. * This message shows the configuration results after the setup operation.
  19747. * It will always be sent to host.
  19748. * The message would appear as follows:
  19749. *
  19750. * |31 24|23 16|15 8|7 0|
  19751. * |-----------------+-----------------+----------------+----------------|
  19752. * | result | response_type | pdev_id | msg_type |
  19753. * |---------------------------------------------------------------------|
  19754. *
  19755. * The message is interpreted as follows:
  19756. * dword0 - b'0:7 - msg_type: This will be set to 0x33
  19757. * (HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE)
  19758. * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is setup on
  19759. * b'16:23 - response_type: Indicate the response type of this setup
  19760. * done msg
  19761. * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE,
  19762. * response to HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST
  19763. * 1: HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE,
  19764. * response to HTT_RX_CCE_SUPER_RULE_INSTALL
  19765. * 2: HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE,
  19766. * response to HTT_RX_CCE_SUPER_RULE_RELEASE
  19767. * b'24:31 - result: Indicate result of setup operation
  19768. * For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE:
  19769. * b'24 - is_rule_enough: indicate if there are
  19770. * enough free cce rule slots
  19771. * 0: not enough
  19772. * 1: enough
  19773. * b'25:31 - avail_rule_num: indicate the number of
  19774. * remaining free cce rule slots, only makes sense
  19775. * when is_rule_enough = 0
  19776. * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE:
  19777. * b'24 - cfg_result_0: indicate the config result
  19778. * of RX_CCE_SUPER_RULE_0
  19779. * 0: Install/Uninstall fails
  19780. * 1: Install/Uninstall succeeds
  19781. * b'25 - cfg_result_1: indicate the config result
  19782. * of RX_CCE_SUPER_RULE_1
  19783. * 0: Install/Uninstall fails
  19784. * 1: Install/Uninstall succeeds
  19785. * b'26:31 - reserved
  19786. * For HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE:
  19787. * b'24 - cfg_result_0: indicate the config result
  19788. * of RX_CCE_SUPER_RULE_0
  19789. * 0: Release fails
  19790. * 1: Release succeeds
  19791. * b'25 - cfg_result_1: indicate the config result
  19792. * of RX_CCE_SUPER_RULE_1
  19793. * 0: Release fails
  19794. * 1: Release succeeds
  19795. * b'26:31 - reserved
  19796. */
  19797. enum htt_rx_cce_super_rule_setup_done_response_type {
  19798. HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE = 0,
  19799. HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE,
  19800. HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE,
  19801. /*All reply type should be before this*/
  19802. HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_RESPONSE,
  19803. };
  19804. PREPACK struct htt_rx_cce_super_rule_setup_done_t {
  19805. A_UINT8 msg_type;
  19806. A_UINT8 pdev_id;
  19807. A_UINT8 response_type;
  19808. union {
  19809. struct {
  19810. /* For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE */
  19811. A_UINT8 is_rule_enough: 1,
  19812. avail_rule_num: 7;
  19813. };
  19814. struct {
  19815. /*
  19816. * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE and
  19817. * HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE
  19818. */
  19819. A_UINT8 cfg_result_0: 1,
  19820. cfg_result_1: 1,
  19821. rsvd: 6;
  19822. };
  19823. } result;
  19824. } POSTPACK;
  19825. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_rx_cce_super_rule_setup_done_t))
  19826. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M 0x0000ff00
  19827. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S 8
  19828. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_GET(_var) \
  19829. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M) >> \
  19830. HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)
  19831. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_SET(_var, _val) \
  19832. do { \
  19833. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID, _val); \
  19834. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)); \
  19835. } while (0)
  19836. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000
  19837. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S 16
  19838. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_GET(_var) \
  19839. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M) >> \
  19840. HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)
  19841. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_SET(_var, _val) \
  19842. do { \
  19843. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE, _val); \
  19844. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)); \
  19845. } while (0)
  19846. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M 0xff000000
  19847. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S 24
  19848. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_GET(_var) \
  19849. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M) >> \
  19850. HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S)
  19851. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_SET(_var, _val) \
  19852. do { \
  19853. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT, _val); \
  19854. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S)); \
  19855. } while (0)
  19856. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M 0x01000000
  19857. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S 24
  19858. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_GET(_var) \
  19859. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M) >> \
  19860. HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S)
  19861. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_SET(_var, _val) \
  19862. do { \
  19863. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH, _val); \
  19864. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S)); \
  19865. } while (0)
  19866. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M 0xFE000000
  19867. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S 25
  19868. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_GET(_var) \
  19869. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M) >> \
  19870. HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S)
  19871. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_SET(_var, _val) \
  19872. do { \
  19873. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM, _val); \
  19874. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S)); \
  19875. } while (0)
  19876. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M 0x01000000
  19877. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S 24
  19878. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_GET(_var) \
  19879. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M) >> \
  19880. HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S)
  19881. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_SET(_var, _val) \
  19882. do { \
  19883. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0, _val); \
  19884. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S)); \
  19885. } while (0)
  19886. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M 0x02000000
  19887. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S 25
  19888. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_GET(_var) \
  19889. (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M) >> \
  19890. HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S)
  19891. #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_SET(_var, _val) \
  19892. do { \
  19893. HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1, _val); \
  19894. ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S)); \
  19895. } while (0)
  19896. /**
  19897. * @brief target -> host TX_LCE_SUPER_RULE setup done message
  19898. *
  19899. * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE
  19900. *
  19901. * @details
  19902. * HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE message is sent by the target
  19903. * when TX_SUPER_RULE setup is done.
  19904. *
  19905. * This message shows the configuration results after the setup operation.
  19906. * It will always be sent to host.
  19907. * The message would appear as follows:
  19908. *
  19909. * |31 24|23 16|15 8|7 0|
  19910. * |-----------------+-----------------+----------------+----------------|
  19911. * | reserved | response_type | pdev_id | msg_type |
  19912. * |---------------------------------------------------------------------|
  19913. * | tx_super_rule_result[0] |
  19914. * |---------------------------------------------------------------------|
  19915. * | tx_super_rule_result[1] |
  19916. * |---------------------------------------------------------------------|
  19917. * | tx_super_rule_result[2] |
  19918. * |---------------------------------------------------------------------|
  19919. *
  19920. * The message is interpreted as follows:
  19921. * dword0 - b'0:7 - msg_type: This will be set to 0x3b
  19922. * (HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE)
  19923. * b'8:15 - pdev_id: Identify which pdev TX_SUPER_RULE is setup on
  19924. * b'16:23 - response_type: Indicate the response type of this setup
  19925. * done msg
  19926. * 0: HTT_TX_LCE_SUPER_RULE_INSTALL_RESPONSE,
  19927. * response to HTT_TX_LCE_SUPER_RULE_INSTALL
  19928. * 1: HTT_TX_LCE_SUPER_RULE_RELEASE_RESPONSE,
  19929. * response to HTT_TX_LCE_SUPER_RULE_RELEASE or
  19930. * FW internal trigger on LCE rule release
  19931. * b'24:31 - reserved:
  19932. *
  19933. * Each tx_super_rule_result structure would appear as follows:
  19934. * |31 24|23 16|15 8|7 0|
  19935. * |---------------------------------------------------------------------|
  19936. * | is_valid | result | l4_dst_port |
  19937. * |---------------------------------------------------------------------|
  19938. *
  19939. * dword0 - b'0:15 - l4_dst_port: destination port corresponding to rule
  19940. * which is added/released
  19941. * b'16:23 - result: Indicate the result of the operation based on
  19942. * the message header's "response_type"
  19943. * For HTT_TX_LCE_SUPER_RULE_INSTALL_RESPONSE:
  19944. * 0: HTT_TX_LCE_SUPER_RULE_INSTALL_FAIL
  19945. * 1: HTT_TX_LCE_SUPER_RULE_INSTALL_SUCCESS
  19946. * For HTT_TX_LCE_SUPER_RULE_RELEASE_RESPONSE:
  19947. * 0: HTT_TX_LCE_SUPER_RULE_RELEASE_FAIL
  19948. * 1: HTT_TX_LCE_SUPER_RULE_RELEASE_SUCCESS
  19949. * 2: HTT_TX_LCE_SUPER_RULE_RELEASE_SUCCESS_HIGH_TPUT
  19950. *
  19951. * The tx_super_rule_result[1] structure is similar.
  19952. * The tx_super_rule_result[2] structure is similar.
  19953. */
  19954. enum htt_tx_lce_super_rule_setup_done_response_type {
  19955. /* Two LCE rules operation responses */
  19956. HTT_TX_LCE_SUPER_RULE_INSTALL_RESPONSE = 0,
  19957. HTT_TX_LCE_SUPER_RULE_RELEASE_RESPONSE,
  19958. /* All reply type should be before this */
  19959. HTT_TX_LCE_RULE_SETUP_INVALID_RESPONSE,
  19960. };
  19961. enum htt_tx_super_rule_install_response_result {
  19962. HTT_TX_LCE_SUPER_RULE_INSTALL_FAIL = 0,
  19963. HTT_TX_LCE_SUPER_RULE_INSTALL_SUCCESS,
  19964. };
  19965. enum htt_tx_super_rule_release_response_result{
  19966. HTT_TX_LCE_SUPER_RULE_RELEASE_FAIL = 0,
  19967. HTT_TX_LCE_SUPER_RULE_RELEASE_SUCCESS,
  19968. HTT_TX_LCE_SUPER_RULE_RELEASE_SUCCESS_HIGH_TPUT,
  19969. };
  19970. typedef struct {
  19971. A_UINT32 l4_dst_port: 16,
  19972. /* result:
  19973. * htt_tx_super_rule_install_response_result or
  19974. * htt_tx_super_rule_release_response_result
  19975. */
  19976. result: 8,
  19977. is_valid: 8;
  19978. } htt_tx_lce_super_rule_result_t;
  19979. PREPACK struct htt_tx_lce_super_rule_setup_done_t {
  19980. A_UINT8 msg_type;
  19981. A_UINT8 pdev_id;
  19982. A_UINT8 response_type; /* htt_tx_lce_super_rule_setup_done_response_type */
  19983. A_UINT8 reserved;
  19984. htt_tx_lce_super_rule_result_t tx_super_rule_result[HTT_TX_LCE_SUPER_RULE_SETUP_NUM];
  19985. } POSTPACK;
  19986. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_tx_lce_super_rule_setup_done_t))
  19987. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M 0x0000ff00
  19988. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S 8
  19989. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_GET(_var) \
  19990. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M) >> \
  19991. HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)
  19992. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_SET(_var, _val) \
  19993. do { \
  19994. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID, _val); \
  19995. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)); \
  19996. } while (0)
  19997. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000
  19998. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S 16
  19999. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_GET(_var) \
  20000. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M) >> \
  20001. HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)
  20002. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_SET(_var, _val) \
  20003. do { \
  20004. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE, _val); \
  20005. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)); \
  20006. } while (0)
  20007. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_M 0x0000ffff
  20008. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_S 0
  20009. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_GET(_var) \
  20010. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_M) >> \
  20011. HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_S)
  20012. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_SET(_var, _val) \
  20013. do { \
  20014. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT, _val); \
  20015. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_DONE_L4_DST_PORT_S)); \
  20016. } while (0)
  20017. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_M 0x00ff0000
  20018. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_S 16
  20019. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_GET(_var) \
  20020. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_M) >> \
  20021. HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_S)
  20022. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_SET(_var, _val) \
  20023. do { \
  20024. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT, _val); \
  20025. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_DONE_RESULT_S)); \
  20026. } while (0)
  20027. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_M 0xff000000
  20028. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_S 24
  20029. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_GET(_var) \
  20030. (((_var) & HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_M) >> \
  20031. HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_S)
  20032. #define HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_SET(_var, _val) \
  20033. do { \
  20034. HTT_CHECK_SET_VAL(HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID, _val); \
  20035. ((_var) |= ((_val) << HTT_TX_LCE_SUPER_RULE_SETUP_DONE_IS_VALID_S)); \
  20036. } while (0)
  20037. /**
  20038. * THE BELOW MESSAGE HAS BEEN DEPRECATED
  20039. *======================================
  20040. * @brief target -> host CoDel MSDU queue latencies array configuration
  20041. *
  20042. * MSG_TYPE => HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND
  20043. *
  20044. * @details
  20045. * The HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND message is used
  20046. * by the target to inform the host of the location and size of the DDR array of
  20047. * per MSDU queue latency metrics. This array is updated by the host and
  20048. * read by the target. The target uses these metric values to determine
  20049. * which MSDU queues have latencies exceeding their CoDel latency target.
  20050. *
  20051. * |31 16|15 8|7 0|
  20052. * |-------------------------------------------+----------|
  20053. * | number of array elements | reserved | MSG_TYPE |
  20054. * |-------------------------------------------+----------|
  20055. * | array physical address, low bits |
  20056. * |------------------------------------------------------|
  20057. * | array physical address, high bits |
  20058. * |------------------------------------------------------|
  20059. * Header fields:
  20060. * - MSG_TYPE
  20061. * Bits 7:0
  20062. * Purpose: Identifies this as a CoDel MSDU queue latencies
  20063. * array configuration message.
  20064. * Value: (HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND)
  20065. * - NUM_ELEM
  20066. * Bits 31:16
  20067. * Purpose: Inform the host of the length of the MSDU queue latencies array.
  20068. * Value: Specifies the number of elements in the MSDU queue latency
  20069. * metrics array. This value is the same as the maximum number of
  20070. * MSDU queues supported by the target.
  20071. * Since each array element is 16 bits, the size in bytes of the
  20072. * MSDU queue latency metrics array is twice the number of elements.
  20073. * - PADDR_LOW
  20074. * Bits 31:0
  20075. * Purpose: Inform the host of the MSDU queue latencies array's location.
  20076. * Value: Lower 32 bits of the physical address of the MSDU queue latency
  20077. * metrics array.
  20078. * - PADDR_HIGH
  20079. * Bits 31:0
  20080. * Purpose: Inform the host of the MSDU queue latencies array's location.
  20081. * Value: Upper 32 bits of the physical address of the MSDU queue latency
  20082. * metrics array.
  20083. */
  20084. typedef struct {
  20085. A_UINT32 msg_type: 8, /* bits 7:0 */
  20086. reserved: 8, /* bits 15:8 */
  20087. num_elem: 16; /* bits 31:16 */
  20088. A_UINT32 paddr_low;
  20089. A_UINT32 paddr_high;
  20090. } htt_t2h_codel_msduq_latencies_array_cfg_int_t; /* DEPRECATED */
  20091. #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_SIZE 12 /* bytes */
  20092. #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M 0xffff0000
  20093. #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S 16
  20094. #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_GET(_var) \
  20095. (((_var) & HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M) >> \
  20096. HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S)
  20097. #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_SET(_var, _val) \
  20098. do { \
  20099. HTT_CHECK_SET_VAL( \
  20100. HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM, _val); \
  20101. ((_var) |= ((_val) << \
  20102. HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S)); \
  20103. } while (0)
  20104. /*
  20105. * This CoDel MSDU queue latencies array whose location and number of
  20106. * elements are specified by this HTT_T2H message consists of 16-bit elements
  20107. * that each specify a statistical summary (min) of a MSDU queue's latency,
  20108. * using milliseconds units.
  20109. */
  20110. #define HTT_CODEL_MSDUQ_LATENCIES_ARRAY_ELEM_BYTES 2
  20111. /**
  20112. * @brief target -> host rx completion indication message definition
  20113. *
  20114. * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DATA_IND
  20115. *
  20116. * @details
  20117. * The following diagram shows the format of the Rx completion indication sent
  20118. * from the target to the host
  20119. *
  20120. * |31|29|28 24|23 12|11 9|8| 7|6|5|4|3|2|1|0|
  20121. * |---------------+----------------------------+----------------|
  20122. * | vdev_id | peer_id | msg_type |
  20123. * hdr: |---------------+--------------------------+-+----------------|
  20124. * | rsvd0 |F| msdu_cnt |
  20125. * pyld: |==========================================+=+================|
  20126. * MSDU 0 | buf addr lo (bits 31:0) |
  20127. * |-----+--------------------------------------+----------------|
  20128. * |rsvd1| SW buffer cookie | buf addr hi |
  20129. * |--+--+-----------------------------+--------+--+-+-+-+-+-+-+-|
  20130. * |R2| W| MSDU length | TID |MC|D|S|C|L|F|R|M|
  20131. * |-------------------------------------------------+---------+-|
  20132. * | rsvd3 | err info|E|
  20133. * |=================================================+=========+=|
  20134. * MSDU 1 | buf addr lo (bits 31:0) |
  20135. * : ... :
  20136. * | rsvd3 | err info|E|
  20137. * |-------------------------------------------------------------|
  20138. * Where:
  20139. * F = fragment
  20140. * M = MPDU retry bit
  20141. * R = raw MPDU frame
  20142. * F = first MSDU in MPDU
  20143. * L = last MSDU in MPDU
  20144. * C = MSDU continuation
  20145. * S = Souce Addr is valid
  20146. * D = Dest Addr is valid
  20147. * MC = Dest Addr is multicast / broadcast
  20148. * W = is first MSDU after WoW wakeup
  20149. * R2 = rsvd2
  20150. * E = error valid
  20151. */
  20152. /* htt_t2h_rx_data_msdu_err:
  20153. * To be filled in "htt_t2h_rx_data_msdu_info.error_info" field
  20154. * when FW forwards MSDU to host.
  20155. */
  20156. typedef enum htt_t2h_rx_data_msdu_err {
  20157. /* ERR_DECRYPT:
  20158. * FW sets this when rxdma_error_code = <enum 3 rxdma_decrypt_err>.
  20159. * host maintains error stats, recycles buffer.
  20160. */
  20161. HTT_RXDATA_ERR_DECRYPT = 0,
  20162. /* ERR_TKIP_MIC:
  20163. * FW sets this when rxdma_error_code = <enum 4 rxdma_tkip_mic_err>.
  20164. * Host maintains error stats, recycles buffer, sends notification to
  20165. * middleware.
  20166. */
  20167. HTT_RXDATA_ERR_TKIP_MIC = 1,
  20168. /* ERR_UNENCRYPTED:
  20169. * FW sets this when rxdma_error_code = <enum 5 rxdma_unecrypted_err>.
  20170. * Host maintains error stats, recycles buffer.
  20171. */
  20172. HTT_RXDATA_ERR_UNENCRYPTED = 2,
  20173. /* ERR_MSDU_LIMIT:
  20174. * FW sets this when rxdma_error_code = <enum 7 rxdma_msdu_limit_err>.
  20175. * Host maintains error stats, recycles buffer.
  20176. */
  20177. HTT_RXDATA_ERR_MSDU_LIMIT = 3,
  20178. /* ERR_FLUSH_REQUEST:
  20179. * FW sets this when rxdma_error_code = <enum 13 rxdma_flush_request>.
  20180. * Host maintains error stats, recycles buffer.
  20181. */
  20182. HTT_RXDATA_ERR_FLUSH_REQUEST = 4,
  20183. /* ERR_OOR:
  20184. * FW full reorder layer maps this error to <enum 7 regular_frame_OOR>.
  20185. * Host maintains error stats, recycles buffer mainly for low
  20186. * TCP KPI debugging.
  20187. */
  20188. HTT_RXDATA_ERR_OOR = 5,
  20189. /* ERR_2K_JUMP:
  20190. * FW full reorder layer maps this error to <enum 5 regular_frame_2k_jump>.
  20191. * Host maintains error stats, recycles buffer mainly for low
  20192. * TCP KPI debugging.
  20193. */
  20194. HTT_RXDATA_ERR_2K_JUMP = 6,
  20195. /* ERR_ZERO_LEN_MSDU:
  20196. * FW sets this error flag for a 0 length MSDU.
  20197. * Host maintains error stats, recycles buffer.
  20198. */
  20199. HTT_RXDATA_ERR_ZERO_LEN_MSDU = 7,
  20200. /* ERR_INVALID_PEER:
  20201. * FW sets this error flag when MSDU is recived from invalid PEER
  20202. * HOST decides to send DEAUTH or not, recyles buffer.
  20203. */
  20204. HTT_RXDATA_ERR_INVALID_PEER = 8,
  20205. /* add new error codes here */
  20206. HTT_RXDATA_ERR_MAX = 32
  20207. } htt_t2h_rx_data_msdu_err_e;
  20208. struct htt_t2h_rx_data_ind_t
  20209. {
  20210. A_UINT32 /* word 0 */
  20211. /* msg_type:
  20212. * Set to Rx data indication i.e. HTT_T2H_MSG_TYPE_RX_DATA_IND.
  20213. */
  20214. msg_type: 8,
  20215. peer_id: 16, /* This will provide peer data */
  20216. vdev_id: 8; /* This will provide vdev id info */
  20217. A_UINT32 /* word 1 */
  20218. /* msdu_cnt:
  20219. * Total number of MSDUs (htt_t2h_rx_data_msdu_info items) in message.
  20220. */
  20221. msdu_cnt: 8,
  20222. frag: 1, /* this bit will be set for 802.11 frag MPDU */
  20223. rsvd0: 23;
  20224. /* NOTE:
  20225. * To preserve backwards compatibility,
  20226. * no new fields can be added in this struct.
  20227. */
  20228. };
  20229. struct htt_t2h_rx_data_msdu_info
  20230. {
  20231. A_UINT32 /* word 0 */
  20232. buffer_addr_low : 32;
  20233. A_UINT32 /* word 1 */
  20234. buffer_addr_high : 8,
  20235. sw_buffer_cookie : 21,
  20236. /* fw_offloads_inspected:
  20237. * When reo_destination_indication is 6 in reo_entrance_ring
  20238. * of the RXDMA2REO MPDU upload, all the MSDUs that are part
  20239. * of the MPDU are inspected by FW offloads layer, subsequently
  20240. * the MSDUs are qualified to be host interested.
  20241. * In such case the fw_offloads_inspected is set to 1, else 0.
  20242. * This will assist host to not consider such MSDUs for FISA
  20243. * flow addition.
  20244. */
  20245. fw_offloads_inspected : 1,
  20246. rsvd1 : 2;
  20247. A_UINT32 /* word 2 */
  20248. mpdu_retry_bit : 1, /* used for stats maintenance */
  20249. raw_mpdu_frame : 1, /* used for pkt drop and processing */
  20250. first_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */
  20251. last_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */
  20252. msdu_continuation : 1, /* used for MSDU scatter/gather support */
  20253. sa_is_valid : 1, /* used for HW issue check in
  20254. * is_sa_da_idx_valid() */
  20255. da_is_valid : 1, /* used for HW issue check and
  20256. * intra-BSS forwarding */
  20257. da_is_mcbc : 1,
  20258. tid_info : 8, /* used for stats maintenance */
  20259. msdu_length : 14,
  20260. is_first_pkt_after_wkp : 1, /* indicates this is the first rx MSDU
  20261. * provided by fw after WoW exit */
  20262. rsvd2 : 1;
  20263. A_UINT32 /* word 3 */
  20264. error_valid : 1, /* Set if the MSDU has any error */
  20265. error_info : 5, /* If error_valid is TRUE, then refer to
  20266. * "htt_t2h_rx_data_msdu_err_e" for
  20267. * checking error reason. */
  20268. rsvd3 : 26;
  20269. /* NOTE:
  20270. * To preserve backwards compatibility,
  20271. * no new fields can be added in this struct.
  20272. */
  20273. };
  20274. /* HTT_RX_DATA_IND_HDR_SIZE: 2 4-byte words
  20275. * This is the size of htt_t2h_rx_data_ind_t alone which is fixed overhead
  20276. * for every Rx DATA IND sent by FW to host.
  20277. */
  20278. #define HTT_RX_DATA_IND_HDR_SIZE (2*4)
  20279. /* HTT_RX_DATA_MSDU_INFO_SIZE: 4 4-bytes words
  20280. * This is the size of each MSDU detail that will be piggybacked with the
  20281. * RX IND header.
  20282. */
  20283. #define HTT_RX_DATA_MSDU_INFO_SIZE (4*4)
  20284. /* member definitions of htt_t2h_rx_data_ind_t */
  20285. #define HTT_RX_DATA_IND_PEER_ID_M 0x00ffff00
  20286. #define HTT_RX_DATA_IND_PEER_ID_S 8
  20287. #define HTT_RX_DATA_IND_PEER_ID_SET(word, value) \
  20288. do { \
  20289. HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_PEER_ID, value); \
  20290. (word) |= (value) << HTT_RX_DATA_IND_PEER_ID_S; \
  20291. } while (0)
  20292. #define HTT_RX_DATA_IND_PEER_ID_GET(word) \
  20293. (((word) & HTT_RX_DATA_IND_PEER_ID_M) >> HTT_RX_DATA_IND_PEER_ID_S)
  20294. #define HTT_RX_DATA_IND_VDEV_ID_M 0xff000000
  20295. #define HTT_RX_DATA_IND_VDEV_ID_S 24
  20296. #define HTT_RX_DATA_IND_VDEV_ID_SET(word, value) \
  20297. do { \
  20298. HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_VDEV_ID, value); \
  20299. (word) |= (value) << HTT_RX_DATA_IND_VDEV_ID_S; \
  20300. } while (0)
  20301. #define HTT_RX_DATA_IND_VDEV_ID_GET(word) \
  20302. (((word) & HTT_RX_DATA_IND_VDEV_ID_M) >> HTT_RX_DATA_IND_VDEV_ID_S)
  20303. #define HTT_RX_DATA_IND_MSDU_CNT_M 0x000000ff
  20304. #define HTT_RX_DATA_IND_MSDU_CNT_S 0
  20305. #define HTT_RX_DATA_IND_MSDU_CNT_SET(word, value) \
  20306. do { \
  20307. HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_MSDU_CNT, value); \
  20308. (word) |= (value) << HTT_RX_DATA_IND_MSDU_CNT_S; \
  20309. } while (0)
  20310. #define HTT_RX_DATA_IND_MSDU_CNT_GET(word) \
  20311. (((word) & HTT_RX_DATA_IND_MSDU_CNT_M) >> HTT_RX_DATA_IND_MSDU_CNT_S)
  20312. #define HTT_RX_DATA_IND_FRAG_M 0x00000100
  20313. #define HTT_RX_DATA_IND_FRAG_S 8
  20314. #define HTT_RX_DATA_IND_FRAG_SET(word, value) \
  20315. do { \
  20316. HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_FRAG, value); \
  20317. (word) |= (value) << HTT_RX_DATA_IND_FRAG_S; \
  20318. } while (0)
  20319. #define HTT_RX_DATA_IND_FRAG_GET(word) \
  20320. (((word) & HTT_RX_DATA_IND_FRAG_M) >> HTT_RX_DATA_IND_FRAG_S)
  20321. /* member definitions of htt_t2h_rx_data_msdu_info */
  20322. #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M 0xFFFFFFFF
  20323. #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S 0
  20324. #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M 0x000000FF
  20325. #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S 0
  20326. #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_SET(word, value) \
  20327. do { \
  20328. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW, value); \
  20329. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S; \
  20330. } while (0)
  20331. #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_GET(word) \
  20332. (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S)
  20333. #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_SET(word, value) \
  20334. do { \
  20335. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH, value); \
  20336. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S; \
  20337. } while (0)
  20338. #define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_GET(word) \
  20339. (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S)
  20340. #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M 0x1FFFFF00
  20341. #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S 8
  20342. #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_SET(word, value) \
  20343. do { \
  20344. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE, value); \
  20345. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S; \
  20346. } while (0)
  20347. #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_GET(word) \
  20348. (((word) & HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M) >> HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S)
  20349. #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M 0x20000000
  20350. #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S 29
  20351. #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_SET(word, value) \
  20352. do { \
  20353. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED, value); \
  20354. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S; \
  20355. } while (0)
  20356. #define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_GET(word) \
  20357. (((word) & HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M) >> HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S)
  20358. #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M 0x00000001
  20359. #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S 0
  20360. #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_SET(word, value) \
  20361. do { \
  20362. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT, value); \
  20363. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S; \
  20364. } while (0)
  20365. #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_GET(word) \
  20366. (((word) & HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M) >> HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S)
  20367. #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M 0x00000002
  20368. #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S 1
  20369. #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_SET(word, value) \
  20370. do { \
  20371. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME, value); \
  20372. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S; \
  20373. } while (0)
  20374. #define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_GET(word) \
  20375. (((word) & HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M) >> HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S)
  20376. #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M 0x00000004
  20377. #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S 2
  20378. #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_SET(word, value) \
  20379. do { \
  20380. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU, value); \
  20381. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S; \
  20382. } while (0)
  20383. #define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_GET(word) \
  20384. (((word) & HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S)
  20385. #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M 0x00000008
  20386. #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S 3
  20387. #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_SET(word, value) \
  20388. do { \
  20389. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU, value); \
  20390. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S; \
  20391. } while (0)
  20392. #define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_GET(word) \
  20393. (((word) & HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S)
  20394. #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M 0x00000010
  20395. #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S 4
  20396. #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_SET(word, value) \
  20397. do { \
  20398. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION, value); \
  20399. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S; \
  20400. } while (0)
  20401. #define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_GET(word) \
  20402. (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S)
  20403. #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M 0x00000020
  20404. #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S 5
  20405. #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_SET(word, value) \
  20406. do { \
  20407. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SA_IS_VALID, value); \
  20408. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S; \
  20409. } while (0)
  20410. #define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_GET(word) \
  20411. (((word) & HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S)
  20412. #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M 0x00000040
  20413. #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S 6
  20414. #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_SET(word, value) \
  20415. do { \
  20416. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_VALID, value); \
  20417. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S; \
  20418. } while (0)
  20419. #define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_GET(word) \
  20420. (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S)
  20421. #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M 0x00000080
  20422. #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S 7
  20423. #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_SET(word, value) \
  20424. do { \
  20425. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC, value); \
  20426. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S; \
  20427. } while (0)
  20428. #define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_GET(word) \
  20429. (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S)
  20430. #define HTT_RX_DATA_MSDU_INFO_TID_INFO_M 0x0000FF00
  20431. #define HTT_RX_DATA_MSDU_INFO_TID_INFO_S 8
  20432. #define HTT_RX_DATA_MSDU_INFO_TID_INFO_SET(word, value) \
  20433. do { \
  20434. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_TID_INFO, value); \
  20435. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_TID_INFO_S; \
  20436. } while (0)
  20437. #define HTT_RX_DATA_MSDU_INFO_TID_INFO_GET(word) \
  20438. (((word) & HTT_RX_DATA_MSDU_INFO_TID_INFO_M) >> HTT_RX_DATA_MSDU_INFO_TID_INFO_S)
  20439. #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M 0x3FFF0000
  20440. #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S 16
  20441. #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_SET(word, value) \
  20442. do { \
  20443. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH, value); \
  20444. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S; \
  20445. } while (0)
  20446. #define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_GET(word) \
  20447. (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S)
  20448. #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M 0x40000000
  20449. #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S 30
  20450. #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_SET(word, value) \
  20451. do { \
  20452. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP, value); \
  20453. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S; \
  20454. } while (0)
  20455. #define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_GET(word) \
  20456. (((word) & HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M) >> HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S)
  20457. #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M 0x00000001
  20458. #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S 0
  20459. #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_SET(word, value) \
  20460. do { \
  20461. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_VALID, value); \
  20462. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S; \
  20463. } while (0)
  20464. #define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_GET(word) \
  20465. (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S)
  20466. #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M 0x0000001E
  20467. #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S 1
  20468. #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_SET(word, value) \
  20469. do { \
  20470. HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_INFO, value); \
  20471. (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S; \
  20472. } while (0)
  20473. #define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_GET(word) \
  20474. (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S)
  20475. /**
  20476. * @brief target -> Primary peer migration message to host
  20477. *
  20478. * MSG_TYPE => HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND
  20479. *
  20480. * @details
  20481. * HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND message is sent by target
  20482. * to host to flush & set-up the RX rings to new primary peer
  20483. *
  20484. * The message would appear as follows:
  20485. *
  20486. * |31 16|15 12|11 8|7 0|
  20487. * |-------------------------------+---------+---------+--------------|
  20488. * | vdev ID | pdev ID | chip ID | msg type |
  20489. * |-------------------------------+---------+---------+--------------|
  20490. * | ML peer ID | SW peer ID |
  20491. * |-------------------------------+----------------------------------|
  20492. *
  20493. * The message is interpreted as follows:
  20494. * dword0 - b'0:7 - msg_type: This will be set to 0x37
  20495. * (HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND)
  20496. * b'8:11 - chip_id: Indicate which chip has been chosen as primary
  20497. * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen
  20498. * as primary
  20499. * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen
  20500. * as primary
  20501. *
  20502. * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer
  20503. * chosen as primary
  20504. * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the
  20505. * primary peer belongs.
  20506. */
  20507. typedef struct {
  20508. A_UINT32 msg_type: 8, /* bits 7:0 */
  20509. chip_id: 4, /* bits 11:8 */
  20510. pdev_id: 4, /* bits 15:12 */
  20511. vdev_id: 16; /* bits 31:16 */
  20512. A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */
  20513. ml_peer_id: 16; /* bits 31:16 */
  20514. } htt_t2h_primary_link_peer_migrate_ind_t;
  20515. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00
  20516. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8
  20517. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \
  20518. (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \
  20519. HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S)
  20520. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \
  20521. do { \
  20522. HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \
  20523. ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\
  20524. } while (0)
  20525. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000
  20526. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12
  20527. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \
  20528. (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \
  20529. HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S)
  20530. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \
  20531. do { \
  20532. HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \
  20533. ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\
  20534. } while (0)
  20535. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000
  20536. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16
  20537. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \
  20538. (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \
  20539. HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S)
  20540. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \
  20541. do { \
  20542. HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \
  20543. ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\
  20544. } while (0)
  20545. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF
  20546. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0
  20547. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \
  20548. (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \
  20549. HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S)
  20550. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \
  20551. do { \
  20552. HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \
  20553. ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\
  20554. } while (0)
  20555. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000
  20556. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16
  20557. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \
  20558. (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \
  20559. HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S)
  20560. #define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \
  20561. do { \
  20562. HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \
  20563. ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\
  20564. } while (0)
  20565. /**
  20566. * @brief target -> host rx peer AST override message defenition
  20567. *
  20568. * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND
  20569. *
  20570. * @details
  20571. * Format inherits parts of the HTT_T2H_MSG_TYPE_PEER_MAP_V3 published above
  20572. * where in the dummy ast index is provided to the host.
  20573. * This new message below is sent to the host at run time from the TX_DE
  20574. * exception path when a SAWF flow is detected for a peer.
  20575. * This is sent up once per SAWF peer.
  20576. * This layout assumes the target operates as little-endian.
  20577. *
  20578. * |31 24|23 16|15 8|7 0|
  20579. * |--------------------------------------+-----------------+-----------------|
  20580. * | SW peer ID | vdev ID | msg type |
  20581. * |-----------------+--------------------+-----------------+-----------------|
  20582. * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
  20583. * |-----------------+--------------------+-----------------+-----------------|
  20584. * | dummy AST Index #1 | MAC addr 5 | MAC addr 4 |
  20585. * |--------------------------------------+-----------------+-----------------|
  20586. * | reserved | dummy AST Index #2 |
  20587. * |--------------------------------------+-----------------------------------|
  20588. *
  20589. * The following field definitions describe the format of the peer ast override
  20590. * index messages sent from the target to the host.
  20591. * - MSG_TYPE
  20592. * Bits 7:0
  20593. * Purpose: identifies this as a peer map v3 message
  20594. * Value: 0x38 (HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND)
  20595. * - VDEV_ID
  20596. * Bits 15:8
  20597. * Purpose: Indicates which virtual device the peer is associated with.
  20598. * - SW_PEER_ID
  20599. * Bits 31:16
  20600. * Purpose: The peer ID (index) that WAL has allocated for this peer.
  20601. * - MAC_ADDR_L32
  20602. * Bits 31:0
  20603. * Purpose: Identifies which peer node the peer ID is for.
  20604. * Value: lower 4 bytes of peer node's MAC address
  20605. * - MAC_ADDR_U16
  20606. * Bits 15:0
  20607. * Purpose: Identifies which peer node the peer ID is for.
  20608. * Value: upper 2 bytes of peer node's MAC address
  20609. * - AST_INDEX1
  20610. * Bits 31:16
  20611. * Purpose: The 1st extra AST index used to identify user defined MSDUQ
  20612. * - AST_INDEX2
  20613. * Bits 15:0
  20614. * Purpose: The 2nd extra AST index used to identify user defined MSDUQ
  20615. */
  20616. /* dword 0 */
  20617. #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M 0xffff0000
  20618. #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S 16
  20619. #define HTT_PEER_AST_OVERRIDE_VDEV_ID_M 0x0000ff00
  20620. #define HTT_PEER_AST_OVERRIDE_VDEV_ID_S 8
  20621. /* dword 1 */
  20622. #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M 0xffffffff
  20623. #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S 0
  20624. /* dword 2 */
  20625. #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M 0x0000ffff
  20626. #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S 0
  20627. #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_M 0xffff0000
  20628. #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_S 16
  20629. /* dword 3 */
  20630. #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_M 0x0000ffff
  20631. #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_S 0
  20632. #define HTT_PEER_AST_OVERRIDE_VDEV_ID_SET(word, value) \
  20633. do { \
  20634. HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_VDEV_ID, value); \
  20635. (word) |= (value) << HTT_PEER_AST_OVERRIDE_VDEV_ID_S; \
  20636. } while (0)
  20637. #define HTT_PEER_AST_OVERRIDE_VDEV_ID_GET(word) \
  20638. (((word) & HTT_PEER_AST_OVERRIDE_VDEV_ID_M) >> HTT_PEER_AST_OVERRIDE_VDEV_ID_S)
  20639. #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_SET(word, value) \
  20640. do { \
  20641. HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_SW_PEER_ID, value); \
  20642. (word) |= (value) << HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S; \
  20643. } while (0)
  20644. #define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_GET(word) \
  20645. (((word) & HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M) >> HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S)
  20646. #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_SET(word, value) \
  20647. do { \
  20648. HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32, value); \
  20649. (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S; \
  20650. } while (0)
  20651. #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_GET(word) \
  20652. (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S)
  20653. #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_SET(word, value) \
  20654. do { \
  20655. HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16, value); \
  20656. (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S; \
  20657. } while (0)
  20658. #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_GET(word) \
  20659. (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S)
  20660. #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_SET(word, value) \
  20661. do { \
  20662. HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX1, value); \
  20663. (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX1_S; \
  20664. } while (0)
  20665. #define HTT_PEER_AST_OVERRIDE_AST_INDEX1_GET(word) \
  20666. (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX1_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX1_S)
  20667. #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_SET(word, value) \
  20668. do { \
  20669. HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX2, value); \
  20670. (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX2_S; \
  20671. } while (0)
  20672. #define HTT_PEER_AST_OVERRIDE_AST_INDEX2_GET(word) \
  20673. (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX2_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX2_S)
  20674. #define HTT_PEER_AST_OVERRIDE_MAC_ADDR_WORD_BASE_OFFSET 4 /* bytes */
  20675. #define HTT_PEER_AST_OVERRIDE_DUMMY_AST1_WORD_BASE_OFFSET 8 /* bytes */
  20676. #define HTT_PEER_AST_OVERRIDE_DUMMY_AST2_WORD_BASE_OFFSET 12 /* bytes */
  20677. #define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES 16
  20678. /**
  20679. * @brief target -> periodic report of tx latency to host
  20680. *
  20681. * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND
  20682. *
  20683. * @details
  20684. * The message starts with a message header followed by one or more
  20685. * htt_t2h_peer_tx_latency_stats structs, one for each peer within the vdev.
  20686. * After each upload, these tx latency stats will be reset.
  20687. *
  20688. * |31 24|23 16|15 14|13 10|9 8|7 0|
  20689. * +-------------------------+-----+-----+---+----------|
  20690. * hdr | |pyld elem sz| | GR | P | msg type |
  20691. *- -|=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
  20692. * pyld | peer ID |
  20693. * |----------------------------------------------------|
  20694. * | peer_tx_latency[0] |
  20695. * |----------------------------------------------------|
  20696. * 1st | peer_tx_latency[1] |
  20697. * peer |----------------------------------------------------|
  20698. * | peer_tx_latency[2] |
  20699. * |----------------------------------------------------|
  20700. * | peer_tx_latency[3] |
  20701. * |----------------------------------------------------|
  20702. * | avg latency |
  20703. * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
  20704. * | peer ID |
  20705. * |----------------------------------------------------|
  20706. * | peer_tx_latency[0] |
  20707. * |----------------------------------------------------|
  20708. * 2nd | peer_tx_latency[1] |
  20709. * peer |----------------------------------------------------|
  20710. * | peer_tx_latency[2] |
  20711. * |----------------------------------------------------|
  20712. * | peer_tx_latency[3] |
  20713. * |----------------------------------------------------|
  20714. * | avg latency |
  20715. * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
  20716. * Where:
  20717. * P = pdev ID
  20718. * GR = granularity
  20719. *
  20720. * @details
  20721. * htt_t2h_tx_latency_stats_periodic_hdr_t:
  20722. * - msg_type
  20723. * Bits 7:0
  20724. * Purpose: identifies this as a tx latency report message
  20725. * Value: 0x3a (HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND)
  20726. * - pdev_id
  20727. * Bits 9:8
  20728. * Purpose: Indicates which pdev this message is associated with.
  20729. * - granularity
  20730. * Bits 13:10
  20731. * Purpose: specifies the granulairty of each tx latency bucket in MS.
  20732. * There are 4 buckets in total. E.g. if granularity is set to 5 ms,
  20733. * then the ranges for the 4 latency histogram buckets will be
  20734. * 0-5ms, 5ms-10ms, 10ms-15ms, 15ms-max, respectively.
  20735. * - payload_elem_size
  20736. * Bits 23:16
  20737. * Purpose: specifies the size of each element within the msg's payload
  20738. * In other words, this field specified the value of
  20739. * sizeof(htt_t2h_peer_tx_latency_stats) based on the target's
  20740. * revision of the htt_t2h_peer_tx_latency_stats definition.
  20741. * If the payload_elem_size reported in the message exceeds the
  20742. * sizeof(htt_t2h_peer_tx_latency_stats) based on the host's
  20743. * revision of the htt_t2h_peer_tx_latency_stats definition,
  20744. * the host shall ignore the excess data.
  20745. * Conversely, if the payload_elem_size reported in the message is
  20746. * less than sizeof(htt_t2h_peer_tx_latency_stats) based on the host's
  20747. * revision of the htt_t2h_peer_tx_latency_stats definition,
  20748. * the host shall use 0x0 values for the portion of the data not
  20749. * provided by the target.
  20750. * The host can compare the payload_elem_size to the total size of
  20751. * the message minus the size of the message header to determine
  20752. * how many peer payload elements are present in the message.
  20753. * - sw_peer_id
  20754. * Purpose: The peer to which the following stats belong
  20755. * - peer_tx_latency
  20756. * Purpose: tx latency histogram for this peer, with 4 buckets whose
  20757. * size (in milliseconds) is specified by the granularity field
  20758. * - avg_latency
  20759. * Purpose: average tx latency (in ms) for this peer in this report interval
  20760. */
  20761. typedef struct {
  20762. A_UINT32 msg_type: 8,
  20763. pdev_id: 2,
  20764. granularity: 4,
  20765. reserved1: 2,
  20766. payload_elem_size: 8,
  20767. reserved2: 8;
  20768. } htt_t2h_tx_latency_stats_periodic_hdr_t;
  20769. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_HDR_SIZE \
  20770. (sizeof(htt_t2h_tx_latency_stats_periodic_hdr_t))
  20771. #define HTT_PEER_TX_LATENCY_REPORT_BINS 4
  20772. typedef struct _htt_tx_latency_stats {
  20773. A_UINT32 peer_id;
  20774. A_UINT32 peer_tx_latency[HTT_PEER_TX_LATENCY_REPORT_BINS];
  20775. A_UINT32 avg_latency;
  20776. } htt_t2h_peer_tx_latency_stats;
  20777. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M 0x00000300
  20778. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S 8
  20779. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \
  20780. (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)
  20781. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \
  20782. do { \
  20783. HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID, _val); \
  20784. ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)); \
  20785. } while (0)
  20786. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M 0x00003C00
  20787. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S 10
  20788. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_GET(_var) \
  20789. (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)
  20790. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_SET(_var, _val) \
  20791. do { \
  20792. HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY, _val); \
  20793. ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \
  20794. } while (0)
  20795. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M 0x00FF0000
  20796. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S 16
  20797. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \
  20798. (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)
  20799. #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_SET(_var, _val) \
  20800. do { \
  20801. HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE, _val); \
  20802. ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)); \
  20803. } while (0)
  20804. /**
  20805. * @brief target -> host report showing MSDU queue configuration
  20806. *
  20807. * MSG_TYPE => HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND
  20808. *
  20809. * @details
  20810. *
  20811. * |31 24|23 16|15|14 11|10|9 8|7 0|
  20812. * |----------------+----------------+--+-----+--+---+----------------------|
  20813. * | peer_id | htt_qtype | msg type |
  20814. * |----------------+----------------+--+-----+--+---+----------+-----------|
  20815. * | error_code | svc_class_id | R| AST | F|WHO| hlos_tid | remap_tid |
  20816. * |----------------+----------------+--+-----+--+---+----------+-----------|
  20817. * | request_cookie | tgt_opaque_msduq_id |
  20818. * |------------------------------------------------------------------------|
  20819. * Where WHO = who_classify_info_sel
  20820. * F = flow_override
  20821. * AST = ast_list_idx
  20822. * R = reserved
  20823. *
  20824. * @details
  20825. * htt_t2h_msg_type_sdwf_msduq_cfg_ind_t:
  20826. *
  20827. * The message is interpreted as follows:
  20828. * dword0 - b'7:0 - msg_type: Identifies this as a MSDU queue cfg indication
  20829. * This will be set to 0x3c
  20830. * (HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND)
  20831. * b'15:8 - HTT qtype (refer to HTT_MSDU_QTYPE)
  20832. * b'31:16 - peer ID
  20833. *
  20834. * dword1 - b'3:0 - remap TID, as assigned in firmware
  20835. * b'7:4 - HLOS TID, as sent by host in TCL Data Command
  20836. * hlos_tid : Common to Lithium and Beryllium
  20837. * b'9:8 - who_classify_info_sel (WWHO, as sent by host in
  20838. * TCL Data Command : Beryllium
  20839. * b'10:10 - flow_override (F), as sent by host in
  20840. * TCL Data Command: Beryllium
  20841. * b'14:11 - ast_list_idx (AST)
  20842. * Array index into the list of extension AST entries
  20843. * (not the actual AST 16-bit index).
  20844. * The ast_list_idx is one-based, with the following
  20845. * range of values:
  20846. * - legacy targets supporting 16 user-defined
  20847. * MSDU queues: 1-2
  20848. * - legacy targets supporting 48 user-defined
  20849. * MSDU queues: 1-6
  20850. * - new targets: 0 (peer_id is used instead)
  20851. * Note that since ast_list_idx is one-based,
  20852. * the host will need to subtract 1 to use it as an
  20853. * index into a list of extension AST entries.
  20854. * b'15:15 - reserved
  20855. * b'23:16 - svc_class_id
  20856. * b'31:24 - error_code
  20857. *
  20858. * dword2 - b'23:0 - tgt_opaque_msduq_id: tx flow number that uniquely
  20859. * identifies the MSDU queue
  20860. * b'24:31 - request_cookie: Identifies which H2T SDWF_MSDUQ_RECFG_REQ
  20861. * request triggered this indication.
  20862. * This will be set to HTT_MSDUQ_CFG_REG_COOKIE_INVALID
  20863. * (0xFF) in any cases when the FW generates this
  20864. * indication autonomously rather than in response to
  20865. * a SDWF_MSDUQ_RECFG_REQ message from the host.
  20866. *
  20867. * The behavior of this indication is as follows:
  20868. * - svc_class_id is set to the service class that the specified MSDUQ is
  20869. * currently linked to.
  20870. * - error_code is set to a defined code if any errors arise.
  20871. * Otherwise a value of 0x00 (ERROR_NONE) indicates success.
  20872. */
  20873. /* HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND */
  20874. typedef enum {
  20875. HTT_SDWF_MSDUQ_CFG_IND_ERROR_NONE = 0x00,
  20876. HTT_SDWF_MSDUQ_CFG_IND_ERROR_PEER_DELETE_IN_PROG = 0x01,
  20877. HTT_SDWF_MSDUQ_CFG_IND_ERROR_SW_MSDUQ_NULL = 0x02,
  20878. HTT_SDWF_MSDUQ_CFG_IND_ERROR_MSDUQ_LOCATE_ERROR = 0x03,
  20879. HTT_SDWF_MSDUQ_CFG_IND_ERROR_QPEER_NULL = 0x04,
  20880. HTT_SDWF_MSDUQ_CFG_IND_ERROR_DEACTIVATED_MSDUQ = 0x05,
  20881. HTT_SDWF_MSDUQ_CFG_IND_ERROR_REACTIVATED_MSDUQ = 0x06,
  20882. HTT_SDWF_MSDUQ_CFG_IND_ERROR_INVALID_SVC_CLASS = 0x07,
  20883. HTT_SDWF_MSDUQ_CFG_IND_ERROR_TIDQ_LOCATE_ERROR = 0x08,
  20884. } HTT_SDWF_MSDUQ_CFG_IND_ERROR_CODE_E;
  20885. PREPACK struct htt_t2h_sdwf_msduq_cfg_ind {
  20886. A_UINT32 msg_type: 8, /* bits 7:0 */
  20887. htt_qtype: 8, /* bits 15:8 */
  20888. peer_id: 16; /* bits 31:16 */
  20889. A_UINT32 remap_tid: 4, /* bits 3:0 */
  20890. hlos_tid: 4, /* bits 7:4 */
  20891. who_classify_info_sel: 2, /* bits 9:8 */
  20892. flow_override: 1, /* bits 10:10 */
  20893. ast_list_idx: 4, /* bits 14:11 */
  20894. reserved: 1, /* bits 15:15 */
  20895. svc_class_id: 8, /* bits 23:16 */
  20896. error_code: 8; /* bits 31:24 */
  20897. A_UINT32 tgt_opaque_msduq_id: 24, /* bits 23:0 */
  20898. request_cookie: 8; /* bits 31:24 */
  20899. } POSTPACK;
  20900. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_M 0x0000FF00
  20901. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_S 8
  20902. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_GET(_var) \
  20903. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_M) >> \
  20904. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_S)
  20905. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_SET(_var, _val) \
  20906. do { \
  20907. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE, _val); \
  20908. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HTT_QTYPE_S)); \
  20909. } while (0)
  20910. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_M 0xFFFF0000
  20911. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_S 16
  20912. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_GET(_var) \
  20913. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_M) >> \
  20914. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_S)
  20915. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_SET(_var, _val) \
  20916. do { \
  20917. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID, _val); \
  20918. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_PEER_ID_S)); \
  20919. } while (0)
  20920. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_M 0x0000000F
  20921. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_S 0
  20922. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_GET(_var) \
  20923. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_M) >> \
  20924. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_S)
  20925. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_SET(_var, _val) \
  20926. do { \
  20927. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID, _val); \
  20928. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REMAP_TID_S)); \
  20929. } while (0)
  20930. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_M 0x000000F0
  20931. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_S 4
  20932. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_GET(_var) \
  20933. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_M) >> \
  20934. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_S)
  20935. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_SET(_var, _val) \
  20936. do { \
  20937. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID, _val); \
  20938. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_HLOS_TID_S)); \
  20939. } while (0)
  20940. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_M 0x00000300
  20941. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_S 8
  20942. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_GET(_var) \
  20943. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_M) >> \
  20944. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_S)
  20945. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_SET(_var, _val) \
  20946. do { \
  20947. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO, _val); \
  20948. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_WHO_CLASSIFY_INFO_S)); \
  20949. } while (0)
  20950. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_M 0x00000400
  20951. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_S 10
  20952. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_GET(_var) \
  20953. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_M) >> \
  20954. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_S)
  20955. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_SET(_var, _val) \
  20956. do { \
  20957. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE, _val); \
  20958. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_FLOW_OVERRIDE_S)); \
  20959. } while (0)
  20960. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_M 0x00007800
  20961. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_S 11
  20962. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_GET(_var) \
  20963. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_M) >> \
  20964. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_S)
  20965. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_SET(_var, _val) \
  20966. do { \
  20967. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX, _val); \
  20968. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_AST_LIST_IDX_S)); \
  20969. } while (0)
  20970. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_M 0x00FF0000
  20971. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_S 16
  20972. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_GET(_var) \
  20973. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_M) >> \
  20974. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_S)
  20975. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_SET(_var, _val) \
  20976. do { \
  20977. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID, _val); \
  20978. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_SVC_CLASS_ID_S)); \
  20979. } while (0)
  20980. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_M 0xFF000000
  20981. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_S 24
  20982. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_GET(_var) \
  20983. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_M) >> \
  20984. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_S)
  20985. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_SET(_var, _val) \
  20986. do { \
  20987. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE, _val); \
  20988. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_ERROR_CODE_S)); \
  20989. } while (0)
  20990. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_M 0x00FFFFFF
  20991. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_S 0
  20992. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_GET(_var) \
  20993. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_M) >> \
  20994. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_S)
  20995. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_SET(_var, _val) \
  20996. do { \
  20997. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID, _val); \
  20998. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_TGT_OPAQUE_MSDUQ_ID_S)); \
  20999. } while (0)
  21000. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_M 0xFF000000
  21001. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_S 24
  21002. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_GET(_var) \
  21003. (((_var) & HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_M) >> \
  21004. HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_S)
  21005. #define HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_SET(_var, _val) \
  21006. do { \
  21007. HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE, _val); \
  21008. ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_S)); \
  21009. } while (0)
  21010. #endif