dp_ctrl.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/types.h>
  7. #include <linux/completion.h>
  8. #include <linux/delay.h>
  9. #include <drm/drm_fixed.h>
  10. #include <linux/version.h>
  11. #include "dp_ctrl.h"
  12. #include "dp_debug.h"
  13. #include "sde_dbg.h"
  14. #define DP_MST_DEBUG(fmt, ...) DP_DEBUG(fmt, ##__VA_ARGS__)
  15. #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
  16. #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
  17. #define DP_CTRL_INTR_MST_DP0_VCPF_SENT BIT(0)
  18. #define DP_CTRL_INTR_MST_DP1_VCPF_SENT BIT(3)
  19. /* dp state ctrl */
  20. #define ST_TRAIN_PATTERN_1 BIT(0)
  21. #define ST_TRAIN_PATTERN_2 BIT(1)
  22. #define ST_TRAIN_PATTERN_3 BIT(2)
  23. #define ST_TRAIN_PATTERN_4 BIT(3)
  24. #define ST_SYMBOL_ERR_RATE_MEASUREMENT BIT(4)
  25. #define ST_PRBS7 BIT(5)
  26. #define ST_CUSTOM_80_BIT_PATTERN BIT(6)
  27. #define ST_SEND_VIDEO BIT(7)
  28. #define ST_PUSH_IDLE BIT(8)
  29. #define MST_DP0_PUSH_VCPF BIT(12)
  30. #define MST_DP0_FORCE_VCPF BIT(13)
  31. #define MST_DP1_PUSH_VCPF BIT(14)
  32. #define MST_DP1_FORCE_VCPF BIT(15)
  33. #define MR_LINK_TRAINING1 0x8
  34. #define MR_LINK_SYMBOL_ERM 0x80
  35. #define MR_LINK_PRBS7 0x100
  36. #define MR_LINK_CUSTOM80 0x200
  37. #define MR_LINK_TRAINING4 0x40
  38. #define DP_MAX_LANES 4
  39. struct dp_mst_ch_slot_info {
  40. u32 start_slot;
  41. u32 tot_slots;
  42. };
  43. struct dp_mst_channel_info {
  44. struct dp_mst_ch_slot_info slot_info[DP_STREAM_MAX];
  45. };
  46. struct dp_ctrl_private {
  47. struct dp_ctrl dp_ctrl;
  48. struct device *dev;
  49. struct dp_aux *aux;
  50. struct dp_panel *panel;
  51. struct dp_link *link;
  52. struct dp_power *power;
  53. struct dp_parser *parser;
  54. struct dp_catalog_ctrl *catalog;
  55. struct dp_pll *pll;
  56. struct completion idle_comp;
  57. struct completion video_comp;
  58. bool orientation;
  59. bool power_on;
  60. bool mst_mode;
  61. bool fec_mode;
  62. bool dsc_mode;
  63. bool sim_mode;
  64. atomic_t aborted;
  65. u8 initial_lane_count;
  66. u8 initial_bw_code;
  67. u32 vic;
  68. u32 stream_count;
  69. u32 training_2_pattern;
  70. struct dp_mst_channel_info mst_ch_info;
  71. };
  72. enum notification_status {
  73. NOTIFY_UNKNOWN,
  74. NOTIFY_CONNECT,
  75. NOTIFY_DISCONNECT,
  76. NOTIFY_CONNECT_IRQ_HPD,
  77. NOTIFY_DISCONNECT_IRQ_HPD,
  78. };
  79. static void dp_ctrl_idle_patterns_sent(struct dp_ctrl_private *ctrl)
  80. {
  81. complete(&ctrl->idle_comp);
  82. }
  83. static void dp_ctrl_video_ready(struct dp_ctrl_private *ctrl)
  84. {
  85. complete(&ctrl->video_comp);
  86. }
  87. static void dp_ctrl_abort(struct dp_ctrl *dp_ctrl, bool abort)
  88. {
  89. struct dp_ctrl_private *ctrl;
  90. if (!dp_ctrl) {
  91. DP_ERR("Invalid input data\n");
  92. return;
  93. }
  94. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  95. atomic_set(&ctrl->aborted, abort);
  96. }
  97. static void dp_ctrl_state_ctrl(struct dp_ctrl_private *ctrl, u32 state)
  98. {
  99. ctrl->catalog->state_ctrl(ctrl->catalog, state);
  100. }
  101. static void dp_ctrl_push_idle(struct dp_ctrl_private *ctrl,
  102. enum dp_stream_id strm)
  103. {
  104. int const idle_pattern_completion_timeout_ms = HZ / 10;
  105. u32 state = 0x0;
  106. if (!ctrl->power_on)
  107. return;
  108. if (!ctrl->mst_mode) {
  109. state = ST_PUSH_IDLE;
  110. goto trigger_idle;
  111. }
  112. if (strm >= DP_STREAM_MAX) {
  113. DP_ERR("mst push idle, invalid stream:%d\n", strm);
  114. return;
  115. }
  116. state |= (strm == DP_STREAM_0) ? MST_DP0_PUSH_VCPF : MST_DP1_PUSH_VCPF;
  117. trigger_idle:
  118. reinit_completion(&ctrl->idle_comp);
  119. dp_ctrl_state_ctrl(ctrl, state);
  120. if (!wait_for_completion_timeout(&ctrl->idle_comp,
  121. idle_pattern_completion_timeout_ms))
  122. DP_WARN("time out\n");
  123. else
  124. DP_DEBUG("mainlink off done\n");
  125. }
  126. /**
  127. * dp_ctrl_configure_source_link_params() - configures DP TX source params
  128. * @ctrl: Display Port Driver data
  129. * @enable: enable or disable DP transmitter
  130. *
  131. * Configures the DP transmitter source params including details such as lane
  132. * configuration, output format and sink/panel timing information.
  133. */
  134. static void dp_ctrl_configure_source_link_params(struct dp_ctrl_private *ctrl,
  135. bool enable)
  136. {
  137. if (!ctrl->power->clk_status(ctrl->power, DP_LINK_PM)) {
  138. DP_WARN("DP link clocks are off\n");
  139. return;
  140. }
  141. if (!ctrl->power->clk_status(ctrl->power, DP_CORE_PM)) {
  142. DP_WARN("DP core clocks are off\n");
  143. return;
  144. }
  145. if (enable) {
  146. ctrl->catalog->lane_mapping(ctrl->catalog, ctrl->orientation,
  147. ctrl->parser->l_map);
  148. ctrl->catalog->lane_pnswap(ctrl->catalog,
  149. ctrl->parser->l_pnswap);
  150. ctrl->catalog->mst_config(ctrl->catalog, ctrl->mst_mode);
  151. ctrl->catalog->config_ctrl(ctrl->catalog,
  152. ctrl->link->link_params.lane_count);
  153. ctrl->catalog->mainlink_levels(ctrl->catalog,
  154. ctrl->link->link_params.lane_count);
  155. ctrl->catalog->mainlink_ctrl(ctrl->catalog, true);
  156. } else {
  157. ctrl->catalog->mainlink_ctrl(ctrl->catalog, false);
  158. }
  159. }
  160. static void dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
  161. {
  162. if (!wait_for_completion_timeout(&ctrl->video_comp, HZ / 2))
  163. DP_WARN("SEND_VIDEO time out\n");
  164. else
  165. DP_DEBUG("SEND_VIDEO triggered\n");
  166. }
  167. static int dp_ctrl_update_sink_vx_px(struct dp_ctrl_private *ctrl)
  168. {
  169. int i, ret;
  170. u8 buf[DP_MAX_LANES];
  171. u8 v_level = ctrl->link->phy_params.v_level;
  172. u8 p_level = ctrl->link->phy_params.p_level;
  173. u8 size = min_t(u8, sizeof(buf), ctrl->link->link_params.lane_count);
  174. u32 max_level_reached = 0;
  175. if (v_level == ctrl->link->phy_params.max_v_level) {
  176. DP_DEBUG("max voltage swing level reached %d\n", v_level);
  177. max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
  178. }
  179. if (p_level == ctrl->link->phy_params.max_p_level) {
  180. DP_DEBUG("max pre-emphasis level reached %d\n", p_level);
  181. max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  182. }
  183. p_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
  184. for (i = 0; i < size; i++)
  185. buf[i] = v_level | p_level | max_level_reached;
  186. DP_DEBUG("lanes: %d, swing: 0x%x, pre-emp: 0x%x\n",
  187. size, v_level, p_level);
  188. ret = drm_dp_dpcd_write(ctrl->aux->drm_aux,
  189. DP_TRAINING_LANE0_SET, buf, size);
  190. return ret <= 0 ? -EINVAL : 0;
  191. }
  192. static void dp_ctrl_update_hw_vx_px(struct dp_ctrl_private *ctrl)
  193. {
  194. struct dp_link *link = ctrl->link;
  195. bool high = false;
  196. if (ctrl->link->link_params.bw_code == DP_LINK_BW_5_4 ||
  197. ctrl->link->link_params.bw_code == DP_LINK_BW_8_1)
  198. high = true;
  199. ctrl->catalog->update_vx_px(ctrl->catalog,
  200. link->phy_params.v_level, link->phy_params.p_level, high);
  201. }
  202. static int dp_ctrl_update_sink_pattern(struct dp_ctrl_private *ctrl, u8 pattern)
  203. {
  204. u8 buf = pattern;
  205. int ret;
  206. DP_DEBUG("sink: pattern=%x\n", pattern);
  207. if (pattern && pattern != DP_TRAINING_PATTERN_4)
  208. buf |= DP_LINK_SCRAMBLING_DISABLE;
  209. ret = drm_dp_dpcd_writeb(ctrl->aux->drm_aux,
  210. DP_TRAINING_PATTERN_SET, buf);
  211. return ret <= 0 ? -EINVAL : 0;
  212. }
  213. static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
  214. u8 *link_status)
  215. {
  216. int ret = 0, len;
  217. u32 const offset = DP_LANE_ALIGN_STATUS_UPDATED - DP_LANE0_1_STATUS;
  218. u32 link_status_read_max_retries = 100;
  219. while (--link_status_read_max_retries) {
  220. len = drm_dp_dpcd_read_link_status(ctrl->aux->drm_aux,
  221. link_status);
  222. if (len != DP_LINK_STATUS_SIZE) {
  223. DP_ERR("DP link status read failed, err: %d\n", len);
  224. ret = len;
  225. break;
  226. }
  227. if (!(link_status[offset] & DP_LINK_STATUS_UPDATED))
  228. break;
  229. }
  230. return ret;
  231. }
  232. static int dp_ctrl_lane_count_down_shift(struct dp_ctrl_private *ctrl)
  233. {
  234. int ret = -EAGAIN;
  235. u8 lanes = ctrl->link->link_params.lane_count;
  236. if (ctrl->panel->link_info.revision != 0x14)
  237. return -EINVAL;
  238. switch (lanes) {
  239. case 4:
  240. ctrl->link->link_params.lane_count = 2;
  241. break;
  242. case 2:
  243. ctrl->link->link_params.lane_count = 1;
  244. break;
  245. default:
  246. if (lanes != ctrl->initial_lane_count)
  247. ret = -EINVAL;
  248. break;
  249. }
  250. DP_DEBUG("new lane count=%d\n", ctrl->link->link_params.lane_count);
  251. return ret;
  252. }
  253. static bool dp_ctrl_is_link_rate_rbr(struct dp_ctrl_private *ctrl)
  254. {
  255. return ctrl->link->link_params.bw_code == DP_LINK_BW_1_62;
  256. }
  257. static u8 dp_ctrl_get_active_lanes(struct dp_ctrl_private *ctrl,
  258. u8 *link_status)
  259. {
  260. u8 lane, count = 0;
  261. for (lane = 0; lane < ctrl->link->link_params.lane_count; lane++) {
  262. if (link_status[lane / 2] & (1 << (lane * 4)))
  263. count++;
  264. else
  265. break;
  266. }
  267. return count;
  268. }
  269. static int dp_ctrl_link_training_1(struct dp_ctrl_private *ctrl)
  270. {
  271. int tries, old_v_level, ret = -EINVAL;
  272. u8 link_status[DP_LINK_STATUS_SIZE];
  273. u8 pattern = 0;
  274. int const maximum_retries = 5;
  275. ctrl->aux->state &= ~DP_STATE_TRAIN_1_FAILED;
  276. ctrl->aux->state &= ~DP_STATE_TRAIN_1_SUCCEEDED;
  277. ctrl->aux->state |= DP_STATE_TRAIN_1_STARTED;
  278. if (ctrl->sim_mode) {
  279. DP_DEBUG("simulation enabled, skip clock recovery\n");
  280. ret = 0;
  281. goto skip_training;
  282. }
  283. dp_ctrl_state_ctrl(ctrl, 0);
  284. /* Make sure to clear the current pattern before starting a new one */
  285. wmb();
  286. tries = 0;
  287. old_v_level = ctrl->link->phy_params.v_level;
  288. while (!atomic_read(&ctrl->aborted)) {
  289. /* update hardware with current swing/pre-emp values */
  290. dp_ctrl_update_hw_vx_px(ctrl);
  291. if (!pattern) {
  292. pattern = DP_TRAINING_PATTERN_1;
  293. ctrl->catalog->set_pattern(ctrl->catalog, pattern);
  294. /* update sink with current settings */
  295. ret = dp_ctrl_update_sink_pattern(ctrl, pattern);
  296. if (ret)
  297. break;
  298. }
  299. ret = dp_ctrl_update_sink_vx_px(ctrl);
  300. if (ret)
  301. break;
  302. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  303. drm_dp_link_train_clock_recovery_delay(ctrl->aux->drm_aux, ctrl->panel->dpcd);
  304. #else
  305. drm_dp_link_train_clock_recovery_delay(ctrl->panel->dpcd);
  306. #endif
  307. ret = dp_ctrl_read_link_status(ctrl, link_status);
  308. if (ret)
  309. break;
  310. if (!drm_dp_clock_recovery_ok(link_status,
  311. ctrl->link->link_params.lane_count))
  312. ret = -EINVAL;
  313. else
  314. break;
  315. if (ctrl->link->phy_params.v_level == ctrl->link->phy_params.max_v_level) {
  316. pr_err_ratelimited("max v_level reached\n");
  317. break;
  318. }
  319. if (old_v_level == ctrl->link->phy_params.v_level) {
  320. if (++tries >= maximum_retries) {
  321. DP_ERR("max tries reached\n");
  322. ret = -ETIMEDOUT;
  323. break;
  324. }
  325. } else {
  326. tries = 0;
  327. old_v_level = ctrl->link->phy_params.v_level;
  328. }
  329. DP_DEBUG("clock recovery not done, adjusting vx px\n");
  330. ctrl->link->adjust_levels(ctrl->link, link_status);
  331. }
  332. if (ret && dp_ctrl_is_link_rate_rbr(ctrl)) {
  333. u8 active_lanes = dp_ctrl_get_active_lanes(ctrl, link_status);
  334. if (active_lanes) {
  335. ctrl->link->link_params.lane_count = active_lanes;
  336. ctrl->link->link_params.bw_code = ctrl->initial_bw_code;
  337. /* retry with new settings */
  338. ret = -EAGAIN;
  339. }
  340. }
  341. skip_training:
  342. ctrl->aux->state &= ~DP_STATE_TRAIN_1_STARTED;
  343. if (ret)
  344. ctrl->aux->state |= DP_STATE_TRAIN_1_FAILED;
  345. else
  346. ctrl->aux->state |= DP_STATE_TRAIN_1_SUCCEEDED;
  347. return ret;
  348. }
  349. static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
  350. {
  351. int ret = 0;
  352. if (!ctrl)
  353. return -EINVAL;
  354. switch (ctrl->link->link_params.bw_code) {
  355. case DP_LINK_BW_8_1:
  356. ctrl->link->link_params.bw_code = DP_LINK_BW_5_4;
  357. break;
  358. case DP_LINK_BW_5_4:
  359. ctrl->link->link_params.bw_code = DP_LINK_BW_2_7;
  360. break;
  361. case DP_LINK_BW_2_7:
  362. case DP_LINK_BW_1_62:
  363. default:
  364. ctrl->link->link_params.bw_code = DP_LINK_BW_1_62;
  365. break;
  366. }
  367. DP_DEBUG("new bw code=0x%x\n", ctrl->link->link_params.bw_code);
  368. return ret;
  369. }
  370. static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
  371. {
  372. dp_ctrl_update_sink_pattern(ctrl, 0);
  373. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  374. drm_dp_link_train_channel_eq_delay(ctrl->aux->drm_aux, ctrl->panel->dpcd);
  375. #else
  376. drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd);
  377. #endif
  378. }
  379. static int dp_ctrl_link_training_2(struct dp_ctrl_private *ctrl)
  380. {
  381. int tries = 0, ret = -EINVAL;
  382. u8 dpcd_pattern, pattern = 0;
  383. int const maximum_retries = 5;
  384. u8 link_status[DP_LINK_STATUS_SIZE];
  385. ctrl->aux->state &= ~DP_STATE_TRAIN_2_FAILED;
  386. ctrl->aux->state &= ~DP_STATE_TRAIN_2_SUCCEEDED;
  387. ctrl->aux->state |= DP_STATE_TRAIN_2_STARTED;
  388. if (ctrl->sim_mode) {
  389. DP_DEBUG("simulation enabled, skip channel equalization\n");
  390. ret = 0;
  391. goto skip_training;
  392. }
  393. dp_ctrl_state_ctrl(ctrl, 0);
  394. /* Make sure to clear the current pattern before starting a new one */
  395. wmb();
  396. dpcd_pattern = ctrl->training_2_pattern;
  397. while (!atomic_read(&ctrl->aborted)) {
  398. /* update hardware with current swing/pre-emp values */
  399. dp_ctrl_update_hw_vx_px(ctrl);
  400. if (!pattern) {
  401. pattern = dpcd_pattern;
  402. /* program hw to send pattern */
  403. ctrl->catalog->set_pattern(ctrl->catalog, pattern);
  404. /* update sink with current pattern */
  405. ret = dp_ctrl_update_sink_pattern(ctrl, pattern);
  406. if (ret)
  407. break;
  408. }
  409. ret = dp_ctrl_update_sink_vx_px(ctrl);
  410. if (ret)
  411. break;
  412. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  413. drm_dp_link_train_channel_eq_delay(ctrl->aux->drm_aux, ctrl->panel->dpcd);
  414. #else
  415. drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd);
  416. #endif
  417. ret = dp_ctrl_read_link_status(ctrl, link_status);
  418. if (ret)
  419. break;
  420. /* check if CR bits still remain set */
  421. if (!drm_dp_clock_recovery_ok(link_status,
  422. ctrl->link->link_params.lane_count)) {
  423. ret = -EINVAL;
  424. break;
  425. }
  426. if (!drm_dp_channel_eq_ok(link_status,
  427. ctrl->link->link_params.lane_count))
  428. ret = -EINVAL;
  429. else
  430. break;
  431. if (tries >= maximum_retries) {
  432. ret = dp_ctrl_lane_count_down_shift(ctrl);
  433. break;
  434. }
  435. tries++;
  436. ctrl->link->adjust_levels(ctrl->link, link_status);
  437. }
  438. skip_training:
  439. ctrl->aux->state &= ~DP_STATE_TRAIN_2_STARTED;
  440. if (ret)
  441. ctrl->aux->state |= DP_STATE_TRAIN_2_FAILED;
  442. else
  443. ctrl->aux->state |= DP_STATE_TRAIN_2_SUCCEEDED;
  444. return ret;
  445. }
  446. static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl)
  447. {
  448. int ret = 0;
  449. u8 const encoding = 0x1, downspread = 0x00;
  450. struct drm_dp_link link_info = {0};
  451. ctrl->link->phy_params.p_level = 0;
  452. ctrl->link->phy_params.v_level = 0;
  453. link_info.num_lanes = ctrl->link->link_params.lane_count;
  454. link_info.rate = drm_dp_bw_code_to_link_rate(
  455. ctrl->link->link_params.bw_code);
  456. link_info.capabilities = ctrl->panel->link_info.capabilities;
  457. ret = dp_link_configure(ctrl->aux->drm_aux, &link_info);
  458. if (ret)
  459. goto end;
  460. ret = drm_dp_dpcd_writeb(ctrl->aux->drm_aux,
  461. DP_DOWNSPREAD_CTRL, downspread);
  462. if (ret <= 0) {
  463. ret = -EINVAL;
  464. goto end;
  465. }
  466. ret = drm_dp_dpcd_writeb(ctrl->aux->drm_aux,
  467. DP_MAIN_LINK_CHANNEL_CODING_SET, encoding);
  468. if (ret <= 0) {
  469. ret = -EINVAL;
  470. goto end;
  471. }
  472. /* disable FEC before link training */
  473. ctrl->catalog->fec_config(ctrl->catalog, false);
  474. ret = dp_ctrl_link_training_1(ctrl);
  475. if (ret) {
  476. DP_ERR("link training #1 failed\n");
  477. goto end;
  478. }
  479. /* print success info as this is a result of user initiated action */
  480. DP_INFO("link training #1 successful\n");
  481. ret = dp_ctrl_link_training_2(ctrl);
  482. if (ret) {
  483. DP_ERR("link training #2 failed\n");
  484. goto end;
  485. }
  486. /* print success info as this is a result of user initiated action */
  487. DP_INFO("link training #2 successful\n");
  488. end:
  489. dp_ctrl_state_ctrl(ctrl, 0);
  490. /* Make sure to clear the current pattern before starting a new one */
  491. wmb();
  492. dp_ctrl_clear_training_pattern(ctrl);
  493. return ret;
  494. }
  495. static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl)
  496. {
  497. int ret = 0;
  498. if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
  499. goto end;
  500. /*
  501. * As part of previous calls, DP controller state might have
  502. * transitioned to PUSH_IDLE. In order to start transmitting a link
  503. * training pattern, we have to first to a DP software reset.
  504. */
  505. ctrl->catalog->reset(ctrl->catalog);
  506. if (ctrl->fec_mode)
  507. drm_dp_dpcd_writeb(ctrl->aux->drm_aux, DP_FEC_CONFIGURATION,
  508. 0x01);
  509. ret = dp_ctrl_link_train(ctrl);
  510. end:
  511. return ret;
  512. }
  513. static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
  514. char *name, enum dp_pm_type clk_type, u32 rate)
  515. {
  516. u32 num = ctrl->parser->mp[clk_type].num_clk;
  517. struct dss_clk *cfg = ctrl->parser->mp[clk_type].clk_config;
  518. /* convert to HZ for byte2 ops */
  519. rate *= ctrl->pll->clk_factor;
  520. while (num && strcmp(cfg->clk_name, name)) {
  521. num--;
  522. cfg++;
  523. }
  524. DP_DEBUG("setting rate=%d on clk=%s\n", rate, name);
  525. if (num)
  526. cfg->rate = rate;
  527. else
  528. DP_ERR("%s clock could not be set with rate %d\n", name, rate);
  529. }
  530. static int dp_ctrl_enable_link_clock(struct dp_ctrl_private *ctrl)
  531. {
  532. int ret = 0;
  533. u32 rate = drm_dp_bw_code_to_link_rate(ctrl->link->link_params.bw_code);
  534. enum dp_pm_type type = DP_LINK_PM;
  535. DP_DEBUG("rate=%d\n", rate);
  536. dp_ctrl_set_clock_rate(ctrl, "link_clk_src", type, rate);
  537. if (ctrl->pll->pll_cfg) {
  538. ret = ctrl->pll->pll_cfg(ctrl->pll, rate);
  539. if (ret < 0) {
  540. DP_ERR("DP pll cfg failed\n");
  541. return ret;
  542. }
  543. }
  544. if (ctrl->pll->pll_prepare) {
  545. ret = ctrl->pll->pll_prepare(ctrl->pll);
  546. if (ret < 0) {
  547. DP_ERR("DP pll prepare failed\n");
  548. return ret;
  549. }
  550. }
  551. ret = ctrl->power->clk_enable(ctrl->power, type, true);
  552. if (ret) {
  553. DP_ERR("Unabled to start link clocks\n");
  554. ret = -EINVAL;
  555. }
  556. return ret;
  557. }
  558. static void dp_ctrl_disable_link_clock(struct dp_ctrl_private *ctrl)
  559. {
  560. int rc = 0;
  561. ctrl->power->clk_enable(ctrl->power, DP_LINK_PM, false);
  562. if (ctrl->pll->pll_unprepare) {
  563. rc = ctrl->pll->pll_unprepare(ctrl->pll);
  564. if (rc < 0)
  565. DP_ERR("pll unprepare failed\n");
  566. }
  567. }
  568. static void dp_ctrl_select_training_pattern(struct dp_ctrl_private *ctrl,
  569. bool downgrade)
  570. {
  571. u32 pattern;
  572. if (drm_dp_tps4_supported(ctrl->panel->dpcd))
  573. pattern = DP_TRAINING_PATTERN_4;
  574. else if (drm_dp_tps3_supported(ctrl->panel->dpcd))
  575. pattern = DP_TRAINING_PATTERN_3;
  576. else
  577. pattern = DP_TRAINING_PATTERN_2;
  578. if (!downgrade)
  579. goto end;
  580. switch (pattern) {
  581. case DP_TRAINING_PATTERN_4:
  582. pattern = DP_TRAINING_PATTERN_3;
  583. break;
  584. case DP_TRAINING_PATTERN_3:
  585. pattern = DP_TRAINING_PATTERN_2;
  586. break;
  587. default:
  588. break;
  589. }
  590. end:
  591. ctrl->training_2_pattern = pattern;
  592. }
  593. static int dp_ctrl_link_setup(struct dp_ctrl_private *ctrl, bool shallow)
  594. {
  595. int rc = -EINVAL;
  596. bool downgrade = false;
  597. u32 link_train_max_retries = 100;
  598. struct dp_catalog_ctrl *catalog;
  599. struct dp_link_params *link_params;
  600. catalog = ctrl->catalog;
  601. link_params = &ctrl->link->link_params;
  602. catalog->phy_lane_cfg(catalog, ctrl->orientation,
  603. link_params->lane_count);
  604. while (1) {
  605. DP_DEBUG("bw_code=%d, lane_count=%d\n",
  606. link_params->bw_code, link_params->lane_count);
  607. rc = dp_ctrl_enable_link_clock(ctrl);
  608. if (rc)
  609. break;
  610. ctrl->catalog->late_phy_init(ctrl->catalog,
  611. ctrl->link->link_params.lane_count,
  612. ctrl->orientation);
  613. dp_ctrl_configure_source_link_params(ctrl, true);
  614. if (!(--link_train_max_retries % 10)) {
  615. struct dp_link_params *link = &ctrl->link->link_params;
  616. link->lane_count = ctrl->initial_lane_count;
  617. link->bw_code = ctrl->initial_bw_code;
  618. downgrade = true;
  619. }
  620. dp_ctrl_select_training_pattern(ctrl, downgrade);
  621. rc = dp_ctrl_setup_main_link(ctrl);
  622. if (!rc)
  623. break;
  624. /*
  625. * Shallow means link training failure is not important.
  626. * If it fails, we still keep the link clocks on.
  627. * In this mode, the system expects DP to be up
  628. * even though the cable is removed. Disconnect interrupt
  629. * will eventually trigger and shutdown DP.
  630. */
  631. if (shallow) {
  632. rc = 0;
  633. break;
  634. }
  635. if (!link_train_max_retries || atomic_read(&ctrl->aborted)) {
  636. dp_ctrl_disable_link_clock(ctrl);
  637. break;
  638. }
  639. if (rc != -EAGAIN)
  640. dp_ctrl_link_rate_down_shift(ctrl);
  641. dp_ctrl_configure_source_link_params(ctrl, false);
  642. dp_ctrl_disable_link_clock(ctrl);
  643. /* hw recommended delays before retrying link training */
  644. msleep(20);
  645. }
  646. return rc;
  647. }
  648. static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl,
  649. struct dp_panel *dp_panel)
  650. {
  651. int ret = 0;
  652. u32 pclk;
  653. enum dp_pm_type clk_type;
  654. char clk_name[32] = "";
  655. ret = ctrl->power->set_pixel_clk_parent(ctrl->power,
  656. dp_panel->stream_id);
  657. if (ret)
  658. return ret;
  659. if (dp_panel->stream_id == DP_STREAM_0) {
  660. clk_type = DP_STREAM0_PM;
  661. strlcpy(clk_name, "strm0_pixel_clk", 32);
  662. } else if (dp_panel->stream_id == DP_STREAM_1) {
  663. clk_type = DP_STREAM1_PM;
  664. strlcpy(clk_name, "strm1_pixel_clk", 32);
  665. } else {
  666. DP_ERR("Invalid stream:%d for clk enable\n",
  667. dp_panel->stream_id);
  668. return -EINVAL;
  669. }
  670. pclk = dp_panel->pinfo.widebus_en ?
  671. (dp_panel->pinfo.pixel_clk_khz >> 1) :
  672. (dp_panel->pinfo.pixel_clk_khz);
  673. dp_ctrl_set_clock_rate(ctrl, clk_name, clk_type, pclk);
  674. ret = ctrl->power->clk_enable(ctrl->power, clk_type, true);
  675. if (ret) {
  676. DP_ERR("Unabled to start stream:%d clocks\n",
  677. dp_panel->stream_id);
  678. ret = -EINVAL;
  679. }
  680. return ret;
  681. }
  682. static int dp_ctrl_disable_stream_clocks(struct dp_ctrl_private *ctrl,
  683. struct dp_panel *dp_panel)
  684. {
  685. int ret = 0;
  686. if (dp_panel->stream_id == DP_STREAM_0) {
  687. return ctrl->power->clk_enable(ctrl->power,
  688. DP_STREAM0_PM, false);
  689. } else if (dp_panel->stream_id == DP_STREAM_1) {
  690. return ctrl->power->clk_enable(ctrl->power,
  691. DP_STREAM1_PM, false);
  692. } else {
  693. DP_ERR("Invalid stream:%d for clk disable\n",
  694. dp_panel->stream_id);
  695. ret = -EINVAL;
  696. }
  697. return ret;
  698. }
  699. static int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset)
  700. {
  701. struct dp_ctrl_private *ctrl;
  702. struct dp_catalog_ctrl *catalog;
  703. if (!dp_ctrl) {
  704. DP_ERR("Invalid input data\n");
  705. return -EINVAL;
  706. }
  707. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  708. ctrl->orientation = flip;
  709. catalog = ctrl->catalog;
  710. if (reset) {
  711. catalog->usb_reset(ctrl->catalog, flip);
  712. catalog->phy_reset(ctrl->catalog);
  713. }
  714. catalog->enable_irq(ctrl->catalog, true);
  715. atomic_set(&ctrl->aborted, 0);
  716. return 0;
  717. }
  718. /**
  719. * dp_ctrl_host_deinit() - Uninitialize DP controller
  720. * @ctrl: Display Port Driver data
  721. *
  722. * Perform required steps to uninitialize DP controller
  723. * and its resources.
  724. */
  725. static void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
  726. {
  727. struct dp_ctrl_private *ctrl;
  728. if (!dp_ctrl) {
  729. DP_ERR("Invalid input data\n");
  730. return;
  731. }
  732. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  733. ctrl->catalog->enable_irq(ctrl->catalog, false);
  734. DP_DEBUG("Host deinitialized successfully\n");
  735. }
  736. static void dp_ctrl_send_video(struct dp_ctrl_private *ctrl)
  737. {
  738. reinit_completion(&ctrl->video_comp);
  739. ctrl->catalog->state_ctrl(ctrl->catalog, ST_SEND_VIDEO);
  740. }
  741. static void dp_ctrl_fec_setup(struct dp_ctrl_private *ctrl)
  742. {
  743. u8 fec_sts = 0;
  744. int i, max_retries = 3;
  745. bool fec_en_detected = false;
  746. if (!ctrl->fec_mode)
  747. return;
  748. /* FEC should be set only for the first stream */
  749. if (ctrl->stream_count > 1)
  750. return;
  751. /* Need to try to enable multiple times due to BS symbols collisions */
  752. for (i = 0; i < max_retries; i++) {
  753. ctrl->catalog->fec_config(ctrl->catalog, ctrl->fec_mode);
  754. /* wait for controller to start fec sequence */
  755. usleep_range(900, 1000);
  756. /* read back FEC status and check if it is enabled */
  757. drm_dp_dpcd_readb(ctrl->aux->drm_aux, DP_FEC_STATUS, &fec_sts);
  758. if (fec_sts & DP_FEC_DECODE_EN_DETECTED) {
  759. fec_en_detected = true;
  760. break;
  761. }
  762. }
  763. SDE_EVT32_EXTERNAL(i, fec_en_detected);
  764. DP_DEBUG("retries %d, fec_en_detected %d\n", i, fec_en_detected);
  765. if (!fec_en_detected)
  766. DP_WARN("failed to enable sink fec\n");
  767. }
  768. static int dp_ctrl_mst_send_act(struct dp_ctrl_private *ctrl)
  769. {
  770. bool act_complete;
  771. if (!ctrl->mst_mode)
  772. return 0;
  773. ctrl->catalog->trigger_act(ctrl->catalog);
  774. msleep(20); /* needs 1 frame time */
  775. ctrl->catalog->read_act_complete_sts(ctrl->catalog, &act_complete);
  776. if (!act_complete)
  777. DP_ERR("mst act trigger complete failed\n");
  778. else
  779. DP_MST_DEBUG("mst ACT trigger complete SUCCESS\n");
  780. return 0;
  781. }
  782. static int dp_ctrl_link_maintenance(struct dp_ctrl *dp_ctrl)
  783. {
  784. int ret = 0;
  785. struct dp_ctrl_private *ctrl;
  786. if (!dp_ctrl) {
  787. DP_ERR("Invalid input data\n");
  788. return -EINVAL;
  789. }
  790. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  791. ctrl->aux->state &= ~DP_STATE_LINK_MAINTENANCE_COMPLETED;
  792. ctrl->aux->state &= ~DP_STATE_LINK_MAINTENANCE_FAILED;
  793. if (!ctrl->power_on) {
  794. DP_ERR("ctrl off\n");
  795. ret = -EINVAL;
  796. goto end;
  797. }
  798. if (atomic_read(&ctrl->aborted))
  799. goto end;
  800. ctrl->aux->state |= DP_STATE_LINK_MAINTENANCE_STARTED;
  801. ret = dp_ctrl_setup_main_link(ctrl);
  802. ctrl->aux->state &= ~DP_STATE_LINK_MAINTENANCE_STARTED;
  803. if (ret) {
  804. ctrl->aux->state |= DP_STATE_LINK_MAINTENANCE_FAILED;
  805. goto end;
  806. }
  807. ctrl->aux->state |= DP_STATE_LINK_MAINTENANCE_COMPLETED;
  808. if (ctrl->stream_count) {
  809. dp_ctrl_send_video(ctrl);
  810. dp_ctrl_mst_send_act(ctrl);
  811. dp_ctrl_wait4video_ready(ctrl);
  812. dp_ctrl_fec_setup(ctrl);
  813. }
  814. end:
  815. return ret;
  816. }
  817. static void dp_ctrl_process_phy_test_request(struct dp_ctrl *dp_ctrl)
  818. {
  819. int ret = 0;
  820. struct dp_ctrl_private *ctrl;
  821. if (!dp_ctrl) {
  822. DP_ERR("Invalid input data\n");
  823. return;
  824. }
  825. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  826. if (!ctrl->link->phy_params.phy_test_pattern_sel) {
  827. DP_DEBUG("no test pattern selected by sink\n");
  828. return;
  829. }
  830. DP_DEBUG("start\n");
  831. /*
  832. * The global reset will need DP link ralated clocks to be
  833. * running. Add the global reset just before disabling the
  834. * link clocks and core clocks.
  835. */
  836. ctrl->catalog->reset(ctrl->catalog);
  837. ctrl->dp_ctrl.stream_pre_off(&ctrl->dp_ctrl, ctrl->panel);
  838. ctrl->dp_ctrl.stream_off(&ctrl->dp_ctrl, ctrl->panel);
  839. ctrl->dp_ctrl.off(&ctrl->dp_ctrl);
  840. ctrl->aux->init(ctrl->aux, ctrl->parser->aux_cfg);
  841. ret = ctrl->dp_ctrl.on(&ctrl->dp_ctrl, ctrl->mst_mode,
  842. ctrl->fec_mode, ctrl->dsc_mode, false);
  843. if (ret)
  844. DP_ERR("failed to enable DP controller\n");
  845. ctrl->dp_ctrl.stream_on(&ctrl->dp_ctrl, ctrl->panel);
  846. DP_DEBUG("end\n");
  847. }
  848. static void dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
  849. {
  850. bool success = false;
  851. u32 pattern_sent = 0x0;
  852. u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
  853. dp_ctrl_update_hw_vx_px(ctrl);
  854. ctrl->catalog->send_phy_pattern(ctrl->catalog, pattern_requested);
  855. dp_ctrl_update_sink_vx_px(ctrl);
  856. ctrl->link->send_test_response(ctrl->link);
  857. pattern_sent = ctrl->catalog->read_phy_pattern(ctrl->catalog);
  858. DP_DEBUG("pattern_request: %s. pattern_sent: 0x%x\n",
  859. dp_link_get_phy_test_pattern(pattern_requested),
  860. pattern_sent);
  861. switch (pattern_sent) {
  862. case MR_LINK_TRAINING1:
  863. if (pattern_requested == DP_PHY_TEST_PATTERN_D10_2)
  864. success = true;
  865. break;
  866. case MR_LINK_SYMBOL_ERM:
  867. if ((pattern_requested == DP_PHY_TEST_PATTERN_ERROR_COUNT)
  868. || (pattern_requested == DP_PHY_TEST_PATTERN_CP2520))
  869. success = true;
  870. break;
  871. case MR_LINK_PRBS7:
  872. if (pattern_requested == DP_PHY_TEST_PATTERN_PRBS7)
  873. success = true;
  874. break;
  875. case MR_LINK_CUSTOM80:
  876. if (pattern_requested == DP_PHY_TEST_PATTERN_80BIT_CUSTOM)
  877. success = true;
  878. break;
  879. case MR_LINK_TRAINING4:
  880. if (pattern_requested == DP_PHY_TEST_PATTERN_CP2520_3)
  881. success = true;
  882. break;
  883. default:
  884. success = false;
  885. break;
  886. }
  887. DP_DEBUG("%s: %s\n", success ? "success" : "failed",
  888. dp_link_get_phy_test_pattern(pattern_requested));
  889. }
  890. static void dp_ctrl_mst_calculate_rg(struct dp_ctrl_private *ctrl,
  891. struct dp_panel *panel, u32 *p_x_int, u32 *p_y_frac_enum)
  892. {
  893. u64 min_slot_cnt, max_slot_cnt;
  894. u64 raw_target_sc, target_sc_fixp;
  895. u64 ts_denom, ts_enum, ts_int;
  896. u64 pclk = panel->pinfo.pixel_clk_khz;
  897. u64 lclk = 0;
  898. u64 lanes = ctrl->link->link_params.lane_count;
  899. u64 bpp = panel->pinfo.bpp;
  900. u64 pbn = panel->pbn;
  901. u64 numerator, denominator, temp, temp1, temp2;
  902. u32 x_int = 0, y_frac_enum = 0;
  903. u64 target_strm_sym, ts_int_fixp, ts_frac_fixp, y_frac_enum_fixp;
  904. lclk = drm_dp_bw_code_to_link_rate(ctrl->link->link_params.bw_code);
  905. if (panel->pinfo.comp_info.enabled)
  906. bpp = panel->pinfo.comp_info.tgt_bpp;
  907. /* min_slot_cnt */
  908. numerator = pclk * bpp * 64 * 1000;
  909. denominator = lclk * lanes * 8 * 1000;
  910. min_slot_cnt = drm_fixp_from_fraction(numerator, denominator);
  911. /* max_slot_cnt */
  912. numerator = pbn * 54 * 1000;
  913. denominator = lclk * lanes;
  914. max_slot_cnt = drm_fixp_from_fraction(numerator, denominator);
  915. /* raw_target_sc */
  916. numerator = max_slot_cnt + min_slot_cnt;
  917. denominator = drm_fixp_from_fraction(2, 1);
  918. raw_target_sc = drm_fixp_div(numerator, denominator);
  919. DP_DEBUG("raw_target_sc before overhead:0x%llx\n", raw_target_sc);
  920. DP_DEBUG("dsc_overhead_fp:0x%llx\n", panel->pinfo.dsc_overhead_fp);
  921. /* apply fec and dsc overhead factor */
  922. if (panel->pinfo.dsc_overhead_fp)
  923. raw_target_sc = drm_fixp_mul(raw_target_sc,
  924. panel->pinfo.dsc_overhead_fp);
  925. if (panel->fec_overhead_fp)
  926. raw_target_sc = drm_fixp_mul(raw_target_sc,
  927. panel->fec_overhead_fp);
  928. DP_DEBUG("raw_target_sc after overhead:0x%llx\n", raw_target_sc);
  929. /* target_sc */
  930. temp = drm_fixp_from_fraction(256 * lanes, 1);
  931. numerator = drm_fixp_mul(raw_target_sc, temp);
  932. denominator = drm_fixp_from_fraction(256 * lanes, 1);
  933. target_sc_fixp = drm_fixp_div(numerator, denominator);
  934. ts_enum = 256 * lanes;
  935. ts_denom = drm_fixp_from_fraction(256 * lanes, 1);
  936. ts_int = drm_fixp2int(target_sc_fixp);
  937. temp = drm_fixp2int_ceil(raw_target_sc);
  938. if (temp != ts_int) {
  939. temp = drm_fixp_from_fraction(ts_int, 1);
  940. temp1 = raw_target_sc - temp;
  941. temp2 = drm_fixp_mul(temp1, ts_denom);
  942. ts_enum = drm_fixp2int(temp2);
  943. }
  944. /* target_strm_sym */
  945. ts_int_fixp = drm_fixp_from_fraction(ts_int, 1);
  946. ts_frac_fixp = drm_fixp_from_fraction(ts_enum, drm_fixp2int(ts_denom));
  947. temp = ts_int_fixp + ts_frac_fixp;
  948. temp1 = drm_fixp_from_fraction(lanes, 1);
  949. target_strm_sym = drm_fixp_mul(temp, temp1);
  950. /* x_int */
  951. x_int = drm_fixp2int(target_strm_sym);
  952. /* y_enum_frac */
  953. temp = drm_fixp_from_fraction(x_int, 1);
  954. temp1 = target_strm_sym - temp;
  955. temp2 = drm_fixp_from_fraction(256, 1);
  956. y_frac_enum_fixp = drm_fixp_mul(temp1, temp2);
  957. temp1 = drm_fixp2int(y_frac_enum_fixp);
  958. temp2 = drm_fixp2int_ceil(y_frac_enum_fixp);
  959. y_frac_enum = (u32)((temp1 == temp2) ? temp1 : temp1 + 1);
  960. panel->mst_target_sc = raw_target_sc;
  961. *p_x_int = x_int;
  962. *p_y_frac_enum = y_frac_enum;
  963. DP_DEBUG("x_int: %d, y_frac_enum: %d\n", x_int, y_frac_enum);
  964. }
  965. static void dp_ctrl_mst_stream_setup(struct dp_ctrl_private *ctrl,
  966. struct dp_panel *panel)
  967. {
  968. u32 x_int, y_frac_enum, lanes, bw_code;
  969. int i;
  970. if (!ctrl->mst_mode)
  971. return;
  972. DP_MST_DEBUG("mst stream channel allocation\n");
  973. for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) {
  974. ctrl->catalog->channel_alloc(ctrl->catalog,
  975. i,
  976. ctrl->mst_ch_info.slot_info[i].start_slot,
  977. ctrl->mst_ch_info.slot_info[i].tot_slots);
  978. }
  979. lanes = ctrl->link->link_params.lane_count;
  980. bw_code = ctrl->link->link_params.bw_code;
  981. dp_ctrl_mst_calculate_rg(ctrl, panel, &x_int, &y_frac_enum);
  982. ctrl->catalog->update_rg(ctrl->catalog, panel->stream_id,
  983. x_int, y_frac_enum);
  984. DP_MST_DEBUG("mst stream:%d, start_slot:%d, tot_slots:%d\n",
  985. panel->stream_id,
  986. panel->channel_start_slot, panel->channel_total_slots);
  987. DP_MST_DEBUG("mst lane_cnt:%d, bw:%d, x_int:%d, y_frac:%d\n",
  988. lanes, bw_code, x_int, y_frac_enum);
  989. }
  990. static void dp_ctrl_dsc_setup(struct dp_ctrl_private *ctrl, struct dp_panel *panel)
  991. {
  992. int rlen;
  993. u32 dsc_enable;
  994. struct dp_panel_info *pinfo = &panel->pinfo;
  995. if (!ctrl->fec_mode)
  996. return;
  997. /* Set DP_DSC_ENABLE DPCD register if compression is enabled for SST monitor.
  998. * Set DP_DSC_ENABLE DPCD register if compression is enabled for
  999. * atleast 1 of the MST monitor.
  1000. */
  1001. dsc_enable = (pinfo->comp_info.enabled == true) ? 1 : 0;
  1002. if (ctrl->mst_mode && (panel->stream_id == DP_STREAM_1) && !dsc_enable)
  1003. return;
  1004. rlen = drm_dp_dpcd_writeb(ctrl->aux->drm_aux, DP_DSC_ENABLE,
  1005. dsc_enable);
  1006. if (rlen < 1)
  1007. DP_WARN("failed to enable sink dsc\n");
  1008. }
  1009. static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel)
  1010. {
  1011. int rc = 0;
  1012. bool link_ready = false;
  1013. struct dp_ctrl_private *ctrl;
  1014. if (!dp_ctrl || !panel)
  1015. return -EINVAL;
  1016. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1017. if (!ctrl->power_on) {
  1018. DP_DEBUG("controller powered off\n");
  1019. return -EPERM;
  1020. }
  1021. rc = dp_ctrl_enable_stream_clocks(ctrl, panel);
  1022. if (rc) {
  1023. DP_ERR("failure on stream clock enable\n");
  1024. return rc;
  1025. }
  1026. panel->pclk_on = true;
  1027. rc = panel->hw_cfg(panel, true);
  1028. if (rc)
  1029. return rc;
  1030. if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
  1031. dp_ctrl_send_phy_test_pattern(ctrl);
  1032. return 0;
  1033. }
  1034. dp_ctrl_mst_stream_setup(ctrl, panel);
  1035. dp_ctrl_send_video(ctrl);
  1036. dp_ctrl_mst_send_act(ctrl);
  1037. dp_ctrl_wait4video_ready(ctrl);
  1038. ctrl->stream_count++;
  1039. link_ready = ctrl->catalog->mainlink_ready(ctrl->catalog);
  1040. DP_DEBUG("mainlink %s\n", link_ready ? "READY" : "NOT READY");
  1041. /* wait for link training completion before fec config as per spec */
  1042. dp_ctrl_fec_setup(ctrl);
  1043. dp_ctrl_dsc_setup(ctrl, panel);
  1044. panel->sink_crc_enable(panel, true);
  1045. return rc;
  1046. }
  1047. static void dp_ctrl_mst_stream_pre_off(struct dp_ctrl *dp_ctrl,
  1048. struct dp_panel *panel)
  1049. {
  1050. struct dp_ctrl_private *ctrl;
  1051. bool act_complete;
  1052. int i;
  1053. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1054. if (!ctrl->mst_mode)
  1055. return;
  1056. for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) {
  1057. ctrl->catalog->channel_alloc(ctrl->catalog,
  1058. i,
  1059. ctrl->mst_ch_info.slot_info[i].start_slot,
  1060. ctrl->mst_ch_info.slot_info[i].tot_slots);
  1061. }
  1062. ctrl->catalog->trigger_act(ctrl->catalog);
  1063. msleep(20); /* needs 1 frame time */
  1064. ctrl->catalog->read_act_complete_sts(ctrl->catalog, &act_complete);
  1065. if (!act_complete)
  1066. DP_ERR("mst stream_off act trigger complete failed\n");
  1067. else
  1068. DP_MST_DEBUG("mst stream_off ACT trigger complete SUCCESS\n");
  1069. }
  1070. static void dp_ctrl_stream_pre_off(struct dp_ctrl *dp_ctrl,
  1071. struct dp_panel *panel)
  1072. {
  1073. struct dp_ctrl_private *ctrl;
  1074. if (!dp_ctrl || !panel) {
  1075. DP_ERR("invalid input\n");
  1076. return;
  1077. }
  1078. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1079. dp_ctrl_push_idle(ctrl, panel->stream_id);
  1080. dp_ctrl_mst_stream_pre_off(dp_ctrl, panel);
  1081. }
  1082. static void dp_ctrl_stream_off(struct dp_ctrl *dp_ctrl, struct dp_panel *panel)
  1083. {
  1084. struct dp_ctrl_private *ctrl;
  1085. if (!dp_ctrl || !panel)
  1086. return;
  1087. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1088. if (!ctrl->power_on)
  1089. return;
  1090. panel->hw_cfg(panel, false);
  1091. panel->pclk_on = false;
  1092. dp_ctrl_disable_stream_clocks(ctrl, panel);
  1093. ctrl->stream_count--;
  1094. }
  1095. static int dp_ctrl_on(struct dp_ctrl *dp_ctrl, bool mst_mode,
  1096. bool fec_mode, bool dsc_mode, bool shallow)
  1097. {
  1098. int rc = 0;
  1099. struct dp_ctrl_private *ctrl;
  1100. u32 rate = 0;
  1101. if (!dp_ctrl) {
  1102. rc = -EINVAL;
  1103. goto end;
  1104. }
  1105. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1106. if (ctrl->power_on)
  1107. goto end;
  1108. if (atomic_read(&ctrl->aborted)) {
  1109. rc = -EPERM;
  1110. goto end;
  1111. }
  1112. ctrl->mst_mode = mst_mode;
  1113. if (fec_mode) {
  1114. ctrl->fec_mode = fec_mode;
  1115. ctrl->dsc_mode = dsc_mode;
  1116. }
  1117. rate = ctrl->panel->link_info.rate;
  1118. if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
  1119. DP_DEBUG("using phy test link parameters\n");
  1120. } else {
  1121. ctrl->link->link_params.bw_code =
  1122. drm_dp_link_rate_to_bw_code(rate);
  1123. ctrl->link->link_params.lane_count =
  1124. ctrl->panel->link_info.num_lanes;
  1125. }
  1126. DP_DEBUG("bw_code=%d, lane_count=%d\n",
  1127. ctrl->link->link_params.bw_code,
  1128. ctrl->link->link_params.lane_count);
  1129. /* backup initial lane count and bw code */
  1130. ctrl->initial_lane_count = ctrl->link->link_params.lane_count;
  1131. ctrl->initial_bw_code = ctrl->link->link_params.bw_code;
  1132. rc = dp_ctrl_link_setup(ctrl, shallow);
  1133. if (!rc)
  1134. ctrl->power_on = true;
  1135. end:
  1136. return rc;
  1137. }
  1138. static void dp_ctrl_off(struct dp_ctrl *dp_ctrl)
  1139. {
  1140. struct dp_ctrl_private *ctrl;
  1141. if (!dp_ctrl)
  1142. return;
  1143. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1144. if (!ctrl->power_on)
  1145. return;
  1146. ctrl->catalog->fec_config(ctrl->catalog, false);
  1147. dp_ctrl_configure_source_link_params(ctrl, false);
  1148. dp_ctrl_state_ctrl(ctrl, 0);
  1149. /* Make sure DP is disabled before clk disable */
  1150. wmb();
  1151. dp_ctrl_disable_link_clock(ctrl);
  1152. ctrl->mst_mode = false;
  1153. ctrl->fec_mode = false;
  1154. ctrl->dsc_mode = false;
  1155. ctrl->power_on = false;
  1156. memset(&ctrl->mst_ch_info, 0, sizeof(ctrl->mst_ch_info));
  1157. DP_DEBUG("DP off done\n");
  1158. }
  1159. static void dp_ctrl_set_mst_channel_info(struct dp_ctrl *dp_ctrl,
  1160. enum dp_stream_id strm,
  1161. u32 start_slot, u32 tot_slots)
  1162. {
  1163. struct dp_ctrl_private *ctrl;
  1164. if (!dp_ctrl || strm >= DP_STREAM_MAX) {
  1165. DP_ERR("invalid input\n");
  1166. return;
  1167. }
  1168. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1169. ctrl->mst_ch_info.slot_info[strm].start_slot = start_slot;
  1170. ctrl->mst_ch_info.slot_info[strm].tot_slots = tot_slots;
  1171. }
  1172. static void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
  1173. {
  1174. struct dp_ctrl_private *ctrl;
  1175. if (!dp_ctrl)
  1176. return;
  1177. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1178. ctrl->catalog->get_interrupt(ctrl->catalog);
  1179. SDE_EVT32_EXTERNAL(ctrl->catalog->isr, ctrl->catalog->isr3, ctrl->catalog->isr5,
  1180. ctrl->catalog->isr6);
  1181. if (ctrl->catalog->isr & DP_CTRL_INTR_READY_FOR_VIDEO)
  1182. dp_ctrl_video_ready(ctrl);
  1183. if (ctrl->catalog->isr & DP_CTRL_INTR_IDLE_PATTERN_SENT)
  1184. dp_ctrl_idle_patterns_sent(ctrl);
  1185. if (ctrl->catalog->isr5 & DP_CTRL_INTR_MST_DP0_VCPF_SENT)
  1186. dp_ctrl_idle_patterns_sent(ctrl);
  1187. if (ctrl->catalog->isr5 & DP_CTRL_INTR_MST_DP1_VCPF_SENT)
  1188. dp_ctrl_idle_patterns_sent(ctrl);
  1189. }
  1190. void dp_ctrl_set_sim_mode(struct dp_ctrl *dp_ctrl, bool en)
  1191. {
  1192. struct dp_ctrl_private *ctrl;
  1193. if (!dp_ctrl)
  1194. return;
  1195. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1196. ctrl->sim_mode = en;
  1197. DP_INFO("sim_mode=%d\n", ctrl->sim_mode);
  1198. }
  1199. int dp_ctrl_setup_misr(struct dp_ctrl *dp_ctrl)
  1200. {
  1201. struct dp_ctrl_private *ctrl;
  1202. if (!dp_ctrl)
  1203. return -EINVAL;
  1204. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1205. return ctrl->catalog->setup_misr(ctrl->catalog);
  1206. }
  1207. int dp_ctrl_read_misr(struct dp_ctrl *dp_ctrl, struct dp_misr40_data *data)
  1208. {
  1209. struct dp_ctrl_private *ctrl;
  1210. if (!dp_ctrl)
  1211. return -EINVAL;
  1212. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1213. return ctrl->catalog->read_misr(ctrl->catalog, data);
  1214. }
  1215. struct dp_ctrl *dp_ctrl_get(struct dp_ctrl_in *in)
  1216. {
  1217. int rc = 0;
  1218. struct dp_ctrl_private *ctrl;
  1219. struct dp_ctrl *dp_ctrl;
  1220. if (!in->dev || !in->panel || !in->aux ||
  1221. !in->link || !in->catalog) {
  1222. DP_ERR("invalid input\n");
  1223. rc = -EINVAL;
  1224. goto error;
  1225. }
  1226. ctrl = devm_kzalloc(in->dev, sizeof(*ctrl), GFP_KERNEL);
  1227. if (!ctrl) {
  1228. rc = -ENOMEM;
  1229. goto error;
  1230. }
  1231. init_completion(&ctrl->idle_comp);
  1232. init_completion(&ctrl->video_comp);
  1233. /* in parameters */
  1234. ctrl->parser = in->parser;
  1235. ctrl->panel = in->panel;
  1236. ctrl->power = in->power;
  1237. ctrl->aux = in->aux;
  1238. ctrl->link = in->link;
  1239. ctrl->catalog = in->catalog;
  1240. ctrl->pll = in->pll;
  1241. ctrl->dev = in->dev;
  1242. ctrl->mst_mode = false;
  1243. ctrl->fec_mode = false;
  1244. dp_ctrl = &ctrl->dp_ctrl;
  1245. /* out parameters */
  1246. dp_ctrl->init = dp_ctrl_host_init;
  1247. dp_ctrl->deinit = dp_ctrl_host_deinit;
  1248. dp_ctrl->on = dp_ctrl_on;
  1249. dp_ctrl->off = dp_ctrl_off;
  1250. dp_ctrl->abort = dp_ctrl_abort;
  1251. dp_ctrl->isr = dp_ctrl_isr;
  1252. dp_ctrl->link_maintenance = dp_ctrl_link_maintenance;
  1253. dp_ctrl->process_phy_test_request = dp_ctrl_process_phy_test_request;
  1254. dp_ctrl->stream_on = dp_ctrl_stream_on;
  1255. dp_ctrl->stream_off = dp_ctrl_stream_off;
  1256. dp_ctrl->stream_pre_off = dp_ctrl_stream_pre_off;
  1257. dp_ctrl->set_mst_channel_info = dp_ctrl_set_mst_channel_info;
  1258. dp_ctrl->set_sim_mode = dp_ctrl_set_sim_mode;
  1259. dp_ctrl->setup_misr = dp_ctrl_setup_misr;
  1260. dp_ctrl->read_misr = dp_ctrl_read_misr;
  1261. return dp_ctrl;
  1262. error:
  1263. return ERR_PTR(rc);
  1264. }
  1265. void dp_ctrl_put(struct dp_ctrl *dp_ctrl)
  1266. {
  1267. struct dp_ctrl_private *ctrl;
  1268. if (!dp_ctrl)
  1269. return;
  1270. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1271. devm_kfree(ctrl->dev, ctrl);
  1272. }