msm_drv.h 32 KB

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  1. /*
  2. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #ifndef __MSM_DRV_H__
  19. #define __MSM_DRV_H__
  20. #include <linux/kernel.h>
  21. #include <linux/clk.h>
  22. #include <linux/cpufreq.h>
  23. #include <linux/module.h>
  24. #include <linux/component.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/pm.h>
  27. #include <linux/pm_runtime.h>
  28. #include <linux/slab.h>
  29. #include <linux/list.h>
  30. #include <linux/iommu.h>
  31. #include <linux/types.h>
  32. #include <linux/of_graph.h>
  33. #include <linux/of_device.h>
  34. #include <linux/sde_io_util.h>
  35. #include <asm/sizes.h>
  36. #include <linux/kthread.h>
  37. #include <drm/drmP.h>
  38. #include <drm/drm_atomic.h>
  39. #include <drm/drm_atomic_helper.h>
  40. #include <drm/drm_crtc_helper.h>
  41. #include <drm/drm_plane_helper.h>
  42. #include <drm/drm_fb_helper.h>
  43. #include <drm/msm_drm.h>
  44. #include <drm/drm_gem.h>
  45. #include "sde_power_handle.h"
  46. #define GET_MAJOR_REV(rev) ((rev) >> 28)
  47. #define GET_MINOR_REV(rev) (((rev) >> 16) & 0xFFF)
  48. #define GET_STEP_REV(rev) ((rev) & 0xFFFF)
  49. struct msm_kms;
  50. struct msm_gpu;
  51. struct msm_mmu;
  52. struct msm_mdss;
  53. struct msm_rd_state;
  54. struct msm_perf_state;
  55. struct msm_gem_submit;
  56. struct msm_fence_context;
  57. struct msm_fence_cb;
  58. struct msm_gem_address_space;
  59. struct msm_gem_vma;
  60. #define NUM_DOMAINS 4 /* one for KMS, then one per gpu core (?) */
  61. #define MAX_CRTCS 16
  62. #define MAX_PLANES 20
  63. #define MAX_ENCODERS 16
  64. #define MAX_BRIDGES 16
  65. #define MAX_CONNECTORS 16
  66. #define TEARDOWN_DEADLOCK_RETRY_MAX 5
  67. struct msm_file_private {
  68. rwlock_t queuelock;
  69. struct list_head submitqueues;
  70. int queueid;
  71. /* update the refcount when user driver calls power_ctrl IOCTL */
  72. unsigned short enable_refcnt;
  73. /* protects enable_refcnt */
  74. struct mutex power_lock;
  75. };
  76. enum msm_mdp_plane_property {
  77. /* blob properties, always put these first */
  78. PLANE_PROP_CSC_V1,
  79. PLANE_PROP_CSC_DMA_V1,
  80. PLANE_PROP_INFO,
  81. PLANE_PROP_SCALER_LUT_ED,
  82. PLANE_PROP_SCALER_LUT_CIR,
  83. PLANE_PROP_SCALER_LUT_SEP,
  84. PLANE_PROP_SKIN_COLOR,
  85. PLANE_PROP_SKY_COLOR,
  86. PLANE_PROP_FOLIAGE_COLOR,
  87. PLANE_PROP_VIG_GAMUT,
  88. PLANE_PROP_VIG_IGC,
  89. PLANE_PROP_DMA_IGC,
  90. PLANE_PROP_DMA_GC,
  91. /* # of blob properties */
  92. PLANE_PROP_BLOBCOUNT,
  93. /* range properties */
  94. PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT,
  95. PLANE_PROP_ALPHA,
  96. PLANE_PROP_COLOR_FILL,
  97. PLANE_PROP_H_DECIMATE,
  98. PLANE_PROP_V_DECIMATE,
  99. PLANE_PROP_INPUT_FENCE,
  100. PLANE_PROP_HUE_ADJUST,
  101. PLANE_PROP_SATURATION_ADJUST,
  102. PLANE_PROP_VALUE_ADJUST,
  103. PLANE_PROP_CONTRAST_ADJUST,
  104. PLANE_PROP_EXCL_RECT_V1,
  105. PLANE_PROP_PREFILL_SIZE,
  106. PLANE_PROP_PREFILL_TIME,
  107. PLANE_PROP_SCALER_V1,
  108. PLANE_PROP_SCALER_V2,
  109. PLANE_PROP_INVERSE_PMA,
  110. /* enum/bitmask properties */
  111. PLANE_PROP_BLEND_OP,
  112. PLANE_PROP_SRC_CONFIG,
  113. PLANE_PROP_FB_TRANSLATION_MODE,
  114. PLANE_PROP_MULTIRECT_MODE,
  115. /* total # of properties */
  116. PLANE_PROP_COUNT
  117. };
  118. enum msm_mdp_crtc_property {
  119. CRTC_PROP_INFO,
  120. CRTC_PROP_DEST_SCALER_LUT_ED,
  121. CRTC_PROP_DEST_SCALER_LUT_CIR,
  122. CRTC_PROP_DEST_SCALER_LUT_SEP,
  123. /* # of blob properties */
  124. CRTC_PROP_BLOBCOUNT,
  125. /* range properties */
  126. CRTC_PROP_INPUT_FENCE_TIMEOUT = CRTC_PROP_BLOBCOUNT,
  127. CRTC_PROP_OUTPUT_FENCE,
  128. CRTC_PROP_OUTPUT_FENCE_OFFSET,
  129. CRTC_PROP_DIM_LAYER_V1,
  130. CRTC_PROP_CORE_CLK,
  131. CRTC_PROP_CORE_AB,
  132. CRTC_PROP_CORE_IB,
  133. CRTC_PROP_LLCC_AB,
  134. CRTC_PROP_LLCC_IB,
  135. CRTC_PROP_DRAM_AB,
  136. CRTC_PROP_DRAM_IB,
  137. CRTC_PROP_ROT_PREFILL_BW,
  138. CRTC_PROP_ROT_CLK,
  139. CRTC_PROP_ROI_V1,
  140. CRTC_PROP_SECURITY_LEVEL,
  141. CRTC_PROP_IDLE_TIMEOUT,
  142. CRTC_PROP_DEST_SCALER,
  143. CRTC_PROP_CAPTURE_OUTPUT,
  144. CRTC_PROP_IDLE_PC_STATE,
  145. /* total # of properties */
  146. CRTC_PROP_COUNT
  147. };
  148. enum msm_mdp_conn_property {
  149. /* blob properties, always put these first */
  150. CONNECTOR_PROP_SDE_INFO,
  151. CONNECTOR_PROP_MODE_INFO,
  152. CONNECTOR_PROP_HDR_INFO,
  153. CONNECTOR_PROP_EXT_HDR_INFO,
  154. CONNECTOR_PROP_PP_DITHER,
  155. CONNECTOR_PROP_HDR_METADATA,
  156. /* # of blob properties */
  157. CONNECTOR_PROP_BLOBCOUNT,
  158. /* range properties */
  159. CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
  160. CONNECTOR_PROP_RETIRE_FENCE,
  161. CONNECTOR_PROP_DST_X,
  162. CONNECTOR_PROP_DST_Y,
  163. CONNECTOR_PROP_DST_W,
  164. CONNECTOR_PROP_DST_H,
  165. CONNECTOR_PROP_ROI_V1,
  166. CONNECTOR_PROP_BL_SCALE,
  167. CONNECTOR_PROP_SV_BL_SCALE,
  168. /* enum/bitmask properties */
  169. CONNECTOR_PROP_TOPOLOGY_NAME,
  170. CONNECTOR_PROP_TOPOLOGY_CONTROL,
  171. CONNECTOR_PROP_AUTOREFRESH,
  172. CONNECTOR_PROP_LP,
  173. CONNECTOR_PROP_FB_TRANSLATION_MODE,
  174. CONNECTOR_PROP_QSYNC_MODE,
  175. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE,
  176. /* total # of properties */
  177. CONNECTOR_PROP_COUNT
  178. };
  179. #define MSM_GPU_MAX_RINGS 4
  180. #define MAX_H_TILES_PER_DISPLAY 2
  181. /**
  182. * enum msm_display_compression_type - compression method used for pixel stream
  183. * @MSM_DISPLAY_COMPRESSION_NONE: Pixel data is not compressed
  184. * @MSM_DISPLAY_COMPRESSION_DSC: DSC compresison is used
  185. */
  186. enum msm_display_compression_type {
  187. MSM_DISPLAY_COMPRESSION_NONE,
  188. MSM_DISPLAY_COMPRESSION_DSC,
  189. };
  190. /**
  191. * enum msm_display_compression_ratio - compression ratio
  192. * @MSM_DISPLAY_COMPRESSION_NONE: no compression
  193. * @MSM_DISPLAY_COMPRESSION_RATIO_2_TO_1: 2 to 1 compression
  194. * @MSM_DISPLAY_COMPRESSION_RATIO_3_TO_1: 3 to 1 compression
  195. */
  196. enum msm_display_compression_ratio {
  197. MSM_DISPLAY_COMPRESSION_RATIO_NONE,
  198. MSM_DISPLAY_COMPRESSION_RATIO_2_TO_1,
  199. MSM_DISPLAY_COMPRESSION_RATIO_3_TO_1,
  200. MSM_DISPLAY_COMPRESSION_RATIO_MAX,
  201. };
  202. /**
  203. * enum msm_display_caps - features/capabilities supported by displays
  204. * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
  205. * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
  206. * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
  207. * @MSM_DISPLAY_CAP_EDID: EDID supported
  208. * @MSM_DISPLAY_ESD_ENABLED: ESD feature enabled
  209. * @MSM_DISPLAY_CAP_MST_MODE: Display with MST support
  210. * @MSM_DISPLAY_SPLIT_LINK: Split Link enabled
  211. */
  212. enum msm_display_caps {
  213. MSM_DISPLAY_CAP_VID_MODE = BIT(0),
  214. MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
  215. MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
  216. MSM_DISPLAY_CAP_EDID = BIT(3),
  217. MSM_DISPLAY_ESD_ENABLED = BIT(4),
  218. MSM_DISPLAY_CAP_MST_MODE = BIT(5),
  219. MSM_DISPLAY_SPLIT_LINK = BIT(6),
  220. };
  221. /**
  222. * enum panel_mode - panel operation mode
  223. * @MSM_DISPLAY_VIDEO_MODE: video mode panel
  224. * @MSM_DISPLAY_CMD_MODE: Command mode panel
  225. * @MODE_MAX:
  226. */
  227. enum panel_op_mode {
  228. MSM_DISPLAY_VIDEO_MODE = 0,
  229. MSM_DISPLAY_CMD_MODE,
  230. MSM_DISPLAY_MODE_MAX,
  231. };
  232. /**
  233. * enum msm_event_wait - type of HW events to wait for
  234. * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
  235. * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
  236. * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
  237. * @MSM_ENC_ACTIVE_REGION - wait for the TG to be in active pixel region
  238. */
  239. enum msm_event_wait {
  240. MSM_ENC_COMMIT_DONE = 0,
  241. MSM_ENC_TX_COMPLETE,
  242. MSM_ENC_VBLANK,
  243. MSM_ENC_ACTIVE_REGION,
  244. };
  245. /**
  246. * struct msm_roi_alignment - region of interest alignment restrictions
  247. * @xstart_pix_align: left x offset alignment restriction
  248. * @width_pix_align: width alignment restriction
  249. * @ystart_pix_align: top y offset alignment restriction
  250. * @height_pix_align: height alignment restriction
  251. * @min_width: minimum width restriction
  252. * @min_height: minimum height restriction
  253. */
  254. struct msm_roi_alignment {
  255. uint32_t xstart_pix_align;
  256. uint32_t width_pix_align;
  257. uint32_t ystart_pix_align;
  258. uint32_t height_pix_align;
  259. uint32_t min_width;
  260. uint32_t min_height;
  261. };
  262. /**
  263. * struct msm_roi_caps - display's region of interest capabilities
  264. * @enabled: true if some region of interest is supported
  265. * @merge_rois: merge rois before sending to display
  266. * @num_roi: maximum number of rois supported
  267. * @align: roi alignment restrictions
  268. */
  269. struct msm_roi_caps {
  270. bool enabled;
  271. bool merge_rois;
  272. uint32_t num_roi;
  273. struct msm_roi_alignment align;
  274. };
  275. /**
  276. * struct msm_display_dsc_info - defines dsc configuration
  277. * @version: DSC version.
  278. * @scr_rev: DSC revision.
  279. * @pic_height: Picture height in pixels.
  280. * @pic_width: Picture width in pixels.
  281. * @initial_lines: Number of initial lines stored in encoder.
  282. * @pkt_per_line: Number of packets per line.
  283. * @bytes_in_slice: Number of bytes in slice.
  284. * @eol_byte_num: Valid bytes at the end of line.
  285. * @pclk_per_line: Compressed width.
  286. * @full_frame_slices: Number of slice per interface.
  287. * @slice_height: Slice height in pixels.
  288. * @slice_width: Slice width in pixels.
  289. * @chunk_size: Chunk size in bytes for slice multiplexing.
  290. * @slice_last_group_size: Size of last group in pixels.
  291. * @bpp: Target bits per pixel.
  292. * @bpc: Number of bits per component.
  293. * @line_buf_depth: Line buffer bit depth.
  294. * @block_pred_enable: Block prediction enabled/disabled.
  295. * @vbr_enable: VBR mode.
  296. * @enable_422: Indicates if input uses 4:2:2 sampling.
  297. * @convert_rgb: DSC color space conversion.
  298. * @input_10_bits: 10 bit per component input.
  299. * @slice_per_pkt: Number of slices per packet.
  300. * @initial_dec_delay: Initial decoding delay.
  301. * @initial_xmit_delay: Initial transmission delay.
  302. * @initial_scale_value: Scale factor value at the beginning of a slice.
  303. * @scale_decrement_interval: Scale set up at the beginning of a slice.
  304. * @scale_increment_interval: Scale set up at the end of a slice.
  305. * @first_line_bpg_offset: Extra bits allocated on the first line of a slice.
  306. * @nfl_bpg_offset: Slice specific settings.
  307. * @slice_bpg_offset: Slice specific settings.
  308. * @initial_offset: Initial offset at the start of a slice.
  309. * @final_offset: Maximum end-of-slice value.
  310. * @rc_model_size: Number of bits in RC model.
  311. * @det_thresh_flatness: Flatness threshold.
  312. * @max_qp_flatness: Maximum QP for flatness adjustment.
  313. * @min_qp_flatness: Minimum QP for flatness adjustment.
  314. * @edge_factor: Ratio to detect presence of edge.
  315. * @quant_incr_limit0: QP threshold.
  316. * @quant_incr_limit1: QP threshold.
  317. * @tgt_offset_hi: Upper end of variability range.
  318. * @tgt_offset_lo: Lower end of variability range.
  319. * @buf_thresh: Thresholds in RC model
  320. * @range_min_qp: Min QP allowed.
  321. * @range_max_qp: Max QP allowed.
  322. * @range_bpg_offset: Bits per group adjustment.
  323. * @extra_width: Extra width required in timing calculations.
  324. */
  325. struct msm_display_dsc_info {
  326. u8 version;
  327. u8 scr_rev;
  328. int pic_height;
  329. int pic_width;
  330. int slice_height;
  331. int slice_width;
  332. int initial_lines;
  333. int pkt_per_line;
  334. int bytes_in_slice;
  335. int bytes_per_pkt;
  336. int eol_byte_num;
  337. int pclk_per_line;
  338. int full_frame_slices;
  339. int slice_last_group_size;
  340. int bpp;
  341. int bpc;
  342. int line_buf_depth;
  343. int slice_per_pkt;
  344. int chunk_size;
  345. bool block_pred_enable;
  346. int vbr_enable;
  347. int enable_422;
  348. int convert_rgb;
  349. int input_10_bits;
  350. int initial_dec_delay;
  351. int initial_xmit_delay;
  352. int initial_scale_value;
  353. int scale_decrement_interval;
  354. int scale_increment_interval;
  355. int first_line_bpg_offset;
  356. int nfl_bpg_offset;
  357. int slice_bpg_offset;
  358. int initial_offset;
  359. int final_offset;
  360. int rc_model_size;
  361. int det_thresh_flatness;
  362. int max_qp_flatness;
  363. int min_qp_flatness;
  364. int edge_factor;
  365. int quant_incr_limit0;
  366. int quant_incr_limit1;
  367. int tgt_offset_hi;
  368. int tgt_offset_lo;
  369. u32 *buf_thresh;
  370. char *range_min_qp;
  371. char *range_max_qp;
  372. char *range_bpg_offset;
  373. u32 extra_width;
  374. };
  375. /**
  376. * struct msm_compression_info - defined panel compression
  377. * @comp_type: type of compression supported
  378. * @comp_ratio: compression ratio
  379. * @dsc_info: dsc configuration if the compression
  380. * supported is DSC
  381. */
  382. struct msm_compression_info {
  383. enum msm_display_compression_type comp_type;
  384. enum msm_display_compression_ratio comp_ratio;
  385. union{
  386. struct msm_display_dsc_info dsc_info;
  387. };
  388. };
  389. /**
  390. * struct msm_display_topology - defines a display topology pipeline
  391. * @num_lm: number of layer mixers used
  392. * @num_enc: number of compression encoder blocks used
  393. * @num_intf: number of interfaces the panel is mounted on
  394. */
  395. struct msm_display_topology {
  396. u32 num_lm;
  397. u32 num_enc;
  398. u32 num_intf;
  399. };
  400. /**
  401. * struct msm_mode_info - defines all msm custom mode info
  402. * @frame_rate: frame_rate of the mode
  403. * @vtotal: vtotal calculated for the mode
  404. * @prefill_lines: prefill lines based on porches.
  405. * @jitter_numer: display panel jitter numerator configuration
  406. * @jitter_denom: display panel jitter denominator configuration
  407. * @clk_rate: DSI bit clock per lane in HZ.
  408. * @topology: supported topology for the mode
  409. * @comp_info: compression info supported
  410. * @roi_caps: panel roi capabilities
  411. * @wide_bus_en: wide-bus mode cfg for interface module
  412. * @mdp_transfer_time_us Specifies the mdp transfer time for command mode
  413. * panels in microseconds.
  414. */
  415. struct msm_mode_info {
  416. uint32_t frame_rate;
  417. uint32_t vtotal;
  418. uint32_t prefill_lines;
  419. uint32_t jitter_numer;
  420. uint32_t jitter_denom;
  421. uint64_t clk_rate;
  422. struct msm_display_topology topology;
  423. struct msm_compression_info comp_info;
  424. struct msm_roi_caps roi_caps;
  425. bool wide_bus_en;
  426. u32 mdp_transfer_time_us;
  427. };
  428. /**
  429. * struct msm_resource_caps_info - defines hw resources
  430. * @num_lm number of layer mixers available
  431. * @num_dsc number of dsc available
  432. * @num_ctl number of ctl available
  433. * @num_3dmux number of 3d mux available
  434. * @max_mixer_width: max width supported by layer mixer
  435. */
  436. struct msm_resource_caps_info {
  437. uint32_t num_lm;
  438. uint32_t num_dsc;
  439. uint32_t num_ctl;
  440. uint32_t num_3dmux;
  441. uint32_t max_mixer_width;
  442. };
  443. /**
  444. * struct msm_display_info - defines display properties
  445. * @intf_type: DRM_MODE_CONNECTOR_ display type
  446. * @capabilities: Bitmask of display flags
  447. * @num_of_h_tiles: Number of horizontal tiles in case of split interface
  448. * @h_tile_instance: Controller instance used per tile. Number of elements is
  449. * based on num_of_h_tiles
  450. * @is_connected: Set to true if display is connected
  451. * @width_mm: Physical width
  452. * @height_mm: Physical height
  453. * @max_width: Max width of display. In case of hot pluggable display
  454. * this is max width supported by controller
  455. * @max_height: Max height of display. In case of hot pluggable display
  456. * this is max height supported by controller
  457. * @clk_rate: DSI bit clock per lane in HZ.
  458. * @display_type: Enum for type of display
  459. * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
  460. * used instead of panel TE in cmd mode panels
  461. * @roi_caps: Region of interest capability info
  462. * @qsync_min_fps Minimum fps supported by Qsync feature
  463. * @te_source vsync source pin information
  464. */
  465. struct msm_display_info {
  466. int intf_type;
  467. uint32_t capabilities;
  468. enum panel_op_mode curr_panel_mode;
  469. uint32_t num_of_h_tiles;
  470. uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
  471. bool is_connected;
  472. unsigned int width_mm;
  473. unsigned int height_mm;
  474. uint32_t max_width;
  475. uint32_t max_height;
  476. uint64_t clk_rate;
  477. uint32_t display_type;
  478. bool is_te_using_watchdog_timer;
  479. struct msm_roi_caps roi_caps;
  480. uint32_t qsync_min_fps;
  481. uint32_t te_source;
  482. };
  483. #define MSM_MAX_ROI 4
  484. /**
  485. * struct msm_roi_list - list of regions of interest for a drm object
  486. * @num_rects: number of valid rectangles in the roi array
  487. * @roi: list of roi rectangles
  488. */
  489. struct msm_roi_list {
  490. uint32_t num_rects;
  491. struct drm_clip_rect roi[MSM_MAX_ROI];
  492. };
  493. /**
  494. * struct - msm_display_kickoff_params - info for display features at kickoff
  495. * @rois: Regions of interest structure for mapping CRTC to Connector output
  496. * @qsync_mode: Qsync mode, where 0: disabled 1: continuous mode
  497. * @qsync_update: Qsync settings were changed/updated
  498. */
  499. struct msm_display_kickoff_params {
  500. struct msm_roi_list *rois;
  501. struct drm_msm_ext_hdr_metadata *hdr_meta;
  502. uint32_t qsync_mode;
  503. bool qsync_update;
  504. };
  505. /**
  506. * struct msm_drm_event - defines custom event notification struct
  507. * @base: base object required for event notification by DRM framework.
  508. * @event: event object required for event notification by DRM framework.
  509. * @info: contains information of DRM object for which events has been
  510. * requested.
  511. * @data: memory location which contains response payload for event.
  512. */
  513. struct msm_drm_event {
  514. struct drm_pending_event base;
  515. struct drm_event event;
  516. struct drm_msm_event_req info;
  517. u8 data[];
  518. };
  519. /* Commit/Event thread specific structure */
  520. struct msm_drm_thread {
  521. struct drm_device *dev;
  522. struct task_struct *thread;
  523. unsigned int crtc_id;
  524. struct kthread_worker worker;
  525. };
  526. struct msm_drm_private {
  527. struct drm_device *dev;
  528. struct msm_kms *kms;
  529. struct sde_power_handle phandle;
  530. /* subordinate devices, if present: */
  531. struct platform_device *gpu_pdev;
  532. /* top level MDSS wrapper device (for MDP5 only) */
  533. struct msm_mdss *mdss;
  534. /* possibly this should be in the kms component, but it is
  535. * shared by both mdp4 and mdp5..
  536. */
  537. struct hdmi *hdmi;
  538. /* eDP is for mdp5 only, but kms has not been created
  539. * when edp_bind() and edp_init() are called. Here is the only
  540. * place to keep the edp instance.
  541. */
  542. struct msm_edp *edp;
  543. /* DSI is shared by mdp4 and mdp5 */
  544. struct msm_dsi *dsi[2];
  545. /* when we have more than one 'msm_gpu' these need to be an array: */
  546. struct msm_gpu *gpu;
  547. struct msm_file_private *lastctx;
  548. struct drm_fb_helper *fbdev;
  549. struct msm_rd_state *rd; /* debugfs to dump all submits */
  550. struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
  551. struct msm_perf_state *perf;
  552. /* list of GEM objects: */
  553. struct list_head inactive_list;
  554. struct workqueue_struct *wq;
  555. /* crtcs pending async atomic updates: */
  556. uint32_t pending_crtcs;
  557. wait_queue_head_t pending_crtcs_event;
  558. unsigned int num_planes;
  559. struct drm_plane *planes[MAX_PLANES];
  560. unsigned int num_crtcs;
  561. struct drm_crtc *crtcs[MAX_CRTCS];
  562. struct msm_drm_thread disp_thread[MAX_CRTCS];
  563. struct msm_drm_thread event_thread[MAX_CRTCS];
  564. struct task_struct *pp_event_thread;
  565. struct kthread_worker pp_event_worker;
  566. unsigned int num_encoders;
  567. struct drm_encoder *encoders[MAX_ENCODERS];
  568. unsigned int num_bridges;
  569. struct drm_bridge *bridges[MAX_BRIDGES];
  570. unsigned int num_connectors;
  571. struct drm_connector *connectors[MAX_CONNECTORS];
  572. /* Properties */
  573. struct drm_property *plane_property[PLANE_PROP_COUNT];
  574. struct drm_property *crtc_property[CRTC_PROP_COUNT];
  575. struct drm_property *conn_property[CONNECTOR_PROP_COUNT];
  576. /* Color processing properties for the crtc */
  577. struct drm_property **cp_property;
  578. /* VRAM carveout, used when no IOMMU: */
  579. struct {
  580. unsigned long size;
  581. dma_addr_t paddr;
  582. /* NOTE: mm managed at the page level, size is in # of pages
  583. * and position mm_node->start is in # of pages:
  584. */
  585. struct drm_mm mm;
  586. spinlock_t lock; /* Protects drm_mm node allocation/removal */
  587. } vram;
  588. struct notifier_block vmap_notifier;
  589. struct shrinker shrinker;
  590. struct drm_atomic_state *pm_state;
  591. /* task holding struct_mutex.. currently only used in submit path
  592. * to detect and reject faults from copy_from_user() for submit
  593. * ioctl.
  594. */
  595. struct task_struct *struct_mutex_task;
  596. /* list of clients waiting for events */
  597. struct list_head client_event_list;
  598. /* whether registered and drm_dev_unregister should be called */
  599. bool registered;
  600. /* msm drv debug root node */
  601. struct dentry *debug_root;
  602. /* update the flag when msm driver receives shutdown notification */
  603. bool shutdown_in_progress;
  604. };
  605. /* get struct msm_kms * from drm_device * */
  606. #define ddev_to_msm_kms(D) ((D) && (D)->dev_private ? \
  607. ((struct msm_drm_private *)((D)->dev_private))->kms : NULL)
  608. struct msm_format {
  609. uint32_t pixel_format;
  610. };
  611. int msm_atomic_prepare_fb(struct drm_plane *plane,
  612. struct drm_plane_state *new_state);
  613. void msm_atomic_commit_tail(struct drm_atomic_state *state);
  614. int msm_atomic_commit(struct drm_device *dev,
  615. struct drm_atomic_state *state, bool nonblock);
  616. /* callback from wq once fence has passed: */
  617. struct msm_fence_cb {
  618. struct work_struct work;
  619. uint32_t fence;
  620. void (*func)(struct msm_fence_cb *cb);
  621. };
  622. void __msm_fence_worker(struct work_struct *work);
  623. #define INIT_FENCE_CB(_cb, _func) do { \
  624. INIT_WORK(&(_cb)->work, __msm_fence_worker); \
  625. (_cb)->func = _func; \
  626. } while (0)
  627. struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
  628. void msm_atomic_state_clear(struct drm_atomic_state *state);
  629. void msm_atomic_state_free(struct drm_atomic_state *state);
  630. void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
  631. struct msm_gem_vma *vma, struct sg_table *sgt,
  632. unsigned int flags);
  633. int msm_gem_map_vma(struct msm_gem_address_space *aspace,
  634. struct msm_gem_vma *vma, struct sg_table *sgt, int npages,
  635. unsigned int flags);
  636. struct device *msm_gem_get_aspace_device(struct msm_gem_address_space *aspace);
  637. void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
  638. struct msm_gem_address_space *
  639. msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
  640. const char *name);
  641. /* For SDE display */
  642. struct msm_gem_address_space *
  643. msm_gem_smmu_address_space_create(struct drm_device *dev, struct msm_mmu *mmu,
  644. const char *name);
  645. /**
  646. * msm_gem_add_obj_to_aspace_active_list: adds obj to active obj list in aspace
  647. */
  648. void msm_gem_add_obj_to_aspace_active_list(
  649. struct msm_gem_address_space *aspace,
  650. struct drm_gem_object *obj);
  651. /**
  652. * msm_gem_remove_obj_from_aspace_active_list: removes obj from active obj
  653. * list in aspace
  654. */
  655. void msm_gem_remove_obj_from_aspace_active_list(
  656. struct msm_gem_address_space *aspace,
  657. struct drm_gem_object *obj);
  658. /**
  659. * msm_gem_smmu_address_space_get: returns the aspace pointer for the requested
  660. * domain
  661. */
  662. struct msm_gem_address_space *
  663. msm_gem_smmu_address_space_get(struct drm_device *dev,
  664. unsigned int domain);
  665. int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
  666. void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
  667. /**
  668. * msm_gem_aspace_domain_attach_detach: function to inform the attach/detach
  669. * of the domain for this aspace
  670. */
  671. void msm_gem_aspace_domain_attach_detach_update(
  672. struct msm_gem_address_space *aspace,
  673. bool is_detach);
  674. /**
  675. * msm_gem_address_space_register_cb: function to register callback for attach
  676. * and detach of the domain
  677. */
  678. int msm_gem_address_space_register_cb(
  679. struct msm_gem_address_space *aspace,
  680. void (*cb)(void *, bool),
  681. void *cb_data);
  682. /**
  683. * msm_gem_address_space_register_cb: function to unregister callback
  684. */
  685. int msm_gem_address_space_unregister_cb(
  686. struct msm_gem_address_space *aspace,
  687. void (*cb)(void *, bool),
  688. void *cb_data);
  689. void msm_gem_submit_free(struct msm_gem_submit *submit);
  690. int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
  691. struct drm_file *file);
  692. void msm_gem_shrinker_init(struct drm_device *dev);
  693. void msm_gem_shrinker_cleanup(struct drm_device *dev);
  694. void msm_gem_sync(struct drm_gem_object *obj);
  695. int msm_gem_mmap_obj(struct drm_gem_object *obj,
  696. struct vm_area_struct *vma);
  697. int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
  698. vm_fault_t msm_gem_fault(struct vm_fault *vmf);
  699. uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
  700. int msm_gem_get_iova(struct drm_gem_object *obj,
  701. struct msm_gem_address_space *aspace, uint64_t *iova);
  702. uint64_t msm_gem_iova(struct drm_gem_object *obj,
  703. struct msm_gem_address_space *aspace);
  704. struct page **msm_gem_get_pages(struct drm_gem_object *obj);
  705. void msm_gem_put_pages(struct drm_gem_object *obj);
  706. void msm_gem_put_iova(struct drm_gem_object *obj,
  707. struct msm_gem_address_space *aspace);
  708. dma_addr_t msm_gem_get_dma_addr(struct drm_gem_object *obj);
  709. int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
  710. struct drm_mode_create_dumb *args);
  711. int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
  712. uint32_t handle, uint64_t *offset);
  713. struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
  714. void *msm_gem_prime_vmap(struct drm_gem_object *obj);
  715. void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
  716. int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
  717. struct reservation_object *msm_gem_prime_res_obj(struct drm_gem_object *obj);
  718. struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
  719. struct dma_buf_attachment *attach, struct sg_table *sg);
  720. int msm_gem_prime_pin(struct drm_gem_object *obj);
  721. void msm_gem_prime_unpin(struct drm_gem_object *obj);
  722. struct drm_gem_object *msm_gem_prime_import(struct drm_device *dev,
  723. struct dma_buf *dma_buf);
  724. void *msm_gem_get_vaddr(struct drm_gem_object *obj);
  725. void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
  726. void msm_gem_put_vaddr(struct drm_gem_object *obj);
  727. int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
  728. int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
  729. int msm_gem_cpu_fini(struct drm_gem_object *obj);
  730. void msm_gem_free_object(struct drm_gem_object *obj);
  731. int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
  732. uint32_t size, uint32_t flags, uint32_t *handle);
  733. struct drm_gem_object *msm_gem_new(struct drm_device *dev,
  734. uint32_t size, uint32_t flags);
  735. struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
  736. uint32_t size, uint32_t flags);
  737. void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
  738. uint32_t flags, struct msm_gem_address_space *aspace,
  739. struct drm_gem_object **bo, uint64_t *iova);
  740. void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
  741. uint32_t flags, struct msm_gem_address_space *aspace,
  742. struct drm_gem_object **bo, uint64_t *iova);
  743. struct drm_gem_object *msm_gem_import(struct drm_device *dev,
  744. struct dma_buf *dmabuf, struct sg_table *sgt);
  745. int msm_gem_delayed_import(struct drm_gem_object *obj);
  746. void msm_framebuffer_set_kmap(struct drm_framebuffer *fb, bool enable);
  747. void msm_framebuffer_set_keepattrs(struct drm_framebuffer *fb, bool enable);
  748. int msm_framebuffer_prepare(struct drm_framebuffer *fb,
  749. struct msm_gem_address_space *aspace);
  750. void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
  751. struct msm_gem_address_space *aspace);
  752. uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
  753. struct msm_gem_address_space *aspace, int plane);
  754. uint32_t msm_framebuffer_phys(struct drm_framebuffer *fb, int plane);
  755. struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
  756. const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
  757. struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
  758. const struct drm_mode_fb_cmd2 *mode_cmd,
  759. struct drm_gem_object **bos);
  760. struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
  761. struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
  762. struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
  763. int w, int h, int p, uint32_t format);
  764. struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
  765. void msm_fbdev_free(struct drm_device *dev);
  766. struct hdmi;
  767. #ifdef CONFIG_DRM_MSM_HDMI
  768. int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
  769. struct drm_encoder *encoder);
  770. void __init msm_hdmi_register(void);
  771. void __exit msm_hdmi_unregister(void);
  772. #else
  773. static inline void __init msm_hdmi_register(void)
  774. {
  775. }
  776. static inline void __exit msm_hdmi_unregister(void)
  777. {
  778. }
  779. #endif
  780. struct msm_edp;
  781. #ifdef CONFIG_DRM_MSM_EDP
  782. void __init msm_edp_register(void);
  783. void __exit msm_edp_unregister(void);
  784. int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
  785. struct drm_encoder *encoder);
  786. #else
  787. static inline void __init msm_edp_register(void)
  788. {
  789. }
  790. static inline void __exit msm_edp_unregister(void)
  791. {
  792. }
  793. static inline int msm_edp_modeset_init(struct msm_edp *edp,
  794. struct drm_device *dev, struct drm_encoder *encoder)
  795. {
  796. return -EINVAL;
  797. }
  798. #endif
  799. struct msm_dsi;
  800. /* *
  801. * msm_mode_object_event_notify - notify user-space clients of drm object
  802. * events.
  803. * @obj: mode object (crtc/connector) that is generating the event.
  804. * @event: event that needs to be notified.
  805. * @payload: payload for the event.
  806. */
  807. void msm_mode_object_event_notify(struct drm_mode_object *obj,
  808. struct drm_device *dev, struct drm_event *event, u8 *payload);
  809. #ifndef CONFIG_DRM_MSM_DSI
  810. void __init msm_dsi_register(void);
  811. void __exit msm_dsi_unregister(void);
  812. int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
  813. struct drm_encoder *encoder);
  814. #else
  815. static inline void __init msm_dsi_register(void)
  816. {
  817. }
  818. static inline void __exit msm_dsi_unregister(void)
  819. {
  820. }
  821. static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
  822. struct drm_device *dev,
  823. struct drm_encoder *encoder)
  824. {
  825. return -EINVAL;
  826. }
  827. #endif
  828. #ifdef CONFIG_DRM_MSM_MDP5
  829. void __init msm_mdp_register(void);
  830. void __exit msm_mdp_unregister(void);
  831. #else
  832. static inline void __init msm_mdp_register(void)
  833. {
  834. }
  835. static inline void __exit msm_mdp_unregister(void)
  836. {
  837. }
  838. #endif
  839. #ifdef CONFIG_DEBUG_FS
  840. void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
  841. void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
  842. void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
  843. int msm_debugfs_late_init(struct drm_device *dev);
  844. int msm_rd_debugfs_init(struct drm_minor *minor);
  845. void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
  846. void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
  847. const char *fmt, ...);
  848. int msm_perf_debugfs_init(struct drm_minor *minor);
  849. void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
  850. #else
  851. static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
  852. static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
  853. const char *fmt, ...) {}
  854. static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
  855. static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
  856. #endif
  857. struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
  858. int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk);
  859. struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
  860. const char *name);
  861. void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
  862. const char *dbgname);
  863. unsigned long msm_iomap_size(struct platform_device *pdev, const char *name);
  864. void msm_iounmap(struct platform_device *dev, void __iomem *addr);
  865. void msm_writel(u32 data, void __iomem *addr);
  866. u32 msm_readl(const void __iomem *addr);
  867. #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
  868. #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
  869. static inline int align_pitch(int width, int bpp)
  870. {
  871. int bytespp = (bpp + 7) / 8;
  872. /* adreno needs pitch aligned to 32 pixels: */
  873. return bytespp * ALIGN(width, 32);
  874. }
  875. /* for the generated headers: */
  876. #define INVALID_IDX(idx) ({BUG(); 0;})
  877. #define fui(x) ({BUG(); 0;})
  878. #define util_float_to_half(x) ({BUG(); 0;})
  879. #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
  880. /* for conditionally setting boolean flag(s): */
  881. #define COND(bool, val) ((bool) ? (val) : 0)
  882. static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
  883. {
  884. ktime_t now = ktime_get();
  885. unsigned long remaining_jiffies;
  886. if (ktime_compare(*timeout, now) < 0) {
  887. remaining_jiffies = 0;
  888. } else {
  889. ktime_t rem = ktime_sub(*timeout, now);
  890. struct timespec ts = ktime_to_timespec(rem);
  891. remaining_jiffies = timespec_to_jiffies(&ts);
  892. }
  893. return remaining_jiffies;
  894. }
  895. #endif /* __MSM_DRV_H__ */